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| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-08-21 22:32:28 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-08-21 22:32:28 -0700 |
| commit | 94c4cad90f76ee3d6427baf22c3ec8361c930aa5 (patch) | |
| tree | 2fb3d274891d6be75fb3cfea36ca6fec01ae092a /include | |
| parent | 7fd9f7569bc89388c6f68aafd3971d08c0cee2f6 (diff) | |
| parent | 6e6798994dc49b9f20ee25ec9e6c92b04727ec3e (diff) | |
| download | history-94c4cad90f76ee3d6427baf22c3ec8361c930aa5.tar.gz | |
Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk
into ppc970.osdl.org:/home/torvalds/v2.6/linux
Diffstat (limited to 'include')
55 files changed, 2352 insertions, 1004 deletions
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h new file mode 100644 index 00000000000000..dbdc017804131f --- /dev/null +++ b/include/asm-arm/arch-imx/dma.h @@ -0,0 +1,71 @@ +/* + * linux/include/asm-arm/imxads/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#define MAX_DMA_CHANNELS 0 + +/* + * DMA registration + */ + +typedef enum { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 3, + DMA_PRIO_LOW = 6 +} imx_dma_prio; + +int imx_request_dma(char *name, imx_dma_prio prio, + void (*irq_handler) (int, void *, struct pt_regs *), + void (*err_handler) (int, void *, struct pt_regs *), + void *data); + +void imx_free_dma(int dma_ch); + + +#define DMA_REQ_UART3_T 2 +#define DMA_REQ_UART3_R 3 +#define DMA_REQ_SSI2_T 4 +#define DMA_REQ_SSI2_R 5 +#define DMA_REQ_CSI_STAT 6 +#define DMA_REQ_CSI_R 7 +#define DMA_REQ_MSHC 8 +#define DMA_REQ_DSPA_DCT_DOUT 9 +#define DMA_REQ_DSPA_DCT_DIN 10 +#define DMA_REQ_DSPA_MAC 11 +#define DMA_REQ_EXT 12 +#define DMA_REQ_SDHC 13 +#define DMA_REQ_SPI1_R 14 +#define DMA_REQ_SPI1_T 15 +#define DMA_REQ_SSI_T 16 +#define DMA_REQ_SSI_R 17 +#define DMA_REQ_ASP_DAC 18 +#define DMA_REQ_ASP_ADC 19 +#define DMA_REQ_USP_EP(x) (20+(x)) +#define DMA_REQ_SPI2_R 26 +#define DMA_REQ_SPI2_T 27 +#define DMA_REQ_UART2_T 28 +#define DMA_REQ_UART2_R 29 +#define DMA_REQ_UART1_T 30 +#define DMA_REQ_UART1_R 31 + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h new file mode 100644 index 00000000000000..c5d559fdb62353 --- /dev/null +++ b/include/asm-arm/arch-imx/hardware.h @@ -0,0 +1,101 @@ +/* + * linux/include/asm-arm/arch-imx/hardware.h + * + * Copyright (C) 1999 ARM Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include "imx-regs.h" + +#ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) + +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) +#endif + +/* + * Memory map + */ + +#define IMX_IO_PHYS 0x00200000 +#define IMX_IO_SIZE 0x00100000 +#define IMX_IO_BASE 0xe0000000 + +#define IMX_CS0_PHYS 0x10000000 +#define IMX_CS0_SIZE 0x02000000 +#define IMX_CS0_VIRT 0xe8000000 + +#define IMX_CS1_PHYS 0x12000000 +#define IMX_CS1_SIZE 0x01000000 +#define IMX_CS1_VIRT 0xea000000 + +#define IMX_CS2_PHYS 0x13000000 +#define IMX_CS2_SIZE 0x01000000 +#define IMX_CS2_VIRT 0xeb000000 + +#define IMX_CS3_PHYS 0x14000000 +#define IMX_CS3_SIZE 0x01000000 +#define IMX_CS3_VIRT 0xec000000 + +#define IMX_CS4_PHYS 0x15000000 +#define IMX_CS4_SIZE 0x01000000 +#define IMX_CS4_VIRT 0xed000000 + +#define IMX_CS5_PHYS 0x16000000 +#define IMX_CS5_SIZE 0x01000000 +#define IMX_CS5_VIRT 0xee000000 + +#define IMX_FB_VIRT 0xF1000000 +#define IMX_FB_SIZE (256*1024) + +/* macro to get at IO space when running virtually */ +#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) + +#ifndef __ASSEMBLY__ +/* + * Handy routine to set GPIO functions + */ +extern void imx_gpio_mode( int gpio_mode ); + +/* get frequencies in Hz */ +extern unsigned int imx_get_system_clk(void); +extern unsigned int imx_get_mcu_clk(void); +extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */ +extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */ +extern unsigned int imx_get_perclk3(void); /* SSI */ +extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/ + /* I2C, DMA */ +#endif + +#define MAXIRQNUM 62 +#define MAXFIQNUM 62 +#define MAXSWINUM 62 + +/* + * Use SDRAM for memory + */ +#define MEM_SIZE 0x01000000 + +#ifdef CONFIG_ARCH_MX1ADS +#include "mx1ads.h" +#endif + +#endif diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h new file mode 100644 index 00000000000000..f32c203952cf76 --- /dev/null +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -0,0 +1,548 @@ +#ifndef _IMX_REGS_H +#define _IMX_REGS_H +/* ------------------------------------------------------------------------ + * Motorola IMX system registers + * ------------------------------------------------------------------------ + * + */ + +/* + * Register BASEs, based on OFFSETs + * + */ +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) +#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) +#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) +#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) +#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) +#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) +#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) +#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) +#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) +#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) +#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) +#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) +#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) +#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) +#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) +#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) +#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) +#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) +#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ +#define CSCR_SYSTEM_SEL (1<<16) + +#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ + +#define CSCR_MPLL_RESTART (1<<21) + +/* + * GPIO Module and I/O Multiplexer + * x = 0..3 for reg_A, reg_B, reg_C, reg_D + */ +#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) +#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) +#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) +#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) +#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) +#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) +#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) +#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) +#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) +#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) +#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) +#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) +#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) +#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) +#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) +#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) +#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) + +#define GPIO_PIN_MASK 0x1f +#define GPIO_PORT_MASK (0x3 << 5) + +#define GPIO_PORTA (0<<5) +#define GPIO_PORTB (1<<5) +#define GPIO_PORTC (2<<5) +#define GPIO_PORTD (3<<5) + +#define GPIO_OUT (1<<7) +#define GPIO_IN (0<<7) +#define GPIO_PUEN (1<<8) + +#define GPIO_PF (0<<9) +#define GPIO_AF (1<<9) + +#define GPIO_OCR_MASK (3<<10) +#define GPIO_AIN (0<<10) +#define GPIO_BIN (1<<10) +#define GPIO_CIN (2<<10) +#define GPIO_GPIO (3<<10) + +#define GPIO_AOUT (1<<12) +#define GPIO_BOUT (1<<13) + +/* assignements for GPIO alternate/primary functions */ + +/* FIXME: This list is not completed. The correct directions are + * missing on some (many) pins + */ +#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) +#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) +#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) +#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) +#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) +#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) +#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) +#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) +#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) +#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) +#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) +#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) +#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) +#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) +#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) +#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) +#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) +#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) +#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) +#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) +#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) +#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) +#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) +#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) +#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) +#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) +#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) +#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) +#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) +#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) +#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) +#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) +#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) +#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) +#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) +#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) +#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) +#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) +#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) +#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) +#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) +#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) +#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) +#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) +#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) +#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) +#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) +#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) +#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) +#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) +#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) +#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) +#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) +#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) +#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) +#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) +#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) +#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) +#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) +#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) +#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) +#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) +#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) +#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) +#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) +#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) +#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) +#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) +#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) +#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) +#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) +#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) +#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) +#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) +#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) +#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) +#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) +#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) +#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) +#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) +#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) +#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) +#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) +#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) +#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) +#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) +#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) +#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) +#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) +#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) +#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) +#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) +#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) +#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) +#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) +#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) +#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) +#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) +#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) +#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) +#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) +#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) +#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) +#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) +#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) + +/* + * DMA Controller + */ +#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ +#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ +#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ +#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ +#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ +#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ +#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ +#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ +#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ +#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ +#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ +#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ +#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ +#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ +#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ +#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ +#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ +#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ +#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ +#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ +#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ +#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ + +#define DCR_DRST (1<<1) +#define DCR_DEN (1<<0) +#define DBTOCR_EN (1<<15) +#define DBTOCR_CNT(x) ((x) & 0x7fff ) +#define CNTR_CNT(x) ((x) & 0xffffff ) +#define CCR_DMOD_LINEAR ( 0x0 << 12 ) +#define CCR_DMOD_2D ( 0x1 << 12 ) +#define CCR_DMOD_FIFO ( 0x2 << 12 ) +#define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) +#define CCR_SMOD_LINEAR ( 0x0 << 10 ) +#define CCR_SMOD_2D ( 0x1 << 10 ) +#define CCR_SMOD_FIFO ( 0x2 << 10 ) +#define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) +#define CCR_MDIR_DEC (1<<9) +#define CCR_MSEL_B (1<<8) +#define CCR_DSIZ_32 ( 0x0 << 6 ) +#define CCR_DSIZ_8 ( 0x1 << 6 ) +#define CCR_DSIZ_16 ( 0x2 << 6 ) +#define CCR_SSIZ_32 ( 0x0 << 4 ) +#define CCR_SSIZ_8 ( 0x1 << 4 ) +#define CCR_SSIZ_16 ( 0x2 << 4 ) +#define CCR_REN (1<<3) +#define CCR_RPT (1<<2) +#define CCR_FRC (1<<1) +#define CCR_CEN (1<<0) +#define RTOR_EN (1<<15) +#define RTOR_CLK (1<<14) +#define RTOR_PSC (1<<13) + +/* + * Interrupt controller + */ + +#define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00) +#define INTCNTL_FIAD (1<<19) +#define INTCNTL_NIAD (1<<20) + +#define IMX_NIMASK __REG(IMX_AITC_BASE+0x04) +#define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08) +#define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c) +#define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10) +#define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14) + +/* + * General purpose timers + */ +#define IMX_TCTL(x) __REG( 0x00 + (x)) +#define TCTL_SWR (1<<15) +#define TCTL_FRR (1<<8) +#define TCTL_CAP_RIS (1<<6) +#define TCTL_CAP_FAL (2<<6) +#define TCTL_CAP_RIS_FAL (3<<6) +#define TCTL_OM (1<<5) +#define TCTL_IRQEN (1<<4) +#define TCTL_CLK_PCLK1 (1<<1) +#define TCTL_CLK_PCLK1_16 (2<<1) +#define TCTL_CLK_TIN (3<<1) +#define TCTL_CLK_32 (4<<1) +#define TCTL_TEN (1<<0) + +#define IMX_TPRER(x) __REG( 0x04 + (x)) +#define IMX_TCMP(x) __REG( 0x08 + (x)) +#define IMX_TCR(x) __REG( 0x0C + (x)) +#define IMX_TCN(x) __REG( 0x10 + (x)) +#define IMX_TSTAT(x) __REG( 0x14 + (x)) +#define TSTAT_CAPT (1<<1) +#define TSTAT_COMP (1<<0) + +/* + * LCD Controller + */ + +#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) + +#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) +#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) +#define SIZE_YMAX(y) ( (y) & 0x1ff ) + +#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) +#define VPW_VPW(x) ( (x) & 0x3ff ) + +#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) +#define CPOS_CC1 (1<<31) +#define CPOS_CC0 (1<<30) +#define CPOS_OP (1<<28) +#define CPOS_CXP(x) (((x) & 3ff) << 16) +#define CPOS_CYP(y) ((y) & 0x1ff) + +#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) +#define LCWHB_BK_EN (1<<31) +#define LCWHB_CW(w) (((w) & 0x1f) << 24) +#define LCWHB_CH(h) (((h) & 0x1f) << 16) +#define LCWHB_BD(x) ((x) & 0xff) + +#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) +#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) +#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) +#define LCHCC_CUR_COL_B(b) ((b) & 0x1f) + +#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) +#define PCR_TFT (1<<31) +#define PCR_COLOR (1<<30) +#define PCR_PBSIZ_1 (0<<28) +#define PCR_PBSIZ_2 (1<<28) +#define PCR_PBSIZ_4 (2<<28) +#define PCR_PBSIZ_8 (3<<28) +#define PCR_BPIX_1 (0<<25) +#define PCR_BPIX_2 (1<<25) +#define PCR_BPIX_4 (2<<25) +#define PCR_BPIX_8 (3<<25) +#define PCR_BPIX_12 (4<<25) +#define PCR_BPIX_16 (4<<25) +#define PCR_PIXPOL (1<<24) +#define PCR_FLMPOL (1<<23) +#define PCR_LPPOL (1<<22) +#define PCR_CLKPOL (1<<21) +#define PCR_OEPOL (1<<20) +#define PCR_SCLKIDLE (1<<19) +#define PCR_END_SEL (1<<18) +#define PCR_END_BYTE_SWAP (1<<17) +#define PCR_REV_VS (1<<16) +#define PCR_ACD_SEL (1<<15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1<<7) +#define PCR_SHARP (1<<6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) +#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) +#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) +#define HCR_H_WAIT_2(x) ((x) & 0xff) + +#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) +#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) +#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) +#define VCR_V_WAIT_2(x) ((x) & 0xff) + +#define LCDC_POS __REG(IMX_LCDC_BASE+0x24) +#define POS_POS(x) ((x) & 1f) + +#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) + +#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1<<15) +#define PWMR_SCR1 (1<<10) +#define PWMR_SCR0 (1<<9) +#define PWMR_CC_EN (1<<8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) +#define DMACR_BURST (1<<31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) &0xf) + +#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) +#define RMCR_LCDC_EN (1<<1) +#define RMCR_SELF_REF (1<<0) + +#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) +#define LCDICR_INT_SYN (1<<2) +#define LCDICR_INT_CON (1) + +#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) +#define LCDISR_UDR_ERR (1<<3) +#define LCDISR_ERR_RES (1<<2) +#define LCDISR_EOF (1<<1) +#define LCDISR_BOF (1<<0) + +/* + * UART Module. Takes the UART base address as argument + */ +#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */ +#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */ +#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */ +#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */ +#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */ +#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */ +#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */ +#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */ +#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */ +#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */ +#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */ +#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */ +#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */ +#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */ +#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */ +#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */ +#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */ +#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */ +#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */ +#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */ +#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */ +#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */ +#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +#endif // _IMX_REGS_H diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h new file mode 100644 index 00000000000000..6c8789fdacd250 --- /dev/null +++ b/include/asm-arm/arch-imx/io.h @@ -0,0 +1,28 @@ +/* + * linux/include/asm-arm/arch-imxads/io.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) (a) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-imx/irq.h b/include/asm-arm/arch-imx/irq.h new file mode 100644 index 00000000000000..545e065d232535 --- /dev/null +++ b/include/asm-arm/arch-imx/irq.h @@ -0,0 +1,20 @@ +/* + * linux/include/asm-arm/arch-imxads/irq.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define fixup_irq(i) (i) diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h new file mode 100644 index 00000000000000..238197cfb9d964 --- /dev/null +++ b/include/asm-arm/arch-imx/irqs.h @@ -0,0 +1,116 @@ +/* + * linux/include/asm-arm/arch-imxads/irqs.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARM_IRQS_H__ +#define __ARM_IRQS_H__ + +/* Use the imx definitions */ +#include <asm/arch/hardware.h> + +/* + * IMX Interrupt numbers + * + */ +#define INT_SOFTINT 0 +#define CSI_INT 6 +#define DSPA_MAC_INT 7 +#define DSPA_INT 8 +#define COMP_INT 9 +#define MSHC_XINT 10 +#define GPIO_INT_PORTA 11 +#define GPIO_INT_PORTB 12 +#define GPIO_INT_PORTC 13 +#define LCDC_INT 14 +#define SIM_INT 15 +#define SIM_DATA_INT 16 +#define RTC_INT 17 +#define RTC_SAMINT 18 +#define UART2_MINT_PFERR 19 +#define UART2_MINT_RTS 20 +#define UART2_MINT_DTR 21 +#define UART2_MINT_UARTC 22 +#define UART2_MINT_TX 23 +#define UART2_MINT_RX 24 +#define UART1_MINT_PFERR 25 +#define UART1_MINT_RTS 26 +#define UART1_MINT_DTR 27 +#define UART1_MINT_UARTC 28 +#define UART1_MINT_TX 29 +#define UART1_MINT_RX 30 +#define VOICE_DAC_INT 31 +#define VOICE_ADC_INT 32 +#define PEN_DATA_INT 33 +#define PWM_INT 34 +#define SDHC_INT 35 +#define I2C_INT 39 +#define CSPI_INT 41 +#define SSI_TX_INT 42 +#define SSI_TX_ERR_INT 43 +#define SSI_RX_INT 44 +#define SSI_RX_ERR_INT 45 +#define TOUCH_INT 46 +#define USBD_INT0 47 +#define USBD_INT1 48 +#define USBD_INT2 49 +#define USBD_INT3 50 +#define USBD_INT4 51 +#define USBD_INT5 52 +#define USBD_INT6 53 +#define BTSYS_INT 55 +#define BTTIM_INT 56 +#define BTWUI_INT 57 +#define TIM2_INT 58 +#define TIM1_INT 59 +#define DMA_ERR 60 +#define DMA_INT 61 +#define GPIO_INT_PORTD 62 + +#define IMX_IRQS (64) + +/* note: the IMX has four gpio ports (A-D), but only + * the following pins are connected to the outside + * world: + * + * PORT A: bits 0-31 + * PORT B: bits 8-31 + * PORT C: bits 3-17 + * PORT D: bits 6-31 + * + * We map these interrupts straight on. As a result we have + * several holes in the interrupt mapping. We do this for two + * reasons: + * - mapping the interrupts without holes would get + * far more complicated + * - Motorola could well decide to bring some processor + * with more pins connected + */ + +#define IRQ_GPIOA(x) (IMX_IRQS + x) +#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) +#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) +#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) + +/* decode irq number to use with IMR(x), ISR(x) and friends */ +#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5) + +#define NR_IRQS (IRQ_GPIOD(32) + 1) +#define IRQ_GPIO(x) +#endif diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h new file mode 100644 index 00000000000000..116a91fa14f19a --- /dev/null +++ b/include/asm-arm/arch-imx/memory.h @@ -0,0 +1,38 @@ +/* + * linux/include/asm-arm/arch-imx/memory.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_MMU_H +#define __ASM_ARCH_MMU_H + +#define PHYS_OFFSET (0x08000000UL) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus__is_a_macro +#define __virt_to_bus(x) (x - PAGE_OFFSET + PHYS_OFFSET) +#define __bus_to_virt__is_a_macro +#define __bus_to_virt(x) (x - PHYS_OFFSET + PAGE_OFFSET) + +#endif diff --git a/include/asm-arm/arch-imx/mx1ads.h b/include/asm-arm/arch-imx/mx1ads.h new file mode 100644 index 00000000000000..d90fa4b49ce19e --- /dev/null +++ b/include/asm-arm/arch-imx/mx1ads.h @@ -0,0 +1,36 @@ +/* + * linux/include/asm-arm/arch-imx/mx1ads.h + * + * Copyright (C) 2004 Robert Schwebel, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_MX1ADS_H +#define __ASM_ARCH_MX1ADS_H + +/* ------------------------------------------------------------------------ */ +/* Memory Map for the M9328MX1ADS (MX1ADS) Board */ +/* ------------------------------------------------------------------------ */ + +#define MX1ADS_FLASH_PHYS 0x10000000 +#define MX1ADS_FLASH_SIZE (16*1024*1024) + +#define IMX_FB_PHYS (0x0C000000 - 0x40000) + +#define CLK32 32000 + +#endif /* __ASM_ARCH_MX1ADS_H */ diff --git a/include/asm-arm/arch-imx/param.h b/include/asm-arm/arch-imx/param.h new file mode 100644 index 00000000000000..7c724f03333e1b --- /dev/null +++ b/include/asm-arm/arch-imx/param.h @@ -0,0 +1,19 @@ +/* + * linux/include/asm-arm/arch-imx/param.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-imx/serial.h b/include/asm-arm/arch-imx/serial.h new file mode 100644 index 00000000000000..c885c48a59ab5d --- /dev/null +++ b/include/asm-arm/arch-imx/serial.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-imx/serial.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#define STD_SERIAL_PORT_DEFNS +#define EXTRA_SERIAL_PORT_DEFNS + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-imx/system.h b/include/asm-arm/arch-imx/system.h new file mode 100644 index 00000000000000..c645fe9afb9dc1 --- /dev/null +++ b/include/asm-arm/arch-imx/system.h @@ -0,0 +1,40 @@ +/* + * linux/include/asm-arm/arch-imxads/system.h + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 Deep Blue Solutions Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static void +arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void +arch_reset(char mode) +{ + cpu_reset(0); +} + +#endif diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h new file mode 100644 index 00000000000000..d65ab3cd5d5d2d --- /dev/null +++ b/include/asm-arm/arch-imx/timex.h @@ -0,0 +1,27 @@ +/* + * linux/include/asm-arm/imx/timex.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +#include <asm/arch/hardware.h> +#define CLOCK_TICK_RATE (CLK32) + +#endif diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h new file mode 100644 index 00000000000000..c79ac10b89e1e4 --- /dev/null +++ b/include/asm-arm/arch-imx/uncompress.h @@ -0,0 +1,78 @@ +/* + * linux/include/asm-arm/arch-imxads/uncompress.h + * + * + * + * Copyright (C) 1999 ARM Limited + * Copyright (C) Shane Nay (shane@minirl.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) + +#define UART1_BASE 0x206000 +#define UART2_BASE 0x207000 +#define USR2 0x98 +#define USR2_TXFE (1<<14) +#define TXR 0x40 +#define UCR1 0x80 +#define UCR1_UARTEN 1 + +/* + * The following code assumes the serial port has already been + * initialized by the bootloader. We search for the first enabled + * port in the most probable order. If you didn't setup a port in + * your bootloader then nothing will appear (which might be desired). + * + * This does not append a newline + */ +static void +puts(const char *s) +{ + unsigned long serial_port; + + do { + serial_port = UART1_BASE; + if ( UART(UCR1) & UCR1_UARTEN ) + break; + serial_port = UART2_BASE; + if ( UART(UCR1) & UCR1_UARTEN ) + break; + return; + } while(0); + + while (*s) { + while ( !(UART(USR2) & USR2_TXFE) ) + barrier(); + + UART(TXR) = *s; + + if (*s == '\n') { + while ( !(UART(USR2) & USR2_TXFE) ) + barrier(); + + UART(TXR) = '\r'; + } + s++; + } +} + +/* + * nothing to do + */ +#define arch_decomp_setup() + +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h new file mode 100644 index 00000000000000..252038f48163c1 --- /dev/null +++ b/include/asm-arm/arch-imx/vmalloc.h @@ -0,0 +1,32 @@ +/* + * linux/include/asm-arm/arch-imx/vmalloc.h + * + * Copyright (C) 2000 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_VMADDR(x) ((unsigned long)(x)) +#define VMALLOC_END (PAGE_OFFSET + 0x10000000) diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h index 45e157101977ca..dd73587e34b992 100644 --- a/include/asm-arm/arch-iop3xx/dma.h +++ b/include/asm-arm/arch-iop3xx/dma.h @@ -1,20 +1,25 @@ /* - * linux/include/asm-arm/arch-iop80310/dma.h + * linux/include/asm-arm/arch-iop3xx/dma.h * - * Copyright (C) 2001 MontaVista Software, Inc. + * Copyright (C) 2004 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef _IOP310_DMA_H_ -#define _IOP310_DMA_H_ +#ifndef _IOP3XX_DMA_H_P +#define _IOP3XX_DMA_H_P -/* 2 DMA on primary PCI and 1 on secondary for 80310 */ -#define MAX_IOP310_DMA_CHANNEL 3 +/* 80310 not supported */ +#define MAX_IOP3XX_DMA_CHANNEL 2 #define MAX_DMA_DESC 64 /*128 */ +#define DMA_FREE 0x0 +#define DMA_ACTIVE 0x1 +#define DMA_COMPLETE 0x2 +#define DMA_ERROR 0x4 + /* * Make the generic DMA bits go away since we don't use it */ @@ -22,27 +27,10 @@ #define MAX_DMA_ADDRESS 0xffffffff -#define IOP310_DMA_P0 0 -#define IOP310_DMA_P1 1 -#define IOP310_DMA_S0 2 - -#define DMA_MOD_READ 0x0001 -#define DMA_MOD_WRITE 0x0002 -#define DMA_MOD_CACHED 0x0004 -#define DMA_MOD_NONCACHED 0x0008 - - -#define DMA_DESC_DONE 0x0010 -#define DMA_INCOMPLETE 0x0020 -#define DMA_HOLD 0x0040 -#define DMA_END_CHAIN 0x0080 -#define DMA_COMPLETE 0x0100 -#define DMA_NOTIFY 0x0200 -#define DMA_NEW_HEAD 0x0400 - -#define DMA_USER_MASK (DMA_NOTIFY | DMA_INCOMPLETE | \ - DMA_HOLD | DMA_COMPLETE) +#define DMA_POLL 0x0 +#define DMA_INTERRUPT 0x1 +#define DMA_DCR_MTM 0x00000040 /* memory to memory transfer */ #define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */ #define DMA_DCR_IE 0x00000010 /* Interrupt Enable */ #define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */ @@ -55,55 +43,12 @@ #define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */ #define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */ -#define DMA_USER_CMD_IE 0x00000001 /* user request int */ -#define DMA_USER_END_CHAIN 0x00000002 /* end of sgl chain flag */ - -/* ATU defines */ -#define IOP310_ATUCR_PRIM_OUT_ENAB /* Configuration */ 0x00000002 -#define IOP310_ATUCR_DIR_ADDR_ENAB /* Configuration */ 0x00000080 - - -typedef void (*dma_callback_t) (void *buf_context); -/* - * DMA Descriptor - */ -typedef struct _dma_desc -{ - u32 NDAR; /* next descriptor address */ - u32 PDAR; /* PCI address */ - u32 PUADR; /* upper PCI address */ - u32 LADR; /* local address */ - u32 BC; /* byte count */ - u32 DC; /* descriptor control */ -} dma_desc_t; - -typedef struct _dma_sgl -{ - dma_desc_t dma_desc; /* DMA descriptor pointer */ - u32 status; /* descriptor status */ - void *data; /* local virt */ - struct _dma_sgl *next; /* next descriptor */ -} dma_sgl_t; - -/* dma sgl head */ -typedef struct _dma_head -{ - u32 total; /* total elements in SGL */ - u32 status; /* status of sgl */ - u32 mode; /* read or write mode */ - dma_sgl_t *list; /* pointer to list */ - dma_callback_t callback; /* callback function */ -} dma_head_t; +//extern iop3xx_dma_t dma_chan[2]; /* function prototypes */ -int dma_request(dmach_t, const char *); -int dma_queue_buffer(dmach_t, dma_head_t *); -int dma_suspend(dmach_t); -int dma_resume(dmach_t); -int dma_flush_all(dmach_t); -void dma_free(dmach_t); -void dma_set_irq_threshold(dmach_t, int); -dma_sgl_t *dma_get_buffer(dmach_t, int); -void dma_return_buffer(dmach_t, dma_sgl_t *); +#ifdef CONFIG_IOP3XX_DMACOPY +extern int iop_memcpy; +void * dma_memcpy(void * to, const void* from, __kernel_size_t n); +#endif -#endif /* _ASM_ARCH_DMA_H */ +#endif /* _ASM_ARCH_DMA_H_P */ diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h index 03338ca25a9e3a..b17559e19fd2a4 100644 --- a/include/asm-arm/arch-iop3xx/hardware.h +++ b/include/asm-arm/arch-iop3xx/hardware.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-iop80310/hardware.h + * linux/include/asm-arm/arch-iop3xx/hardware.h */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H @@ -15,28 +15,11 @@ * The PCI IO space is located at virtual 0xfe000000 from physical * 0x90000000. The PCI BARs must be programmed with physical addresses, * but when we read them, we convert them to virtual addresses. See - * arch/arm/mach-iop310/iop310-pci.c + * arch/arm/mach-iop3xx/iop3XX-pci.c */ #define pcibios_assign_all_busses() 1 -#ifdef CONFIG_ARCH_IOP310 -/* - * these are the values for the secondary PCI bus on the 80312 chip. I will - * have to do some fixup in the bus/dev fixup code - */ -#define PCIBIOS_MIN_IO 0 -#define PCIBIOS_MIN_MEM 0x88000000 - -// Generic chipset bits -#include "iop310.h" - -// Board specific -#if defined(CONFIG_ARCH_IQ80310) -#include "iq80310.h" -#endif -#endif - #ifdef CONFIG_ARCH_IOP321 #define PCIBIOS_MIN_IO 0x90000000 diff --git a/include/asm-arm/arch-iop3xx/iop310-irqs.h b/include/asm-arm/arch-iop3xx/iop310-irqs.h deleted file mode 100644 index f468a285832f2c..00000000000000 --- a/include/asm-arm/arch-iop3xx/iop310-irqs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * linux/include/asm-arm/arch-iop310/irqs.h - * - * Author: Nicolas Pitre - * Copyright: (C) 2001 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com> - * - */ -#include <linux/config.h> - -/* - * XS80200 specific IRQs - */ -#define IRQ_XS80200_BCU 0 /* Bus Control Unit */ -#define IRQ_XS80200_PMU 1 /* Performance Monitoring Unit */ -#define IRQ_XS80200_EXTIRQ 2 /* external IRQ signal */ -#define IRQ_XS80200_EXTFIQ 3 /* external IRQ signal */ - -#define NR_XS80200_IRQS 4 - -#define XSCALE_PMU_IRQ IRQ_XS80200_PMU - -/* - * IOP80310 chipset interrupts - */ -#define IOP310_IRQ_OFS NR_XS80200_IRQS -#define IOP310_IRQ(x) (IOP310_IRQ_OFS + (x)) - -/* - * On FIQ1ISR register - */ -#define IRQ_IOP310_DMA0 IOP310_IRQ(0) /* DMA Channel 0 */ -#define IRQ_IOP310_DMA1 IOP310_IRQ(1) /* DMA Channel 1 */ -#define IRQ_IOP310_DMA2 IOP310_IRQ(2) /* DMA Channel 2 */ -#define IRQ_IOP310_PMON IOP310_IRQ(3) /* Bus performance Unit */ -#define IRQ_IOP310_AAU IOP310_IRQ(4) /* Application Accelator Unit */ - -/* - * On FIQ2ISR register - */ -#define IRQ_IOP310_I2C IOP310_IRQ(5) /* I2C unit */ -#define IRQ_IOP310_MU IOP310_IRQ(6) /* messaging unit */ - -#define NR_IOP310_IRQS (IOP310_IRQ(6) + 1) - -#define NR_IRQS NR_IOP310_IRQS - - -/* - * Interrupts available on the Cyclone IQ80310 board - */ -#ifdef CONFIG_ARCH_IQ80310 - -#define IQ80310_IRQ_OFS NR_IOP310_IRQS -#define IQ80310_IRQ(y) ((IQ80310_IRQ_OFS) + (y)) - -#define IRQ_IQ80310_TIMER IQ80310_IRQ(0) /* Timer Interrupt */ -#define IRQ_IQ80310_I82559 IQ80310_IRQ(1) /* I82559 Ethernet Interrupt */ -#define IRQ_IQ80310_UART1 IQ80310_IRQ(2) /* UART1 Interrupt */ -#define IRQ_IQ80310_UART2 IQ80310_IRQ(3) /* UART2 Interrupt */ -#define IRQ_IQ80310_INTD IQ80310_IRQ(4) /* PCI INTD */ - - -/* - * ONLY AVAILABLE ON REV F OR NEWER BOARDS! - */ -#define IRQ_IQ80310_INTA IQ80310_IRQ(5) /* PCI INTA */ -#define IRQ_IQ80310_INTB IQ80310_IRQ(6) /* PCI INTB */ -#define IRQ_IQ80310_INTC IQ80310_IRQ(7) /* PCI INTC */ - -#undef NR_IRQS -#define NR_IRQS (IQ80310_IRQ(7) + 1) - -#endif // CONFIG_ARCH_IQ80310 - diff --git a/include/asm-arm/arch-iop3xx/iop310.h b/include/asm-arm/arch-iop3xx/iop310.h deleted file mode 100644 index a68ac48d2db323..00000000000000 --- a/include/asm-arm/arch-iop3xx/iop310.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * linux/include/asm/arch-iop3xx/iop310.h - * - * Intel IOP310 Companion Chip definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP310_HW_H_ -#define _IOP310_HW_H_ - -/* - * This is needed for mixed drivers that need to work on all - * IOP3xx variants but behave slightly differently on each. - */ -#ifndef __ASSEMBLY__ -#define iop_is_310() ((processor_id & 0xffffe3f0) == 0x69052000) -#endif - -/* - * IOP310 I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP310_PCISEC_LOWER_IO 0x90010000 -#define IOP310_PCISEC_UPPER_IO 0x9001ffff -#define IOP310_PCISEC_LOWER_MEM 0x88000000 -#define IOP310_PCISEC_UPPER_MEM 0x8bffffff - -#define IOP310_PCIPRI_LOWER_IO 0x90000000 -#define IOP310_PCIPRI_UPPER_IO 0x9000ffff -#define IOP310_PCIPRI_LOWER_MEM 0x80000000 -#define IOP310_PCIPRI_UPPER_MEM 0x83ffffff - -#define IOP310_PCI_WINDOW_SIZE 64 * 0x100000 - -/* - * IOP310 chipset registers - */ -#define IOP310_VIRT_MEM_BASE 0xe8001000 /* chip virtual mem address*/ -#define IOP310_PHY_MEM_BASE 0x00001000 /* chip physical memory address */ -#define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg)) - -/* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */ -#define IOP310_VIDR (volatile u16 *)IOP310_REG_ADDR(0x00001000) -#define IOP310_DIDR (volatile u16 *)IOP310_REG_ADDR(0x00001002) -#define IOP310_PCR (volatile u16 *)IOP310_REG_ADDR(0x00001004) -#define IOP310_PSR (volatile u16 *)IOP310_REG_ADDR(0x00001006) -#define IOP310_RIDR (volatile u8 *)IOP310_REG_ADDR(0x00001008) -#define IOP310_CCR (volatile u32 *)IOP310_REG_ADDR(0x00001009) -#define IOP310_CLSR (volatile u8 *)IOP310_REG_ADDR(0x0000100C) -#define IOP310_PLTR (volatile u8 *)IOP310_REG_ADDR(0x0000100D) -#define IOP310_HTR (volatile u8 *)IOP310_REG_ADDR(0x0000100E) -/* Reserved 0x0000100F through 0x00001017 */ -#define IOP310_PBNR (volatile u8 *)IOP310_REG_ADDR(0x00001018) -#define IOP310_SBNR (volatile u8 *)IOP310_REG_ADDR(0x00001019) -#define IOP310_SUBBNR (volatile u8 *)IOP310_REG_ADDR(0x0000101A) -#define IOP310_SLTR (volatile u8 *)IOP310_REG_ADDR(0x0000101B) -#define IOP310_IOBR (volatile u8 *)IOP310_REG_ADDR(0x0000101C) -#define IOP310_IOLR (volatile u8 *)IOP310_REG_ADDR(0x0000101D) -#define IOP310_SSR (volatile u16 *)IOP310_REG_ADDR(0x0000101E) -#define IOP310_MBR (volatile u16 *)IOP310_REG_ADDR(0x00001020) -#define IOP310_MLR (volatile u16 *)IOP310_REG_ADDR(0x00001022) -#define IOP310_PMBR (volatile u16 *)IOP310_REG_ADDR(0x00001024) -#define IOP310_PMLR (volatile u16 *)IOP310_REG_ADDR(0x00001026) -/* Reserved 0x00001028 through 0x00001033 */ -#define IOP310_CAPR (volatile u8 *)IOP310_REG_ADDR(0x00001034) -/* Reserved 0x00001035 through 0x0000103D */ -#define IOP310_BCR (volatile u16 *)IOP310_REG_ADDR(0x0000103E) -#define IOP310_EBCR (volatile u16 *)IOP310_REG_ADDR(0x00001040) -#define IOP310_SISR (volatile u16 *)IOP310_REG_ADDR(0x00001042) -#define IOP310_PBISR (volatile u32 *)IOP310_REG_ADDR(0x00001044) -#define IOP310_SBISR (volatile u32 *)IOP310_REG_ADDR(0x00001048) -#define IOP310_SACR (volatile u32 *)IOP310_REG_ADDR(0x0000104C) -#define IOP310_PIRSR (volatile u32 *)IOP310_REG_ADDR(0x00001050) -#define IOP310_SIOBR (volatile u8 *)IOP310_REG_ADDR(0x00001054) -#define IOP310_SIOLR (volatile u8 *)IOP310_REG_ADDR(0x00001055) -#define IOP310_SCDR (volatile u8 *)IOP310_REG_ADDR(0x00001056) - -#define IOP310_SMBR (volatile u16 *)IOP310_REG_ADDR(0x00001058) -#define IOP310_SMLR (volatile u16 *)IOP310_REG_ADDR(0x0000105A) -#define IOP310_SDER (volatile u16 *)IOP310_REG_ADDR(0x0000105C) -#define IOP310_QCR (volatile u16 *)IOP310_REG_ADDR(0x0000105E) -#define IOP310_CAPID (volatile u8 *)IOP310_REG_ADDR(0x00001068) -#define IOP310_NIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001069) -#define IOP310_PMCR (volatile u16 *)IOP310_REG_ADDR(0x0000106A) -#define IOP310_PMCSR (volatile u16 *)IOP310_REG_ADDR(0x0000106C) -#define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E) -/* Reserved 0x00001064 through 0x000010FFH */ - -/* Performance monitoring unit 0x00001100 through 0x000011FF*/ -#define IOP310_PMONGTMR (volatile u32 *)IOP310_REG_ADDR(0x00001100) -#define IOP310_PMONESR (volatile u32 *)IOP310_REG_ADDR(0x00001104) -#define IOP310_PMONEMISR (volatile u32 *)IOP310_REG_ADDR(0x00001108) -#define IOP310_PMONGTSR (volatile u32 *)IOP310_REG_ADDR(0x00001110) -#define IOP310_PMONPECR1 (volatile u32 *)IOP310_REG_ADDR(0x00001114) -#define IOP310_PMONPECR2 (volatile u32 *)IOP310_REG_ADDR(0x00001118) -#define IOP310_PMONPECR3 (volatile u32 *)IOP310_REG_ADDR(0x0000111C) -#define IOP310_PMONPECR4 (volatile u32 *)IOP310_REG_ADDR(0x00001120) -#define IOP310_PMONPECR5 (volatile u32 *)IOP310_REG_ADDR(0x00001124) -#define IOP310_PMONPECR6 (volatile u32 *)IOP310_REG_ADDR(0x00001128) -#define IOP310_PMONPECR7 (volatile u32 *)IOP310_REG_ADDR(0x0000112C) -#define IOP310_PMONPECR8 (volatile u32 *)IOP310_REG_ADDR(0x00001130) -#define IOP310_PMONPECR9 (volatile u32 *)IOP310_REG_ADDR(0x00001134) -#define IOP310_PMONPECR10 (volatile u32 *)IOP310_REG_ADDR(0x00001138) -#define IOP310_PMONPECR11 (volatile u32 *)IOP310_REG_ADDR(0x0000113C) -#define IOP310_PMONPECR12 (volatile u32 *)IOP310_REG_ADDR(0x00001140) -#define IOP310_PMONPECR13 (volatile u32 *)IOP310_REG_ADDR(0x00001144) -#define IOP310_PMONPECR14 (volatile u32 *)IOP310_REG_ADDR(0x00001148) - -/* Address Translation Unit 0x00001200 through 0x000012FF */ -#define IOP310_ATUVID (volatile u16 *)IOP310_REG_ADDR(0x00001200) -#define IOP310_ATUDID (volatile u16 *)IOP310_REG_ADDR(0x00001202) -#define IOP310_PATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001204) -#define IOP310_PATUSR (volatile u16 *)IOP310_REG_ADDR(0x00001206) -#define IOP310_ATURID (volatile u8 *)IOP310_REG_ADDR(0x00001208) -#define IOP310_ATUCCR (volatile u32 *)IOP310_REG_ADDR(0x00001209) -#define IOP310_ATUCLSR (volatile u8 *)IOP310_REG_ADDR(0x0000120C) -#define IOP310_ATULT (volatile u8 *)IOP310_REG_ADDR(0x0000120D) -#define IOP310_ATUHTR (volatile u8 *)IOP310_REG_ADDR(0x0000120E) - -#define IOP310_PIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001210) -/* Reserved 0x00001214 through 0x0000122B */ -#define IOP310_ASVIR (volatile u16 *)IOP310_REG_ADDR(0x0000122C) -#define IOP310_ASIR (volatile u16 *)IOP310_REG_ADDR(0x0000122E) -#define IOP310_ERBAR (volatile u32 *)IOP310_REG_ADDR(0x00001230) -#define IOP310_ATUCAPPTR (volatile u8 *)IOP310_REG_ADDR(0x00001234) -/* Reserved 0x00001235 through 0x0000123B */ -#define IOP310_ATUILR (volatile u8 *)IOP310_REG_ADDR(0x0000123C) -#define IOP310_ATUIPR (volatile u8 *)IOP310_REG_ADDR(0x0000123D) -#define IOP310_ATUMGNT (volatile u8 *)IOP310_REG_ADDR(0x0000123E) -#define IOP310_ATUMLAT (volatile u8 *)IOP310_REG_ADDR(0x0000123F) -#define IOP310_PIALR (volatile u32 *)IOP310_REG_ADDR(0x00001240) -#define IOP310_PIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001244) -#define IOP310_SIABAR (volatile u32 *)IOP310_REG_ADDR(0x00001248) -#define IOP310_SIALR (volatile u32 *)IOP310_REG_ADDR(0x0000124C) -#define IOP310_SIATVR (volatile u32 *)IOP310_REG_ADDR(0x00001250) -#define IOP310_POMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001254) -/* Reserved 0x00001258 through 0x0000125B */ -#define IOP310_POIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000125C) -#define IOP310_PODWVR (volatile u32 *)IOP310_REG_ADDR(0x00001260) -#define IOP310_POUDR (volatile u32 *)IOP310_REG_ADDR(0x00001264) -#define IOP310_SOMWVR (volatile u32 *)IOP310_REG_ADDR(0x00001268) -#define IOP310_SOIOWVR (volatile u32 *)IOP310_REG_ADDR(0x0000126C) -/* Reserved 0x00001270 through 0x00001273*/ -#define IOP310_ERLR (volatile u32 *)IOP310_REG_ADDR(0x00001274) -#define IOP310_ERTVR (volatile u32 *)IOP310_REG_ADDR(0x00001278) -/* Reserved 0x00001279 through 0x0000127C*/ -#define IOP310_ATUCAPID (volatile u8 *)IOP310_REG_ADDR(0x00001280) -#define IOP310_ATUNIPTR (volatile u8 *)IOP310_REG_ADDR(0x00001281) -#define IOP310_APMCR (volatile u16 *)IOP310_REG_ADDR(0x00001282) -#define IOP310_APMCSR (volatile u16 *)IOP310_REG_ADDR(0x00001284) -/* Reserved 0x00001286 through 0x00001287 */ -#define IOP310_ATUCR (volatile u32 *)IOP310_REG_ADDR(0x00001288) -/* Reserved 0x00001289 through 0x0000128C*/ -#define IOP310_PATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001290) -#define IOP310_SATUISR (volatile u32 *)IOP310_REG_ADDR(0x00001294) -#define IOP310_SATUCMD (volatile u16 *)IOP310_REG_ADDR(0x00001298) -#define IOP310_SATUSR (volatile u16 *)IOP310_REG_ADDR(0x0000129A) -#define IOP310_SODWVR (volatile u32 *)IOP310_REG_ADDR(0x0000129C) -#define IOP310_SOUDR (volatile u32 *)IOP310_REG_ADDR(0x000012A0) -#define IOP310_POCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A4) -#define IOP310_SOCCAR (volatile u32 *)IOP310_REG_ADDR(0x000012A8) -#define IOP310_POCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012AC) -#define IOP310_SOCCDR (volatile u32 *)IOP310_REG_ADDR(0x000012B0) -#define IOP310_PAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B4) -#define IOP310_SAQCR (volatile u32 *)IOP310_REG_ADDR(0x000012B8) -#define IOP310_PATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012BC) -#define IOP310_SATUIMR (volatile u32 *)IOP310_REG_ADDR(0x000012C0) -/* Reserved 0x000012C4 through 0x000012FF */ -/* Messaging Unit 0x00001300 through 0x000013FF */ -#define IOP310_MUIMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001310) -#define IOP310_MUIMR1 (volatile u32 *)IOP310_REG_ADDR(0x00001314) -#define IOP310_MUOMR0 (volatile u32 *)IOP310_REG_ADDR(0x00001318) -#define IOP310_MUOMR1 (volatile u32 *)IOP310_REG_ADDR(0x0000131C) -#define IOP310_MUIDR (volatile u32 *)IOP310_REG_ADDR(0x00001320) -#define IOP310_MUIISR (volatile u32 *)IOP310_REG_ADDR(0x00001324) -#define IOP310_MUIIMR (volatile u32 *)IOP310_REG_ADDR(0x00001328) -#define IOP310_MUODR (volatile u32 *)IOP310_REG_ADDR(0x0000132C) -#define IOP310_MUOISR (volatile u32 *)IOP310_REG_ADDR(0x00001330) -#define IOP310_MUOIMR (volatile u32 *)IOP310_REG_ADDR(0x00001334) -#define IOP310_MUMUCR (volatile u32 *)IOP310_REG_ADDR(0x00001350) -#define IOP310_MUQBAR (volatile u32 *)IOP310_REG_ADDR(0x00001354) -#define IOP310_MUIFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001360) -#define IOP310_MUIFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001364) -#define IOP310_MUIPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001368) -#define IOP310_MUIPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000136C) -#define IOP310_MUOFHPR (volatile u32 *)IOP310_REG_ADDR(0x00001370) -#define IOP310_MUOFTPR (volatile u32 *)IOP310_REG_ADDR(0x00001374) -#define IOP310_MUOPHPR (volatile u32 *)IOP310_REG_ADDR(0x00001378) -#define IOP310_MUOPTPR (volatile u32 *)IOP310_REG_ADDR(0x0000137C) -#define IOP310_MUIAR (volatile u32 *)IOP310_REG_ADDR(0x00001380) -/* DMA Controller 0x00001400 through 0x000014FF */ -#define IOP310_DMA0CCR (volatile u32 *)IOP310_REG_ADDR(0x00001400) -#define IOP310_DMA0CSR (volatile u32 *)IOP310_REG_ADDR(0x00001404) -/* Reserved 0x001408 through 0x00140B */ -#define IOP310_DMA0DAR (volatile u32 *)IOP310_REG_ADDR(0x0000140C) -#define IOP310_DMA0NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001410) -#define IOP310_DMA0PADR (volatile u32 *)IOP310_REG_ADDR(0x00001414) -#define IOP310_DMA0PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001418) -#define IOP310_DMA0LADR (volatile u32 *)IOP310_REG_ADDR(0x0000141C) -#define IOP310_DMA0BCR (volatile u32 *)IOP310_REG_ADDR(0x00001420) -#define IOP310_DMA0DCR (volatile u32 *)IOP310_REG_ADDR(0x00001424) -/* Reserved 0x00001428 through 0x0000143F */ -#define IOP310_DMA1CCR (volatile u32 *)IOP310_REG_ADDR(0x00001440) -#define IOP310_DMA1CSR (volatile u32 *)IOP310_REG_ADDR(0x00001444) -/* Reserved 0x00001448 through 0x0000144B */ -#define IOP310_DMA1DAR (volatile u32 *)IOP310_REG_ADDR(0x0000144C) -#define IOP310_DMA1NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001450) -#define IOP310_DMA1PADR (volatile u32 *)IOP310_REG_ADDR(0x00001454) -#define IOP310_DMA1PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001458) -#define IOP310_DMA1LADR (volatile u32 *)IOP310_REG_ADDR(0x0000145C) -#define IOP310_DMA1BCR (volatile u32 *)IOP310_REG_ADDR(0x00001460) -#define IOP310_DMA1DCR (volatile u32 *)IOP310_REG_ADDR(0x00001464) -/* Reserved 0x00001468 through 0x0000147F */ -#define IOP310_DMA2CCR (volatile u32 *)IOP310_REG_ADDR(0x00001480) -#define IOP310_DMA2CSR (volatile u32 *)IOP310_REG_ADDR(0x00001484) -/* Reserved 0x00001488 through 0x0000148B */ -#define IOP310_DMA2DAR (volatile u32 *)IOP310_REG_ADDR(0x0000148C) -#define IOP310_DMA2NDAR (volatile u32 *)IOP310_REG_ADDR(0x00001490) -#define IOP310_DMA2PADR (volatile u32 *)IOP310_REG_ADDR(0x00001494) -#define IOP310_DMA2PUADR (volatile u32 *)IOP310_REG_ADDR(0x00001498) -#define IOP310_DMA2LADR (volatile u32 *)IOP310_REG_ADDR(0x0000149C) -#define IOP310_DMA2BCR (volatile u32 *)IOP310_REG_ADDR(0x000014A0) -#define IOP310_DMA2DCR (volatile u32 *)IOP310_REG_ADDR(0x000014A4) - -/* Memory controller 0x00001500 through 0x0015FF */ - -/* core interface unit 0x00001640 - 0x0000167F */ -#define IOP310_CIUISR (volatile u32 *)IOP310_REG_ADDR(0x00001644) - -/* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */ -#define IOP310_IRQISR (volatile u32 *)IOP310_REG_ADDR(0x00001700) -#define IOP310_FIQ2ISR (volatile u32 *)IOP310_REG_ADDR(0x00001704) -#define IOP310_FIQ1ISR (volatile u32 *)IOP310_REG_ADDR(0x00001708) -#define IOP310_PDIDR (volatile u32 *)IOP310_REG_ADDR(0x00001710) - -/* AAU registers. DJ 0x00001800 - 0x00001838 */ -#define IOP310_AAUACR (volatile u32 *)IOP310_REG_ADDR(0x00001800) -#define IOP310_AAUASR (volatile u32 *)IOP310_REG_ADDR(0x00001804) -#define IOP310_AAUADAR (volatile u32 *)IOP310_REG_ADDR(0x00001808) -#define IOP310_AAUANDAR (volatile u32 *)IOP310_REG_ADDR(0x0000180C) -#define IOP310_AAUSAR1 (volatile u32 *)IOP310_REG_ADDR(0x00001810) -#define IOP310_AAUSAR2 (volatile u32 *)IOP310_REG_ADDR(0x00001814) -#define IOP310_AAUSAR3 (volatile u32 *)IOP310_REG_ADDR(0x00001818) -#define IOP310_AAUSAR4 (volatile u32 *)IOP310_REG_ADDR(0x0000181C) -#define IOP310_AAUDAR (volatile u32 *)IOP310_REG_ADDR(0x00001820) -#define IOP310_AAUABCR (volatile u32 *)IOP310_REG_ADDR(0x00001824) -#define IOP310_AAUADCR (volatile u32 *)IOP310_REG_ADDR(0x00001828) -#define IOP310_AAUSAR5 (volatile u32 *)IOP310_REG_ADDR(0x0000182C) -#define IOP310_AAUSAR6 (volatile u32 *)IOP310_REG_ADDR(0x00001830) -#define IOP310_AAUSAR7 (volatile u32 *)IOP310_REG_ADDR(0x00001834) -#define IOP310_AAUSAR8 (volatile u32 *)IOP310_REG_ADDR(0x00001838) - -#endif // _IOP310_HW_H_ diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h index dcf2c7ff998250..4530adba61a7ea 100644 --- a/include/asm-arm/arch-iop3xx/iop321.h +++ b/include/asm-arm/arch-iop3xx/iop321.h @@ -30,7 +30,7 @@ #define IOP321_PCI_IO_BASE 0x90000000 #define IOP321_PCI_IO_SIZE 0x00010000 -#define IOP321_PCI_MEM_BASE 0x40000000 +#define IOP321_PCI_MEM_BASE 0x80000000 #define IOP321_PCI_MEM_SIZE 0x40000000 /* diff --git a/include/asm-arm/arch-iop3xx/iq80310.h b/include/asm-arm/arch-iop3xx/iq80310.h deleted file mode 100644 index 85dbda84c6ba2b..00000000000000 --- a/include/asm-arm/arch-iop3xx/iq80310.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * linux/include/asm/arch-iop80310/iq80310.h - * - * Intel IQ-80310 evaluation board registers - */ - -#ifndef _IQ80310_H_ -#define _IQ80310_H_ - -#define IQ80310_RAMBASE 0xa0000000 -#define IQ80310_UART1 0xfe800000 /* UART #1 */ -#define IQ80310_UART2 0xfe810000 /* UART #2 */ -#define IQ80310_INT_STAT 0xfe820000 /* Interrupt (XINT3#) Status */ -#define IQ80310_BOARD_REV 0xfe830000 /* Board revision register */ -#define IQ80310_CPLD_REV 0xfe840000 /* CPLD revision register */ -#define IQ80310_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ80310_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ80310_PCI_INT_STAT 0xfe850000 /* PCI Interrupt Status */ -#define IQ80310_INT_MASK 0xfe860000 /* Interrupt (XINT3#) Mask */ -#define IQ80310_BACKPLANE 0xfe870000 /* Backplane Detect */ -#define IQ80310_TIMER_LA0 0xfe880000 /* Timer LA0 */ -#define IQ80310_TIMER_LA1 0xfe890000 /* Timer LA1 */ -#define IQ80310_TIMER_LA2 0xfe8a0000 /* Timer LA2 */ -#define IQ80310_TIMER_LA3 0xfe8b0000 /* Timer LA3 */ -#define IQ80310_TIMER_EN 0xfe8c0000 /* Timer Enable */ -#define IQ80310_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ80310_JTAG 0xfe8e0000 /* JTAG Port Access */ -#define IQ80310_BATT_STAT 0xfe8f0000 /* Battery Status */ - -#endif // _IQ80310_H_ diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h index 1df33024c8eacf..d3bc792882378d 100644 --- a/include/asm-arm/arch-iop3xx/irqs.h +++ b/include/asm-arm/arch-iop3xx/irqs.h @@ -15,11 +15,7 @@ /* * Whic iop3xx implementation is this? */ -#ifdef CONFIG_ARCH_IOP310 - -#include "iop310-irqs.h" - -#else +#ifdef CONFIG_ARCH_IOP321 #include "iop321-irqs.h" diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h index a2d077a3b3b5f2..0b95d4be71daa9 100644 --- a/include/asm-arm/arch-iop3xx/memory.h +++ b/include/asm-arm/arch-iop3xx/memory.h @@ -1,12 +1,11 @@ /* - * linux/include/asm-arm/arch-iop80310/memory.h + * linux/include/asm-arm/arch-iop3xx/memory.h */ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H #include <linux/config.h> -#include <asm/arch/iop310.h> #include <asm/arch/iop321.h> /* @@ -21,23 +20,13 @@ * bus_to_virt: Used to convert an address for DMA operations * to an address that the kernel can use. */ -#ifdef CONFIG_ARCH_IOP310 - -#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0)) -#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR))) - -#elif defined(CONFIG_ARCH_IOP321) +#if defined(CONFIG_ARCH_IOP321) #define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0)) #define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2))) #endif -/* boot mem allocate global pointer for MU circular queues QBAR */ -#ifdef CONFIG_IOP3XX_MU -extern void *mu_mem; -#endif - #define PFN_TO_NID(addr) (0) #endif diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h index 56a1672f1f6d99..acf404e87358a3 100644 --- a/include/asm-arm/arch-iop3xx/param.h +++ b/include/asm-arm/arch-iop3xx/param.h @@ -1,3 +1,3 @@ /* - * linux/include/asm-arm/arch-iop80310/param.h + * linux/include/asm-arm/arch-iop3xx/param.h */ diff --git a/include/asm-arm/arch-iop3xx/pmon.h b/include/asm-arm/arch-iop3xx/pmon.h deleted file mode 100644 index 7f93c1054c35f7..00000000000000 --- a/include/asm-arm/arch-iop3xx/pmon.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Definitions for XScale 80312 PMON - * (C) 2001 Intel Corporation - * Author: Chen Chen(chen.chen@intel.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _IOP310_PMON_H_ -#define _IOP310_PMON_H_ - -/* - * Different modes for Event Select Register for intel 80312 - */ - -#define IOP310_PMON_MODE0 0x00000000 -#define IOP310_PMON_MODE1 0x00000001 -#define IOP310_PMON_MODE2 0x00000002 -#define IOP310_PMON_MODE3 0x00000003 -#define IOP310_PMON_MODE4 0x00000004 -#define IOP310_PMON_MODE5 0x00000005 -#define IOP310_PMON_MODE6 0x00000006 -#define IOP310_PMON_MODE7 0x00000007 - -typedef struct _iop310_pmon_result -{ - u32 timestamp; /* Global Time Stamp Register */ - u32 timestamp_overflow; /* Time Stamp overflow count */ - u32 event_count[14]; /* Programmable Event Counter - Registers 1-14 */ - u32 event_overflow[14]; /* Overflow counter for PECR1-14 */ -} iop310_pmon_res_t; - -/* function prototypes */ - -/* Claim IQ80312 PMON for usage */ -int iop310_pmon_claim(void); - -/* Start IQ80312 PMON */ -int iop310_pmon_start(int, int); - -/* Stop Performance Monitor Unit */ -int iop310_pmon_stop(iop310_pmon_res_t *); - -/* Release IQ80312 PMON */ -int iop310_pmon_release(int); - -#endif diff --git a/include/asm-arm/arch-iop3xx/serial.h b/include/asm-arm/arch-iop3xx/serial.h index 8217c12b812e05..34e539e24c8386 100644 --- a/include/asm-arm/arch-iop3xx/serial.h +++ b/include/asm-arm/arch-iop3xx/serial.h @@ -15,18 +15,6 @@ /* Standard COM flags */ #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#ifdef CONFIG_ARCH_IQ80310 - -#define IRQ_UART1 IRQ_IQ80310_UART1 -#define IRQ_UART2 IRQ_IQ80310_UART2 - -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, IQ80310_UART2, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, IQ80310_UART1, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */ - -#endif // CONFIG_ARCH_IQ80310 - #ifdef CONFIG_ARCH_IQ80321 #define IRQ_UART1 IRQ_IQ80321_UART diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h index 54a101b3944f8b..f6a6d91eeec18b 100644 --- a/include/asm-arm/arch-iop3xx/system.h +++ b/include/asm-arm/arch-iop3xx/system.h @@ -1,5 +1,5 @@ /* - * linux/include/asm-arm/arch-iop80310/system.h + * linux/include/asm-arm/arch-iop3xx/system.h * * Copyright (C) 2001 MontaVista Software, Inc. * diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h index 2aec857754b48c..f216e1f4d6bd64 100644 --- a/include/asm-arm/arch-iop3xx/timex.h +++ b/include/asm-arm/arch-iop3xx/timex.h @@ -1,22 +1,12 @@ /* * linux/include/asm-arm/arch-iop3xx/timex.h * - * IOP310 architecture timex specifications + * IOP3xx architecture timex specifications */ #include <linux/config.h> -#ifdef CONFIG_ARCH_IQ80310 - -#ifndef CONFIG_XSCALE_PMU_TIMER -/* This is for the on-board timer */ -#define CLOCK_TICK_RATE 33000000 /* Underlying HZ */ -#else -/* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */ -#define CLOCK_TICK_RATE 733000000 -#endif // IQ80310 - -#elif defined(CONFIG_ARCH_IQ80321) +#if defined(CONFIG_ARCH_IQ80321) #define CLOCK_TICK_RATE 200000000 diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h index fd7e72b7d11305..893d8954f7e17d 100644 --- a/include/asm-arm/arch-iop3xx/uncompress.h +++ b/include/asm-arm/arch-iop3xx/uncompress.h @@ -1,13 +1,11 @@ /* - * linux/include/asm-arm/arch-iop80310/uncompress.h + * linux/include/asm-arm/arch-iop3xx/uncompress.h */ #include <linux/config.h> #include <linux/serial_reg.h> #include <asm/hardware.h> -#ifdef CONFIG_ARCH_IQ80310 -#define UART2_BASE ((volatile unsigned char *)IQ80310_UART2) -#elif defined(CONFIG_ARCH_IQ80321) +#if defined(CONFIG_ARCH_IQ80321) #define UART2_BASE ((volatile unsigned char *)IQ80321_UART1) #endif diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h index fe2c06ddedbf85..e51f24888302c9 100644 --- a/include/asm-arm/arch-omap/board-h2.h +++ b/include/asm-arm/arch-omap/board-h2.h @@ -31,5 +31,15 @@ /* Placeholder for H2 specific defines */ +/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ +#define OMAP1610_ETHR_BASE 0xE8000000 +#define OMAP1610_ETHR_SIZE SZ_4K +#define OMAP1610_ETHR_START 0x04000000 + +/* Intel STRATA NOR flash at CS3 */ +#define OMAP1610_NOR_FLASH_BASE 0xD8000000 +#define OMAP1610_NOR_FLASH_SIZE SZ_32M +#define OMAP1610_NOR_FLASH_START 0x0C000000 + #endif /* __ASM_ARCH_OMAP_H2_H */ diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h index f08276f896522c..80c37bf3bf4070 100644 --- a/include/asm-arm/arch-omap/board-h3.h +++ b/include/asm-arm/arch-omap/board-h3.h @@ -1,9 +1,8 @@ /* * linux/include/asm-arm/arch-omap/board-h3.h * - * Hardware definitions for TI OMAP1610 H3 board. - * - * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> + * Copyright (C) 2001 RidgeRun, Inc. + * Copyright (C) 2004 Texas Instruments, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -25,11 +24,84 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ - #ifndef __ASM_ARCH_OMAP_H3_H #define __ASM_ARCH_OMAP_H3_H -/* Placeholder for H3 specific defines */ +/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ +#define OMAP1710_ETHR_BASE 0xE8000000 +#define OMAP1710_ETHR_SIZE SZ_4K +#define OMAP1710_ETHR_START 0x04000000 -#endif /* __ASM_ARCH_OMAP_H3_H */ +/* Intel STRATA NOR flash at CS3 */ +#define OMAP_NOR_FLASH_BASE 0xD8000000 +#define OMAP_NOR_FLASH_SIZE SZ_32M +#define OMAP_NOR_FLASH_START 0x00000000 + +#define MAXIRQNUM (IH_BOARD_BASE) +#define MAXFIQNUM MAXIRQNUM +#define MAXSWINUM MAXIRQNUM +#define NR_IRQS (MAXIRQNUM + 1) + +#define OMAP_MCBSP1_BASE OMAP1610_MCBSP1_BASE +#define AUDIO_DRR2 (OMAP_MCBSP1_BASE + 0x00) +#define AUDIO_DRR1 (OMAP_MCBSP1_BASE + 0x02) +#define AUDIO_DXR2 (OMAP_MCBSP1_BASE + 0x04) +#define AUDIO_DXR1 (OMAP_MCBSP1_BASE + 0x06) +#define AUDIO_SPCR2 (OMAP_MCBSP1_BASE + 0x08) +#define AUDIO_SPCR1 (OMAP_MCBSP1_BASE + 0x0a) +#define AUDIO_RCR2 (OMAP_MCBSP1_BASE + 0x0c) +#define AUDIO_RCR1 (OMAP_MCBSP1_BASE + 0x0e) +#define AUDIO_XCR2 (OMAP_MCBSP1_BASE + 0x10) +#define AUDIO_XCR1 (OMAP_MCBSP1_BASE + 0x12) +#define AUDIO_SRGR2 (OMAP_MCBSP1_BASE + 0x14) +#define AUDIO_SRGR1 (OMAP_MCBSP1_BASE + 0x16) +#define AUDIO_MCR2 (OMAP_MCBSP1_BASE + 0x18) +#define AUDIO_MCR1 (OMAP_MCBSP1_BASE + 0x1a) +#define AUDIO_RCERA (OMAP_MCBSP1_BASE + 0x1c) +#define AUDIO_RCERB (OMAP_MCBSP1_BASE + 0x1e) +#define AUDIO_XCERA (OMAP_MCBSP1_BASE + 0x20) +#define AUDIO_XCERB (OMAP_MCBSP1_BASE + 0x22) +#define AUDIO_PCR0 (OMAP_MCBSP1_BASE + 0x24) + +/* UART3 Registers Maping through MPU bus */ +#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ +#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) +#define UART3_THR (OMAP_MPU_UART3_BASE + 0) +#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) +#define UART3_IER (OMAP_MPU_UART3_BASE + 4) +#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) +#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) +#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) +#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) +#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) +#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) +#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) +#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) +#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) +#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) +#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) +#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) +#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) +#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) +#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) +#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) +#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) +#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) +#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) +#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) +#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) +#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) + +#endif /* __ASM_ARCH_OMAP_H3_H */ diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h index 50671ba477d720..87e45d92940a73 100644 --- a/include/asm-arm/arch-omap/board-innovator.h +++ b/include/asm-arm/arch-omap/board-innovator.h @@ -28,92 +28,6 @@ #if defined (CONFIG_ARCH_OMAP1510) -/* - * --------------------------------------------------------------------------- - * OMAP-1510 FPGA - * --------------------------------------------------------------------------- - */ -#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ -#define OMAP1510_FPGA_SIZE SZ_4K -#define OMAP1510_FPGA_START 0x08000000 /* Physical */ - -/* Revision */ -#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) -#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) - -#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) -#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) -#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) -#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) - -/* Interrupt status */ -#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) -#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) - -/* Interrupt mask */ -#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) -#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) - -/* Reset registers */ -#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) -#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) - -#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) -#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) -#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) -#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) -#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) -#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) -#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) -#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) -#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) -#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) - -#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) - -#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) -#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) -#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) -#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) -#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) -#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) -#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) -#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) -#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) -#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) -#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) - -#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) -#define OMAP1510_FPGA_ETHR_BASE (OMAP1510_FPGA_BASE + 0x300) - -/* - * Power up Giga UART driver, turn on HID clock. - * Turn off BT power, since we're not using it and it - * draws power. - */ -#define OMAP1510_FPGA_RESET_VALUE 0x42 - -#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) -#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) -#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) -#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) -#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) -#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) -#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) -#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) - -/* - * Innovator/OMAP1510 FPGA HID register bit definitions - */ -#define FPGA_HID_SCLK (1<<0) /* output */ -#define FPGA_HID_MOSI (1<<1) /* output */ -#define FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ -#define FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ -#define FPGA_HID_MISO (1<<4) /* input */ -#define FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ -#define FPGA_HID_rsrvd (1<<6) -#define FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ - #ifndef OMAP_SDRAM_DEVICE #define OMAP_SDRAM_DEVICE D256M_1X16_4B #endif @@ -147,37 +61,8 @@ #define OMAP_FLASH_1_START 0x01000000 #define OMAP_FLASH_1_SIZE SZ_16M -/* The FPGA IRQ is cascaded through GPIO_13 */ -#define INT_FPGA (IH_GPIO_BASE + 13) - -/* IRQ Numbers for interrupts muxed through the FPGA */ -#define IH_FPGA_BASE IH_BOARD_BASE -#define INT_FPGA_ATN (IH_FPGA_BASE + 0) -#define INT_FPGA_ACK (IH_FPGA_BASE + 1) -#define INT_FPGA2 (IH_FPGA_BASE + 2) -#define INT_FPGA3 (IH_FPGA_BASE + 3) -#define INT_FPGA4 (IH_FPGA_BASE + 4) -#define INT_FPGA5 (IH_FPGA_BASE + 5) -#define INT_FPGA6 (IH_FPGA_BASE + 6) -#define INT_FPGA7 (IH_FPGA_BASE + 7) -#define INT_FPGA8 (IH_FPGA_BASE + 8) -#define INT_FPGA9 (IH_FPGA_BASE + 9) -#define INT_FPGA10 (IH_FPGA_BASE + 10) -#define INT_FPGA11 (IH_FPGA_BASE + 11) -#define INT_FPGA12 (IH_FPGA_BASE + 12) -#define INT_ETHER (IH_FPGA_BASE + 13) -#define INT_FPGAUART1 (IH_FPGA_BASE + 14) -#define INT_FPGAUART2 (IH_FPGA_BASE + 15) -#define INT_FPGA_TS (IH_FPGA_BASE + 16) -#define INT_FPGA17 (IH_FPGA_BASE + 17) -#define INT_FPGA_CAM (IH_FPGA_BASE + 18) -#define INT_FPGA_RTC_A (IH_FPGA_BASE + 19) -#define INT_FPGA_RTC_B (IH_FPGA_BASE + 20) -#define INT_FPGA_CD (IH_FPGA_BASE + 21) -#define INT_FPGA22 (IH_FPGA_BASE + 22) -#define INT_FPGA23 (IH_FPGA_BASE + 23) - -#define NR_FPGA_IRQS 24 +#define NR_FPGA_IRQS 24 +#define NR_IRQS IH_BOARD_BASE + NR_FPGA_IRQS #ifndef __ASSEMBLY__ void fpga_write(unsigned char val, int reg); diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h index 4839c44511c0b1..0c224cc74fe428 100644 --- a/include/asm-arm/arch-omap/board-perseus2.h +++ b/include/asm-arm/arch-omap/board-perseus2.h @@ -2,8 +2,7 @@ * linux/include/asm-arm/arch-omap/board-perseus2.h * * Copyright 2003 by Texas Instruments Incorporated - * OMAP730 / P2-sample additions - * Author: Jean Pihet + * OMAP730 / Perseus2 support by Jean Pihet * * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) * Author: RidgeRun, Inc. @@ -28,46 +27,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H -#define __ASM_ARCH_OMAP_P2SAMPLE_H +#ifndef __ASM_ARCH_OMAP_PERSEUS2_H +#define __ASM_ARCH_OMAP_PERSEUS2_H -#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2) - -/* - * NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER - * P2SAMPLE_ since they are specific to the EVM and not the chip. - */ - -/* --------------------------------------------------------------------------- - * OMAP730 Debug Board FPGA - * --------------------------------------------------------------------------- - */ - -/* maps in the FPGA registers and the ETHR registers */ -#define OMAP730_FPGA_BASE 0xE8000000 /* VA */ -#define OMAP730_FPGA_SIZE SZ_4K /* SIZE */ -#define OMAP730_FPGA_START 0x04000000 /* PA */ - -#define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START -#define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE -#define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */ -#define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */ -#define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */ -#define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */ -#define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */ -#define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */ -#define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */ - -// LEDs definition on debug board (16 LEDs) -#define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15) -#define OMAP730_FPGA_LED_STARTSTOP (1 << 14) -#define OMAP730_FPGA_LED_HALTED (1 << 13) -#define OMAP730_FPGA_LED_IDLE (1 << 12) -#define OMAP730_FPGA_LED_TIMER (1 << 11) -// cpu0 load-meter LEDs -#define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... -#define OMAP730_FPGA_LOAD_METER_SIZE 11 -#define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1) +#include <asm/arch/fpga.h> #ifndef OMAP_SDRAM_DEVICE #define OMAP_SDRAM_DEVICE D256M_1X16_4B @@ -86,22 +49,10 @@ #define OMAP_FLASH_0_START 0x00000000 /* PA */ #define OMAP_FLASH_0_SIZE SZ_32M -/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */ -#define INT_ETHER INT_730_MPU_EXT_NIRQ - #define MAXIRQNUM IH_BOARD_BASE #define MAXFIQNUM MAXIRQNUM #define MAXSWINUM MAXIRQNUM #define NR_IRQS (MAXIRQNUM + 1) -#ifndef __ASSEMBLY__ -void fpga_write(unsigned char val, int reg); -unsigned char fpga_read(int reg); -#endif - -#else -#error "Only OMAP730 Perseus2 supported!" -#endif - #endif diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h index fe21fc817749e3..a24193510e90e8 100644 --- a/include/asm-arm/arch-omap/board.h +++ b/include/asm-arm/arch-omap/board.h @@ -17,32 +17,69 @@ #define OMAP_TAG_CLOCK 0x4f01 #define OMAP_TAG_MMC 0x4f02 #define OMAP_TAG_UART 0x4f03 +#define OMAP_TAG_USB 0x4f04 -struct omap_clock_info { +struct omap_clock_config { /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ u8 system_clock_type; }; -struct omap_mmc_info { +struct omap_mmc_config { u8 mmc_blocks; s8 mmc1_power_pin, mmc2_power_pin; s8 mmc1_switch_pin, mmc2_switch_pin; }; -struct omap_uart_info { +struct omap_uart_config { u8 console_uart; u32 console_speed; }; -struct omap_board_info_entry { +struct omap_usb_config { + /* Configure drivers according to the connectors on your board: + * - "A" connector (rectagular) + * ... for host/OHCI use, set "register_host". + * - "B" connector (squarish) or "Mini-B" + * ... for device/gadget use, set "register_dev". + * - "Mini-AB" connector (very similar to Mini-B) + * ... for OTG use as device OR host, initialize "otg" + */ + unsigned register_host:1; + unsigned register_dev:1; + u8 otg; /* port number, 1-based: usb1 == 2 */ + + u8 hmc_mode; + + /* implicitly true if otg: host supports remote wakeup? */ + u8 rwc; + + /* signaling pins used to talk to transceiver on usbN: + * 0 == usbN unused + * 2 == usb0-only, using internal transceiver + * 3 == 3 wire bidirectional + * 4 == 4 wire bidirectional + * 6 == 6 wire unidirectional (or TLL) + */ + u8 pins[3]; +}; + +struct omap_board_config_entry { u16 tag; u16 len; u8 data[0]; }; -extern const void *__omap_get_per_info(u16 tag, size_t len); +struct omap_board_config_kernel { + u16 tag; + const void *data; +}; + +extern const void *__omap_get_config(u16 tag, size_t len); + +#define omap_get_config(tag, type) \ + ((const type *) __omap_get_config((tag), sizeof(type))) -#define omap_get_per_info(tag, type) \ - ((const type *) __omap_get_per_info((tag), sizeof(type))) +extern struct omap_board_config_kernel *omap_board_config; +extern int omap_board_config_size; #endif diff --git a/include/asm-arm/arch-omap/bus.h b/include/asm-arm/arch-omap/bus.h deleted file mode 100644 index afb61f8eacb329..00000000000000 --- a/include/asm-arm/arch-omap/bus.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * linux/include/asm-arm/arch-omap/bus.h - * - * Virtual bus for OMAP. Allows better power management, such as managing - * shared clocks, and mapping of bus addresses to Local Bus addresses. - * - * See drivers/usb/host/ohci-omap.c or drivers/video/omap/omapfb.c for - * examples on how to register drivers to this bus. - * - * Copyright (C) 2003 - 2004 Nokia Corporation - * Written by Tony Lindgren <tony@atomide.com> - * Portions of code based on sa1111.c. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#ifndef __ASM_ARM_ARCH_OMAP_BUS_H -#define __ASM_ARM_ARCH_OMAP_BUS_H - -extern struct bus_type omap_bus_types[]; - -/* - * Description for physical device - */ -struct omap_dev { - struct device dev; /* Standard device description */ - char *name; - unsigned int devid; /* OMAP device id */ - unsigned int busid; /* OMAP virtual busid */ - struct resource res; /* Standard resource description */ - void *mapbase; /* OMAP physical address */ - unsigned int irq[6]; /* OMAP interrupts */ - u64 *dma_mask; /* Used by USB OHCI only */ - u64 coherent_dma_mask; /* Used by USB OHCI only */ -}; - -#define OMAP_DEV(_d) container_of((_d), struct omap_dev, dev) - -#define omap_get_drvdata(d) dev_get_drvdata(&(d)->dev) -#define omap_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p) - -/* - * Description for device driver - */ -struct omap_driver { - struct device_driver drv; /* Standard driver description */ - unsigned int devid; /* OMAP device id for bus */ - unsigned int busid; /* OMAP virtual busid */ - unsigned int clocks; /* OMAP shared clocks */ - int (*probe)(struct omap_dev *); - int (*remove)(struct omap_dev *); - int (*suspend)(struct omap_dev *, u32); - int (*resume)(struct omap_dev *); -}; - -#define OMAP_DRV(_d) container_of((_d), struct omap_driver, drv) -#define OMAP_DRIVER_NAME(_omapdev) ((_omapdev)->dev.driver->name) - -/* - * Device ID numbers for bus types - */ -#define OMAP_OCP_DEVID_USB 0 - -#define OMAP_TIPB_DEVID_OHCI 0 -#define OMAP_TIPB_DEVID_LCD 1 -#define OMAP_TIPB_DEVID_MMC 2 -#define OMAP_TIPB_DEVID_OTG 3 -#define OMAP_TIPB_DEVID_UDC 4 - -/* - * Virtual bus definitions for OMAP - */ -#define OMAP_NR_BUSES 2 - -#define OMAP_BUS_NAME_TIPB "tipb" -#define OMAP_BUS_NAME_LBUS "lbus" - -enum { - OMAP_BUS_TIPB = 0, - OMAP_BUS_LBUS, -}; - -/* See arch/arm/mach-omap/bus.c for the rest of the bus definitions. */ - -extern int omap_driver_register(struct omap_driver *driver); -extern void omap_driver_unregister(struct omap_driver *driver); -extern int omap_device_register(struct omap_dev *odev); -extern void omap_device_unregister(struct omap_dev *odev); - -#endif diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h index 565a87f175bcef..dc9f61a43cb9b3 100644 --- a/include/asm-arm/arch-omap/fpga.h +++ b/include/asm-arm/arch-omap/fpga.h @@ -19,8 +19,161 @@ #ifndef __ASM_ARCH_OMAP_FPGA_H #define __ASM_ARCH_OMAP_FPGA_H -extern void fpga_init_irq(void); -extern unsigned char fpga_read(int reg); -extern void fpga_write(unsigned char val, int reg); +#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510) +extern void omap1510_fpga_init_irq(void); +#else +#define omap1510_fpga_init_irq() (0) +#endif + +#define fpga_read(reg) __raw_readb(reg) +#define fpga_write(val, reg) __raw_writeb(val, reg) + +/* + * --------------------------------------------------------------------------- + * H2/P2 Debug board FPGA + * --------------------------------------------------------------------------- + */ +/* maps in the FPGA registers and the ETHR registers */ +#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ +#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ +#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ + +#define H2P2_DBG_FPGA_ETHR_START H2P2_DBG_FPGA_START +#define H2P2_DBG_FPGA_ETHR_BASE H2P2_DBG_FPGA_BASE +#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ +#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ +#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ +#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ +#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ +#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ +#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ + +/* LEDs definition on debug board (16 LEDs) */ +#define H2P2_DBG_FPGA_LED_CLAIMRELEASE (1 << 15) +#define H2P2_DBG_FPGA_LED_STARTSTOP (1 << 14) +#define H2P2_DBG_FPGA_LED_HALTED (1 << 13) +#define H2P2_DBG_FPGA_LED_IDLE (1 << 12) +#define H2P2_DBG_FPGA_LED_TIMER (1 << 11) +/* cpu0 load-meter LEDs */ +#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... +#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 +#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) + + +/* + * --------------------------------------------------------------------------- + * OMAP-1510 FPGA + * --------------------------------------------------------------------------- + */ +#define OMAP1510_FPGA_BASE 0xE8000000 /* Virtual */ +#define OMAP1510_FPGA_SIZE SZ_4K +#define OMAP1510_FPGA_START 0x08000000 /* Physical */ + +/* Revision */ +#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) +#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) + +#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) +#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) +#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) +#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) + +/* Interrupt status */ +#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) +#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) + +/* Interrupt mask */ +#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) +#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) + +/* Reset registers */ +#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) +#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) + +#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) +#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) +#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) +#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) +#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) +#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) +#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) +#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) +#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) +#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) + +#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) + +#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) +#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) +#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) + +#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) +#define OMAP1510_FPGA_ETHR_BASE (OMAP1510_FPGA_BASE + 0x300) + +/* + * Power up Giga UART driver, turn on HID clock. + * Turn off BT power, since we're not using it and it + * draws power. + */ +#define OMAP1510_FPGA_RESET_VALUE 0x42 + +#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7) +#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6) +#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5) +#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4) +#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3) +#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2) +#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1) +#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0) + +/* + * Innovator/OMAP1510 FPGA HID register bit definitions + */ +#define OMAP1510_FPGA_HID_SCLK (1<<0) /* output */ +#define OMAP1510_FPGA_HID_MOSI (1<<1) /* output */ +#define OMAP1510_FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ +#define OMAP1510_FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ +#define OMAP1510_FPGA_HID_MISO (1<<4) /* input */ +#define OMAP1510_FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ +#define OMAP1510_FPGA_HID_rsrvd (1<<6) +#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ + +/* The FPGA IRQ is cascaded through GPIO_13 */ +#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) + +/* IRQ Numbers for interrupts muxed through the FPGA */ +#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE +#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) +#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) +#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) +#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) +#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) +#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) +#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) +#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) +#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) +#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) +#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) +#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) +#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) +#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) +#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) +#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) +#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) +#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) +#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) +#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) +#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) +#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) +#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) +#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23) #endif diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 348072bc4fbcf3..fe0286912414b1 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -178,6 +178,7 @@ #define IRQ_CONTROL_REG_OFFSET 0x18 #define IRQ_ISR_REG_OFFSET 0x9c #define IRQ_ILR0_REG_OFFSET 0x1c +#define IRQ_GMR_REG_OFFSET 0xa0 /* * --------------------------------------------------------------------------- @@ -185,22 +186,23 @@ * --------------------------------------------------------------------------- */ #define TCMIF_BASE 0xfffecc00 -#define IMIF_PRIO (TCMIF_BASE + 0x00) -#define EMIFS_PRIO (TCMIF_BASE + 0x04) -#define EMIFF_PRIO (TCMIF_BASE + 0x08) -#define EMIFS_CONFIG (TCMIF_BASE + 0x0c) -#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) -#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) -#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) -#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) -#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define EMIFF_MRS (TCMIF_BASE + 0x24) -#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) -#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) -#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) -#define TC_ENDIANISM (TCMIF_BASE + 0x34) -#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) -#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) +#define IMIF_PRIO_REG __REG32(TCMIF_BASE + 0x00) +#define EMIFS_PRIO_REG __REG32(TCMIF_BASE + 0x04) +#define EMIFF_PRIO_REG __REG32(TCMIF_BASE + 0x08) +#define EMIFS_CONFIG_REG __REG32(TCMIF_BASE + 0x0c) +#define EMIFS_CS0_CONFIG_REG __REG32(TCMIF_BASE + 0x10) +#define EMIFS_CS1_CONFIG_REG __REG32(TCMIF_BASE + 0x14) +#define EMIFS_CS2_CONFIG_REG __REG32(TCMIF_BASE + 0x18) +#define EMIFS_CS3_CONFIG_REG __REG32(TCMIF_BASE + 0x1c) +#define EMIFF_SDRAM_CONFIG_REG __REG32(TCMIF_BASE + 0x20) +#define EMIFF_MRS_REG __REG32(TCMIF_BASE + 0x24) +#define TC_TIMEOUT1_REG __REG32(TCMIF_BASE + 0x28) +#define TC_TIMEOUT2_REG __REG32(TCMIF_BASE + 0x2c) +#define TC_TIMEOUT3_REG __REG32(TCMIF_BASE + 0x30) +#define TC_ENDIANISM_REG __REG32(TCMIF_BASE + 0x34) +#define EMIFF_SDRAM_CONFIG_2_REG __REG32(TCMIF_BASE + 0x3c) +#define EMIF_CFG_DYNAMIC_WS_REG __REG32(TCMIF_BASE + 0x40) + /* * ---------------------------------------------------------------------------- * System control registers @@ -290,6 +292,7 @@ #define OMAP_ID_1610 0x3576 #define OMAP_ID_1710 0x35F7 #define OMAP_ID_5912 0x358C +#define OMAP_ID_1611 0x358C #ifdef CONFIG_ARCH_OMAP730 #include "omap730.h" @@ -307,12 +310,16 @@ #ifdef CONFIG_ARCH_OMAP1610 #include "omap1610.h" -#define cpu_is_omap1710() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710) -/* Detect 1710 as 1610 for now */ -#define cpu_is_omap1610() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610 \ - || cpu_is_omap1710()) +#define cpu_is_omap1610() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1610) || \ + (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1611) #else #define cpu_is_omap1610() 0 +#endif + +#ifdef CONFIG_ARCH_OMAP1710 +#include "omap1610.h" +#define cpu_is_omap1710() (((OMAP_ID_REG >> ID_SHIFT) & ID_MASK) == OMAP_ID_1710) +#else #define cpu_is_omap1710() 0 #endif @@ -343,7 +350,6 @@ #ifdef CONFIG_MACH_OMAP_H3 #include "board-h3.h" -#error "Support for H3 board not yet implemented." #endif #ifdef CONFIG_MACH_OMAP_H4 diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h new file mode 100644 index 00000000000000..8e490e3f654d27 --- /dev/null +++ b/include/asm-arm/arch-omap/mcbsp.h @@ -0,0 +1,253 @@ +/* + * linux/include/asm-arm/arch-omap/gpio.h + * + * Defines for Multi-Channel Buffered Serial Port + * + * Copyright (C) 2002 RidgeRun, Inc. + * Author: Steve Johnson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __ASM_ARCH_OMAP_MCBSP_H +#define __ASM_ARCH_OMAP_MCBSP_H + +#include <asm/arch/hardware.h> + +#define OMAP730_MCBSP1_BASE 0xfffb1000 +#define OMAP730_MCBSP2_BASE 0xfffb1800 + +#define OMAP1510_MCBSP1_BASE 0xe1011000 +#define OMAP1510_MCBSP2_BASE 0xfffb1000 +#define OMAP1510_MCBSP3_BASE 0xe1017000 + +#define OMAP1610_MCBSP1_BASE 0xe1011800 +#define OMAP1610_MCBSP2_BASE 0xfffb1000 +#define OMAP1610_MCBSP3_BASE 0xe1017000 + +#define OMAP_MCBSP_REG_DRR2 0x00 +#define OMAP_MCBSP_REG_DRR1 0x02 +#define OMAP_MCBSP_REG_DXR2 0x04 +#define OMAP_MCBSP_REG_DXR1 0x06 +#define OMAP_MCBSP_REG_SPCR2 0x08 +#define OMAP_MCBSP_REG_SPCR1 0x0a +#define OMAP_MCBSP_REG_RCR2 0x0c +#define OMAP_MCBSP_REG_RCR1 0x0e +#define OMAP_MCBSP_REG_XCR2 0x10 +#define OMAP_MCBSP_REG_XCR1 0x12 +#define OMAP_MCBSP_REG_SRGR2 0x14 +#define OMAP_MCBSP_REG_SRGR1 0x16 +#define OMAP_MCBSP_REG_MCR2 0x18 +#define OMAP_MCBSP_REG_MCR1 0x1a +#define OMAP_MCBSP_REG_RCERA 0x1c +#define OMAP_MCBSP_REG_RCERB 0x1e +#define OMAP_MCBSP_REG_XCERA 0x20 +#define OMAP_MCBSP_REG_XCERB 0x22 +#define OMAP_MCBSP_REG_PCR0 0x24 +#define OMAP_MCBSP_REG_RCERC 0x26 +#define OMAP_MCBSP_REG_RCERD 0x28 +#define OMAP_MCBSP_REG_XCERC 0x2A +#define OMAP_MCBSP_REG_XCERD 0x2C +#define OMAP_MCBSP_REG_RCERE 0x2E +#define OMAP_MCBSP_REG_RCERF 0x30 +#define OMAP_MCBSP_REG_XCERE 0x32 +#define OMAP_MCBSP_REG_XCERF 0x34 +#define OMAP_MCBSP_REG_RCERG 0x36 +#define OMAP_MCBSP_REG_RCERH 0x38 +#define OMAP_MCBSP_REG_XCERG 0x3A +#define OMAP_MCBSP_REG_XCERH 0x3C + +#define OMAP_MAX_MCBSP_COUNT 3 + +#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg) +#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg) + +/************************** McBSP SPCR1 bit definitions ***********************/ +#define RRST 0x0001 +#define RRDY 0x0002 +#define RFULL 0x0004 +#define RSYNC_ERR 0x0008 +#define RINTM(value) ((value)<<4) /* bits 4:5 */ +#define ABIS 0x0040 +#define DXENA 0x0080 +#define CLKSTP(value) ((value)<<11) /* bits 11:12 */ +#define RJUST(value) ((value)<<13) /* bits 13:14 */ +#define DLB 0x8000 + +/************************** McBSP SPCR2 bit definitions ***********************/ +#define XRST 0x0001 +#define XRDY 0x0002 +#define XEMPTY 0x0004 +#define XSYNC_ERR 0x0008 +#define XINTM(value) ((value)<<4) /* bits 4:5 */ +#define GRST 0x0040 +#define FRST 0x0080 +#define SOFT 0x0100 +#define FREE 0x0200 + +/************************** McBSP PCR bit definitions *************************/ +#define CLKRP 0x0001 +#define CLKXP 0x0002 +#define FSRP 0x0004 +#define FSXP 0x0008 +#define DR_STAT 0x0010 +#define DX_STAT 0x0020 +#define CLKS_STAT 0x0040 +#define SCLKME 0x0080 +#define CLKRM 0x0100 +#define CLKXM 0x0200 +#define FSRM 0x0400 +#define FSXM 0x0800 +#define RIOEN 0x1000 +#define XIOEN 0x2000 +#define IDLE_EN 0x4000 + +/************************** McBSP RCR1 bit definitions ************************/ +#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */ +#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */ + +/************************** McBSP XCR1 bit definitions ************************/ +#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */ +#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */ + +/*************************** McBSP RCR2 bit definitions ***********************/ +#define RDATDLY(value) (value) /* Bits 0:1 */ +#define RFIG 0x0004 +#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */ +#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */ +#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */ +#define RPHASE 0x8000 + +/*************************** McBSP XCR2 bit definitions ***********************/ +#define XDATDLY(value) (value) /* Bits 0:1 */ +#define XFIG 0x0004 +#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */ +#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */ +#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */ +#define XPHASE 0x8000 + +/************************* McBSP SRGR1 bit definitions ************************/ +#define CLKGDV(value) (value) /* Bits 0:7 */ +#define FWID(value) ((value)<<8) /* Bits 8:15 */ + +/************************* McBSP SRGR2 bit definitions ************************/ +#define FPER(value) (value) /* Bits 0:11 */ +#define FSGM 0x1000 +#define CLKSM 0x2000 +#define CLKSP 0x4000 +#define GSYNC 0x8000 + +/************************* McBSP MCR1 bit definitions *************************/ +#define RMCM 0x0001 +#define RCBLK(value) ((value)<<2) /* Bits 2:4 */ +#define RPABLK(value) ((value)<<5) /* Bits 5:6 */ +#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */ + +/************************* McBSP MCR2 bit definitions *************************/ +#define XMCM(value) (value) /* Bits 0:1 */ +#define XCBLK(value) ((value)<<2) /* Bits 2:4 */ +#define XPABLK(value) ((value)<<5) /* Bits 5:6 */ +#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ + + +/* we don't do multichannel for now */ +struct omap_mcbsp_reg_cfg { + u16 spcr2; + u16 spcr1; + u16 rcr2; + u16 rcr1; + u16 xcr2; + u16 xcr1; + u16 srgr2; + u16 srgr1; + u16 mcr2; + u16 mcr1; + u16 pcr0; + u16 rcerc; + u16 rcerd; + u16 xcerc; + u16 xcerd; + u16 rcere; + u16 rcerf; + u16 xcere; + u16 xcerf; + u16 rcerg; + u16 rcerh; + u16 xcerg; + u16 xcerh; +}; + +typedef enum { + OMAP_MCBSP1 = 0, + OMAP_MCBSP2, + OMAP_MCBSP3, +} omap_mcbsp_id; + +typedef enum { + OMAP_MCBSP_WORD_8 = 0, + OMAP_MCBSP_WORD_12, + OMAP_MCBSP_WORD_16, + OMAP_MCBSP_WORD_20, + OMAP_MCBSP_WORD_24, + OMAP_MCBSP_WORD_32, +} omap_mcbsp_word_length; + +typedef enum { + OMAP_MCBSP_CLK_RISING = 0, + OMAP_MCBSP_CLK_FALLING, +} omap_mcbsp_clk_polarity; + +typedef enum { + OMAP_MCBSP_FS_ACTIVE_HIGH = 0, + OMAP_MCBSP_FS_ACTIVE_LOW, +} omap_mcbsp_fs_polarity; + +typedef enum { + OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0, + OMAP_MCBSP_CLK_STP_MODE_DELAY, +} omap_mcbsp_clk_stp_mode; + + +/******* SPI specific mode **********/ +typedef enum { + OMAP_MCBSP_SPI_MASTER = 0, + OMAP_MCBSP_SPI_SLAVE, +} omap_mcbsp_spi_mode; + +struct omap_mcbsp_spi_cfg { + omap_mcbsp_spi_mode spi_mode; + omap_mcbsp_clk_polarity rx_clock_polarity; + omap_mcbsp_clk_polarity tx_clock_polarity; + omap_mcbsp_fs_polarity fsx_polarity; + u8 clk_div; + omap_mcbsp_clk_stp_mode clk_stp_mode; + omap_mcbsp_word_length word_length; +}; + +void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); +int omap_mcbsp_request(unsigned int id); +void omap_mcbsp_free(unsigned int id); +void omap_mcbsp_start(unsigned int id); +void omap_mcbsp_stop(unsigned int id); +void omap_mcbsp_xmit_word(unsigned int id, u32 word); +u32 omap_mcbsp_recv_word(unsigned int id); + +int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); +int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); + +/* SPI specific API */ +void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); + +#endif diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h index 4f9e8c842d6d91..c93c05288c1743 100644 --- a/include/asm-arm/arch-omap/memory.h +++ b/include/asm-arm/arch-omap/memory.h @@ -64,7 +64,7 @@ #define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET) #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) -#define is_lbus_device(dev) (cpu_is_omap1510() && dev->coherent_dma_mask == 0x0fffffff) +#define is_lbus_device(dev) (cpu_is_omap1510() && dev && dev->coherent_dma_mask == 0x0fffffff) #define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ (dma_addr_t)virt_to_lbus(page_address(page)) : \ diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 405395706196c5..d0fdf9833ac4a7 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -135,6 +135,10 @@ typedef enum { UART3_CLKREQ, UART3_BCLK, /* 12MHz clock out */ + /* PWT & PWL */ + PWT, + PWL, + /* USB master generic */ R18_USB_VBUS, R18_1510_USB_GPIO0, @@ -154,6 +158,7 @@ typedef enum { USB1_RCV, USB1_SPEED, R13_1610_USB1_SPEED, + R13_1710_USB1_SE0, /* USB2 master */ USB2_SUSP, @@ -169,6 +174,10 @@ typedef enum { R19_1510_GPIO1, M14_1510_GPIO2, + /* OMAP-1710 GPIO */ + R18_1710_GPIO0, + W15_1710_GPIO40, + /* MPUIO */ MPUIO2, MPUIO4, @@ -225,6 +234,7 @@ typedef enum { P10_1610_GPIO22, V5_1610_GPIO24, AA20_1610_GPIO_41, + W19_1610_GPIO48, /* OMAP-1610 uWire */ V19_1610_UWIRE_SCLK, @@ -242,6 +252,11 @@ typedef enum { MMC_CLK, MMC_DAT3, + /* OMAP-1710 MMC CMDDIR and DATDIR0 */ + M15_1710_MMC_CLKI, + P19_1710_MMC_CMDDIR, + P20_1710_MMC_DATDIR0, + /* OMAP-1610 USB0 alternate pin configuration */ W9_USB0_TXEN, AA9_USB0_VP, @@ -317,6 +332,10 @@ MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0) MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0) MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0) +/* PWT & PWL, conflicts with UART3 */ +MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0) +MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0) + /* USB internal master generic */ MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1) MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1) @@ -336,6 +355,7 @@ MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1) MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1) MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1) MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1) +MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1) /* USB2 master */ MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1) @@ -347,9 +367,13 @@ MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1) MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1) /* OMAP-1510 GPIO */ -MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1) -MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1) -MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1) +MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1) +MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1) +MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1) + +/* OMAP-1710 GPIO */ +MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1) +MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1) /* MPUIO */ MUX_CFG("MPUIO2", 7, 18, 0, 1, 1, 1, NA, 0, 1) @@ -408,6 +432,7 @@ MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1) MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1) MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1) MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1) +MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1) /* OMAP-1610 uWire */ MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1) @@ -417,13 +442,16 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1) MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1) -/* First MMC interface, same on 1510 and 1610 */ +/* First MMC interface, same on 1510, 1610 and 1710 */ MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1) MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1) MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1) MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1) MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1) MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1) +MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1) +MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1) +MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1) /* OMAP-1610 USB0 alternate configuration */ MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1) diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h index b13584662a6831..f491a48ef2e118 100644 --- a/include/asm-arm/arch-omap/omap1510.h +++ b/include/asm-arm/arch-omap/omap1510.h @@ -40,16 +40,6 @@ #define OMAP1510_SRAM_SIZE (SZ_128K + SZ_64K) #define OMAP1510_SRAM_START 0x20000000 -#define OMAP1510_MCBSP1_BASE 0xE1011000 -#define OMAP1510_MCBSP1_SIZE SZ_4K -#define OMAP1510_MCBSP1_START 0xE1011000 - -#define OMAP1510_MCBSP2_BASE 0xFFFB1000 - -#define OMAP1510_MCBSP3_BASE 0xE1017000 -#define OMAP1510_MCBSP3_SIZE SZ_4K -#define OMAP1510_MCBSP3_START 0xE1017000 - #define OMAP1510_DSP_BASE 0xE0000000 #define OMAP1510_DSP_SIZE 0x28000 #define OMAP1510_DSP_START 0xE0000000 @@ -58,5 +48,14 @@ #define OMAP1510_DSPREG_SIZE SZ_128K #define OMAP1510_DSPREG_START 0xE1000000 +/* + * ---------------------------------------------------------------------------- + * Memory used by power management + * ---------------------------------------------------------------------------- + */ + +#define OMAP1510_SRAM_IDLE_SUSPEND (OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200) +#define OMAP1510_SRAM_API_SUSPEND (OMAP1510_SRAM_IDLE_SUSPEND + 0x100) + #endif /* __ASM_ARCH_OMAP1510_H */ diff --git a/include/asm-arm/arch-omap/omap1610.h b/include/asm-arm/arch-omap/omap1610.h index 667a6f697c1105..6b36752f415080 100644 --- a/include/asm-arm/arch-omap/omap1610.h +++ b/include/asm-arm/arch-omap/omap1610.h @@ -49,6 +49,15 @@ #define OMAP1610_DSPREG_START 0xE1000000 /* + * ---------------------------------------------------------------------------- + * Memory used by power management + * ---------------------------------------------------------------------------- + */ + +#define OMAP1610_SRAM_IDLE_SUSPEND (OMAP1610_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200) +#define OMAP1610_SRAM_API_SUSPEND (OMAP1610_SRAM_IDLE_SUSPEND + 0x100) + +/* * --------------------------------------------------------------------------- * Interrupts * --------------------------------------------------------------------------- diff --git a/include/asm-arm/arch-omap/omap5912.h b/include/asm-arm/arch-omap/omap5912.h index f996af7c185b69..76b554ee02364d 100644 --- a/include/asm-arm/arch-omap/omap5912.h +++ b/include/asm-arm/arch-omap/omap5912.h @@ -50,6 +50,15 @@ #define OMAP5912_DSPREG_START 0xE1000000 /* + * ---------------------------------------------------------------------------- + * Memory used by power management + * ---------------------------------------------------------------------------- + */ + +#define OMAP5912_SRAM_IDLE_SUSPEND (OMAP5912_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200) +#define OMAP5912_SRAM_API_SUSPEND (OMAP5912_SRAM_IDLE_SUSPEND + 0x100) + +/* * --------------------------------------------------------------------------- * Interrupts * --------------------------------------------------------------------------- diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h index 8ca76368729504..599ab00f5488a5 100644 --- a/include/asm-arm/arch-omap/omap730.h +++ b/include/asm-arm/arch-omap/omap730.h @@ -40,12 +40,6 @@ #define OMAP730_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K) #define OMAP730_SRAM_START 0x20000000 -#define OMAP730_MCBSP1_BASE 0xfffb1000 -#define OMAP730_MCBSP1_SIZE (SZ_1K * 2) -#define OMAP730_MCBSP1_START 0xfffb1000 - -#define OMAP730_MCBSP2_BASE 0xfffb1800 - #define OMAP730_DSP_BASE 0xE0000000 #define OMAP730_DSP_SIZE 0x50000 #define OMAP730_DSP_START 0xE0000000 diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h new file mode 100644 index 00000000000000..0f97bb2e8fcef9 --- /dev/null +++ b/include/asm-arm/arch-omap/tps65010.h @@ -0,0 +1,80 @@ +/* linux/include/asm-arm/arch-omap/tps65010.h + * + * Functions to access TPS65010 power management device. + * + * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_TPS65010_H +#define __ASM_ARCH_TPS65010_H + +/* + * ---------------------------------------------------------------------------- + * Macros used by exported functions + * ---------------------------------------------------------------------------- + */ + +#define LED1 1 +#define LED2 2 +#define OFF 0 +#define ON 1 +#define BLINK 2 +#define GPIO1 1 +#define GPIO2 2 +#define GPIO3 3 +#define GPIO4 4 +#define LOW 0 +#define HIGH 1 + +/* + * ---------------------------------------------------------------------------- + * Exported functions + * ---------------------------------------------------------------------------- + */ + +/* Draw from VBUS: + * 0 mA -- DON'T DRAW (might supply power instead) + * 100 mA -- usb unit load (slowest charge rate) + * 500 mA -- usb high power (fast battery charge) + */ +extern int tps65010_set_vbus_draw(unsigned mA); + +/* tps65010_set_gpio_out_value parameter: + * gpio: GPIO1, GPIO2, GPIO3 or GPIO4 + * value: LOW or HIGH + */ +extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value); + +/* tps65010_set_led parameter: + * led: LED1 or LED2 + * mode: ON, OFF or BLINK + */ +extern int tps65010_set_led(unsigned led, unsigned mode); + +/* tps65010_set_low_pwr parameter: + * mode: ON or OFF + */ +extern int tps65010_set_low_pwr(unsigned mode); + +#endif /* __ASM_ARCH_TPS65010_H */ + diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h new file mode 100644 index 00000000000000..1438c6cef0caa1 --- /dev/null +++ b/include/asm-arm/arch-omap/usb.h @@ -0,0 +1,108 @@ +// include/asm-arm/mach-omap/usb.h + +#ifndef __ASM_ARCH_OMAP_USB_H +#define __ASM_ARCH_OMAP_USB_H + +#include <asm/arch/board.h> + +/*-------------------------------------------------------------------------*/ + +#define OTG_BASE 0xfffb0400 +#define UDC_BASE 0xfffb4000 +#define OMAP_OHCI_BASE 0xfffba000 + +/*-------------------------------------------------------------------------*/ + +/* + * OTG and transceiver registers, for OMAPs starting with ARM926 + */ +#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) +#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) + +#define OTG_REV_REG OTG_REG32(0x00) +#define OTG_SYSCON_1_REG OTG_REG32(0x04) +# define USB2_TRX_MODE(w) (((w)>>24)&0x07) +# define USB1_TRX_MODE(w) (((w)>>20)&0x07) +# define USB0_TRX_MODE(w) (((w)>>16)&0x07) +# define OTG_IDLE_EN (1 << 15) +# define HST_IDLE_EN (1 << 14) +# define DEV_IDLE_EN (1 << 13) +# define OTG_RESET_DONE (1 << 2) +#define OTG_SYSCON_2_REG OTG_REG32(0x08) +# define OTG_EN (1 << 31) +# define USBX_SYNCHRO (1 << 30) +# define OTG_MST16 (1 << 29) +# define SRP_GPDATA (1 << 28) +# define SRP_GPDVBUS (1 << 27) +# define SRP_GPUVBUS(w) (((w)>>24)&0x07) +# define A_WAIT_VRISE(w) (((w)>>20)&0x07) +# define B_ASE_BRST(w) (((w)>>16)&0x07) +# define SRP_DPW (1 << 14) +# define SRP_DATA (1 << 13) +# define SRP_VBUS (1 << 12) +# define OTG_PADEN (1 << 10) +# define HMC_PADEN (1 << 9) +# define UHOST_EN (1 << 8) +# define HMC_TLLSPEED (1 << 7) +# define HMC_TLLATTACH (1 << 6) +# define OTG_HMC(w) (((w)>>0)&0x3f) +#define OTG_CTRL_REG OTG_REG32(0x0c) +# define OTG_ASESSVLD (1 << 20) +# define OTG_BSESSEND (1 << 19) +# define OTG_BSESSVLD (1 << 18) +# define OTG_VBUSVLD (1 << 17) +# define OTG_ID (1 << 16) +# define OTG_DRIVER_SEL (1 << 15) +# define OTG_A_SETB_HNPEN (1 << 12) +# define OTG_A_BUSREQ (1 << 11) +# define OTG_B_HNPEN (1 << 9) +# define OTG_B_BUSREQ (1 << 8) +# define OTG_BUSDROP (1 << 7) +# define OTG_PULLDOWN (1 << 5) +# define OTG_PULLUP (1 << 4) +# define OTG_DRV_VBUS (1 << 3) +# define OTG_PD_VBUS (1 << 2) +# define OTG_PU_VBUS (1 << 1) +# define OTG_PU_ID (1 << 0) +#define OTG_IRQ_EN_REG OTG_REG16(0x10) +# define DRIVER_SWITCH (1 << 15) +# define A_VBUS_ERR (1 << 13) +# define A_REQ_TMROUT (1 << 12) +# define A_SRP_DETECT (1 << 11) +# define B_HNP_FAIL (1 << 10) +# define B_SRP_TMROUT (1 << 9) +# define B_SRP_DONE (1 << 8) +# define B_SRP_STARTED (1 << 7) +# define OPRT_CHG (1 << 0) +#define OTG_IRQ_SRC_REG OTG_REG16(0x14) + // same bits as in IRQ_EN +#define OTG_OUTCTRL_REG OTG_REG16(0x18) +# define OTGVPD (1 << 14) +# define OTGVPU (1 << 13) +# define OTGPUID (1 << 12) +# define USB2VDR (1 << 10) +# define USB2PDEN (1 << 9) +# define USB2PUEN (1 << 8) +# define USB1VDR (1 << 6) +# define USB1PDEN (1 << 5) +# define USB1PUEN (1 << 4) +# define USB0VDR (1 << 2) +# define USB0PDEN (1 << 1) +# define USB0PUEN (1 << 0) +#define OTG_TEST_REG OTG_REG16(0x20) +#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) + +/*-------------------------------------------------------------------------*/ + +#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) +# define CONF_USB2_UNI_R (1 << 8) +# define CONF_USB1_UNI_R (1 << 7) +# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) +# define CONF_USB0_ISOLATE_R (1 << 3) +# define CONF_USB_PWRDN_DM_R (1 << 2) +# define CONF_USB_PWRDN_DP_R (1 << 1) + + + + +#endif /* __ASM_ARCH_OMAP_USB_H */ diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index df4bc662850e8d..56db3d49bfc813 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -22,7 +22,7 @@ * Note: this structure must always be aligned to a 16-byte boundary. */ -typedef struct { +typedef struct pxa_dma_desc { volatile u32 ddadr; /* Points to the next descriptor + flags */ volatile u32 dsadr; /* DSADR value for the current transfer */ volatile u32 dtadr; /* DTADR value for the current transfer */ diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h index ea084c784b25b7..9cae3822a4840e 100644 --- a/include/asm-arm/arch-s3c2410/dma.h +++ b/include/asm-arm/arch-s3c2410/dma.h @@ -27,7 +27,7 @@ * */ #define MAX_DMA_ADDRESS 0x20000000 -#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ +#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ /* according to the samsung port, we cannot use the regular @@ -39,131 +39,282 @@ /* we have 4 dma channels */ -#define S3C2410_DMA_CHANNELS (4) +#define S3C2410_DMA_CHANNELS (4) +/* types */ + +typedef enum { + S3C2410_DMA_IDLE, + S3C2410_DMA_RUNNING, + S3C2410_DMA_PAUSED +} s3c2410_dma_state_t; + + +/* s3c2410_dma_loadst_t + * + * This represents the state of the DMA engine, wrt to the loaded / running + * transfers. Since we don't have any way of knowing exactly the state of + * the DMA transfers, we need to know the state to make decisions on wether + * we can + * + * S3C2410_DMA_NONE + * + * There are no buffers loaded (the channel should be inactive) + * + * S3C2410_DMA_1LOADED + * + * There is one buffer loaded, however it has not been confirmed to be + * loaded by the DMA engine. This may be because the channel is not + * yet running, or the DMA driver decided that it was too costly to + * sit and wait for it to happen. + * + * S3C2410_DMA_1RUNNING + * + * The buffer has been confirmed running, and not finisged + * + * S3C2410_DMA_1LOADED_1RUNNING + * + * There is a buffer waiting to be loaded by the DMA engine, and one + * currently running. +*/ + +typedef enum { + S3C2410_DMALOAD_NONE, + S3C2410_DMALOAD_1LOADED, + S3C2410_DMALOAD_1RUNNING, + S3C2410_DMALOAD_1LOADED_1RUNNING, +} s3c2410_dma_loadst_t; + +typedef enum { + S3C2410_RES_OK, + S3C2410_RES_ERR, + S3C2410_RES_ABORT +} s3c2410_dma_buffresult_t; + + +typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t; + +enum s3c2410_dmasrc_e { + S3C2410_DMASRC_HW, /* source is memory */ + S3C2410_DMASRC_MEM /* source is hardware */ +}; + +/* enum s3c2410_chan_op_e + * + * operation codes passed to the DMA code by the user, and also used + * to inform the current channel owner of any changes to the system state +*/ + +enum s3c2410_chan_op_e { + S3C2410_DMAOP_START, + S3C2410_DMAOP_STOP, + S3C2410_DMAOP_PAUSE, + S3C2410_DMAOP_RESUME, + S3C2410_DMAOP_FLUSH, + S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ +}; + +typedef enum s3c2410_chan_op_e s3c2410_chan_op_t; + +/* flags */ + +#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about + * waiting for reloads */ +#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ /* dma buffer */ typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t; +struct s3c2410_dma_client { + char *name; +}; + +typedef struct s3c2410_dma_client s3c2410_dma_client_t; + +/* s3c2410_dma_buf_s + * + * internally used buffer structure to describe a queued or running + * buffer. +*/ + struct s3c2410_dma_buf_s { s3c2410_dma_buf_t *next; - int magic; /* magic */ - int size; /* buffer size in bytes */ - dma_addr_t data; /* start of DMA data */ - dma_addr_t ptr; /* where the DMA got to [1] */ - int ref; - void *id; /* client's id */ - unsigned char no_callback; /* disable callback for buffer */ + int magic; /* magic */ + int size; /* buffer size in bytes */ + dma_addr_t data; /* start of DMA data */ + dma_addr_t ptr; /* where the DMA got to [1] */ + void *id; /* client's id */ }; /* [1] is this updated for both recv/send modes? */ typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; -typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size); -typedef void (*s3c2410_dma_enfn_t)(s3c2410_dma_chan_t *, int on); -typedef void (*s3c2410_dma_pausefn_t)(s3c2410_dma_chan_t *, int on); +/* s3c2410_dma_cbfn_t + * + * buffer callback routine type +*/ + +typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, + s3c2410_dma_buffresult_t result); + +typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, + s3c2410_chan_op_t ); + +struct s3c2410_dma_stats_s { + unsigned long loads; + unsigned long timeout_longest; + unsigned long timeout_shortest; + unsigned long timeout_avg; + unsigned long timeout_failed; +}; + +typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; + +/* struct s3c2410_dma_chan_s + * + * full state information for each DMA channel +*/ struct s3c2410_dma_chan_s { - /* channel state flags */ - unsigned char number; /* number of this dma channel */ - unsigned char in_use; /* channel allocated */ - unsigned char started; /* channel has been started */ - unsigned char stopped; /* channel stopped */ - unsigned char sleeping; - unsigned char xfer_unit; /* size of an transfer */ - unsigned char irq_claimed; + /* channel state flags and information */ + unsigned char number; /* number of this dma channel */ + unsigned char in_use; /* channel allocated */ + unsigned char irq_claimed; /* irq claimed for channel */ + unsigned char irq_enabled; /* irq enabled for channel */ + unsigned char xfer_unit; /* size of an transfer */ + + /* channel state */ + + s3c2410_dma_state_t state; + s3c2410_dma_loadst_t load_state; + s3c2410_dma_client_t *client; + + /* channel configuration */ + s3c2410_dmasrc_t source; + unsigned long dev_addr; + unsigned long load_timeout; + unsigned int flags; /* channel flags */ /* channel's hardware position and configuration */ - unsigned long regs; /* channels registers */ - unsigned int irq; /* channel irq */ - unsigned long addr_reg; /* data address register for buffs */ - unsigned long dcon; /* default value of DCON */ + unsigned long regs; /* channels registers */ + unsigned int irq; /* channel irq */ + unsigned long addr_reg; /* data address register */ + unsigned long dcon; /* default value of DCON */ - /* driver handlers for channel */ - s3c2410_dma_cbfn_t callback_fn; /* callback function for buf-done */ - s3c2410_dma_enfn_t enable_fn; /* channel enable function */ - s3c2410_dma_pausefn_t pause_fn; /* channel pause function */ + /* driver handles */ + s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ + s3c2410_dma_opfn_t op_fn; /* channel operation callback */ - /* buffer list and information */ - s3c2410_dma_buf_t *curr; /* current dma buffer */ - s3c2410_dma_buf_t *next; /* next buffer to load */ - s3c2410_dma_buf_t *end; /* end of queue */ + /* stats gathering */ + s3c2410_dma_stats_t *stats; + s3c2410_dma_stats_t stats_store; - int queue_count; /* number of items in queue */ - int loaded_count; /* number of loaded buffers */ + /* buffer list and information */ + s3c2410_dma_buf_t *curr; /* current dma buffer */ + s3c2410_dma_buf_t *next; /* next buffer to load */ + s3c2410_dma_buf_t *end; /* end of queue */ }; -/* note, we don't really use dma_deivce_t at the moment */ +/* the currently allocated channel information */ +extern s3c2410_dma_chan_t s3c2410_chans[]; + +/* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; -typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t; +/* functions --------------------------------------------------------------- */ -/* these two defines control the source for the dma channel, - * wether it is from memory or an device +/* s3c2410_dma_request + * + * request a dma channel exclusivley */ -enum s3c2410_dmasrc_e { - S3C2410_DMASRC_HW, /* source is memory */ - S3C2410_DMASRC_MEM /* source is hardware */ -}; +extern int s3c2410_dma_request(dmach_t channel, + s3c2410_dma_client_t *, void *dev); + + +/* s3c2410_dma_ctrl + * + * change the state of the dma channel +*/ + +extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); + +/* s3c2410_dma_setflags + * + * set the channel's flags to a given state +*/ -/* dma control routines */ +extern int s3c2410_dma_setflags(dmach_t channel, + unsigned int flags); -extern int s3c2410_request_dma(dmach_t channel, const char *devid, void *dev); -extern int s3c2410_free_dma(dmach_t channel); -extern int s3c2410_dma_flush_all(dmach_t channel); +/* s3c2410_dma_free + * + * free the dma channel (will also abort any outstanding operations) +*/ -extern int s3c2410_dma_stop(dmach_t channel); -extern int s3c2410_dma_resume(dmach_t channel); +extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); -extern int s3c2410_dma_queue(dmach_t channel, void *id, - dma_addr_t data, int size); +/* s3c2410_dma_enqueue + * + * place the given buffer onto the queue of operations for the channel. + * The buffer must be allocated from dma coherent memory, or the Dcache/WB + * drained before the buffer is given to the DMA system. +*/ -#define s3c2410_dma_queue_buffer s3c2410_dma_queue +extern int s3c2410_dma_enqueue(dmach_t channel, void *id, + dma_addr_t data, int size); -/* channel configuration */ +/* s3c2410_dma_config + * + * configure the dma channel +*/ extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); +/* s3c2410_dma_devconfig + * + * configure the device we're talking to +*/ + extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, int hwcfg, unsigned long devaddr); -extern int s3c2410_dma_set_enablefn(dmach_t, s3c2410_dma_enfn_t rtn); -extern int s3c2410_dma_set_pausefn(dmach_t, s3c2410_dma_pausefn_t rtn); -extern int s3c2410_dma_set_callbackfn(dmach_t, s3c2410_dma_cbfn_t rtn); +extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); +extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); -#define s3c2410_dma_set_callback s3c2410_dma_set_callbackfn +/* DMA Register definitions */ -#define S3C2410_DMA_DISRC (0x00) -#define S3C2410_DMA_DISRCC (0x04) -#define S3C2410_DMA_DIDST (0x08) -#define S3C2410_DMA_DIDSTC (0x0C) -#define S3C2410_DMA_DCON (0x10) -#define S3C2410_DMA_DSTAT (0x14) -#define S3C2410_DMA_DCSRC (0x18) -#define S3C2410_DMA_DCDST (0x1C) -#define S3C2410_DMA_DMASKTRIG (0x20) +#define S3C2410_DMA_DISRC (0x00) +#define S3C2410_DMA_DISRCC (0x04) +#define S3C2410_DMA_DIDST (0x08) +#define S3C2410_DMA_DIDSTC (0x0C) +#define S3C2410_DMA_DCON (0x10) +#define S3C2410_DMA_DSTAT (0x14) +#define S3C2410_DMA_DCSRC (0x18) +#define S3C2410_DMA_DCDST (0x1C) +#define S3C2410_DMA_DMASKTRIG (0x20) -#define S3C2410_DMASKTRIG_STOP (1<<2) -#define S3C2410_DMASKTRIG_ON (1<<1) +#define S3C2410_DMASKTRIG_STOP (1<<2) +#define S3C2410_DMASKTRIG_ON (1<<1) #define S3C2410_DMASKTRIG_SWTRIG (1<<0) -#define S3C2410_DCOM_DEMAND (0<<31) +#define S3C2410_DCOM_DEMAND (0<<31) #define S3C2410_DCON_HANDSHAKE (1<<31) #define S3C2410_DCON_SYNC_PCLK (0<<30) #define S3C2410_DCON_SYNC_HCLK (1<<30) -#define S3C2410_DCON_INTREQ (1<<29) +#define S3C2410_DCON_INTREQ (1<<29) -#define S3C2410_DCON_SRCSHIFT (24) +#define S3C2410_DCON_SRCSHIFT (24) -#define S3C2410_DCON_BYTE (0<<20) -#define S3C2410_DCON_HALFWORD (1<<20) -#define S3C2410_DCON_WORD (2<<20) +#define S3C2410_DCON_BYTE (0<<20) +#define S3C2410_DCON_HALFWORD (1<<20) +#define S3C2410_DCON_WORD (2<<20) #define S3C2410_DCON_AUTORELOAD (0<<22) -#define S3C2410_DCON_HWTRIG (1<<23) +#define S3C2410_DCON_NORELOAD (1<<22) +#define S3C2410_DCON_HWTRIG (1<<23) #endif /* __ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index a82d55cc6f08a9..f3f090525d052d 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h @@ -1,6 +1,6 @@ /* linux/include/asm/arch-s3c2410/regs-clock.h * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> + * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> * http://www.simtec.co.uk/products/SWLINUX/ * * This program is free software; you can redistribute it and/or modify @@ -10,8 +10,9 @@ * S3C2410 clock register definitions * * Changelog: - * 19-06-2003 BJD Created file - * 12-03-2004 BJD Updated include protection + * 08-Aug-2004 Herbert Pötzl Added CLKCON definitions + * 19-06-2003 Ben Dooks Created file + * 12-03-2004 Ben Dooks Updated include protection */ @@ -30,6 +31,24 @@ #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) +#define S3C2410_CLKCON_IDLE (1<<2) +#define S3C2410_CLKCON_POWER (1<<3) +#define S3C2410_CLKCON_NAND (1<<4) +#define S3C2410_CLKCON_LCDC (1<<5) +#define S3C2410_CLKCON_USBH (1<<6) +#define S3C2410_CLKCON_USBD (1<<7) +#define S3C2410_CLKCON_PWMT (1<<8) +#define S3C2410_CLKCON_SDI (1<<9) +#define S3C2410_CLKCON_UART0 (1<<10) +#define S3C2410_CLKCON_UART1 (1<<11) +#define S3C2410_CLKCON_UART2 (1<<12) +#define S3C2410_CLKCON_GPIO (1<<13) +#define S3C2410_CLKCON_RTC (1<<14) +#define S3C2410_CLKCON_ADC (1<<15) +#define S3C2410_CLKCON_IIC (1<<16) +#define S3C2410_CLKCON_IIS (1<<17) +#define S3C2410_CLKCON_SPI (1<<18) + #define S3C2410_PLLCON_MDIVSHIFT 12 #define S3C2410_PLLCON_PDIVSHIFT 4 #define S3C2410_PLLCON_SDIVSHIFT 0 diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h index b67e06c0f588e4..29533be8be619e 100644 --- a/include/asm-arm/elf.h +++ b/include/asm-arm/elf.h @@ -1,6 +1,8 @@ #ifndef __ASMARM_ELF_H #define __ASMARM_ELF_H +#include <linux/config.h> + /* * ELF register definitions.. */ @@ -14,6 +16,7 @@ typedef unsigned long elf_freg_t[3]; #define EM_ARM 40 #define EF_ARM_APCS26 0x08 +#define EF_ARM_SOFT_FLOAT 0x200 #define R_ARM_NONE 0 #define R_ARM_PC24 1 @@ -91,6 +94,8 @@ extern char elf_platform[]; (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \ ((x)->e_flags & EF_ARM_APCS26) == 0) +#ifndef CONFIG_IWMMXT + /* Old NetWinder binaries were compiled in such a way that the iBCS heuristic always trips on them. Until these binaries become uncommon enough not to care, don't trust the `ibcs' flag here. In any case @@ -99,6 +104,28 @@ extern char elf_platform[]; #define SET_PERSONALITY(ex,ibcs2) \ set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT)) +#else + +/* + * All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run + * legacy binaries which used to contain FPA11 floating point instructions + * that have always been emulated by the kernel. PFA11 and iWMMXt overlap + * on coprocessor 1 space though. We therefore must decide if given task + * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked + * at all times for the prefetch exception handler to catch FPA11 opcodes + * and emulate them. The best indication to discriminate those two cases + * is the SOFT_FLOAT flag in the ELF header. + */ + +#define SET_PERSONALITY(ex,ibcs2) \ +do { \ + set_personality(PER_LINUX_32BIT); \ + if ((ex).e_flags & EF_ARM_SOFT_FLOAT) \ + set_thread_flag(TIF_USING_IWMMXT); \ +} while (0) + +#endif + #endif #endif diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h index 7492cfa21f7a57..f7430e3aa55d2e 100644 --- a/include/asm-arm/fpstate.h +++ b/include/asm-arm/fpstate.h @@ -11,7 +11,7 @@ #ifndef __ASM_ARM_FPSTATE_H #define __ASM_ARM_FPSTATE_H -#define FP_SIZE 35 +#include <linux/config.h> #ifndef __ASSEMBLY__ @@ -43,19 +43,32 @@ union vfp_state { extern void vfp_flush_thread(union vfp_state *); extern void vfp_release_thread(union vfp_state *); +#define FP_HARD_SIZE 35 + struct fp_hard_struct { - unsigned int save[FP_SIZE]; /* as yet undefined */ + unsigned int save[FP_HARD_SIZE]; /* as yet undefined */ }; +#define FP_SOFT_SIZE 35 + struct fp_soft_struct { - unsigned int save[FP_SIZE]; /* undefined information */ + unsigned int save[FP_SOFT_SIZE]; /* undefined information */ +}; + +struct iwmmxt_struct { + unsigned int save[0x98/sizeof(int) + 1]; }; union fp_state { struct fp_hard_struct hard; struct fp_soft_struct soft; +#ifdef CONFIG_IWMMXT + struct iwmmxt_struct iwmmxt; +#endif }; +#define FP_SIZE (sizeof(union fp_state) / sizeof(int)) + #endif #endif diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h index 283dde118b20db..1fd1a5b6504ba9 100644 --- a/include/asm-arm/hardware.h +++ b/include/asm-arm/hardware.h @@ -15,13 +15,4 @@ #include <asm/arch/hardware.h> -#ifndef __ASSEMBLY__ - -struct platform_device; - -extern int platform_add_devices(struct platform_device **, int); -extern int platform_add_device(struct platform_device *); - -#endif - #endif diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 93aa555cfa05ea..1855fb73c4d579 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -271,10 +271,12 @@ extern void __iounmap(void *addr); #ifndef __arch_ioremap #define ioremap(cookie,size) __ioremap(cookie,size,0,1) #define ioremap_nocache(cookie,size) __ioremap(cookie,size,0,1) +#define ioremap_cached(cookie,size) __ioremap(cookie,size,L_PTE_CACHEABLE,1) #define iounmap(cookie) __iounmap(cookie) #else #define ioremap(cookie,size) __arch_ioremap((cookie),(size),0,1) #define ioremap_nocache(cookie,size) __arch_ioremap((cookie),(size),0,1) +#define ioremap_cached(cookie,size) __arch_ioremap((cookie),(size),L_PTE_CACHEABLE,1) #define iounmap(cookie) __arch_iounmap(cookie) #endif diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h index ea0b992eebc230..8fe094f256c4f1 100644 --- a/include/asm-arm/mach/pci.h +++ b/include/asm-arm/mach/pci.h @@ -52,10 +52,6 @@ void pci_common_init(struct hw_pci *); /* * PCI controllers */ -extern int iop310_setup(int nr, struct pci_sys_data *); -extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *); -extern void iop310_init(void); - extern int iop321_setup(int nr, struct pci_sys_data *); extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *); extern void iop321_init(void); diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 41f117fb5e9f85..237862bf656863 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -108,10 +108,18 @@ static inline void *phys_to_virt(unsigned long x) /* * Virtual <-> DMA view memory address translations * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *deprecated*. + * memory. Use of these is *deprecated* (and that doesn't mean + * use the __ prefixed forms instead.) See dma-mapping.h. */ -#define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) -#define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) +static inline __deprecated unsigned long virt_to_bus(void *x) +{ + return __virt_to_bus((unsigned long)x); +} + +static inline __deprecated void *bus_to_virt(unsigned long x) +{ + return (void *)__bus_to_virt(x); +} /* * Conversion between a struct page and a physical address. @@ -177,9 +185,9 @@ static inline void *phys_to_virt(unsigned long x) * We should really eliminate virt_to_bus() here - it's deprecated. */ #ifndef __arch_page_to_dma -#define page_to_dma(dev, page) ((dma_addr_t)__virt_to_bus(page_address(page))) +#define page_to_dma(dev, page) ((dma_addr_t)__virt_to_bus((unsigned long)page_address(page))) #define dma_to_virt(dev, addr) (__bus_to_virt(addr)) -#define virt_to_dma(dev, addr) (__virt_to_bus(addr)) +#define virt_to_dma(dev, addr) (__virt_to_bus((unsigned long)(addr))) #else #define page_to_dma(dev, page) (__arch_page_to_dma(dev, page)) #define dma_to_virt(dev, addr) (__arch_dma_to_virt(dev, addr)) diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h index b3ef76481942aa..1a362ca4147601 100644 --- a/include/asm-arm/thread_info.h +++ b/include/asm-arm/thread_info.h @@ -100,23 +100,18 @@ extern void free_thread_info(struct thread_info *); #define thread_saved_fp(tsk) \ ((unsigned long)((tsk)->thread_info->cpu_context.fp)) -#else /* !__ASSEMBLY__ */ - -#define TI_FLAGS 0 -#define TI_PREEMPT 4 -#define TI_ADDR_LIMIT 8 -#define TI_TASK 12 -#define TI_EXEC_DOMAIN 16 -#define TI_CPU 20 -#define TI_CPU_DOMAIN 24 -#define TI_CPU_SAVE 28 -#define TI_USED_CP 76 -#define TI_FPSTATE (TI_USED_CP+16) -#define TI_VFPSTATE (TI_FPSTATE+FP_SIZE*4) +extern void iwmmxt_task_disable(struct thread_info *); +extern void iwmmxt_task_copy(struct thread_info *, void *); +extern void iwmmxt_task_restore(struct thread_info *, void *); +extern void iwmmxt_task_release(struct thread_info *); #endif -#define PREEMPT_ACTIVE 0x04000000 +/* + * We use bit 30 of the preempt_count to indicate that kernel + * preemption is occuring. See include/asm-arm/hardirq.h. + */ +#define PREEMPT_ACTIVE 0x40000000 /* * thread information flags: @@ -131,15 +126,15 @@ extern void free_thread_info(struct thread_info *); #define TIF_SIGPENDING 1 #define TIF_NEED_RESCHED 2 #define TIF_SYSCALL_TRACE 8 -#define TIF_USED_FPU 16 -#define TIF_POLLING_NRFLAG 17 +#define TIF_POLLING_NRFLAG 16 +#define TIF_USING_IWMMXT 17 #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_USED_FPU (1 << TIF_USED_FPU) #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) +#define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) /* * Change these and you break ASM code in entry-common.S |