[PATCH] PA-RISC update

 - __PAGE_OFFSET is 0x10000000 (Randolph Chung)
 - PA8800 support (Grant Grundler)
 - debuglocks (Thibaut Varene)
 - PDC chassis disabling (Thibaut Varene)
 - Distinguish between Dinos in request_irq (Thibaut Varene)
 - Document interrupt registers (Randolph Chung)
 - Revamp CONFIG_DISCONTIGMEM support (Randolph Chung)
 - Remove STI console warning and special casing (Randolph Chung)
 - n4000 defconfig (Randolph Chung)
 - iosapic fixes (Bjorn Helgaas)
 - Fix a bug in entry.S where pa_dbit_lock was being trashed (Randolph Chung)
 - SMP support (Randolph Chung, Grant Grundler, James Bottomley)
 - Clear the pte in the fault handler (Joel Soete)
 - Change _exit prototype (Carlos O'Donell)
 - Better unwinding support (Randolph Chung)
 - GCC 3.4 fixes (Carlos O'Donell, Randolph Chung)

7 files changed, 482 insertions, 200 deletions

diff --git a/drivers/parisc/dino.c b/drivers/parisc/dino.c
index a9ca3c25c35158..5840219f6efd72 100644
--- a/drivers/parisc/dino.c
+++ b/drivers/parisc/dino.c
@@ -932,13 +932,16 @@ dino_driver_callback(struct parisc_device *dev)
 	struct dino_device *dino_dev;	// Dino specific control struct
 	const char *version = "unknown";
 	const int name_len = 32;
+	char hw_path[64];
 	char *name;
 	int is_cujo = 0;
 	struct pci_bus *bus;
-
+	
 	name = kmalloc(name_len, GFP_KERNEL);
-	if(name)
-		snprintf(name, name_len, "Dino %s", dev->dev.bus_id);
+	if(name) {
+		print_pa_hwpath(dev, hw_path);
+		snprintf(name, name_len, "Dino [%s]", hw_path);
+	} 
 	else
 		name = "Dino";
 
diff --git a/drivers/parisc/iommu-helpers.h b/drivers/parisc/iommu-helpers.h
index a6757b3bbf00ad..38d9e1aba1d0f5 100644
--- a/drivers/parisc/iommu-helpers.h
+++ b/drivers/parisc/iommu-helpers.h
@@ -49,7 +49,15 @@ iommu_fill_pdir(struct ioc *ioc, struct scatterlist *startsg, int nents,
 			sg_dma_len(startsg) = 0;
 			dma_offset = (unsigned long) pide & ~IOVP_MASK;
 			n_mappings++;
+#if defined(ZX1_SUPPORT)
+			/* Pluto IOMMU IO Virt Address is not zero based */
+			sg_dma_address(dma_sg) = pide | ioc->ibase;
+#else
+			/* SBA, ccio, and dino are zero based.
+			 * Trying to save a few CPU cycles for most users.
+			 */
 			sg_dma_address(dma_sg) = pide;
+#endif
 			pdirp = &(ioc->pdir_base[pide >> IOVP_SHIFT]);
 			prefetchw(pdirp);
 		}
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index 60466bd12a293c..33bff2ea9a8791 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -169,10 +169,11 @@
 
 #include <asm/byteorder.h>	/* get in-line asm for swab */
 #include <asm/pdc.h>
+#include <asm/pdcpat.h>
 #include <asm/page.h>
 #include <asm/segment.h>
 #include <asm/system.h>
-#include <asm/io.h>		/* gsc_read/write functions */
+#include <asm/io.h>		/* read/write functions */
 #ifdef CONFIG_SUPERIO
 #include <asm/superio.h>
 #endif
@@ -223,19 +224,7 @@ assert_failed (char *a, char *f, int l)
 #endif
 
 
-#define READ_U8(addr)  gsc_readb(addr)
-#define READ_U16(addr) le16_to_cpu(gsc_readw((u16 *) (addr)))
-#define READ_U32(addr) le32_to_cpu(gsc_readl((u32 *) (addr)))
-#define READ_REG16(addr) gsc_readw((u16 *) (addr))
-#define READ_REG32(addr) gsc_readl((u32 *) (addr))
-#define WRITE_U8(value, addr) gsc_writeb(value, addr)
-#define WRITE_U16(value, addr) gsc_writew(cpu_to_le16(value), (u16 *) (addr))
-#define WRITE_U32(value, addr) gsc_writel(cpu_to_le32(value), (u32 *) (addr))
-#define WRITE_REG16(value, addr) gsc_writew(value, (u16 *) (addr))
-#define WRITE_REG32(value, addr) gsc_writel(value, (u32 *) (addr))
-
-
-#define IOSAPIC_REG_SELECT              0
+#define IOSAPIC_REG_SELECT              0x00
 #define IOSAPIC_REG_WINDOW              0x10
 #define IOSAPIC_REG_EOI                 0x40
 
@@ -244,8 +233,19 @@ assert_failed (char *a, char *f, int l)
 #define IOSAPIC_IRDT_ENTRY(idx)		(0x10+(idx)*2)
 #define IOSAPIC_IRDT_ENTRY_HI(idx)	(0x11+(idx)*2)
 
+static inline unsigned int iosapic_read(unsigned long iosapic, unsigned int reg)
+{
+	writel(reg, iosapic + IOSAPIC_REG_SELECT);
+	return readl(iosapic + IOSAPIC_REG_WINDOW);
+}
+
+static inline void iosapic_write(unsigned long iosapic, unsigned int reg, u32 val)
+{
+	writel(reg, iosapic + IOSAPIC_REG_SELECT);
+	writel(val, iosapic + IOSAPIC_REG_WINDOW);
+}
+
 /*
-** FIXME: revisit which GFP flags we should really be using.
 **     GFP_KERNEL includes __GFP_WAIT flag and that may not
 **     be acceptable. Since this is boot time, we shouldn't have
 **     to wait ever and this code should (will?) never get called
@@ -260,16 +260,13 @@ assert_failed (char *a, char *f, int l)
 #define	IOSAPIC_UNLOCK(lck)	spin_unlock_irqrestore(lck, irqflags)
 
 
-#define IOSAPIC_VERSION_MASK            0x000000ff
-#define IOSAPIC_VERSION_SHIFT           0x0
-#define	IOSAPIC_VERSION(ver)				\
-		(int) ((ver & IOSAPIC_VERSION_MASK) >> IOSAPIC_VERSION_SHIFT)
+#define IOSAPIC_VERSION_MASK	0x000000ff
+#define	IOSAPIC_VERSION(ver)	((int) (ver & IOSAPIC_VERSION_MASK))
 
 #define IOSAPIC_MAX_ENTRY_MASK          0x00ff0000
-
 #define IOSAPIC_MAX_ENTRY_SHIFT         0x10
-#define	IOSAPIC_IRDT_MAX_ENTRY(ver)			\
-		(int) ((ver&IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
+#define	IOSAPIC_IRDT_MAX_ENTRY(ver)	\
+	(int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
 
 /* bits in the "low" I/O Sapic IRdT entry */
 #define IOSAPIC_IRDT_ENABLE       0x10000
@@ -281,9 +278,6 @@ assert_failed (char *a, char *f, int l)
 #define IOSAPIC_IRDT_ID_EID_SHIFT              0x10
 
 
-
-#define	IOSAPIC_EOI(eoi_addr, eoi_data) gsc_writel(eoi_data, eoi_addr)
-
 static struct iosapic_info *iosapic_list;
 static spinlock_t iosapic_lock;
 static int iosapic_count;
@@ -403,14 +397,14 @@ iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
 	struct irt_entry *p = table;
 	int i;
 
-	printk(KERN_DEBUG MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
-	printk(KERN_DEBUG MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
+	printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
+	printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
 		table,
 		num_entries,
 		(int) sizeof(struct irt_entry));
 
 	for (i = 0 ; i < num_entries ; i++, p++) {
-		printk(KERN_DEBUG MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
+		printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
 		p->entry_type, p->entry_length, p->interrupt_type,
 		p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
 		p->src_seg_id, p->dest_iosapic_intin,
@@ -608,22 +602,26 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
 static irqreturn_t
 iosapic_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 {
-	struct vector_info *vi = (struct vector_info *)dev_id;
+	struct vector_info *vi = (struct vector_info *) dev_id;
 	extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
 	int irq_num = vi->iosapic->isi_region->data.irqbase + vi->irqline;
 
-	DBG("iosapic_interrupt(): irq %d line %d eoi %p\n",
-		irq, vi->irqline, vi->eoi_addr);
+	DBG("iosapic_interrupt(): irq %d line %d eoi 0x%p 0x%x\n",
+		irq, vi->irqline, vi->eoi_addr, vi->eoi_data);
+
+	/* Do NOT need to mask/unmask IRQ. processor is already masked. */
 
-/* FIXME: Need to mask/unmask? processor IRQ is already masked... */
 	do_irq(&vi->iosapic->isi_region->action[vi->irqline], irq_num, regs);
 
 	/*
+	** PARISC only supports PCI devices below I/O SAPIC.
 	** PCI only supports level triggered in order to share IRQ lines.
-	** I/O SAPIC must always issue EOI.
+	** ergo I/O SAPIC must always issue EOI on parisc.
+	**
+	** i386/ia64 support ISA devices and have to deal with
+	** edge-triggered interrupts too.
 	*/
-	IOSAPIC_EOI(vi->eoi_addr, vi->eoi_data);
-
+	__raw_writel(vi->eoi_data, vi->eoi_addr);
 	return IRQ_HANDLED;
 }
 
@@ -715,8 +713,7 @@ iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
 	ASSERT(tmp == 0);
 
 	vi->eoi_addr = (u32 *) (isi->isi_hpa + IOSAPIC_REG_EOI);
-	vi->eoi_data = cpu_to_le32(vi->irqline);
-
+	vi->eoi_data = cpu_to_le32(vi->txn_data);
 	ASSERT(NULL != isi->isi_region);
 
 	DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
@@ -733,13 +730,8 @@ iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
 	struct iosapic_info *isp = vi->iosapic;
 	u8 idx = vi->irqline;
 
-	/* point the window register to the lower word */
-	WRITE_U32(IOSAPIC_IRDT_ENTRY(idx), isp->isi_hpa+IOSAPIC_REG_SELECT);
-	*dp0 = READ_U32(isp->isi_hpa+IOSAPIC_REG_WINDOW);
-
-	/* point the window register to the higher word */
-	WRITE_U32(IOSAPIC_IRDT_ENTRY_HI(idx), isp->isi_hpa+IOSAPIC_REG_SELECT);
-	*dp1 = READ_U32(isp->isi_hpa+IOSAPIC_REG_WINDOW);
+	*dp0 = iosapic_read(isp->isi_hpa, IOSAPIC_IRDT_ENTRY(idx));
+	*dp1 = iosapic_read(isp->isi_hpa, IOSAPIC_IRDT_ENTRY_HI(idx));
 }
 
 
@@ -750,24 +742,20 @@ iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
 
 	ASSERT(NULL != isp);
 	ASSERT(0 != isp->isi_hpa);
-	DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %p WINDOW %p  0x%x 0x%x\n",
+	DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %p 0x%x 0x%x\n",
 		vi->irqline,
-		isp->isi_hpa, isp->isi_hpa+IOSAPIC_REG_WINDOW,
+		isp->isi_hpa,
 		dp0, dp1);
 
-	/* point the window register to the lower word */
-	WRITE_U32(IOSAPIC_IRDT_ENTRY(vi->irqline), isp->isi_hpa+IOSAPIC_REG_SELECT);
-	WRITE_U32( dp0, isp->isi_hpa+IOSAPIC_REG_WINDOW);
+	iosapic_write(isp->isi_hpa, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
 
 	/* Read the window register to flush the writes down to HW  */
-	dp0 = READ_U32(isp->isi_hpa+IOSAPIC_REG_WINDOW);
+	dp0 = readl(isp->isi_hpa+IOSAPIC_REG_WINDOW);
 
-	/* point the window register to the higher word */
-	WRITE_U32(IOSAPIC_IRDT_ENTRY_HI(vi->irqline), isp->isi_hpa+IOSAPIC_REG_SELECT);
-	WRITE_U32( dp1, isp->isi_hpa+IOSAPIC_REG_WINDOW);
+	iosapic_write(isp->isi_hpa, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
 
 	/* Read the window register to flush the writes down to HW  */
-	dp1 = READ_U32(isp->isi_hpa+IOSAPIC_REG_WINDOW);
+	dp1 = readl(isp->isi_hpa+IOSAPIC_REG_WINDOW);
 }
 
 
@@ -882,12 +870,12 @@ iosapic_enable_irq(void *dev, int irq)
 	iosapic_set_irt_data(vi, &d0, &d1);
 	iosapic_wr_irt_entry(vi, d0, d1);
 
-
 #ifdef DEBUG_IOSAPIC_IRT
 {
 	u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
 	printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
-	while (t < vi->eoi_addr) printk(" %x", READ_U32(t++));
+	for ( ; t < vi->eoi_addr; t++)
+		printk(" %x", readl(t));
 	printk("\n");
 }
 
@@ -896,11 +884,7 @@ printk("iosapic_enable_irq(): sel ");
 	struct iosapic_info *isp = vi->iosapic;
 
 	for (d0=0x10; d0<0x1e; d0++) {
-		/* point the window register to the lower word */
-		WRITE_U32(d0, isp->isi_hpa+IOSAPIC_REG_SELECT);
-
-		/* read the word */
-		d1 = READ_U32(isp->isi_hpa+IOSAPIC_REG_WINDOW);
+		d1 = iosapic_read(isp->isi_hpa, d0);
 		printk(" %x", d1);
 	}
 }
@@ -908,13 +892,12 @@ printk("\n");
 #endif
 
 	/*
-	** KLUGE: IRQ should not be asserted when Drivers enabling their IRQ.
-	**        PCI supports level triggered in order to share IRQ lines.
-	**
-	** Issueing I/O SAPIC an EOI causes an interrupt iff IRQ line is
-	** asserted.
+	** Issueing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
+	** asserted.  IRQ generally should not be asserted when a driver
+	** enables their IRQ. It can lead to "interesting" race conditions
+	** in the driver initialization sequence.
 	*/
-	IOSAPIC_EOI(vi->eoi_addr, vi->eoi_data);
+	__raw_writel(vi->eoi_data, vi->eoi_addr);
 }
 
 
@@ -949,11 +932,7 @@ iosapic_rd_version(struct iosapic_info *isi)
 	ASSERT(isi);
 	ASSERT(isi->isi_hpa);
 
-	/* point window to the version register */
-	WRITE_U32(IOSAPIC_REG_VERSION, isi->isi_hpa+IOSAPIC_REG_SELECT);
-
-	/* now read the version register */
-	return (READ_U32(isi->isi_hpa+IOSAPIC_REG_WINDOW));
+	return iosapic_read(isi->isi_hpa, IOSAPIC_REG_VERSION);
 }
 
 
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 176e0951b15c3d..8126dbdcdafdd9 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -34,7 +34,6 @@
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
 #include <linux/init.h>		/* for __init and __devinit */
-/* #define PCI_DEBUG	enable ASSERT */
 #include <linux/pci.h>
 #include <linux/ioport.h>
 #include <linux/slab.h>
@@ -43,6 +42,7 @@
 #include <asm/byteorder.h>
 #include <asm/irq.h>		/* for struct irq_region support */
 #include <asm/pdc.h>
+#include <asm/pdcpat.h>
 #include <asm/page.h>
 #include <asm/segment.h>
 #include <asm/system.h>
@@ -89,6 +89,19 @@
 #define DBG_PAT(x...)
 #endif
 
+#ifdef DEBUG_LBA
+#undef ASSERT
+#define ASSERT(expr) \
+	if(!(expr)) { \
+		printk("\n%s:%d: Assertion " #expr " failed!\n", \
+				__FILE__, __LINE__); \
+		panic(#expr); \
+	}
+#else
+#define ASSERT(expr)
+#endif
+
+
 /*
 ** Config accessor functions only pass in the 8-bit bus number and not
 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
@@ -159,6 +172,8 @@
 #define LBA_HINT_CFG	0x0310
 #define LBA_HINT_BASE	0x0380	/* 14 registers at every 8 bytes. */
 
+#define LBA_BUS_MODE	0x0620
+
 /* ERROR regs are needed for config cycle kluges */
 #define LBA_ERROR_CONFIG 0x0680
 #define     LBA_SMART_MODE 0x20
@@ -168,12 +183,31 @@
 #define LBA_IOSAPIC_BASE	0x800 /* Offset of IRQ logic */
 
 /* non-postable I/O port space, densely packed */
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 #define LBA_ASTRO_PORT_BASE	(0xfffffffffee00000UL)
 #else
 #define LBA_ASTRO_PORT_BASE	(0xfee00000UL)
 #endif
 
+#define ELROY_HVERS	0x782
+#define MERCURY_HVERS	0x783
+#define QUICKSILVER_HVERS	0x784
+
+static inline int IS_ELROY(struct parisc_device *d)
+{
+	return (d->id.hversion == ELROY_HVERS);
+}
+
+static inline int IS_MERCURY(struct parisc_device *d)
+{
+	return (d->id.hversion == MERCURY_HVERS);
+}
+
+static inline int IS_QUICKSILVER(struct parisc_device *d)
+{
+	return (d->id.hversion == QUICKSILVER_HVERS);
+}
+
 
 /*
 ** lba_device: Per instance Elroy data structure
@@ -184,7 +218,7 @@ struct lba_device {
 	spinlock_t	lba_lock;
 	void		*iosapic_obj;
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 	unsigned long	iop_base;    /* PA_VIEW - for IO port accessor funcs */
 #endif
 
@@ -288,11 +322,6 @@ lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
 {
 	u8 first_bus = d->hba.hba_bus->secondary;
 	u8 last_sub_bus = d->hba.hba_bus->subordinate;
-#if 0
-/* FIXME - see below in this function */
-        u8 dev = PCI_SLOT(dfn);
-        u8 func = PCI_FUNC(dfn);
-#endif
 
 	ASSERT(bus >= first_bus);
 	ASSERT(bus <= last_sub_bus);
@@ -306,19 +335,7 @@ lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
 	    return(FALSE);
 	}
 
-#if 0
-/*
-** FIXME: Need to implement code to fill the devices bitmap based
-** on contents of the local pci_bus tree "data base".
-** pci_register_ops() walks the bus for us and builds the tree.
-** For now, always do the config cycle.
-*/
-	bus -= first_bus;
-
-	return (((d->devices[bus][dev]) >> func) & 0x1);
-#else
 	return TRUE;
-#endif
 }
 
 
@@ -503,6 +520,43 @@ lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
 	return(data);
 }
 
+#ifdef CONFIG_PARISC64
+#define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr))
+
+static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
+{
+	int tok = pat_cfg_addr(bus->number, devfn, pos);
+	u32 tmp;
+	int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp);
+
+	DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret);
+
+	switch (size) {
+		case 1: *data = (u8)  tmp; return (tmp == (u8)  ~0);
+		case 2: *data = (u16) tmp; return (tmp == (u16) ~0);
+		case 4: *data = (u32) tmp; return (tmp == (u32) ~0);
+	}
+	*data = ~0;
+	return (ret);
+}
+
+static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
+{
+	int tok = pat_cfg_addr(bus->number, devfn, pos);
+	int ret = pdc_pat_io_pci_cfg_write(tok, size, data);
+
+	DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size);
+	return (ret);
+}
+
+static struct pci_ops pat_cfg_ops = {
+	.read =		pat_cfg_read,
+	.write =	pat_cfg_write,
+};
+#else
+/* keep the compiler from complaining about undeclared variables */
+#define pat_cfg_ops lba_cfg_ops
+#endif
 
 static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
 {
@@ -610,6 +664,7 @@ static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int s
 	}
 
 	DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
+
 	/* Basic Algorithm */
 	LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
 	switch(size) {
@@ -639,7 +694,7 @@ lba_bios_init(void)
 }
 
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 
 /*
 ** Determine if a device is already configured.
@@ -677,6 +732,8 @@ lba_claim_dev_resources(struct pci_dev *dev)
 		}
 	}
 }
+#else
+#define lba_claim_dev_resources(dev)
 #endif
 
 
@@ -734,7 +791,7 @@ lba_fixup_bus(struct pci_bus *bus)
 			lba_dump_res(&iomem_resource, 2);
 		}
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 		if (ldev->hba.gmmio_space.flags) {
 			err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
 			if (err < 0) {
@@ -792,12 +849,10 @@ lba_fixup_bus(struct pci_bus *bus)
 		bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
 #endif
 
-#ifdef __LP64__
 		if (is_pdc_pat()) {
 			/* Claim resources for PDC's devices */
 			lba_claim_dev_resources(dev);
 		}
-#endif
 
                 /*
 		** P2PB's have no IRQs. ignore them.
@@ -925,7 +980,7 @@ static struct pci_port_ops lba_astro_port_ops = {
 };
 
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 #define PIOP_TO_GMMIO(lba, addr) \
 	((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
 
@@ -1093,7 +1148,11 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 		}
 	}
 }
-#endif	/* __LP64__ */
+#else
+/* keep compiler from complaining about missing declarations */
+#define lba_pat_port_ops lba_astro_port_ops
+#define lba_pat_resources(pa_dev, lba_dev)
+#endif	/* CONFIG_PARISC64 */
 
 
 static void
@@ -1103,7 +1162,7 @@ lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 	unsigned long rsize;
 	int lba_num;
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 	/*
 	** Sign extend all BAR values on "legacy" platforms.
 	** "Sprockets" PDC (Forte/Allegro) initializes everything
@@ -1237,7 +1296,7 @@ lba_hw_init(struct lba_device *d)
 	printk("\n");
 #endif	/* DEBUG_LBA_PAT */
 
-#ifdef __LP64__
+#ifdef CONFIG_PARISC64
 /*
  * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
  * Only N-Class and up can really make use of Get slot status.
@@ -1317,7 +1376,7 @@ lba_common_init(struct lba_device *lba_dev)
 ** have work to do.
 */
 static int __init
-lba_driver_callback(struct parisc_device *dev)
+lba_driver_probe(struct parisc_device *dev)
 {
 	struct lba_device *lba_dev;
 	struct pci_bus *lba_bus;
@@ -1327,25 +1386,36 @@ lba_driver_callback(struct parisc_device *dev)
 
 	/* Read HW Rev First */
 	func_class = READ_REG32(dev->hpa + LBA_FCLASS);
-	func_class &= 0xf;
-
-	switch (func_class) {
-	case 0:	version = "TR1.0"; break;
-	case 1:	version = "TR2.0"; break;
-	case 2:	version = "TR2.1"; break;
-	case 3:	version = "TR2.2"; break;
-	case 4:	version = "TR3.0"; break;
-	case 5:	version = "TR4.0"; break;
-	default: version = "TR4+";
-	}
 
-	printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
-		MODULE_NAME, version, func_class & 0xf, dev->hpa);
+	if (IS_ELROY(dev)) {	
+		func_class &= 0xf;
+		switch (func_class) {
+		case 0:	version = "TR1.0"; break;
+		case 1:	version = "TR2.0"; break;
+		case 2:	version = "TR2.1"; break;
+		case 3:	version = "TR2.2"; break;
+		case 4:	version = "TR3.0"; break;
+		case 5:	version = "TR4.0"; break;
+		default: version = "TR4+";
+		}
+		printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
+			MODULE_NAME, version, func_class & 0xf, dev->hpa);
+
+		/* Just in case we find some prototypes... */
+	} else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
+		func_class &= 0xff;
+		version = kmalloc(6, GFP_KERNEL);
+		sprintf(version,"TR%d.%d",(func_class >> 4),(func_class & 0xf));
+		/* We could use one printk for both and have it outside,
+                 * but for the mask for func_class.
+                 */ 
+		printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
+			MODULE_NAME, version, func_class & 0xff, dev->hpa);
+	}
 
-	/* Just in case we find some prototypes... */
 	if (func_class < 2) {
-		printk(KERN_WARNING "Can't support LBA older than TR2.1 "
-			"- continuing under adversity.\n");
+		printk(KERN_WARNING "Can't support LBA older than TR2.1"
+				" - continuing under adversity.\n");
 	}
 
 	/*
@@ -1388,16 +1458,12 @@ lba_driver_callback(struct parisc_device *dev)
 
 	/* ---------- Third : setup I/O Port and MMIO resources  --------- */
 
-#ifdef __LP64__
 	if (is_pdc_pat()) {
 		/* PDC PAT firmware uses PIOP region of GMMIO space. */
 		pci_port = &lba_pat_port_ops;
-
 		/* Go ask PDC PAT what resources this LBA has */
 		lba_pat_resources(dev, lba_dev);
-	} else
-#endif
-	{
+	} else {
 		/* Sprockets PDC uses NPIOP region */
 		pci_port = &lba_astro_port_ops;
 
@@ -1412,9 +1478,9 @@ lba_driver_callback(struct parisc_device *dev)
 	dev->dev.platform_data = lba_dev;
 	lba_bus = lba_dev->hba.hba_bus =
 		pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
-				      &lba_cfg_ops, NULL);
+				is_pdc_pat() ? &pat_cfg_ops : &lba_cfg_ops,
+				NULL);
 
-#ifdef __LP64__
 	if (is_pdc_pat()) {
 		/* assign resources to un-initialized devices */
 		DBG_PAT("LBA pci_bus_assign_resources()\n");
@@ -1427,7 +1493,6 @@ lba_driver_callback(struct parisc_device *dev)
 		lba_dump_res(&lba_dev->hba.lmmio_space, 2);
 #endif
 	}
-#endif
 
 	/*
 	** Once PCI register ops has walked the bus, access to config
@@ -1443,14 +1508,16 @@ lba_driver_callback(struct parisc_device *dev)
 }
 
 static struct parisc_device_id lba_tbl[] = {
-	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x782, 0xa },
+	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
+	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
+	{ HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
 	{ 0, }
 };
 
 static struct parisc_driver lba_driver = {
 	.name =		MODULE_NAME,
 	.id_table =	lba_tbl,
-	.probe =	lba_driver_callback,
+	.probe =	lba_driver_probe,
 };
 
 /*
diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c
index 7d497802b906d6..c7d2d5d996ebc8 100644
--- a/drivers/parisc/led.c
+++ b/drivers/parisc/led.c
@@ -157,13 +157,13 @@ static int led_proc_read(char *page, char **start, off_t off, int count,
 static int led_proc_write(struct file *file, const char *buf, 
 	unsigned long count, void *data)
 {
-	char *cur, lbuf[count];
+	char *cur, lbuf[count + 1];
 	int d;
 
 	if (!capable(CAP_SYS_ADMIN))
 		return -EACCES;
 
-	memset(lbuf, 0, count);
+	memset(lbuf, 0, count + 1);
 
 	if (copy_from_user(lbuf, buf, count))
 		return -EFAULT;
@@ -197,7 +197,7 @@ static int led_proc_write(struct file *file, const char *buf,
 
 		break;
 	case LED_HASLCD:
-		while (*cur && cur[strlen(cur)-1] == '\n')
+		if (*cur && cur[strlen(cur)-1] == '\n')
 			cur[strlen(cur)-1] = 0;
 		if (*cur == 0) 
 			cur = lcd_text_default;
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index f1c850d20e4fa7..f3cf291adc776b 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -27,9 +27,7 @@
 
 #include <linux/mm.h>
 #include <linux/string.h>
-#undef PCI_DEBUG		/* for ASSERT */
 #include <linux/pci.h>
-#undef PCI_DEBUG
 
 #include <asm/byteorder.h>
 #include <asm/io.h>
@@ -40,8 +38,13 @@
 #include <linux/proc_fs.h>
 #include <asm/runway.h>		/* for proc_runway_root */
 #include <asm/pdc.h>		/* for PDC_MODEL_* */
+#include <asm/pdcpat.h>		/* for is_pdc_pat() */
 #include <asm/parisc-device.h>
 
+
+/* declared in arch/parisc/kernel/setup.c */
+extern struct proc_dir_entry * proc_mckinley_root;
+
 #define MODULE_NAME "SBA"
 
 #ifdef CONFIG_PROC_FS
@@ -54,6 +57,7 @@
 ** Don't even think about messing with it unless you have
 ** plenty of 710's to sacrifice to the computer gods. :^)
 */
+#undef DEBUG_SBA_ASSERT
 #undef DEBUG_SBA_INIT
 #undef DEBUG_SBA_RUN
 #undef DEBUG_SBA_RUN_SG
@@ -62,8 +66,6 @@
 #undef DEBUG_LARGE_SG_ENTRIES
 #undef DEBUG_DMB_TRAP
 
-#define SBA_INLINE	__inline__
-
 #ifdef DEBUG_SBA_INIT
 #define DBG_INIT(x...)	printk(x)
 #else
@@ -89,6 +91,27 @@
 #define DBG_RES(x...)
 #endif
 
+#ifdef DEBUG_SBA_ASSERT
+#undef ASSERT
+#define ASSERT(expr) \
+	if(!(expr)) { \
+		printk("\n%s:%d: Assertion " #expr " failed!\n", \
+				__FILE__, __LINE__); \
+		panic(#expr); \
+	}
+#else
+#define ASSERT(expr)
+#endif
+
+
+#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
+/* "low end" PA8800 machines use ZX1 chipset */
+#define ZX1_SUPPORT
+#endif
+
+#define SBA_INLINE	__inline__
+
+
 /*
 ** The number of pdir entries to "free" before issueing
 ** a read to PCOM register to flush out PCOM writes.
@@ -112,6 +135,9 @@
 #define REOG_MERCED_PORT	0x805
 #define REOG_ROPES_PORT		0x783
 
+#define PLUTO_MCKINLEY_PORT	0x880
+#define PLUTO_ROPES_PORT	0x784
+
 #define SBA_FUNC_ID	0x0000	/* function id */
 #define SBA_FCLASS	0x0008	/* function class, bist, header, rev... */
 
@@ -121,12 +147,17 @@
 #define IS_IKE(id) \
 (((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
 
+#define IS_PLUTO(id) \
+(((id)->hversion == PLUTO_MCKINLEY_PORT) || ((id)->hversion == PLUTO_ROPES_PORT))
+
 #define SBA_FUNC_SIZE 4096   /* SBA configuration function reg set */
 
 #define ASTRO_IOC_OFFSET 0x20000
 /* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
 #define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
 
+#define PLUTO_IOC_OFFSET 0x1000
+
 #define IOC_CTRL          0x8	/* IOC_CTRL offset */
 #define IOC_CTRL_TC       (1 << 0) /* TOC Enable */
 #define IOC_CTRL_CE       (1 << 1) /* Coalesce Enable */
@@ -134,7 +165,7 @@
 #define IOC_CTRL_RM       (1 << 8) /* Real Mode */
 #define IOC_CTRL_NC       (1 << 9) /* Non Coherent Mode */
 
-#define MAX_IOC		2	/* per Ike. Astro only has 1 */
+#define MAX_IOC		2	/* per Ike. Pluto/Astro only have 1. */
 
 
 /*
@@ -170,7 +201,9 @@
 #define IOC_TCNFG	0x318
 #define IOC_PDIR_BASE	0x320
 
-#define IOC_IOVA_SPACE_BASE	0	/* IOVA ranges start at 0 */
+/* AGP GART driver looks for this */
+#define SBA_IOMMU_COOKIE    0x0000badbadc0ffeeUL
+
 
 /*
 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
@@ -181,9 +214,7 @@
 ** page since the Virtual Coherence Index has to be generated
 ** and updated for each page.
 **
-** IOVP_SIZE could only be greater than PAGE_SIZE if we are
-** confident the drivers really only touch the next physical
-** page iff that driver instance owns it.
+** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
 */
 #define IOVP_SIZE	PAGE_SIZE
 #define IOVP_SHIFT	PAGE_SHIFT
@@ -207,13 +238,20 @@ struct ioc {
 	unsigned long	ioc_hpa;	/* I/O MMU base address */
 	char	*res_map;	/* resource map, bit == pdir entry */
 	u64	*pdir_base;	/* physical base address */
-
+	unsigned long	ibase;	/* pdir IOV Space base - shared w/lba_pci */
+	unsigned long	imask;	/* pdir IOV Space mask - shared w/lba_pci */
+#ifdef ZX1_SUPPORT
+	unsigned long	iovp_mask;	/* help convert IOVA to IOVP */
+#endif
 	unsigned long	*res_hint;	/* next avail IOVP - circular search */
 	spinlock_t	res_lock;
-	unsigned long	hint_mask_pdir;	/* bits used for DMA hints */
 	unsigned int	res_bitshift;	/* from the LEFT! */
 	unsigned int	res_size;	/* size of resource map in bytes */
+#if SBA_HINT_SUPPORT
+/* FIXME : DMA HINTs not used */
+	unsigned long	hint_mask_pdir;	/* bits used for DMA hints */
 	unsigned int	hint_shift_pdir;
+#endif
 #if DELAYED_RESOURCE_CNT > 0
 	int saved_cnt;
 	struct sba_dma_pair {
@@ -239,8 +277,6 @@ struct ioc {
 
 	/* STUFF We don't need in performance path */
 	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
-	unsigned long	ibase;		/* pdir IOV Space base - shared w/lba_pci */
-	unsigned long	imask;		/* pdir IOV Space mask - shared w/lba_pci */
 };
 
 struct sba_device {
@@ -274,6 +310,9 @@ static unsigned long piranha_bad_128k = 0;
 /* Looks nice and keeps the compiler happy */
 #define SBA_DEV(d) ((struct sba_device *) (d))
 
+#if SBA_AGP_SUPPORT
+static int reserve_sba_gart = 1;
+#endif
 
 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
 
@@ -333,12 +372,15 @@ static void
 sba_dump_tlb(unsigned long hpa)
 {
 	DBG_INIT("IO TLB at 0x%lx\n", hpa);
-	DBG_INIT("IOC_IBASE    : %Lx\n", READ_REG64(hpa+IOC_IBASE));
-	DBG_INIT("IOC_IMASK    : %Lx\n", READ_REG64(hpa+IOC_IMASK));
-	DBG_INIT("IOC_TCNFG    : %Lx\n", READ_REG64(hpa+IOC_TCNFG));
-	DBG_INIT("IOC_PDIR_BASE: %Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
+	DBG_INIT("IOC_IBASE    : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
+	DBG_INIT("IOC_IMASK    : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
+	DBG_INIT("IOC_TCNFG    : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
+	DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
 	DBG_INIT("\n");
 }
+#else
+#define sba_dump_ranges(x)
+#define sba_dump_tlb(x)
 #endif
 
 
@@ -458,13 +500,18 @@ sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
 #define PAGES_PER_RANGE 1	/* could increase this to 4 or 8 if needed */
 
 /* Convert from IOVP to IOVA and vice versa. */
-#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset) | ((hint_reg)<<(ioc->hint_shift_pdir)))
-#define SBA_IOVP(ioc,iova) ((iova) & ioc->hint_mask_pdir)
 
-/* FIXME : review these macros to verify correctness and usage */
+#ifdef ZX1_SUPPORT
+/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
+#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
+#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
+#else
+/* only support Astro and ancestors. Saves a few cycles in key places */
+#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
+#define SBA_IOVP(ioc,iova) (iova)
+#endif
+
 #define PDIR_INDEX(iovp)   ((iovp)>>IOVP_SHIFT)
-#define MKIOVP(dma_hint,pide)  (dma_addr_t)((long)(dma_hint) | ((long)(pide) << IOVP_SHIFT))
-#define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
 
 #define RESMAP_MASK(n)    (~0UL << (BITS_PER_LONG - (n)))
 #define RESMAP_IDX_MASK   (sizeof(unsigned long) - 1)
@@ -661,8 +708,9 @@ sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
 *
 ***************************************************************/
 
+#if SBA_HINT_SUPPORT
 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
-
+#endif
 
 typedef unsigned long space_t;
 #define KERNEL_SPACE 0
@@ -677,25 +725,33 @@ typedef unsigned long space_t;
  *
  * Given a virtual address (vba, arg2) and space id, (sid, arg1)
  * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
- * pdir_ptr (arg0). Each IO Pdir entry consists of 8 bytes as
- * shown below (MSB == bit 0):
+ * pdir_ptr (arg0). 
+ * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
+ * for Astro/Ike looks like:
+ *
  *
  *  0                    19                                 51   55       63
  * +-+---------------------+----------------------------------+----+--------+
  * |V|        U            |            PPN[43:12]            | U  |   VI   |
  * +-+---------------------+----------------------------------+----+--------+
  *
- *  V  == Valid Bit
+ * Pluto is basically identical, supports fewer physical address bits:
+ *
+ *  0                       23                              51   55       63
+ * +-+------------------------+-------------------------------+----+--------+
+ * |V|        U               |         PPN[39:12]            | U  |   VI   |
+ * +-+------------------------+-------------------------------+----+--------+
+ *
+ *  V  == Valid Bit  (Most Significant Bit is bit 0)
  *  U  == Unused
  * PPN == Physical Page Number
  * VI  == Virtual Index (aka Coherent Index)
  *
- * The physical address fields are filled with the results of the LPA
- * instruction.  The virtual index field is filled with the results of
- * of the LCI (Load Coherence Index) instruction.  The 8 bits used for
- * the virtual index are bits 12:19 of the value returned by LCI.
+ * LPA instruction output is put into PPN field.
+ * LCI (Load Coherence Index) instruction provides the "VI" bits.
  *
- * We need to pre-swap the bytes since PCX-W is Big Endian.
+ * We pre-swap the bytes since PCX-W is Big Endian and the
+ * IOMMU uses little endian for the pdir.
  */
 
 
@@ -713,7 +769,7 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
 	ASSERT(sid == KERNEL_SPACE);
 
 	pa = virt_to_phys(vba);
-	pa &= ~4095ULL;			/* clear out offset bits */
+	pa &= IOVP_MASK;
 
 	mtsp(sid,1);
 	asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
@@ -800,7 +856,7 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
 		} while (byte_cnt > 0);
 	}
 
-	WRITE_REG(iovp, ioc->ioc_hpa+IOC_PCOM);
+	WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
 }
 
 /**
@@ -868,7 +924,7 @@ sba_map_single(struct device *dev, void *addr, size_t size,
 	pide = sba_alloc_range(ioc, size);
 	iovp = (dma_addr_t) pide << IOVP_SHIFT;
 
-	DBG_RUN("%s() 0x%p -> 0x%lx",
+	DBG_RUN("%s() 0x%p -> 0x%lx\n",
 		__FUNCTION__, addr, (long) iovp | offset);
 
 	pdir_start = &(ioc->pdir_base[pide]);
@@ -877,7 +933,7 @@ sba_map_single(struct device *dev, void *addr, size_t size,
 		ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
 		sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
 
-		DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
+		DBG_RUN("	pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
 			pdir_start,
 			(u8) (((u8 *) pdir_start)[7]),
 			(u8) (((u8 *) pdir_start)[6]),
@@ -941,14 +997,18 @@ sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
 	ioc->usingle_pages += size >> IOVP_SHIFT;
 #endif
 
+	sba_mark_invalid(ioc, iova, size);
+
 #if DELAYED_RESOURCE_CNT > 0
+	/* Delaying when we re-use a IO Pdir entry reduces the number
+	 * of MMIO reads needed to flush writes to the PCOM register.
+	 */
 	d = &(ioc->saved[ioc->saved_cnt]);
 	d->iova = iova;
 	d->size = size;
 	if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
 		int cnt = ioc->saved_cnt;
 		while (cnt--) {
-			sba_mark_invalid(ioc, d->iova, d->size);
 			sba_free_range(ioc, d->iova, d->size);
 			d--;
 		}
@@ -956,7 +1016,6 @@ sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
 		READ_REG(ioc->ioc_hpa+IOC_PCOM);	/* flush purges */
 	}
 #else /* DELAYED_RESOURCE_CNT == 0 */
-	sba_mark_invalid(ioc, iova, size);
 	sba_free_range(ioc, iova, size);
 	READ_REG(ioc->ioc_hpa+IOC_PCOM);	/* flush purges */
 #endif /* DELAYED_RESOURCE_CNT == 0 */
@@ -1321,6 +1380,142 @@ sba_alloc_pdir(unsigned int pdir_size)
 	return (void *) pdir_base;
 }
 
+static void
+sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+{
+        /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
+        extern void lba_set_iregs(struct parisc_device *, u32, u32);
+
+	u32 iova_space_mask;
+	u32 iova_space_size;
+	int iov_order, tcnfg;
+	struct parisc_device *lba;
+#if SBA_AGP_SUPPORT
+	int agp_found = 0;
+#endif
+	/*
+	** Firmware programs the base and size of a "safe IOVA space"
+	** (one that doesn't overlap memory or LMMIO space) in the
+	** IBASE and IMASK registers.
+	*/
+	ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
+	iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
+
+	if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
+		printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
+		iova_space_size /= 2;
+	}
+
+	/*
+	** iov_order is always based on a 1GB IOVA space since we want to
+	** turn on the other half for AGP GART.
+	*/
+	iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
+	ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
+
+	DBG_INIT("%s() hpa 0x%lx IOV %dMB (%d bits)\n",
+		__FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
+		iov_order + PAGE_SHIFT);
+
+	ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
+						   get_order(ioc->pdir_size));
+	if (!ioc->pdir_base)
+		panic("Couldn't allocate I/O Page Table\n");
+
+	memset(ioc->pdir_base, 0, ioc->pdir_size);
+
+	DBG_INIT("%s() pdir %p size %x\n",
+			__FUNCTION__, ioc->pdir_base, ioc->pdir_size);
+
+#if SBA_HINT_SUPPORT
+	ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
+	ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
+
+	DBG_INIT("	hint_shift_pdir %x hint_mask_pdir %lx\n",
+		ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+#endif
+
+	ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
+	WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
+
+	/* build IMASK for IOC and Elroy */
+	iova_space_mask =  0xffffffff;
+	iova_space_mask <<= (iov_order + PAGE_SHIFT);
+	ioc->imask = iova_space_mask;
+#ifdef ZX1_SUPPORT
+	ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
+#endif
+	sba_dump_tlb(ioc->ioc_hpa);
+
+	/*
+	** setup Mercury IBASE/IMASK registers as well.
+	*/
+	for (lba = sba->child; lba; lba = lba->sibling) {
+		int rope_num = (lba->hpa >> 13) & 0xf;
+		if (rope_num >> 3 == ioc_num)
+			lba_set_iregs(lba, ioc->ibase, ioc->imask);
+	}
+
+	WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
+
+#ifdef __LP64__
+	/*
+	** Setting the upper bits makes checking for bypass addresses
+	** a little faster later on.
+	*/
+	ioc->imask |= 0xFFFFFFFF00000000UL;
+#endif
+
+	/* Set I/O PDIR Page size to system page size */
+	switch (PAGE_SHIFT) {
+		case 12: tcnfg = 0; break;	/*  4K */
+		case 13: tcnfg = 1; break;	/*  8K */
+		case 14: tcnfg = 2; break;	/* 16K */
+		case 16: tcnfg = 3; break;	/* 64K */
+		default:
+			panic(__FILE__ "Unsupported system page size %d",
+				1 << PAGE_SHIFT);
+			break;
+	}
+	WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
+
+	/*
+	** Program the IOC's ibase and enable IOVA translation
+	** Bit zero == enable bit.
+	*/
+	WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
+
+	/*
+	** Clear I/O TLB of any possible entries.
+	** (Yes. This is a bit paranoid...but so what)
+	*/
+	WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
+
+#if SBA_AGP_SUPPORT
+	/*
+	** If an AGP device is present, only use half of the IOV space
+	** for PCI DMA.  Unfortunately we can't know ahead of time
+	** whether GART support will actually be used, for now we
+	** can just key on any AGP device found in the system.
+	** We program the next pdir index after we stop w/ a key for
+	** the GART code to handshake on.
+	*/
+	device=NULL;
+	for (lba = sba->child; lba; lba = lba->sibling) {
+		if (IS_QUICKSILVER(lba))
+			break;
+	}
+
+	if (lba) {
+		DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
+		ioc->pdir_size /= 2;
+		((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
+	} else {
+		DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
+	}
+#endif /* 0 */
+
+}
 
 static void
 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
@@ -1381,15 +1576,19 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 		__FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
 		iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
 
+	ioc->pdir_base = sba_alloc_pdir(pdir_size);
+
+	DBG_INIT("%s() pdir %p size %x\n",
+			__FUNCTION__, ioc->pdir_base, pdir_size);
+
+#if SBA_HINT_SUPPORT
 	/* FIXME : DMA HINTs not used */
 	ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
 	ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
 
-	ioc->pdir_base = sba_alloc_pdir(pdir_size);
-
-	DBG_INIT("%s() pdir %p size %x hint_shift_pdir %x hint_mask_pdir %lx\n",
-		__FUNCTION__, ioc->pdir_base, pdir_size,
-		ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+	DBG_INIT("	hint_shift_pdir %x hint_mask_pdir %lx\n",
+			ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+#endif
 
 	ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
 	WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
@@ -1402,8 +1601,11 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 	** On C3000 w/512MB mem, HP-UX 10.20 reports:
 	**     ibase=0, imask=0xFE000000, size=0x2000000.
 	*/
-	ioc->ibase = IOC_IOVA_SPACE_BASE | 1;	/* bit 0 == enable bit */
+	ioc->ibase = 0;
 	ioc->imask = iova_space_mask;	/* save it */
+#ifdef ZX1_SUPPORT
+	ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
+#endif
 
 	DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
 		__FUNCTION__, ioc->ibase, ioc->imask);
@@ -1426,7 +1628,7 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 	/*
 	** Program the IOC's ibase and enable IOVA translation
 	*/
-	WRITE_REG(ioc->ibase, ioc->ioc_hpa+IOC_IBASE);
+	WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
 	WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
 
 	/* Set I/O PDIR Page size to 4K */
@@ -1438,6 +1640,8 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
 	*/
 	WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
 
+	ioc->ibase = 0; /* used by SBA_IOVA and related macros */	
+
 	DBG_INIT("%s() DONE\n", __FUNCTION__);
 }
 
@@ -1476,23 +1680,32 @@ sba_hw_init(struct sba_device *sba_dev)
 		*/
 	}
 
-	ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
-	DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
-		__FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
-	ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
-	ioc_ctl |= IOC_CTRL_TC;	/* Astro: firmware enables this */
+	if (!IS_PLUTO(sba_dev->iodc)) {
+		ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
+		DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
+			__FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
+		ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
+		ioc_ctl |= IOC_CTRL_TC;	/* Astro: firmware enables this */
 
-	WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
+		WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
 
 #ifdef DEBUG_SBA_INIT
-	ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
-	DBG_INIT(" 0x%Lx\n", ioc_ctl);
+		ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
+		DBG_INIT(" 0x%Lx\n", ioc_ctl);
 #endif
+	} /* if !PLUTO */
 
 	if (IS_ASTRO(sba_dev->iodc)) {
 		/* PAT_PDC (L-class) also reports the same goofy base */
 		sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
 		num_ioc = 1;
+	} else if (IS_PLUTO(sba_dev->iodc)) {
+		/* We use a negative value for IOC HPA so it gets 
+                 * corrected when we add it with IKE's IOC offset.
+		 * Doesnt look clean, but fewer code. 
+                 */
+		sba_dev->ioc[0].ioc_hpa = -PLUTO_IOC_OFFSET;
+		num_ioc = 1;
 	} else {
 		sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
 		num_ioc = 2;
@@ -1517,7 +1730,11 @@ sba_hw_init(struct sba_device *sba_dev)
 		/* flush out the writes */
 		READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
 
-		sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
+		if (IS_PLUTO(sba_dev->iodc)) {
+			sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
+		} else {
+			sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
+		}
 	}
 }
 
@@ -1709,12 +1926,17 @@ static struct parisc_device_id sba_tbl[] = {
 	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
 	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
 	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
+	{ HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
 /* These two entries commented out because we don't find them in a
  * buswalk yet.  If/when we do, they would cause us to think we had
  * many more SBAs then we really do.
  *	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
  *	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
  */
+/* We shall also comment out Pluto Ropes Port since bus walk doesnt
+ * report it yet. 
+ *	{ HPHW_BCPORT, HVERSION_REV_ANY_ID, PLUTO_ROPES_PORT, 0xc },
+ */
 	{ 0, }
 };
 
@@ -1739,9 +1961,7 @@ sba_driver_callback(struct parisc_device *dev)
 	int i;
 	char *version;
 
-#ifdef DEBUG_SBA_INIT
 	sba_dump_ranges(dev->hpa);
-#endif
 
 	/* Read HW Rev First */
 	func_class = READ_REG(dev->hpa + SBA_FCLASS);
@@ -1758,13 +1978,16 @@ sba_driver_callback(struct parisc_device *dev)
 		version = astro_rev;
 
 	} else if (IS_IKE(&dev->id)) {
-		static char ike_rev[]="Ike rev ?";
-
+		static char ike_rev[] = "Ike rev ?";
 		ike_rev[8] = '0' + (char) (func_class & 0xff);
 		version = ike_rev;
+	} else if (IS_PLUTO(&dev->id)) {
+		static char pluto_rev[]="Pluto ?.?";
+		pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 
+		pluto_rev[8] = '0' + (char) (func_class & 0x0f); 
+		version = pluto_rev;
 	} else {
-		static char reo_rev[]="REO rev ?";
-
+		static char reo_rev[] = "REO rev ?";
 		reo_rev[8] = '0' + (char) (func_class & 0xff);
 		version = reo_rev;
 	}
@@ -1772,18 +1995,14 @@ sba_driver_callback(struct parisc_device *dev)
 	if (!global_ioc_cnt) {
 		global_ioc_cnt = count_parisc_driver(&sba_driver);
 
-		/* Only Astro has one IOC per SBA */
-		if (!IS_ASTRO(&dev->id))
+		/* Astro and Pluto have one IOC per SBA */
+		if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
 			global_ioc_cnt *= 2;
 	}
 
 	printk(KERN_INFO "%s found %s at 0x%lx\n",
 		MODULE_NAME, version, dev->hpa);
 
-#ifdef DEBUG_SBA_INIT
-	sba_dump_tlb(dev->hpa);
-#endif
-
 	sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
 	if (NULL == sba_dev) {
 		printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
@@ -1813,6 +2032,8 @@ sba_driver_callback(struct parisc_device *dev)
 		create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
 	} else if (IS_IKE(&dev->id)) {
 		create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
+	} else if (IS_PLUTO(&dev->id)) {
+		create_proc_info_entry("Pluto", 0, proc_mckinley_root, sba_proc_info);
 	} else {
 		create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
 	}
diff --git a/drivers/parisc/superio.c b/drivers/parisc/superio.c
index ad7811509b7807..6357ec10ebf4ed 100644
--- a/drivers/parisc/superio.c
+++ b/drivers/parisc/superio.c
@@ -419,8 +419,10 @@ superio_serial_init(void)
 {
 #ifdef CONFIG_SERIAL_8250
 	int retval;
+#ifdef CONFIG_SERIAL_8250_CONSOLE
 	extern void serial8250_console_init(void); /* drivers/serial/8250.c */
-	
+#endif        
+        
 	if (!sio_dev.irq_region)
 		return; /* superio not present */
 
@@ -438,8 +440,10 @@ superio_serial_init(void)
 		return;
 	}
 
+#ifdef CONFIG_SERIAL_8250_CONSOLE
 	serial8250_console_init();
-
+#endif
+        
 	serial[1].iobase = sio_dev.sp2_base;
 	serial[1].irq = sio_dev.irq_region->data.irqbase + SP2_IRQ;
 	retval = early_serial_setup(&serial[1]);