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| author | David Gibson <david@gibson.dropbear.id.au> | 2005-01-10 17:11:19 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-01-10 17:11:19 -0800 |
| commit | bced89beb5f1982c93b0d504ffd3279c174d7801 (patch) | |
| tree | 5b3f4e6bff17047085f06f373eccef94c0477421 /arch | |
| parent | 63ba1a213e5b8e77f954632c71d6ca4af0b3a0b4 (diff) | |
| download | history-bced89beb5f1982c93b0d504ffd3279c174d7801.tar.gz | |
[PATCH] ppc64: rename perf counter register #defines
This patch makes some cleanups to the #defines for various fields in the
MMCR0 performance monitor control register. Specifically, the names of a
couple of bits are changed so that: a) they are a bit less cumbersomely
long and b) they match the names used in the hardware documentation.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ppc64/oprofile/op_model_power4.c | 2 | ||||
| -rw-r--r-- | arch/ppc64/oprofile/op_model_rs64.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c index c0f7a151c76462..b1ca798f4c2908 100644 --- a/arch/ppc64/oprofile/op_model_power4.c +++ b/arch/ppc64/oprofile/op_model_power4.c @@ -97,7 +97,7 @@ static void power4_cpu_setup(void *unused) mtspr(SPRN_MMCR0, mmcr0); mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE; - mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL; + mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE; mtspr(SPRN_MMCR0, mmcr0); mtspr(SPRN_MMCR1, mmcr1_val); diff --git a/arch/ppc64/oprofile/op_model_rs64.c b/arch/ppc64/oprofile/op_model_rs64.c index b34ea586440a78..b3cddb7e03d00f 100644 --- a/arch/ppc64/oprofile/op_model_rs64.c +++ b/arch/ppc64/oprofile/op_model_rs64.c @@ -119,7 +119,7 @@ static void rs64_cpu_setup(void *unused) mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE; /* Only applies to POWER3, but should be safe on RS64 */ - mmcr0 |= MMCR0_PMC1INTCONTROL|MMCR0_PMCNINTCONTROL; + mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE; mtspr(SPRN_MMCR0, mmcr0); dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(), |