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| author | Catalin Marinas <catalin.marinas@com.rmk.(none)> | 2005-01-14 19:54:18 +0000 |
|---|---|---|
| committer | Russell King <rmk@flint.arm.linux.org.uk> | 2005-01-14 19:54:18 +0000 |
| commit | 9ceea8edb0a970c9e57a742efaf4fd7a5aae9881 (patch) | |
| tree | 0338aa8a9f0c36a4059b4b67111ff00ca5b0db3d /arch | |
| parent | 8d8f47da64ec762ec3717cb0b85d2876aad9399d (diff) | |
| download | history-9ceea8edb0a970c9e57a742efaf4fd7a5aae9881.tar.gz | |
[ARM PATCH] 2404/1: BTAC/BTB flushing added in cpu_v6_switch_mm
Patch from Catalin Marinas
This is needed since ARMv6 branch prediction tagging is done by the
virtual address and the ASIDs aren't taken into account.
Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/proc-v6.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 40b63b945dd497..0aa73d4147838b 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -105,6 +105,7 @@ ENTRY(cpu_v6_dcache_clean_area) ENTRY(cpu_v6_switch_mm) mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 mcr p15, 0, r1, c13, c0, 1 @ set context ID |