diff options
| author | Geoffrey LEVAND <geoffrey.levand@am.sony.com> | 2004-08-07 00:58:23 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-08-07 00:58:23 -0700 |
| commit | 99b81994fa66ae680109f3326172dd94cb25d593 (patch) | |
| tree | 3d423515156fb3a119f58a9abdc5da561669ea9f /arch | |
| parent | 4aecd0d481b9fcf1b2359b461bea764dff3ee788 (diff) | |
| download | history-99b81994fa66ae680109f3326172dd94cb25d593.tar.gz | |
[PATCH] ppc32: fix ebony uart clock
This patch corrects the Ebony board's uart clock value to the rate of the
external Epson SG-615P clock source. Now good to 115Kbps.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com> for CELF
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
| -rwxr-xr-x | arch/ppc/platforms/4xx/ebony.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h index 749fff956fe6c4..c4352e6bb71af4 100755 --- a/arch/ppc/platforms/4xx/ebony.h +++ b/arch/ppc/platforms/4xx/ebony.h @@ -64,7 +64,8 @@ #define UART0_IO_BASE (u8 *) 0xE0000200 #define UART1_IO_BASE (u8 *) 0xE0000300 -#define BASE_BAUD 33000000/3/16 +/* external Epson SG-615P */ +#define BASE_BAUD 691200 #define STD_UART_OP(num) \ { 0, BASE_BAUD, 0, UART##num##_INT, \ |