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| author | David S. Miller <davem@nuts.davemloft.net> | 2004-08-09 07:28:42 -0700 |
|---|---|---|
| committer | David S. Miller <davem@nuts.davemloft.net> | 2004-08-09 07:28:42 -0700 |
| commit | 79bd9937a72837bcc12db89d2d4fc62795227892 (patch) | |
| tree | 195fe493b25a5289d43eedeadded0dbd91a5e20c /arch | |
| parent | 5dd3733b45c37f12709d70236d821a6a44c2fae3 (diff) | |
| download | history-79bd9937a72837bcc12db89d2d4fc62795227892.tar.gz | |
[SPARC64]: Fix spitfire bugs in tlb flush and copy_page changes.
- VISEntry clobbers %g3, so have to do %asi stuff
after we invoke it.
- Need to or in 0x10 to TLB flush addresses when
flushing in secondary context
- Context register restore using wrong address register
- Spitfire not so tolerant of membar in delay slot.
Signed-off-by: David S. Miller <davem@redhat.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sparc64/lib/copy_page.S | 6 | ||||
| -rw-r--r-- | arch/sparc64/mm/ultra.S | 10 |
2 files changed, 9 insertions, 7 deletions
diff --git a/arch/sparc64/lib/copy_page.S b/arch/sparc64/lib/copy_page.S index 69af6a7f074236..c7111e044b5a71 100644 --- a/arch/sparc64/lib/copy_page.S +++ b/arch/sparc64/lib/copy_page.S @@ -167,15 +167,15 @@ copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */ nop 9: + VISEntry ldx [%g6 + TI_FLAGS], %g3 + mov %o0, %g1 andcc %g3, _TIF_BLKCOMMIT, %g0 rd %asi, %g3 be,a,pt %icc, 1f wr %g0, ASI_BLK_P, %asi wr %g0, ASI_BLK_COMMIT_P, %asi -1: VISEntry - mov %o0, %g1 - ldda [%o1] ASI_BLK_P, %f0 +1: ldda [%o1] ASI_BLK_P, %f0 add %o1, 0x40, %o1 ldda [%o1] ASI_BLK_P, %f16 add %o1, 0x40, %o1 diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S index fae62faf0c81fb..af8205edfbd0fe 100644 --- a/arch/sparc64/mm/ultra.S +++ b/arch/sparc64/mm/ultra.S @@ -59,14 +59,15 @@ __flush_tlb_pending: 1: sub %o1, (1 << 3), %o1 ldx [%o2 + %o1], %o3 andcc %o3, 1, %g0 + andn %o3, 1, %o3 be,pn %icc, 2f - andn %o3, 1, %o3 + or %o3, 0x10, %o3 stxa %g0, [%o3] ASI_IMMU_DEMAP 2: stxa %g0, [%o3] ASI_DMMU_DEMAP + membar #Sync brnz,pt %o1, 1b nop - flush %g6 - stxa %g2, [%o2] ASI_DMMU + stxa %g2, [%o4] ASI_DMMU flush %g6 retl wrpr %g5, 0x0, %pstate @@ -395,8 +396,9 @@ xcall_flush_tlb_pending: andn %g5, 0x1, %g5 stxa %g0, [%g5] ASI_IMMU_DEMAP 2: stxa %g0, [%g5] ASI_DMMU_DEMAP + membar #Sync brnz,pt %g1, 1b - membar #Sync + nop stxa %g2, [%g4] ASI_DMMU retry |