[ARM PATCH] 1965/1: gas only generates the c and f field bits for the "msr [cs]psr, rN" instruction

Patch from Catalin Marinas

Gas translates the "msr [cs]psr, rN" instruction to "msr [cs]psr_cf, rN". This may cause problems on the ARMv6 architecture where the A and E bits can leak into the SVC mode from the USR mode via the exception handlers. The reverse can happen when returning to user mode. The patch adds _cxsf to all the msr instruction without the field specifier.

5 files changed, 15 insertions, 15 deletions

diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
index a1a0c847dda2d3..4a8a689d15e61c 100644
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ b/arch/arm/boot/compressed/head-clps7500.S
@@ -34,7 +34,7 @@
 		mov	r0, #0x30
 		mcr	p15, 0, r0, c1, c0, 0
 		mov	r0, #0x13
-		msr	cpsr, r0
+		msr	cpsr_cxsf, r0
 		mov	r12, #0x03000000	@ point to LEDs
 		orr	r12, r12, #0x00020000
 		orr	r12, r12, #0xba00
@@ -71,7 +71,7 @@
 		/* Ensure all interrupts are off and MMU disabled */
 		mrs	r0, cpsr
 		orr	r0, r0, #0xc0
-		msr	cpsr, r0
+		msr	cpsr_cxsf, r0
 
 		adr	lr, 1b
 		orr	lr, lr, #0x10000000
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index e483bc9b00c4d2..7fe5c2d39efdf5 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -952,7 +952,7 @@ __dabt_svc:	sub	sp, sp, #S_FRAME_SIZE
 		bl	do_DataAbort
 		disable_irq r0
 		ldr	r0, [sp, #S_PSR]
-		msr	spsr, r0
+		msr	spsr_cxsf, r0
 		ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr
 
 		.align	5
@@ -988,7 +988,7 @@ preempt_return:
 		strne	r0, [r0, -r0]			@ bug()
 #endif
 		ldr	r0, [sp, #S_PSR]		@ irqs are already disabled
-		msr	spsr, r0
+		msr	spsr_cxsf, r0
 		ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr
 
 		.ltorg
@@ -1031,7 +1031,7 @@ __und_svc:	sub	sp, sp, #S_FRAME_SIZE
 
 1:		disable_irq r0
 		ldr	lr, [sp, #S_PSR]		@ Get SVC cpsr
-		msr	spsr, lr
+		msr	spsr_cxsf, lr
 		ldmia	sp, {r0 - pc}^			@ Restore SVC registers
 
 		.align	5
@@ -1052,7 +1052,7 @@ __pabt_svc:	sub	sp, sp, #S_FRAME_SIZE
 		bl	do_PrefetchAbort		@ call abort handler
 		disable_irq r0
 		ldr	r0, [sp, #S_PSR]
-		msr	spsr, r0
+		msr	spsr_cxsf, r0
 		ldmia	sp, {r0 - pc}^			@ load r0 - pc, cpsr
 
 		.align	5
@@ -1303,7 +1303,7 @@ vector_IRQ:	@
 		mrs	r13, cpsr
 		bic	r13, r13, #MODE_MASK
 		orr	r13, r13, #MODE_SVC
-		msr	spsr, r13			@ switch to SVC_32 mode
+		msr	spsr_cxsf, r13			@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -1346,7 +1346,7 @@ vector_data:	@
 		mrs	r13, cpsr
 		bic	r13, r13, #MODE_MASK
 		orr	r13, r13, #MODE_SVC
-		msr	spsr, r13			@ switch to SVC_32 mode
+		msr	spsr_cxsf, r13			@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -1390,7 +1390,7 @@ vector_prefetch:
 		mrs	r13, cpsr
 		bic	r13, r13, #MODE_MASK
 		orr	r13, r13, #MODE_SVC
-		msr	spsr, r13			@ switch to SVC_32 mode
+		msr	spsr_cxsf, r13			@ switch to SVC_32 mode
 
 		ands	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
@@ -1433,7 +1433,7 @@ vector_undefinstr:
 		mrs	r13, cpsr
 		bic	r13, r13, #MODE_MASK
 		orr	r13, r13, #MODE_SVC
-		msr	spsr, r13			@ switch to SVC_32 mode
+		msr	spsr_cxsf, r13			@ switch to SVC_32 mode
 
 		and	lr, lr, #15
 		ldr	lr, [pc, lr, lsl #2]
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8686a90c15a8da..3314274b73714e 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -102,7 +102,7 @@ ENTRY(ret_from_fork)
 	ldr	r0, [sp, #S_PSR]		@ Get calling cpsr
 	sub	lr, lr, #4
 	str	lr, [r8]
-	msr	spsr, r0
+	msr	spsr_cxsf, r0
 	ldmia	sp, {r0 - lr}^			@ Get calling r0 - lr
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 0af6f53e2302fd..ef152e3b53fc1a 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -99,7 +99,7 @@
 	ldr	r1, [sp, #S_PSR]		@ Get calling cpsr
 	disable_irq ip				@ disable IRQs
 	ldr	lr, [sp, #S_PC]!		@ Get PC
-	msr	spsr, r1			@ save in spsr_svc
+	msr	spsr_cxsf, r1			@ save in spsr_svc
 	ldmdb	sp, {r0 - lr}^			@ Get calling r0 - lr
 	mov	r0, r0
 	add	sp, sp, #S_FRAME_SIZE - S_PC
@@ -112,7 +112,7 @@
 	.macro	fast_restore_user_regs
 	ldr	r1, [sp, #S_OFF + S_PSR]	@ get calling cpsr
 	ldr	lr, [sp, #S_OFF + S_PC]!	@ get pc
-	msr	spsr, r1			@ save in spsr_svc
+	msr	spsr_cxsf, r1			@ save in spsr_svc
 	ldmdb	sp, {r1 - lr}^			@ get calling r1 - lr
 	mov	r0, r0
 	add	sp, sp, #S_FRAME_SIZE - S_PC
@@ -125,7 +125,7 @@
 	.macro	slow_restore_user_regs
 	ldr	r1, [sp, #S_PSR]		@ get calling cpsr
 	ldr	lr, [sp, #S_PC]!		@ get pc
-	msr	spsr, r1			@ save in spsr_svc
+	msr	spsr_cxsf, r1			@ save in spsr_svc
 	ldmdb	sp, {r0 - lr}^			@ get calling r1 - lr
 	mov	r0, r0
 	add	sp, sp, #S_FRAME_SIZE - S_PC
diff --git a/arch/arm/lib/ecard.S b/arch/arm/lib/ecard.S
index f71a44a90c23d2..fb7b602a6f76a4 100644
--- a/arch/arm/lib/ecard.S
+++ b/arch/arm/lib/ecard.S
@@ -16,7 +16,7 @@
 
 #define CPSR2SPSR(rt) \
 		mrs	rt, cpsr; \
-		msr	spsr, rt
+		msr	spsr_cxsf, rt
 
 @ Purpose: call an expansion card loader to read bytes.
 @ Proto  : char read_loader(int offset, char *card_base, char *loader);