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| author | Alan Cox <alan@lxorguk.ukuu.org.uk> | 2004-08-22 00:03:35 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-08-22 00:03:35 -0700 |
| commit | 1039575efbc41a46b982ced18b877e0e152cc42c (patch) | |
| tree | 2eb629297e4a91730a2137f7f63e9e527b7a9b51 /arch | |
| parent | 2b74f0cda0211b0c79eedcfb685de3eedfb0a676 (diff) | |
| download | history-1039575efbc41a46b982ced18b877e0e152cc42c.tar.gz | |
[PATCH] missing CPU descriptors
There are a couple of cache descriptors in the current Intel manuals
missing from our tables at least one of which appears in an actual
processor in the real world.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/i386/kernel/cpu/intel.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c index 09acdd76b6d3a4..42379aec880d53 100644 --- a/arch/i386/kernel/cpu/intel.c +++ b/arch/i386/kernel/cpu/intel.c @@ -97,10 +97,12 @@ static struct _cache_table cache_table[] __initdata = { 0x70, LVL_TRACE, 12 }, { 0x71, LVL_TRACE, 16 }, { 0x72, LVL_TRACE, 32 }, + { 0x78, LVL_2, 1024 }, { 0x79, LVL_2, 128 }, { 0x7a, LVL_2, 256 }, { 0x7b, LVL_2, 512 }, { 0x7c, LVL_2, 1024 }, + { 0x7d, LVL_2, 2048 }, { 0x82, LVL_2, 256 }, { 0x83, LVL_2, 512 }, { 0x84, LVL_2, 1024 }, |