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| author | Jack Steiner <steiner@sgi.com> | 2004-07-12 00:27:49 -0700 |
|---|---|---|
| committer | David Mosberger <davidm@tiger.hpl.hp.com> | 2004-07-12 00:27:49 -0700 |
| commit | 48cd6783d73afae968acf1c36e7b4e149328d20b (patch) | |
| tree | 81785d34f28b2afa710c6ec91d7af9aecee41b6a /Documentation | |
| parent | eac9ee8eb9f1a46be51870207fa68ce169810ded (diff) | |
| download | history-48cd6783d73afae968acf1c36e7b4e149328d20b.tar.gz | |
[PATCH] ia64: Reduce TLB flushing during process migration
This patch adds an architecture-specific callout after explicit
processor migrations. The callout allows architectures (or platforms)
to update TLB specific information (ex., cpu_vm_mask).
Signed-off-by: Jack Steiner <steiner@sgi.com>
Signed-off-by: David Mosberger <davidm@hpl.hp.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/cachetlb.txt | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt index 98e4c6c7319d4a..26bb2b4052cd87 100644 --- a/Documentation/cachetlb.txt +++ b/Documentation/cachetlb.txt @@ -132,6 +132,17 @@ changes occur: translations for software managed TLB configurations. The sparc64 port currently does this. +7) void tlb_migrate_finish(struct mm_struct *mm) + + This interface is called at the end of an explicit + process migration. This interface provides a hook + to allow a platform to update TLB or context-specific + information for the address space. + + The ia64 sn2 platform is one example of a platform + that uses this interface. + + Next, we have the cache flushing interfaces. In general, when Linux is changing an existing virtual-->physical mapping to a new value, the sequence will be in one of the following forms: |