aboutsummaryrefslogtreecommitdiffstats
path: root/queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch
diff options
context:
space:
mode:
Diffstat (limited to 'queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch')
-rw-r--r--queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch58
1 files changed, 58 insertions, 0 deletions
diff --git a/queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch b/queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch
new file mode 100644
index 0000000000..52cdcc40ac
--- /dev/null
+++ b/queue-6.7/drm-amd-display-handle-range-offsets-in-vrr-ranges.patch
@@ -0,0 +1,58 @@
+From 937844d661354bf142dc1c621396fdab10ecbacc Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 28 Feb 2024 15:59:22 -0500
+Subject: drm/amd/display: handle range offsets in VRR ranges
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 937844d661354bf142dc1c621396fdab10ecbacc upstream.
+
+Need to check the offset bits for values greater than 255.
+
+v2: also update amdgpu_dm_connector values.
+
+Suggested-by: Mano Ségransan <mano.segransan@protonmail.com>
+Tested-by: Mano Ségransan <mano.segransan@protonmail.com>
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3203
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 ++++++++++++++-----
+ 1 file changed, 14 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -10876,14 +10876,23 @@ void amdgpu_dm_update_freesync_caps(stru
+ if (range->flags != 1)
+ continue;
+
+- amdgpu_dm_connector->min_vfreq = range->min_vfreq;
+- amdgpu_dm_connector->max_vfreq = range->max_vfreq;
+- amdgpu_dm_connector->pixel_clock_mhz =
+- range->pixel_clock_mhz * 10;
+-
+ connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
+ connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
+
++ if (edid->revision >= 4) {
++ if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
++ connector->display_info.monitor_range.min_vfreq += 255;
++ if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
++ connector->display_info.monitor_range.max_vfreq += 255;
++ }
++
++ amdgpu_dm_connector->min_vfreq =
++ connector->display_info.monitor_range.min_vfreq;
++ amdgpu_dm_connector->max_vfreq =
++ connector->display_info.monitor_range.max_vfreq;
++ amdgpu_dm_connector->pixel_clock_mhz =
++ range->pixel_clock_mhz * 10;
++
+ break;
+ }
+