diff options
Diffstat (limited to 'queue-6.6/arm64-dts-mediatek-mt7622-fix-clock-controllers.patch')
| -rw-r--r-- | queue-6.6/arm64-dts-mediatek-mt7622-fix-clock-controllers.patch | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/queue-6.6/arm64-dts-mediatek-mt7622-fix-clock-controllers.patch b/queue-6.6/arm64-dts-mediatek-mt7622-fix-clock-controllers.patch new file mode 100644 index 0000000000..c83ab745cc --- /dev/null +++ b/queue-6.6/arm64-dts-mediatek-mt7622-fix-clock-controllers.patch @@ -0,0 +1,96 @@ +From 1352076152f96551c89cfe2b36e8f8d36a29c352 Mon Sep 17 00:00:00 2001 +From: Sasha Levin <sashal@kernel.org> +Date: Sun, 17 Mar 2024 23:10:47 +0100 +Subject: arm64: dts: mediatek: mt7622: fix clock controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Rafał Miłecki <rafal@milecki.pl> + +[ Upstream commit 3ba5a61594347ab46e7c2cff6cd63ea0f1282efb ] + +1. Drop unneeded "syscon"s (bindings were updated recently) +2. Use "clock-controller" in nodenames +3. Add missing "#clock-cells" + +Fixes: d7167881e03e ("arm64: dts: mt7622: add clock controller device nodes") +Fixes: e9b65ecb7c30 ("arm64: dts: mediatek: mt7622: introduce nodes for Wireless Ethernet Dispatch") +Signed-off-by: Rafał Miłecki <rafal@milecki.pl> +Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> +Link: https://lore.kernel.org/r/20240317221050.18595-2-zajec5@gmail.com +Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> +Signed-off-by: Sasha Levin <sashal@kernel.org> +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 27 +++++++++++------------- + 1 file changed, 12 insertions(+), 15 deletions(-) + +diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +index 3ee9266fa8e98..283fdf7d2d8b9 100644 +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -283,16 +283,14 @@ + }; + }; + +- apmixedsys: apmixedsys@10209000 { +- compatible = "mediatek,mt7622-apmixedsys", +- "syscon"; ++ apmixedsys: clock-controller@10209000 { ++ compatible = "mediatek,mt7622-apmixedsys"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + +- topckgen: topckgen@10210000 { +- compatible = "mediatek,mt7622-topckgen", +- "syscon"; ++ topckgen: clock-controller@10210000 { ++ compatible = "mediatek,mt7622-topckgen"; + reg = <0 0x10210000 0 0x1000>; + #clock-cells = <1>; + }; +@@ -734,9 +732,8 @@ + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + }; + +- ssusbsys: ssusbsys@1a000000 { +- compatible = "mediatek,mt7622-ssusbsys", +- "syscon"; ++ ssusbsys: clock-controller@1a000000 { ++ compatible = "mediatek,mt7622-ssusbsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -793,9 +790,8 @@ + }; + }; + +- pciesys: pciesys@1a100800 { +- compatible = "mediatek,mt7622-pciesys", +- "syscon"; ++ pciesys: clock-controller@1a100800 { ++ compatible = "mediatek,mt7622-pciesys"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; +@@ -921,12 +917,13 @@ + }; + }; + +- hifsys: syscon@1af00000 { +- compatible = "mediatek,mt7622-hifsys", "syscon"; ++ hifsys: clock-controller@1af00000 { ++ compatible = "mediatek,mt7622-hifsys"; + reg = <0 0x1af00000 0 0x70>; ++ #clock-cells = <1>; + }; + +- ethsys: syscon@1b000000 { ++ ethsys: clock-controller@1b000000 { + compatible = "mediatek,mt7622-ethsys", + "syscon"; + reg = <0 0x1b000000 0 0x1000>; +-- +2.43.0 + |