Merge branch 'for_3.17/net-misc' into keystone/masterkeystone/master

7 files changed, 777 insertions, 66 deletions

diff --git a/arch/arm/boot/dts/k2-rtm-boc-board.dtsi b/arch/arm/boot/dts/k2-rtm-boc-board.dtsi
new file mode 100644
index 00000000000000..3144c7b57cce22
--- /dev/null
+++ b/arch/arm/boot/dts/k2-rtm-boc-board.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2014 Texas Instruments, Inc.
+ *
+ * Keystone 2 RTM BOC expansion board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	mdiox_gpio: mdiox-gpio {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio0 2 0x2 /* mdc */
+				&gpio0 0 0x2>; /* mdio */
+
+		phyx0: phyx@0 {
+			compatible = "Marvell,88x2242", "ethernet-phy-ieee802.3-c45";
+			reg = <0>;
+			reset-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>,
+					<&pca9555 9 GPIO_ACTIVE_HIGH>,
+					<&pca9555 10 GPIO_ACTIVE_HIGH>;
+		};
+
+		phyx1: phyx@1 {
+			compatible = "Marvell,88x2242", "ethernet-phy-ieee802.3-c45";
+			reg = <1>;
+			reset-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>,
+					<&pca9555 9 GPIO_ACTIVE_HIGH>,
+					<&pca9555 10 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&i2c2 {
+	pca9555: pca@20 {
+		compatible = "nxp,pca9555";
+		gpio-controller;
+		#gpio-cells = <2>;
+		reg = <0x20>;
+	};
+};
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index 1f90cbf27fd7f7..47ad18572b08f4 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -11,11 +11,16 @@
 
 #include "keystone.dtsi"
 #include "k2hk.dtsi"
+#include "k2-rtm-boc-board.dtsi"
 
 / {
 	compatible =  "ti,k2hk-evm","ti,keystone";
 	model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
 
+	aliases {
+		serial0	= &uart0;
+	};
+
 	soc {
 		clocks {
 			refclksys: refclksys {
@@ -53,6 +58,319 @@
 				clock-output-names = "refclk-ddr3b";
 			};
 		};
+		qmss: qmss@2a40000 {
+			compatible = "ti,keystone-navigator-qmss";
+			dma-coherent;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&chipclk13>;
+			ranges;
+			queue-range	= <0 0x4000>;
+			linkram0	= <0x100000 0x8000>;
+			linkram1	= <0x0 0x10000>;
+
+			qmgrs {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				qmgr0 {
+					managed-queues = <0 0x2000>;
+					reg = <0x2a40000 0x20000>,
+					      <0x2a06000 0x400>,
+					      <0x2a02000 0x1000>,
+					      <0x2a03000 0x1000>,
+					      <0x23a80000 0x20000>,
+					      <0x2a80000 0x20000>;
+					reg-names = "peek", "status", "config",
+						    "region", "push", "pop";
+				};
+
+				qmgr1 {
+					managed-queues = <0x2000 0x2000>;
+					reg = <0x2a60000 0x20000>,
+					      <0x2a06400 0x400>,
+					      <0x2a04000 0x1000>,
+					      <0x2a05000 0x1000>,
+					      <0x23aa0000 0x20000>,
+					      <0x2aa0000 0x20000>;
+					reg-names = "peek", "status", "config",
+						    "region", "push", "pop";
+				};
+			};
+			queue-pools {
+				qpend {
+					qpend-0 {
+						qrange = <658 8>;
+						interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+							     0 43 0xf04 0 44 0xf04 0 45 0xf04
+							     0 46 0xf04 0 47 0xf04>;
+					};
+					qpend-1 {
+						qrange = <8704 16>;
+						interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+							      0 51 0xf04 0 52 0xf04 0 53 0xf04
+							      0 54 0xf04 0 55 0xf04 0 56 0xf04
+							      0 57 0xf04 0 58 0xf04 0 59 0xf04
+							      0 60 0xf04 0 61 0xf04 0 62 0xf04
+							      0 63 0xf04>;
+						qalloc-by-id;
+					};
+					qpend-2 {
+						qrange = <8720 16>;
+						interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+							      0 59 0xf04 0 68 0xf04 0 69 0xf04
+							      0 70 0xf04 0 71 0xf04 0 72 0xf04
+							      0 73 0xf04 0 74 0xf04 0 75 0xf04
+							      0 76 0xf04 0 77 0xf04 0 78 0xf04
+							      0 79 0xf04>;
+					};
+				};
+				general-purpose {
+					gp-0 {
+						qrange = <4000 64>;
+					};
+					netcp-tx {
+						qrange = <640 9>;
+						qalloc-by-id;
+					};
+					netcpx-tx {
+						qrange = <8752 8>;
+						qalloc-by-id;
+					};
+				};
+				accumulator {
+					acc-0 {
+						qrange = <128 32>;
+						accumulator = <0 36 16 2 50>;
+						interrupts = <0 215 0xf01>;
+						multi-queue;
+						qalloc-by-id;
+					};
+					acc-1 {
+						qrange = <160 32>;
+						accumulator = <0 37 16 2 50>;
+						interrupts = <0 216 0xf01>;
+						multi-queue;
+					};
+					acc-2 {
+						qrange = <192 32>;
+						accumulator = <0 38 16 2 50>;
+						interrupts = <0 217 0xf01>;
+						multi-queue;
+					};
+					acc-3 {
+						qrange = <224 32>;
+						accumulator = <0 39 16 2 50>;
+						interrupts = <0 218 0xf01>;
+						multi-queue;
+					};
+				};
+			};
+			descriptor-regions {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				region-12 {
+					id = <12>;
+					region-spec = <8192 128>;	/* num_desc desc_size */
+					link-index = <0x4000>;
+				};
+			};
+			pdsps {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				pdsp0@0x2a10000 {
+					firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
+					reg = <0x2a10000 0x1000>,
+					      <0x2a0f000 0x100>,
+					      <0x2a0c000 0x3c8>,
+					      <0x2a20000 0x4000>;
+					reg-names = "iram", "reg", "intd", "cmd";
+					id = <0>;
+				};
+			};
+		}; /* qmss */
+
+		knav_dmas: knav_dmas@0 {
+			compatible = "ti,keystone-navigator-dma";
+			clocks = <&papllclk>, <&clkxge>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			ti,navigator-cloud-address = <0x23a80000 0x23a90000
+						   0x23aa0000 0x23ab0000>;
+
+			dma_gbe: dma_gbe@0 {
+				reg = <0x2004000 0x100>,
+					  <0x2004400 0x120>,
+					  <0x2004800 0x300>,
+					  <0x2004c00 0x120>,
+					  <0x2005000 0x400>;
+				reg-names = "global", "txchan", "rxchan",
+						"txsched", "rxflow";
+			};
+
+			dma_xgbe: dma_xgbe@0 {
+				reg = <0x2fa1000 0x100>,
+					<0x2fa1400 0x200>,
+					<0x2fa1800 0x200>,
+					<0x2fa1c00 0x200>,
+					<0x2fa2000 0x400>;
+				reg-names = "global", "txchan", "rxchan",
+						"txsched", "rxflow";
+			};
+		};
+
+		netcp: netcp@2090000 {
+			reg = <0x2620110 0x8>;
+			reg-names = "efuse";
+			compatible = "ti,netcp-1.0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
+			dma-coherent;
+			/* big-endian; */
+
+			ti,navigator-dmas = <&dma_gbe 22>,
+					<&dma_gbe 23>,
+					<&dma_gbe 8>;
+			ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+
+			netcp-devices {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				gbe@0x2090000 {
+					label = "netcp-gbe";
+					reg = <0x2090000 0xf00>;
+					/* enable-ale; */
+					tx-queue = <648>;
+					tx-channel = "nettx";
+
+					interfaces {
+						gbe0: interface-0 {
+							slave-port = <0>;
+							link-interface	= <4>;
+						};
+						gbe1: interface-1 {
+							slave-port = <1>;
+							link-interface	= <4>;
+						};
+					};
+
+					secondary-slave-ports {
+						port-2 {
+							slave-port = <2>;
+							link-interface	= <2>;
+						};
+						port-3 {
+							slave-port = <3>;
+							link-interface	= <2>;
+						};
+					};
+				};
+			};
+
+			netcp-interfaces {
+				interface-0 {
+					rx-channel = "netrx0";
+					rx-pool = <1024 12>;
+					tx-pool = <1024 12>;
+					rx-queue-depth = <128 128 0 0>;
+					rx-buffer-size = <1518 4096 0 0>;
+					rx-queue = <8704>;
+					tx-completion-queue = <8706>;
+					efuse-mac = <1>;
+					netcp-gbe = <&gbe0>;
+
+				};
+				interface-1 {
+					rx-channel = "netrx1";
+					rx-pool = <1024 12>;
+					tx-pool = <1024 12>;
+					rx-queue-depth = <128 128 0 0>;
+					rx-buffer-size = <1518 4096 0 0>;
+					rx-queue = <8705>;
+					tx-completion-queue = <8707>;
+					efuse-mac = <0>;
+					local-mac-address = [02 18 31 7e 3e 6f];
+					netcp-gbe = <&gbe1>;
+				};
+			};
+		};
+
+		netcpx: netcpx@2f00000 {
+			compatible = "ti,netcp-1.0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&clkxge>;
+			clock-names = "clk_xge";
+			dma-coherent;
+			/* big-endian; */
+
+			ti,navigator-dmas = <&dma_xgbe 0>,
+					<&dma_xgbe 8>,
+					<&dma_xgbe 0>;
+			ti,navigator-dma-names = "xnetrx0", "xnetrx1", "xnettx";
+
+			netcp-devices {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				xgbe@0x2f00000 {
+					label = "netcp-xgbe";
+					reg =	<0x2f00000 0xa0600>,
+						<0x0231e000 0x2000>;
+					/* enable-ale; */
+					tx-queue = <8752>;
+					tx-channel = "xnettx";
+
+					interfaces {
+						xgbe0: interface-0 {
+							slave-port = <0>;
+							link-interface	= <10>;
+							phy-handle = <&phyx0>;
+						};
+						xgbe1: interface-1 {
+							slave-port = <1>;
+							link-interface	= <10>;
+							phy-handle = <&phyx1>;
+						};
+					};
+				};
+			};
+
+			netcp-interfaces {
+				interface-0 {
+					rx-channel = "xnetrx0";
+					rx-pool = <1024 12>; /* num_desc region-id */
+					tx-pool = <1024 12>; /* num_desc region-id */
+					rx-queue-depth = <960 64 0 0>;
+					rx-buffer-size = <1518 4096 0 0>;
+					rx-queue = <8708>;
+					tx-completion-queue = <8710>;
+					efuse-mac = <0>;
+					netcp-xgbe = <&xgbe0>;
+
+				};
+				interface-1 {
+					rx-channel = "xnetrx1";
+					rx-pool = <1024 12>; /* num_desc region-id */
+					tx-pool = <1024 12>; /* num_desc region-id */
+					rx-queue-depth = <960 64 0 0>;
+					rx-buffer-size = <1518 4096 0 0>;
+					rx-queue = <8709>;
+					tx-completion-queue = <8711>;
+					efuse-mac = <0>;
+					netcp-xgbe = <&xgbe1>;
+				};
+			};
+		};
 	};
 
 	leds {
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index c1414cb81fd4ac..75a6f9c37e8028 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -266,5 +266,6 @@
 			ranges = <0 0 0x30000000 0x10000000
 				  1 0 0x21000A00 0x00000100>;
 		};
+
 	};
 };
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index 067a8f82194d5d..dc6aac0ef4f82b 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -10,9 +10,10 @@ CONFIG_KALLSYMS_ALL=y
 # CONFIG_ELF_CORE is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_EMBEDDED=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
@@ -25,6 +26,7 @@ CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
+CONFIG_CMA=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 # CONFIG_SUSPEND is not set
@@ -47,64 +49,63 @@ CONFIG_IP_ROUTE_VERBOSE=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=y
-CONFIG_NET_IPGRE_DEMUX=y
-CONFIG_NET_IPGRE=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
 CONFIG_IP_MROUTE=y
 CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
 CONFIG_IP_PIMSM_V2=y
-CONFIG_INET_AH=y
-CONFIG_INET_IPCOMP=y
-CONFIG_IPV6=y
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_IPV6_SIT=m
+CONFIG_INET_AH=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=m
+CONFIG_INET_DIAG=m
 CONFIG_IPV6_MULTIPLE_TABLES=y
 CONFIG_IPV6_SUBTREES=y
 CONFIG_IPV6_MROUTE=y
 CONFIG_IPV6_PIMSM_V2=y
 CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=y
-CONFIG_NF_CT_NETLINK=y
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
-CONFIG_NETFILTER_XT_TARGET_MARK=y
-CONFIG_NETFILTER_XT_MATCH_COMMENT=y
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
-CONFIG_NETFILTER_XT_MATCH_CPU=y
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
-CONFIG_NETFILTER_XT_MATCH_LENGTH=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MARK=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
-CONFIG_NETFILTER_XT_MATCH_STATE=y
-CONFIG_NF_CONNTRACK_IPV4=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=y
-CONFIG_IP_NF_MATCH_ECN=y
-CONFIG_IP_NF_MATCH_TTL=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_TARGET_ULOG=y
-CONFIG_IP_NF_MANGLE=y
-CONFIG_IP_NF_TARGET_CLUSTERIP=y
-CONFIG_IP_NF_TARGET_ECN=y
-CONFIG_IP_NF_TARGET_TTL=y
-CONFIG_IP_NF_RAW=y
-CONFIG_IP_NF_ARPTABLES=y
-CONFIG_IP_NF_ARPFILTER=y
-CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK=m
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
 CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP_SCTP=y
-CONFIG_VLAN_8021Q=y
+CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_CMA=y
 CONFIG_DMA_CMA=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -115,12 +116,16 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_DAVINCI=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=y
-CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
+CONFIG_TI_KEYSTONE_NETCP=y
+CONFIG_PHYLIB=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
@@ -132,12 +137,15 @@ CONFIG_I2C_DAVINCI=y
 CONFIG_SPI=y
 CONFIG_SPI_DAVINCI=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DAVINCI=y
+CONFIG_GPIO_PCA953X=y
 # CONFIG_HWMON is not set
 CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_KEYSTONE=y
 CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_CORE=y
 CONFIG_DAVINCI_WATCHDOG=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -148,8 +156,19 @@ CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_DEBUG=y
 CONFIG_USB_DWC3_VERBOSE=y
 CONFIG_KEYSTONE_USB_PHY=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_DMADEVICES=y
 CONFIG_TI_EDMA=y
+CONFIG_SOC_TI=y
+CONFIG_KEYSTONE_NAVIGATOR_QMSS=y
+CONFIG_KEYSTONE_NAVIGATOR_DMA=y
 CONFIG_MEMORY=y
 CONFIG_TI_AEMIF=y
 CONFIG_EXT4_FS=y
@@ -171,27 +190,23 @@ CONFIG_NFSD_V3_ACL=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_SHIRQ=y
 CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
 CONFIG_CRYPTO_USER=y
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_AUTHENC=y
 CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_DES=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_USER_API_SKCIPHER=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_DAVINCI=y
-CONFIG_LEDS_CLASS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LIBCRC32C=y
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index e721a37c3473ef..15922a236c9db6 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -358,6 +358,9 @@ static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
 	gc->dev = &chip->client->dev;
 	gc->owner = THIS_MODULE;
 	gc->names = chip->names;
+#ifdef CONFIG_OF_GPIO
+	gc->of_node = gc->dev->of_node;
+#endif
 }
 
 #ifdef CONFIG_GPIO_PCA953X_IRQ
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7dc3d5b304cfc2..9ee3e72305fa69 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -3,7 +3,7 @@
 libphy-objs			:= phy.o phy_device.o mdio_bus.o
 
 obj-$(CONFIG_PHYLIB)		+= libphy.o
-obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
+obj-$(CONFIG_MARVELL_PHY)	+= marvell.o mv88x2242.o
 obj-$(CONFIG_DAVICOM_PHY)	+= davicom.o
 obj-$(CONFIG_CICADA_PHY)	+= cicada.o
 obj-$(CONFIG_LXT_PHY)		+= lxt.o
diff --git a/drivers/net/phy/mv88x2242.c b/drivers/net/phy/mv88x2242.c
new file mode 100644
index 00000000000000..7bbde8ff715c37
--- /dev/null
+++ b/drivers/net/phy/mv88x2242.c
@@ -0,0 +1,330 @@
+/* Driver for Marvell PHY 88X2242
+ *
+ * Partially based on drivers/net/phy/bcm87xx.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated
+ * Authors: WingMan Kwok <w-kwok2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/phy.h>
+#include <linux/of.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+
+#define MARVELL_PHY_ID_88X2242	0x01410f12
+#define MARVELL_PHY_ID_MASK	0xfffffc00
+
+/* chip level regs */
+#define MV88X2242_TX_SRC_N		(MII_ADDR_C45 | 0x1ff400)
+#define MV88X2242_TX_SRC_M		(MII_ADDR_C45 | 0x1ff401)
+#define MV88X2242_HOST_LANE_MUX	(MII_ADDR_C45 | 0x1ff402)
+#define MV88X2242_HW_RESET		(MII_ADDR_C45 | 0x1ff404)
+
+/* port level regs */
+#define MV88X2242_PCS_CONFIG		(MII_ADDR_C45 | 0x1ff002)
+#define MV88X2242_PORT_RESET		(MII_ADDR_C45 | 0x1ff003)
+#define MV88X2242_GPIO_TRI_CTRL	(MII_ADDR_C45 | 0x1ff013)
+#define MV88X2242_GPIO_INTR_TYPE3	(MII_ADDR_C45 | 0x1ff016)
+
+/* SFI PMA regs */
+#define MV88X2242_PMD_RX_SIGNAL_DETECT	(MII_ADDR_C45 | 0x01000a)
+
+/* SFI 10BASE-R PCS regs */
+#define MV88X2242_10GBASER_PCS_CTRL	(MII_ADDR_C45 | 0x030000)
+#define MV88X2242_10GBASER_PCS_STATUS	(MII_ADDR_C45 | 0x030020)
+#define MV88X2242_LASI_CONTROL		(MII_ADDR_C45 | 0x038000)
+#define MV88X2242_LASI_STATUS		(MII_ADDR_C45 | 0x038001)
+
+/* XFI 10BASE-R PCS regs */
+#define MV88X2242_BASER_PCS_STATUS	(MII_ADDR_C45 | 0x040020)
+
+static int mv88x2242_chip_init_done;
+
+
+/* Perform one time chip level initialization.
+ */
+static int mv88x2242_chip_level_config(struct phy_device *phydev)
+{
+	int val;
+
+	/* chip hw reset */
+	phy_write(phydev, MV88X2242_HW_RESET, 0x4000);
+
+	mdelay(10);
+
+	/* Map ports */
+	/* Added by TI for port mapping 0123:0123,
+	 *	The default is M0-to-N0, M2-to-N1,
+	 *	so setting bit 9 makes M1-to-N1 instead.
+	 *	Must be done prior to the reset!
+	 * BEGR: I believe only one write is required for this,
+	 * as 31.F4xx registers are accessible through any of the
+	 * 4 PHY addresses.
+	 */
+	phy_write(phydev, MV88X2242_HOST_LANE_MUX, BIT(9));
+
+	/* Shut down unused lanes */
+	val = phy_read(phydev, MV88X2242_TX_SRC_N);
+	val &= 0x00ff;
+	phy_write(phydev, MV88X2242_TX_SRC_N, val);
+
+	val = phy_read(phydev, MV88X2242_TX_SRC_M);
+	val &= 0x00ff;
+	phy_write(phydev, MV88X2242_TX_SRC_M, val);
+
+	return 0;
+}
+
+/* Perform one time port level initialization.
+ */
+static int mv88x2242_port_level_config(struct phy_device *phydev)
+{
+	int val;
+
+	if (phydev->priv) {
+		dev_info(&phydev->dev, "phy %d already configured\n",
+			 phydev->addr);
+		return 0;
+	}
+
+	/*10gx2, 6G */
+	phy_write(phydev, MV88X2242_PCS_CONFIG, 0x7171);
+
+	/* pcs reset */
+	phy_write(phydev, MV88X2242_PORT_RESET, 0x8080);
+
+	mdelay(10);
+
+	/* Required to Enable Optical module transmitter */
+	/* For Fiber Tx Disable to enable optics (REQUIRED) */
+	val = phy_read(phydev, MV88X2242_GPIO_INTR_TYPE3);
+	val = (val & ~0x0018) | 0x0010;
+	phy_write(phydev, MV88X2242_GPIO_INTR_TYPE3, val);
+
+	/* Enable Marvell I2C SCL/SDA operations */
+	val = phy_read(phydev, MV88X2242_GPIO_INTR_TYPE3);
+	val = (val & ~0x0800) | 0x0800;
+	phy_write(phydev, MV88X2242_GPIO_INTR_TYPE3, val);
+
+	val = phy_read(phydev, MV88X2242_GPIO_INTR_TYPE3);
+	val = (val & ~0x8000) | 0x8000;
+	phy_write(phydev, MV88X2242_GPIO_INTR_TYPE3, val);
+
+	val = phy_read(phydev, MV88X2242_GPIO_TRI_CTRL);
+	val = (val & ~0x0800) | 0x0800;
+	phy_write(phydev, MV88X2242_GPIO_TRI_CTRL, val);
+
+	mdelay(10);
+
+	phydev->priv = (void *)1;
+
+	/* Read Each Lane Optical traceiver name? */
+
+	return 0;
+}
+
+/* Reset chip
+ */
+static int mv88x2242_chip_reset(struct phy_device *phydev)
+{
+	int ret;
+	struct gpio_desc *gpio_reset0;
+	struct gpio_desc *gpio_reset1;
+	struct gpio_desc *gpio_reset2;
+	int msec = 1;
+	struct device *dev = &phydev->dev;
+
+	gpio_reset0 = gpiod_get_index(dev, "reset", 0);
+	if (IS_ERR(gpio_reset0))
+		return PTR_ERR(gpio_reset0);
+
+	gpio_reset1 = gpiod_get_index(dev, "reset", 1);
+	if (IS_ERR(gpio_reset1)) {
+		gpiod_put(gpio_reset0);
+		return PTR_ERR(gpio_reset1);
+	}
+
+	gpio_reset2 = gpiod_get_index(dev, "reset", 2);
+	if (IS_ERR(gpio_reset2)) {
+		gpiod_put(gpio_reset0);
+		gpiod_put(gpio_reset1);
+		return PTR_ERR(gpio_reset2);
+	}
+
+	ret  = gpiod_direction_output(gpio_reset0, 0);
+	ret |= gpiod_direction_output(gpio_reset1, 0);
+	ret |= gpiod_direction_output(gpio_reset2, 0);
+	if (ret)
+		goto err;
+
+	msleep(msec);
+
+	gpiod_set_value_cansleep(gpio_reset0, 1);
+	gpiod_set_value_cansleep(gpio_reset1, 1);
+	gpiod_set_value_cansleep(gpio_reset2, 1);
+
+err:
+	gpiod_put(gpio_reset0);
+	gpiod_put(gpio_reset1);
+	gpiod_put(gpio_reset2);
+	return ret;
+}
+
+static int mv88x2242_config_init(struct phy_device *phydev)
+{
+	if (!mv88x2242_chip_init_done) {
+		int ret;
+		/* chip level config */
+		ret = mv88x2242_chip_reset(phydev);
+		if (ret)
+			return ret;
+		mv88x2242_chip_level_config(phydev);
+		mv88x2242_chip_init_done = 1;
+	}
+
+	/* port level config */
+	mv88x2242_port_level_config(phydev);
+
+	phydev->supported = SUPPORTED_10000baseR_FEC;
+	phydev->advertising = ADVERTISED_10000baseR_FEC;
+	phydev->state = PHY_NOLINK;
+	phydev->autoneg = AUTONEG_DISABLE;
+
+	return 0;
+}
+
+static int mv88x2242_config_aneg(struct phy_device *phydev)
+{
+	return -EINVAL;
+}
+
+static int mv88x2242_read_status(struct phy_device *phydev)
+{
+	int rx_signal_detect;
+	int pcs_status;
+
+	rx_signal_detect = phy_read(phydev, MV88X2242_PMD_RX_SIGNAL_DETECT);
+	if (rx_signal_detect < 0)
+		return rx_signal_detect;
+
+	if ((rx_signal_detect & BIT(0)) == 0)
+		goto no_link;
+
+	pcs_status = phy_read(phydev, MV88X2242_10GBASER_PCS_STATUS);
+	if (pcs_status < 0)
+		return pcs_status;
+
+	if ((pcs_status & BIT(0)) == 0)
+		goto no_link;
+
+	pcs_status = phy_read(phydev, MV88X2242_BASER_PCS_STATUS);
+	if (pcs_status < 0)
+		return pcs_status;
+
+	if ((pcs_status & BIT(12)) == 0) {
+		dev_warn(&phydev->dev,
+			 "WARN: host side receive link down\n");
+		goto no_link;
+	}
+
+	phydev->speed = SPEED_10000;
+	phydev->link = 1;
+	phydev->duplex = DUPLEX_FULL;
+	return 0;
+
+no_link:
+	phydev->link = 0;
+	return 0;
+}
+
+static int mv88x2242_config_intr(struct phy_device *phydev)
+{
+	int reg, err;
+
+	reg = phy_read(phydev, MV88X2242_LASI_CONTROL);
+
+	if (reg < 0)
+		return reg;
+
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
+		reg |= 1;
+	else
+		reg &= ~1;
+
+	err = phy_write(phydev, MV88X2242_LASI_CONTROL, reg);
+	return err;
+}
+
+static int mv88x2242_did_interrupt(struct phy_device *phydev)
+{
+	int reg;
+
+	reg = phy_read(phydev, MV88X2242_LASI_STATUS);
+
+	if (reg < 0) {
+		dev_err(&phydev->dev,
+			"Error: Read of MV88X2242_LASI_STATUS failed: %d\n",
+			 reg);
+		return 0;
+	}
+	return (reg & 1) != 0;
+}
+
+static int mv88x2242_ack_interrupt(struct phy_device *phydev)
+{
+	/* Reading the LASI status clears it. */
+	mv88x2242_did_interrupt(phydev);
+	return 0;
+}
+
+static int mv88x2242_match_phy_device(struct phy_device *phydev)
+{
+	return (phydev->c45_ids.device_ids[4] & MARVELL_PHY_ID_MASK) ==
+		(MARVELL_PHY_ID_88X2242 & MARVELL_PHY_ID_MASK);
+}
+
+static struct phy_driver mv88x2242_driver[] = {
+{
+	.phy_id		= MARVELL_PHY_ID_88X2242,
+	.phy_id_mask	= MARVELL_PHY_ID_MASK,
+	.name		= "Marvell 88x2242",
+	.flags		= PHY_HAS_INTERRUPT,
+	.config_init	= mv88x2242_config_init,
+	.config_aneg	= mv88x2242_config_aneg,
+	.read_status	= mv88x2242_read_status,
+	.ack_interrupt	= mv88x2242_ack_interrupt,
+	.config_intr	= mv88x2242_config_intr,
+	.did_interrupt	= mv88x2242_did_interrupt,
+	.match_phy_device = mv88x2242_match_phy_device,
+	.driver		= { .owner = THIS_MODULE },
+}
+};
+
+static int __init mv88x2242_init(void)
+{
+	return phy_drivers_register(mv88x2242_driver,
+				     ARRAY_SIZE(mv88x2242_driver));
+}
+module_init(mv88x2242_init);
+
+static void __exit mv88x2242_exit(void)
+{
+	phy_drivers_unregister(mv88x2242_driver,
+			       ARRAY_SIZE(mv88x2242_driver));
+}
+module_exit(mv88x2242_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("WingMan Kwok <w-kwok2@ti.com>");
+MODULE_DESCRIPTION("Driver For Marvell PHY 88X2242");