diff options
Diffstat (limited to 'v5.12/47403a4b49767f1d533e4dc5f5cf5cc957f22a5e')
| -rw-r--r-- | v5.12/47403a4b49767f1d533e4dc5f5cf5cc957f22a5e | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/v5.12/47403a4b49767f1d533e4dc5f5cf5cc957f22a5e b/v5.12/47403a4b49767f1d533e4dc5f5cf5cc957f22a5e new file mode 100644 index 00000000000..3831d150bc5 --- /dev/null +++ b/v5.12/47403a4b49767f1d533e4dc5f5cf5cc957f22a5e @@ -0,0 +1,20 @@ +47403a4b4976 ("x86/nmi: Remove an unnecessary IS_ENABLED(CONFIG_SMP)") +8f849ff63bcb ("x86/microcode: Handle "offline" CPUs correctly") +1582c0f4a213 ("x86/microcode: Protect against instrumentation") +7eb314a22800 ("x86/microcode: Rendezvous and load in NMI") +0bf871651211 ("x86/microcode: Replace the all-in-one rendevous handler") +6067788f04b1 ("x86/microcode: Provide new control functions") +ba3aeb97cb2c ("x86/microcode: Add per CPU control field") +4b753955e915 ("x86/microcode: Add per CPU result state") +0772b9aa1a8f ("x86/microcode: Sanitize __wait_for_cpus()") +6f059e634dcd ("x86/microcode: Clarify the late load logic") +634ac23ad609 ("x86/microcode: Handle "nosmt" correctly") +2a1dada3d1cf ("x86/microcode/intel: Save the microcode only after a successful late-load") +dd5e3e3ca6ac ("x86/microcode/intel: Simplify early loading") +0177669ee61d ("x86/microcode/intel: Cleanup code further") +6b072022ab2e ("x86/microcode/intel: Simplify and rename generic_load_microcode()") +b0f0bf5eef5f ("x86/microcode/intel: Simplify scan_microcode()") +ae76d951f653 ("x86/microcode/intel: Rip out mixed stepping support for Intel CPUs") +0b62f6cb0773 ("x86/microcode/32: Move early loading after paging enable") +4c585af7180c ("x86/boot/32: Temporarily map initrd for microcode loading") +a62f4ca106fd ("x86/boot/32: De-uglify the 2/3 level paging difference in mk_early_pgtbl_32()") |