diff options
Diffstat (limited to 'v5.10/b34ae8598c9c3a95e7f8eaeaa1fcf6fdba0aef68')
| -rw-r--r-- | v5.10/b34ae8598c9c3a95e7f8eaeaa1fcf6fdba0aef68 | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/v5.10/b34ae8598c9c3a95e7f8eaeaa1fcf6fdba0aef68 b/v5.10/b34ae8598c9c3a95e7f8eaeaa1fcf6fdba0aef68 new file mode 100644 index 00000000000..fcb045618ea --- /dev/null +++ b/v5.10/b34ae8598c9c3a95e7f8eaeaa1fcf6fdba0aef68 @@ -0,0 +1,20 @@ +b34ae8598c9c ("phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550") +5301b7a04040 ("phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings") +2226ec072ed3 ("phy: qcom-qmp: qserdes-com: Add some more v6 register offsets") +7c4bf8cb9d40 ("phy: qcom: qmp-ufs: add QMP UFS PHY tables for SM8650") +8abe9792d1ff ("phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280") +b102ce6d847a ("phy: qcom: qmp-ufs: add missing offsets to sm8150 configuration") +20b5c6ae18ff ("phy: qcom-qmp-ufs: populate offsets configuration") +607c101fe9f2 ("phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p") +868c2a6ceead ("phy: qcom-qmp-ufs: Add SM7150 support") +1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") +5b8154ce5009 ("phy: qcom-qmp: pcs-ufs: Add v6 register offsets") +c9736600a64f ("phy: qcom-qmp: qserdes-txrx-ufs: Add v6 register offsets") +ddf070f6c9cb ("phy: qcom-qmp: qserdes-txrx: Add v6 register offsets") +2df32d96f2e3 ("phy: qcom-qmp: qserdes-com: Add v6 register offsets") +6900fdf496fd ("phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsets") +2a397a23a565 ("phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC") +8d0fb02ce5c9 ("phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC") +90c64cc05fd6 ("phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC") +692b65516080 ("phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC") +f89dcb24e2ec ("phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC") |