Glossary: Add an entry for "Plain Access"akira.2021.04.04a

The book uses "plain access", so it deserves a glossary entry.
And of course "marked access" is its antonym, more or less.

Reported-by: Akira Yokosawa <akiyks@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
[akiyks: rebased on indexing-scheme branch]

1 files changed, 8 insertions, 4 deletions

diff --git a/glossary.tex b/glossary.tex
index 057d3efd..950c9460 100644
--- a/glossary.tex
+++ b/glossary.tex
@@ -174,11 +174,11 @@
 	A race condition in which several CPUs or threads access
 	a variable concurrently, and in which at least one of those
 	accesses is a store and at least one of those accesses
-	is unmarked.
+	is a plain access.
 	It is important to note that while the presence of data races
 	often indicates the presence of bugs, the absence of data races
 	in no way implies the absence of bugs.
-	(See ``Marked access''.)
+	(See ``Plain access''.)
 \item[\IX{Deadlock Free}:]
 	A forward-progress guarantee in which, in the absence of
 	failures, at least one thread makes progress within a finite
@@ -301,9 +301,9 @@
 	macro, such as \co{READ_ONCE()}, \co{WRITE_ONCE()},
 	\co{atomic_inc()}, and so on, in order to protect that access
 	from compiler and/or hardware optimizations.
-	In contrast, an unmarked access simply mentions the name of
+	In contrast, a plain access simply mentions the name of
 	the object being accessed, so that in the following, line~2
-	is the unmarked equivalent of line~1:
+	is the plain-access equivalent of line~1:
 	\begin{VerbatimN}
 	WRITE_ONCE(a, READ_ONCE(b) + READ_ONCE(c));
 	a = b + c;
@@ -393,6 +393,10 @@
 	In the 1960s through the early 1980s, pipelined CPUs were the
 	province of supercomputers, but started appearing in microprocessors
 	(such as the 80486) in the late 1980s.
+\item[\IX{Plain Access}:]
+	A source-code memory access that simply mentions the name of
+	the object being accessed.
+	(See ``Marked access''.)
 \item[\IX{Process Consistency}:]
 	A memory-consistency model in which each CPU's stores appear to
 	occur in program order, but in which different CPUs might see