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From 4fdaa5e13105cb6702c37f8e8de7650e85cf0e1b Mon Sep 17 00:00:00 2001
From: Wu Zhangjin <wuzhangjin@gmail.com>
Date: Mon, 6 Jul 2009 15:39:03 +0800
Subject: [PATCH] Loongson-2F: Flush the branch target history such as BTB and RAS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
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commit 8235687ddfd6618f6257685f17280bf85db17595 in tip.
As the Chapter 15: "Errata: Issue of Out-of-order in loongson"[1] shows, to
workaround the Issue of Loongson-2F，We need to do:
"When switching from user model to kernel model, you should flush the branch
target history such as BTB and RAS."
This patch did clear BTB(branch target buffer), forbid RAS(row address strobe)
via Loongson-2F's 64bit diagnostic register.
[1] Chinese Version: http://www.loongson.cn/uploadfile/file/200808211
[2] English Version of Chapter 15:
http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/mips/include/asm/stackframe.h | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 58730c5..83e6590 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -100,6 +100,25 @@
#endif
.macro get_saved_sp /* SMP variation */
CPU_ID_MFC0 k0, CPU_ID_REG
+#ifdef CONFIG_CPU_LOONGSON2F
+ /*
+ * Clear BTB(branch target buffer), forbid RAS(row address
+ * strobe) to workaround the Out-of-oder Issue in Loongson2F
+ * via it's diagnostic register.
+ */
+ move k0, ra
+ jal 1f
+ nop
+1: jal 1f
+ nop
+1: jal 1f
+ nop
+1: jal 1f
+ nop
+1: move ra, k0
+ li k0, 3
+ mtc0 k0, $22
+#endif /* CONFIG_CPU_LOONGSON2F */
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
lui k1, %hi(kernelsp)
#else
--
1.7.0.4
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