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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2018-07-03 23:28:42 -0400 |
|---|---|---|
| committer | Paul Gortmaker <paul.gortmaker@windriver.com> | 2018-07-03 23:28:42 -0400 |
| commit | 71d60a0005f82568136ecf6054a67e01cffcacac (patch) | |
| tree | 7b34799e6cdbaf0d968eafc65332432c3b0804cb | |
| parent | 20be7382ce6473722a5dbe94a7bbcd14e0907e93 (diff) | |
| download | longterm-queue-4.12-71d60a0005f82568136ecf6054a67e01cffcacac.tar.gz | |
clk: context refresh
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| -rw-r--r-- | queue/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5.patch | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/queue/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5.patch b/queue/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5.patch index 49c38cd..0370731 100644 --- a/queue/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5.patch +++ b/queue/clk-uniphier-fix-DAPLL2-clock-rate-of-Pro5.patch @@ -1,4 +1,4 @@ -From 67affb78a4e4feb837953e3434c8402a5c3b272f Mon Sep 17 00:00:00 2001 +From a73a281175f0f4757ccef3893fdf6aeffe55281a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada <yamada.masahiro@socionext.com> Date: Thu, 5 Oct 2017 11:32:59 +0900 Subject: [PATCH] clk: uniphier: fix DAPLL2 clock rate of Pro5 @@ -9,12 +9,13 @@ The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c -index 0e396f3da526..bffe095e603a 100644 +index c8027d909429..29e16b1ec52f 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c -@@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { +@@ -111,7 +111,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ @@ -22,7 +23,7 @@ index 0e396f3da526..bffe095e603a 100644 + UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), - UNIPHIER_PRO5_SYS_CLK_NAND(2), + UNIPHIER_SLD3_SYS_CLK_NAND(2), -- 2.15.0 |