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| author | Andre Przywara <andre.przywara@arm.com> | 2022-10-04 15:51:52 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2022-10-04 16:15:24 +0100 |
| commit | c46a09cf1d8e4e34b64f06132acf2effbc85e48d (patch) | |
| tree | e47d9dc8ea0ddfff3a027e4fa22ff098079c5473 | |
| parent | 5aeb34ee72c055d886034c8d0b54c29bd49ad9fb (diff) | |
| download | boot-wrapper-aarch64-c46a09cf1d8e4e34b64f06132acf2effbc85e48d.tar.gz | |
sme: Fix sign-extension bug in SMCR_EL3 write
To enable the full AArch64 ISA support in streaming SVE mode, we need to
set bit 31 in the SMCR_EL3 system register. However ORing (1 << 31) into
an unsigned long variable will lead to all upper 32 bits becoming 1,
which is not what we want. We are just saved by those bits being RES0,
at least for now.
Explicitly use an unsigned base for the shift, to avoid the sign
extension.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Mark: use 'BIT(31)' rather than '(1U << 31)']
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20221004145152.3020464-1-andre.przywara@arm.com/
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index d063948..89a8f78 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -117,7 +117,7 @@ #define ZCR_EL3_LEN_MAX 0xf #define SMCR_EL3 s3_6_c1_c2_6 -#define SMCR_EL3_FA64 (1 << 31) +#define SMCR_EL3_FA64 BIT(31) #define SMCR_EL3_LEN_MAX 0xf #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 |