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| author | Alexandru Elisei <alexandru.elisei@arm.com> | 2020-07-31 10:44:43 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2020-08-12 13:06:04 +0100 |
| commit | 8d5a765251d9113c3c0f9fa14de42a9e7486fe8a (patch) | |
| tree | 3fe2034644bacedf756e6c82da62344a980ff6ee | |
| parent | fd74c8cbd0e17483d2299208cad9742bee605ca7 (diff) | |
| download | boot-wrapper-aarch64-8d5a765251d9113c3c0f9fa14de42a9e7486fe8a.tar.gz | |
aarch64: Enable SPE for the non-secure world
MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the
profiling buffer to use non-secure memory and to permit direct register
accesses from the non-secure world.
So far, we haven't programmed MDCR_EL3 explicitly even though there are
other fields which reset to an UNKNOWN value. The majority of those, when
cleared, allow lower exception levels to use the features they control; for
the other fields we don't have support yet. Reset the register to zero
with the exception of MDCR_EL3.NSPB.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/boot.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index c2fe92c..37f4b98 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -62,6 +62,17 @@ _start: msr cptr_el3, xzr // Disable copro. traps to EL3 + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #32, #4 + cbz x1, 1f + + // Enable SPE for the non-secure world. + ldr x1, =(0x3 << 12) + orr x0, x0, x1 + +1: msr mdcr_el3, x0 // Disable traps to EL3 + mrs x0, id_aa64pfr0_el1 ubfx x0, x0, #32, #4 // SVE present? cbz x0, 1f // Skip SVE init if not |