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| author | Joey Gouly <joey.gouly@arm.com> | 2023-06-16 17:00:35 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2023-06-19 09:31:45 +0100 |
| commit | 226fddeaaa1295688ddbad563b67b1c90113efeb (patch) | |
| tree | e87ef8aa713643524b21a25d568e46cea4e78297 | |
| parent | 9f26a1c1f27bd6b5b66c265114848007fc22e4aa (diff) | |
| download | boot-wrapper-aarch64-226fddeaaa1295688ddbad563b67b1c90113efeb.tar.gz | |
aarch64: enable access to TCR2_ELx
Allow access the TCR2_ELx register which provides extended translation
controls similar to TCR_ELx.
Initialise these registers to a value of 0.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 8 | ||||
| -rw-r--r-- | arch/aarch64/init.c | 6 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 89a8f78..0213d53 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -17,6 +17,9 @@ #define CURRENTEL_EL2 (2 << 2) #define CURRENTEL_EL1 (1 << 2) +#define TCR2_EL2 s3_4_c2_c0_3 +#define TCR2_EL1 s3_0_c2_c0_3 + /* * RES1 bit definitions definitions as of ARM DDI 0487G.b * @@ -51,6 +54,7 @@ #define SCR_EL3_TME BIT(34) #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) +#define SCR_EL3_TCR2EN BIT(43) #define HCR_EL2_RES1 BIT(1) @@ -73,6 +77,8 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) +#define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) + #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) @@ -122,6 +128,8 @@ #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 +#define ID_AA64MMFR3_EL1 s3_0_c0_c7_3 + #define SCTLR_EL1_CP15BEN (1 << 5) #ifdef KERNEL_32 diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 471e234..e09e050 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -64,6 +64,12 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR1_EL1, HCX)) scr |= SCR_EL3_HXEn; + if (mrs_field(ID_AA64MMFR3_EL1, TCRX)) { + scr |= SCR_EL3_TCR2EN; + msr(TCR2_EL2, 0); + msr(TCR2_EL1, 0); + } + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA; |