diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-02 18:50:50 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-08-02 18:50:50 -0700 |
| commit | cd7a3e42ee78f772571a6446699c9d326fcb0320 (patch) | |
| tree | 85750e1a0a70a1dd5d6cf1c88e3e8478fe76b5f8 | |
| parent | 2e19797cebcd5b0261310aac3713075b3021a271 (diff) | |
| download | ltsi-kernel-cd7a3e42ee78f772571a6446699c9d326fcb0320.tar.gz | |
More Renesas patches, but will not all apply cleanly
Needs to be fixed up...
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
287 files changed, 39089 insertions, 0 deletions
diff --git a/patches.renesas/0001-clocksource-em_sti-Split-clock-prepare-and-enable-st.patch b/patches.renesas/0001-clocksource-em_sti-Split-clock-prepare-and-enable-st.patch new file mode 100644 index 00000000000000..4c0a8cbfd89d10 --- /dev/null +++ b/patches.renesas/0001-clocksource-em_sti-Split-clock-prepare-and-enable-st.patch @@ -0,0 +1,90 @@ +From a2e54bf8c7bbfc421b16e28fd2ea7770d1c11cf5 Mon Sep 17 00:00:00 2001 +From: Nicolai Stange <nicstange@gmail.com> +Date: Mon, 6 Feb 2017 22:12:01 +0100 +Subject: [PATCH 001/286] clocksource: em_sti: Split clock prepare and enable + steps + +Currently, the em_sti driver prepares and enables the needed clock in +em_sti_enable(), potentially called through its clockevent device's +->set_state_oneshot(). + +However, the clk_prepare() step may sleep whereas tick_program_event() and +thus, ->set_state_oneshot(), can be called in atomic context. + +Split the clk_prepare_enable() in em_sti_enable() into two steps: +- prepare the clock at device probing via clk_prepare() +- and enable it in em_sti_enable() via clk_enable(). +Slightly reorder resource initialization in em_sti_probe() in order to +facilitate error handling in later patches. + +Signed-off-by: Nicolai Stange <nicstange@gmail.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +(cherry picked from commit 3814ae092d36da04d5fbaf777c1564dc4ee68559) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/em_sti.c | 21 ++++++++++++++------- + 1 file changed, 14 insertions(+), 7 deletions(-) + +diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c +index 19bb1792d647..51a346c91a98 100644 +--- a/drivers/clocksource/em_sti.c ++++ b/drivers/clocksource/em_sti.c +@@ -78,7 +78,7 @@ static int em_sti_enable(struct em_sti_priv *p) + int ret; + + /* enable clock */ +- ret = clk_prepare_enable(p->clk); ++ ret = clk_enable(p->clk); + if (ret) { + dev_err(&p->pdev->dev, "cannot enable clock\n"); + return ret; +@@ -107,7 +107,7 @@ static void em_sti_disable(struct em_sti_priv *p) + em_sti_write(p, STI_INTENCLR, 3); + + /* stop clock */ +- clk_disable_unprepare(p->clk); ++ clk_disable(p->clk); + } + + static cycle_t em_sti_count(struct em_sti_priv *p) +@@ -303,6 +303,7 @@ static int em_sti_probe(struct platform_device *pdev) + struct em_sti_priv *p; + struct resource *res; + int irq; ++ int ret; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (p == NULL) +@@ -323,6 +324,13 @@ static int em_sti_probe(struct platform_device *pdev) + if (IS_ERR(p->base)) + return PTR_ERR(p->base); + ++ if (devm_request_irq(&pdev->dev, irq, em_sti_interrupt, ++ IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, ++ dev_name(&pdev->dev), p)) { ++ dev_err(&pdev->dev, "failed to request low IRQ\n"); ++ return -ENOENT; ++ } ++ + /* get hold of clock */ + p->clk = devm_clk_get(&pdev->dev, "sclk"); + if (IS_ERR(p->clk)) { +@@ -330,11 +338,10 @@ static int em_sti_probe(struct platform_device *pdev) + return PTR_ERR(p->clk); + } + +- if (devm_request_irq(&pdev->dev, irq, em_sti_interrupt, +- IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, +- dev_name(&pdev->dev), p)) { +- dev_err(&pdev->dev, "failed to request low IRQ\n"); +- return -ENOENT; ++ ret = clk_prepare(p->clk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "cannot prepare clock\n"); ++ return ret; + } + + raw_spin_lock_init(&p->lock); +-- +2.13.3 + diff --git a/patches.renesas/0002-clocksource-em_sti-Compute-rate-before-registration.patch b/patches.renesas/0002-clocksource-em_sti-Compute-rate-before-registration.patch new file mode 100644 index 00000000000000..2f24ccd95e7b46 --- /dev/null +++ b/patches.renesas/0002-clocksource-em_sti-Compute-rate-before-registration.patch @@ -0,0 +1,111 @@ +From 0e0354a566fd8c79628ed603cf9fc909461c9b84 Mon Sep 17 00:00:00 2001 +From: Nicolai Stange <nicstange@gmail.com> +Date: Mon, 6 Feb 2017 22:12:02 +0100 +Subject: [PATCH 002/286] clocksource: em_sti: Compute rate before registration + +With the upcoming NTP correction related rate adjustments to be implemented +in the clockevents core, the latter needs to get informed about every rate +change of a clockevent device made after its registration. + +Currently, em_sti violates this requirement in that it registers its +clockevent device with a dummy rate and sets its final rate through +clockevents_config() called from its ->set_state_oneshot(). + +This patch moves the setting of the clockevent device's rate to its +registration. + +I checked all current em_sti users in arch/arm/mach-shmobile and right now, +none of them changes any rate in any clock tree relevant to em_sti after +their respective time_init(). Since all em_sti instances are created after +time_init(), none of them should ever observe any clock rate changes. + +- Determine the ->rate value in em_sti_probe() at device probing rather + than at first usage. +- Set the clockevent device's rate at its registration. +- Although not strictly necessary for the upcoming clockevent core changes, + set the clocksource's rate at its registration for consistency. + +Signed-off-by: Nicolai Stange <nicstange@gmail.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +(cherry picked from commit 4e53aa2fde4124878fc6b2183d6e8ec46e12ceb0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/em_sti.c | 25 ++++++++++++------------- + 1 file changed, 12 insertions(+), 13 deletions(-) + +diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c +index 51a346c91a98..e1d465239042 100644 +--- a/drivers/clocksource/em_sti.c ++++ b/drivers/clocksource/em_sti.c +@@ -84,9 +84,6 @@ static int em_sti_enable(struct em_sti_priv *p) + return ret; + } + +- /* configure channel, periodic mode and maximum timeout */ +- p->rate = clk_get_rate(p->clk); +- + /* reset the counter */ + em_sti_write(p, STI_SET_H, 0x40000000); + em_sti_write(p, STI_SET_L, 0x00000000); +@@ -205,13 +202,9 @@ static cycle_t em_sti_clocksource_read(struct clocksource *cs) + + static int em_sti_clocksource_enable(struct clocksource *cs) + { +- int ret; + struct em_sti_priv *p = cs_to_em_sti(cs); + +- ret = em_sti_start(p, USER_CLOCKSOURCE); +- if (!ret) +- __clocksource_update_freq_hz(cs, p->rate); +- return ret; ++ return em_sti_start(p, USER_CLOCKSOURCE); + } + + static void em_sti_clocksource_disable(struct clocksource *cs) +@@ -240,8 +233,7 @@ static int em_sti_register_clocksource(struct em_sti_priv *p) + + dev_info(&p->pdev->dev, "used as clock source\n"); + +- /* Register with dummy 1 Hz value, gets updated in ->enable() */ +- clocksource_register_hz(cs, 1); ++ clocksource_register_hz(cs, p->rate); + return 0; + } + +@@ -263,7 +255,6 @@ static int em_sti_clock_event_set_oneshot(struct clock_event_device *ced) + + dev_info(&p->pdev->dev, "used for oneshot clock events\n"); + em_sti_start(p, USER_CLOCKEVENT); +- clockevents_config(&p->ced, p->rate); + return 0; + } + +@@ -294,8 +285,7 @@ static void em_sti_register_clockevent(struct em_sti_priv *p) + + dev_info(&p->pdev->dev, "used for clock events\n"); + +- /* Register with dummy 1 Hz value, gets updated in ->set_state_oneshot() */ +- clockevents_config_and_register(ced, 1, 2, 0xffffffff); ++ clockevents_config_and_register(ced, p->rate, 2, 0xffffffff); + } + + static int em_sti_probe(struct platform_device *pdev) +@@ -344,6 +334,15 @@ static int em_sti_probe(struct platform_device *pdev) + return ret; + } + ++ ret = clk_enable(p->clk); ++ if (ret < 0) { ++ dev_err(&p->pdev->dev, "cannot enable clock\n"); ++ clk_unprepare(p->clk); ++ return ret; ++ } ++ p->rate = clk_get_rate(p->clk); ++ clk_disable(p->clk); ++ + raw_spin_lock_init(&p->lock); + em_sti_register_clockevent(p); + em_sti_register_clocksource(p); +-- +2.13.3 + diff --git a/patches.renesas/0003-arm64-dts-r8a7796-Add-I2C-for-DVFS-device-node.patch b/patches.renesas/0003-arm64-dts-r8a7796-Add-I2C-for-DVFS-device-node.patch new file mode 100644 index 00000000000000..638e73c47bef55 --- /dev/null +++ b/patches.renesas/0003-arm64-dts-r8a7796-Add-I2C-for-DVFS-device-node.patch @@ -0,0 +1,52 @@ +From 12d77c1aa293e03e71546c6fbc82badc653de5c1 Mon Sep 17 00:00:00 2001 +From: Dien Pham <dien.pham.ry@rvc.renesas.com> +Date: Thu, 26 Jan 2017 09:52:27 +0100 +Subject: [PATCH 003/286] arm64: dts: r8a7796: Add I2C for DVFS device node + +This patch adds I2C for DVFS device node for R8A7796 SoC. + +Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 0fb1fd20043f619e444720062e61cdc40130c0c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index f7120cdedd0d..c95ad177b097 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -25,6 +25,7 @@ + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; ++ i2c7 = &i2c_dvfs; + }; + + psci { +@@ -269,6 +270,19 @@ + #power-domain-cells = <1>; + }; + ++ i2c_dvfs: i2c@e60b0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,iic-r8a7796", ++ "renesas,rcar-gen3-iic", ++ "renesas,rmobile-iic"; ++ reg = <0 0xe60b0000 0 0x425>; ++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 926>; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0004-arm64-dts-r8a7796-salvator-x-Add-I2C-for-DVFS-device.patch b/patches.renesas/0004-arm64-dts-r8a7796-salvator-x-Add-I2C-for-DVFS-device.patch new file mode 100644 index 00000000000000..d299391955a15b --- /dev/null +++ b/patches.renesas/0004-arm64-dts-r8a7796-salvator-x-Add-I2C-for-DVFS-device.patch @@ -0,0 +1,34 @@ +From 703192ae09064fa24ff84c04174774d313715df7 Mon Sep 17 00:00:00 2001 +From: Dien Pham <dien.pham.ry@rvc.renesas.com> +Date: Thu, 26 Jan 2017 09:52:28 +0100 +Subject: [PATCH 004/286] arm64: dts: r8a7796: salvator-x: Add I2C for DVFS + device support + +This patch adds support of I2C for DVFS device for Salvator-X board on +R8A7796 SoC. + +Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit d8e62f0729bb404caa6ba42b65d5a1e4d370a6e3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +index c7f40f8f3169..61f4662db497 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -261,3 +261,7 @@ + timeout-sec = <60>; + status = "okay"; + }; ++ ++&i2c_dvfs { ++ status = "okay"; ++}; +-- +2.13.3 + diff --git a/patches.renesas/0005-arm64-dts-r8a7795-Add-I2C-for-DVFS-core-to-dtsi.patch b/patches.renesas/0005-arm64-dts-r8a7795-Add-I2C-for-DVFS-core-to-dtsi.patch new file mode 100644 index 00000000000000..8f026d90f323df --- /dev/null +++ b/patches.renesas/0005-arm64-dts-r8a7795-Add-I2C-for-DVFS-core-to-dtsi.patch @@ -0,0 +1,54 @@ +From 43ac3b64dfa4aba65d9254a5638dc39b1e8bb1a2 Mon Sep 17 00:00:00 2001 +From: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Date: Thu, 26 Jan 2017 09:52:29 +0100 +Subject: [PATCH 005/286] arm64: dts: r8a7795: Add I2C for DVFS core to dtsi + +This patch adds I2C for DVFS device support for R8A7795 SoC. + +Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> +Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit d7e0d64a46f97f67ecbc0194ce6a394f512109c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index eac4f29aa5cd..fe266bb3d913 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -25,6 +25,7 @@ + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; ++ i2c7 = &i2c_dvfs; + }; + + psci { +@@ -793,6 +794,19 @@ + status = "disabled"; + }; + ++ i2c_dvfs: i2c@e60b0000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "renesas,iic-r8a7795", ++ "renesas,rcar-gen3-iic", ++ "renesas,rmobile-iic"; ++ reg = <0 0xe60b0000 0 0x425>; ++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 926>; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0006-arm64-dts-r8a7795-salvator-x-Enable-I2C-for-DVFS-dev.patch b/patches.renesas/0006-arm64-dts-r8a7795-salvator-x-Enable-I2C-for-DVFS-dev.patch new file mode 100644 index 00000000000000..c345566efdafa2 --- /dev/null +++ b/patches.renesas/0006-arm64-dts-r8a7795-salvator-x-Enable-I2C-for-DVFS-dev.patch @@ -0,0 +1,37 @@ +From 8cc947bf0ad234059dcec0b0913745e7a0cd384a Mon Sep 17 00:00:00 2001 +From: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Date: Thu, 26 Jan 2017 09:52:30 +0100 +Subject: [PATCH 006/286] arm64: dts: r8a7795: salvator-x: Enable I2C for DVFS + device + +This patch enables I2C for DVFS device for for Salvator-X board on +R8A7795 SoC. + +Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 006ced572a3b2247639ce06443aff00704888001) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index 7a8986edcdc0..dc1177c76aa5 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -485,6 +485,10 @@ + clock-frequency = <22579200>; + }; + ++&i2c_dvfs { ++ status = "okay"; ++}; ++ + &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; +-- +2.13.3 + diff --git a/patches.renesas/0007-arm64-dts-h3ulcb-Update-memory-node-to-4-GiB-map.patch b/patches.renesas/0007-arm64-dts-h3ulcb-Update-memory-node-to-4-GiB-map.patch new file mode 100644 index 00000000000000..35e9d290e3649c --- /dev/null +++ b/patches.renesas/0007-arm64-dts-h3ulcb-Update-memory-node-to-4-GiB-map.patch @@ -0,0 +1,54 @@ +From a1e5a69fcc15a90127c60a0b4289f1e173b86284 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> +Date: Thu, 26 Jan 2017 18:13:52 +0300 +Subject: [PATCH 007/286] arm64: dts: h3ulcb: Update memory node to 4 GiB map + +This patch adds memory region: + + - After changes, the H3ULCB board has the following map: + Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff + Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff + Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff + Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff + + - Before changes, the old map looked like this: + Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff + +Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a262d66224c4c34bc2bee16d4d37d460a738788c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +index c5f8f69a4f5f..9811534f296e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +@@ -33,6 +33,21 @@ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + ++ memory@500000000 { ++ device_type = "memory"; ++ reg = <0x5 0x00000000 0x0 0x40000000>; ++ }; ++ ++ memory@600000000 { ++ device_type = "memory"; ++ reg = <0x6 0x00000000 0x0 0x40000000>; ++ }; ++ ++ memory@700000000 { ++ device_type = "memory"; ++ reg = <0x7 0x00000000 0x0 0x40000000>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +-- +2.13.3 + diff --git a/patches.renesas/0008-arm64-dts-r8a7795-Use-rgmii-txid-phy-mode-for-Ethern.patch b/patches.renesas/0008-arm64-dts-r8a7795-Use-rgmii-txid-phy-mode-for-Ethern.patch new file mode 100644 index 00000000000000..c7bbbb405cd2b4 --- /dev/null +++ b/patches.renesas/0008-arm64-dts-r8a7795-Use-rgmii-txid-phy-mode-for-Ethern.patch @@ -0,0 +1,56 @@ +From b731f5be9342650b498665e13e4de21b63612de6 Mon Sep 17 00:00:00 2001 +From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Date: Wed, 1 Feb 2017 09:42:00 +0100 +Subject: [PATCH 008/286] arm64: dts: r8a7795: Use rgmii-txid phy-mode for + EthernetAVB + +Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode +of APSR") the EthernetAVB driver enables tx and rx clock internal delay +modes (TDM and RDM) depending on the phy mode as follows: + + phy mode | ASPR delay mode + -----------+---------------- + rgmii-id | TDM and RDM + rgmii-rxid | RDM + rgmii-txid | TDM + +And prior to the above commit no internal delay mode settings were +implemented for any phy mode. + +With this and the above change present tx internal delay mode is enabled +which has been observed to address failures in the case of 1Gbps +communication using the by salvator-x board with the KSZ9031RNX phy. This +has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) +SoCs. + +With the above patch present but this patch present tx and rx internal +delay modes are enabled; and with the above patch and this present absent +no internal delay modes are enabled. In both cases failures have been +observed when using 1Gbps communication in the environments described +above. + +Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dda3887907d743385f2599fa18c765bd295ae2da) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index fe266bb3d913..382a8987bca9 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -564,7 +564,7 @@ + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +- phy-mode = "rgmii-id"; ++ phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +-- +2.13.3 + diff --git a/patches.renesas/0009-arm64-dts-r8a7795-salvator-x-Fix-EthernetAVB-PHY-tim.patch b/patches.renesas/0009-arm64-dts-r8a7795-salvator-x-Fix-EthernetAVB-PHY-tim.patch new file mode 100644 index 00000000000000..a126d46e6ca070 --- /dev/null +++ b/patches.renesas/0009-arm64-dts-r8a7795-salvator-x-Fix-EthernetAVB-PHY-tim.patch @@ -0,0 +1,48 @@ +From 9d19633139ba2d394bd7d27827a40f810845a32b Mon Sep 17 00:00:00 2001 +From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Date: Wed, 1 Feb 2017 09:42:01 +0100 +Subject: [PATCH 009/286] arm64: dts: r8a7795: salvator-x: Fix EthernetAVB PHY + timing + +Set PHY rxc-skew-ps to 1500 and all other values to their default values. + +This is intended to to address failures in the case of 1Gbps communication +using the by salvator-x board with the KSZ9031RNX phy. This has been +reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. + +Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 0e45da1c6ea6b18616d95c697ecd6234bc504ef6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index dc1177c76aa5..5158ba3f9ce3 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -497,18 +497,7 @@ + status = "okay"; + + phy0: ethernet-phy@0 { +- rxc-skew-ps = <900>; +- rxdv-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txc-skew-ps = <900>; +- txen-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; ++ rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +-- +2.13.3 + diff --git a/patches.renesas/0010-arm64-dts-h3ulcb-Fix-EthernetAVB-PHY-timing.patch b/patches.renesas/0010-arm64-dts-h3ulcb-Fix-EthernetAVB-PHY-timing.patch new file mode 100644 index 00000000000000..a0c5eed09c9946 --- /dev/null +++ b/patches.renesas/0010-arm64-dts-h3ulcb-Fix-EthernetAVB-PHY-timing.patch @@ -0,0 +1,46 @@ +From 3e30b73fbad9de8c9f84a5c43066cff94ab7d5c8 Mon Sep 17 00:00:00 2001 +From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Date: Wed, 1 Feb 2017 09:42:02 +0100 +Subject: [PATCH 010/286] arm64: dts: h3ulcb: Fix EthernetAVB PHY timing + +Set PHY rxc-skew-ps to 1500 and all other values to their default values. + +This is intended to to address failures in the case of 1Gbps communication +using the by h3ulcb board with the KSZ9031RNX phy. + +Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5b9fd1962f605a31842371471e559407c293131f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +index 9811534f296e..69c623faf80c 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +@@ -354,18 +354,7 @@ + status = "okay"; + + phy0: ethernet-phy@0 { +- rxc-skew-ps = <900>; +- rxdv-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txc-skew-ps = <900>; +- txen-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; ++ rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +-- +2.13.3 + diff --git a/patches.renesas/0011-arm64-dts-r8a7796-Use-rgmii-txid-phy-mode-for-Ethern.patch b/patches.renesas/0011-arm64-dts-r8a7796-Use-rgmii-txid-phy-mode-for-Ethern.patch new file mode 100644 index 00000000000000..ecfe3e3e912a3d --- /dev/null +++ b/patches.renesas/0011-arm64-dts-r8a7796-Use-rgmii-txid-phy-mode-for-Ethern.patch @@ -0,0 +1,56 @@ +From fba4075b8b42f6bc778148c334fdc92bf4ef95a2 Mon Sep 17 00:00:00 2001 +From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Date: Wed, 1 Feb 2017 09:42:03 +0100 +Subject: [PATCH 011/286] arm64: dts: r8a7796: Use rgmii-txid phy-mode for + EthernetAVB + +Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode +of APSR") the EthernetAVB driver enables tx and rx clock internal delay +modes (TDM and RDM) depending on the phy mode as follows: + + phy mode | ASPR delay mode + -----------+---------------- + rgmii-id | TDM and RDM + rgmii-rxid | RDM + rgmii-txid | TDM + +And prior to the above commit no internal delay mode settings were +implemented for any phy mode. + +With this and the above change present tx internal delay mode is enabled +which has been observed to address failures in the case of 1Gbps +communication using the by salvator-x board with the KSZ9031RNX phy. This +has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) +SoCs. + +With the above patch present but this patch present tx and rx internal +delay modes are enabled; and with the above patch and this present absent +no internal delay modes are enabled. In both cases failures have been +observed when using 1Gbps communication in the environments described +above. + +Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 325f39010b431f6a1ece74d69f10dcca2329c08d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index c95ad177b097..1c1c1eae9cba 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -483,7 +483,7 @@ + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +- phy-mode = "rgmii-id"; ++ phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +-- +2.13.3 + diff --git a/patches.renesas/0012-arm64-dts-r8a7796-salvator-x-Fix-EthernetAVB-PHY-tim.patch b/patches.renesas/0012-arm64-dts-r8a7796-salvator-x-Fix-EthernetAVB-PHY-tim.patch new file mode 100644 index 00000000000000..0c11d655d16b05 --- /dev/null +++ b/patches.renesas/0012-arm64-dts-r8a7796-salvator-x-Fix-EthernetAVB-PHY-tim.patch @@ -0,0 +1,48 @@ +From 849cb9f03570b13a3581e9348962f13b88477556 Mon Sep 17 00:00:00 2001 +From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Date: Wed, 1 Feb 2017 09:42:04 +0100 +Subject: [PATCH 012/286] arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY + timing + +Set PHY rxc-skew-ps to 1500 and all other values to their default values. + +This is intended to to address failures in the case of 1Gbps communication +using the by salvator-x board with the KSZ9031RNX phy. This has been +reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. + +Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ef3f08c83fd186ab4bbad6a6250c5a347fbf6551) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +index 61f4662db497..93ed23ab71bb 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -172,18 +172,7 @@ + status = "okay"; + + phy0: ethernet-phy@0 { +- rxc-skew-ps = <900>; +- rxdv-skew-ps = <0>; +- rxd0-skew-ps = <0>; +- rxd1-skew-ps = <0>; +- rxd2-skew-ps = <0>; +- rxd3-skew-ps = <0>; +- txc-skew-ps = <900>; +- txen-skew-ps = <0>; +- txd0-skew-ps = <0>; +- txd1-skew-ps = <0>; +- txd2-skew-ps = <0>; +- txd3-skew-ps = <0>; ++ rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +-- +2.13.3 + diff --git a/patches.renesas/0013-arm64-defconfig-Enable-SH-Mobile-I2C-controller.patch b/patches.renesas/0013-arm64-defconfig-Enable-SH-Mobile-I2C-controller.patch new file mode 100644 index 00000000000000..c85ecbc2cb505d --- /dev/null +++ b/patches.renesas/0013-arm64-defconfig-Enable-SH-Mobile-I2C-controller.patch @@ -0,0 +1,34 @@ +From 5b19e15eca49afdf6fd7e521d656bde071f42a19 Mon Sep 17 00:00:00 2001 +From: Simon Horman <horms+renesas@verge.net.au> +Date: Thu, 26 Jan 2017 09:52:26 +0100 +Subject: [PATCH 013/286] arm64: defconfig: Enable SH Mobile I2C controller + +Enable SH Mobile I2C controller for use on R-Car Gen3 SoCs. + +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 58e7696e0e3c085804fb6754a7dadf7267d0fa77) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + arch/arm64/configs/defconfig +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 8447beac5570..908fcffb4233 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -234,6 +234,7 @@ CONFIG_I2C_IMX=y + CONFIG_I2C_MESON=y + CONFIG_I2C_MV64XXX=y + CONFIG_I2C_QUP=y ++CONFIG_I2C_SH_MOBILE=y + CONFIG_I2C_TEGRA=y + CONFIG_I2C_UNIPHIER_F=y + CONFIG_I2C_RCAR=y +-- +2.13.3 + diff --git a/patches.renesas/0014-ARM64-defconfig-enable-the-leds-pwm-driver-and-defau.patch b/patches.renesas/0014-ARM64-defconfig-enable-the-leds-pwm-driver-and-defau.patch new file mode 100644 index 00000000000000..08b6cb784ba926 --- /dev/null +++ b/patches.renesas/0014-ARM64-defconfig-enable-the-leds-pwm-driver-and-defau.patch @@ -0,0 +1,38 @@ +From ec260662b3d8c65793ac239f778dc8f3c2c01e34 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Date: Sun, 19 Feb 2017 23:23:25 +0100 +Subject: [PATCH 014/286] ARM64: defconfig: enable the leds-pwm driver and + default-on trigger + +This enables the leds-pwm driver to support LEDs which are PWM-powered +(and thus dimmable). Additionally we have to enable the "default-on" +trigger - this was not required before because the gpio-leds driver has +a separate "default-state" property which can be used to enable the LED +by default. + +Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> +Signed-off-by: Kevin Hilman <khilman@baylibre.com> +(cherry picked from commit 95fbe8b08b2d420e4f5a77701f165d6b23827862) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 908fcffb4233..c11c1473dad0 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -370,8 +370,10 @@ CONFIG_MMC_SUNXI=y + CONFIG_NEW_LEDS=y + CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_PWM=y + CONFIG_LEDS_SYSCON=y + CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + CONFIG_LEDS_TRIGGER_HEARTBEAT=y + CONFIG_LEDS_TRIGGER_CPU=y + CONFIG_RTC_CLASS=y +-- +2.13.3 + diff --git a/patches.renesas/0015-arm64-dts-r8a7796-dtsi-Add-all-HSCIF-nodes.patch b/patches.renesas/0015-arm64-dts-r8a7796-dtsi-Add-all-HSCIF-nodes.patch new file mode 100644 index 00000000000000..6a255dcf75e6e9 --- /dev/null +++ b/patches.renesas/0015-arm64-dts-r8a7796-dtsi-Add-all-HSCIF-nodes.patch @@ -0,0 +1,103 @@ +From ad5326e9d9fb1e5818c5b4f9da3d8306d6b2b21b Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 7 Dec 2016 17:44:47 +0100 +Subject: [PATCH 015/286] arm64: dts: r8a7796 dtsi: Add all HSCIF nodes + +Add the device nodes for all HSCIF serial ports, incl. clocks, and +power domain. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +[simon: express register size in hex; refer to power domain in changelog] +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 68cd161072605c276d4e6c8cd06fbe7b00a0f680) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++ + 1 file changed, 70 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 1c1c1eae9cba..714fd96b29eb 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -489,6 +489,76 @@ + status = "disabled"; + }; + ++ hscif0: serial@e6540000 { ++ compatible = "renesas,hscif-r8a7796", ++ "renesas,rcar-gen3-hscif", ++ "renesas,hscif"; ++ reg = <0 0xe6540000 0 0x60>; ++ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 520>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ hscif1: serial@e6550000 { ++ compatible = "renesas,hscif-r8a7796", ++ "renesas,rcar-gen3-hscif", ++ "renesas,hscif"; ++ reg = <0 0xe6550000 0 0x60>; ++ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 519>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ hscif2: serial@e6560000 { ++ compatible = "renesas,hscif-r8a7796", ++ "renesas,rcar-gen3-hscif", ++ "renesas,hscif"; ++ reg = <0 0xe6560000 0 0x60>; ++ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 518>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ hscif3: serial@e66a0000 { ++ compatible = "renesas,hscif-r8a7796", ++ "renesas,rcar-gen3-hscif", ++ "renesas,hscif"; ++ reg = <0 0xe66a0000 0 0x60>; ++ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 517>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ hscif4: serial@e66b0000 { ++ compatible = "renesas,hscif-r8a7796", ++ "renesas,rcar-gen3-hscif", ++ "renesas,hscif"; ++ reg = <0 0xe66b0000 0 0x60>; ++ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 516>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; +-- +2.13.3 + diff --git a/patches.renesas/0016-arm64-dts-r8a7796-Add-all-SCIF-nodes.patch b/patches.renesas/0016-arm64-dts-r8a7796-Add-all-SCIF-nodes.patch new file mode 100644 index 00000000000000..8421946df65624 --- /dev/null +++ b/patches.renesas/0016-arm64-dts-r8a7796-Add-all-SCIF-nodes.patch @@ -0,0 +1,103 @@ +From 8949f820fadbd95083aa0f900272814c1579f4da Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 7 Dec 2016 17:44:26 +0100 +Subject: [PATCH 016/286] arm64: dts: r8a7796: Add all SCIF nodes + +Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks +and power domain. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 19d76f3ec8fc6ff38f1c5ca534d75a957c8661ea) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 ++++++++++++++++++++++++++++++++ + 1 file changed, 65 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 714fd96b29eb..5fb93fc043c2 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -559,6 +559,32 @@ + status = "disabled"; + }; + ++ scif0: serial@e6e60000 { ++ compatible = "renesas,scif-r8a7796", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6e60000 0 64>; ++ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 207>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ scif1: serial@e6e68000 { ++ compatible = "renesas,scif-r8a7796", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6e68000 0 64>; ++ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 206>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; +@@ -572,6 +598,45 @@ + status = "disabled"; + }; + ++ scif3: serial@e6c50000 { ++ compatible = "renesas,scif-r8a7796", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6c50000 0 64>; ++ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 204>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ scif4: serial@e6c40000 { ++ compatible = "renesas,scif-r8a7796", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6c40000 0 64>; ++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 203>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ ++ scif5: serial@e6f30000 { ++ compatible = "renesas,scif-r8a7796", ++ "renesas,rcar-gen3-scif", "renesas,scif"; ++ reg = <0 0xe6f30000 0 64>; ++ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_MOD 202>, ++ <&cpg CPG_CORE R8A7796_CLK_S3D1>, ++ <&scif_clk>; ++ clock-names = "fck", "brg_int", "scif_clk"; ++ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ status = "disabled"; ++ }; ++ + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; +-- +2.13.3 + diff --git a/patches.renesas/0017-arm64-dts-r8a7796-Enable-SCIF-DMA.patch b/patches.renesas/0017-arm64-dts-r8a7796-Enable-SCIF-DMA.patch new file mode 100644 index 00000000000000..9c6ef7863a4844 --- /dev/null +++ b/patches.renesas/0017-arm64-dts-r8a7796-Enable-SCIF-DMA.patch @@ -0,0 +1,69 @@ +From e4f535b3c4be699cdb91b9c4c3ffc39668b821c9 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 7 Dec 2016 17:44:27 +0100 +Subject: [PATCH 017/286] arm64: dts: r8a7796: Enable SCIF DMA + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dbcae5ea4bd27409291e3329c9106f37f0118590) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 5fb93fc043c2..951e351ddae1 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -568,6 +568,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x51>, <&dmac1 0x50>, ++ <&dmac2 0x51>, <&dmac2 0x50>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -581,6 +584,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x53>, <&dmac1 0x52>, ++ <&dmac2 0x53>, <&dmac2 0x52>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -607,6 +613,8 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac0 0x57>, <&dmac0 0x56>; ++ dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -620,6 +628,8 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac0 0x59>, <&dmac0 0x58>; ++ dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -633,6 +643,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, ++ <&dmac2 0x5b>, <&dmac2 0x5a>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0018-arm64-dts-r8a7796-salvator-x-add-SCIF1-DEBUG1.patch b/patches.renesas/0018-arm64-dts-r8a7796-salvator-x-add-SCIF1-DEBUG1.patch new file mode 100644 index 00000000000000..c506f3fc2b1837 --- /dev/null +++ b/patches.renesas/0018-arm64-dts-r8a7796-salvator-x-add-SCIF1-DEBUG1.patch @@ -0,0 +1,58 @@ +From 1c78d614357aa51833a3fd179eaab71aba45a3cd Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Fri, 3 Feb 2017 11:38:20 +0100 +Subject: [PATCH 018/286] arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) + +Enables the SCIF hooked up to the DEBUG1 connector. + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d5566d251f5e839e36db8db8105d8f8f57e54768) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +index 93ed23ab71bb..74b8c653c9fe 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -18,6 +18,7 @@ + + aliases { + serial0 = &scif2; ++ serial1 = &scif1; + ethernet0 = &avb; + }; + +@@ -113,6 +114,11 @@ + function = "avb"; + }; + ++ scif1_pins: scif1 { ++ groups = "scif1_data_a", "scif1_ctrl"; ++ function = "scif1"; ++ }; ++ + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; +@@ -228,6 +234,14 @@ + status = "okay"; + }; + ++&scif1 { ++ pinctrl-0 = <&scif1_pins>; ++ pinctrl-names = "default"; ++ ++ uart-has-rtscts; ++ status = "okay"; ++}; ++ + &scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; +-- +2.13.3 + diff --git a/patches.renesas/0019-arm64-dts-r8a7796-Enable-HSCIF-DMA.patch b/patches.renesas/0019-arm64-dts-r8a7796-Enable-HSCIF-DMA.patch new file mode 100644 index 00000000000000..54084b14b17599 --- /dev/null +++ b/patches.renesas/0019-arm64-dts-r8a7796-Enable-HSCIF-DMA.patch @@ -0,0 +1,69 @@ +From 960c270de35d28eabaa41b1b70233573e87f5357 Mon Sep 17 00:00:00 2001 +From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Date: Wed, 7 Dec 2016 17:44:48 +0100 +Subject: [PATCH 019/286] arm64: dts: r8a7796: Enable HSCIF DMA + +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6d50bb8935042c4b7747b57df064ff41295e4769) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 951e351ddae1..aa404ed9142e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -499,6 +499,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x31>, <&dmac1 0x30>, ++ <&dmac2 0x31>, <&dmac2 0x30>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -513,6 +516,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x33>, <&dmac1 0x32>, ++ <&dmac2 0x33>, <&dmac2 0x32>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -527,6 +533,9 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac1 0x35>, <&dmac1 0x34>, ++ <&dmac2 0x35>, <&dmac2 0x34>; ++ dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -541,6 +550,8 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac0 0x37>, <&dmac0 0x36>; ++ dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +@@ -555,6 +566,8 @@ + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; ++ dmas = <&dmac0 0x39>, <&dmac0 0x38>; ++ dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0020-arm64-dts-r8a7795-Add-Cortex-A53-CPU-cores.patch b/patches.renesas/0020-arm64-dts-r8a7795-Add-Cortex-A53-CPU-cores.patch new file mode 100644 index 00000000000000..ac17d08be11074 --- /dev/null +++ b/patches.renesas/0020-arm64-dts-r8a7795-Add-Cortex-A53-CPU-cores.patch @@ -0,0 +1,95 @@ +From 57e1fdd47fccc40ea526e983dbf5332d31c37522 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 24 Feb 2017 14:59:27 +0100 +Subject: [PATCH 020/286] arm64: dts: r8a7795: Add Cortex-A53 CPU cores + +This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 +cores (4 x Cortex-A57 + 4 x Cortex-A53). + +Based on work by Takeshi Kihara and Dirk Behme. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 799a75abdef348500bab14e873e7711afa426aaf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 ++++++++++++++++++++++++++++---- + 1 file changed, 41 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 382a8987bca9..61830697e33c 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -73,6 +73,42 @@ + enable-method = "psci"; + }; + ++ a53_0: cpu@100 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x100>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_1: cpu@101 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x101>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7795_PD_CA53_CPU1>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_2: cpu@102 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x102>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7795_PD_CA53_CPU2>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_3: cpu@103 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x103>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7795_PD_CA53_CPU3>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ + L2_CA57: cache-controller@0 { + compatible = "cache"; + reg = <0>; +@@ -166,7 +202,7 @@ + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 +- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +@@ -307,13 +343,13 @@ + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 +- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 +- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 +- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 +- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; ++ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { +-- +2.13.3 + diff --git a/patches.renesas/0021-arm64-dts-r8a7795-Add-Cortex-A53-PMU-node.patch b/patches.renesas/0021-arm64-dts-r8a7795-Add-Cortex-A53-PMU-node.patch new file mode 100644 index 00000000000000..87644d03079f9e --- /dev/null +++ b/patches.renesas/0021-arm64-dts-r8a7795-Add-Cortex-A53-PMU-node.patch @@ -0,0 +1,44 @@ +From a691805bccb105f7bd61f1bd77c9032250119e31 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 24 Feb 2017 14:59:28 +0100 +Subject: [PATCH 021/286] arm64: dts: r8a7795: Add Cortex-A53 PMU node + +Enable the performance monitor unit for the Cortex-A53 cores on the +R8A7795 SoC. + +Extracted from a patch by Takeshi Kihara in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9190748fd608dc3aa80edacab9e6818f2d6f71b6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 61830697e33c..3573872974e0 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -340,6 +340,18 @@ + <&a57_3>; + }; + ++ pmu_a53 { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&a53_0>, ++ <&a53_1>, ++ <&a53_2>, ++ <&a53_3>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 +-- +2.13.3 + diff --git a/patches.renesas/0022-arm64-dts-r8a7795-Upgrade-to-PSCI-v1.0-to-support-Su.patch b/patches.renesas/0022-arm64-dts-r8a7795-Upgrade-to-PSCI-v1.0-to-support-Su.patch new file mode 100644 index 00000000000000..57df4949e2e16b --- /dev/null +++ b/patches.renesas/0022-arm64-dts-r8a7795-Upgrade-to-PSCI-v1.0-to-support-Su.patch @@ -0,0 +1,45 @@ +From 173289a216e48c22bfb23a2000c8ce65155c555e Mon Sep 17 00:00:00 2001 +From: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Date: Fri, 24 Feb 2017 14:49:13 +0100 +Subject: [PATCH 022/286] arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support + Suspend-to-RAM + +>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI +function call. Hence, upgrade PSCI version for R-Car H3 to support +Suspend-to-RAM. + +The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support +since necessary callback functions will be registered after a query +to ARM Trusted Firmware about SYSTEM_SUSPEND support. + +Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and +CPUIdle should be able to work normally with this change. + +Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +[geert: Keep "arm,psci-0.2"] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 71585040b77e7b388708dc35bdc49f106fa55a4a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 3573872974e0..c1e00a3e7c45 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -29,7 +29,7 @@ + }; + + psci { +- compatible = "arm,psci-0.2"; ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + +-- +2.13.3 + diff --git a/patches.renesas/0023-arm64-dts-r8a7796-Upgrade-to-PSCI-v1.0-to-support-Su.patch b/patches.renesas/0023-arm64-dts-r8a7796-Upgrade-to-PSCI-v1.0-to-support-Su.patch new file mode 100644 index 00000000000000..d391a066842569 --- /dev/null +++ b/patches.renesas/0023-arm64-dts-r8a7796-Upgrade-to-PSCI-v1.0-to-support-Su.patch @@ -0,0 +1,45 @@ +From 9bd3cc397e75ded3a22999037c0ab1f052383b6b Mon Sep 17 00:00:00 2001 +From: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Date: Fri, 24 Feb 2017 14:49:14 +0100 +Subject: [PATCH 023/286] arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support + Suspend-to-RAM + +>From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI +function call. Hence, upgrade PSCI version for R-Car M3-W to support +Suspend-to-RAM. + +The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support +since necessary callback functions will be registered after a query +to ARM Trusted Firmware about SYSTEM_SUSPEND support. + +Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and +CPUIdle should be able to work normally with this change. + +Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +[geert: Keep "arm,psci-0.2"] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit b3f26910c0daafded536cf5edceab2ab469252cb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index aa404ed9142e..dbf82bc6ba64 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -29,7 +29,7 @@ + }; + + psci { +- compatible = "arm,psci-0.2"; ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + +-- +2.13.3 + diff --git a/patches.renesas/0024-arm64-dts-r8a7795-Remove-unit-addresses-and-regs-fro.patch b/patches.renesas/0024-arm64-dts-r8a7795-Remove-unit-addresses-and-regs-fro.patch new file mode 100644 index 00000000000000..675724020971a4 --- /dev/null +++ b/patches.renesas/0024-arm64-dts-r8a7795-Remove-unit-addresses-and-regs-fro.patch @@ -0,0 +1,46 @@ +From 7e479fdcf0534f34e6035d8aa1ea67b08e41b734 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 3 Mar 2017 14:18:16 +0100 +Subject: [PATCH 024/286] arm64: dts: r8a7795: Remove unit-addresses and regs + from integrated caches + +The Cortex-A57/A53 cache controllers are integrated controllers, and +thus the device nodes representing them should not have unit-addresses +or reg properties. + +Fixes: 6f7bf82cc912441f ("arm64: dts: r8a7795: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d165856de103a6d317a9c9a5782eacd5dc90a9dc) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index c1e00a3e7c45..14772bc02125 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -109,17 +109,15 @@ + enable-method = "psci"; + }; + +- L2_CA57: cache-controller@0 { ++ L2_CA57: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + +- L2_CA53: cache-controller@100 { ++ L2_CA53: cache-controller-1 { + compatible = "cache"; +- reg = <0x100>; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0025-arm64-dts-r8a7796-Remove-unit-address-and-reg-from-i.patch b/patches.renesas/0025-arm64-dts-r8a7796-Remove-unit-address-and-reg-from-i.patch new file mode 100644 index 00000000000000..5822acf42e1859 --- /dev/null +++ b/patches.renesas/0025-arm64-dts-r8a7796-Remove-unit-address-and-reg-from-i.patch @@ -0,0 +1,37 @@ +From f187d3ef9f6d25d6afac8d6c401f567f4be85d48 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 3 Mar 2017 14:18:17 +0100 +Subject: [PATCH 025/286] arm64: dts: r8a7796: Remove unit-address and reg from + integrated cache + +The Cortex-A57 cache controller is an integrated controller, and thus +the device node representing it should not have a unit-addresses or reg +property. + +Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 57a4fd420c6e8a04b6a87ff24d34250cd7c48f15) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index dbf82bc6ba64..27f7dd9bd988 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -47,9 +47,8 @@ + enable-method = "psci"; + }; + +- L2_CA57: cache-controller@0 { ++ L2_CA57: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0026-arm64-dts-r8a7795-salvator-x-Set-drive-strength-for-.patch b/patches.renesas/0026-arm64-dts-r8a7795-salvator-x-Set-drive-strength-for-.patch new file mode 100644 index 00000000000000..7e70ff79f81101 --- /dev/null +++ b/patches.renesas/0026-arm64-dts-r8a7795-salvator-x-Set-drive-strength-for-.patch @@ -0,0 +1,56 @@ +From 3944e77e8a83676fa61dd8531a7a96dbf83911d2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Mon, 5 Dec 2016 18:43:10 +0100 +Subject: [PATCH 026/286] arm64: dts: r8a7795: salvator-x: Set drive-strength + for ravb pins +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The EthernetAVB should not depend on the bootloader to setup correct +drive-strength values. Values for drive-strength where found by +examining the registers after the bootloader has configured the +registers and successfully used the EthernetAVB. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7d73a4da2681dc5d04e8ed9f4aa96c1deed2dbc5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index 5158ba3f9ce3..277ab8484e0c 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -247,8 +247,22 @@ + }; + + avb_pins: avb { +- groups = "avb_mdc"; +- function = "avb"; ++ mux { ++ groups = "avb_link", "avb_phy_int", "avb_mdc", ++ "avb_mii"; ++ function = "avb"; ++ }; ++ ++ pins_mdc { ++ groups = "avb_mdc"; ++ drive-strength = <24>; ++ }; ++ ++ pins_mii_tx { ++ pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", ++ "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; ++ drive-strength = <12>; ++ }; + }; + + du_pins: du { +-- +2.13.3 + diff --git a/patches.renesas/0027-arm64-dts-r8a7795-Tidyup-Audio-DMAC-channel-for-DVC.patch b/patches.renesas/0027-arm64-dts-r8a7795-Tidyup-Audio-DMAC-channel-for-DVC.patch new file mode 100644 index 00000000000000..e5b05f6d069a05 --- /dev/null +++ b/patches.renesas/0027-arm64-dts-r8a7795-Tidyup-Audio-DMAC-channel-for-DVC.patch @@ -0,0 +1,60 @@ +From fdc8214f2dc4348061dca59676daac2aacd67f91 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 7 Mar 2017 05:30:06 +0000 +Subject: [PATCH 027/286] arm64: dts: r8a7795: Tidyup Audio-DMAC channel for + DVC + +Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. +Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. + +Because of this, current platform board (using SRC/DVC/SSI) +Playback/Capture both will use same Audio-DMAC0 +(but it depends on audio data path). + +First note is that this "rx" and "tx" are from each IP point, +it doesn't mean Playback/Capture. +Second note is that Audio DMAC assigned on DT is only for +Audio-DMAC, Audio-DMAC-peri-peri has no entry. + +=> Audio-DMAC +-> Audio-DMAC-peri-peri +-- HW connection + +Playback case + + [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] + rx ~~~~~~~~~~~~ +Capture + + [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] + tx ~~~~~~~~~~~~ + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b5a8ffad0eb0c1e5e601253edac163b2da9e855d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 14772bc02125..55c09f1b89c9 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1075,11 +1075,11 @@ + + rcar_sound,dvc { + dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; ++ dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; ++ dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; +-- +2.13.3 + diff --git a/patches.renesas/0028-arm64-defconfig-enable-MVNETA.patch b/patches.renesas/0028-arm64-defconfig-enable-MVNETA.patch new file mode 100644 index 00000000000000..b74e5915b1923c --- /dev/null +++ b/patches.renesas/0028-arm64-defconfig-enable-MVNETA.patch @@ -0,0 +1,30 @@ +From 503707f43c86a3186e4a62229c6e208f8ade7b5c Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT <gregory.clement@free-electrons.com> +Date: Mon, 20 Feb 2017 18:27:17 +0100 +Subject: [PATCH 028/286] arm64: defconfig: enable MVNETA + +Now that the Armada 37xx SoCs support the mvneta driver, enable it by +default. It is especially useful when booting on an NFS root. + +Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +(cherry picked from commit d7ec74f412f5e5c6b964a4b635b1e3f1d72a7b34) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index c11c1473dad0..8394c2871d8e 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -177,6 +177,7 @@ CONFIG_HNS_ENET=y + CONFIG_E1000E=y + CONFIG_IGB=y + CONFIG_IGBVF=y ++CONFIG_MVNETA=y + CONFIG_SKY2=y + CONFIG_RAVB=y + CONFIG_SMC91X=y +-- +2.13.3 + diff --git a/patches.renesas/0029-arm64-defconfig-enable-I2C_PXA.patch b/patches.renesas/0029-arm64-defconfig-enable-I2C_PXA.patch new file mode 100644 index 00000000000000..0cd3950439adc9 --- /dev/null +++ b/patches.renesas/0029-arm64-defconfig-enable-I2C_PXA.patch @@ -0,0 +1,30 @@ +From 08cd9ace8bf7bb977f4987efc622cf0e5271662a Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT <gregory.clement@free-electrons.com> +Date: Wed, 22 Feb 2017 18:31:46 +0100 +Subject: [PATCH 029/286] arm64: defconfig: enable I2C_PXA + +Now that the Armada 37xx SoCs support the i2c pxa driver, enable it by +default. + +Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +(cherry picked from commit efbd24646abc044f70afc53bd331c7b520f499fd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 8394c2871d8e..4c3b6235bf3d 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -234,6 +234,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y + CONFIG_I2C_IMX=y + CONFIG_I2C_MESON=y + CONFIG_I2C_MV64XXX=y ++CONFIG_I2C_PXA=y + CONFIG_I2C_QUP=y + CONFIG_I2C_SH_MOBILE=y + CONFIG_I2C_TEGRA=y +-- +2.13.3 + diff --git a/patches.renesas/0030-arm64-dts-r8a7796-Add-Cortex-A57-CPU-cores.patch b/patches.renesas/0030-arm64-dts-r8a7796-Add-Cortex-A57-CPU-cores.patch new file mode 100644 index 00000000000000..2c0ae54b385b93 --- /dev/null +++ b/patches.renesas/0030-arm64-dts-r8a7796-Add-Cortex-A57-CPU-cores.patch @@ -0,0 +1,77 @@ +From 9470e627eeb80471401e1bc308f48b63e2a28346 Mon Sep 17 00:00:00 2001 +From: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Date: Tue, 7 Mar 2017 19:03:22 +0100 +Subject: [PATCH 030/286] arm64: dts: r8a7796: Add Cortex-A57 CPU cores + +This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of +2 x Cortex-A57. + +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +[geert: Rebased] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +(cherry picked from commit 7328be4a03b10c19e49a564f4c2e3a9ebcf34ca7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 20 ++++++++++++++------ + 1 file changed, 14 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 27f7dd9bd988..d2a2110fc7fc 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -37,7 +37,6 @@ + #address-cells = <1>; + #size-cells = <0>; + +- /* 1 core only at this point */ + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; +@@ -47,6 +46,15 @@ + enable-method = "psci"; + }; + ++ a57_1: cpu@1 { ++ compatible = "arm,cortex-a57","arm,armv8"; ++ reg = <0x1>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7796_PD_CA57_CPU1>; ++ next-level-cache = <&L2_CA57>; ++ enable-method = "psci"; ++ }; ++ + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; +@@ -100,7 +108,7 @@ + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 +- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; ++ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +@@ -109,13 +117,13 @@ + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 +- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 +- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 +- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 +- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; ++ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + wdt0: watchdog@e6020000 { +-- +2.13.3 + diff --git a/patches.renesas/0031-arm64-dts-r8a7796-Add-Cortex-A57-PMU-node.patch b/patches.renesas/0031-arm64-dts-r8a7796-Add-Cortex-A57-PMU-node.patch new file mode 100644 index 00000000000000..46a7dedb301797 --- /dev/null +++ b/patches.renesas/0031-arm64-dts-r8a7796-Add-Cortex-A57-PMU-node.patch @@ -0,0 +1,39 @@ +From c311a85c223388fe5023c62e5af0de510f634a35 Mon Sep 17 00:00:00 2001 +From: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Date: Tue, 7 Mar 2017 19:03:23 +0100 +Subject: [PATCH 031/286] arm64: dts: r8a7796: Add Cortex-A57 PMU node + +Enable the performance monitor unit for the Cortex-A57 cores on the +R8A7796 SoC. + +Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9fccf4d6103eeb5db88c1ae026d61b87f722414a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index d2a2110fc7fc..454e1292f910 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -252,6 +252,14 @@ + reg = <0 0xe6060000 0 0x50c>; + }; + ++ pmu_a57 { ++ compatible = "arm,cortex-a57-pmu"; ++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&a57_0>, ++ <&a57_1>; ++ }; ++ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; +-- +2.13.3 + diff --git a/patches.renesas/0032-arm64-dts-r8a7796-Add-CA53-L2-cache-controller-node.patch b/patches.renesas/0032-arm64-dts-r8a7796-Add-CA53-L2-cache-controller-node.patch new file mode 100644 index 00000000000000..2b2d2c2daaf590 --- /dev/null +++ b/patches.renesas/0032-arm64-dts-r8a7796-Add-CA53-L2-cache-controller-node.patch @@ -0,0 +1,42 @@ +From de17eb0a86edbf87cb7619eebf00f3130b521e9e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 7 Mar 2017 19:03:24 +0100 +Subject: [PATCH 032/286] arm64: dts: r8a7796: Add CA53 L2 cache-controller + node + +Add a device node for the Cortex-A53 L2 cache-controller. + +The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as +32 KiB x 16 ways). + +Extracted from a patch by Takeshi Kihara in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a681e6d63285b879bb9bab0bd79e2021e6dcbda1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index 454e1292f910..b951f5ffe9e0 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -61,6 +61,13 @@ + cache-unified; + cache-level = <2>; + }; ++ ++ L2_CA53: cache-controller-1 { ++ compatible = "cache"; ++ power-domains = <&sysc R8A7796_PD_CA53_SCU>; ++ cache-unified; ++ cache-level = <2>; ++ }; + }; + + extal_clk: extal { +-- +2.13.3 + diff --git a/patches.renesas/0033-arm64-dts-r8a7796-Add-Cortex-A53-CPU-cores.patch b/patches.renesas/0033-arm64-dts-r8a7796-Add-Cortex-A53-CPU-cores.patch new file mode 100644 index 00000000000000..4a60596dd3a7e6 --- /dev/null +++ b/patches.renesas/0033-arm64-dts-r8a7796-Add-Cortex-A53-CPU-cores.patch @@ -0,0 +1,95 @@ +From 0bc9baf9b589e7ae43480e343841510965b3b831 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 7 Mar 2017 19:03:25 +0100 +Subject: [PATCH 033/286] arm64: dts: r8a7796: Add Cortex-A53 CPU cores + +This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of +6 cores (2 x Cortex-A57 + 4 x Cortex-A53). + +Based on a patch by Takeshi Kihara in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b4dc3b4b1a65fec829ee8704c7647c06a8038108) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 ++++++++++++++++++++++++++++---- + 1 file changed, 41 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index b951f5ffe9e0..b32a180009dd 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -55,6 +55,42 @@ + enable-method = "psci"; + }; + ++ a53_0: cpu@100 { ++ compatible = "arm,cortex-a53", "arm,armv8"; ++ reg = <0x100>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7796_PD_CA53_CPU0>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_1: cpu@101 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x101>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7796_PD_CA53_CPU1>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_2: cpu@102 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x102>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7796_PD_CA53_CPU2>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ ++ a53_3: cpu@103 { ++ compatible = "arm,cortex-a53","arm,armv8"; ++ reg = <0x103>; ++ device_type = "cpu"; ++ power-domains = <&sysc R8A7796_PD_CA53_CPU3>; ++ next-level-cache = <&L2_CA53>; ++ enable-method = "psci"; ++ }; ++ + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; +@@ -115,7 +151,7 @@ + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 +- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; ++ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; +@@ -124,13 +160,13 @@ + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 +- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 +- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 +- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ++ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 +- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; ++ (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + + wdt0: watchdog@e6020000 { +-- +2.13.3 + diff --git a/patches.renesas/0034-arm64-dts-r8a7796-Add-Cortex-A53-PMU-node.patch b/patches.renesas/0034-arm64-dts-r8a7796-Add-Cortex-A53-PMU-node.patch new file mode 100644 index 00000000000000..15647f86af1663 --- /dev/null +++ b/patches.renesas/0034-arm64-dts-r8a7796-Add-Cortex-A53-PMU-node.patch @@ -0,0 +1,44 @@ +From 66f6a0203fa7058cc5173f7537c480faad3b4f47 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 7 Mar 2017 19:03:26 +0100 +Subject: [PATCH 034/286] arm64: dts: r8a7796: Add Cortex-A53 PMU node + +Enable the performance monitor unit for the Cortex-A53 cores on the +R8A7796 SoC. + +Extracted from a patch by Takeshi Kihara in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ccc499330dbcaa8f6065bd1b10a64ca09fa96c3e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index b32a180009dd..a90abf14dc4e 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -303,6 +303,18 @@ + <&a57_1>; + }; + ++ pmu_a53 { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-affinity = <&a53_0>, ++ <&a53_1>, ++ <&a53_2>, ++ <&a53_3>; ++ }; ++ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; +-- +2.13.3 + diff --git a/patches.renesas/0035-arm64-dts-h3ulcb-Drop-superfluous-status-update-for-.patch b/patches.renesas/0035-arm64-dts-h3ulcb-Drop-superfluous-status-update-for-.patch new file mode 100644 index 00000000000000..ce6a1864013aa4 --- /dev/null +++ b/patches.renesas/0035-arm64-dts-h3ulcb-Drop-superfluous-status-update-for-.patch @@ -0,0 +1,32 @@ +From de1fdd8c3e0dbc54b50145d304c0e6dd10d7f89a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:13 +0100 +Subject: [PATCH 035/286] arm64: dts: h3ulcb: Drop superfluous status update + for frequency override + +The scif_clk device node is already enabled in r8a7795.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c9060f50d82fc9b548571a9adea9ebff22b3347b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +index 69c623faf80c..ab352159de65 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +@@ -228,7 +228,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &i2c2 { +-- +2.13.3 + diff --git a/patches.renesas/0036-arm64-dts-r8a7795-salvator-x-Drop-superfluous-status.patch b/patches.renesas/0036-arm64-dts-r8a7795-salvator-x-Drop-superfluous-status.patch new file mode 100644 index 00000000000000..4a26fa348ab5fc --- /dev/null +++ b/patches.renesas/0036-arm64-dts-r8a7795-salvator-x-Drop-superfluous-status.patch @@ -0,0 +1,40 @@ +From 0a4d9cec23920958c68ea4fc0ae8bf4ad9afeabc Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:14 +0100 +Subject: [PATCH 036/286] arm64: dts: r8a7795: salvator-x: Drop superfluous + status updates for frequency overrides + +The scif_clk and pcie_bus_clk device nodes are already enabled in +r8a7795.dtsi, so there is no need to update their statuses again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 971939d1da07c7b55d35aca31288cce297731c71) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index 277ab8484e0c..f25241921067 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -362,7 +362,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &i2c2 { +@@ -574,7 +573,6 @@ + + &pcie_bus_clk { + clock-frequency = <100000000>; +- status = "okay"; + }; + + &pciec0 { +-- +2.13.3 + diff --git a/patches.renesas/0037-arm64-dts-m3ulcb-Drop-superfluous-status-update-for-.patch b/patches.renesas/0037-arm64-dts-m3ulcb-Drop-superfluous-status-update-for-.patch new file mode 100644 index 00000000000000..d0646921d6e3b3 --- /dev/null +++ b/patches.renesas/0037-arm64-dts-m3ulcb-Drop-superfluous-status-update-for-.patch @@ -0,0 +1,32 @@ +From e4c771ac474bb616e317cca2b98e26dee8a462cb Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:15 +0100 +Subject: [PATCH 037/286] arm64: dts: m3ulcb: Drop superfluous status update + for frequency override + +The scif_clk device node is already enabled in r8a7796.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cb4de4ece41a55ba125e6e8d1fa727457132dc41) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +index c3f064ac2cb4..372b2a944716 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +@@ -180,7 +180,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &wdt0 { +-- +2.13.3 + diff --git a/patches.renesas/0038-arm64-dts-r8a7796-salvator-x-Drop-superfluous-status.patch b/patches.renesas/0038-arm64-dts-r8a7796-salvator-x-Drop-superfluous-status.patch new file mode 100644 index 00000000000000..7ada2da1b30bf4 --- /dev/null +++ b/patches.renesas/0038-arm64-dts-r8a7796-salvator-x-Drop-superfluous-status.patch @@ -0,0 +1,32 @@ +From a09d775200ea3331a17bb0d38ea1a233a45659b4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:16 +0100 +Subject: [PATCH 038/286] arm64: dts: r8a7796: salvator-x: Drop superfluous + status update for frequency override + +The scif_clk device node is already enabled in r8a7796.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3cbe33367d4fd480a92fbc131a96fa925be9e95d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +index 74b8c653c9fe..c9f59b6ce33f 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +@@ -250,7 +250,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &i2c2 { +-- +2.13.3 + diff --git a/patches.renesas/0039-arm64-set-CONFIG_MMC_BCM2835-y-in-defconfig.patch b/patches.renesas/0039-arm64-set-CONFIG_MMC_BCM2835-y-in-defconfig.patch new file mode 100644 index 00000000000000..f1ed15a5708de7 --- /dev/null +++ b/patches.renesas/0039-arm64-set-CONFIG_MMC_BCM2835-y-in-defconfig.patch @@ -0,0 +1,37 @@ +From 61bab7f0b6352029b38afa972a373b85529d99f4 Mon Sep 17 00:00:00 2001 +From: Gerd Hoffmann <kraxel@redhat.com> +Date: Wed, 8 Mar 2017 10:19:09 +0100 +Subject: [PATCH 039/286] arm64: set CONFIG_MMC_BCM2835=y in defconfig + +We need to enable this controller so that we can switch the SD card's +pinmux over to it by default, which will improve storage performance. + +Read access (dd with 64k blocks on rpi2): + CONFIG_MMC_SDHCI_IPROC: 11-12 MB/s + CONFIG_MMC_BCM2835: 19-20 MB/s + +Differences on write access are pretty much in the noise. + +Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> +Reviewed-by: Eric Anholt <eric@anholt.net> +(cherry picked from commit 3c9d36192802d60fca73c85c7096221371c36be7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 4c3b6235bf3d..a174a015b96e 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -369,6 +369,7 @@ CONFIG_MMC_DW=y + CONFIG_MMC_DW_EXYNOS=y + CONFIG_MMC_DW_K3=y + CONFIG_MMC_SUNXI=y ++CONFIG_MMC_BCM2835=y + CONFIG_NEW_LEDS=y + CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y +-- +2.13.3 + diff --git a/patches.renesas/0040-arm64-dts-r8a7795-Correct-SATA-device-size-to-2MiB.patch b/patches.renesas/0040-arm64-dts-r8a7795-Correct-SATA-device-size-to-2MiB.patch new file mode 100644 index 00000000000000..1834c0c802fb59 --- /dev/null +++ b/patches.renesas/0040-arm64-dts-r8a7795-Correct-SATA-device-size-to-2MiB.patch @@ -0,0 +1,33 @@ +From 2bc9aa15be1f4adc2a49295f3e2d0e86304afd63 Mon Sep 17 00:00:00 2001 +From: Magnus Damm <damm+renesas@opensource.se> +Date: Mon, 20 Mar 2017 17:49:21 +0900 +Subject: [PATCH 040/286] arm64: dts: r8a7795: Correct SATA device size to 2MiB + +Update the r8a7795 SATA device node to use a 2MiB I/O space as specified +in the "72. Serial-ATA" section of R-Car-Gen3-rev0.52E.pdf + +Signed-off-by: Magnus Damm <damm+renesas@opensource.se> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e9f0089b2d8a3d450b8ec02eccfb92b950110fbe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index 55c09f1b89c9..e58175084b57 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -1209,7 +1209,7 @@ + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795"; +- reg = <0 0xee300000 0 0x1fff>; ++ reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; +-- +2.13.3 + diff --git a/patches.renesas/0041-arm64-dts-r8a7795-Add-reset-control-properties.patch b/patches.renesas/0041-arm64-dts-r8a7795-Add-reset-control-properties.patch new file mode 100644 index 00000000000000..6c4445b3d3435f --- /dev/null +++ b/patches.renesas/0041-arm64-dts-r8a7795-Add-reset-control-properties.patch @@ -0,0 +1,772 @@ +From c9397ebb604769c17e00ab489a2f63be027f5546 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 16 Mar 2017 15:07:23 +0100 +Subject: [PATCH 041/286] arm64: dts: r8a7795: Add reset control properties + +Add properties to describe the reset topology for on-SoC devices: + - Add the "#reset-cells" property to the CPG/MSSR device node, + - Add resets and reset-names properties to the various device nodes. + +This allows to reset SoC devices using the Reset Controller API. + +Note that all resets added match the corresponding module clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit dcccc13210eff0e5be2b36548198952c5683f3db) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795.dtsi | 93 ++++++++++++++++++++++++++++++++ + 1 file changed, 93 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +index e58175084b57..e99d6443b3e4 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi +@@ -204,6 +204,7 @@ + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 408>; + }; + + wdt0: watchdog@e6020000 { +@@ -211,6 +212,7 @@ + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 402>; + status = "disabled"; + }; + +@@ -226,6 +228,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { +@@ -240,6 +243,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { +@@ -254,6 +258,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { +@@ -268,6 +273,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { +@@ -282,6 +288,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { +@@ -296,6 +303,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { +@@ -310,6 +318,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { +@@ -324,6 +333,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 905>; + }; + + pmu_a57 { +@@ -369,6 +379,7 @@ + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; ++ #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { +@@ -405,6 +416,7 @@ + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 407>; + }; + + dmac0: dma-controller@e6700000 { +@@ -436,6 +448,7 @@ + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -469,6 +482,7 @@ + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -502,6 +516,7 @@ + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -535,6 +550,7 @@ + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -568,6 +584,7 @@ + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -610,6 +627,7 @@ + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; +@@ -628,6 +646,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 916>; + status = "disabled"; + }; + +@@ -643,6 +662,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 915>; + status = "disabled"; + }; + +@@ -659,6 +679,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 914>; + status = "disabled"; + + channel0 { +@@ -683,6 +704,7 @@ + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 520>; + status = "disabled"; + }; + +@@ -699,6 +721,7 @@ + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 519>; + status = "disabled"; + }; + +@@ -715,6 +738,7 @@ + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 518>; + status = "disabled"; + }; + +@@ -731,6 +755,7 @@ + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 517>; + status = "disabled"; + }; + +@@ -747,6 +772,7 @@ + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 516>; + status = "disabled"; + }; + +@@ -762,6 +788,7 @@ + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 207>; + status = "disabled"; + }; + +@@ -777,6 +804,7 @@ + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 206>; + status = "disabled"; + }; + +@@ -792,6 +820,7 @@ + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 310>; + status = "disabled"; + }; + +@@ -807,6 +836,7 @@ + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 204>; + status = "disabled"; + }; + +@@ -822,6 +852,7 @@ + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 203>; + status = "disabled"; + }; + +@@ -837,6 +868,7 @@ + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 202>; + status = "disabled"; + }; + +@@ -850,6 +882,7 @@ + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 926>; + status = "disabled"; + }; + +@@ -862,6 +895,7 @@ + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -877,6 +911,7 @@ + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; +@@ -892,6 +927,7 @@ + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; +@@ -907,6 +943,7 @@ + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -922,6 +959,7 @@ + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -937,6 +975,7 @@ + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -952,6 +991,7 @@ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; +@@ -963,6 +1003,7 @@ + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -972,6 +1013,7 @@ + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -981,6 +1023,7 @@ + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -990,6 +1033,7 @@ + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -999,6 +1043,7 @@ + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -1008,6 +1053,7 @@ + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -1017,6 +1063,7 @@ + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; +@@ -1213,6 +1260,7 @@ + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 815>; + status = "disabled"; + }; + +@@ -1222,6 +1270,7 @@ + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 328>; + status = "disabled"; + }; + +@@ -1231,6 +1280,7 @@ + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 327>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 327>; + status = "disabled"; + }; + +@@ -1243,6 +1293,7 @@ + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -1256,6 +1307,7 @@ + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; +@@ -1267,6 +1319,7 @@ + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 314>; + status = "disabled"; + }; + +@@ -1277,6 +1330,7 @@ + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 313>; + status = "disabled"; + }; + +@@ -1287,6 +1341,7 @@ + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 312>; + status = "disabled"; + }; + +@@ -1297,6 +1352,7 @@ + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 311>; + status = "disabled"; + }; + +@@ -1307,6 +1363,7 @@ + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; +@@ -1317,6 +1374,7 @@ + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; +@@ -1327,6 +1385,7 @@ + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 701>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 701>; + #phy-cells = <0>; + status = "disabled"; + }; +@@ -1339,6 +1398,7 @@ + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; + status = "disabled"; + }; + +@@ -1350,6 +1410,7 @@ + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; + status = "disabled"; + }; + +@@ -1361,6 +1422,7 @@ + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 701>; + status = "disabled"; + }; + +@@ -1372,6 +1434,7 @@ + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 703>; + status = "disabled"; + }; + +@@ -1383,6 +1446,7 @@ + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 702>; + status = "disabled"; + }; + +@@ -1394,6 +1458,7 @@ + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 701>; + status = "disabled"; + }; + +@@ -1410,6 +1475,7 @@ + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 704>; + status = "disabled"; + }; + +@@ -1436,6 +1502,7 @@ + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 319>; + status = "disabled"; + }; + +@@ -1462,6 +1529,7 @@ + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 318>; + status = "disabled"; + }; + +@@ -1471,6 +1539,7 @@ + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; +@@ -1480,6 +1549,7 @@ + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 606>; + }; + + fcpf0: fcp@fe950000 { +@@ -1487,6 +1557,7 @@ + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { +@@ -1494,6 +1565,7 @@ + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 614>; + }; + + fcpf2: fcp@fe952000 { +@@ -1501,6 +1573,7 @@ + reg = <0 0xfe952000 0 0x200>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 613>; + }; + + vspbd: vsp@fe960000 { +@@ -1509,6 +1582,7 @@ + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; +@@ -1518,6 +1592,7 @@ + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 607>; + }; + + vspi0: vsp@fe9a0000 { +@@ -1526,6 +1601,7 @@ + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; +@@ -1535,6 +1611,7 @@ + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 611>; + }; + + vspi1: vsp@fe9b0000 { +@@ -1543,6 +1620,7 @@ + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; +@@ -1552,6 +1630,7 @@ + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 610>; + }; + + vspi2: vsp@fe9c0000 { +@@ -1560,6 +1639,7 @@ + interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 629>; + + renesas,fcp = <&fcpvi2>; + }; +@@ -1569,6 +1649,7 @@ + reg = <0 0xfe9cf000 0 0x200>; + clocks = <&cpg CPG_MOD 609>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 609>; + }; + + vspd0: vsp@fea20000 { +@@ -1577,6 +1658,7 @@ + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; +@@ -1586,6 +1668,7 @@ + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 603>; + }; + + vspd1: vsp@fea28000 { +@@ -1594,6 +1677,7 @@ + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; +@@ -1603,6 +1687,7 @@ + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 602>; + }; + + vspd2: vsp@fea30000 { +@@ -1611,6 +1696,7 @@ + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; +@@ -1620,6 +1706,7 @@ + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 601>; + }; + + vspd3: vsp@fea38000 { +@@ -1628,6 +1715,7 @@ + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 620>; + + renesas,fcp = <&fcpvd3>; + }; +@@ -1637,6 +1725,7 @@ + reg = <0 0xfea3f000 0 0x200>; + clocks = <&cpg CPG_MOD 600>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 600>; + }; + + fdp1@fe940000 { +@@ -1645,6 +1734,7 @@ + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + +@@ -1654,6 +1744,7 @@ + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + +@@ -1663,6 +1754,7 @@ + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7795_PD_A3VP>; ++ resets = <&cpg 117>; + renesas,fcp = <&fcpf2>; + }; + +@@ -1722,6 +1814,7 @@ + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0042-arm64-dts-r8a7796-Add-reset-control-properties.patch b/patches.renesas/0042-arm64-dts-r8a7796-Add-reset-control-properties.patch new file mode 100644 index 00000000000000..8a964e56f2f456 --- /dev/null +++ b/patches.renesas/0042-arm64-dts-r8a7796-Add-reset-control-properties.patch @@ -0,0 +1,396 @@ +From ab3df83b62b93ac01be4cc9eabbda4ed5a4f02d4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 16 Mar 2017 15:07:24 +0100 +Subject: [PATCH 042/286] arm64: dts: r8a7796: Add reset control properties + +Add properties to describe the reset topology for on-SoC devices: + - Add the "#reset-cells" property to the CPG/MSSR device node, + - Add resets and reset-names properties to the various device nodes. + +This allows to reset SoC devices using the Reset Controller API. + +Note that all resets added match the corresponding module clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit bec0948e810fffce38b9b886b0283a44eb025043) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 ++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +index a90abf14dc4e..2ec1ed5f4991 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi ++++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi +@@ -155,6 +155,7 @@ + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 408>; + }; + + timer { +@@ -175,6 +176,7 @@ + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 402>; + status = "disabled"; + }; + +@@ -190,6 +192,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { +@@ -204,6 +207,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { +@@ -218,6 +222,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { +@@ -232,6 +237,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { +@@ -246,6 +252,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { +@@ -260,6 +267,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { +@@ -274,6 +282,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { +@@ -288,6 +297,7 @@ + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { +@@ -322,6 +332,7 @@ + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; ++ #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { +@@ -350,6 +361,7 @@ + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 926>; + status = "disabled"; + }; + +@@ -362,6 +374,7 @@ + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; +@@ -378,6 +391,7 @@ + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; +@@ -394,6 +408,7 @@ + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; +@@ -410,6 +425,7 @@ + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -425,6 +441,7 @@ + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -440,6 +457,7 @@ + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; +@@ -455,6 +473,7 @@ + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; +@@ -473,6 +492,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 916>; + status = "disabled"; + }; + +@@ -488,6 +508,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 915>; + status = "disabled"; + }; + +@@ -504,6 +525,7 @@ + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 914>; + status = "disabled"; + + channel0 { +@@ -553,6 +575,7 @@ + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; +@@ -573,6 +596,7 @@ + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 520>; + status = "disabled"; + }; + +@@ -590,6 +614,7 @@ + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 519>; + status = "disabled"; + }; + +@@ -607,6 +632,7 @@ + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 518>; + status = "disabled"; + }; + +@@ -623,6 +649,7 @@ + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 517>; + status = "disabled"; + }; + +@@ -639,6 +666,7 @@ + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 516>; + status = "disabled"; + }; + +@@ -655,6 +683,7 @@ + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 207>; + status = "disabled"; + }; + +@@ -671,6 +700,7 @@ + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 206>; + status = "disabled"; + }; + +@@ -684,6 +714,7 @@ + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 310>; + status = "disabled"; + }; + +@@ -699,6 +730,7 @@ + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 204>; + status = "disabled"; + }; + +@@ -714,6 +746,7 @@ + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 203>; + status = "disabled"; + }; + +@@ -730,6 +763,7 @@ + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 202>; + status = "disabled"; + }; + +@@ -743,6 +777,7 @@ + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -758,6 +793,7 @@ + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -772,6 +808,7 @@ + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -786,6 +823,7 @@ + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -820,6 +858,7 @@ + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -853,6 +892,7 @@ + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -886,6 +926,7 @@ + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; +@@ -897,6 +938,7 @@ + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 314>; + status = "disabled"; + }; + +@@ -907,6 +949,7 @@ + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 313>; + status = "disabled"; + }; + +@@ -917,6 +960,7 @@ + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 312>; + status = "disabled"; + }; + +@@ -927,6 +971,7 @@ + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 311>; + status = "disabled"; + }; + +@@ -940,6 +985,7 @@ + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; ++ resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0043-arm64-defconfig-Enable-video-DRM-and-LPASS-drivers-f.patch b/patches.renesas/0043-arm64-defconfig-Enable-video-DRM-and-LPASS-drivers-f.patch new file mode 100644 index 00000000000000..436d2b7338bf34 --- /dev/null +++ b/patches.renesas/0043-arm64-defconfig-Enable-video-DRM-and-LPASS-drivers-f.patch @@ -0,0 +1,56 @@ +From c9cd2211b24a94d89ca0a44ecd9bf8b1660e67f9 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Tue, 14 Mar 2017 19:10:26 +0200 +Subject: [PATCH 043/286] arm64: defconfig: Enable video, DRM and LPASS drivers + for Exynos5433 and Exynos7 + +Enable drivers specific to Exynos5433 and Exynos7: +1. MFD Low Power Audio SubSystem (LPASS), +2. DRM drivers (DECON display, outputs), +3. Drivers for video-related sub-blocks (JPEG, Multi Format Codec, + GScaler). + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> +(cherry picked from commit 0edf17984f251e633465e028a0115d57b1b7eb88) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index a174a015b96e..55af8c6f3404 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -279,6 +279,7 @@ CONFIG_RENESAS_WDT=y + CONFIG_S3C2410_WATCHDOG=y + CONFIG_MESON_GXBB_WATCHDOG=m + CONFIG_MESON_WATCHDOG=m ++CONFIG_MFD_EXYNOS_LPASS=m + CONFIG_MFD_MAX77620=y + CONFIG_MFD_SPMI_PMIC=y + CONFIG_MFD_SEC_CORE=y +@@ -302,10 +303,20 @@ CONFIG_MEDIA_CONTROLLER=y + CONFIG_VIDEO_V4L2_SUBDEV_API=y + # CONFIG_DVB_NET is not set + CONFIG_V4L_MEM2MEM_DRIVERS=y ++CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m ++CONFIG_VIDEO_SAMSUNG_S5P_MFC=m ++CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m + CONFIG_VIDEO_RENESAS_FCP=m + CONFIG_VIDEO_RENESAS_VSP1=m + CONFIG_DRM=m + CONFIG_DRM_NOUVEAU=m ++CONFIG_DRM_EXYNOS=m ++CONFIG_DRM_EXYNOS5433_DECON=y ++CONFIG_DRM_EXYNOS7_DECON=y ++CONFIG_DRM_EXYNOS_DSI=y ++# CONFIG_DRM_EXYNOS_DP is not set ++CONFIG_DRM_EXYNOS_HDMI=y ++CONFIG_DRM_EXYNOS_MIC=y + CONFIG_DRM_RCAR_DU=m + CONFIG_DRM_RCAR_HDMI=y + CONFIG_DRM_RCAR_LVDS=y +-- +2.13.3 + diff --git a/patches.renesas/0044-arm64-defconfig-enable-MVPP2.patch b/patches.renesas/0044-arm64-defconfig-enable-MVPP2.patch new file mode 100644 index 00000000000000..2d7dcb60d0fe83 --- /dev/null +++ b/patches.renesas/0044-arm64-defconfig-enable-MVPP2.patch @@ -0,0 +1,31 @@ +From e2210b65a559c0f434e6ca57092be519d00d9703 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +Date: Thu, 16 Mar 2017 16:16:28 +0100 +Subject: [PATCH 044/286] arm64: defconfig: enable MVPP2 + +The MVPP2 network driver is used for the ARM64 Marvell Armada 7K and 8K +platforms, so enable it in the arm64 defconfig. + +Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> +Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +(cherry picked from commit 66e56302842e9971426bd7e504c4db4f88cbb037) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 55af8c6f3404..8b5d5f3131d3 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -177,6 +177,7 @@ CONFIG_HNS_ENET=y + CONFIG_E1000E=y + CONFIG_IGB=y + CONFIG_IGBVF=y ++CONFIG_MVPP2=y + CONFIG_MVNETA=y + CONFIG_SKY2=y + CONFIG_RAVB=y +-- +2.13.3 + diff --git a/patches.renesas/0045-clk-renesas-Add-r8a7795-ES2.0-CPG-Core-Clock-Definit.patch b/patches.renesas/0045-clk-renesas-Add-r8a7795-ES2.0-CPG-Core-Clock-Definit.patch new file mode 100644 index 00000000000000..c106d29d72acc8 --- /dev/null +++ b/patches.renesas/0045-clk-renesas-Add-r8a7795-ES2.0-CPG-Core-Clock-Definit.patch @@ -0,0 +1,36 @@ +From 469531bf6d590e2ca38bd51e8547a4017da1bb3a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 29 Sep 2016 13:06:15 +0200 +Subject: [PATCH 045/286] clk: renesas: Add r8a7795 ES2.0 CPG Core Clock + Definitions + +Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as +listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3 +Hardware User's Manual rev. 0.53E. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 89f1b1c614253d7ea57543f769d93fced99d4d05) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/dt-bindings/clock/r8a7795-cpg-mssr.h | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h +index e864aae0a256..f047eaf261f3 100644 +--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h ++++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h +@@ -60,4 +60,11 @@ + #define R8A7795_CLK_R 45 + #define R8A7795_CLK_OSC 46 + ++/* r8a7795 ES2.0 CPG Core Clocks */ ++#define R8A7795_CLK_S0D2 47 ++#define R8A7795_CLK_S0D3 48 ++#define R8A7795_CLK_S0D6 49 ++#define R8A7795_CLK_S0D8 50 ++#define R8A7795_CLK_S0D12 51 ++ + #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0046-arm64-kdump-enable-kdump-in-defconfig.patch b/patches.renesas/0046-arm64-kdump-enable-kdump-in-defconfig.patch new file mode 100644 index 00000000000000..003d29bc529152 --- /dev/null +++ b/patches.renesas/0046-arm64-kdump-enable-kdump-in-defconfig.patch @@ -0,0 +1,31 @@ +From f711c67ec90d14dbfa71c3e68c99667ae386f729 Mon Sep 17 00:00:00 2001 +From: AKASHI Takahiro <takahiro.akashi@linaro.org> +Date: Mon, 3 Apr 2017 11:24:39 +0900 +Subject: [PATCH 046/286] arm64: kdump: enable kdump in defconfig + +Kdump is enabled by default as kexec is. + +Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> +Acked-by: Catalin Marinas <catalin.marinas@arm.com> +Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> +(cherry picked from commit 3f5c1e1e761981b41d0be22f9aadfc7458fcc786) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 8b5d5f3131d3..92041816d78f 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -78,6 +78,7 @@ CONFIG_CMA=y + CONFIG_SECCOMP=y + CONFIG_XEN=y + CONFIG_KEXEC=y ++CONFIG_CRASH_DUMP=y + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set + CONFIG_COMPAT=y + CONFIG_CPU_IDLE=y +-- +2.13.3 + diff --git a/patches.renesas/0047-arm64-dts-r8a7795-salvator-x-Drop-_clk-suffix-from-X.patch b/patches.renesas/0047-arm64-dts-r8a7795-salvator-x-Drop-_clk-suffix-from-X.patch new file mode 100644 index 00000000000000..873b839ea59fe7 --- /dev/null +++ b/patches.renesas/0047-arm64-dts-r8a7795-salvator-x-Drop-_clk-suffix-from-X.patch @@ -0,0 +1,34 @@ +From 10645d56f8dba2de706585840c59c0856aa92efa Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 12:08:09 +0200 +Subject: [PATCH 047/286] arm64: dts: r8a7795: salvator-x: Drop _clk suffix + from X12 clock node name + +The current practice is to not add _clk suffixes to clock node names in +DT, as these names are used as the actual clock names. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 6922bd71adab0a7fe8ffbdc3e72a46431fa29656) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +index f25241921067..639aa085d996 100644 +--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts ++++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +@@ -56,7 +56,7 @@ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + +- x12_clk: x12_clk { ++ x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; +-- +2.13.3 + diff --git a/patches.renesas/0048-arm64-defconfig-enable-the-Safexcel-crypto-engine-as.patch b/patches.renesas/0048-arm64-defconfig-enable-the-Safexcel-crypto-engine-as.patch new file mode 100644 index 00000000000000..09cbbf88771337 --- /dev/null +++ b/patches.renesas/0048-arm64-defconfig-enable-the-Safexcel-crypto-engine-as.patch @@ -0,0 +1,33 @@ +From 243e7b35a571726190f7237e7f45f39443ccb70d Mon Sep 17 00:00:00 2001 +From: Antoine Tenart <antoine.tenart@free-electrons.com> +Date: Wed, 29 Mar 2017 14:44:32 +0200 +Subject: [PATCH 048/286] arm64: defconfig: enable the Safexcel crypto engine + as a module + +The Safexcel EIP197 cryptographic engine is used on some Marvell SoCs, +such as Armada 7040 and Armada 8040. Enable this driver as a module in +the ARM64 defconfig. + +Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> +Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +(cherry picked from commit 10ebb57ffcbf062ff224585fefa274e703fc363d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 92041816d78f..8fe9569d8145 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -487,6 +487,7 @@ CONFIG_MEMTEST=y + CONFIG_SECURITY=y + CONFIG_CRYPTO_ECHAINIV=y + CONFIG_CRYPTO_ANSI_CPRNG=y ++CONFIG_CRYPTO_DEV_SAFEXCEL=m + CONFIG_ARM64_CRYPTO=y + CONFIG_CRYPTO_SHA1_ARM64_CE=y + CONFIG_CRYPTO_SHA2_ARM64_CE=y +-- +2.13.3 + diff --git a/patches.renesas/0049-i2c-rcar-fix-resume-by-always-initializing-registers.patch b/patches.renesas/0049-i2c-rcar-fix-resume-by-always-initializing-registers.patch new file mode 100644 index 00000000000000..a03d63f47b3568 --- /dev/null +++ b/patches.renesas/0049-i2c-rcar-fix-resume-by-always-initializing-registers.patch @@ -0,0 +1,45 @@ +From 78ded0f782b36fc9716b27771bd543fb7cd74575 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 18 Apr 2017 20:38:35 +0200 +Subject: [PATCH 049/286] i2c: rcar: fix resume by always initializing + registers before transfer + +Resume failed because of uninitialized registers. Instead of adding a +resume callback, we simply initialize registers before every transfer. +This lightweight change is more robust and will keep us safe if we ever +need support for power domains or dynamic frequency changes. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit ae481cc139658e89eb3ea671dd00b67bd87f01a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-rcar.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 26f2ff22e97e..66b84bf51bbf 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -700,6 +700,8 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap, + + pm_runtime_get_sync(dev); + ++ rcar_i2c_init(priv); ++ + ret = rcar_i2c_bus_barrier(priv); + if (ret < 0) + goto out; +@@ -860,8 +862,6 @@ static int rcar_i2c_probe(struct platform_device *pdev) + if (ret < 0) + goto out_pm_put; + +- rcar_i2c_init(priv); +- + /* Don't suspend when multi-master to keep arbitration working */ + if (of_property_read_bool(dev->of_node, "multi-master")) + priv->flags |= ID_P_PM_BLOCKED; +-- +2.13.3 + diff --git a/patches.renesas/0050-i2c-rcar-clarify-PM-handling-with-more-comments.patch b/patches.renesas/0050-i2c-rcar-clarify-PM-handling-with-more-comments.patch new file mode 100644 index 00000000000000..cc309d8c884856 --- /dev/null +++ b/patches.renesas/0050-i2c-rcar-clarify-PM-handling-with-more-comments.patch @@ -0,0 +1,48 @@ +From ad3794d1f29c79c25e51a986d6e66d9179a0495f Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Thu, 20 Apr 2017 12:04:33 +0200 +Subject: [PATCH 050/286] i2c: rcar: clarify PM handling with more comments + +PM handling is correct but might be a bit subtle. Add some comments for +clarification. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit 63a761eef55759c0bc725739fe575193c09fa4ef) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-rcar.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 66b84bf51bbf..214bf2835d1f 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -753,6 +753,7 @@ static int rcar_reg_slave(struct i2c_client *slave) + if (slave->flags & I2C_CLIENT_TEN) + return -EAFNOSUPPORT; + ++ /* Keep device active for slave address detection logic */ + pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv)); + + priv->slave = slave; +@@ -856,13 +857,14 @@ static int rcar_i2c_probe(struct platform_device *pdev) + priv->dma_direction = DMA_NONE; + priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER); + ++ /* Activate device for clock calculation */ + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + ret = rcar_i2c_clock_calculate(priv, &i2c_t); + if (ret < 0) + goto out_pm_put; + +- /* Don't suspend when multi-master to keep arbitration working */ ++ /* Stay always active when multi-master to keep arbitration working */ + if (of_property_read_bool(dev->of_node, "multi-master")) + priv->flags |= ID_P_PM_BLOCKED; + else +-- +2.13.3 + diff --git a/patches.renesas/0051-i2c-rcar-use-correct-length-when-unmapping-DMA.patch b/patches.renesas/0051-i2c-rcar-use-correct-length-when-unmapping-DMA.patch new file mode 100644 index 00000000000000..0071740352ef57 --- /dev/null +++ b/patches.renesas/0051-i2c-rcar-use-correct-length-when-unmapping-DMA.patch @@ -0,0 +1,39 @@ +From 2f3c42c442e2fceae677090e021d175f4ce12f44 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Sun, 28 May 2017 09:52:17 +0200 +Subject: [PATCH 051/286] i2c: rcar: use correct length when unmapping DMA +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Because we need to transfer some bytes with PIO, the msg length is not +the length of the DMA buffer. Use the correct value which we used when +doing the mapping. + +Fixes: 73e8b0528346e8 ("i2c: rcar: add DMA support") +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +(cherry picked from commit 916335036d4fe33f9806240cb0d1900f4975b959) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/i2c/busses/i2c-rcar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 214bf2835d1f..8be3e6cb8fe6 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -319,7 +319,7 @@ static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv) + rcar_i2c_write(priv, ICFBSCR, TCYC06); + + dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg), +- priv->msg->len, priv->dma_direction); ++ sg_dma_len(&priv->sg), priv->dma_direction); + + priv->dma_direction = DMA_NONE; + } +-- +2.13.3 + diff --git a/patches.renesas/0052-ARM-dts-r7s72100-update-sdhi-clock-bindings.patch b/patches.renesas/0052-ARM-dts-r7s72100-update-sdhi-clock-bindings.patch new file mode 100644 index 00000000000000..f9b262c0e2a68e --- /dev/null +++ b/patches.renesas/0052-ARM-dts-r7s72100-update-sdhi-clock-bindings.patch @@ -0,0 +1,82 @@ +From d22659eda4cf22d9e56db64f81402491c12cf39b Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 25 Jan 2017 15:28:10 -0500 +Subject: [PATCH 052/286] ARM: dts: r7s72100: update sdhi clock bindings + +The SDHI controller in the RZ/A1 has 2 clock sources per channel and both +need to be enabled/disabled for proper operation. This fixes the fact that +the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and +that all 4 clock sources need to be defined an used. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3d2abda02ad2d06d5f22de7f6b0f39126670bc48) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 17 ++++++++++++----- + include/dt-bindings/clock/r7s72100-clock.h | 6 ++++-- + 2 files changed, 16 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index b8aa256bd515..614ba79a9774 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -162,9 +162,12 @@ + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0444 4>; +- clocks = <&p1_clk>, <&p1_clk>; +- clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; +- clock-output-names = "sdhi1", "sdhi0"; ++ clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; ++ clock-indices = < ++ R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 ++ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 ++ >; ++ clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; + }; + }; + +@@ -488,7 +491,9 @@ + GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + +- clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; ++ clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, ++ <&mstp12_clks R7S72100_CLK_SDHI01>; ++ clock-names = "core", "cd"; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; +@@ -501,7 +506,9 @@ + GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; + +- clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; ++ clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, ++ <&mstp12_clks R7S72100_CLK_SDHI11>; ++ clock-names = "core", "cd"; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; +diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h +index ce09915c298f..cd2ed5194255 100644 +--- a/include/dt-bindings/clock/r7s72100-clock.h ++++ b/include/dt-bindings/clock/r7s72100-clock.h +@@ -49,7 +49,9 @@ + #define R7S72100_CLK_SPI4 3 + + /* MSTP12 */ +-#define R7S72100_CLK_SDHI0 3 +-#define R7S72100_CLK_SDHI1 2 ++#define R7S72100_CLK_SDHI00 3 ++#define R7S72100_CLK_SDHI01 2 ++#define R7S72100_CLK_SDHI10 1 ++#define R7S72100_CLK_SDHI11 0 + + #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0053-ARM-dts-r8a7743-Fix-SCIFB0-dmas-indentation.patch b/patches.renesas/0053-ARM-dts-r8a7743-Fix-SCIFB0-dmas-indentation.patch new file mode 100644 index 00000000000000..561208533d7a07 --- /dev/null +++ b/patches.renesas/0053-ARM-dts-r8a7743-Fix-SCIFB0-dmas-indentation.patch @@ -0,0 +1,30 @@ +From ce05cb88124a19fdbfaa79d87389c729dba5f519 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 8 Feb 2017 19:00:43 +0100 +Subject: [PATCH 053/286] ARM: dts: r8a7743: Fix SCIFB0 dmas indentation + +Fixes: 809c013426914694 ("ARM: dts: r8a7743: add [H]SCIF{A|B} support") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c8290f9f2e1d119512e1821fc13d1d145aa23f77) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi +index d8393b97768b..c166be2f18e0 100644 +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -277,7 +277,7 @@ + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; ++ <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + status = "disabled"; +-- +2.13.3 + diff --git a/patches.renesas/0054-ARM-dts-r8a7745-Fix-SCIFB0-dmas-indentation.patch b/patches.renesas/0054-ARM-dts-r8a7745-Fix-SCIFB0-dmas-indentation.patch new file mode 100644 index 00000000000000..071d768cf12924 --- /dev/null +++ b/patches.renesas/0054-ARM-dts-r8a7745-Fix-SCIFB0-dmas-indentation.patch @@ -0,0 +1,30 @@ +From 7de4d32d20e9acb249c9f4b8005595840920bbf6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Wed, 8 Feb 2017 19:00:44 +0100 +Subject: [PATCH 054/286] ARM: dts: r8a7745: Fix SCIFB0 dmas indentation + +Fixes: e0d2da54c4d01ba2 ("ARM: dts: r8a7745: add [H]SCIF{|A|B} support") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ad20bb6868f1d29f9c911f14087be4f93c098604) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi +index 1f65ff68a469..25175a74b6b7 100644 +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -277,7 +277,7 @@ + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, +- <&dmac1 0x3d>, <&dmac1 0x3e>; ++ <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + status = "disabled"; +-- +2.13.3 + diff --git a/patches.renesas/0055-ARM-dts-r8a73a4-Remove-unit-addresses-and-regs-from-.patch b/patches.renesas/0055-ARM-dts-r8a73a4-Remove-unit-addresses-and-regs-from-.patch new file mode 100644 index 00000000000000..9ce7fbce6a8b97 --- /dev/null +++ b/patches.renesas/0055-ARM-dts-r8a73a4-Remove-unit-addresses-and-regs-from-.patch @@ -0,0 +1,47 @@ +From 990ac1488361850941a593db7667c76e3a88797c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:36 +0100 +Subject: [PATCH 055/286] ARM: dts: r8a73a4: Remove unit-addresses and regs + from integrated caches + +The Cortex-A15/A7 cache controllers are integrated controllers, and thus +the device nodes representing them should not have unit-addresses or reg +properties. + +Fixes: b0da45c60d2f7b08 ("ARM: dts: r8a73a4: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cdaf6417b723e380501f46e555abf0c1c3090124) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 00eb9a7114dc..6fb7eaba9126 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -32,18 +32,16 @@ + next-level-cache = <&L2_CA15>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + clocks = <&cpg_clocks R8A73A4_CLK_Z>; + power-domains = <&pd_a3sm>; + cache-unified; + cache-level = <2>; + }; + +- L2_CA7: cache-controller@100 { ++ L2_CA7: cache-controller-1 { + compatible = "cache"; +- reg = <0x100>; + clocks = <&cpg_clocks R8A73A4_CLK_Z2>; + power-domains = <&pd_a3km>; + cache-unified; +-- +2.13.3 + diff --git a/patches.renesas/0056-ARM-dts-r8a7743-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0056-ARM-dts-r8a7743-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..06e465165ac020 --- /dev/null +++ b/patches.renesas/0056-ARM-dts-r8a7743-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 6a9b216413c5b1c2f285637f971c45a04f281fcc Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:37 +0100 +Subject: [PATCH 056/286] ARM: dts: r8a7743: Remove unit-address and reg from + integrated cache + +The Cortex-A15 cache controller is an integrated controller, and thus +the device node representing it should not have a unit-addresses or reg +property. + +Fixes: 34e8d993a68ae459 ("ARM: dts: r8a7743: initial SoC device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 37f0c804e57ac93ca37a98aa5a210c6b73e6572a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi +index c166be2f18e0..cd908796fb3b 100644 +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -32,9 +32,8 @@ + next-level-cache = <&L2_CA15>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; +-- +2.13.3 + diff --git a/patches.renesas/0057-ARM-dts-r8a7745-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0057-ARM-dts-r8a7745-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..61b302b5097859 --- /dev/null +++ b/patches.renesas/0057-ARM-dts-r8a7745-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 42bf632b7d7b30934a952d11213b87d96bcc6023 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:38 +0100 +Subject: [PATCH 057/286] ARM: dts: r8a7745: Remove unit-address and reg from + integrated cache + +The Cortex-A7 cache controller is an integrated controller, and thus the +device node representing it should not have a unit-addresses or reg +property. + +Fixes: c95360247bdd67d3 ("ARM: dts: r8a7745: initial SoC device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 51c00a9f730dd27da23e9dec593c22c0f9f5a1b1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi +index 25175a74b6b7..bca88715fada 100644 +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -32,9 +32,8 @@ + next-level-cache = <&L2_CA7>; + }; + +- L2_CA7: cache-controller@0 { ++ L2_CA7: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7745_PD_CA7_SCU>; +-- +2.13.3 + diff --git a/patches.renesas/0058-ARM-dts-r8a7790-Remove-unit-addresses-and-regs-from-.patch b/patches.renesas/0058-ARM-dts-r8a7790-Remove-unit-addresses-and-regs-from-.patch new file mode 100644 index 00000000000000..8cf21aabcfdf6a --- /dev/null +++ b/patches.renesas/0058-ARM-dts-r8a7790-Remove-unit-addresses-and-regs-from-.patch @@ -0,0 +1,46 @@ +From 38d94a2c2d3dffb0c18d28baf668d89b9c334dea Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:39 +0100 +Subject: [PATCH 058/286] ARM: dts: r8a7790: Remove unit-addresses and regs + from integrated caches + +The Cortex-A15/A7 cache controllers are integrated controllers, and thus +the device nodes representing them should not have unit-addresses or reg +properties. + +Fixes: 2c3de36700d4f3a5 ("ARM: dts: r8a7790: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d492909c84b895564d7ac413546ae988945c68db) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 6d10450de6d7..20cf191e0852 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -129,17 +129,15 @@ + next-level-cache = <&L2_CA7>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7790_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + +- L2_CA7: cache-controller@100 { ++ L2_CA7: cache-controller-1 { + compatible = "cache"; +- reg = <0x100>; + power-domains = <&sysc R8A7790_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0059-ARM-dts-r8a7791-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0059-ARM-dts-r8a7791-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..92925a4ad3dd70 --- /dev/null +++ b/patches.renesas/0059-ARM-dts-r8a7791-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 00bcd74c3d7c10cf84a2b54391f03e8101ec94a4 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:40 +0100 +Subject: [PATCH 059/286] ARM: dts: r8a7791: Remove unit-address and reg from + integrated cache + +The Cortex-A15 cache controller is an integrated controller, and thus +the device node representing it should not have a unit-addresses or reg +property. + +Fixes: 6f9314ce258c8504 ("ARM: dts: r8a7791: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5d6a2165abd4635ecf5ece3d02fe8677f00d32c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 381b3c513b25..96f5539aede7 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -74,9 +74,8 @@ + next-level-cache = <&L2_CA15>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0060-ARM-dts-r8a7792-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0060-ARM-dts-r8a7792-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..7eafe8266599db --- /dev/null +++ b/patches.renesas/0060-ARM-dts-r8a7792-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 30918d73bb8dbf1074a380a9d2db2913238420e6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:41 +0100 +Subject: [PATCH 060/286] ARM: dts: r8a7792: Remove unit-address and reg from + integrated cache + +The Cortex-A15 cache controller is an integrated controller, and thus +the device node representing it should not have a unit-addresses or reg +property. + +Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit a0504f0880c11da301dc2b5a5135bd02376e367e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7792.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi +index 8ecfda7a004e..c762f44f7732 100644 +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -60,9 +60,8 @@ + next-level-cache = <&L2_CA15>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7792_PD_CA15_SCU>; +-- +2.13.3 + diff --git a/patches.renesas/0061-ARM-dts-r8a7793-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0061-ARM-dts-r8a7793-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..9c5a36184318b8 --- /dev/null +++ b/patches.renesas/0061-ARM-dts-r8a7793-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 30af71d9a050783fde91edae2ac024bc29846bdf Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:42 +0100 +Subject: [PATCH 061/286] ARM: dts: r8a7793: Remove unit-address and reg from + integrated cache + +The Cortex-A15 cache controller is an integrated controller, and thus +the device node representing it should not have a unit-addresses or reg +property. + +Fixes: ad53f5f00b095a0d ("ARM: dts: r8a7793: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit beffa8872a3680ef804eb0320ec77037170f4686) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 48ce21c5e8db..38506f563b2b 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -65,9 +65,8 @@ + power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + }; + +- L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7793_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0062-ARM-dts-r8a7794-Remove-unit-address-and-reg-from-int.patch b/patches.renesas/0062-ARM-dts-r8a7794-Remove-unit-address-and-reg-from-int.patch new file mode 100644 index 00000000000000..96fa88520de3e7 --- /dev/null +++ b/patches.renesas/0062-ARM-dts-r8a7794-Remove-unit-address-and-reg-from-int.patch @@ -0,0 +1,37 @@ +From 768259cf227690716d59217c9237b3b788212d86 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:40:43 +0100 +Subject: [PATCH 062/286] ARM: dts: r8a7794: Remove unit-address and reg from + integrated cache + +The Cortex-A7 cache controller is an integrated controller, and thus the +device node representing it should not have a unit-addresses or reg +property. + +Fixes: 34ea4b4a827b4ee7 ("ARM: dts: r8a7794: Fix W=1 dtc warnings") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 65d0b7ed40f8a3a41a0ac5ed5ca4d1874c6aaf2d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 319c1069b7ee..cb31cd2232f9 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -56,9 +56,8 @@ + next-level-cache = <&L2_CA7>; + }; + +- L2_CA7: cache-controller@0 { ++ L2_CA7: cache-controller-0 { + compatible = "cache"; +- reg = <0>; + power-domains = <&sysc R8A7794_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; +-- +2.13.3 + diff --git a/patches.renesas/0063-ARM-dts-r8a7790-Tidyup-Audio-DMAC-channel-for-DVC.patch b/patches.renesas/0063-ARM-dts-r8a7790-Tidyup-Audio-DMAC-channel-for-DVC.patch new file mode 100644 index 00000000000000..cd3945945e2047 --- /dev/null +++ b/patches.renesas/0063-ARM-dts-r8a7790-Tidyup-Audio-DMAC-channel-for-DVC.patch @@ -0,0 +1,59 @@ +From 859a317e88728520543a91bdacd519dd3638d566 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 7 Mar 2017 05:28:57 +0000 +Subject: [PATCH 063/286] ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC + +Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. +Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. + +Because of this, current platform board (using SRC/DVC/SSI) +Playback/Capture both will use same Audio-DMAC0 +(but it depends on data path). + +First note is that this "rx" and "tx" are from each IP point, +it doesn't mean Playback/Capture. +Second note is that Audio DMAC assigned on DT is only for +Audio-DMAC, Audio-DMAC-peri-peri has no entry. + +=> Audio-DMAC +-> Audio-DMAC-peri-peri +-- HW connection + +Playback case + + [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] + rx ~~~~~~~~~~~~ +Capture + + [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] + tx ~~~~~~~~~~~~ + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c4a59df9de199426b773a15e0c774ae25f628d5d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 20cf191e0852..495c583054a8 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1738,11 +1738,11 @@ + + rcar_sound,dvc { + dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; ++ dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; ++ dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; +-- +2.13.3 + diff --git a/patches.renesas/0064-ARM-dts-r7s72100-Add-watchdog-timer.patch b/patches.renesas/0064-ARM-dts-r7s72100-Add-watchdog-timer.patch new file mode 100644 index 00000000000000..c7d54d8ca83398 --- /dev/null +++ b/patches.renesas/0064-ARM-dts-r7s72100-Add-watchdog-timer.patch @@ -0,0 +1,40 @@ +From 0ae198db28be0e6256d2441209aa5f5aa3d04292 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Sat, 4 Mar 2017 17:37:37 -0500 +Subject: [PATCH 064/286] ARM: dts: r7s72100: Add watchdog timer + +Add watchdog timer support for RZ/A1. +For the RZ/A1, the only way to do a reset is to overflow the WDT, so this +is useful even if you don't need the watchdog functionality. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Guenter Roeck <linux@roeck-us.net> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 69ed50de582eff6307fd3fa050fdc505731f0a2d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 614ba79a9774..9b12d73e67dc 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -371,6 +371,13 @@ + <0xe8202000 0x1000>; + }; + ++ wdt: watchdog@fcfe0000 { ++ compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; ++ reg = <0xfcfe0000 0x6>; ++ interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>; ++ clocks = <&p0_clk>; ++ }; ++ + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0065-ARM-dts-r8a73a4-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0065-ARM-dts-r8a73a4-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..e526e23c4a4f44 --- /dev/null +++ b/patches.renesas/0065-ARM-dts-r8a73a4-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,72 @@ +From 8c1599019236b1f34a272635f4e58f3aa5452b25 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:06 +0100 +Subject: [PATCH 065/286] ARM: dts: r8a73a4: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock and the C4 power domain, +so it can be power managed using that clock in the future. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c11333cc2e7ebe41e2aa4fa353abafa1f21a0662) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a73a4.dtsi | 13 +++++++++---- + include/dt-bindings/clock/r8a73a4-clock.h | 1 + + 2 files changed, 10 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi +index 6fb7eaba9126..1f5c9f6dddba 100644 +--- a/arch/arm/boot/dts/r8a73a4.dtsi ++++ b/arch/arm/boot/dts/r8a73a4.dtsi +@@ -467,6 +467,9 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&pd_c4>; + }; + + bsc: bus@fec10000 { +@@ -725,16 +728,18 @@ + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&main_div2_clk>, <&main_div2_clk>, ++ clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, ++ <&main_div2_clk>, + <&cpg_clocks R8A73A4_CLK_HP>, + <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < +- R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 +- R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 ++ R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS ++ R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 ++ R8A73A4_CLK_IIC3 + >; + clock-output-names = +- "irqc", "iic5", "iic4", "iic3"; ++ "irqc", "intc-sys", "iic5", "iic4", "iic3"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h +index dd11ecdf837e..4b3668157257 100644 +--- a/include/dt-bindings/clock/r8a73a4-clock.h ++++ b/include/dt-bindings/clock/r8a73a4-clock.h +@@ -54,6 +54,7 @@ + #define R8A73A4_CLK_IIC3 11 + #define R8A73A4_CLK_IIC4 10 + #define R8A73A4_CLK_IIC5 9 ++#define R8A73A4_CLK_INTC_SYS 8 + #define R8A73A4_CLK_IRQC 7 + + /* MSTP5 */ +-- +2.13.3 + diff --git a/patches.renesas/0066-ARM-dts-r8a7790-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0066-ARM-dts-r8a7790-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..19cbc197d8cd69 --- /dev/null +++ b/patches.renesas/0066-ARM-dts-r8a7790-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,63 @@ +From 497b0731f181a1996b7677209b85625aba672439 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:07 +0100 +Subject: [PATCH 066/286] ARM: dts: r8a7790: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock, and add it to the "always +on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 9e58523624fc063ce43ad3ef2bf6d603bda50a5e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 9 ++++++--- + include/dt-bindings/clock/r8a7790-clock.h | 1 + + 2 files changed, 7 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 495c583054a8..534525665bb3 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -185,6 +185,9 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + }; + + gpio0: gpio@e6050000 { +@@ -1364,10 +1367,10 @@ + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&cp_clk>; ++ clocks = <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; +- clock-indices = <R8A7790_CLK_IRQC>; +- clock-output-names = "irqc"; ++ clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>; ++ clock-output-names = "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h +index fa5e8da809f2..20641fa68e73 100644 +--- a/include/dt-bindings/clock/r8a7790-clock.h ++++ b/include/dt-bindings/clock/r8a7790-clock.h +@@ -82,6 +82,7 @@ + + /* MSTP4 */ + #define R8A7790_CLK_IRQC 7 ++#define R8A7790_CLK_INTC_SYS 8 + + /* MSTP5 */ + #define R8A7790_CLK_AUDIO_DMAC1 1 +-- +2.13.3 + diff --git a/patches.renesas/0067-ARM-dts-r8a7791-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0067-ARM-dts-r8a7791-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..e46b4073119f01 --- /dev/null +++ b/patches.renesas/0067-ARM-dts-r8a7791-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,63 @@ +From 7087c01544a08af46135c92268b946c393fbf277 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:08 +0100 +Subject: [PATCH 067/286] ARM: dts: r8a7791: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock, and add it to the "always +on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit c2f2e266acb39f86bda1461874568ced7eaa6752) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 9 ++++++--- + include/dt-bindings/clock/r8a7791-clock.h | 1 + + 2 files changed, 7 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 96f5539aede7..9e2bceb2f1d6 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -117,6 +117,9 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + }; + + gpio0: gpio@e6050000 { +@@ -1365,10 +1368,10 @@ + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&cp_clk>; ++ clocks = <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; +- clock-indices = <R8A7791_CLK_IRQC>; +- clock-output-names = "irqc"; ++ clock-indices = <R8A7791_CLK_IRQC R8A7791_CLK_INTC_SYS>; ++ clock-output-names = "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h +index ffa11379b3f0..adc50dc31ab3 100644 +--- a/include/dt-bindings/clock/r8a7791-clock.h ++++ b/include/dt-bindings/clock/r8a7791-clock.h +@@ -72,6 +72,7 @@ + + /* MSTP4 */ + #define R8A7791_CLK_IRQC 7 ++#define R8A7791_CLK_INTC_SYS 8 + + /* MSTP5 */ + #define R8A7791_CLK_AUDIO_DMAC1 1 +-- +2.13.3 + diff --git a/patches.renesas/0068-ARM-dts-r8a7792-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0068-ARM-dts-r8a7792-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..f0723093321f39 --- /dev/null +++ b/patches.renesas/0068-ARM-dts-r8a7792-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,65 @@ +From 6e262fda2cdc91076056ffbf813e0a735e6acd30 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:09 +0100 +Subject: [PATCH 068/286] ARM: dts: r8a7792: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock, and add it to the "always +on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 90dce5428ae5499f06d91297ef10b3b613044774) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7792.dtsi | 11 ++++++++--- + include/dt-bindings/clock/r8a7792-clock.h | 1 + + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi +index c762f44f7732..6c0797ebc08f 100644 +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -92,6 +92,9 @@ + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + irqc: interrupt-controller@e61c0000 { +@@ -895,10 +898,12 @@ + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&cp_clk>; ++ clocks = <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; +- clock-indices = <R8A7792_CLK_IRQC>; +- clock-output-names = "irqc"; ++ clock-indices = < ++ R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS ++ >; ++ clock-output-names = "irqc", "intc-sys"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7792-mstp-clocks", +diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h +index 9a8b392ceb00..94dd16a1e6e6 100644 +--- a/include/dt-bindings/clock/r8a7792-clock.h ++++ b/include/dt-bindings/clock/r8a7792-clock.h +@@ -45,6 +45,7 @@ + + /* MSTP4 */ + #define R8A7792_CLK_IRQC 7 ++#define R8A7792_CLK_INTC_SYS 8 + + /* MSTP5 */ + #define R8A7792_CLK_AUDIO_DMAC0 2 +-- +2.13.3 + diff --git a/patches.renesas/0069-ARM-dts-r8a7794-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0069-ARM-dts-r8a7794-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..01e3ba8f3ccdbd --- /dev/null +++ b/patches.renesas/0069-ARM-dts-r8a7794-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,63 @@ +From 8cf2f36fc62ea403b4bfb89664fef5af6e5b108c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:11 +0100 +Subject: [PATCH 069/286] ARM: dts: r8a7794: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock, and add it to the "always +on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 133a3f1a19c99218a39e9d3e91e9e5442fa0f191) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 9 ++++++--- + include/dt-bindings/clock/r8a7794-clock.h | 1 + + 2 files changed, 7 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index cb31cd2232f9..38bf9ed8e739 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -74,6 +74,9 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + }; + + gpio0: gpio@e6050000 { +@@ -1247,10 +1250,10 @@ + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&cp_clk>; ++ clocks = <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; +- clock-indices = <R8A7794_CLK_IRQC>; +- clock-output-names = "irqc"; ++ clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>; ++ clock-output-names = "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h +index 88e64846cf37..a26776f7dedd 100644 +--- a/include/dt-bindings/clock/r8a7794-clock.h ++++ b/include/dt-bindings/clock/r8a7794-clock.h +@@ -64,6 +64,7 @@ + + /* MSTP4 */ + #define R8A7794_CLK_IRQC 7 ++#define R8A7794_CLK_INTC_SYS 8 + + /* MSTP5 */ + #define R8A7794_CLK_AUDIO_DMAC0 2 +-- +2.13.3 + diff --git a/patches.renesas/0070-ARM-dts-r8a7791-Tidyup-Audio-DMAC-channel-for-DVC.patch b/patches.renesas/0070-ARM-dts-r8a7791-Tidyup-Audio-DMAC-channel-for-DVC.patch new file mode 100644 index 00000000000000..eca0c5608b6b49 --- /dev/null +++ b/patches.renesas/0070-ARM-dts-r8a7791-Tidyup-Audio-DMAC-channel-for-DVC.patch @@ -0,0 +1,59 @@ +From 69e42103203b9e866676919ad2f41b5693c19b87 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 7 Mar 2017 05:29:21 +0000 +Subject: [PATCH 070/286] ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC + +Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. +Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. + +Because of this, current platform board (using SRC/DVC/SSI) +Playback/Capture both will use same Audio-DMAC0 +(but it depends on audio data path). + +First note is that this "rx" and "tx" are from each IP point, +it doesn't mean Playback/Capture. +Second note is that Audio DMAC assigned on DT is only for +Audio-DMAC, Audio-DMAC-peri-peri has no entry. + +=> Audio-DMAC +-> Audio-DMAC-peri-peri +-- HW connection + +Playback case + + [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] + rx ~~~~~~~~~~~~ +Capture + + [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] + tx ~~~~~~~~~~~~ + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d49db72b567d6273f41f045b0c146837d3e50f8d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 9e2bceb2f1d6..4202d474992e 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1779,11 +1779,11 @@ + + rcar_sound,dvc { + dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; ++ dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; ++ dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; +-- +2.13.3 + diff --git a/patches.renesas/0071-ARM-dts-r8a7793-Tidyup-Audio-DMAC-channel-for-DVC.patch b/patches.renesas/0071-ARM-dts-r8a7793-Tidyup-Audio-DMAC-channel-for-DVC.patch new file mode 100644 index 00000000000000..ebdeee73f7a2e8 --- /dev/null +++ b/patches.renesas/0071-ARM-dts-r8a7793-Tidyup-Audio-DMAC-channel-for-DVC.patch @@ -0,0 +1,59 @@ +From 9bb373ce94adecc32a93c56280f8b694429ed707 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 7 Mar 2017 05:29:43 +0000 +Subject: [PATCH 071/286] ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC + +Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. +Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. + +Because of this, current platform board (using SRC/DVC/SSI) +Playback/Capture both will use same Audio-DMAC0 +(but it depends on audio data path). + +First note is that this "rx" and "tx" are from each IP point, +it doesn't mean Playback/Capture. +Second note is that Audio DMAC assigned on DT is only for +Audio-DMAC, Audio-DMAC-peri-peri has no entry. + +=> Audio-DMAC +-> Audio-DMAC-peri-peri +-- HW connection + +Playback case + + [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] + rx ~~~~~~~~~~~~ +Capture + + [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] + tx ~~~~~~~~~~~~ + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d2b10f99962aa5ec9865a77827931bf20211a39c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 38506f563b2b..53c89b47eaf0 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -1425,11 +1425,11 @@ + + rcar_sound,dvc { + dvc0: dvc-0 { +- dmas = <&audma0 0xbc>; ++ dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { +- dmas = <&audma0 0xbe>; ++ dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; +-- +2.13.3 + diff --git a/patches.renesas/0072-ARM-dts-r8a7793-Add-INTC-SYS-clock-to-device-tree.patch b/patches.renesas/0072-ARM-dts-r8a7793-Add-INTC-SYS-clock-to-device-tree.patch new file mode 100644 index 00000000000000..800904ef69b45b --- /dev/null +++ b/patches.renesas/0072-ARM-dts-r8a7793-Add-INTC-SYS-clock-to-device-tree.patch @@ -0,0 +1,71 @@ +From 1c384dcb3906189f27fd8b58ca6686f96569c110 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 6 Mar 2017 17:58:10 +0100 +Subject: [PATCH 072/286] ARM: dts: r8a7793: Add INTC-SYS clock to device tree + +Link the ARM GIC to the INTC-SYS module clock, and add it to the "always +on" PM Domain, so it can be power managed using that clock. + +Note that currently the GIC-400 driver doesn't support module clocks nor +Runtime PM, so this must be handled as a critical clock. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2f25c2d1cdf04ab0f247351e286d3fdefbdad09b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 11 ++++++++--- + include/dt-bindings/clock/r8a7793-clock.h | 5 +++-- + 2 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 53c89b47eaf0..9fcf3a9ca084 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -108,6 +108,9 @@ + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; ++ clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>; ++ clock-names = "clk"; ++ power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + }; + + gpio0: gpio@e6050000 { +@@ -1178,10 +1181,12 @@ + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; +- clocks = <&cp_clk>; ++ clocks = <&cp_clk>, <&zs_clk>; + #clock-cells = <1>; +- clock-indices = <R8A7793_CLK_IRQC>; +- clock-output-names = "irqc"; ++ clock-indices = < ++ R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS ++ >; ++ clock-output-names = "irqc", "intc-sys"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h +index efcbc594fe82..7318d45d4e7e 100644 +--- a/include/dt-bindings/clock/r8a7793-clock.h ++++ b/include/dt-bindings/clock/r8a7793-clock.h +@@ -77,10 +77,11 @@ + + /* MSTP4 */ + #define R8A7793_CLK_IRQC 7 ++#define R8A7793_CLK_INTC_SYS 8 + + /* MSTP5 */ +-#define R8A7793_CLK_AUDIO_DMAC1 1 +-#define R8A7793_CLK_AUDIO_DMAC0 2 ++#define R8A7793_CLK_AUDIO_DMAC1 1 ++#define R8A7793_CLK_AUDIO_DMAC0 2 + #define R8A7793_CLK_ADSP_MOD 6 + #define R8A7793_CLK_THERMAL 22 + #define R8A7793_CLK_PWM 23 +-- +2.13.3 + diff --git a/patches.renesas/0073-ARM-dts-porter-Always-use-status-okay-to-enable-devi.patch b/patches.renesas/0073-ARM-dts-porter-Always-use-status-okay-to-enable-devi.patch new file mode 100644 index 00000000000000..72afc9bec12287 --- /dev/null +++ b/patches.renesas/0073-ARM-dts-porter-Always-use-status-okay-to-enable-devi.patch @@ -0,0 +1,42 @@ +From 40afb305890a450e2671cd889a2abe154dbde7b6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:04 +0100 +Subject: [PATCH 073/286] ARM: dts: porter: Always use status "okay" to enable + devices + +While status "ok" does work, the canonical form is "okay", so update the +few places that used the former. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d8fc23051a9b6dd66ed0cc3c2a676991493b8112) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791-porter.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts +index 6761d11d3f9e..d9aa2cd6d625 100644 +--- a/arch/arm/boot/dts/r8a7791-porter.dts ++++ b/arch/arm/boot/dts/r8a7791-porter.dts +@@ -226,7 +226,7 @@ + + phy-handle = <&phy1>; + renesas,ether-link-active-low; +- status = "ok"; ++ status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; +@@ -359,7 +359,7 @@ + + /* composite video input */ + &vin0 { +- status = "ok"; ++ status = "okay"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + +-- +2.13.3 + diff --git a/patches.renesas/0074-ARM-dts-bockw-Drop-superfluous-status-update-for-fre.patch b/patches.renesas/0074-ARM-dts-bockw-Drop-superfluous-status-update-for-fre.patch new file mode 100644 index 00000000000000..2a3ef9ea038658 --- /dev/null +++ b/patches.renesas/0074-ARM-dts-bockw-Drop-superfluous-status-update-for-fre.patch @@ -0,0 +1,30 @@ +From 6323d104a6def0e2547ecc54f9122d9a424ed51c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:05 +0100 +Subject: [PATCH 074/286] ARM: dts: bockw: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7778.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ffbb98d4d1f194e455bae2bc2eab2995188c652e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7778-bockw.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts +index 211d239d9041..c79d55eb43c5 100644 +--- a/arch/arm/boot/dts/r8a7778-bockw.dts ++++ b/arch/arm/boot/dts/r8a7778-bockw.dts +@@ -229,5 +229,4 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0075-ARM-dts-marzen-Drop-superfluous-status-update-for-fr.patch b/patches.renesas/0075-ARM-dts-marzen-Drop-superfluous-status-update-for-fr.patch new file mode 100644 index 00000000000000..93112d6c526f99 --- /dev/null +++ b/patches.renesas/0075-ARM-dts-marzen-Drop-superfluous-status-update-for-fr.patch @@ -0,0 +1,32 @@ +From 981301245b0ce242cd402189ee5d7bb2137aa060 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:06 +0100 +Subject: [PATCH 075/286] ARM: dts: marzen: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7779.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2f69fd8cb2187631ad68531a07406ad6b179b122) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7779-marzen.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts +index 89c5b24a3d03..9412a86f9b30 100644 +--- a/arch/arm/boot/dts/r8a7779-marzen.dts ++++ b/arch/arm/boot/dts/r8a7779-marzen.dts +@@ -236,7 +236,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &sdhi0 { +-- +2.13.3 + diff --git a/patches.renesas/0076-ARM-dts-lager-Drop-superfluous-status-update-for-fre.patch b/patches.renesas/0076-ARM-dts-lager-Drop-superfluous-status-update-for-fre.patch new file mode 100644 index 00000000000000..afea0defc3cd8e --- /dev/null +++ b/patches.renesas/0076-ARM-dts-lager-Drop-superfluous-status-update-for-fre.patch @@ -0,0 +1,32 @@ +From 5ef4a097d908a4895092210588f09c194c85bd93 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:07 +0100 +Subject: [PATCH 076/286] ARM: dts: lager: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7790.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 2507e3d41a3f0f09e7d756b34e3bb953d6d3b76d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790-lager.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts +index bd512c86e852..ba100a6f67ca 100644 +--- a/arch/arm/boot/dts/r8a7790-lager.dts ++++ b/arch/arm/boot/dts/r8a7790-lager.dts +@@ -581,7 +581,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &msiof1 { +-- +2.13.3 + diff --git a/patches.renesas/0077-ARM-dts-koelsch-Drop-superfluous-status-updates-for-.patch b/patches.renesas/0077-ARM-dts-koelsch-Drop-superfluous-status-updates-for-.patch new file mode 100644 index 00000000000000..d7818856342d59 --- /dev/null +++ b/patches.renesas/0077-ARM-dts-koelsch-Drop-superfluous-status-updates-for-.patch @@ -0,0 +1,40 @@ +From 993ce94fb09b4165d1a6037320e537aa61bbee3c Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:08 +0100 +Subject: [PATCH 077/286] ARM: dts: koelsch: Drop superfluous status updates + for frequency overrides + +The scif_clk and pcie_bus_clk device nodes are already enabled in +r8a7791.dtsi, so there is no need to update their statuses again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b20b1de4b542749a500c426796bb7fa400b03e58) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791-koelsch.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts +index 5405d337d744..59beb8402a36 100644 +--- a/arch/arm/boot/dts/r8a7791-koelsch.dts ++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts +@@ -516,7 +516,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &sdhi0 { +@@ -767,7 +766,6 @@ + + &pcie_bus_clk { + clock-frequency = <100000000>; +- status = "okay"; + }; + + &pciec { +-- +2.13.3 + diff --git a/patches.renesas/0078-ARM-dts-porter-Drop-superfluous-status-update-for-fr.patch b/patches.renesas/0078-ARM-dts-porter-Drop-superfluous-status-update-for-fr.patch new file mode 100644 index 00000000000000..27078ea436f162 --- /dev/null +++ b/patches.renesas/0078-ARM-dts-porter-Drop-superfluous-status-update-for-fr.patch @@ -0,0 +1,32 @@ +From 62e32bac42b235f2b1f7139e19f0d414a3956e04 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:09 +0100 +Subject: [PATCH 078/286] ARM: dts: porter: Drop superfluous status update for + frequency override + +The pcie_bus_clk device node is already enabled in r8a7791.dtsi, so +there is no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b546d090c8ecca05c83e71d931f6d9ad72a8d730) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791-porter.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts +index d9aa2cd6d625..95da5cb9d37a 100644 +--- a/arch/arm/boot/dts/r8a7791-porter.dts ++++ b/arch/arm/boot/dts/r8a7791-porter.dts +@@ -401,7 +401,6 @@ + + &pcie_bus_clk { + clock-frequency = <100000000>; +- status = "okay"; + }; + + &pciec { +-- +2.13.3 + diff --git a/patches.renesas/0079-ARM-dts-gose-Drop-superfluous-status-update-for-freq.patch b/patches.renesas/0079-ARM-dts-gose-Drop-superfluous-status-update-for-freq.patch new file mode 100644 index 00000000000000..47d59e9f9d961a --- /dev/null +++ b/patches.renesas/0079-ARM-dts-gose-Drop-superfluous-status-update-for-freq.patch @@ -0,0 +1,32 @@ +From ab460d3eda1bedd36298055ad30c17ba19afbd02 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:10 +0100 +Subject: [PATCH 079/286] ARM: dts: gose: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7793.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e68f8b428d84c304ca534505eafa98cb02a5bae0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793-gose.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts +index 92fff07c5e2b..806c93f6ae8b 100644 +--- a/arch/arm/boot/dts/r8a7793-gose.dts ++++ b/arch/arm/boot/dts/r8a7793-gose.dts +@@ -412,7 +412,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &sdhi0 { +-- +2.13.3 + diff --git a/patches.renesas/0080-ARM-dts-alt-Drop-superfluous-status-update-for-frequ.patch b/patches.renesas/0080-ARM-dts-alt-Drop-superfluous-status-update-for-frequ.patch new file mode 100644 index 00000000000000..d9816ea5a65822 --- /dev/null +++ b/patches.renesas/0080-ARM-dts-alt-Drop-superfluous-status-update-for-frequ.patch @@ -0,0 +1,32 @@ +From ee2e5d232d77c705101316163b801b8fdd013289 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:11 +0100 +Subject: [PATCH 080/286] ARM: dts: alt: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7794.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e5fada0cf2131b901e411bb65c22ddc98b6dcf98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794-alt.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts +index 569e3f0e97a5..3fcf76b8e923 100644 +--- a/arch/arm/boot/dts/r8a7794-alt.dts ++++ b/arch/arm/boot/dts/r8a7794-alt.dts +@@ -375,7 +375,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + &qspi { +-- +2.13.3 + diff --git a/patches.renesas/0081-ARM-dts-silk-Drop-superfluous-status-update-for-freq.patch b/patches.renesas/0081-ARM-dts-silk-Drop-superfluous-status-update-for-freq.patch new file mode 100644 index 00000000000000..778bb30bbc5c4a --- /dev/null +++ b/patches.renesas/0081-ARM-dts-silk-Drop-superfluous-status-update-for-freq.patch @@ -0,0 +1,32 @@ +From 67256c05d4c35bf5f112d07dbf3b44785cfb7565 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:19:12 +0100 +Subject: [PATCH 081/286] ARM: dts: silk: Drop superfluous status update for + frequency override + +The scif_clk device node is already enabled in r8a7794.dtsi, so there is +no need to update its status again. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d01ff18992218f3a13f45f45a886b3bf8f250f14) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794-silk.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts +index cf880ac06f4b..c742d80d6dca 100644 +--- a/arch/arm/boot/dts/r8a7794-silk.dts ++++ b/arch/arm/boot/dts/r8a7794-silk.dts +@@ -248,7 +248,6 @@ + + &scif_clk { + clock-frequency = <14745600>; +- status = "okay"; + }; + + ðer { +-- +2.13.3 + diff --git a/patches.renesas/0082-ARM-shmobile-Document-RZ-G1H-SoC-DT-binding.patch b/patches.renesas/0082-ARM-shmobile-Document-RZ-G1H-SoC-DT-binding.patch new file mode 100644 index 00000000000000..7331ca2e8a44c6 --- /dev/null +++ b/patches.renesas/0082-ARM-shmobile-Document-RZ-G1H-SoC-DT-binding.patch @@ -0,0 +1,31 @@ +From c87818d71cc24ce1d07c0db397ae4f6d718995b9 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:48:27 +0100 +Subject: [PATCH 082/286] ARM: shmobile: Document RZ/G1H SoC DT binding + +Document the RZ/G1H (r8a7742) SoC. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 368d03531f39ffaa793a98b9a17c79d660b1cd1a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt +index c9502634316d..b8155a209c58 100644 +--- a/Documentation/devicetree/bindings/arm/shmobile.txt ++++ b/Documentation/devicetree/bindings/arm/shmobile.txt +@@ -13,6 +13,8 @@ SoCs: + compatible = "renesas,r8a73a4" + - R-Mobile A1 (R8A77400) + compatible = "renesas,r8a7740" ++ - RZ/G1H (R8A77420) ++ compatible = "renesas,r8a7742" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" + - RZ/G1E (R8A77450) +-- +2.13.3 + diff --git a/patches.renesas/0083-ARM-shmobile-Document-RZ-G1N-SoC-DT-binding.patch b/patches.renesas/0083-ARM-shmobile-Document-RZ-G1N-SoC-DT-binding.patch new file mode 100644 index 00000000000000..8b48c8d32f3541 --- /dev/null +++ b/patches.renesas/0083-ARM-shmobile-Document-RZ-G1N-SoC-DT-binding.patch @@ -0,0 +1,31 @@ +From efcb2dcbf18f63019eb8312f05d954237568db23 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:48:28 +0100 +Subject: [PATCH 083/286] ARM: shmobile: Document RZ/G1N SoC DT binding + +Document the RZ/G1N (r8a7744) SoC. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cfb9f93437eb6663ca99e85c47bb3656ccfe59c5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt +index b8155a209c58..170fe0562c63 100644 +--- a/Documentation/devicetree/bindings/arm/shmobile.txt ++++ b/Documentation/devicetree/bindings/arm/shmobile.txt +@@ -17,6 +17,8 @@ SoCs: + compatible = "renesas,r8a7742" + - RZ/G1M (R8A77430) + compatible = "renesas,r8a7743" ++ - RZ/G1N (R8A77440) ++ compatible = "renesas,r8a7744" + - RZ/G1E (R8A77450) + compatible = "renesas,r8a7745" + - R-Car M1A (R8A77781) +-- +2.13.3 + diff --git a/patches.renesas/0084-ARM-8660-1-shmobile-r7s72100-Enable-L2-cache.patch b/patches.renesas/0084-ARM-8660-1-shmobile-r7s72100-Enable-L2-cache.patch new file mode 100644 index 00000000000000..d8fa1955b5c2fc --- /dev/null +++ b/patches.renesas/0084-ARM-8660-1-shmobile-r7s72100-Enable-L2-cache.patch @@ -0,0 +1,34 @@ +From 44190534ecc21378fe400df0ba872f720f4578ff Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Thu, 16 Feb 2017 18:54:39 +0100 +Subject: [PATCH 084/286] ARM: 8660/1: shmobile: r7s72100: Enable L2 cache + +Even though L2C is specified in the DT, you still need to add the aux +settings in the machine_desc. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> +(cherry picked from commit a96bb197693eb9e7a7221867bd944ccd6b6e12e6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/mach-shmobile/setup-r7s72100.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c +index d46639fc6849..319ca9508ec6 100644 +--- a/arch/arm/mach-shmobile/setup-r7s72100.c ++++ b/arch/arm/mach-shmobile/setup-r7s72100.c +@@ -26,6 +26,8 @@ static const char *const r7s72100_boards_compat_dt[] __initconst = { + }; + + DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") ++ .l2c_aux_val = 0, ++ .l2c_aux_mask = ~0, + .init_early = shmobile_init_delay, + .init_late = shmobile_init_late, + .dt_compat = r7s72100_boards_compat_dt, +-- +2.13.3 + diff --git a/patches.renesas/0085-phy-rcar-gen3-usb2-fix-implementation-for-runtime-PM.patch b/patches.renesas/0085-phy-rcar-gen3-usb2-fix-implementation-for-runtime-PM.patch new file mode 100644 index 00000000000000..f0579b718a2e58 --- /dev/null +++ b/patches.renesas/0085-phy-rcar-gen3-usb2-fix-implementation-for-runtime-PM.patch @@ -0,0 +1,108 @@ +From 7d5313842c13ce15381188961da37b1919c1b842 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Tue, 14 Mar 2017 08:37:40 +0900 +Subject: [PATCH 085/286] phy: rcar-gen3-usb2: fix implementation for runtime + PM + +This patch fixes an issue that this driver doesn't take care of the runtime +PM. This code assumed that devm_phy_create() called pm_runtime_enable(dev), +but it misunderstood the dev_phy_create()'s specification. +This driver should call its own pm_runtime_enable() before +dev_phy_create(). + +Fixes: f3b5a8d9b50d ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver") +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> +(cherry picked from commit 441a681b8843474c9796b50c35794ff102701f37) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/phy/phy-rcar-gen3-usb2.c | 31 ++++++++++++++++++++++++------- + 1 file changed, 24 insertions(+), 7 deletions(-) + +diff --git a/drivers/phy/phy-rcar-gen3-usb2.c b/drivers/phy/phy-rcar-gen3-usb2.c +index 54a83675f0a8..e35af04301ac 100644 +--- a/drivers/phy/phy-rcar-gen3-usb2.c ++++ b/drivers/phy/phy-rcar-gen3-usb2.c +@@ -20,6 +20,7 @@ + #include <linux/of_address.h> + #include <linux/phy/phy.h> + #include <linux/platform_device.h> ++#include <linux/pm_runtime.h> + #include <linux/regulator/consumer.h> + #include <linux/workqueue.h> + +@@ -395,7 +396,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) + struct rcar_gen3_chan *channel; + struct phy_provider *provider; + struct resource *res; +- int irq; ++ int irq, ret = 0; + + if (!dev->of_node) { + dev_err(dev, "This driver needs device tree\n"); +@@ -434,17 +435,24 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) + } + } + +- /* devm_phy_create() will call pm_runtime_enable(dev); */ ++ /* ++ * devm_phy_create() will call pm_runtime_enable(&phy->dev); ++ * And then, phy-core will manage runtime pm for this device. ++ */ ++ pm_runtime_enable(dev); + channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops); + if (IS_ERR(channel->phy)) { + dev_err(dev, "Failed to create USB2 PHY\n"); +- return PTR_ERR(channel->phy); ++ ret = PTR_ERR(channel->phy); ++ goto error; + } + + channel->vbus = devm_regulator_get_optional(dev, "vbus"); + if (IS_ERR(channel->vbus)) { +- if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) +- return PTR_ERR(channel->vbus); ++ if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) { ++ ret = PTR_ERR(channel->vbus); ++ goto error; ++ } + channel->vbus = NULL; + } + +@@ -454,15 +462,22 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (IS_ERR(provider)) { + dev_err(dev, "Failed to register PHY provider\n"); ++ ret = PTR_ERR(provider); ++ goto error; + } else if (channel->has_otg) { + int ret; + + ret = device_create_file(dev, &dev_attr_role); + if (ret < 0) +- return ret; ++ goto error; + } + +- return PTR_ERR_OR_ZERO(provider); ++ return 0; ++ ++error: ++ pm_runtime_disable(dev); ++ ++ return ret; + } + + static int rcar_gen3_phy_usb2_remove(struct platform_device *pdev) +@@ -472,6 +487,8 @@ static int rcar_gen3_phy_usb2_remove(struct platform_device *pdev) + if (channel->has_otg) + device_remove_file(&pdev->dev, &dev_attr_role); + ++ pm_runtime_disable(&pdev->dev); ++ + return 0; + }; + +-- +2.13.3 + diff --git a/patches.renesas/0086-dmaengine-rcar-dmac-enable-descriptor-mode-on-40bit.patch b/patches.renesas/0086-dmaengine-rcar-dmac-enable-descriptor-mode-on-40bit.patch new file mode 100644 index 00000000000000..130fd03e649097 --- /dev/null +++ b/patches.renesas/0086-dmaengine-rcar-dmac-enable-descriptor-mode-on-40bit.patch @@ -0,0 +1,133 @@ +From bf0a6232ae78482a78127bb1a39e7ec09d1cfb37 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 Mar 2017 04:22:36 +0000 +Subject: [PATCH 086/286] dmaengine: rcar-dmac: enable descriptor mode on 40bit + +SYS-DMAC can use 40bit address transfer, and it supports Descriptor +Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was +40bit address today. But it can use Descriptor Mode with 40bit if +transfer Source/Destination address are located in same 4GiB region +in the 40 bit address space. +This patch enables it if all condition was clear + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit 1175f83cdb7a321b8b7b061d18846d58490b2654) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/dma/sh/rcar-dmac.c | 52 ++++++++++++++++++++++++++++------------------ + 1 file changed, 32 insertions(+), 20 deletions(-) + +diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c +index 48b22d5c8602..db41795fe42a 100644 +--- a/drivers/dma/sh/rcar-dmac.c ++++ b/drivers/dma/sh/rcar-dmac.c +@@ -344,13 +344,19 @@ static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan) + rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid); + + if (desc->hwdescs.use) { +- struct rcar_dmac_xfer_chunk *chunk; ++ struct rcar_dmac_xfer_chunk *chunk = ++ list_first_entry(&desc->chunks, ++ struct rcar_dmac_xfer_chunk, node); + + dev_dbg(chan->chan.device->dev, + "chan%u: queue desc %p: %u@%pad\n", + chan->index, desc, desc->nchunks, &desc->hwdescs.dma); + + #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT ++ rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR, ++ chunk->src_addr >> 32); ++ rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR, ++ chunk->dst_addr >> 32); + rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE, + desc->hwdescs.dma >> 32); + #endif +@@ -368,8 +374,6 @@ static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan) + * should. Initialize it manually with the destination address + * of the first chunk. + */ +- chunk = list_first_entry(&desc->chunks, +- struct rcar_dmac_xfer_chunk, node); + rcar_dmac_chan_write(chan, RCAR_DMADAR, + chunk->dst_addr & 0xffffffff); + +@@ -855,8 +859,12 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, + unsigned int nchunks = 0; + unsigned int max_chunk_size; + unsigned int full_size = 0; +- bool highmem = false; ++ bool cross_boundary = false; + unsigned int i; ++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT ++ u32 high_dev_addr; ++ u32 high_mem_addr; ++#endif + + desc = rcar_dmac_desc_get(chan); + if (!desc) +@@ -882,6 +890,16 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, + + full_size += len; + ++#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT ++ if (i == 0) { ++ high_dev_addr = dev_addr >> 32; ++ high_mem_addr = mem_addr >> 32; ++ } ++ ++ if ((dev_addr >> 32 != high_dev_addr) || ++ (mem_addr >> 32 != high_mem_addr)) ++ cross_boundary = true; ++#endif + while (len) { + unsigned int size = min(len, max_chunk_size); + +@@ -890,18 +908,14 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, + * Prevent individual transfers from crossing 4GB + * boundaries. + */ +- if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) ++ if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) { + size = ALIGN(dev_addr, 1ULL << 32) - dev_addr; +- if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) ++ cross_boundary = true; ++ } ++ if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) { + size = ALIGN(mem_addr, 1ULL << 32) - mem_addr; +- +- /* +- * Check if either of the source or destination address +- * can't be expressed in 32 bits. If so we can't use +- * hardware descriptor lists. +- */ +- if (dev_addr >> 32 || mem_addr >> 32) +- highmem = true; ++ cross_boundary = true; ++ } + #endif + + chunk = rcar_dmac_xfer_chunk_get(chan); +@@ -943,13 +957,11 @@ rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl, + * Use hardware descriptor lists if possible when more than one chunk + * needs to be transferred (otherwise they don't make much sense). + * +- * The highmem check currently covers the whole transfer. As an +- * optimization we could use descriptor lists for consecutive lowmem +- * chunks and direct manual mode for highmem chunks. Whether the +- * performance improvement would be significant enough compared to the +- * additional complexity remains to be investigated. ++ * Source/Destination address should be located in same 4GiB region ++ * in the 40bit address space when it uses Hardware descriptor, ++ * and cross_boundary is checking it. + */ +- desc->hwdescs.use = !highmem && nchunks > 1; ++ desc->hwdescs.use = !cross_boundary && nchunks > 1; + if (desc->hwdescs.use) { + if (rcar_dmac_fill_hwdesc(chan, desc) < 0) + desc->hwdescs.use = false; +-- +2.13.3 + diff --git a/patches.renesas/0087-rcar-dmac-fixup-descriptor-pointer-for-descriptor-mo.patch b/patches.renesas/0087-rcar-dmac-fixup-descriptor-pointer-for-descriptor-mo.patch new file mode 100644 index 00000000000000..38ccd71c0239de --- /dev/null +++ b/patches.renesas/0087-rcar-dmac-fixup-descriptor-pointer-for-descriptor-mo.patch @@ -0,0 +1,37 @@ +From acd40bdff4c20d4f347a1baa9df718a9fd3a0286 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 23 May 2017 07:08:43 +0000 +Subject: [PATCH 087/286] rcar-dmac: fixup descriptor pointer for descriptor + mode + +In descriptor mode, the descriptor running pointer is not maintained +by the interrupt handler, thus, driver finds the running descriptor +from the descriptor pointer field in the CHCRB register. +But, CHCRB::DPTR indicates *next* descriptor pointer, not current. +Thus, The residue calculation will be missed. This patch fixup it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Vinod Koul <vinod.koul@intel.com> +(cherry picked from commit 56b177055adb246cdeca174331dbf92fc49bfccd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/dma/sh/rcar-dmac.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c +index db41795fe42a..bd261c9e9664 100644 +--- a/drivers/dma/sh/rcar-dmac.c ++++ b/drivers/dma/sh/rcar-dmac.c +@@ -1287,6 +1287,9 @@ static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan, + if (desc->hwdescs.use) { + dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) & + RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT; ++ if (dptr == 0) ++ dptr = desc->nchunks; ++ dptr--; + WARN_ON(dptr >= desc->nchunks); + } else { + running = desc->running; +-- +2.13.3 + diff --git a/patches.renesas/0088-soc-renesas-Provide-dummy-rcar_rst_read_mode_pins-fo.patch b/patches.renesas/0088-soc-renesas-Provide-dummy-rcar_rst_read_mode_pins-fo.patch new file mode 100644 index 00000000000000..facebbab355add --- /dev/null +++ b/patches.renesas/0088-soc-renesas-Provide-dummy-rcar_rst_read_mode_pins-fo.patch @@ -0,0 +1,43 @@ +From 1b2556d563072a770f7d9efb1a175d4d9dd5bd16 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 25 Apr 2017 19:36:25 +0200 +Subject: [PATCH 088/286] soc: renesas: Provide dummy rcar_rst_read_mode_pins() + for compile-testing + +If the R-Car RST driver is not included, compile-testing R-Car clock +drivers fails with a link error: + + undefined reference to `rcar_rst_read_mode_pins' + +To fix this, provide a dummy version. Use the exact same test logic as +in drivers/soc/renesas/Makefile, as there is no Kconfig symbol (yet) to +control compilation of the R-Car RST driver. + +Fixes: 527c02f66d263d2e ("soc: renesas: Add R-Car RST driver") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7b4ccb3c466f62bbf2f4dd5d6a143d945a6f3051) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/linux/soc/renesas/rcar-rst.h | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/include/linux/soc/renesas/rcar-rst.h b/include/linux/soc/renesas/rcar-rst.h +index a18e0783946b..787e7ad53d45 100644 +--- a/include/linux/soc/renesas/rcar-rst.h ++++ b/include/linux/soc/renesas/rcar-rst.h +@@ -1,6 +1,11 @@ + #ifndef __LINUX_SOC_RENESAS_RCAR_RST_H__ + #define __LINUX_SOC_RENESAS_RCAR_RST_H__ + ++#if defined(CONFIG_ARCH_RCAR_GEN1) || defined(CONFIG_ARCH_RCAR_GEN2) || \ ++ defined(CONFIG_ARCH_R8A7795) || defined(CONFIG_ARCH_R8A7796) + int rcar_rst_read_mode_pins(u32 *mode); ++#else ++static inline int rcar_rst_read_mode_pins(u32 *mode) { return -ENODEV; } ++#endif + + #endif /* __LINUX_SOC_RENESAS_RCAR_RST_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0089-ASoC-rsnd-drop-useles-self-assignments.patch b/patches.renesas/0089-ASoC-rsnd-drop-useles-self-assignments.patch new file mode 100644 index 00000000000000..d6d16048adbf17 --- /dev/null +++ b/patches.renesas/0089-ASoC-rsnd-drop-useles-self-assignments.patch @@ -0,0 +1,36 @@ +From fc91b2c92c7e301c0089745ad96a77bbdc006a03 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 20 Feb 2017 21:58:34 +0100 +Subject: [PATCH 089/286] ASoC: rsnd: drop useles self-assignments + +Coverity reported (CID 1397992) this self-assignment. I think the code +stays readable even with the assignments removed. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 34157f7bec8276b4296cf2ec172fc13385ac8af7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 47b370cb2d3b..24adb3cc17aa 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -674,12 +674,10 @@ static int rsnd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + /* set clock inversion */ + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_IF: +- rdai->bit_clk_inv = rdai->bit_clk_inv; + rdai->frm_clk_inv = !rdai->frm_clk_inv; + break; + case SND_SOC_DAIFMT_IB_NF: + rdai->bit_clk_inv = !rdai->bit_clk_inv; +- rdai->frm_clk_inv = rdai->frm_clk_inv; + break; + case SND_SOC_DAIFMT_IB_IF: + rdai->bit_clk_inv = !rdai->bit_clk_inv; +-- +2.13.3 + diff --git a/patches.renesas/0090-ASoC-rsnd-check-return-value-of-init-function.patch b/patches.renesas/0090-ASoC-rsnd-check-return-value-of-init-function.patch new file mode 100644 index 00000000000000..cbf3e1f0f684d9 --- /dev/null +++ b/patches.renesas/0090-ASoC-rsnd-check-return-value-of-init-function.patch @@ -0,0 +1,45 @@ +From 50813a270801972fe172e06ea55fbe310fa25822 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 20 Feb 2017 22:05:07 +0100 +Subject: [PATCH 090/286] ASoC: rsnd: check return value of init function + +Currently, this function cannot fail for the ADG case. Still, let's +apply defensive programming techniques to make sure we fail gracefully +whenever rsnd_mod_init() gets extended with another failure case. +Reported by Coverity (CID 1397893). + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 56d2c61d611a50e58dba521be1325dc90f9cc933) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 85a33ac0a5c4..54146f66538c 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -564,6 +564,7 @@ int rsnd_adg_probe(struct rsnd_priv *priv) + struct rsnd_adg *adg; + struct device *dev = rsnd_priv_to_dev(priv); + struct device_node *np = dev->of_node; ++ int ret; + + adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); + if (!adg) { +@@ -571,8 +572,10 @@ int rsnd_adg_probe(struct rsnd_priv *priv) + return -ENOMEM; + } + +- rsnd_mod_init(priv, &adg->mod, &adg_ops, ++ ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, + NULL, NULL, 0, 0); ++ if (ret) ++ return ret; + + rsnd_adg_get_clkin(priv, adg); + rsnd_adg_get_clkout(priv, adg); +-- +2.13.3 + diff --git a/patches.renesas/0091-ASoC-rcar-enable-PCM-RATE-untile-192000.patch b/patches.renesas/0091-ASoC-rcar-enable-PCM-RATE-untile-192000.patch new file mode 100644 index 00000000000000..9797dd8ef9ebb0 --- /dev/null +++ b/patches.renesas/0091-ASoC-rcar-enable-PCM-RATE-untile-192000.patch @@ -0,0 +1,32 @@ +From 252ca21bffaf817c340f53af3339ef879147e0c0 Mon Sep 17 00:00:00 2001 +From: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Date: Wed, 22 Mar 2017 05:43:35 +0000 +Subject: [PATCH 091/286] ASoC: rcar: enable PCM RATE untile 192000 + +R-Car sound can handle untile 192000 rate. + +Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit dc2721564f6da549f6eb29ac5bca28d65beadcb7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 24adb3cc17aa..672783e18711 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -96,7 +96,7 @@ + #include <linux/pm_runtime.h> + #include "rsnd.h" + +-#define RSND_RATES SNDRV_PCM_RATE_8000_96000 ++#define RSND_RATES SNDRV_PCM_RATE_8000_192000 + #define RSND_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) + + static const struct of_device_id rsnd_of_match[] = { +-- +2.13.3 + diff --git a/patches.renesas/0092-ASoC-rcar-ssi-don-t-set-SSICR.CKDV-000-with-SSIWSR.C.patch b/patches.renesas/0092-ASoC-rcar-ssi-don-t-set-SSICR.CKDV-000-with-SSIWSR.C.patch new file mode 100644 index 00000000000000..9bfb47ef4543ae --- /dev/null +++ b/patches.renesas/0092-ASoC-rcar-ssi-don-t-set-SSICR.CKDV-000-with-SSIWSR.C.patch @@ -0,0 +1,44 @@ +From 30441b6767296017619be3dab7e658c204d526ab Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 22 Mar 2017 04:02:43 +0000 +Subject: [PATCH 092/286] ASoC: rcar: ssi: don't set SSICR.CKDV = 000 with + SSIWSR.CONT + +R-Car Datasheet is indicating "SSICR.CKDV = 000 is invalid when +SSIWSR.WS_MODE = 1 or SSIWSR.CONT = 1". +Current driver will set CONT, thus, we shouldn't use CKDV = 000. +This patch fixup it. + +Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 6b8530cc056efd4a11b034ca5b1e9f7e9563f553) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ssi.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index 411bda2387ad..135c5669f796 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -228,6 +228,15 @@ static int rsnd_ssi_master_clk_start(struct rsnd_mod *mod, + for (j = 0; j < ARRAY_SIZE(ssi_clk_mul_table); j++) { + + /* ++ * It will set SSIWSR.CONT here, but SSICR.CKDV = 000 ++ * with it is not allowed. (SSIWSR.WS_MODE with ++ * SSICR.CKDV = 000 is not allowed either). ++ * Skip it. See SSICR.CKDV ++ */ ++ if (j == 0) ++ continue; ++ ++ /* + * this driver is assuming that + * system word is 32bit x chan + * see rsnd_ssi_init() +-- +2.13.3 + diff --git a/patches.renesas/0093-ASoC-rcar-remove-rsnd_kctrl_remove.patch b/patches.renesas/0093-ASoC-rcar-remove-rsnd_kctrl_remove.patch new file mode 100644 index 00000000000000..0451fe3996d8d0 --- /dev/null +++ b/patches.renesas/0093-ASoC-rcar-remove-rsnd_kctrl_remove.patch @@ -0,0 +1,94 @@ +From 4af6bb2bc9279f9acb617ae18c3d57d98ec59bc7 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 28 Mar 2017 02:31:23 +0000 +Subject: [PATCH 093/286] ASoC: rcar: remove rsnd_kctrl_remove() + +Current rcar driver is trying to remove kctrl when remove time. +But, 1) rcar driver can't/shouldn't remove before removing sound +card driver, 2) sound card driver will call snd_ctl_dev_free() +and removes all kctrls by snd_ctl_remove(). +Thus, rsnd_kctrl_remove() is not necessary. Current implementation +will get Oops when removing rcar driver after sound card. +This patch fix this issue. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e0c4211854bfebd5507761a2bfddaa9e37074230) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 9 --------- + sound/soc/sh/rcar/dvc.c | 16 ---------------- + sound/soc/sh/rcar/rsnd.h | 3 --- + 3 files changed, 28 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 672783e18711..35c96e4bbd64 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -1037,15 +1037,6 @@ static int __rsnd_kctrl_new(struct rsnd_mod *mod, + return 0; + } + +-void _rsnd_kctrl_remove(struct rsnd_kctrl_cfg *cfg) +-{ +- if (cfg->card && cfg->kctrl) +- snd_ctl_remove(cfg->card, cfg->kctrl); +- +- cfg->card = NULL; +- cfg->kctrl = NULL; +-} +- + int rsnd_kctrl_new_m(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct snd_soc_pcm_runtime *rtd, +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index cf8f59cdd8d7..994fdb7d0034 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -218,21 +218,6 @@ static int rsnd_dvc_probe_(struct rsnd_mod *mod, + return rsnd_cmd_attach(io, rsnd_mod_id(mod)); + } + +-static int rsnd_dvc_remove_(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct rsnd_priv *priv) +-{ +- struct rsnd_dvc *dvc = rsnd_mod_to_dvc(mod); +- +- rsnd_kctrl_remove(dvc->volume); +- rsnd_kctrl_remove(dvc->mute); +- rsnd_kctrl_remove(dvc->ren); +- rsnd_kctrl_remove(dvc->rup); +- rsnd_kctrl_remove(dvc->rdown); +- +- return 0; +-} +- + static int rsnd_dvc_init(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct rsnd_priv *priv) +@@ -332,7 +317,6 @@ static struct rsnd_mod_ops rsnd_dvc_ops = { + .name = DVC_NAME, + .dma_req = rsnd_dvc_dma_req, + .probe = rsnd_dvc_probe_, +- .remove = rsnd_dvc_remove_, + .init = rsnd_dvc_init, + .quit = rsnd_dvc_quit, + .pcm_new = rsnd_dvc_pcm_new, +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 7410ec0174db..81ef3f18834a 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -611,9 +611,6 @@ struct rsnd_kctrl_cfg_s { + u32 val; + }; + +-void _rsnd_kctrl_remove(struct rsnd_kctrl_cfg *cfg); +-#define rsnd_kctrl_remove(_cfg) _rsnd_kctrl_remove(&((_cfg).cfg)) +- + int rsnd_kctrl_new_m(struct rsnd_mod *mod, + struct rsnd_dai_stream *io, + struct snd_soc_pcm_runtime *rtd, +-- +2.13.3 + diff --git a/patches.renesas/0094-ASoC-rcar-fixup-of_clk_add_provider-usage-for-multi-.patch b/patches.renesas/0094-ASoC-rcar-fixup-of_clk_add_provider-usage-for-multi-.patch new file mode 100644 index 00000000000000..eb6bfe24addedf --- /dev/null +++ b/patches.renesas/0094-ASoC-rcar-fixup-of_clk_add_provider-usage-for-multi-.patch @@ -0,0 +1,48 @@ +From 420dadd1d49dc0e4a8d32543cc5c5495205350e8 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 30 Mar 2017 01:49:06 +0000 +Subject: [PATCH 094/286] ASoC: rcar: fixup of_clk_add_provider() usage for + multi clkout + +Current adg is calling of_clk_add_povider() multiple times, +but it is not correct usage. This patch fixup its parameter +and call it once. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit d7f298197a22f11b38059f257842dac7c30a564c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 14 ++++++-------- + 1 file changed, 6 insertions(+), 8 deletions(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 54146f66538c..33378618deeb 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -537,16 +537,14 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + clk = clk_register_fixed_rate(dev, clkout_name[i], + parent_clk_name, 0, + req_rate); +- if (!IS_ERR(clk)) { +- adg->onecell.clks = adg->clkout; +- adg->onecell.clk_num = CLKOUTMAX; +- ++ adg->clkout[i] = ERR_PTR(-ENOENT); ++ if (!IS_ERR(clk)) + adg->clkout[i] = clk; +- +- of_clk_add_provider(np, of_clk_src_onecell_get, +- &adg->onecell); +- } + } ++ adg->onecell.clks = adg->clkout; ++ adg->onecell.clk_num = CLKOUTMAX; ++ of_clk_add_provider(np, of_clk_src_onecell_get, ++ &adg->onecell); + } + + adg->ckr = ckr; +-- +2.13.3 + diff --git a/patches.renesas/0095-ASoC-rcar-call-missing-of_clk_del_provider-when-remo.patch b/patches.renesas/0095-ASoC-rcar-call-missing-of_clk_del_provider-when-remo.patch new file mode 100644 index 00000000000000..e22ec802935ce0 --- /dev/null +++ b/patches.renesas/0095-ASoC-rcar-call-missing-of_clk_del_provider-when-remo.patch @@ -0,0 +1,36 @@ +From 6353731d1067bdacf9759317c51c880924db1f22 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 30 Mar 2017 01:49:27 +0000 +Subject: [PATCH 095/286] ASoC: rcar: call missing of_clk_del_provider() when + remove + +adg is calling of_clk_add_provider() when probe time, +thus, remove should call of_clk_del_provider(), it doesn't now. +This patch fix this issue. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit b5aac5a9adf667f907c34c520e023bc19f8c226c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 33378618deeb..214a9ce90bb4 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -590,5 +590,10 @@ int rsnd_adg_probe(struct rsnd_priv *priv) + + void rsnd_adg_remove(struct rsnd_priv *priv) + { ++ struct device *dev = rsnd_priv_to_dev(priv); ++ struct device_node *np = dev->of_node; ++ ++ of_clk_del_provider(np); ++ + rsnd_adg_clk_disable(priv); + } +-- +2.13.3 + diff --git a/patches.renesas/0096-ASoC-rsnd-tidyup-src-convert_rate-reset-timing.patch b/patches.renesas/0096-ASoC-rsnd-tidyup-src-convert_rate-reset-timing.patch new file mode 100644 index 00000000000000..fbaaf6241562a9 --- /dev/null +++ b/patches.renesas/0096-ASoC-rsnd-tidyup-src-convert_rate-reset-timing.patch @@ -0,0 +1,52 @@ +From bcf8ce0f63df36c4b9741a8e2589dedfbbfcb367 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 6 Apr 2017 07:24:36 +0000 +Subject: [PATCH 096/286] ASoC: rsnd: tidyup src->convert_rate reset timing + +Current src->convert_rate will be set on .hw_param, and +be reset on .quit timing. +But, .hw_param will not be called again if user did Ctrl-Z + fg. +It should be reset on initial of .hw_param to keep its value. +Here, ctu.c already do this. +This patch solves this issue, other wise, MIXed sound will be +strange if user did like below. + + > aplay -D plughw:0,0 sound_44100.wav & + > aplay -D plughw:0,1 sound_96000.wav + > Ctrl-Z + > fg # 96kHz will be played as 44.1kHz + +Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit fc99d23f6d3ec6b17772915114018444393e0ad1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/src.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 42db48db09ba..20b5b2ec625e 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -167,6 +167,7 @@ static int rsnd_src_hw_params(struct rsnd_mod *mod, + * dpcm_fe_dai_hw_params() + * dpcm_be_dai_hw_params() + */ ++ src->convert_rate = 0; + if (fe->dai_link->dynamic) { + int stream = substream->stream; + struct snd_soc_dpcm *dpcm; +@@ -414,8 +415,6 @@ static int rsnd_src_quit(struct rsnd_mod *mod, + + rsnd_mod_power_off(mod); + +- src->convert_rate = 0; +- + /* reset sync convert_rate */ + src->sync.val = 0; + +-- +2.13.3 + diff --git a/patches.renesas/0097-ASoC-rsnd-merge-rsnd_kctrl_new_m-s-e-into-rsnd_kctrl.patch b/patches.renesas/0097-ASoC-rsnd-merge-rsnd_kctrl_new_m-s-e-into-rsnd_kctrl.patch new file mode 100644 index 00000000000000..42483fc5fe12d3 --- /dev/null +++ b/patches.renesas/0097-ASoC-rsnd-merge-rsnd_kctrl_new_m-s-e-into-rsnd_kctrl.patch @@ -0,0 +1,237 @@ +From 51ebea31c27d49c9d12270062e64269b9fef4bad Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Thu, 6 Apr 2017 07:25:13 +0000 +Subject: [PATCH 097/286] ASoC: rsnd: merge rsnd_kctrl_new_m/s/e into + rsnd_kctrl_new() + +Current rsnd driver is using rsnd_kctrl_new_m/s/e function, +but the differences are very few. +This patch merge these rsnd_kctrl_new_m/s/e into rsnd_kctrl_new + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 32973dcf71ebee8806a6ee552665c5fad6857e16) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 96 +++++++++++++++++------------------------------- + sound/soc/sh/rcar/dvc.c | 8 ++-- + sound/soc/sh/rcar/rsnd.h | 50 ++++++++++++------------- + 3 files changed, 62 insertions(+), 92 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 35c96e4bbd64..f8eb9d3d1949 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -1000,13 +1000,30 @@ static int rsnd_kctrl_put(struct snd_kcontrol *kctrl, + return change; + } + +-static int __rsnd_kctrl_new(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- struct rsnd_kctrl_cfg *cfg, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod)) ++struct rsnd_kctrl_cfg *rsnd_kctrl_init_m(struct rsnd_kctrl_cfg_m *cfg) ++{ ++ cfg->cfg.val = cfg->val; ++ ++ return &cfg->cfg; ++} ++ ++struct rsnd_kctrl_cfg *rsnd_kctrl_init_s(struct rsnd_kctrl_cfg_s *cfg) ++{ ++ cfg->cfg.val = &cfg->val; ++ ++ return &cfg->cfg; ++} ++ ++int rsnd_kctrl_new(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct snd_soc_pcm_runtime *rtd, ++ const unsigned char *name, ++ void (*update)(struct rsnd_dai_stream *io, ++ struct rsnd_mod *mod), ++ struct rsnd_kctrl_cfg *cfg, ++ const char * const *texts, ++ int size, ++ u32 max) + { + struct snd_card *card = rtd->card->snd_card; + struct snd_kcontrol *kctrl; +@@ -1021,6 +1038,9 @@ static int __rsnd_kctrl_new(struct rsnd_mod *mod, + }; + int ret; + ++ if (size > RSND_MAX_CHANNELS) ++ return -EINVAL; ++ + kctrl = snd_ctl_new1(&knew, mod); + if (!kctrl) + return -ENOMEM; +@@ -1029,65 +1049,17 @@ static int __rsnd_kctrl_new(struct rsnd_mod *mod, + if (ret < 0) + return ret; + +- cfg->update = update; +- cfg->card = card; +- cfg->kctrl = kctrl; +- cfg->io = io; ++ cfg->texts = texts; ++ cfg->max = max; ++ cfg->size = size; ++ cfg->update = update; ++ cfg->card = card; ++ cfg->kctrl = kctrl; ++ cfg->io = io; + + return 0; + } + +-int rsnd_kctrl_new_m(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- struct rsnd_kctrl_cfg_m *_cfg, +- int ch_size, +- u32 max) +-{ +- if (ch_size > RSND_MAX_CHANNELS) +- return -EINVAL; +- +- _cfg->cfg.max = max; +- _cfg->cfg.size = ch_size; +- _cfg->cfg.val = _cfg->val; +- return __rsnd_kctrl_new(mod, io, rtd, name, &_cfg->cfg, update); +-} +- +-int rsnd_kctrl_new_s(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- struct rsnd_kctrl_cfg_s *_cfg, +- u32 max) +-{ +- _cfg->cfg.max = max; +- _cfg->cfg.size = 1; +- _cfg->cfg.val = &_cfg->val; +- return __rsnd_kctrl_new(mod, io, rtd, name, &_cfg->cfg, update); +-} +- +-int rsnd_kctrl_new_e(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- struct rsnd_kctrl_cfg_s *_cfg, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- const char * const *texts, +- u32 max) +-{ +- _cfg->cfg.max = max; +- _cfg->cfg.size = 1; +- _cfg->cfg.val = &_cfg->val; +- _cfg->cfg.texts = texts; +- return __rsnd_kctrl_new(mod, io, rtd, name, &_cfg->cfg, update); +-} +- + /* + * snd_soc_platform + */ +diff --git a/sound/soc/sh/rcar/dvc.c b/sound/soc/sh/rcar/dvc.c +index 994fdb7d0034..463de8360985 100644 +--- a/sound/soc/sh/rcar/dvc.c ++++ b/sound/soc/sh/rcar/dvc.c +@@ -285,18 +285,18 @@ static int rsnd_dvc_pcm_new(struct rsnd_mod *mod, + ret = rsnd_kctrl_new_e(mod, io, rtd, + is_play ? + "DVC Out Ramp Up Rate" : "DVC In Ramp Up Rate", +- &dvc->rup, + rsnd_dvc_volume_update, +- dvc_ramp_rate, ARRAY_SIZE(dvc_ramp_rate)); ++ &dvc->rup, ++ dvc_ramp_rate); + if (ret < 0) + return ret; + + ret = rsnd_kctrl_new_e(mod, io, rtd, + is_play ? + "DVC Out Ramp Down Rate" : "DVC In Ramp Down Rate", +- &dvc->rdown, + rsnd_dvc_volume_update, +- dvc_ramp_rate, ARRAY_SIZE(dvc_ramp_rate)); ++ &dvc->rdown, ++ dvc_ramp_rate); + + if (ret < 0) + return ret; +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 81ef3f18834a..3dc9e06f5943 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -611,32 +611,30 @@ struct rsnd_kctrl_cfg_s { + u32 val; + }; + +-int rsnd_kctrl_new_m(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- struct rsnd_kctrl_cfg_m *_cfg, +- int ch_size, +- u32 max); +-int rsnd_kctrl_new_s(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- struct rsnd_kctrl_cfg_s *_cfg, +- u32 max); +-int rsnd_kctrl_new_e(struct rsnd_mod *mod, +- struct rsnd_dai_stream *io, +- struct snd_soc_pcm_runtime *rtd, +- const unsigned char *name, +- struct rsnd_kctrl_cfg_s *_cfg, +- void (*update)(struct rsnd_dai_stream *io, +- struct rsnd_mod *mod), +- const char * const *texts, +- u32 max); ++struct rsnd_kctrl_cfg *rsnd_kctrl_init_m(struct rsnd_kctrl_cfg_m *cfg); ++struct rsnd_kctrl_cfg *rsnd_kctrl_init_s(struct rsnd_kctrl_cfg_s *cfg); ++int rsnd_kctrl_new(struct rsnd_mod *mod, ++ struct rsnd_dai_stream *io, ++ struct snd_soc_pcm_runtime *rtd, ++ const unsigned char *name, ++ void (*update)(struct rsnd_dai_stream *io, ++ struct rsnd_mod *mod), ++ struct rsnd_kctrl_cfg *cfg, ++ const char * const *texts, ++ int size, ++ u32 max); ++ ++#define rsnd_kctrl_new_m(mod, io, rtd, name, update, cfg, size, max) \ ++ rsnd_kctrl_new(mod, io, rtd, name, update, rsnd_kctrl_init_m(cfg), \ ++ NULL, size, max) ++ ++#define rsnd_kctrl_new_s(mod, io, rtd, name, update, cfg, max) \ ++ rsnd_kctrl_new(mod, io, rtd, name, update, rsnd_kctrl_init_s(cfg), \ ++ NULL, 1, max) ++ ++#define rsnd_kctrl_new_e(mod, io, rtd, name, update, cfg, texts) \ ++ rsnd_kctrl_new(mod, io, rtd, name, update, rsnd_kctrl_init_s(cfg), \ ++ texts, 1, ARRAY_SIZE(texts)) + + /* + * R-Car SSI +-- +2.13.3 + diff --git a/patches.renesas/0098-ASoC-rsnd-rsnd_mod_make_sure-is-not-under-DEBUG.patch b/patches.renesas/0098-ASoC-rsnd-rsnd_mod_make_sure-is-not-under-DEBUG.patch new file mode 100644 index 00000000000000..127c7773e6bf54 --- /dev/null +++ b/patches.renesas/0098-ASoC-rsnd-rsnd_mod_make_sure-is-not-under-DEBUG.patch @@ -0,0 +1,55 @@ +From 2f2c00ce9b9915cc70995ecdee13a059a70ef6d4 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 19 Apr 2017 00:41:24 +0000 +Subject: [PATCH 098/286] ASoC: rsnd: rsnd_mod_make_sure() is not under DEBUG + +rsnd_mod_make_sure() will be used any situation, +thus, under DEBUG is not realistic. +This patch move it to non DEBUG area + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 9ca5e57d78446c8bd42adff3dcae693703f91d9c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/core.c | 2 -- + sound/soc/sh/rcar/rsnd.h | 2 +- + 2 files changed, 1 insertion(+), 3 deletions(-) + +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index f8eb9d3d1949..1744015408c3 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -110,7 +110,6 @@ MODULE_DEVICE_TABLE(of, rsnd_of_match); + /* + * rsnd_mod functions + */ +-#ifdef DEBUG + void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type) + { + if (mod->type != type) { +@@ -121,7 +120,6 @@ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type) + rsnd_mod_name(mod), rsnd_mod_id(mod)); + } + } +-#endif + + char *rsnd_mod_name(struct rsnd_mod *mod) + { +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index 3dc9e06f5943..dbf4163427e8 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -727,8 +727,8 @@ void rsnd_cmd_remove(struct rsnd_priv *priv); + int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id); + struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id); + +-#ifdef DEBUG + void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type); ++#ifdef DEBUG + #define rsnd_mod_confirm_ssi(mssi) rsnd_mod_make_sure(mssi, RSND_MOD_SSI) + #define rsnd_mod_confirm_src(msrc) rsnd_mod_make_sure(msrc, RSND_MOD_SRC) + #define rsnd_mod_confirm_dvc(mdvc) rsnd_mod_make_sure(mdvc, RSND_MOD_DVC) +-- +2.13.3 + diff --git a/patches.renesas/0099-ASoC-rsnd-enable-clock-frequency-for-both-44.1kHz-48.patch b/patches.renesas/0099-ASoC-rsnd-enable-clock-frequency-for-both-44.1kHz-48.patch new file mode 100644 index 00000000000000..7c73bb0b1add55 --- /dev/null +++ b/patches.renesas/0099-ASoC-rsnd-enable-clock-frequency-for-both-44.1kHz-48.patch @@ -0,0 +1,131 @@ +From c637f5ea01d84bb11aa2f31c1a07b73b37b81c73 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 19 Apr 2017 00:45:52 +0000 +Subject: [PATCH 099/286] ASoC: rsnd: enable clock-frequency for both + 44.1kHz/48kHz + +Current clock-frequency allows only 1 clock, but ADG can +handle both 44.1kHz/48kHz base clocks. This patch enables these. + +On Salvator-X board, AUDIO_CLKOUT which is generated by ADG +is connected to ak4613 MCKI, and it should be synchronized with +LRCK. Thus, we need both 44.1kHz/48kHz base clock-frequency. +Otherwise, either one sounds strange in high frequency sound. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 25165f79adc76b812bfb4d8f2ab120aafb28d0e6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 39 ++++++++++++++++++++++++++------------- + 1 file changed, 26 insertions(+), 13 deletions(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 214a9ce90bb4..96fef91b480c 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -43,6 +43,7 @@ struct rsnd_adg { + }; + + #define LRCLK_ASYNC (1 << 0) ++#define AUDIO_OUT_48 (1 << 1) + #define adg_mode_flags(adg) (adg->flags) + + #define for_each_rsnd_clk(pos, adg, i) \ +@@ -364,7 +365,10 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) + + rsnd_adg_set_ssi_clk(ssi_mod, data); + +- if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) { ++ if (adg_mode_flags(adg) & LRCLK_ASYNC) { ++ if (adg_mode_flags(adg) & AUDIO_OUT_48) ++ ckr = 0x80000000; ++ } else { + if (0 == (rate % 8000)) + ckr = 0x80000000; + } +@@ -427,11 +431,14 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + struct clk *clk; + struct device *dev = rsnd_priv_to_dev(priv); + struct device_node *np = dev->of_node; ++ struct property *prop; + u32 ckr, rbgx, rbga, rbgb; +- u32 rate, req_rate = 0, div; ++ u32 rate, div; ++#define REQ_SIZE 2 ++ u32 req_rate[REQ_SIZE] = {}; + uint32_t count = 0; + unsigned long req_48kHz_rate, req_441kHz_rate; +- int i; ++ int i, req_size; + const char *parent_clk_name = NULL; + static const char * const clkout_name[] = { + [CLKOUT] = "audio_clkout", +@@ -452,13 +459,18 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + * ADG supports BRRA/BRRB output only + * this means all clkout0/1/2/3 will be same rate + */ +- of_property_read_u32(np, "clock-frequency", &req_rate); ++ prop = of_find_property(np, "clock-frequency", NULL);; ++ req_size = prop->length / sizeof(u32); ++ ++ of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); + req_48kHz_rate = 0; + req_441kHz_rate = 0; +- if (0 == (req_rate % 44100)) +- req_441kHz_rate = req_rate; +- if (0 == (req_rate % 48000)) +- req_48kHz_rate = req_rate; ++ for (i = 0; i < req_size; i++) { ++ if (0 == (req_rate[i] % 44100)) ++ req_441kHz_rate = req_rate[i]; ++ if (0 == (req_rate[i] % 48000)) ++ req_48kHz_rate = req_rate[i]; ++ } + + /* + * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC +@@ -505,10 +517,8 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + rbgb = rbgx; + adg->rbgb_rate_for_48khz = rate / div; + ckr |= brg_table[i] << 16; +- if (req_48kHz_rate) { ++ if (req_48kHz_rate) + parent_clk_name = __clk_get_name(clk); +- ckr |= 0x80000000; +- } + } + } + } +@@ -523,7 +533,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + */ + if (!count) { + clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], +- parent_clk_name, 0, req_rate); ++ parent_clk_name, 0, req_rate[0]); + if (!IS_ERR(clk)) { + adg->clkout[CLKOUT] = clk; + of_clk_add_provider(np, of_clk_src_simple_get, clk); +@@ -536,7 +546,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + for (i = 0; i < CLKOUTMAX; i++) { + clk = clk_register_fixed_rate(dev, clkout_name[i], + parent_clk_name, 0, +- req_rate); ++ req_rate[0]); + adg->clkout[i] = ERR_PTR(-ENOENT); + if (!IS_ERR(clk)) + adg->clkout[i] = clk; +@@ -551,6 +561,9 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + adg->rbga = rbga; + adg->rbgb = rbgb; + ++ if (req_rate[0] % 48000 == 0) ++ adg->flags = AUDIO_OUT_48; ++ + for_each_rsnd_clkout(clk, adg, i) + dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); + dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", +-- +2.13.3 + diff --git a/patches.renesas/0100-ASoC-rsnd-fix-semicolon.cocci-warnings.patch b/patches.renesas/0100-ASoC-rsnd-fix-semicolon.cocci-warnings.patch new file mode 100644 index 00000000000000..4e0a7599a19d73 --- /dev/null +++ b/patches.renesas/0100-ASoC-rsnd-fix-semicolon.cocci-warnings.patch @@ -0,0 +1,36 @@ +From 5f5411d9434584fc9a0baa4033ec6e0e733b2bab Mon Sep 17 00:00:00 2001 +From: kbuild test robot <fengguang.wu@intel.com> +Date: Fri, 21 Apr 2017 13:02:57 +0800 +Subject: [PATCH 100/286] ASoC: rsnd: fix semicolon.cocci warnings + +sound/soc/sh/rcar/adg.c:462:54-55: Unneeded semicolon + + Remove unneeded semicolon. + +Generated by: scripts/coccinelle/misc/semicolon.cocci + +Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 75f9e4adb56fbb8ffaab7d316f0c02df00e4b755) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 96fef91b480c..faa1a4f09766 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -459,7 +459,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + * ADG supports BRRA/BRRB output only + * this means all clkout0/1/2/3 will be same rate + */ +- prop = of_find_property(np, "clock-frequency", NULL);; ++ prop = of_find_property(np, "clock-frequency", NULL); + req_size = prop->length / sizeof(u32); + + of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); +-- +2.13.3 + diff --git a/patches.renesas/0101-ASoC-rsnd-Fix-possible-NULL-pointer-dereference.patch b/patches.renesas/0101-ASoC-rsnd-Fix-possible-NULL-pointer-dereference.patch new file mode 100644 index 00000000000000..22dcdef382bd1b --- /dev/null +++ b/patches.renesas/0101-ASoC-rsnd-Fix-possible-NULL-pointer-dereference.patch @@ -0,0 +1,96 @@ +From ff192f55348f2b8a96118f72bb287e5ffd5cfdd2 Mon Sep 17 00:00:00 2001 +From: Marek Vasut <marek.vasut+renesas@gmail.com> +Date: Fri, 21 Apr 2017 00:41:20 +0000 +Subject: [PATCH 101/286] ASoC: rsnd: Fix possible NULL pointer dereference + +25165f79adc76b812bfb4d8f2ab120aafb28d0e6 +("ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz") +supports both 44.1kHz/48kHz clock-frequency settings for ADG +which will be used for AUDIO_OLKOUTn. +But some board doesn't need it, thus, it is not mandatory. + +But, above patch didn't care about the case of "clock-frequency" DT +property was not present. +This patch ignores ADG settings if AUDIO_OLKOUTn was not used. + +Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> +[Kuninori: tidyup not to break non AUDIO_OLKOUTn case] +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> + +(cherry picked from commit e8dffe6c2004278c588b3bb441a3dbe998a3f2e4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index faa1a4f09766..66203d107a11 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -453,13 +453,18 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + [CLKI] = 0x2, + }; + +- of_property_read_u32(np, "#clock-cells", &count); ++ ckr = 0; ++ rbga = 2; /* default 1/6 */ ++ rbgb = 2; /* default 1/6 */ + + /* + * ADG supports BRRA/BRRB output only + * this means all clkout0/1/2/3 will be same rate + */ + prop = of_find_property(np, "clock-frequency", NULL); ++ if (!prop) ++ goto rsnd_adg_get_clkout_end; ++ + req_size = prop->length / sizeof(u32); + + of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); +@@ -472,6 +477,9 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + req_48kHz_rate = req_rate[i]; + } + ++ if (req_rate[0] % 48000 == 0) ++ adg->flags = AUDIO_OUT_48; ++ + /* + * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC + * have 44.1kHz or 48kHz base clocks for now. +@@ -481,9 +489,6 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + * rsnd_adg_ssi_clk_try_start() + * rsnd_ssi_master_clk_start() + */ +- ckr = 0; +- rbga = 2; /* default 1/6 */ +- rbgb = 2; /* default 1/6 */ + adg->rbga_rate_for_441khz = 0; + adg->rbgb_rate_for_48khz = 0; + for_each_rsnd_clk(clk, adg, i) { +@@ -528,6 +533,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + * this means all clkout0/1/2/3 will be * same rate + */ + ++ of_property_read_u32(np, "#clock-cells", &count); + /* + * for clkout + */ +@@ -557,13 +563,11 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + &adg->onecell); + } + ++rsnd_adg_get_clkout_end: + adg->ckr = ckr; + adg->rbga = rbga; + adg->rbgb = rbgb; + +- if (req_rate[0] % 48000 == 0) +- adg->flags = AUDIO_OUT_48; +- + for_each_rsnd_clkout(clk, adg, i) + dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk)); + dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", +-- +2.13.3 + diff --git a/patches.renesas/0102-ASoC-rsnd-don-t-use-PDTA-bit-for-24bit-on-SSI.patch b/patches.renesas/0102-ASoC-rsnd-don-t-use-PDTA-bit-for-24bit-on-SSI.patch new file mode 100644 index 00000000000000..1467ed1f2de625 --- /dev/null +++ b/patches.renesas/0102-ASoC-rsnd-don-t-use-PDTA-bit-for-24bit-on-SSI.patch @@ -0,0 +1,206 @@ +From 86f119e18638ed97072aa2d521dbd4bcf4592b1c Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 May 2017 01:51:41 +0000 +Subject: [PATCH 102/286] ASoC: rsnd: don't use PDTA bit for 24bit on SSI + +Current SSI uses PDTA bit which indicates data that Input/Output +data are Right-Aligned. But, 24bit sound should be Left-Aligned +in this HW. Because Linux is using Right-Aligned data, and HW uses +Left-Aligned data, current 24bit data is missing lower 8bit. +To fix this issue, this patch removes PDTA bit, and shift 8bit +in necessary module + +Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 90431eb49bff6d79814cbf0c96e13597ad53095c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/cmd.c | 1 + + sound/soc/sh/rcar/core.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++ + sound/soc/sh/rcar/gen.c | 1 + + sound/soc/sh/rcar/rsnd.h | 2 ++ + sound/soc/sh/rcar/src.c | 12 ++++++++++-- + sound/soc/sh/rcar/ssi.c | 2 +- + sound/soc/sh/rcar/ssiu.c | 3 ++- + 7 files changed, 68 insertions(+), 4 deletions(-) + +diff --git a/sound/soc/sh/rcar/cmd.c b/sound/soc/sh/rcar/cmd.c +index 7d92a24b7cfa..d879c010cf03 100644 +--- a/sound/soc/sh/rcar/cmd.c ++++ b/sound/soc/sh/rcar/cmd.c +@@ -89,6 +89,7 @@ static int rsnd_cmd_init(struct rsnd_mod *mod, + dev_dbg(dev, "ctu/mix path = 0x%08x", data); + + rsnd_mod_write(mod, CMD_ROUTE_SLCT, data); ++ rsnd_mod_write(mod, CMD_BUSIF_MODE, rsnd_get_busif_shift(io, mod) | 1); + rsnd_mod_write(mod, CMD_BUSIF_DALIGN, rsnd_get_dalign(mod, io)); + + rsnd_adg_set_cmd_timsel_gen2(mod, io); +diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c +index 1744015408c3..8c1f4e2e0c4f 100644 +--- a/sound/soc/sh/rcar/core.c ++++ b/sound/soc/sh/rcar/core.c +@@ -343,6 +343,57 @@ u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io) + return 0x76543210; + } + ++u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod) ++{ ++ enum rsnd_mod_type playback_mods[] = { ++ RSND_MOD_SRC, ++ RSND_MOD_CMD, ++ RSND_MOD_SSIU, ++ }; ++ enum rsnd_mod_type capture_mods[] = { ++ RSND_MOD_CMD, ++ RSND_MOD_SRC, ++ RSND_MOD_SSIU, ++ }; ++ struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); ++ struct rsnd_mod *tmod = NULL; ++ enum rsnd_mod_type *mods = ++ rsnd_io_is_play(io) ? ++ playback_mods : capture_mods; ++ int i; ++ ++ /* ++ * This is needed for 24bit data ++ * We need to shift 8bit ++ * ++ * Linux 24bit data is located as 0x00****** ++ * HW 24bit data is located as 0x******00 ++ * ++ */ ++ switch (runtime->sample_bits) { ++ case 16: ++ return 0; ++ case 32: ++ break; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(playback_mods); i++) { ++ tmod = rsnd_io_to_mod(io, mods[i]); ++ if (tmod) ++ break; ++ } ++ ++ if (tmod != mod) ++ return 0; ++ ++ if (rsnd_io_is_play(io)) ++ return (0 << 20) | /* shift to Left */ ++ (8 << 16); /* 8bit */ ++ else ++ return (1 << 20) | /* shift to Right */ ++ (8 << 16); /* 8bit */ ++} ++ + /* + * rsnd_dai functions + */ +diff --git a/sound/soc/sh/rcar/gen.c b/sound/soc/sh/rcar/gen.c +index 63b6d3c28021..4b0980728e13 100644 +--- a/sound/soc/sh/rcar/gen.c ++++ b/sound/soc/sh/rcar/gen.c +@@ -236,6 +236,7 @@ static int rsnd_gen2_probe(struct rsnd_priv *priv) + RSND_GEN_M_REG(SRC_ROUTE_MODE0, 0xc, 0x20), + RSND_GEN_M_REG(SRC_CTRL, 0x10, 0x20), + RSND_GEN_M_REG(SRC_INT_ENABLE0, 0x18, 0x20), ++ RSND_GEN_M_REG(CMD_BUSIF_MODE, 0x184, 0x20), + RSND_GEN_M_REG(CMD_BUSIF_DALIGN,0x188, 0x20), + RSND_GEN_M_REG(CMD_ROUTE_SLCT, 0x18c, 0x20), + RSND_GEN_M_REG(CMD_CTRL, 0x190, 0x20), +diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h +index dbf4163427e8..323af41ecfcb 100644 +--- a/sound/soc/sh/rcar/rsnd.h ++++ b/sound/soc/sh/rcar/rsnd.h +@@ -73,6 +73,7 @@ enum rsnd_reg { + RSND_REG_SCU_SYS_INT_EN0, + RSND_REG_SCU_SYS_INT_EN1, + RSND_REG_CMD_CTRL, ++ RSND_REG_CMD_BUSIF_MODE, + RSND_REG_CMD_BUSIF_DALIGN, + RSND_REG_CMD_ROUTE_SLCT, + RSND_REG_CMDOUT_TIMSEL, +@@ -204,6 +205,7 @@ void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg, + u32 mask, u32 data); + u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io); + u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io); ++u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod); + + /* + * R-Car DMA +diff --git a/sound/soc/sh/rcar/src.c b/sound/soc/sh/rcar/src.c +index 20b5b2ec625e..76a477a3ccb5 100644 +--- a/sound/soc/sh/rcar/src.c ++++ b/sound/soc/sh/rcar/src.c +@@ -190,11 +190,13 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io, + struct rsnd_priv *priv = rsnd_mod_to_priv(mod); + struct device *dev = rsnd_priv_to_dev(priv); + struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); ++ int is_play = rsnd_io_is_play(io); + int use_src = 0; + u32 fin, fout; + u32 ifscr, fsrate, adinr; + u32 cr, route; + u32 bsdsr, bsisr; ++ u32 i_busif, o_busif, tmp; + uint ratio; + + if (!runtime) +@@ -270,6 +272,11 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io, + break; + } + ++ /* BUSIF_MODE */ ++ tmp = rsnd_get_busif_shift(io, mod); ++ i_busif = ( is_play ? tmp : 0) | 1; ++ o_busif = (!is_play ? tmp : 0) | 1; ++ + rsnd_mod_write(mod, SRC_ROUTE_MODE0, route); + + rsnd_mod_write(mod, SRC_SRCIR, 1); /* initialize */ +@@ -281,8 +288,9 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io, + rsnd_mod_write(mod, SRC_BSISR, bsisr); + rsnd_mod_write(mod, SRC_SRCIR, 0); /* cancel initialize */ + +- rsnd_mod_write(mod, SRC_I_BUSIF_MODE, 1); +- rsnd_mod_write(mod, SRC_O_BUSIF_MODE, 1); ++ rsnd_mod_write(mod, SRC_I_BUSIF_MODE, i_busif); ++ rsnd_mod_write(mod, SRC_O_BUSIF_MODE, o_busif); ++ + rsnd_mod_write(mod, SRC_BUSIF_DALIGN, rsnd_get_dalign(mod, io)); + + rsnd_adg_set_src_timesel_gen2(mod, io, fin, fout); +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index 135c5669f796..e43277a5068c 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -302,7 +302,7 @@ static void rsnd_ssi_config_init(struct rsnd_mod *mod, + * always use 32bit system word. + * see also rsnd_ssi_master_clk_enable() + */ +- cr_own = FORCE | SWL_32 | PDTA; ++ cr_own = FORCE | SWL_32; + + if (rdai->bit_clk_inv) + cr_own |= SCKP; +diff --git a/sound/soc/sh/rcar/ssiu.c b/sound/soc/sh/rcar/ssiu.c +index 14fafdaf1395..512d238b79e2 100644 +--- a/sound/soc/sh/rcar/ssiu.c ++++ b/sound/soc/sh/rcar/ssiu.c +@@ -144,7 +144,8 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod, + (rsnd_io_is_play(io) ? + rsnd_runtime_channel_after_ctu(io) : + rsnd_runtime_channel_original(io))); +- rsnd_mod_write(mod, SSI_BUSIF_MODE, 1); ++ rsnd_mod_write(mod, SSI_BUSIF_MODE, ++ rsnd_get_busif_shift(io, mod) | 1); + rsnd_mod_write(mod, SSI_BUSIF_DALIGN, + rsnd_get_dalign(mod, io)); + } +-- +2.13.3 + diff --git a/patches.renesas/0103-ASoC-rsnd-don-t-call-free_irq-on-Parent-SSI.patch b/patches.renesas/0103-ASoC-rsnd-don-t-call-free_irq-on-Parent-SSI.patch new file mode 100644 index 00000000000000..9fda8cc064ffaf --- /dev/null +++ b/patches.renesas/0103-ASoC-rsnd-don-t-call-free_irq-on-Parent-SSI.patch @@ -0,0 +1,40 @@ +From 7c80502b95e9d1eebb2f2357cf1cae89fe6df45c Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Tue, 16 May 2017 01:48:24 +0000 +Subject: [PATCH 103/286] ASoC: rsnd: don't call free_irq() on Parent SSI + +If SSI uses shared pin, some SSI will be used as parent SSI. +Then, normal SSI's remove and Parent SSI's remove +(these are same SSI) will be called when unbind or remove timing. +In this case, free_irq() will be called twice. +This patch solve this issue. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 1f8754d4daea5f257370a52a30fcb22798c54516) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ssi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index e43277a5068c..c224695c1484 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -709,6 +709,11 @@ static int rsnd_ssi_dma_remove(struct rsnd_mod *mod, + struct rsnd_priv *priv) + { + struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod); ++ struct rsnd_mod *ssi_parent_mod = rsnd_io_to_mod_ssip(io); ++ ++ /* Do nothing for SSI parent mod */ ++ if (ssi_parent_mod == mod) ++ return 0; + + /* PIO will request IRQ again */ + free_irq(ssi->irq, mod); +-- +2.13.3 + diff --git a/patches.renesas/0104-ASoC-rsnd-SSI-PIO-adjust-to-24bit-mode.patch b/patches.renesas/0104-ASoC-rsnd-SSI-PIO-adjust-to-24bit-mode.patch new file mode 100644 index 00000000000000..e12d561a11016a --- /dev/null +++ b/patches.renesas/0104-ASoC-rsnd-SSI-PIO-adjust-to-24bit-mode.patch @@ -0,0 +1,50 @@ +From 4432f39584367123bd0643e0f09d13f0c6653d01 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 24 May 2017 01:17:10 +0000 +Subject: [PATCH 104/286] ASoC: rsnd: SSI PIO adjust to 24bit mode + +commit 90431eb49bff ("ASoC: rsnd: don't use PDTA bit for 24bit on SSI") +fixups 24bit mode data alignment, but PIO was not cared. +This patch fixes PIO mode 24bit data alignment + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 7819a942de7b993771bd9377babc80485fe7606b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/ssi.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c +index c224695c1484..91e5c07911b4 100644 +--- a/sound/soc/sh/rcar/ssi.c ++++ b/sound/soc/sh/rcar/ssi.c +@@ -550,6 +550,13 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod, + struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); + u32 *buf = (u32 *)(runtime->dma_area + + rsnd_dai_pointer_offset(io, 0)); ++ int shift = 0; ++ ++ switch (runtime->sample_bits) { ++ case 32: ++ shift = 8; ++ break; ++ } + + /* + * 8/16/32 data can be assesse to TDR/RDR register +@@ -557,9 +564,9 @@ static void __rsnd_ssi_interrupt(struct rsnd_mod *mod, + * see rsnd_ssi_init() + */ + if (rsnd_io_is_play(io)) +- rsnd_mod_write(mod, SSITDR, *buf); ++ rsnd_mod_write(mod, SSITDR, (*buf) << shift); + else +- *buf = rsnd_mod_read(mod, SSIRDR); ++ *buf = (rsnd_mod_read(mod, SSIRDR) >> shift); + + elapsed = rsnd_dai_pointer_update(io, sizeof(*buf)); + } +-- +2.13.3 + diff --git a/patches.renesas/0105-ASoC-rsnd-fixup-parent_clk_name-of-AUDIO_CLKOUTx.patch b/patches.renesas/0105-ASoC-rsnd-fixup-parent_clk_name-of-AUDIO_CLKOUTx.patch new file mode 100644 index 00000000000000..f3dcada1bb4b6f --- /dev/null +++ b/patches.renesas/0105-ASoC-rsnd-fixup-parent_clk_name-of-AUDIO_CLKOUTx.patch @@ -0,0 +1,45 @@ +From b12b392f643bed70c859a953ca4ff8c5c3a8bf42 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Fri, 26 May 2017 01:44:19 +0000 +Subject: [PATCH 105/286] ASoC: rsnd: fixup parent_clk_name of AUDIO_CLKOUTx + +commit 25165f79adc7 ("ASoC: rsnd: enable clock-frequency for both +44.1kHz/48kHz") supported both 44.1kHz/48kHz for AUDIO_CLKOUTx, +but it didn't care its parent clock name. +This patch fixes it. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit e8a3ce1130134046e9da132aa4d043566df8237d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/sh/rcar/adg.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c +index 66203d107a11..d3b0dc145a56 100644 +--- a/sound/soc/sh/rcar/adg.c ++++ b/sound/soc/sh/rcar/adg.c +@@ -507,7 +507,8 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + rbga = rbgx; + adg->rbga_rate_for_441khz = rate / div; + ckr |= brg_table[i] << 20; +- if (req_441kHz_rate) ++ if (req_441kHz_rate && ++ !(adg_mode_flags(adg) & AUDIO_OUT_48)) + parent_clk_name = __clk_get_name(clk); + } + } +@@ -522,7 +523,8 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv, + rbgb = rbgx; + adg->rbgb_rate_for_48khz = rate / div; + ckr |= brg_table[i] << 16; +- if (req_48kHz_rate) ++ if (req_48kHz_rate && ++ (adg_mode_flags(adg) & AUDIO_OUT_48)) + parent_clk_name = __clk_get_name(clk); + } + } +-- +2.13.3 + diff --git a/patches.renesas/0106-soc-renesas-Identify-RZ-G1H.patch b/patches.renesas/0106-soc-renesas-Identify-RZ-G1H.patch new file mode 100644 index 00000000000000..8564c900d7ba5d --- /dev/null +++ b/patches.renesas/0106-soc-renesas-Identify-RZ-G1H.patch @@ -0,0 +1,44 @@ +From bf263b778b4c2a544c6fdfc5ea3d68b94b2a3af6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:48:29 +0100 +Subject: [PATCH 106/286] soc: renesas: Identify RZ/G1H + +Add support for identifying the RZ/G1H (r8a7742) SoC. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 8848e1b14231a40ed66229fb3ee98519b32f2ae7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/soc/renesas/renesas-soc.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c +index 330960312296..f0172e59c040 100644 +--- a/drivers/soc/renesas/renesas-soc.c ++++ b/drivers/soc/renesas/renesas-soc.c +@@ -80,6 +80,11 @@ static const struct renesas_soc soc_rmobile_a1 __initconst __maybe_unused = { + .id = 0x40, + }; + ++static const struct renesas_soc soc_rz_g1h __initconst __maybe_unused = { ++ .family = &fam_rzg, ++ .id = 0x45, ++}; ++ + static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = { + .family = &fam_rzg, + .id = 0x47, +@@ -150,6 +155,9 @@ static const struct of_device_id renesas_socs[] __initconst = { + #ifdef CONFIG_ARCH_R8A7740 + { .compatible = "renesas,r8a7740", .data = &soc_rmobile_a1 }, + #endif ++#ifdef CONFIG_ARCH_R8A7742 ++ { .compatible = "renesas,r8a7742", .data = &soc_rz_g1h }, ++#endif + #ifdef CONFIG_ARCH_R8A7743 + { .compatible = "renesas,r8a7743", .data = &soc_rz_g1m }, + #endif +-- +2.13.3 + diff --git a/patches.renesas/0107-soc-renesas-Identify-RZ-G1N.patch b/patches.renesas/0107-soc-renesas-Identify-RZ-G1N.patch new file mode 100644 index 00000000000000..894cefc9f701e9 --- /dev/null +++ b/patches.renesas/0107-soc-renesas-Identify-RZ-G1N.patch @@ -0,0 +1,44 @@ +From 1b8a2f707ba20da6c91df51a973b509e05c4e257 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 14:48:30 +0100 +Subject: [PATCH 107/286] soc: renesas: Identify RZ/G1N + +Add support for identifying the RZ/G1N (r8a7744) SoC. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit cd59de80dd34dd2d1a3ca97d7a6e712c048b135a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/soc/renesas/renesas-soc.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c +index f0172e59c040..b894cf64225b 100644 +--- a/drivers/soc/renesas/renesas-soc.c ++++ b/drivers/soc/renesas/renesas-soc.c +@@ -90,6 +90,11 @@ static const struct renesas_soc soc_rz_g1m __initconst __maybe_unused = { + .id = 0x47, + }; + ++static const struct renesas_soc soc_rz_g1n __initconst __maybe_unused = { ++ .family = &fam_rzg, ++ .id = 0x4b, ++}; ++ + static const struct renesas_soc soc_rz_g1e __initconst __maybe_unused = { + .family = &fam_rzg, + .id = 0x4c, +@@ -161,6 +166,9 @@ static const struct of_device_id renesas_socs[] __initconst = { + #ifdef CONFIG_ARCH_R8A7743 + { .compatible = "renesas,r8a7743", .data = &soc_rz_g1m }, + #endif ++#ifdef CONFIG_ARCH_R8A7744 ++ { .compatible = "renesas,r8a7744", .data = &soc_rz_g1n }, ++#endif + #ifdef CONFIG_ARCH_R8A7745 + { .compatible = "renesas,r8a7745", .data = &soc_rz_g1e }, + #endif +-- +2.13.3 + diff --git a/patches.renesas/0108-soc-renesas-Register-SoC-device-early.patch b/patches.renesas/0108-soc-renesas-Register-SoC-device-early.patch new file mode 100644 index 00000000000000..2a8c3d4ecb6772 --- /dev/null +++ b/patches.renesas/0108-soc-renesas-Register-SoC-device-early.patch @@ -0,0 +1,33 @@ +From 5ff959f7308aec42e22f94ddd60c4015639d8863 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 31 Mar 2017 11:01:54 +0200 +Subject: [PATCH 108/286] soc: renesas: Register SoC device early + +The r8a7795 SYSC driver manages PM Domains, and thus is initialized from +an early_initcall(). However, this means the driver cannot check the +SoC revision, as the SoC device hasn't been registered yet. + +Change renesas_soc_init() from a core_initcall() to an early_initcall() +to fix this (renesas-soc.o is listed before rcar-sysc.o in the Makefile). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit b1d134ba9de2b7a136406530e34fc8b110ba6efd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/soc/renesas/renesas-soc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c +index b894cf64225b..ca26f13d399c 100644 +--- a/drivers/soc/renesas/renesas-soc.c ++++ b/drivers/soc/renesas/renesas-soc.c +@@ -270,4 +270,4 @@ static int __init renesas_soc_init(void) + + return 0; + } +-core_initcall(renesas_soc_init); ++early_initcall(renesas_soc_init); +-- +2.13.3 + diff --git a/patches.renesas/0109-ata-sata_rcar-Handle-return-value-of-clk_prepare_ena.patch b/patches.renesas/0109-ata-sata_rcar-Handle-return-value-of-clk_prepare_ena.patch new file mode 100644 index 00000000000000..ec80bccd35d305 --- /dev/null +++ b/patches.renesas/0109-ata-sata_rcar-Handle-return-value-of-clk_prepare_ena.patch @@ -0,0 +1,64 @@ +From 37ca7df9881ca9ef9440fede4b128272fb4dbbcc Mon Sep 17 00:00:00 2001 +From: Arvind Yadav <arvind.yadav.cs@gmail.com> +Date: Tue, 9 May 2017 16:00:28 +0530 +Subject: [PATCH 109/286] ata: sata_rcar: Handle return value of + clk_prepare_enable + +Here, Clock enable can failed. So adding an error check for +clk_prepare_enable. + +tj: minor style updates + +Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> +Signed-off-by: Tejun Heo <tj@kernel.org> +(cherry picked from commit 5dc63fdcc09f47fb226b8bc7d83a61feb787d817) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/ata/sata_rcar.c | 15 ++++++++++++--- + 1 file changed, 12 insertions(+), 3 deletions(-) + +diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c +index 5d38245a7a73..b7939a2c1fab 100644 +--- a/drivers/ata/sata_rcar.c ++++ b/drivers/ata/sata_rcar.c +@@ -890,7 +890,10 @@ static int sata_rcar_probe(struct platform_device *pdev) + dev_err(&pdev->dev, "failed to get access to sata clock\n"); + return PTR_ERR(priv->clk); + } +- clk_prepare_enable(priv->clk); ++ ++ ret = clk_prepare_enable(priv->clk); ++ if (ret) ++ return ret; + + host = ata_host_alloc(&pdev->dev, 1); + if (!host) { +@@ -970,8 +973,11 @@ static int sata_rcar_resume(struct device *dev) + struct ata_host *host = dev_get_drvdata(dev); + struct sata_rcar_priv *priv = host->private_data; + void __iomem *base = priv->base; ++ int ret; + +- clk_prepare_enable(priv->clk); ++ ret = clk_prepare_enable(priv->clk); ++ if (ret) ++ return ret; + + /* ack and mask */ + iowrite32(0, base + SATAINTSTAT_REG); +@@ -988,8 +994,11 @@ static int sata_rcar_restore(struct device *dev) + { + struct ata_host *host = dev_get_drvdata(dev); + struct sata_rcar_priv *priv = host->private_data; ++ int ret; + +- clk_prepare_enable(priv->clk); ++ ret = clk_prepare_enable(priv->clk); ++ if (ret) ++ return ret; + + sata_rcar_setup_port(host); + +-- +2.13.3 + diff --git a/patches.renesas/0110-clocksource-sh_cmt-Compute-rate-before-registration-.patch b/patches.renesas/0110-clocksource-sh_cmt-Compute-rate-before-registration-.patch new file mode 100644 index 00000000000000..ff593c0655d834 --- /dev/null +++ b/patches.renesas/0110-clocksource-sh_cmt-Compute-rate-before-registration-.patch @@ -0,0 +1,188 @@ +From ab67f3126a94453061629edcb5ccb8bcc53ac499 Mon Sep 17 00:00:00 2001 +From: Nicolai Stange <nicstange@gmail.com> +Date: Mon, 6 Feb 2017 22:11:59 +0100 +Subject: [PATCH 110/286] clocksource: sh_cmt: Compute rate before registration + again + +With the upcoming NTP correction related rate adjustments to be implemented +in the clockevents core, the latter needs to get informed about every rate +change of a clockevent device made after its registration. + +Currently, sh_cmt violates this requirement in that it registers its +clockevent device with a dummy rate and sets its final ->mult and ->shift +values from its ->set_state_oneshot() and ->set_state_periodic() functions +respectively. + +This patch moves the setting of the clockevent device's ->mult and ->shift +values to before its registration. + +Note that there has been some back and forth regarding this question with +respect to the clocksource also provided by this driver: + commit f4d7c3565c16 ("clocksource: sh_cmt: compute mult and shift before + registration") +moves the rate determination from the clocksource's ->enable() function to +before its registration. OTOH, the later + commit 3593f5fe40a1 ("clocksource: sh_cmt: __clocksource_updatefreq_hz() + update") +basically reverts this, saying + "Without this patch the old code uses clocksource_register() together + with a hack that assumes a never changing clock rate." + +However, I checked all current sh_cmt users in arch/sh as well as in +arch/arm/mach-shmobile carefully and right now, none of them changes any +rate in any clock tree relevant to sh_cmt after their respective +time_init(). Since all sh_cmt instances are created after time_init(), none +of them should ever observe any clock rate changes. + +What's more, both, a clocksource as well as a clockevent device, can +immediately get selected for use at their registration and thus, enabled +at this point already. So it's probably safer to assume a "never changing +clock rate" here. + +- Move the struct sh_cmt_channel's ->rate member to struct sh_cmt_device: + it's a property of the underlying clock which is in turn specific to + the sh_cmt_device. +- Determine the ->rate value in sh_cmt_setup() at device probing rather + than at first usage. +- Set the clockevent device's ->mult and ->shift values right before its + registration. +- Although not strictly necessary for the upcoming clockevent core changes, + set the clocksource's rate at its registration for consistency. + +Signed-off-by: Nicolai Stange <nicstange@gmail.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +(cherry picked from commit 890f423b266623e1cfb3a97b864f3e5039bdfbb9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_cmt.c | 45 ++++++++++++++++++++++++-------------------- + 1 file changed, 25 insertions(+), 20 deletions(-) + +diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c +index 103c49362c68..3038885d4180 100644 +--- a/drivers/clocksource/sh_cmt.c ++++ b/drivers/clocksource/sh_cmt.c +@@ -103,7 +103,6 @@ struct sh_cmt_channel { + unsigned long match_value; + unsigned long next_match_value; + unsigned long max_match_value; +- unsigned long rate; + raw_spinlock_t lock; + struct clock_event_device ced; + struct clocksource cs; +@@ -118,6 +117,7 @@ struct sh_cmt_device { + + void __iomem *mapbase; + struct clk *clk; ++ unsigned long rate; + + raw_spinlock_t lock; /* Protect the shared start/stop register */ + +@@ -320,7 +320,7 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) + raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); + } + +-static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) ++static int sh_cmt_enable(struct sh_cmt_channel *ch) + { + int k, ret; + +@@ -340,11 +340,9 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) + + /* configure channel, periodic mode and maximum timeout */ + if (ch->cmt->info->width == 16) { +- *rate = clk_get_rate(ch->cmt->clk) / 512; + sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | + SH_CMT16_CMCSR_CKS512); + } else { +- *rate = clk_get_rate(ch->cmt->clk) / 8; + sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | + SH_CMT32_CMCSR_CMTOUT_IE | + SH_CMT32_CMCSR_CMR_IRQ | +@@ -572,7 +570,7 @@ static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) + raw_spin_lock_irqsave(&ch->lock, flags); + + if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) +- ret = sh_cmt_enable(ch, &ch->rate); ++ ret = sh_cmt_enable(ch); + + if (ret) + goto out; +@@ -640,10 +638,9 @@ static int sh_cmt_clocksource_enable(struct clocksource *cs) + ch->total_cycles = 0; + + ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); +- if (!ret) { +- __clocksource_update_freq_hz(cs, ch->rate); ++ if (!ret) + ch->cs_enabled = true; +- } ++ + return ret; + } + +@@ -697,8 +694,7 @@ static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, + dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", + ch->index); + +- /* Register with dummy 1 Hz value, gets updated in ->enable() */ +- clocksource_register_hz(cs, 1); ++ clocksource_register_hz(cs, ch->cmt->rate); + return 0; + } + +@@ -709,19 +705,10 @@ static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) + + static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) + { +- struct clock_event_device *ced = &ch->ced; +- + sh_cmt_start(ch, FLAG_CLOCKEVENT); + +- /* TODO: calculate good shift from rate and counter bit width */ +- +- ced->shift = 32; +- ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); +- ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); +- ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); +- + if (periodic) +- sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); ++ sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); + else + sh_cmt_set_next(ch, ch->max_match_value); + } +@@ -824,6 +811,12 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, + ced->suspend = sh_cmt_clock_event_suspend; + ced->resume = sh_cmt_clock_event_resume; + ++ /* TODO: calculate good shift from rate and counter bit width */ ++ ced->shift = 32; ++ ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); ++ ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); ++ ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); ++ + dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", + ch->index); + clockevents_register_device(ced); +@@ -996,6 +989,18 @@ static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) + if (ret < 0) + goto err_clk_put; + ++ /* Determine clock rate. */ ++ ret = clk_enable(cmt->clk); ++ if (ret < 0) ++ goto err_clk_unprepare; ++ ++ if (cmt->info->width == 16) ++ cmt->rate = clk_get_rate(cmt->clk) / 512; ++ else ++ cmt->rate = clk_get_rate(cmt->clk) / 8; ++ ++ clk_disable(cmt->clk); ++ + /* Map the memory resource(s). */ + ret = sh_cmt_map_memory(cmt); + if (ret < 0) +-- +2.13.3 + diff --git a/patches.renesas/0111-clockevents-drivers-sh_cmt-Set-min_delta_ticks-and-m.patch b/patches.renesas/0111-clockevents-drivers-sh_cmt-Set-min_delta_ticks-and-m.patch new file mode 100644 index 00000000000000..b4c133ea3a4f3a --- /dev/null +++ b/patches.renesas/0111-clockevents-drivers-sh_cmt-Set-min_delta_ticks-and-m.patch @@ -0,0 +1,52 @@ +From 51b1edb2e3af7fc16e3c6d1e91eba33e0e79d4fe Mon Sep 17 00:00:00 2001 +From: Nicolai Stange <nicstange@gmail.com> +Date: Thu, 30 Mar 2017 22:09:12 +0200 +Subject: [PATCH 111/286] clockevents/drivers/sh_cmt: Set ->min_delta_ticks and + ->max_delta_ticks + +In preparation for making the clockevents core NTP correction aware, +all clockevent device drivers must set ->min_delta_ticks and +->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a +clockevent device's rate is going to change dynamically and thus, the +ratio of ns to ticks ceases to stay invariant. + +Make the sh_cmt clockevent driver initialize these fields properly. + +This patch alone doesn't introduce any change in functionality as the +clockevents core still looks exclusively at the (untouched) ->min_delta_ns +and ->max_delta_ns. As soon as this has changed, a followup patch will +purge the initialization of ->min_delta_ns and ->max_delta_ns from this +driver. + +Cc: Ingo Molnar <mingo@redhat.com> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Daniel Lezcano <daniel.lezcano@linaro.org> +Cc: Richard Cochran <richardcochran@gmail.com> +Cc: Prarit Bhargava <prarit@redhat.com> +Cc: Stephen Boyd <sboyd@codeaurora.org> +Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> +Signed-off-by: Nicolai Stange <nicstange@gmail.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +(cherry picked from commit bb2e94ac0cf4628f5e5f778c8de4a376dac43558) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_cmt.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c +index 3038885d4180..97ce6bf27f7c 100644 +--- a/drivers/clocksource/sh_cmt.c ++++ b/drivers/clocksource/sh_cmt.c +@@ -815,7 +815,9 @@ static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, + ced->shift = 32; + ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); + ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); ++ ced->max_delta_ticks = ch->max_match_value; + ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); ++ ced->min_delta_ticks = 0x1f; + + dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", + ch->index); +-- +2.13.3 + diff --git a/patches.renesas/0112-sh_eth-Use-platform-device-for-printing-before-regis.patch b/patches.renesas/0112-sh_eth-Use-platform-device-for-printing-before-regis.patch new file mode 100644 index 00000000000000..39bff78d0e9262 --- /dev/null +++ b/patches.renesas/0112-sh_eth-Use-platform-device-for-printing-before-regis.patch @@ -0,0 +1,41 @@ +From 8b4fd81780bf8efb3940864f1cdb1b10313ba293 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 18 May 2017 15:01:34 +0200 +Subject: [PATCH 112/286] sh_eth: Use platform device for printing before + register_netdev() + +The MDIO initialization failure message is printed using the network +device, before it has been registered, leading to: + + (null): failed to initialise MDIO + +Use the platform device instead to fix this: + + sh-eth ee700000.ethernet: failed to initialise MDIO + +Fixes: daacf03f0bbfefee ("sh_eth: Register MDIO bus before registering the network device") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 5f5c5449acad0cd3322e53e1ac68c044483b0aa5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index b1e9f3f412e0..07e8fce2b9a4 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -3222,7 +3222,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + /* MDIO bus init */ + ret = sh_mdio_init(mdp, pd); + if (ret) { +- dev_err(&ndev->dev, "failed to initialise MDIO\n"); ++ dev_err(&pdev->dev, "failed to initialise MDIO\n"); + goto out_release; + } + +-- +2.13.3 + diff --git a/patches.renesas/0113-sh_eth-Do-not-print-an-error-message-for-probe-defer.patch b/patches.renesas/0113-sh_eth-Do-not-print-an-error-message-for-probe-defer.patch new file mode 100644 index 00000000000000..8849ef769b1214 --- /dev/null +++ b/patches.renesas/0113-sh_eth-Do-not-print-an-error-message-for-probe-defer.patch @@ -0,0 +1,41 @@ +From d83a040b8a8b34e8fa6f7858533a5964e92f4b87 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 18 May 2017 15:01:35 +0200 +Subject: [PATCH 113/286] sh_eth: Do not print an error message for probe + deferral + +EPROBE_DEFER is not an error, hence printing an error message like + + sh-eth ee700000.ethernet: failed to initialise MDIO + +may confuse the user. + +To fix this, suppress the error message in case of probe deferral. +While at it, shorten the message, and add the actual error code. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit b7ce520e9f71ff65d0aa0ad86223f94ae4095fae) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/renesas/sh_eth.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c +index 07e8fce2b9a4..30ce538e92dd 100644 +--- a/drivers/net/ethernet/renesas/sh_eth.c ++++ b/drivers/net/ethernet/renesas/sh_eth.c +@@ -3222,7 +3222,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev) + /* MDIO bus init */ + ret = sh_mdio_init(mdp, pd); + if (ret) { +- dev_err(&pdev->dev, "failed to initialise MDIO\n"); ++ if (ret != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); + goto out_release; + } + +-- +2.13.3 + diff --git a/patches.renesas/0114-mmc-sh_mmcif-Document-r7s72100-DT-bindings.patch b/patches.renesas/0114-mmc-sh_mmcif-Document-r7s72100-DT-bindings.patch new file mode 100644 index 00000000000000..9393a7e2d6f67c --- /dev/null +++ b/patches.renesas/0114-mmc-sh_mmcif-Document-r7s72100-DT-bindings.patch @@ -0,0 +1,45 @@ +From b38149f99928f4601691501cb88dd0df1aca39ae Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 22 Mar 2017 10:42:09 -0400 +Subject: [PATCH 114/286] mmc: sh_mmcif: Document r7s72100 DT bindings + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 474e25e15f508889d4f8c672ab54323743ee595b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/mmc/renesas,mmcif.txt | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +index e4ba92aa035e..c32dc5a9dbe6 100644 +--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt ++++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt +@@ -8,6 +8,7 @@ Required properties: + + - compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a + fallback. Examples with <soctype> are: ++ - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs + - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs + - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs + - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs +@@ -17,6 +18,13 @@ Required properties: + - "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs + - "renesas,mmcif-sh73a0" for the MMCIF found in sh73a0 SoCs + ++- interrupts: Some SoCs have only 1 shared interrupt, while others have either ++ 2 or 3 individual interrupts (error, int, card detect). Below is the number ++ of interrupts for each SoC: ++ 1: r8a73a4, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794 ++ 2: r8a7740, sh73a0 ++ 3: r7s72100 ++ + - clocks: reference to the functional clock + + - dmas: reference to the DMA channels, one per channel name listed in the +-- +2.13.3 + diff --git a/patches.renesas/0115-media-sh_mobile_ceu_camera-use-module_platform_drive.patch b/patches.renesas/0115-media-sh_mobile_ceu_camera-use-module_platform_drive.patch new file mode 100644 index 00000000000000..3f22c327cea14c --- /dev/null +++ b/patches.renesas/0115-media-sh_mobile_ceu_camera-use-module_platform_drive.patch @@ -0,0 +1,44 @@ +From e5604c25c48d06089ad2ccaf1f870317320cf06e Mon Sep 17 00:00:00 2001 +From: Geliang Tang <geliangtang@gmail.com> +Date: Tue, 15 Nov 2016 10:58:35 -0200 +Subject: [PATCH 115/286] [media] sh_mobile_ceu_camera: use + module_platform_driver + +Use module_platform_driver() helper to simplify the code. + +Signed-off-by: Geliang Tang <geliangtang@gmail.com> +Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 855749a75609122b57b2d4ebd872944836388a14) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c | 13 +------------ + 1 file changed, 1 insertion(+), 12 deletions(-) + +diff --git a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +index a15bfb5aea47..96dc01750bc0 100644 +--- a/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c ++++ b/drivers/media/platform/soc_camera/sh_mobile_ceu_camera.c +@@ -1801,18 +1801,7 @@ static struct platform_driver sh_mobile_ceu_driver = { + .remove = sh_mobile_ceu_remove, + }; + +-static int __init sh_mobile_ceu_init(void) +-{ +- return platform_driver_register(&sh_mobile_ceu_driver); +-} +- +-static void __exit sh_mobile_ceu_exit(void) +-{ +- platform_driver_unregister(&sh_mobile_ceu_driver); +-} +- +-module_init(sh_mobile_ceu_init); +-module_exit(sh_mobile_ceu_exit); ++module_platform_driver(sh_mobile_ceu_driver); + + MODULE_DESCRIPTION("SuperH Mobile CEU driver"); + MODULE_AUTHOR("Magnus Damm"); +-- +2.13.3 + diff --git a/patches.renesas/0116-mmc-tmio-ensure-end-of-DMA-and-SD-access-are-in-sync.patch b/patches.renesas/0116-mmc-tmio-ensure-end-of-DMA-and-SD-access-are-in-sync.patch new file mode 100644 index 00000000000000..94a8071f2d1836 --- /dev/null +++ b/patches.renesas/0116-mmc-tmio-ensure-end-of-DMA-and-SD-access-are-in-sync.patch @@ -0,0 +1,164 @@ +From 0ea0d11e069936d066faeb6e1d561dc1fb961312 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Fri, 17 Feb 2017 19:22:41 +0100 +Subject: [PATCH 116/286] mmc: tmio: ensure end of DMA and SD access are in + sync + +The current code assumes that DMA is finished before SD access end is +flagged. Thus, it schedules the 'dma_complete' tasklet in the SD card +interrupt routine when DATAEND is set. The assumption is not safe, +though. Even by mounting an SD card, it can be seen that sometimes DMA +complete is first, sometimes DATAEND. It seems they are usually close +enough timewise to not cause problems. However, a customer reported that +with CMD53 sometimes things really break apart. As a result, the BSP has +a patch which introduces flags for both events and makes sure both flags +are set before scheduling the tasklet. The customer accepted the patch, +yet it doesn't seem a proper upstream solution to me. + +This patch refactors the code to replace the tasklet with already +existing and more lightweight mechanisms. First of all, we set the +callback in a DMA descriptor to automatically get notified when DMA is +done. In the callback, we then use a completion to make sure the SD +access has already ended. Then, we proceed as before. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 52ad9a8e854ca13151f4af8140297f73d49e318a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 2 +- + drivers/mmc/host/tmio_mmc_dma.c | 58 ++++++++++++++++++++++++----------------- + drivers/mmc/host/tmio_mmc_pio.c | 4 +-- + 3 files changed, 37 insertions(+), 27 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 26eb9401b3f3..3f25984cf184 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -136,7 +136,7 @@ struct tmio_mmc_host { + bool force_pio; + struct dma_chan *chan_rx; + struct dma_chan *chan_tx; +- struct tasklet_struct dma_complete; ++ struct completion dma_dataend; + struct tasklet_struct dma_issue; + struct scatterlist bounce_sg; + u8 *bounce_buf; +diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c +index fa8a936a3d9b..c7684fa91f1f 100644 +--- a/drivers/mmc/host/tmio_mmc_dma.c ++++ b/drivers/mmc/host/tmio_mmc_dma.c +@@ -43,6 +43,31 @@ void tmio_mmc_abort_dma(struct tmio_mmc_host *host) + tmio_mmc_enable_dma(host, true); + } + ++static void tmio_mmc_dma_callback(void *arg) ++{ ++ struct tmio_mmc_host *host = arg; ++ ++ wait_for_completion(&host->dma_dataend); ++ ++ spin_lock_irq(&host->lock); ++ ++ if (!host->data) ++ goto out; ++ ++ if (host->data->flags & MMC_DATA_READ) ++ dma_unmap_sg(host->chan_rx->device->dev, ++ host->sg_ptr, host->sg_len, ++ DMA_FROM_DEVICE); ++ else ++ dma_unmap_sg(host->chan_tx->device->dev, ++ host->sg_ptr, host->sg_len, ++ DMA_TO_DEVICE); ++ ++ tmio_mmc_do_data_irq(host); ++out: ++ spin_unlock_irq(&host->lock); ++} ++ + static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host) + { + struct scatterlist *sg = host->sg_ptr, *sg_tmp; +@@ -88,6 +113,10 @@ static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host) + DMA_DEV_TO_MEM, DMA_CTRL_ACK); + + if (desc) { ++ reinit_completion(&host->dma_dataend); ++ desc->callback = tmio_mmc_dma_callback; ++ desc->callback_param = host; ++ + cookie = dmaengine_submit(desc); + if (cookie < 0) { + desc = NULL; +@@ -162,6 +191,10 @@ static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host) + DMA_MEM_TO_DEV, DMA_CTRL_ACK); + + if (desc) { ++ reinit_completion(&host->dma_dataend); ++ desc->callback = tmio_mmc_dma_callback; ++ desc->callback_param = host; ++ + cookie = dmaengine_submit(desc); + if (cookie < 0) { + desc = NULL; +@@ -221,29 +254,6 @@ static void tmio_mmc_issue_tasklet_fn(unsigned long priv) + dma_async_issue_pending(chan); + } + +-static void tmio_mmc_tasklet_fn(unsigned long arg) +-{ +- struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; +- +- spin_lock_irq(&host->lock); +- +- if (!host->data) +- goto out; +- +- if (host->data->flags & MMC_DATA_READ) +- dma_unmap_sg(host->chan_rx->device->dev, +- host->sg_ptr, host->sg_len, +- DMA_FROM_DEVICE); +- else +- dma_unmap_sg(host->chan_tx->device->dev, +- host->sg_ptr, host->sg_len, +- DMA_TO_DEVICE); +- +- tmio_mmc_do_data_irq(host); +-out: +- spin_unlock_irq(&host->lock); +-} +- + void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata) + { + /* We can only either use DMA for both Tx and Rx or not use it at all */ +@@ -306,7 +316,7 @@ void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdat + if (!host->bounce_buf) + goto ebouncebuf; + +- tasklet_init(&host->dma_complete, tmio_mmc_tasklet_fn, (unsigned long)host); ++ init_completion(&host->dma_dataend); + tasklet_init(&host->dma_issue, tmio_mmc_issue_tasklet_fn, (unsigned long)host); + } + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 6b789a739d4d..c41f2252945e 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -596,11 +596,11 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat) + + if (done) { + tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); +- tasklet_schedule(&host->dma_complete); ++ complete(&host->dma_dataend); + } + } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) { + tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); +- tasklet_schedule(&host->dma_complete); ++ complete(&host->dma_dataend); + } else { + tmio_mmc_do_data_irq(host); + tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP); +-- +2.13.3 + diff --git a/patches.renesas/0117-mmc-host-tmio-use-defines-for-CTL_STOP_INTERNAL_ACTI.patch b/patches.renesas/0117-mmc-host-tmio-use-defines-for-CTL_STOP_INTERNAL_ACTI.patch new file mode 100644 index 00000000000000..930a949b25e477 --- /dev/null +++ b/patches.renesas/0117-mmc-host-tmio-use-defines-for-CTL_STOP_INTERNAL_ACTI.patch @@ -0,0 +1,65 @@ +From 9c30ff8daad8d73f4a02636fb1915e16a42f1346 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 14 Mar 2017 11:09:16 +0100 +Subject: [PATCH 117/286] mmc: host: tmio: use defines for + CTL_STOP_INTERNAL_ACTION values + +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 9afcbf4a6f1995f3b47088764eaef7b56154beb9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 4 ++++ + drivers/mmc/host/tmio_mmc_pio.c | 6 +++--- + 2 files changed, 7 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index 3f25984cf184..eb913c8c4e6e 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -49,6 +49,10 @@ + #define CTL_CLK_AND_WAIT_CTL 0x138 + #define CTL_RESET_SDIO 0x1e0 + ++/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ ++#define TMIO_STOP_STP BIT(0) ++#define TMIO_STOP_SEC BIT(8) ++ + /* Definitions for values the CTRL_STATUS register can take. */ + #define TMIO_STAT_CMDRESPEND BIT(0) + #define TMIO_STAT_DATAEND BIT(2) +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index c41f2252945e..c655c9de1dde 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -340,7 +340,7 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command + + /* CMD12 is handled by hardware */ + if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) { +- sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001); ++ sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, TMIO_STOP_STP); + return 0; + } + +@@ -367,7 +367,7 @@ static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command + if (data) { + c |= DATA_PRESENT; + if (data->blocks > 1) { +- sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100); ++ sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, TMIO_STOP_SEC); + c |= TRANSFER_MULTI; + + /* +@@ -554,7 +554,7 @@ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) + + if (stop) { + if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg) +- sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000); ++ sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0); + else + BUG(); + } +-- +2.13.3 + diff --git a/patches.renesas/0118-mmc-host-tmio-fix-minor-typos-in-comments.patch b/patches.renesas/0118-mmc-host-tmio-fix-minor-typos-in-comments.patch new file mode 100644 index 00000000000000..d69e6c179770d9 --- /dev/null +++ b/patches.renesas/0118-mmc-host-tmio-fix-minor-typos-in-comments.patch @@ -0,0 +1,50 @@ +From 97a33e2c1f9472f18c1fe963065900eb4cb74564 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 14 Mar 2017 11:09:17 +0100 +Subject: [PATCH 118/286] mmc: host: tmio: fix minor typos in comments + +Making sure we match the actual register names. + +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit d8acd16c84c32a65a291e8f16ba4cb3b6d182e30) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +index eb913c8c4e6e..900258350b65 100644 +--- a/drivers/mmc/host/tmio_mmc.h ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -53,7 +53,7 @@ + #define TMIO_STOP_STP BIT(0) + #define TMIO_STOP_SEC BIT(8) + +-/* Definitions for values the CTRL_STATUS register can take. */ ++/* Definitions for values the CTL_STATUS register can take */ + #define TMIO_STAT_CMDRESPEND BIT(0) + #define TMIO_STAT_DATAEND BIT(2) + #define TMIO_STAT_CARD_REMOVE BIT(3) +@@ -64,7 +64,7 @@ + #define TMIO_STAT_CARD_INSERT_A BIT(9) + #define TMIO_STAT_SIGSTATE_A BIT(10) + +-/* These belong technically to CTRL_STATUS2, but the driver merges them */ ++/* These belong technically to CTL_STATUS2, but the driver merges them */ + #define TMIO_STAT_CMD_IDX_ERR BIT(16) + #define TMIO_STAT_CRCFAIL BIT(17) + #define TMIO_STAT_STOPBIT_ERR BIT(18) +@@ -88,7 +88,7 @@ + + #define TMIO_BBS 512 /* Boot block size */ + +-/* Definitions for values the CTRL_SDIO_STATUS register can take. */ ++/* Definitions for values the CTL_SDIO_STATUS register can take */ + #define TMIO_SDIO_STAT_IOIRQ 0x0001 + #define TMIO_SDIO_STAT_EXPUB52 0x4000 + #define TMIO_SDIO_STAT_EXWT 0x8000 +-- +2.13.3 + diff --git a/patches.renesas/0119-mmc-host-tmio-don-t-BUG-on-unsupported-stop-commands.patch b/patches.renesas/0119-mmc-host-tmio-don-t-BUG-on-unsupported-stop-commands.patch new file mode 100644 index 00000000000000..70a4b48a3a6a4c --- /dev/null +++ b/patches.renesas/0119-mmc-host-tmio-don-t-BUG-on-unsupported-stop-commands.patch @@ -0,0 +1,41 @@ +From 028b6f9e2b0adc8c6f75a05fcbdd0e66345bb708 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 14 Mar 2017 11:09:18 +0100 +Subject: [PATCH 119/286] mmc: host: tmio: don't BUG on unsupported stop + commands + +Halting the kernel on an unsupported stop command seems overkill, report +the error and say what we already did (due to autocmd12) instead. + +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 022f731e03d190d0e4f52f2b1bd90fae0eadd56d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index c655c9de1dde..42a912a3de67 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -553,10 +553,11 @@ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) + } + + if (stop) { +- if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg) +- sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0); +- else +- BUG(); ++ if (stop->opcode != MMC_STOP_TRANSMISSION || stop->arg) ++ dev_err(&host->pdev->dev, "unsupported stop: CMD%u,0x%x. We did CMD12,0\n", ++ stop->opcode, stop->arg); ++ ++ sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0); + } + + schedule_work(&host->done); +-- +2.13.3 + diff --git a/patches.renesas/0120-mmc-host-tmio-fill-in-response-from-auto-cmd12.patch b/patches.renesas/0120-mmc-host-tmio-fill-in-response-from-auto-cmd12.patch new file mode 100644 index 00000000000000..f7665f10e03856 --- /dev/null +++ b/patches.renesas/0120-mmc-host-tmio-fill-in-response-from-auto-cmd12.patch @@ -0,0 +1,37 @@ +From d1863b53a1de4d7be9354ca30af40523b44b77d2 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Tue, 14 Mar 2017 11:09:19 +0100 +Subject: [PATCH 120/286] mmc: host: tmio: fill in response from auto cmd12 + +After we received the dataend interrupt, R1 response register carries +the value from the automatically generated stop command. Report that +info back to the MMC block layer, so we will be notified in case of e.g. +ECC errors which happened during the last transfer. + +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit eb7c00e1461124ad0e85f1a9a3954d7164809c13) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 42a912a3de67..5b01d22932cd 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -557,6 +557,9 @@ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) + dev_err(&host->pdev->dev, "unsupported stop: CMD%u,0x%x. We did CMD12,0\n", + stop->opcode, stop->arg); + ++ /* fill in response from auto CMD12 */ ++ stop->resp[0] = sd_ctrl_read16_and_16_as_32(host, CTL_RESPONSE); ++ + sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0); + } + +-- +2.13.3 + diff --git a/patches.renesas/0121-mmc-tmio-always-unmap-DMA-before-waiting-for-interru.patch b/patches.renesas/0121-mmc-tmio-always-unmap-DMA-before-waiting-for-interru.patch new file mode 100644 index 00000000000000..d6018d950d0e5f --- /dev/null +++ b/patches.renesas/0121-mmc-tmio-always-unmap-DMA-before-waiting-for-interru.patch @@ -0,0 +1,49 @@ +From 4c4c55ec5ccc7ef42434a777c156dc1a0dd85000 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Thu, 16 Mar 2017 11:56:02 +0100 +Subject: [PATCH 121/286] mmc: tmio: always unmap DMA before waiting for + interrupt + +In the (maybe academical) case, we don't get a DATAEND interrupt after +DMA completed, we will wait endlessly for the completion to complete. +This is not bad per se, since we have a more generic completion tracking +a timeout. In that rare case, however, the DMA buffer will not get +unmapped and we have a leak. Reorder the code, so unmapping will always +take place. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +(cherry picked from commit 5f07ef8f603ace496ca8c20eef446c5ae7a10474) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_dma.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c +index c7684fa91f1f..e2093db2b7ff 100644 +--- a/drivers/mmc/host/tmio_mmc_dma.c ++++ b/drivers/mmc/host/tmio_mmc_dma.c +@@ -47,8 +47,6 @@ static void tmio_mmc_dma_callback(void *arg) + { + struct tmio_mmc_host *host = arg; + +- wait_for_completion(&host->dma_dataend); +- + spin_lock_irq(&host->lock); + + if (!host->data) +@@ -63,6 +61,11 @@ static void tmio_mmc_dma_callback(void *arg) + host->sg_ptr, host->sg_len, + DMA_TO_DEVICE); + ++ spin_unlock_irq(&host->lock); ++ ++ wait_for_completion(&host->dma_dataend); ++ ++ spin_lock_irq(&host->lock); + tmio_mmc_do_data_irq(host); + out: + spin_unlock_irq(&host->lock); +-- +2.13.3 + diff --git a/patches.renesas/0122-mmc-tmio-always-get-number-of-taps.patch b/patches.renesas/0122-mmc-tmio-always-get-number-of-taps.patch new file mode 100644 index 00000000000000..7cf16218ca64e6 --- /dev/null +++ b/patches.renesas/0122-mmc-tmio-always-get-number-of-taps.patch @@ -0,0 +1,52 @@ +From bc21d58162e277dd0cac98d4c65e24b508cd520d Mon Sep 17 00:00:00 2001 +From: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> +Date: Fri, 17 Mar 2017 10:04:50 +0100 +Subject: [PATCH 122/286] mmc: tmio: always get number of taps + +Current code gets number of taps only once and keeps the value. This is +not correct, we need to obtain it every time before executing tuning, +so remove the outer if-block. + +Signed-off-by: Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> +[wsa: extracted from a larger patch and reworded commit message] +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Reviewed-by: Simon Horman <horms+renesas@verge.net.au> +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> + +(cherry picked from commit 43b0b361b0170030603cf76f70b099f3323edcf3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/mmc/host/tmio_mmc_pio.c | 16 +++++++--------- + 1 file changed, 7 insertions(+), 9 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c +index 5b01d22932cd..a2d92f10501b 100644 +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -815,16 +815,14 @@ static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) + struct tmio_mmc_host *host = mmc_priv(mmc); + int i, ret = 0; + +- if (!host->tap_num) { +- if (!host->init_tuning || !host->select_tuning) +- /* Tuning is not supported */ +- goto out; ++ if (!host->init_tuning || !host->select_tuning) ++ /* Tuning is not supported */ ++ goto out; + +- host->tap_num = host->init_tuning(host); +- if (!host->tap_num) +- /* Tuning is not supported */ +- goto out; +- } ++ host->tap_num = host->init_tuning(host); ++ if (!host->tap_num) ++ /* Tuning is not supported */ ++ goto out; + + if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) { + dev_warn_once(&host->pdev->dev, +-- +2.13.3 + diff --git a/patches.renesas/0123-rtc-sh-add-support-for-rza-series.patch b/patches.renesas/0123-rtc-sh-add-support-for-rza-series.patch new file mode 100644 index 00000000000000..4382f39e19acb2 --- /dev/null +++ b/patches.renesas/0123-rtc-sh-add-support-for-rza-series.patch @@ -0,0 +1,124 @@ +From 5bfac81a8cb4ffbbe4b361ad9939c9bcf2d4c688 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:29 -0700 +Subject: [PATCH 123/286] rtc: sh: add support for rza series + +This same RTC is used in RZ/A series MPUs, therefore with some slight +changes, this driver can be reused. Additionally, since ARM architectures +require Device Tree configurations, device tree support has been added. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> +(cherry picked from commit dab5aec64bf5907f65926675807e4ebe83b3b10e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/rtc/Kconfig | 4 ++-- + drivers/rtc/rtc-sh.c | 33 ++++++++++++++++++++++++++++----- + 2 files changed, 30 insertions(+), 7 deletions(-) + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index 0723c97ebea3..ca7e07043468 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1301,10 +1301,10 @@ config RTC_DRV_SA1100 + + config RTC_DRV_SH + tristate "SuperH On-Chip RTC" +- depends on SUPERH && HAVE_CLK ++ depends on SUPERH || ARCH_RENESAS + help + Say Y here to enable support for the on-chip RTC found in +- most SuperH processors. ++ most SuperH processors. This RTC is also found in RZ/A SoCs. + + To compile this driver as a module, choose M here: the + module will be called rtc-sh. +diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c +index 17b6235d67a5..9c45b5216b5f 100644 +--- a/drivers/rtc/rtc-sh.c ++++ b/drivers/rtc/rtc-sh.c +@@ -27,7 +27,15 @@ + #include <linux/log2.h> + #include <linux/clk.h> + #include <linux/slab.h> ++#ifdef CONFIG_SUPERH + #include <asm/rtc.h> ++#else ++/* Default values for RZ/A RTC */ ++#define rtc_reg_size sizeof(u16) ++#define RTC_BIT_INVERTED 0 /* no chip bugs */ ++#define RTC_CAP_4_DIGIT_YEAR (1 << 0) ++#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR ++#endif + + #define DRV_NAME "sh-rtc" + +@@ -570,6 +578,8 @@ static int __init sh_rtc_probe(struct platform_device *pdev) + rtc->alarm_irq = platform_get_irq(pdev, 2); + + res = platform_get_resource(pdev, IORESOURCE_IO, 0); ++ if (!res) ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (unlikely(res == NULL)) { + dev_err(&pdev->dev, "No IO resource\n"); + return -ENOENT; +@@ -587,12 +597,15 @@ static int __init sh_rtc_probe(struct platform_device *pdev) + if (unlikely(!rtc->regbase)) + return -EINVAL; + +- clk_id = pdev->id; +- /* With a single device, the clock id is still "rtc0" */ +- if (clk_id < 0) +- clk_id = 0; ++ if (!pdev->dev.of_node) { ++ clk_id = pdev->id; ++ /* With a single device, the clock id is still "rtc0" */ ++ if (clk_id < 0) ++ clk_id = 0; + +- snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); ++ snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); ++ } else ++ snprintf(clk_name, sizeof(clk_name), "fck"); + + rtc->clk = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(rtc->clk)) { +@@ -608,6 +621,8 @@ static int __init sh_rtc_probe(struct platform_device *pdev) + clk_enable(rtc->clk); + + rtc->capabilities = RTC_DEF_CAPABILITIES; ++ ++#ifdef CONFIG_SUPERH + if (dev_get_platdata(&pdev->dev)) { + struct sh_rtc_platform_info *pinfo = + dev_get_platdata(&pdev->dev); +@@ -618,6 +633,7 @@ static int __init sh_rtc_probe(struct platform_device *pdev) + */ + rtc->capabilities |= pinfo->capabilities; + } ++#endif + + if (rtc->carry_irq <= 0) { + /* register shared periodic/carry/alarm irq */ +@@ -738,10 +754,17 @@ static int sh_rtc_resume(struct device *dev) + + static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); + ++static const struct of_device_id sh_rtc_of_match[] = { ++ { .compatible = "renesas,sh-rtc", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, sh_rtc_of_match); ++ + static struct platform_driver sh_rtc_platform_driver = { + .driver = { + .name = DRV_NAME, + .pm = &sh_rtc_pm_ops, ++ .of_match_table = sh_rtc_of_match, + }, + .remove = __exit_p(sh_rtc_remove), + }; +-- +2.13.3 + diff --git a/patches.renesas/0124-dt-bindings-rtc-document-the-rtc-sh-bindings.patch b/patches.renesas/0124-dt-bindings-rtc-document-the-rtc-sh-bindings.patch new file mode 100644 index 00000000000000..48146ecca81a18 --- /dev/null +++ b/patches.renesas/0124-dt-bindings-rtc-document-the-rtc-sh-bindings.patch @@ -0,0 +1,55 @@ +From 68d9f0eaf76cb8ade7f976925039504881cca766 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:30 -0700 +Subject: [PATCH 124/286] dt-bindings: rtc: document the rtc-sh bindings + +Add the binding documentation for rtc-sh which is an RTC for +SuperH and RZ/A SoCs. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Acked-by: Rob Herring <robh@kernel.org> +Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> +(cherry picked from commit 04767b9fc2315c90a1e4bfdee883c0cbc122f30f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/rtc/rtc-sh.txt | 28 ++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + create mode 100644 Documentation/devicetree/bindings/rtc/rtc-sh.txt + +diff --git a/Documentation/devicetree/bindings/rtc/rtc-sh.txt b/Documentation/devicetree/bindings/rtc/rtc-sh.txt +new file mode 100644 +index 000000000000..7676c7d28874 +--- /dev/null ++++ b/Documentation/devicetree/bindings/rtc/rtc-sh.txt +@@ -0,0 +1,28 @@ ++* Real Time Clock for Renesas SH and ARM SoCs ++ ++Required properties: ++- compatible: Should be "renesas,r7s72100-rtc" and "renesas,sh-rtc" as a ++ fallback. ++- reg: physical base address and length of memory mapped region. ++- interrupts: 3 interrupts for alarm, period, and carry. ++- interrupt-names: The interrupts should be labeled as "alarm", "period", and ++ "carry". ++- clocks: The functional clock source for the RTC controller must be listed ++ first (if exists). Additionally, potential clock counting sources are to be ++ listed. ++- clock-names: The functional clock must be labeled as "fck". Other clocks ++ may be named in accordance to the SoC hardware manuals. ++ ++ ++Example: ++rtc: rtc@fcff1000 { ++ compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; ++ reg = <0xfcff1000 0x2e>; ++ interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING ++ GIC_SPI 277 IRQ_TYPE_EDGE_RISING ++ GIC_SPI 278 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "alarm", "period", "carry"; ++ clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, ++ <&rtc_x3_clk>, <&extal_clk>; ++ clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; ++}; +-- +2.13.3 + diff --git a/patches.renesas/0125-rtc-sh-mark-PM-functions-as-unused.patch b/patches.renesas/0125-rtc-sh-mark-PM-functions-as-unused.patch new file mode 100644 index 00000000000000..c537c60d03c1ab --- /dev/null +++ b/patches.renesas/0125-rtc-sh-mark-PM-functions-as-unused.patch @@ -0,0 +1,57 @@ +From 36115074d0ca9886383cf2d948a17fd685bd1806 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Wed, 19 Apr 2017 19:52:43 +0200 +Subject: [PATCH 125/286] rtc: sh: mark PM functions as unused + +The sh_rtc_set_irq_wake() function is only called from the suspend/resume handlers +that may be hidden, causing a harmless warning: + +drivers/rtc/rtc-sh.c:724:13: error: 'sh_rtc_set_irq_wake' defined but not used [-Werror=unused-function] + static void sh_rtc_set_irq_wake(struct device *dev, int enabled) + +The most reliable way to avoid the warning is to remove the existing #ifdef +and mark the two functions as __maybe_unused so the compiler can silently +drop all three when there is no reference. + +Fixes: dab5aec64bf5 ("rtc: sh: add support for rza series") +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> +(cherry picked from commit 5d05e81516cfe7606ee0cd8278fe225314dccfbe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/rtc/rtc-sh.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c +index 9c45b5216b5f..fc2c3cdedbf9 100644 +--- a/drivers/rtc/rtc-sh.c ++++ b/drivers/rtc/rtc-sh.c +@@ -734,8 +734,7 @@ static void sh_rtc_set_irq_wake(struct device *dev, int enabled) + } + } + +-#ifdef CONFIG_PM_SLEEP +-static int sh_rtc_suspend(struct device *dev) ++static int __maybe_unused sh_rtc_suspend(struct device *dev) + { + if (device_may_wakeup(dev)) + sh_rtc_set_irq_wake(dev, 1); +@@ -743,14 +742,13 @@ static int sh_rtc_suspend(struct device *dev) + return 0; + } + +-static int sh_rtc_resume(struct device *dev) ++static int __maybe_unused sh_rtc_resume(struct device *dev) + { + if (device_may_wakeup(dev)) + sh_rtc_set_irq_wake(dev, 0); + + return 0; + } +-#endif + + static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); + +-- +2.13.3 + diff --git a/patches.renesas/0126-serial-sh-sci-Fix-hang-in-sci_reset.patch b/patches.renesas/0126-serial-sh-sci-Fix-hang-in-sci_reset.patch new file mode 100644 index 00000000000000..367c3f9fa007ad --- /dev/null +++ b/patches.renesas/0126-serial-sh-sci-Fix-hang-in-sci_reset.patch @@ -0,0 +1,54 @@ +From 5300c730b0d6a6dfdbf92bc9db438f603e5d2a67 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 11:13:44 +0200 +Subject: [PATCH 126/286] serial: sh-sci: Fix hang in sci_reset() + +When the .set_termios() callback resets the UART, it first waits (busy +loops) until all characters in the transmit FIFO have been transmitted, +to prevent a port configuration change from impacting these characters. + +However, if the UART has dedicated RTS/CTS hardware flow control +enabled, these characters may have been stuck in the FIFO due to CTS not +being asserted by the remote side. + + - When a new user opens the port, .set_termios() is called while + transmission is still disabled, leading to an infinite loop: + + NMI watchdog: BUG: soft lockup - CPU#0 stuck for 22s! + + - When an active user changes port configuration without waiting for + the draining of the transmit FIFO, this may also block indefinitely, + until CTS is asserted by the remote side. + +This has been observed with SCIFA (on r8a7740/armadillo), and SCIFB and +HSCIF (on r8a7791/koelsch). + +To fix this, remove the code that waits for the draining of the transmit +FIFO. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit e37f712f760478a3bce8a68b8d85b5b0bf6642eb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index a08272553439..be09431e46f5 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2159,10 +2159,6 @@ static void sci_reset(struct uart_port *port) + unsigned int status; + struct sci_port *s = to_sci_port(port); + +- do { +- status = serial_port_in(port, SCxSR); +- } while (!(status & SCxSR_TEND(port))); +- + serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ + + reg = sci_getreg(port, SCFCR); +-- +2.13.3 + diff --git a/patches.renesas/0127-serial-sh-sci-Fix-late-enablement-of-AUTORTS.patch b/patches.renesas/0127-serial-sh-sci-Fix-late-enablement-of-AUTORTS.patch new file mode 100644 index 00000000000000..5a57c96d489b73 --- /dev/null +++ b/patches.renesas/0127-serial-sh-sci-Fix-late-enablement-of-AUTORTS.patch @@ -0,0 +1,46 @@ +From a7731cf682c4d2cac37ded614ec428dba109269d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 11:13:45 +0200 +Subject: [PATCH 127/286] serial: sh-sci: Fix late enablement of AUTORTS + +When changing hardware control flow for a UART with dedicated RTS/CTS +pins, the new AUTORTS state is not immediately reflected in the +hardware, but only when RTS is raised. However, the serial core does +not call .set_mctrl() after .set_termios(), hence AUTORTS may only +become effective when the port is closed, and reopened later. +Note that this problem does not happen when manually using stty to +change CRTSCTS, as AUTORTS will work fine on next open. + +To fix this, call .set_mctrl() from .set_termios() when dedicated +RTS/CTS pins are present, to refresh the AUTORTS or RTS state. +This is similar to what other drivers supporting AUTORTS do (e.g. +omap-serial). + +Reported-by: Baumann, Christoph (C.) <cbaumann@visteon.com> +Fixes: 33f50ffc253854cf ("serial: sh-sci: Fix support for hardware-assisted RTS/CTS") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5f76895e4c712b1b5af450cf344389b8c53ac2c2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index be09431e46f5..a8b4bea3925b 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -2372,6 +2372,10 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, + + serial_port_out(port, SCFCR, ctrl); + } ++ if (port->flags & UPF_HARD_FLOW) { ++ /* Refresh (Auto) RTS */ ++ sci_set_mctrl(port, port->mctrl); ++ } + + scr_val |= SCSCR_RE | SCSCR_TE | + (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); +-- +2.13.3 + diff --git a/patches.renesas/0128-serial-sh-sci-Fix-AUTO-RTS-in-sci_init_pins.patch b/patches.renesas/0128-serial-sh-sci-Fix-AUTO-RTS-in-sci_init_pins.patch new file mode 100644 index 00000000000000..cf0e953d995726 --- /dev/null +++ b/patches.renesas/0128-serial-sh-sci-Fix-AUTO-RTS-in-sci_init_pins.patch @@ -0,0 +1,75 @@ +From f0abb3a9917717e58b130674f099c6493c46624b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 11:13:46 +0200 +Subject: [PATCH 128/286] serial: sh-sci: Fix (AUTO)RTS in sci_init_pins() + +If a UART has dedicated RTS/CTS pins, and hardware control flow is +disabled (or AUTORTS is not yet effective), changing any serial port +configuration deasserts RTS, as .set_termios() calls sci_init_pins(). + +To fix this, consider the current (AUTO)RTS state when (re)initializing +the pins. Note that for SCIFA/SCIFB, AUTORTS needs explicit +configuration of the RTS# pin function, while (H)SCIF handles this +automatically. + +Fixes: d2b9775d795ec05f ("serial: sh-sci: Correct pin initialization on (H)SCIF") +Fixes: e9d7a45a03991349 ("serial: sh-sci: Add pin initialization for SCIFA/SCIFB") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit cfa6eb239154315e6efcdda1d929e024097f927b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/tty/serial/sh-sci.c | 25 +++++++++++++++++++------ + 1 file changed, 19 insertions(+), 6 deletions(-) + +diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c +index a8b4bea3925b..66b459e8a4ac 100644 +--- a/drivers/tty/serial/sh-sci.c ++++ b/drivers/tty/serial/sh-sci.c +@@ -683,24 +683,37 @@ static void sci_init_pins(struct uart_port *port, unsigned int cflag) + } + + if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { ++ u16 data = serial_port_in(port, SCPDR); + u16 ctrl = serial_port_in(port, SCPCR); + + /* Enable RXD and TXD pin functions */ + ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); + if (to_sci_port(port)->has_rtscts) { +- /* RTS# is output, driven 1 */ +- ctrl |= SCPCR_RTSC; +- serial_port_out(port, SCPDR, +- serial_port_in(port, SCPDR) | SCPDR_RTSD); ++ /* RTS# is output, active low, unless autorts */ ++ if (!(port->mctrl & TIOCM_RTS)) { ++ ctrl |= SCPCR_RTSC; ++ data |= SCPDR_RTSD; ++ } else if (!s->autorts) { ++ ctrl |= SCPCR_RTSC; ++ data &= ~SCPDR_RTSD; ++ } else { ++ /* Enable RTS# pin function */ ++ ctrl &= ~SCPCR_RTSC; ++ } + /* Enable CTS# pin function */ + ctrl &= ~SCPCR_CTSC; + } ++ serial_port_out(port, SCPDR, data); + serial_port_out(port, SCPCR, ctrl); + } else if (sci_getreg(port, SCSPTR)->size) { + u16 status = serial_port_in(port, SCSPTR); + +- /* RTS# is output, driven 1 */ +- status |= SCSPTR_RTSIO | SCSPTR_RTSDT; ++ /* RTS# is always output; and active low, unless autorts */ ++ status |= SCSPTR_RTSIO; ++ if (!(port->mctrl & TIOCM_RTS)) ++ status |= SCSPTR_RTSDT; ++ else if (!s->autorts) ++ status &= ~SCSPTR_RTSDT; + /* CTS# and SCK are inputs */ + status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); + serial_port_out(port, SCSPTR, status); +-- +2.13.3 + diff --git a/patches.renesas/0129-clocksource-sh_tmu-Compute-rate-before-registration-.patch b/patches.renesas/0129-clocksource-sh_tmu-Compute-rate-before-registration-.patch new file mode 100644 index 00000000000000..08bd3a40598388 --- /dev/null +++ b/patches.renesas/0129-clocksource-sh_tmu-Compute-rate-before-registration-.patch @@ -0,0 +1,151 @@ +From 82f4b40ec43c886c8c16939ca9bf9f37bfc8e6bc Mon Sep 17 00:00:00 2001 +From: Nicolai Stange <nicstange@gmail.com> +Date: Mon, 6 Feb 2017 22:12:00 +0100 +Subject: [PATCH 129/286] clocksource: sh_tmu: Compute rate before registration + again + +With the upcoming NTP correction related rate adjustments to be implemented +in the clockevents core, the latter needs to get informed about every rate +change of a clockevent device made after its registration. + +Currently, sh_tmu violates this requirement in that it registers its +clockevent device with a dummy rate and sets its final rate through +clockevents_config() called from its ->set_state_oneshot() and +->set_state_periodic() functions respectively. + +This patch moves the setting of the clockevent device's rate to its +registration. + +Note that there has been some back and forth regarding this question with +respect to the clocksource also provided by this driver: + commit 66f49121ffa4 ("clocksource: sh_tmu: compute mult and shift before + registration") +moves the rate determination from the clocksource's ->enable() function to +before its registration. OTOH, the later + commit 0aeac458d9eb ("clocksource: sh_tmu: __clocksource_updatefreq_hz() + update") +basically reverts this, saying + "Without this patch the old code uses clocksource_register() together + with a hack that assumes a never changing clock rate." + +However, I checked all current sh_tmu users in arch/sh as well as in +arch/arm/mach-shmobile carefully and right now, none of them changes any +rate in any clock tree relevant to sh_tmu after their respective +time_init(). Since all sh_tmu instances are created after time_init(), none +of them should ever observe any clock rate changes. + +What's more, both, a clocksource as well as a clockevent device, can +immediately get selected for use at their registration and thus, enabled +at this point already. So it's probably safer to assume a "never changing +clock rate" here. + +- Move the struct sh_tmu_channel's ->rate member to struct sh_tmu_device: + it's a property of the underlying clock which is in turn specific to + the sh_tmu_device. +- Determine the ->rate value in sh_tmu_setup() at device probing rather + than at first usage. +- Set the clockevent device's rate at its registration. +- Although not strictly necessary for the upcoming clockevent core changes, + set the clocksource's rate at its registration for consistency. + +Signed-off-by: Nicolai Stange <nicstange@gmail.com> +Signed-off-by: John Stultz <john.stultz@linaro.org> +(cherry picked from commit c3c0a20df9fc55e2243a31f91a943b3e8ba61289) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clocksource/sh_tmu.c | 26 +++++++++++++------------- + 1 file changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c +index 469e776ec17a..820004297dec 100644 +--- a/drivers/clocksource/sh_tmu.c ++++ b/drivers/clocksource/sh_tmu.c +@@ -46,7 +46,6 @@ struct sh_tmu_channel { + void __iomem *base; + int irq; + +- unsigned long rate; + unsigned long periodic; + struct clock_event_device ced; + struct clocksource cs; +@@ -59,6 +58,7 @@ struct sh_tmu_device { + + void __iomem *mapbase; + struct clk *clk; ++ unsigned long rate; + + enum sh_tmu_model model; + +@@ -165,7 +165,6 @@ static int __sh_tmu_enable(struct sh_tmu_channel *ch) + sh_tmu_write(ch, TCNT, 0xffffffff); + + /* configure channel to parent clock / 4, irq off */ +- ch->rate = clk_get_rate(ch->tmu->clk) / 4; + sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); + + /* enable channel */ +@@ -271,10 +270,8 @@ static int sh_tmu_clocksource_enable(struct clocksource *cs) + return 0; + + ret = sh_tmu_enable(ch); +- if (!ret) { +- __clocksource_update_freq_hz(cs, ch->rate); ++ if (!ret) + ch->cs_enabled = true; +- } + + return ret; + } +@@ -334,8 +331,7 @@ static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, + dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", + ch->index); + +- /* Register with dummy 1 Hz value, gets updated in ->enable() */ +- clocksource_register_hz(cs, 1); ++ clocksource_register_hz(cs, ch->tmu->rate); + return 0; + } + +@@ -346,14 +342,10 @@ static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) + + static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) + { +- struct clock_event_device *ced = &ch->ced; +- + sh_tmu_enable(ch); + +- clockevents_config(ced, ch->rate); +- + if (periodic) { +- ch->periodic = (ch->rate + HZ/2) / HZ; ++ ch->periodic = (ch->tmu->rate + HZ/2) / HZ; + sh_tmu_set_next(ch, ch->periodic, 1); + } + } +@@ -435,7 +427,7 @@ static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, + dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", + ch->index); + +- clockevents_config_and_register(ced, 1, 0x300, 0xffffffff); ++ clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); + + ret = request_irq(ch->irq, sh_tmu_interrupt, + IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, +@@ -561,6 +553,14 @@ static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) + if (ret < 0) + goto err_clk_put; + ++ /* Determine clock rate. */ ++ ret = clk_enable(tmu->clk); ++ if (ret < 0) ++ goto err_clk_unprepare; ++ ++ tmu->rate = clk_get_rate(tmu->clk) / 4; ++ clk_disable(tmu->clk); ++ + /* Map the memory resource. */ + ret = sh_tmu_map_memory(tmu); + if (ret < 0) { +-- +2.13.3 + diff --git a/patches.renesas/0130-ASoC-simple-scu-card-use-defined-dev-on-probe.patch b/patches.renesas/0130-ASoC-simple-scu-card-use-defined-dev-on-probe.patch new file mode 100644 index 00000000000000..f2078c679b6f9c --- /dev/null +++ b/patches.renesas/0130-ASoC-simple-scu-card-use-defined-dev-on-probe.patch @@ -0,0 +1,41 @@ +From d195cb8da0880a5fbf1963bf3bab55a739270283 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Mar 2017 04:43:40 +0000 +Subject: [PATCH 130/286] ASoC: simple-scu-card: use defined dev on probe() + +Current asoc_simple_card_probe() already has dev definition, +but some place doesn't use it. Let's fix this issue. + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 40b68dac75a1d16266d3c89244ccf7b899afac3e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/generic/simple-scu-card.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/generic/simple-scu-card.c b/sound/soc/generic/simple-scu-card.c +index 308ff4c11a8d..420b1c50b850 100644 +--- a/sound/soc/generic/simple-scu-card.c ++++ b/sound/soc/generic/simple-scu-card.c +@@ -257,7 +257,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) + struct snd_soc_dai_link *dai_link; + struct asoc_simple_dai *dai_props; + struct device *dev = &pdev->dev; +- struct device_node *np = pdev->dev.of_node; ++ struct device_node *np = dev->of_node; + int num, ret; + + /* Allocate the private data */ +@@ -292,7 +292,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) + + snd_soc_card_set_drvdata(&priv->snd_card, priv); + +- ret = devm_snd_soc_register_card(&pdev->dev, &priv->snd_card); ++ ret = devm_snd_soc_register_card(dev, &priv->snd_card); + if (ret >= 0) + return ret; + err: +-- +2.13.3 + diff --git a/patches.renesas/0131-ASoC-simple-scu-card-add-new-simple_priv_to_card-mac.patch b/patches.renesas/0131-ASoC-simple-scu-card-add-new-simple_priv_to_card-mac.patch new file mode 100644 index 00000000000000..fca3ad37144ca6 --- /dev/null +++ b/patches.renesas/0131-ASoC-simple-scu-card-add-new-simple_priv_to_card-mac.patch @@ -0,0 +1,132 @@ +From f50afccfe8e364866d0b849a542e6db5dec6b659 Mon Sep 17 00:00:00 2001 +From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Date: Wed, 15 Mar 2017 04:44:16 +0000 +Subject: [PATCH 131/286] ASoC: simple-scu-card: add new simple_priv_to_card() + macro + +Current simple card driver is directly calling priv->snd_card +everywhere, but it makes unreadable code. +Let's use simple_priv_to_card() macro for it + +Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit d27f3b4a2d81e873de4d11899e510a1a507da8e3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/generic/simple-scu-card.c | 35 ++++++++++++++++++++--------------- + 1 file changed, 20 insertions(+), 15 deletions(-) + +diff --git a/sound/soc/generic/simple-scu-card.c b/sound/soc/generic/simple-scu-card.c +index 420b1c50b850..dcbcab230d1b 100644 +--- a/sound/soc/generic/simple-scu-card.c ++++ b/sound/soc/generic/simple-scu-card.c +@@ -31,9 +31,10 @@ struct simple_card_data { + u32 convert_channels; + }; + +-#define simple_priv_to_dev(priv) ((priv)->snd_card.dev) +-#define simple_priv_to_link(priv, i) ((priv)->snd_card.dai_link + (i)) ++#define simple_priv_to_card(priv) (&(priv)->snd_card) + #define simple_priv_to_props(priv, i) ((priv)->dai_props + (i)) ++#define simple_priv_to_dev(priv) (simple_priv_to_card(priv)->dev) ++#define simple_priv_to_link(priv, i) (simple_priv_to_card(priv)->dai_link + (i)) + + #define DAI "sound-dai" + #define CELL "#sound-dai-cells" +@@ -109,6 +110,7 @@ static int asoc_simple_card_dai_link_of(struct device_node *np, + struct device *dev = simple_priv_to_dev(priv); + struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, idx); + struct asoc_simple_dai *dai_props = simple_priv_to_props(priv, idx); ++ struct snd_soc_card *card = simple_priv_to_card(priv); + int ret; + + if (is_fe) { +@@ -163,7 +165,7 @@ static int asoc_simple_card_dai_link_of(struct device_node *np, + if (ret < 0) + return ret; + +- snd_soc_of_parse_audio_prefix(&priv->snd_card, ++ snd_soc_of_parse_audio_prefix(card, + &priv->codec_conf, + dai_link->codec_of_node, + PREFIX "prefix"); +@@ -201,6 +203,7 @@ static int asoc_simple_card_parse_of(struct device_node *node, + { + struct device *dev = simple_priv_to_dev(priv); + struct device_node *np; ++ struct snd_soc_card *card = simple_priv_to_card(priv); + unsigned int daifmt = 0; + bool is_fe; + int ret, i; +@@ -208,7 +211,7 @@ static int asoc_simple_card_parse_of(struct device_node *node, + if (!node) + return -EINVAL; + +- ret = snd_soc_of_parse_audio_routing(&priv->snd_card, PREFIX "routing"); ++ ret = snd_soc_of_parse_audio_routing(card, PREFIX "routing"); + if (ret < 0) + return ret; + +@@ -239,12 +242,12 @@ static int asoc_simple_card_parse_of(struct device_node *node, + i++; + } + +- ret = asoc_simple_card_parse_card_name(&priv->snd_card, PREFIX); ++ ret = asoc_simple_card_parse_card_name(card, PREFIX); + if (ret < 0) + return ret; + + dev_dbg(dev, "New card: %s\n", +- priv->snd_card.name ? priv->snd_card.name : ""); ++ card->name ? card->name : ""); + dev_dbg(dev, "convert_rate %d\n", priv->convert_rate); + dev_dbg(dev, "convert_channels %d\n", priv->convert_channels); + +@@ -256,6 +259,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) + struct simple_card_data *priv; + struct snd_soc_dai_link *dai_link; + struct asoc_simple_dai *dai_props; ++ struct snd_soc_card *card; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int num, ret; +@@ -276,12 +280,13 @@ static int asoc_simple_card_probe(struct platform_device *pdev) + priv->dai_link = dai_link; + + /* Init snd_soc_card */ +- priv->snd_card.owner = THIS_MODULE; +- priv->snd_card.dev = dev; +- priv->snd_card.dai_link = priv->dai_link; +- priv->snd_card.num_links = num; +- priv->snd_card.codec_conf = &priv->codec_conf; +- priv->snd_card.num_configs = 1; ++ card = simple_priv_to_card(priv); ++ card->owner = THIS_MODULE; ++ card->dev = dev; ++ card->dai_link = priv->dai_link; ++ card->num_links = num; ++ card->codec_conf = &priv->codec_conf; ++ card->num_configs = 1; + + ret = asoc_simple_card_parse_of(np, priv); + if (ret < 0) { +@@ -290,13 +295,13 @@ static int asoc_simple_card_probe(struct platform_device *pdev) + goto err; + } + +- snd_soc_card_set_drvdata(&priv->snd_card, priv); ++ snd_soc_card_set_drvdata(card, priv); + +- ret = devm_snd_soc_register_card(dev, &priv->snd_card); ++ ret = devm_snd_soc_register_card(dev, card); + if (ret >= 0) + return ret; + err: +- asoc_simple_card_clean_reference(&priv->snd_card); ++ asoc_simple_card_clean_reference(card); + + return ret; + } +-- +2.13.3 + diff --git a/patches.renesas/0132-smsc911x-Adding-support-for-Micochip-LAN9250-Etherne.patch b/patches.renesas/0132-smsc911x-Adding-support-for-Micochip-LAN9250-Etherne.patch new file mode 100644 index 00000000000000..ecfd8824e4077c --- /dev/null +++ b/patches.renesas/0132-smsc911x-Adding-support-for-Micochip-LAN9250-Etherne.patch @@ -0,0 +1,152 @@ +From 181e06e684c052715499d9e5213e7f883f3282cc Mon Sep 17 00:00:00 2001 +From: David Cai <david.cai@microchip.com> +Date: Tue, 2 May 2017 20:59:14 +0000 +Subject: [PATCH 132/286] smsc911x: Adding support for Micochip LAN9250 + Ethernet controller + +Adding support for Microchip LAN9250 Ethernet controller. + +Signed-off-by: David Cai <david.cai@microchip.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit f6fec61eb555e47e87234e8915ad726ba6c2d3f8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/ethernet/smsc/smsc911x.c | 49 ++++++++++++++++++++++-------------- + drivers/net/ethernet/smsc/smsc911x.h | 19 ++++++++++++++ + 2 files changed, 49 insertions(+), 19 deletions(-) + +diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c +index 6fb2d15b5351..d0e9f6530580 100644 +--- a/drivers/net/ethernet/smsc/smsc911x.c ++++ b/drivers/net/ethernet/smsc/smsc911x.c +@@ -25,7 +25,7 @@ + * LAN9215, LAN9216, LAN9217, LAN9218 + * LAN9210, LAN9211 + * LAN9220, LAN9221 +- * LAN89218 ++ * LAN89218,LAN9250 + * + */ + +@@ -1450,6 +1450,8 @@ static int smsc911x_soft_reset(struct smsc911x_data *pdata) + unsigned int timeout; + unsigned int temp; + int ret; ++ unsigned int reset_offset = HW_CFG; ++ unsigned int reset_mask = HW_CFG_SRST_; + + /* + * Make sure to power-up the PHY chip before doing a reset, otherwise +@@ -1476,15 +1478,23 @@ static int smsc911x_soft_reset(struct smsc911x_data *pdata) + } + } + ++ if ((pdata->idrev & 0xFFFF0000) == LAN9250) { ++ /* special reset for LAN9250 */ ++ reset_offset = RESET_CTL; ++ reset_mask = RESET_CTL_DIGITAL_RST_; ++ } ++ + /* Reset the LAN911x */ +- smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_); ++ smsc911x_reg_write(pdata, reset_offset, reset_mask); ++ ++ /* verify reset bit is cleared */ + timeout = 10; + do { + udelay(10); +- temp = smsc911x_reg_read(pdata, HW_CFG); +- } while ((--timeout) && (temp & HW_CFG_SRST_)); ++ temp = smsc911x_reg_read(pdata, reset_offset); ++ } while ((--timeout) && (temp & reset_mask)); + +- if (unlikely(temp & HW_CFG_SRST_)) { ++ if (unlikely(temp & reset_mask)) { + SMSC_WARN(pdata, drv, "Failed to complete reset"); + return -EIO; + } +@@ -2259,28 +2269,29 @@ static int smsc911x_init(struct net_device *dev) + + pdata->idrev = smsc911x_reg_read(pdata, ID_REV); + switch (pdata->idrev & 0xFFFF0000) { +- case 0x01180000: +- case 0x01170000: +- case 0x01160000: +- case 0x01150000: +- case 0x218A0000: ++ case LAN9118: ++ case LAN9117: ++ case LAN9116: ++ case LAN9115: ++ case LAN89218: + /* LAN911[5678] family */ + pdata->generation = pdata->idrev & 0x0000FFFF; + break; + +- case 0x118A0000: +- case 0x117A0000: +- case 0x116A0000: +- case 0x115A0000: ++ case LAN9218: ++ case LAN9217: ++ case LAN9216: ++ case LAN9215: + /* LAN921[5678] family */ + pdata->generation = 3; + break; + +- case 0x92100000: +- case 0x92110000: +- case 0x92200000: +- case 0x92210000: +- /* LAN9210/LAN9211/LAN9220/LAN9221 */ ++ case LAN9210: ++ case LAN9211: ++ case LAN9220: ++ case LAN9221: ++ case LAN9250: ++ /* LAN9210/LAN9211/LAN9220/LAN9221/LAN9250 */ + pdata->generation = 4; + break; + +diff --git a/drivers/net/ethernet/smsc/smsc911x.h b/drivers/net/ethernet/smsc/smsc911x.h +index 54d648920a1b..8d75508acd2b 100644 +--- a/drivers/net/ethernet/smsc/smsc911x.h ++++ b/drivers/net/ethernet/smsc/smsc911x.h +@@ -20,6 +20,22 @@ + #ifndef __SMSC911X_H__ + #define __SMSC911X_H__ + ++/*Chip ID*/ ++#define LAN9115 0x01150000 ++#define LAN9116 0x01160000 ++#define LAN9117 0x01170000 ++#define LAN9118 0x01180000 ++#define LAN9215 0x115A0000 ++#define LAN9216 0x116A0000 ++#define LAN9217 0x117A0000 ++#define LAN9218 0x118A0000 ++#define LAN9210 0x92100000 ++#define LAN9211 0x92110000 ++#define LAN9220 0x92200000 ++#define LAN9221 0x92210000 ++#define LAN9250 0x92500000 ++#define LAN89218 0x218A0000 ++ + #define TX_FIFO_LOW_THRESHOLD ((u32)1600) + #define SMSC911X_EEPROM_SIZE ((u32)128) + #define USE_DEBUG 0 +@@ -303,6 +319,9 @@ + #define E2P_DATA_EEPROM_DATA_ 0x000000FF + #define LAN_REGISTER_EXTENT 0x00000100 + ++#define RESET_CTL 0x1F8 ++#define RESET_CTL_DIGITAL_RST_ 0x00000001 ++ + /* + * MAC Control and Status Register (Indirect Address) + * Offset (through the MAC_CSR CMD and DATA port) +-- +2.13.3 + diff --git a/patches.renesas/0133-usb-gadget-udc-renesas_usb3-add-USB-ID-signal-monito.patch b/patches.renesas/0133-usb-gadget-udc-renesas_usb3-add-USB-ID-signal-monito.patch new file mode 100644 index 00000000000000..2e2ccfd7b57ffa --- /dev/null +++ b/patches.renesas/0133-usb-gadget-udc-renesas_usb3-add-USB-ID-signal-monito.patch @@ -0,0 +1,151 @@ +From 63f957c06c366e02bb5ea89a0b57ea5971befd77 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Thu, 30 Mar 2017 11:16:04 +0900 +Subject: [PATCH 133/286] usb: gadget: udc: renesas_usb3: add USB ID signal + monitoring + +This usb 3.0 peripheral controller has a register (USB_OTG_STA) to monitor +the USB ID signal. So, this patch adds the ID signal monitoring to change +the mode to host (A-Host) or peripheral (B-Peripheral). +This patch also removes hardcoded setting as B-Peripheral mode. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit 77172a1f886a696bab5b4d3006ccf55ee4b1bfe5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/gadget/udc/renesas_usb3.c | 67 ++++++++++++++++++++++++++++++++--- + 1 file changed, 63 insertions(+), 4 deletions(-) + +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index ba78e3f7aea8..898e2d1b681e 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -37,6 +37,9 @@ + #define USB3_USB_INT_ENA_2 0x22c + #define USB3_STUP_DAT_0 0x230 + #define USB3_STUP_DAT_1 0x234 ++#define USB3_USB_OTG_STA 0x268 ++#define USB3_USB_OTG_INT_STA 0x26c ++#define USB3_USB_OTG_INT_ENA 0x270 + #define USB3_P0_MOD 0x280 + #define USB3_P0_CON 0x288 + #define USB3_P0_STA 0x28c +@@ -124,6 +127,9 @@ + /* USB_INT_ENA_2 and USB_INT_STA_2 */ + #define USB_INT_2_PIPE(n) BIT(n) + ++/* USB_OTG_STA, USB_OTG_INT_STA and USB_OTG_INT_ENA */ ++#define USB_OTG_IDMON BIT(4) ++ + /* P0_MOD */ + #define P0_MOD_DIR BIT(6) + +@@ -362,10 +368,6 @@ static void usb3_init_axi_bridge(struct renesas_usb3 *usb3) + + static void usb3_init_epc_registers(struct renesas_usb3 *usb3) + { +- /* FIXME: How to change host / peripheral mode as well? */ +- usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON); +- usb3_clear_bit(usb3, DRD_CON_VBOUT, USB3_DRD_CON); +- + usb3_write(usb3, ~0, USB3_USB_INT_STA_1); + usb3_enable_irq_1(usb3, USB_INT_1_VBUS_CNG); + } +@@ -538,11 +540,49 @@ static void usb3_check_vbus(struct renesas_usb3 *usb3) + } + } + ++static void usb3_set_mode(struct renesas_usb3 *usb3, bool host) ++{ ++ if (host) ++ usb3_clear_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON); ++ else ++ usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON); ++} ++ ++static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable) ++{ ++ if (enable) ++ usb3_set_bit(usb3, DRD_CON_VBOUT, USB3_DRD_CON); ++ else ++ usb3_clear_bit(usb3, DRD_CON_VBOUT, USB3_DRD_CON); ++} ++ ++static void usb3_mode_config(struct renesas_usb3 *usb3, bool host, bool a_dev) ++{ ++ usb3_set_mode(usb3, host); ++ usb3_vbus_out(usb3, a_dev); ++} ++ ++static bool usb3_is_a_device(struct renesas_usb3 *usb3) ++{ ++ return !(usb3_read(usb3, USB3_USB_OTG_STA) & USB_OTG_IDMON); ++} ++ ++static void usb3_check_id(struct renesas_usb3 *usb3) ++{ ++ if (usb3_is_a_device(usb3)) ++ usb3_mode_config(usb3, true, true); ++ else ++ usb3_mode_config(usb3, false, false); ++} ++ + static void renesas_usb3_init_controller(struct renesas_usb3 *usb3) + { + usb3_init_axi_bridge(usb3); + usb3_init_epc_registers(usb3); ++ usb3_write(usb3, USB_OTG_IDMON, USB3_USB_OTG_INT_STA); ++ usb3_write(usb3, USB_OTG_IDMON, USB3_USB_OTG_INT_ENA); + ++ usb3_check_id(usb3); + usb3_check_vbus(usb3); + } + +@@ -551,6 +591,7 @@ static void renesas_usb3_stop_controller(struct renesas_usb3 *usb3) + usb3_disconnect(usb3); + usb3_write(usb3, 0, USB3_P0_INT_ENA); + usb3_write(usb3, 0, USB3_PN_INT_ENA); ++ usb3_write(usb3, 0, USB3_USB_OTG_INT_ENA); + usb3_write(usb3, 0, USB3_USB_INT_ENA_1); + usb3_write(usb3, 0, USB3_USB_INT_ENA_2); + usb3_write(usb3, 0, USB3_AXI_INT_ENA); +@@ -1496,10 +1537,22 @@ static void usb3_irq_epc_int_2(struct renesas_usb3 *usb3, u32 int_sta_2) + } + } + ++static void usb3_irq_idmon_change(struct renesas_usb3 *usb3) ++{ ++ usb3_check_id(usb3); ++} ++ ++static void usb3_irq_otg_int(struct renesas_usb3 *usb3, u32 otg_int_sta) ++{ ++ if (otg_int_sta & USB_OTG_IDMON) ++ usb3_irq_idmon_change(usb3); ++} ++ + static void usb3_irq_epc(struct renesas_usb3 *usb3) + { + u32 int_sta_1 = usb3_read(usb3, USB3_USB_INT_STA_1); + u32 int_sta_2 = usb3_read(usb3, USB3_USB_INT_STA_2); ++ u32 otg_int_sta = usb3_read(usb3, USB3_USB_OTG_INT_STA); + + int_sta_1 &= usb3_read(usb3, USB3_USB_INT_ENA_1); + if (int_sta_1) { +@@ -1510,6 +1563,12 @@ static void usb3_irq_epc(struct renesas_usb3 *usb3) + int_sta_2 &= usb3_read(usb3, USB3_USB_INT_ENA_2); + if (int_sta_2) + usb3_irq_epc_int_2(usb3, int_sta_2); ++ ++ otg_int_sta &= usb3_read(usb3, USB3_USB_OTG_INT_ENA); ++ if (otg_int_sta) { ++ usb3_write(usb3, otg_int_sta, USB3_USB_OTG_INT_STA); ++ usb3_irq_otg_int(usb3, otg_int_sta); ++ } + } + + static irqreturn_t renesas_usb3_irq(int irq, void *_usb3) +-- +2.13.3 + diff --git a/patches.renesas/0134-usb-gadget-udc-renesas_usb3-add-extcon-support.patch b/patches.renesas/0134-usb-gadget-udc-renesas_usb3-add-extcon-support.patch new file mode 100644 index 00000000000000..35d0263560430c --- /dev/null +++ b/patches.renesas/0134-usb-gadget-udc-renesas_usb3-add-extcon-support.patch @@ -0,0 +1,140 @@ +From afde35d3ceec87f8fc0a29deacd653aaf4a27ac3 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Thu, 30 Mar 2017 11:16:05 +0900 +Subject: [PATCH 134/286] usb: gadget: udc: renesas_usb3: add extcon support + +This patch adds extcon support to see VBUS/ID signal states. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit 3b68e7ca388815459ef4466e17ed6661d0d67a5b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/gadget/udc/Kconfig | 1 + + drivers/usb/gadget/udc/renesas_usb3.c | 43 +++++++++++++++++++++++++++++++++-- + 2 files changed, 42 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig +index 658b8da60915..ef7cf8dbf38c 100644 +--- a/drivers/usb/gadget/udc/Kconfig ++++ b/drivers/usb/gadget/udc/Kconfig +@@ -177,6 +177,7 @@ config USB_RENESAS_USBHS_UDC + config USB_RENESAS_USB3 + tristate 'Renesas USB3.0 Peripheral controller' + depends on ARCH_RENESAS || COMPILE_TEST ++ depends on EXTCON + help + Renesas USB3.0 Peripheral controller is a USB peripheral controller + that supports super, high, and full speed USB 3.0 data transfers. +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index 898e2d1b681e..55f8a966b3ae 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -10,6 +10,7 @@ + + #include <linux/delay.h> + #include <linux/err.h> ++#include <linux/extcon.h> + #include <linux/interrupt.h> + #include <linux/io.h> + #include <linux/module.h> +@@ -263,6 +264,8 @@ struct renesas_usb3 { + + struct usb_gadget gadget; + struct usb_gadget_driver *driver; ++ struct extcon_dev *extcon; ++ struct work_struct extcon_work; + + struct renesas_usb3_ep *usb3_ep; + int num_usb3_eps; +@@ -275,6 +278,8 @@ struct renesas_usb3 { + u8 ep0_buf[USB3_EP0_BUF_SIZE]; + bool softconnect; + bool workaround_for_vbus; ++ bool extcon_host; /* check id and set EXTCON_USB_HOST */ ++ bool extcon_usb; /* check vbus and set EXTCON_USB */ + }; + + #define gadget_to_renesas_usb3(_gadget) \ +@@ -338,6 +343,15 @@ static int usb3_wait(struct renesas_usb3 *usb3, u32 reg, u32 mask, + return -EBUSY; + } + ++static void renesas_usb3_extcon_work(struct work_struct *work) ++{ ++ struct renesas_usb3 *usb3 = container_of(work, struct renesas_usb3, ++ extcon_work); ++ ++ extcon_set_state_sync(usb3->extcon, EXTCON_USB_HOST, usb3->extcon_host); ++ extcon_set_state_sync(usb3->extcon, EXTCON_USB, usb3->extcon_usb); ++} ++ + static void usb3_enable_irq_1(struct renesas_usb3 *usb3, u32 bits) + { + usb3_set_bit(usb3, bits, USB3_USB_INT_ENA_1); +@@ -533,10 +547,14 @@ static void usb3_check_vbus(struct renesas_usb3 *usb3) + if (usb3->workaround_for_vbus) { + usb3_connect(usb3); + } else { +- if (usb3_read(usb3, USB3_USB_STA) & USB_STA_VBUS_STA) ++ usb3->extcon_usb = !!(usb3_read(usb3, USB3_USB_STA) & ++ USB_STA_VBUS_STA); ++ if (usb3->extcon_usb) + usb3_connect(usb3); + else + usb3_disconnect(usb3); ++ ++ schedule_work(&usb3->extcon_work); + } + } + +@@ -569,10 +587,14 @@ static bool usb3_is_a_device(struct renesas_usb3 *usb3) + + static void usb3_check_id(struct renesas_usb3 *usb3) + { +- if (usb3_is_a_device(usb3)) ++ usb3->extcon_host = usb3_is_a_device(usb3); ++ ++ if (usb3->extcon_host) + usb3_mode_config(usb3, true, true); + else + usb3_mode_config(usb3, false, false); ++ ++ schedule_work(&usb3->extcon_work); + } + + static void renesas_usb3_init_controller(struct renesas_usb3 *usb3) +@@ -1975,6 +1997,12 @@ static const struct of_device_id usb3_of_match[] = { + }; + MODULE_DEVICE_TABLE(of, usb3_of_match); + ++static const unsigned int renesas_usb3_cable[] = { ++ EXTCON_USB, ++ EXTCON_USB_HOST, ++ EXTCON_NONE, ++}; ++ + static int renesas_usb3_probe(struct platform_device *pdev) + { + struct renesas_usb3 *usb3; +@@ -2018,6 +2046,17 @@ static int renesas_usb3_probe(struct platform_device *pdev) + if (ret < 0) + return ret; + ++ INIT_WORK(&usb3->extcon_work, renesas_usb3_extcon_work); ++ usb3->extcon = devm_extcon_dev_allocate(&pdev->dev, renesas_usb3_cable); ++ if (IS_ERR(usb3->extcon)) ++ return PTR_ERR(usb3->extcon); ++ ++ ret = devm_extcon_dev_register(&pdev->dev, usb3->extcon); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to register extcon\n"); ++ return ret; ++ } ++ + /* for ep0 handling */ + usb3->ep0_req = __renesas_usb3_ep_alloc_request(GFP_KERNEL); + if (!usb3->ep0_req) +-- +2.13.3 + diff --git a/patches.renesas/0135-usb-gadget-udc-renesas_usb3-add-support-for-usb-role.patch b/patches.renesas/0135-usb-gadget-udc-renesas_usb3-add-support-for-usb-role.patch new file mode 100644 index 00000000000000..e3415ca5bc3d63 --- /dev/null +++ b/patches.renesas/0135-usb-gadget-udc-renesas_usb3-add-support-for-usb-role.patch @@ -0,0 +1,160 @@ +From cc28c666d14e15e9d69e351da1c98439aab737e0 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Fri, 31 Mar 2017 12:58:05 +0900 +Subject: [PATCH 135/286] usb: gadget: udc: renesas_usb3: add support for usb + role swap + +This patch adds support for usb role swap via sysfs "role". + +For example: + 1) Connect a usb cable using 2 Salvator-X boards. + - For A-Device, the cable is connected to CN11 (USB3.0 ch0). + - For B-Device, the cable is connected to CN9 (USB2.0 ch0). + 2) On A-Device, you input the following command: + # echo peripheral > /sys/devices/platform/soc/ee020000.usb/role + 3) On B-Device, you input the following command: + # echo host > /sys/devices/platform/soc/ee080200.usb-phy/role + +Then, the A-Device acts as a peripheral and the B-Device acts as +a host. Please note that A-Device must input the following command +if you want the board to act as a host again. + # echo host > /sys/devices/platform/soc/ee020000.usb/role + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit cc995c9ec1184b964ffdf8cf242250bb4319cd91) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/usb/gadget/udc/renesas_usb3.c +--- + .../ABI/testing/sysfs-platform-renesas_usb3 | 15 ++++++ + drivers/usb/gadget/udc/renesas_usb3.c | 56 ++++++++++++++++++++++ + 2 files changed, 71 insertions(+) + create mode 100644 Documentation/ABI/testing/sysfs-platform-renesas_usb3 + +diff --git a/Documentation/ABI/testing/sysfs-platform-renesas_usb3 b/Documentation/ABI/testing/sysfs-platform-renesas_usb3 +new file mode 100644 +index 000000000000..5621c15d5dc0 +--- /dev/null ++++ b/Documentation/ABI/testing/sysfs-platform-renesas_usb3 +@@ -0,0 +1,15 @@ ++What: /sys/devices/platform/<renesas_usb3's name>/role ++Date: March 2017 ++KernelVersion: 4.13 ++Contact: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> ++Description: ++ This file can be read and write. ++ The file can show/change the drd mode of usb. ++ ++ Write the following string to change the mode: ++ "host" - switching mode from peripheral to host. ++ "peripheral" - switching mode from host to peripheral. ++ ++ Read the file, then it shows the following strings: ++ "host" - The mode is host now. ++ "peripheral" - The mode is peripheral now. +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index 55f8a966b3ae..f16649c6d76e 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -372,6 +372,11 @@ static void usb3_disable_pipe_irq(struct renesas_usb3 *usb3, int num) + usb3_clear_bit(usb3, USB_INT_2_PIPE(num), USB3_USB_INT_ENA_2); + } + ++static bool usb3_is_host(struct renesas_usb3 *usb3) ++{ ++ return !(usb3_read(usb3, USB3_DRD_CON) & DRD_CON_PERI_CON); ++} ++ + static void usb3_init_axi_bridge(struct renesas_usb3 *usb3) + { + /* Set AXI_INT */ +@@ -576,8 +581,14 @@ static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable) + + static void usb3_mode_config(struct renesas_usb3 *usb3, bool host, bool a_dev) + { ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb3->lock, flags); + usb3_set_mode(usb3, host); + usb3_vbus_out(usb3, a_dev); ++ if (!host && a_dev) /* for A-Peripheral */ ++ usb3_connect(usb3); ++ spin_unlock_irqrestore(&usb3->lock, flags); + } + + static bool usb3_is_a_device(struct renesas_usb3 *usb3) +@@ -1862,11 +1873,49 @@ static const struct usb_gadget_ops renesas_usb3_gadget_ops = { + .set_selfpowered = renesas_usb3_set_selfpowered, + }; + ++static ssize_t role_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct renesas_usb3 *usb3 = dev_get_drvdata(dev); ++ bool new_mode_is_host; ++ ++ if (!usb3->driver) ++ return -ENODEV; ++ ++ if (!strncmp(buf, "host", strlen("host"))) ++ new_mode_is_host = true; ++ else if (!strncmp(buf, "peripheral", strlen("peripheral"))) ++ new_mode_is_host = false; ++ else ++ return -EINVAL; ++ ++ if (new_mode_is_host == usb3_is_host(usb3)) ++ return -EINVAL; ++ ++ usb3_mode_config(usb3, new_mode_is_host, usb3_is_a_device(usb3)); ++ ++ return count; ++} ++ ++static ssize_t role_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct renesas_usb3 *usb3 = dev_get_drvdata(dev); ++ ++ if (!usb3->driver) ++ return -ENODEV; ++ ++ return sprintf(buf, "%s\n", usb3_is_host(usb3) ? "host" : "peripheral"); ++} ++static DEVICE_ATTR_RW(role); ++ + /*------- platform_driver ------------------------------------------------*/ + static int renesas_usb3_remove(struct platform_device *pdev) + { + struct renesas_usb3 *usb3 = platform_get_drvdata(pdev); + ++ device_remove_file(&pdev->dev, &dev_attr_role); ++ + usb_del_gadget_udc(&usb3->gadget); + + __renesas_usb3_ep_free_request(usb3->ep0_req); +@@ -2066,12 +2115,19 @@ static int renesas_usb3_probe(struct platform_device *pdev) + if (ret < 0) + goto err_add_udc; + ++ ret = device_create_file(&pdev->dev, &dev_attr_role); ++ if (ret < 0) ++ goto err_dev_create; ++ + usb3->workaround_for_vbus = priv->workaround_for_vbus; + + dev_info(&pdev->dev, "probed\n"); + + return 0; + ++err_dev_create: ++ usb_del_gadget_udc(&usb3->gadget); ++ + err_add_udc: + __renesas_usb3_ep_free_request(usb3->ep0_req); + +-- +2.13.3 + diff --git a/patches.renesas/0136-usb-gadget-udc-renesas_usb3-fix-pm_runtime-functions.patch b/patches.renesas/0136-usb-gadget-udc-renesas_usb3-fix-pm_runtime-functions.patch new file mode 100644 index 00000000000000..86c82b4bf276bf --- /dev/null +++ b/patches.renesas/0136-usb-gadget-udc-renesas_usb3-fix-pm_runtime-functions.patch @@ -0,0 +1,38 @@ +From 56d576361b399fa7936be32c5b4c4d0927c48351 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 26 Apr 2017 20:50:07 +0900 +Subject: [PATCH 136/286] usb: gadget: udc: renesas_usb3: fix pm_runtime + functions calling + +This patch fixes an issue that this driver is possible to access +the registers before pm_runtime_get_sync() if a gadget driver is +installed first. After that, oops happens on R-Car Gen3 environment. +To avoid it, this patch changes the pm_runtime call timing from +probe/remove to udc_start/udc_stop. + +Fixes: 746bfe63bba3 ("usb: gadget: renesas_usb3: add support for Renesas USB3.0 peripheral controller") +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit cdc876877ebc3f0677b267756d4564e2a429e730) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/gadget/udc/renesas_usb3.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index f16649c6d76e..401ba92f15db 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -1841,6 +1841,9 @@ static int renesas_usb3_stop(struct usb_gadget *gadget) + pm_runtime_put(usb3_to_dev(usb3)); + pm_runtime_disable(usb3_to_dev(usb3)); + ++ pm_runtime_put(usb3_to_dev(usb3)); ++ pm_runtime_disable(usb3_to_dev(usb3)); ++ + return 0; + } + +-- +2.13.3 + diff --git a/patches.renesas/0137-usb-gadget-udc-renesas_usb3-fix-deadlock-by-spinlock.patch b/patches.renesas/0137-usb-gadget-udc-renesas_usb3-fix-deadlock-by-spinlock.patch new file mode 100644 index 00000000000000..fb38b7e0aabb64 --- /dev/null +++ b/patches.renesas/0137-usb-gadget-udc-renesas_usb3-fix-deadlock-by-spinlock.patch @@ -0,0 +1,40 @@ +From f4c60efb4fc4269eebae46ec0e348ee5ad51a49b Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 26 Apr 2017 20:50:08 +0900 +Subject: [PATCH 137/286] usb: gadget: udc: renesas_usb3: fix deadlock by + spinlock + +This patch fixes an issue that this driver is possible to cause +deadlock by double-spinclocked in renesas_usb3_stop_controller(). +So, this patch removes spinlock API calling in renesas_usb3_stop(). +(In other words, the previous code had a redundant lock.) + +Fixes: 746bfe63bba3 ("usb: gadget: renesas_usb3: add support for Renesas USB3.0 peripheral controller") +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit 067d6fdc558d2c43f0bfdc7af99630dd5eb08dc5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/usb/gadget/udc/renesas_usb3.c +--- + drivers/usb/gadget/udc/renesas_usb3.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index 401ba92f15db..f16649c6d76e 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -1841,9 +1841,6 @@ static int renesas_usb3_stop(struct usb_gadget *gadget) + pm_runtime_put(usb3_to_dev(usb3)); + pm_runtime_disable(usb3_to_dev(usb3)); + +- pm_runtime_put(usb3_to_dev(usb3)); +- pm_runtime_disable(usb3_to_dev(usb3)); +- + return 0; + } + +-- +2.13.3 + diff --git a/patches.renesas/0138-usb-gadget-udc-renesas_usb3-Fix-PN_INT_ENA-disabling.patch b/patches.renesas/0138-usb-gadget-udc-renesas_usb3-Fix-PN_INT_ENA-disabling.patch new file mode 100644 index 00000000000000..49eaf3d434acc0 --- /dev/null +++ b/patches.renesas/0138-usb-gadget-udc-renesas_usb3-Fix-PN_INT_ENA-disabling.patch @@ -0,0 +1,42 @@ +From b34ed6237b6d70437330da9dcd93fdbf6e5ab4a4 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 26 Apr 2017 20:50:10 +0900 +Subject: [PATCH 138/286] usb: gadget: udc: renesas_usb3: Fix PN_INT_ENA + disabling timing + +The PN_INT_ENA register should be used after usb3_pn_change() is called. +So, this patch moves the access from renesas_usb3_stop_controller() to +usb3_disable_pipe_n(). + +Fixes: 746bfe63bba3 ("usb: gadget: renesas_usb3: add support for Renesas USB3.0 peripheral controller") +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +(cherry picked from commit afbbc7913a288c29616bd31ae612548f6475151a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/gadget/udc/renesas_usb3.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index f16649c6d76e..cba129376001 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -623,7 +623,6 @@ static void renesas_usb3_stop_controller(struct renesas_usb3 *usb3) + { + usb3_disconnect(usb3); + usb3_write(usb3, 0, USB3_P0_INT_ENA); +- usb3_write(usb3, 0, USB3_PN_INT_ENA); + usb3_write(usb3, 0, USB3_USB_OTG_INT_ENA); + usb3_write(usb3, 0, USB3_USB_INT_ENA_1); + usb3_write(usb3, 0, USB3_USB_INT_ENA_2); +@@ -1682,6 +1681,7 @@ static int usb3_disable_pipe_n(struct renesas_usb3_ep *usb3_ep) + + spin_lock_irqsave(&usb3->lock, flags); + if (!usb3_pn_change(usb3, usb3_ep->num)) { ++ usb3_write(usb3, 0, USB3_PN_INT_ENA); + usb3_write(usb3, 0, USB3_PN_RAMMAP); + usb3_clear_bit(usb3, PN_CON_EN, USB3_PN_CON); + } +-- +2.13.3 + diff --git a/patches.renesas/0139-media-v4l-vsp1-Fix-format-info-documentation.patch b/patches.renesas/0139-media-v4l-vsp1-Fix-format-info-documentation.patch new file mode 100644 index 00000000000000..300d1af0838f32 --- /dev/null +++ b/patches.renesas/0139-media-v4l-vsp1-Fix-format-info-documentation.patch @@ -0,0 +1,40 @@ +From cddde446001cdae0f52612b8bceed6d491d7cfa0 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran@bingham.xyz> +Date: Thu, 9 Jun 2016 14:57:02 -0300 +Subject: [PATCH 139/286] [media] v4l: vsp1: Fix format-info documentation + +Minor tweaks to document the swap register and make the documentation +match the struct ordering + +Signed-off-by: Kieran Bingham <kieran@bingham.xyz> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit f1450162544f5c4dc801c85bb28f64c0fa6146e7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_pipe.h | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h +index ac4ad2655551..1144bf1e671a 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.h ++++ b/drivers/media/platform/vsp1/vsp1_pipe.h +@@ -25,11 +25,12 @@ struct vsp1_rwpf; + + /* + * struct vsp1_format_info - VSP1 video format description +- * @mbus: media bus format code + * @fourcc: V4L2 pixel format FCC identifier ++ * @mbus: media bus format code ++ * @hwfmt: VSP1 hardware format ++ * @swap: swap register control + * @planes: number of planes + * @bpp: bits per pixel +- * @hwfmt: VSP1 hardware format + * @swap_yc: the Y and C components are swapped (Y comes before C) + * @swap_uv: the U and V components are swapped (V comes before U) + * @hsub: horizontal subsampling factor +-- +2.13.3 + diff --git a/patches.renesas/0140-media-v4l-vsp1-Clean-up-file-handle-in-open-error-pa.patch b/patches.renesas/0140-media-v4l-vsp1-Clean-up-file-handle-in-open-error-pa.patch new file mode 100644 index 00000000000000..6e4071b4144d60 --- /dev/null +++ b/patches.renesas/0140-media-v4l-vsp1-Clean-up-file-handle-in-open-error-pa.patch @@ -0,0 +1,34 @@ +From 54fe8c7437ac37e64bf09c65edf2d73aff9a4a43 Mon Sep 17 00:00:00 2001 +From: Shailendra Verma <shailendra.v@samsung.com> +Date: Fri, 25 Nov 2016 03:07:57 -0200 +Subject: [PATCH 140/286] [media] v4l: vsp1: Clean up file handle in open() + error path + +v4l2_fh_init is already done. So call the v4l2_fh_exit in error +condition before returing from the function. + +Signed-off-by: Shailendra Verma <shailendra.v@samsung.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit dadc3be66c282d4c2c917186447494ae79f7b79f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 3319277c026a..0113a55b19c9 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -1050,6 +1050,7 @@ static int vsp1_video_open(struct file *file) + ret = vsp1_device_get(video->vsp1); + if (ret < 0) { + v4l2_fh_del(vfh); ++ v4l2_fh_exit(vfh); + kfree(vfh); + } + +-- +2.13.3 + diff --git a/patches.renesas/0141-media-v4l-vsp1-Fix-RPF-WPF-U-V-order-in-3-planar-for.patch b/patches.renesas/0141-media-v4l-vsp1-Fix-RPF-WPF-U-V-order-in-3-planar-for.patch new file mode 100644 index 00000000000000..19bcf234ec3e42 --- /dev/null +++ b/patches.renesas/0141-media-v4l-vsp1-Fix-RPF-WPF-U-V-order-in-3-planar-for.patch @@ -0,0 +1,113 @@ +From 6774abf08332a88cc1bb6f0daf6a4f8ed61c66ec Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 12 Feb 2017 20:58:20 -0200 +Subject: [PATCH 141/286] [media] v4l: vsp1: Fix RPF/WPF U/V order in 3-planar + formats on Gen3 + +The RPF and WPF U/V order bits have no effect for 3-planar formats on +Gen3 hardware. Swap the U and V planes addresses manually instead in +that case. + +Fixes: b915bd24a034 ("[media] v4l: vsp1: Add tri-planar memory formats support") + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 3425382288fbd13b60581f20076aebd0ef414282) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_rpf.c | 43 ++++++++++++++++++++-------------- + drivers/media/platform/vsp1/vsp1_wpf.c | 9 +++++++ + 2 files changed, 35 insertions(+), 17 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c +index b2e34a800ffa..1d0944f308ae 100644 +--- a/drivers/media/platform/vsp1/vsp1_rpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rpf.c +@@ -72,7 +72,8 @@ static void rpf_configure(struct vsp1_entity *entity, + } + + if (params == VSP1_ENTITY_PARAMS_PARTITION) { +- unsigned int offsets[2]; ++ struct vsp1_device *vsp1 = rpf->entity.vsp1; ++ struct vsp1_rwpf_memory mem = rpf->mem; + struct v4l2_rect crop; + + /* +@@ -120,22 +121,30 @@ static void rpf_configure(struct vsp1_entity *entity, + (crop.width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) | + (crop.height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT)); + +- offsets[0] = crop.top * format->plane_fmt[0].bytesperline +- + crop.left * fmtinfo->bpp[0] / 8; +- +- if (format->num_planes > 1) +- offsets[1] = crop.top * format->plane_fmt[1].bytesperline +- + crop.left / fmtinfo->hsub +- * fmtinfo->bpp[1] / 8; +- else +- offsets[1] = 0; +- +- vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y, +- rpf->mem.addr[0] + offsets[0]); +- vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0, +- rpf->mem.addr[1] + offsets[1]); +- vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1, +- rpf->mem.addr[2] + offsets[1]); ++ mem.addr[0] += crop.top * format->plane_fmt[0].bytesperline ++ + crop.left * fmtinfo->bpp[0] / 8; ++ ++ if (format->num_planes > 1) { ++ unsigned int offset; ++ ++ offset = crop.top * format->plane_fmt[1].bytesperline ++ + crop.left / fmtinfo->hsub ++ * fmtinfo->bpp[1] / 8; ++ mem.addr[1] += offset; ++ mem.addr[2] += offset; ++ } ++ ++ /* ++ * On Gen3 hardware the SPUVS bit has no effect on 3-planar ++ * formats. Swap the U and V planes manually in that case. ++ */ ++ if (vsp1->info->gen == 3 && format->num_planes == 3 && ++ fmtinfo->swap_uv) ++ swap(mem.addr[1], mem.addr[2]); ++ ++ vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_Y, mem.addr[0]); ++ vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C0, mem.addr[1]); ++ vsp1_rpf_write(rpf, dl, VI6_RPF_SRCM_ADDR_C1, mem.addr[2]); + return; + } + +diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c +index 7c48f81cd5c1..052a83e2d489 100644 +--- a/drivers/media/platform/vsp1/vsp1_wpf.c ++++ b/drivers/media/platform/vsp1/vsp1_wpf.c +@@ -216,6 +216,7 @@ static void wpf_configure(struct vsp1_entity *entity, + + if (params == VSP1_ENTITY_PARAMS_PARTITION) { + const struct v4l2_pix_format_mplane *format = &wpf->format; ++ const struct vsp1_format_info *fmtinfo = wpf->fmtinfo; + struct vsp1_rwpf_memory mem = wpf->mem; + unsigned int flip = wpf->flip.active; + unsigned int width = source_format->width; +@@ -281,6 +282,14 @@ static void wpf_configure(struct vsp1_entity *entity, + } + } + ++ /* ++ * On Gen3 hardware the SPUVS bit has no effect on 3-planar ++ * formats. Swap the U and V planes manually in that case. ++ */ ++ if (vsp1->info->gen == 3 && format->num_planes == 3 && ++ fmtinfo->swap_uv) ++ swap(mem.addr[1], mem.addr[2]); ++ + vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_Y, mem.addr[0]); + vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C0, mem.addr[1]); + vsp1_wpf_write(wpf, dl, VI6_WPF_DSTM_ADDR_C1, mem.addr[2]); +-- +2.13.3 + diff --git a/patches.renesas/0142-media-v4l-vsp1-Prevent-multiple-streamon-race-commen.patch b/patches.renesas/0142-media-v4l-vsp1-Prevent-multiple-streamon-race-commen.patch new file mode 100644 index 00000000000000..b9e90a17c74452 --- /dev/null +++ b/patches.renesas/0142-media-v4l-vsp1-Prevent-multiple-streamon-race-commen.patch @@ -0,0 +1,74 @@ +From a30ea33c0959c27b2069168fec97eeb1c62ea66d Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Fri, 6 Jan 2017 10:15:28 -0200 +Subject: [PATCH 142/286] [media] v4l: vsp1: Prevent multiple streamon race + commencing pipeline early + +With multiple inputs through the BRU it is feasible for the streams to +race each other at stream-on. + +Multiple VIDIOC_STREAMON calls racing each other could have process +N-1 skipping over the pipeline setup section and then start the pipeline +early, if videobuf2 has already enqueued buffers to the driver for +process N but not called the .start_streaming() operation yet + +In the case of the video pipelines, this +can present two serious issues. + + 1) A null-dereference if the pipe->dl is committed at the same time as + the vsp1_video_setup_pipeline() is processing + + 2) A hardware hang, where a display list is committed without having + called vsp1_video_setup_pipeline() first + +Repair this issue, by ensuring that only the stream which configures the +pipeline is able to start it. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 4461c84b52b4a952c657505ef7e4e06b016783df) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_video.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 0113a55b19c9..eb422c150847 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -797,6 +797,7 @@ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count) + { + struct vsp1_video *video = vb2_get_drv_priv(vq); + struct vsp1_pipeline *pipe = video->rwpf->pipe; ++ bool start_pipeline = false; + unsigned long flags; + int ret; + +@@ -807,11 +808,23 @@ static int vsp1_video_start_streaming(struct vb2_queue *vq, unsigned int count) + mutex_unlock(&pipe->lock); + return ret; + } ++ ++ start_pipeline = true; + } + + pipe->stream_count++; + mutex_unlock(&pipe->lock); + ++ /* ++ * vsp1_pipeline_ready() is not sufficient to establish that all streams ++ * are prepared and the pipeline is configured, as multiple streams ++ * can race through streamon with buffers already queued; Therefore we ++ * don't even attempt to start the pipeline until the last stream has ++ * called through here. ++ */ ++ if (!start_pipeline) ++ return 0; ++ + spin_lock_irqsave(&pipe->irqlock, flags); + if (vsp1_pipeline_ready(pipe)) + vsp1_video_pipeline_run(pipe); +-- +2.13.3 + diff --git a/patches.renesas/0143-media-v4l-vsp1-Remove-redundant-pipe-dl-usage-from-d.patch b/patches.renesas/0143-media-v4l-vsp1-Remove-redundant-pipe-dl-usage-from-d.patch new file mode 100644 index 00000000000000..3fe15d4f32f577 --- /dev/null +++ b/patches.renesas/0143-media-v4l-vsp1-Remove-redundant-pipe-dl-usage-from-d.patch @@ -0,0 +1,83 @@ +From 7969fe3ab2a6a4a3bd5f12767adf43c405bbce61 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Fri, 6 Jan 2017 10:15:31 -0200 +Subject: [PATCH 143/286] [media] v4l: vsp1: Remove redundant pipe->dl usage + from drm + +The pipe->dl is used only inside vsp1_du_atomic_flush(), and can be +obtained and stored locally to simplify the code. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit f2074708ee07848f86105b68bdce062de4e6685d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_drm.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c +index 10287be5606f..afcb754579fc 100644 +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -219,9 +219,6 @@ void vsp1_du_atomic_begin(struct device *dev) + struct vsp1_pipeline *pipe = &vsp1->drm->pipe; + + vsp1->drm->num_inputs = pipe->num_inputs; +- +- /* Prepare the display list. */ +- pipe->dl = vsp1_dl_list_get(pipe->output->dlm); + } + EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin); + +@@ -425,10 +422,14 @@ void vsp1_du_atomic_flush(struct device *dev) + struct vsp1_pipeline *pipe = &vsp1->drm->pipe; + struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, }; + struct vsp1_entity *entity; ++ struct vsp1_dl_list *dl; + unsigned long flags; + unsigned int i; + int ret; + ++ /* Prepare the display list. */ ++ dl = vsp1_dl_list_get(pipe->output->dlm); ++ + /* Count the number of enabled inputs and sort them by Z-order. */ + pipe->num_inputs = 0; + +@@ -483,26 +484,25 @@ void vsp1_du_atomic_flush(struct device *dev) + struct vsp1_rwpf *rpf = to_rwpf(&entity->subdev); + + if (!pipe->inputs[rpf->entity.index]) { +- vsp1_dl_list_write(pipe->dl, entity->route->reg, ++ vsp1_dl_list_write(dl, entity->route->reg, + VI6_DPR_NODE_UNUSED); + continue; + } + } + +- vsp1_entity_route_setup(entity, pipe->dl); ++ vsp1_entity_route_setup(entity, dl); + + if (entity->ops->configure) { +- entity->ops->configure(entity, pipe, pipe->dl, ++ entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_INIT); +- entity->ops->configure(entity, pipe, pipe->dl, ++ entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_RUNTIME); +- entity->ops->configure(entity, pipe, pipe->dl, ++ entity->ops->configure(entity, pipe, dl, + VSP1_ENTITY_PARAMS_PARTITION); + } + } + +- vsp1_dl_list_commit(pipe->dl); +- pipe->dl = NULL; ++ vsp1_dl_list_commit(dl); + + /* Start or stop the pipeline if needed. */ + if (!vsp1->drm->num_inputs && pipe->num_inputs) { +-- +2.13.3 + diff --git a/patches.renesas/0144-media-v4l-vsp1-Fix-multi-line-comment-style.patch b/patches.renesas/0144-media-v4l-vsp1-Fix-multi-line-comment-style.patch new file mode 100644 index 00000000000000..ff61084da16c93 --- /dev/null +++ b/patches.renesas/0144-media-v4l-vsp1-Fix-multi-line-comment-style.patch @@ -0,0 +1,679 @@ +From 12e22e7b09865fd034a229106baf224f4b48becb Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 26 Feb 2017 10:29:50 -0300 +Subject: [PATCH 144/286] [media] v4l: vsp1: Fix multi-line comment style + +Fix all multi-line comments to comply with the kernel coding style. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 9dbed95ba640c1b4fb2d069814924811bdeb0de6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_bru.c | 27 ++++++++++++++++--------- + drivers/media/platform/vsp1/vsp1_dl.c | 27 ++++++++++++++++--------- + drivers/media/platform/vsp1/vsp1_drm.c | 21 +++++++++++++------- + drivers/media/platform/vsp1/vsp1_drv.c | 12 +++++++---- + drivers/media/platform/vsp1/vsp1_entity.c | 9 ++++++--- + drivers/media/platform/vsp1/vsp1_hsit.c | 3 ++- + drivers/media/platform/vsp1/vsp1_lif.c | 6 ++++-- + drivers/media/platform/vsp1/vsp1_pipe.c | 9 ++++++--- + drivers/media/platform/vsp1/vsp1_rpf.c | 9 ++++++--- + drivers/media/platform/vsp1/vsp1_rwpf.c | 6 ++++-- + drivers/media/platform/vsp1/vsp1_sru.c | 3 ++- + drivers/media/platform/vsp1/vsp1_uds.c | 3 ++- + drivers/media/platform/vsp1/vsp1_video.c | 33 ++++++++++++++++++++----------- + drivers/media/platform/vsp1/vsp1_wpf.c | 12 +++++++---- + 14 files changed, 120 insertions(+), 60 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_bru.c b/drivers/media/platform/vsp1/vsp1_bru.c +index ee8355c28f94..85362c5ef57a 100644 +--- a/drivers/media/platform/vsp1/vsp1_bru.c ++++ b/drivers/media/platform/vsp1/vsp1_bru.c +@@ -251,7 +251,8 @@ static int bru_set_selection(struct v4l2_subdev *subdev, + sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1); + sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1); + +- /* Scaling isn't supported, the compose rectangle size must be identical ++ /* ++ * Scaling isn't supported, the compose rectangle size must be identical + * to the sink format size. + */ + format = vsp1_entity_get_pad_format(&bru->entity, config, sel->pad); +@@ -300,13 +301,15 @@ static void bru_configure(struct vsp1_entity *entity, + format = vsp1_entity_get_pad_format(&bru->entity, bru->entity.config, + bru->entity.source_pad); + +- /* The hardware is extremely flexible but we have no userspace API to ++ /* ++ * The hardware is extremely flexible but we have no userspace API to + * expose all the parameters, nor is it clear whether we would have use + * cases for all the supported modes. Let's just harcode the parameters + * to sane default values for now. + */ + +- /* Disable dithering and enable color data normalization unless the ++ /* ++ * Disable dithering and enable color data normalization unless the + * format at the pipeline output is premultiplied. + */ + flags = pipe->output ? pipe->output->format.flags : 0; +@@ -314,7 +317,8 @@ static void bru_configure(struct vsp1_entity *entity, + flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ? + 0 : VI6_BRU_INCTRL_NRM); + +- /* Set the background position to cover the whole output image and ++ /* ++ * Set the background position to cover the whole output image and + * configure its color. + */ + vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_SIZE, +@@ -325,7 +329,8 @@ static void bru_configure(struct vsp1_entity *entity, + vsp1_bru_write(bru, dl, VI6_BRU_VIRRPF_COL, bru->bgcolor | + (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT)); + +- /* Route BRU input 1 as SRC input to the ROP unit and configure the ROP ++ /* ++ * Route BRU input 1 as SRC input to the ROP unit and configure the ROP + * unit with a NOP operation to make BRU input 1 available as the + * Blend/ROP unit B SRC input. + */ +@@ -337,7 +342,8 @@ static void bru_configure(struct vsp1_entity *entity, + bool premultiplied = false; + u32 ctrl = 0; + +- /* Configure all Blend/ROP units corresponding to an enabled BRU ++ /* ++ * Configure all Blend/ROP units corresponding to an enabled BRU + * input for alpha blending. Blend/ROP units corresponding to + * disabled BRU inputs are used in ROP NOP mode to ignore the + * SRC input. +@@ -352,13 +358,15 @@ static void bru_configure(struct vsp1_entity *entity, + | VI6_BRU_CTRL_AROP(VI6_ROP_NOP); + } + +- /* Select the virtual RPF as the Blend/ROP unit A DST input to ++ /* ++ * Select the virtual RPF as the Blend/ROP unit A DST input to + * serve as a background color. + */ + if (i == 0) + ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF; + +- /* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to ++ /* ++ * Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to + * D in that order. The Blend/ROP unit B SRC is hardwired to the + * ROP unit output, the corresponding register bits must be set + * to 0. +@@ -368,7 +376,8 @@ static void bru_configure(struct vsp1_entity *entity, + + vsp1_bru_write(bru, dl, VI6_BRU_CTRL(i), ctrl); + +- /* Harcode the blending formula to ++ /* ++ * Harcode the blending formula to + * + * DSTc = DSTc * (1 - SRCa) + SRCc * SRCa + * DSTa = DSTa * (1 - SRCa) + SRCa +diff --git a/drivers/media/platform/vsp1/vsp1_dl.c b/drivers/media/platform/vsp1/vsp1_dl.c +index ad545aff4e35..7d8f37772b56 100644 +--- a/drivers/media/platform/vsp1/vsp1_dl.c ++++ b/drivers/media/platform/vsp1/vsp1_dl.c +@@ -240,7 +240,8 @@ static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm) + INIT_LIST_HEAD(&dl->fragments); + dl->dlm = dlm; + +- /* Initialize the display list body and allocate DMA memory for the body ++ /* ++ * Initialize the display list body and allocate DMA memory for the body + * and the optional header. Both are allocated together to avoid memory + * fragmentation, with the header located right after the body in + * memory. +@@ -511,7 +512,8 @@ void vsp1_dl_list_commit(struct vsp1_dl_list *dl) + goto done; + } + +- /* Once the UPD bit has been set the hardware can start processing the ++ /* ++ * Once the UPD bit has been set the hardware can start processing the + * display list at any time and we can't touch the address and size + * registers. In that case mark the update as pending, it will be + * queued up to the hardware by the frame end interrupt handler. +@@ -523,7 +525,8 @@ void vsp1_dl_list_commit(struct vsp1_dl_list *dl) + goto done; + } + +- /* Program the hardware with the display list body address and size. ++ /* ++ * Program the hardware with the display list body address and size. + * The UPD bit will be cleared by the device when the display list is + * processed. + */ +@@ -547,7 +550,8 @@ void vsp1_dlm_irq_display_start(struct vsp1_dl_manager *dlm) + { + spin_lock(&dlm->lock); + +- /* The display start interrupt signals the end of the display list ++ /* ++ * The display start interrupt signals the end of the display list + * processing by the device. The active display list, if any, won't be + * accessed anymore and can be reused. + */ +@@ -566,14 +570,16 @@ void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm) + __vsp1_dl_list_put(dlm->active); + dlm->active = NULL; + +- /* Header mode is used for mem-to-mem pipelines only. We don't need to ++ /* ++ * Header mode is used for mem-to-mem pipelines only. We don't need to + * perform any operation as there can't be any new display list queued + * in that case. + */ + if (dlm->mode == VSP1_DL_MODE_HEADER) + goto done; + +- /* The UPD bit set indicates that the commit operation raced with the ++ /* ++ * The UPD bit set indicates that the commit operation raced with the + * interrupt and occurred after the frame end event and UPD clear but + * before interrupt processing. The hardware hasn't taken the update + * into account yet, we'll thus skip one frame and retry. +@@ -581,7 +587,8 @@ void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm) + if (vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD) + goto done; + +- /* The device starts processing the queued display list right after the ++ /* ++ * The device starts processing the queued display list right after the + * frame end interrupt. The display list thus becomes active. + */ + if (dlm->queued) { +@@ -589,7 +596,8 @@ void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm) + dlm->queued = NULL; + } + +- /* Now that the UPD bit has been cleared we can queue the next display ++ /* ++ * Now that the UPD bit has been cleared we can queue the next display + * list to the hardware if one has been prepared. + */ + if (dlm->pending) { +@@ -615,7 +623,8 @@ void vsp1_dlm_setup(struct vsp1_device *vsp1) + | VI6_DL_CTRL_DC2 | VI6_DL_CTRL_DC1 | VI6_DL_CTRL_DC0 + | VI6_DL_CTRL_DLE; + +- /* The DRM pipeline operates with display lists in Continuous Frame ++ /* ++ * The DRM pipeline operates with display lists in Continuous Frame + * Mode, all other pipelines use manual start. + */ + if (vsp1->drm) +diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c +index afcb754579fc..8cd88547da2c 100644 +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -78,7 +78,8 @@ int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg) + int ret; + + if (!cfg) { +- /* NULL configuration means the CRTC is being disabled, stop ++ /* ++ * NULL configuration means the CRTC is being disabled, stop + * the pipeline and turn the light off. + */ + ret = vsp1_pipeline_stop(pipe); +@@ -106,7 +107,8 @@ int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg) + dev_dbg(vsp1->dev, "%s: configuring LIF with format %ux%u\n", + __func__, cfg->width, cfg->height); + +- /* Configure the format at the BRU sinks and propagate it through the ++ /* ++ * Configure the format at the BRU sinks and propagate it through the + * pipeline. + */ + memset(&format, 0, sizeof(format)); +@@ -175,7 +177,8 @@ int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg) + __func__, format.format.width, format.format.height, + format.format.code); + +- /* Verify that the format at the output of the pipeline matches the ++ /* ++ * Verify that the format at the output of the pipeline matches the + * requested frame size and media bus code. + */ + if (format.format.width != cfg->width || +@@ -185,7 +188,8 @@ int vsp1_du_setup_lif(struct device *dev, const struct vsp1_du_lif_config *cfg) + return -EPIPE; + } + +- /* Mark the pipeline as streaming and enable the VSP1. This will store ++ /* ++ * Mark the pipeline as streaming and enable the VSP1. This will store + * the pipeline pointer in all entities, which the s_stream handlers + * will need. We don't start the entities themselves right at this point + * as there's no plane configured yet, so we can't start processing +@@ -317,7 +321,8 @@ static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1, + const struct v4l2_rect *crop; + int ret; + +- /* Configure the format on the RPF sink pad and propagate it up to the ++ /* ++ * Configure the format on the RPF sink pad and propagate it up to the + * BRU sink pad. + */ + crop = &vsp1->drm->inputs[rpf->entity.index].crop; +@@ -356,7 +361,8 @@ static int vsp1_du_setup_rpf_pipe(struct vsp1_device *vsp1, + __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height, + rpf->entity.index); + +- /* RPF source, hardcode the format to ARGB8888 to turn on format ++ /* ++ * RPF source, hardcode the format to ARGB8888 to turn on format + * conversion if needed. + */ + format.pad = RWPF_PAD_SOURCE; +@@ -528,7 +534,8 @@ int vsp1_drm_create_links(struct vsp1_device *vsp1) + unsigned int i; + int ret; + +- /* VSPD instances require a BRU to perform composition and a LIF to ++ /* ++ * VSPD instances require a BRU to perform composition and a LIF to + * output to the DU. + */ + if (!vsp1->bru || !vsp1->lif) +diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c +index aa237b48ad55..8d1e61b353bb 100644 +--- a/drivers/media/platform/vsp1/vsp1_drv.c ++++ b/drivers/media/platform/vsp1/vsp1_drv.c +@@ -170,7 +170,8 @@ static int vsp1_uapi_create_links(struct vsp1_device *vsp1) + } + + for (i = 0; i < vsp1->info->wpf_count; ++i) { +- /* Connect the video device to the WPF. All connections are ++ /* ++ * Connect the video device to the WPF. All connections are + * immutable. + */ + struct vsp1_rwpf *wpf = vsp1->wpf[i]; +@@ -227,7 +228,8 @@ static int vsp1_create_entities(struct vsp1_device *vsp1) + media_device_init(mdev); + + vsp1->media_ops.link_setup = vsp1_entity_link_setup; +- /* Don't perform link validation when the userspace API is disabled as ++ /* ++ * Don't perform link validation when the userspace API is disabled as + * the pipeline is configured internally by the driver in that case, and + * its configuration can thus be trusted. + */ +@@ -279,7 +281,8 @@ static int vsp1_create_entities(struct vsp1_device *vsp1) + + list_add_tail(&vsp1->hst->entity.list_dev, &vsp1->entities); + +- /* The LIF is only supported when used in conjunction with the DU, in ++ /* ++ * The LIF is only supported when used in conjunction with the DU, in + * which case the userspace API is disabled. If the userspace API is + * enabled skip the LIF, even when present. + */ +@@ -391,7 +394,8 @@ static int vsp1_create_entities(struct vsp1_device *vsp1) + if (ret < 0) + goto done; + +- /* Register subdev nodes if the userspace API is enabled or initialize ++ /* ++ * Register subdev nodes if the userspace API is enabled or initialize + * the DRM pipeline otherwise. + */ + if (vsp1->info->uapi) { +diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c +index da673495c222..12eca5660d6e 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.c ++++ b/drivers/media/platform/vsp1/vsp1_entity.c +@@ -199,7 +199,8 @@ int vsp1_subdev_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config; + struct v4l2_mbus_framefmt *format; + +- /* The entity can't perform format conversion, the sink format ++ /* ++ * The entity can't perform format conversion, the sink format + * is always identical to the source format. + */ + if (code->index) +@@ -263,7 +264,8 @@ int vsp1_subdev_enum_frame_size(struct v4l2_subdev *subdev, + fse->min_height = min_height; + fse->max_height = max_height; + } else { +- /* The size on the source pad are fixed and always identical to ++ /* ++ * The size on the source pad are fixed and always identical to + * the size on the sink pad. + */ + fse->min_width = format->width; +@@ -407,7 +409,8 @@ int vsp1_entity_init(struct vsp1_device *vsp1, struct vsp1_entity *entity, + + vsp1_entity_init_cfg(subdev, NULL); + +- /* Allocate the pad configuration to store formats and selection ++ /* ++ * Allocate the pad configuration to store formats and selection + * rectangles. + */ + entity->config = v4l2_subdev_alloc_pad_config(&entity->subdev); +diff --git a/drivers/media/platform/vsp1/vsp1_hsit.c b/drivers/media/platform/vsp1/vsp1_hsit.c +index 94316afc54ff..764d405345ee 100644 +--- a/drivers/media/platform/vsp1/vsp1_hsit.c ++++ b/drivers/media/platform/vsp1/vsp1_hsit.c +@@ -84,7 +84,8 @@ static int hsit_set_format(struct v4l2_subdev *subdev, + format = vsp1_entity_get_pad_format(&hsit->entity, config, fmt->pad); + + if (fmt->pad == HSIT_PAD_SOURCE) { +- /* The HST and HSI output format code and resolution can't be ++ /* ++ * The HST and HSI output format code and resolution can't be + * modified. + */ + fmt->format = *format; +diff --git a/drivers/media/platform/vsp1/vsp1_lif.c b/drivers/media/platform/vsp1/vsp1_lif.c +index e32acae1fc6e..702487f895b3 100644 +--- a/drivers/media/platform/vsp1/vsp1_lif.c ++++ b/drivers/media/platform/vsp1/vsp1_lif.c +@@ -84,7 +84,8 @@ static int lif_set_format(struct v4l2_subdev *subdev, + format = vsp1_entity_get_pad_format(&lif->entity, config, fmt->pad); + + if (fmt->pad == LIF_PAD_SOURCE) { +- /* The LIF source format is always identical to its sink ++ /* ++ * The LIF source format is always identical to its sink + * format. + */ + fmt->format = *format; +@@ -176,7 +177,8 @@ struct vsp1_lif *vsp1_lif_create(struct vsp1_device *vsp1) + lif->entity.ops = &lif_entity_ops; + lif->entity.type = VSP1_ENTITY_LIF; + +- /* The LIF is never exposed to userspace, but media entity registration ++ /* ++ * The LIF is never exposed to userspace, but media entity registration + * requires a function to be set. Use PROC_VIDEO_PIXEL_FORMATTER just to + * avoid triggering a WARN_ON(), the value won't be seen anywhere. + */ +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c +index 280ba0804699..3f1acf68dc6e 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.c ++++ b/drivers/media/platform/vsp1/vsp1_pipe.c +@@ -251,7 +251,8 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + int ret; + + if (pipe->lif) { +- /* When using display lists in continuous frame mode the only ++ /* ++ * When using display lists in continuous frame mode the only + * way to stop the pipeline is to reset the hardware. + */ + ret = vsp1_reset_wpf(pipe->output->entity.vsp1, +@@ -322,7 +323,8 @@ void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe, + if (!pipe->uds) + return; + +- /* The BRU background color has a fixed alpha value set to 255, the ++ /* ++ * The BRU background color has a fixed alpha value set to 255, the + * output alpha value is thus always equal to 255. + */ + if (pipe->uds_input->type == VSP1_ENTITY_BRU) +@@ -337,7 +339,8 @@ void vsp1_pipelines_suspend(struct vsp1_device *vsp1) + unsigned int i; + int ret; + +- /* To avoid increasing the system suspend time needlessly, loop over the ++ /* ++ * To avoid increasing the system suspend time needlessly, loop over the + * pipelines twice, first to set them all to the stopping state, and + * then to wait for the stop to complete. + */ +diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c +index 1d0944f308ae..f5a9a4c8c74d 100644 +--- a/drivers/media/platform/vsp1/vsp1_rpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rpf.c +@@ -195,7 +195,8 @@ static void rpf_configure(struct vsp1_entity *entity, + (left << VI6_RPF_LOC_HCOORD_SHIFT) | + (top << VI6_RPF_LOC_VCOORD_SHIFT)); + +- /* On Gen2 use the alpha channel (extended to 8 bits) when available or ++ /* ++ * On Gen2 use the alpha channel (extended to 8 bits) when available or + * a fixed alpha value set through the V4L2_CID_ALPHA_COMPONENT control + * otherwise. + * +@@ -225,7 +226,8 @@ static void rpf_configure(struct vsp1_entity *entity, + u32 mult; + + if (fmtinfo->alpha) { +- /* When the input contains an alpha channel enable the ++ /* ++ * When the input contains an alpha channel enable the + * alpha multiplier. If the input is premultiplied we + * need to multiply both the alpha channel and the pixel + * components by the global alpha value to keep them +@@ -240,7 +242,8 @@ static void rpf_configure(struct vsp1_entity *entity, + VI6_RPF_MULT_ALPHA_P_MMD_RATIO : + VI6_RPF_MULT_ALPHA_P_MMD_NONE); + } else { +- /* When the input doesn't contain an alpha channel the ++ /* ++ * When the input doesn't contain an alpha channel the + * global alpha value is applied in the unpacking unit, + * the alpha multiplier isn't needed and must be + * disabled. +diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c +index 04104ef28fb5..7d52c88a583e 100644 +--- a/drivers/media/platform/vsp1/vsp1_rwpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rwpf.c +@@ -86,7 +86,8 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev, + format = vsp1_entity_get_pad_format(&rwpf->entity, config, fmt->pad); + + if (fmt->pad == RWPF_PAD_SOURCE) { +- /* The RWPF performs format conversion but can't scale, only the ++ /* ++ * The RWPF performs format conversion but can't scale, only the + * format code can be changed on the source pad. + */ + format->code = fmt->format.code; +@@ -205,7 +206,8 @@ static int vsp1_rwpf_set_selection(struct v4l2_subdev *subdev, + format = vsp1_entity_get_pad_format(&rwpf->entity, config, + RWPF_PAD_SINK); + +- /* Restrict the crop rectangle coordinates to multiples of 2 to avoid ++ /* ++ * Restrict the crop rectangle coordinates to multiples of 2 to avoid + * shifting the color plane. + */ + if (format->code == MEDIA_BUS_FMT_AYUV8_1X32) { +diff --git a/drivers/media/platform/vsp1/vsp1_sru.c b/drivers/media/platform/vsp1/vsp1_sru.c +index b4e568a3b4ed..30142793dfcd 100644 +--- a/drivers/media/platform/vsp1/vsp1_sru.c ++++ b/drivers/media/platform/vsp1/vsp1_sru.c +@@ -191,7 +191,8 @@ static void sru_try_format(struct vsp1_sru *sru, + SRU_PAD_SINK); + fmt->code = format->code; + +- /* We can upscale by 2 in both direction, but not independently. ++ /* ++ * We can upscale by 2 in both direction, but not independently. + * Compare the input and output rectangles areas (avoiding + * integer overflows on the output): if the requested output + * area is larger than 1.5^2 the input area upscale by two, +diff --git a/drivers/media/platform/vsp1/vsp1_uds.c b/drivers/media/platform/vsp1/vsp1_uds.c +index da8f89a31ea4..4226403ad235 100644 +--- a/drivers/media/platform/vsp1/vsp1_uds.c ++++ b/drivers/media/platform/vsp1/vsp1_uds.c +@@ -293,7 +293,8 @@ static void uds_configure(struct vsp1_entity *entity, + + dev_dbg(uds->entity.vsp1->dev, "hscale %u vscale %u\n", hscale, vscale); + +- /* Multi-tap scaling can't be enabled along with alpha scaling when ++ /* ++ * Multi-tap scaling can't be enabled along with alpha scaling when + * scaling down with a factor lower than or equal to 1/2 in either + * direction. + */ +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index eb422c150847..620beb21dd14 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -103,7 +103,8 @@ static int __vsp1_video_try_format(struct vsp1_video *video, + unsigned int height = pix->height; + unsigned int i; + +- /* Backward compatibility: replace deprecated RGB formats by their XRGB ++ /* ++ * Backward compatibility: replace deprecated RGB formats by their XRGB + * equivalent. This selects the format older userspace applications want + * while still exposing the new format. + */ +@@ -114,7 +115,8 @@ static int __vsp1_video_try_format(struct vsp1_video *video, + } + } + +- /* Retrieve format information and select the default format if the ++ /* ++ * Retrieve format information and select the default format if the + * requested format isn't supported. + */ + info = vsp1_get_format_info(video->vsp1, pix->pixelformat); +@@ -140,7 +142,8 @@ static int __vsp1_video_try_format(struct vsp1_video *video, + pix->height = clamp(height, VSP1_VIDEO_MIN_HEIGHT, + VSP1_VIDEO_MAX_HEIGHT); + +- /* Compute and clamp the stride and image size. While not documented in ++ /* ++ * Compute and clamp the stride and image size. While not documented in + * the datasheet, strides not aligned to a multiple of 128 bytes result + * in image corruption. + */ +@@ -449,7 +452,8 @@ static void vsp1_video_pipeline_frame_end(struct vsp1_pipeline *pipe) + state = pipe->state; + pipe->state = VSP1_PIPELINE_STOPPED; + +- /* If a stop has been requested, mark the pipeline as stopped and ++ /* ++ * If a stop has been requested, mark the pipeline as stopped and + * return. Otherwise restart the pipeline if ready. + */ + if (state == VSP1_PIPELINE_STOPPING) +@@ -491,7 +495,8 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe, + entity = to_vsp1_entity( + media_entity_to_v4l2_subdev(pad->entity)); + +- /* A BRU is present in the pipeline, store the BRU input pad ++ /* ++ * A BRU is present in the pipeline, store the BRU input pad + * number in the input RPF for use when configuring the RPF. + */ + if (entity->type == VSP1_ENTITY_BRU) { +@@ -526,7 +531,8 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe, + : &input->entity; + } + +- /* Follow the source link. The link setup operations ensure ++ /* ++ * Follow the source link. The link setup operations ensure + * that the output fan-out can't be more than one, there is thus + * no need to verify here that only a single source link is + * activated. +@@ -596,7 +602,8 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe, + if (pipe->num_inputs == 0 || !pipe->output) + return -EPIPE; + +- /* Follow links downstream for each input and make sure the graph ++ /* ++ * Follow links downstream for each input and make sure the graph + * contains no loop and that all branches end at the output WPF. + */ + for (i = 0; i < video->vsp1->info->rpf_count; ++i) { +@@ -627,7 +634,8 @@ static struct vsp1_pipeline *vsp1_video_pipeline_get(struct vsp1_video *video) + struct vsp1_pipeline *pipe; + int ret; + +- /* Get a pipeline object for the video node. If a pipeline has already ++ /* ++ * Get a pipeline object for the video node. If a pipeline has already + * been allocated just increment its reference count and return it. + * Otherwise allocate a new pipeline and initialize it, it will be freed + * when the last reference is released. +@@ -767,7 +775,8 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe) + if (pipe->uds) { + struct vsp1_uds *uds = to_uds(&pipe->uds->subdev); + +- /* If a BRU is present in the pipeline before the UDS, the alpha ++ /* ++ * If a BRU is present in the pipeline before the UDS, the alpha + * component doesn't need to be scaled as the BRU output alpha + * value is fixed to 255. Otherwise we need to scale the alpha + * component only when available at the input RPF. +@@ -981,7 +990,8 @@ vsp1_video_streamon(struct file *file, void *fh, enum v4l2_buf_type type) + if (video->queue.owner && video->queue.owner != file->private_data) + return -EBUSY; + +- /* Get a pipeline for the video node and start streaming on it. No link ++ /* ++ * Get a pipeline for the video node and start streaming on it. No link + * touching an entity in the pipeline can be activated or deactivated + * once streaming is started. + */ +@@ -1001,7 +1011,8 @@ vsp1_video_streamon(struct file *file, void *fh, enum v4l2_buf_type type) + + mutex_unlock(&mdev->graph_mutex); + +- /* Verify that the configured format matches the output of the connected ++ /* ++ * Verify that the configured format matches the output of the connected + * subdev. + */ + ret = vsp1_video_verify_format(video); +diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c +index 052a83e2d489..25a2ed6e2e18 100644 +--- a/drivers/media/platform/vsp1/vsp1_wpf.c ++++ b/drivers/media/platform/vsp1/vsp1_wpf.c +@@ -88,12 +88,14 @@ static int wpf_init_controls(struct vsp1_rwpf *wpf) + /* Only WPF0 supports flipping. */ + num_flip_ctrls = 0; + } else if (vsp1->info->features & VSP1_HAS_WPF_HFLIP) { +- /* When horizontal flip is supported the WPF implements two ++ /* ++ * When horizontal flip is supported the WPF implements two + * controls (horizontal flip and vertical flip). + */ + num_flip_ctrls = 2; + } else if (vsp1->info->features & VSP1_HAS_WPF_VFLIP) { +- /* When only vertical flip is supported the WPF implements a ++ /* ++ * When only vertical flip is supported the WPF implements a + * single control (vertical flip). + */ + num_flip_ctrls = 1; +@@ -139,7 +141,8 @@ static int wpf_s_stream(struct v4l2_subdev *subdev, int enable) + if (enable) + return 0; + +- /* Write to registers directly when stopping the stream as there will be ++ /* ++ * Write to registers directly when stopping the stream as there will be + * no pipeline run to apply the display list. + */ + vsp1_write(vsp1, VI6_WPF_IRQ_ENB(wpf->entity.index), 0); +@@ -336,7 +339,8 @@ static void wpf_configure(struct vsp1_entity *entity, + + vsp1_dl_list_write(dl, VI6_WPF_WRBCK_CTRL, 0); + +- /* Sources. If the pipeline has a single input and BRU is not used, ++ /* ++ * Sources. If the pipeline has a single input and BRU is not used, + * configure it as the master layer. Otherwise configure all + * inputs as sub-layers and select the virtual RPF as the master + * layer. +-- +2.13.3 + diff --git a/patches.renesas/0145-media-v4l-vsp1-Disable-HSV-formats-on-Gen3-hardware.patch b/patches.renesas/0145-media-v4l-vsp1-Disable-HSV-formats-on-Gen3-hardware.patch new file mode 100644 index 00000000000000..8eb2d9724008d0 --- /dev/null +++ b/patches.renesas/0145-media-v4l-vsp1-Disable-HSV-formats-on-Gen3-hardware.patch @@ -0,0 +1,45 @@ +From b3de52df146afcab2c2fb0efcc83128484cc3b01 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 28 Feb 2017 19:44:55 -0300 +Subject: [PATCH 145/286] [media] v4l: vsp1: Disable HSV formats on Gen3 + hardware + +While all VSP instances can process HSV internally, on Gen3 hardware +reading or writing HSV24 or HSV32 from/to memory causes the device to +hang. Disable those pixel formats on Gen3 hardware. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 40ad34d8ebe7abd0d4df35a3364bf446e10f5c52) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_pipe.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c +index 3f1acf68dc6e..35364f594e19 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.c ++++ b/drivers/media/platform/vsp1/vsp1_pipe.c +@@ -157,9 +157,15 @@ const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1, + { + unsigned int i; + +- /* Special case, the VYUY format is supported on Gen2 only. */ +- if (vsp1->info->gen != 2 && fourcc == V4L2_PIX_FMT_VYUY) +- return NULL; ++ /* Special case, the VYUY and HSV formats are supported on Gen2 only. */ ++ if (vsp1->info->gen != 2) { ++ switch (fourcc) { ++ case V4L2_PIX_FMT_VYUY: ++ case V4L2_PIX_FMT_HSV24: ++ case V4L2_PIX_FMT_HSV32: ++ return NULL; ++ } ++ } + + for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) { + const struct vsp1_format_info *info = &vsp1_video_formats[i]; +-- +2.13.3 + diff --git a/patches.renesas/0146-media-v4l-vsp1-Fix-struct-vsp1_drm-documentation.patch b/patches.renesas/0146-media-v4l-vsp1-Fix-struct-vsp1_drm-documentation.patch new file mode 100644 index 00000000000000..aca0ef0b27db56 --- /dev/null +++ b/patches.renesas/0146-media-v4l-vsp1-Fix-struct-vsp1_drm-documentation.patch @@ -0,0 +1,34 @@ +From f526ade345cb37c71922c90f64b843f9b55a7acd Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Thu, 2 Mar 2017 07:12:22 -0300 +Subject: [PATCH 146/286] [media] v4l: vsp1: Fix struct vsp1_drm documentation + +The struct vsp1_drm references a member 'planes' which doesn't exist. +Correctly identify this documentation against the 'inputs' + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 1b8ce4060b02c9ebfcb75a9d91cf85fb1fb1bc1b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_drm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_drm.h b/drivers/media/platform/vsp1/vsp1_drm.h +index 9e28ab9254ba..c8d2f88fc483 100644 +--- a/drivers/media/platform/vsp1/vsp1_drm.h ++++ b/drivers/media/platform/vsp1/vsp1_drm.h +@@ -21,7 +21,7 @@ + * vsp1_drm - State for the API exposed to the DRM driver + * @pipe: the VSP1 pipeline used for display + * @num_inputs: number of active pipeline inputs at the beginning of an update +- * @planes: source crop rectangle, destination compose rectangle and z-order ++ * @inputs: source crop rectangle, destination compose rectangle and z-order + * position for every input + */ + struct vsp1_drm { +-- +2.13.3 + diff --git a/patches.renesas/0147-media-v4l-vsp1-Register-pipe-with-output-WPF.patch b/patches.renesas/0147-media-v4l-vsp1-Register-pipe-with-output-WPF.patch new file mode 100644 index 00000000000000..c4007034b6a674 --- /dev/null +++ b/patches.renesas/0147-media-v4l-vsp1-Register-pipe-with-output-WPF.patch @@ -0,0 +1,40 @@ +From 3db01168e75ecf212a106b0a3cd94f7d56bbb41a Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Mon, 27 Feb 2017 10:40:34 -0300 +Subject: [PATCH 147/286] [media] v4l: vsp1: Register pipe with output WPF + +The DRM object does not register the pipe with the WPF object. This is +used internally throughout the driver as a means of accessing the pipe. +As such this breaks operations which require access to the pipe from WPF +interrupts. + +Register the pipe inside the WPF object after it has been declared as +the output. + +Fixes: ff7e97c94d9f ("[media] v4l: vsp1: Store pipeline pointer in rwpf") + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 1531a208ed861e4bd287444f9466ffcf98383de2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_drm.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c +index 8cd88547da2c..6e161347088e 100644 +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -602,6 +602,7 @@ int vsp1_drm_init(struct vsp1_device *vsp1) + pipe->bru = &vsp1->bru->entity; + pipe->lif = &vsp1->lif->entity; + pipe->output = vsp1->wpf[0]; ++ pipe->output->pipe = pipe; + + return 0; + } +-- +2.13.3 + diff --git a/patches.renesas/0148-media-v4l-vsp1-wpf-Implement-rotation-support.patch b/patches.renesas/0148-media-v4l-vsp1-wpf-Implement-rotation-support.patch new file mode 100644 index 00000000000000..954942f7e588d2 --- /dev/null +++ b/patches.renesas/0148-media-v4l-vsp1-wpf-Implement-rotation-support.patch @@ -0,0 +1,403 @@ +From 04ea04ffd159659412bb8d7f22060c26675f6d05 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 20 Jun 2016 06:07:08 -0300 +Subject: [PATCH 148/286] [media] v4l: vsp1: wpf: Implement rotation support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some WPF instances, on Gen3 devices, can perform 90° rotation when +writing frames to memory. Implement support for this using the +V4L2_CID_ROTATE control. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 3e9a0e0bfafdf6c28c520d43fd64c5775d04662f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_rpf.c | 2 +- + drivers/media/platform/vsp1/vsp1_rwpf.c | 5 + + drivers/media/platform/vsp1/vsp1_rwpf.h | 7 +- + drivers/media/platform/vsp1/vsp1_video.c | 12 +- + drivers/media/platform/vsp1/vsp1_wpf.c | 205 +++++++++++++++++++++++-------- + 5 files changed, 177 insertions(+), 54 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_rpf.c b/drivers/media/platform/vsp1/vsp1_rpf.c +index f5a9a4c8c74d..8feddd59cf8d 100644 +--- a/drivers/media/platform/vsp1/vsp1_rpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rpf.c +@@ -106,7 +106,7 @@ static void rpf_configure(struct vsp1_entity *entity, + * of the pipeline. + */ + output = vsp1_entity_get_pad_format(wpf, wpf->config, +- RWPF_PAD_SOURCE); ++ RWPF_PAD_SINK); + + crop.width = pipe->partition.width * input_width + / output->width; +diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.c b/drivers/media/platform/vsp1/vsp1_rwpf.c +index 7d52c88a583e..cfd8f1904fa6 100644 +--- a/drivers/media/platform/vsp1/vsp1_rwpf.c ++++ b/drivers/media/platform/vsp1/vsp1_rwpf.c +@@ -121,6 +121,11 @@ static int vsp1_rwpf_set_format(struct v4l2_subdev *subdev, + RWPF_PAD_SOURCE); + *format = fmt->format; + ++ if (rwpf->flip.rotate) { ++ format->width = fmt->format.height; ++ format->height = fmt->format.width; ++ } ++ + done: + mutex_unlock(&rwpf->entity.lock); + return ret; +diff --git a/drivers/media/platform/vsp1/vsp1_rwpf.h b/drivers/media/platform/vsp1/vsp1_rwpf.h +index 1c98aff3da5d..58215a7ab631 100644 +--- a/drivers/media/platform/vsp1/vsp1_rwpf.h ++++ b/drivers/media/platform/vsp1/vsp1_rwpf.h +@@ -56,9 +56,14 @@ struct vsp1_rwpf { + + struct { + spinlock_t lock; +- struct v4l2_ctrl *ctrls[2]; ++ struct { ++ struct v4l2_ctrl *vflip; ++ struct v4l2_ctrl *hflip; ++ struct v4l2_ctrl *rotate; ++ } ctrls; + unsigned int pending; + unsigned int active; ++ bool rotate; + } flip; + + struct vsp1_rwpf_memory mem; +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 620beb21dd14..79f48a025546 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -187,9 +187,13 @@ static void vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe) + struct vsp1_entity *entity; + unsigned int div_size; + ++ /* ++ * Partitions are computed on the size before rotation, use the format ++ * at the WPF sink. ++ */ + format = vsp1_entity_get_pad_format(&pipe->output->entity, + pipe->output->entity.config, +- RWPF_PAD_SOURCE); ++ RWPF_PAD_SINK); + div_size = format->width; + + /* Gen2 hardware doesn't require image partitioning. */ +@@ -229,9 +233,13 @@ static struct v4l2_rect vsp1_video_partition(struct vsp1_pipeline *pipe, + struct v4l2_rect partition; + unsigned int modulus; + ++ /* ++ * Partitions are computed on the size before rotation, use the format ++ * at the WPF sink. ++ */ + format = vsp1_entity_get_pad_format(&pipe->output->entity, + pipe->output->entity.config, +- RWPF_PAD_SOURCE); ++ RWPF_PAD_SINK); + + /* A single partition simply processes the output size in full. */ + if (pipe->partitions <= 1) { +diff --git a/drivers/media/platform/vsp1/vsp1_wpf.c b/drivers/media/platform/vsp1/vsp1_wpf.c +index 25a2ed6e2e18..32df109b119f 100644 +--- a/drivers/media/platform/vsp1/vsp1_wpf.c ++++ b/drivers/media/platform/vsp1/vsp1_wpf.c +@@ -43,32 +43,90 @@ static inline void vsp1_wpf_write(struct vsp1_rwpf *wpf, + enum wpf_flip_ctrl { + WPF_CTRL_VFLIP = 0, + WPF_CTRL_HFLIP = 1, +- WPF_CTRL_MAX, + }; + ++static int vsp1_wpf_set_rotation(struct vsp1_rwpf *wpf, unsigned int rotation) ++{ ++ struct vsp1_video *video = wpf->video; ++ struct v4l2_mbus_framefmt *sink_format; ++ struct v4l2_mbus_framefmt *source_format; ++ bool rotate; ++ int ret = 0; ++ ++ /* ++ * Only consider the 0°/180° from/to 90°/270° modifications, the rest ++ * is taken care of by the flipping configuration. ++ */ ++ rotate = rotation == 90 || rotation == 270; ++ if (rotate == wpf->flip.rotate) ++ return 0; ++ ++ /* Changing rotation isn't allowed when buffers are allocated. */ ++ mutex_lock(&video->lock); ++ ++ if (vb2_is_busy(&video->queue)) { ++ ret = -EBUSY; ++ goto done; ++ } ++ ++ sink_format = vsp1_entity_get_pad_format(&wpf->entity, ++ wpf->entity.config, ++ RWPF_PAD_SINK); ++ source_format = vsp1_entity_get_pad_format(&wpf->entity, ++ wpf->entity.config, ++ RWPF_PAD_SOURCE); ++ ++ mutex_lock(&wpf->entity.lock); ++ ++ if (rotate) { ++ source_format->width = sink_format->height; ++ source_format->height = sink_format->width; ++ } else { ++ source_format->width = sink_format->width; ++ source_format->height = sink_format->height; ++ } ++ ++ wpf->flip.rotate = rotate; ++ ++ mutex_unlock(&wpf->entity.lock); ++ ++done: ++ mutex_unlock(&video->lock); ++ return ret; ++} ++ + static int vsp1_wpf_s_ctrl(struct v4l2_ctrl *ctrl) + { + struct vsp1_rwpf *wpf = + container_of(ctrl->handler, struct vsp1_rwpf, ctrls); +- unsigned int i; ++ unsigned int rotation; + u32 flip = 0; ++ int ret; + +- switch (ctrl->id) { +- case V4L2_CID_HFLIP: +- case V4L2_CID_VFLIP: +- for (i = 0; i < WPF_CTRL_MAX; ++i) { +- if (wpf->flip.ctrls[i]) +- flip |= wpf->flip.ctrls[i]->val ? BIT(i) : 0; +- } ++ /* Update the rotation. */ ++ rotation = wpf->flip.ctrls.rotate ? wpf->flip.ctrls.rotate->val : 0; ++ ret = vsp1_wpf_set_rotation(wpf, rotation); ++ if (ret < 0) ++ return ret; + +- spin_lock_irq(&wpf->flip.lock); +- wpf->flip.pending = flip; +- spin_unlock_irq(&wpf->flip.lock); +- break; ++ /* ++ * Compute the flip value resulting from all three controls, with ++ * rotation by 180° flipping the image in both directions. Store the ++ * result in the pending flip field for the next frame that will be ++ * processed. ++ */ ++ if (wpf->flip.ctrls.vflip->val) ++ flip |= BIT(WPF_CTRL_VFLIP); + +- default: +- return -EINVAL; +- } ++ if (wpf->flip.ctrls.hflip && wpf->flip.ctrls.hflip->val) ++ flip |= BIT(WPF_CTRL_HFLIP); ++ ++ if (rotation == 180 || rotation == 270) ++ flip ^= BIT(WPF_CTRL_VFLIP) | BIT(WPF_CTRL_HFLIP); ++ ++ spin_lock_irq(&wpf->flip.lock); ++ wpf->flip.pending = flip; ++ spin_unlock_irq(&wpf->flip.lock); + + return 0; + } +@@ -89,10 +147,10 @@ static int wpf_init_controls(struct vsp1_rwpf *wpf) + num_flip_ctrls = 0; + } else if (vsp1->info->features & VSP1_HAS_WPF_HFLIP) { + /* +- * When horizontal flip is supported the WPF implements two +- * controls (horizontal flip and vertical flip). ++ * When horizontal flip is supported the WPF implements three ++ * controls (horizontal flip, vertical flip and rotation). + */ +- num_flip_ctrls = 2; ++ num_flip_ctrls = 3; + } else if (vsp1->info->features & VSP1_HAS_WPF_VFLIP) { + /* + * When only vertical flip is supported the WPF implements a +@@ -107,17 +165,19 @@ static int wpf_init_controls(struct vsp1_rwpf *wpf) + vsp1_rwpf_init_ctrls(wpf, num_flip_ctrls); + + if (num_flip_ctrls >= 1) { +- wpf->flip.ctrls[WPF_CTRL_VFLIP] = ++ wpf->flip.ctrls.vflip = + v4l2_ctrl_new_std(&wpf->ctrls, &vsp1_wpf_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + } + +- if (num_flip_ctrls == 2) { +- wpf->flip.ctrls[WPF_CTRL_HFLIP] = ++ if (num_flip_ctrls == 3) { ++ wpf->flip.ctrls.hflip = + v4l2_ctrl_new_std(&wpf->ctrls, &vsp1_wpf_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); +- +- v4l2_ctrl_cluster(2, wpf->flip.ctrls); ++ wpf->flip.ctrls.rotate = ++ v4l2_ctrl_new_std(&wpf->ctrls, &vsp1_wpf_ctrl_ops, ++ V4L2_CID_ROTATE, 0, 270, 90, 0); ++ v4l2_ctrl_cluster(3, &wpf->flip.ctrls.vflip); + } + + if (wpf->ctrls.error) { +@@ -222,8 +282,8 @@ static void wpf_configure(struct vsp1_entity *entity, + const struct vsp1_format_info *fmtinfo = wpf->fmtinfo; + struct vsp1_rwpf_memory mem = wpf->mem; + unsigned int flip = wpf->flip.active; +- unsigned int width = source_format->width; +- unsigned int height = source_format->height; ++ unsigned int width = sink_format->width; ++ unsigned int height = sink_format->height; + unsigned int offset; + + /* +@@ -246,45 +306,78 @@ static void wpf_configure(struct vsp1_entity *entity, + /* + * Update the memory offsets based on flipping configuration. + * The destination addresses point to the locations where the +- * VSP starts writing to memory, which can be different corners +- * of the image depending on vertical flipping. ++ * VSP starts writing to memory, which can be any corner of the ++ * image depending on the combination of flipping and rotation. + */ +- if (pipe->partitions > 1) { +- const struct vsp1_format_info *fmtinfo = wpf->fmtinfo; + +- /* +- * Horizontal flipping is handled through a line buffer +- * and doesn't modify the start address, but still needs +- * to be handled when image partitioning is in effect to +- * order the partitions correctly. +- */ +- if (flip & BIT(WPF_CTRL_HFLIP)) +- offset = format->width - pipe->partition.left +- - pipe->partition.width; ++ /* ++ * First take the partition left coordinate into account. ++ * Compute the offset to order the partitions correctly on the ++ * output based on whether flipping is enabled. Consider ++ * horizontal flipping when rotation is disabled but vertical ++ * flipping when rotation is enabled, as rotating the image ++ * switches the horizontal and vertical directions. The offset ++ * is applied horizontally or vertically accordingly. ++ */ ++ if (flip & BIT(WPF_CTRL_HFLIP) && !wpf->flip.rotate) ++ offset = format->width - pipe->partition.left ++ - pipe->partition.width; ++ else if (flip & BIT(WPF_CTRL_VFLIP) && wpf->flip.rotate) ++ offset = format->height - pipe->partition.left ++ - pipe->partition.width; ++ else ++ offset = pipe->partition.left; ++ ++ for (i = 0; i < format->num_planes; ++i) { ++ unsigned int hsub = i > 0 ? fmtinfo->hsub : 1; ++ unsigned int vsub = i > 0 ? fmtinfo->vsub : 1; ++ ++ if (wpf->flip.rotate) ++ mem.addr[i] += offset / vsub ++ * format->plane_fmt[i].bytesperline; + else +- offset = pipe->partition.left; +- +- mem.addr[0] += offset * fmtinfo->bpp[0] / 8; +- if (format->num_planes > 1) { +- mem.addr[1] += offset / fmtinfo->hsub +- * fmtinfo->bpp[1] / 8; +- mem.addr[2] += offset / fmtinfo->hsub +- * fmtinfo->bpp[2] / 8; +- } ++ mem.addr[i] += offset / hsub ++ * fmtinfo->bpp[i] / 8; + } + + if (flip & BIT(WPF_CTRL_VFLIP)) { +- mem.addr[0] += (format->height - 1) ++ /* ++ * When rotating the output (after rotation) image ++ * height is equal to the partition width (before ++ * rotation). Otherwise it is equal to the output ++ * image height. ++ */ ++ if (wpf->flip.rotate) ++ height = pipe->partition.width; ++ else ++ height = format->height; ++ ++ mem.addr[0] += (height - 1) + * format->plane_fmt[0].bytesperline; + + if (format->num_planes > 1) { +- offset = (format->height / wpf->fmtinfo->vsub - 1) ++ offset = (height / fmtinfo->vsub - 1) + * format->plane_fmt[1].bytesperline; + mem.addr[1] += offset; + mem.addr[2] += offset; + } + } + ++ if (wpf->flip.rotate && !(flip & BIT(WPF_CTRL_HFLIP))) { ++ unsigned int hoffset = max(0, (int)format->width - 16); ++ ++ /* ++ * Compute the output coordinate. The partition ++ * horizontal (left) offset becomes a vertical offset. ++ */ ++ for (i = 0; i < format->num_planes; ++i) { ++ unsigned int hsub = i > 0 ? fmtinfo->hsub : 1; ++ ++ mem.addr[i] += hoffset / hsub ++ * fmtinfo->bpp[i] / 8; ++ } ++ } ++ + /* + * On Gen3 hardware the SPUVS bit has no effect on 3-planar + * formats. Swap the U and V planes manually in that case. +@@ -306,6 +399,9 @@ static void wpf_configure(struct vsp1_entity *entity, + + outfmt = fmtinfo->hwfmt << VI6_WPF_OUTFMT_WRFMT_SHIFT; + ++ if (wpf->flip.rotate) ++ outfmt |= VI6_WPF_OUTFMT_ROT; ++ + if (fmtinfo->alpha) + outfmt |= VI6_WPF_OUTFMT_PXA; + if (fmtinfo->swap_yc) +@@ -367,9 +463,18 @@ static void wpf_configure(struct vsp1_entity *entity, + VI6_WFP_IRQ_ENB_DFEE); + } + ++static unsigned int wpf_max_width(struct vsp1_entity *entity, ++ struct vsp1_pipeline *pipe) ++{ ++ struct vsp1_rwpf *wpf = to_rwpf(&entity->subdev); ++ ++ return wpf->flip.rotate ? 256 : wpf->max_width; ++} ++ + static const struct vsp1_entity_operations wpf_entity_ops = { + .destroy = vsp1_wpf_destroy, + .configure = wpf_configure, ++ .max_width = wpf_max_width, + }; + + /* ----------------------------------------------------------------------------- +-- +2.13.3 + diff --git a/patches.renesas/0149-ASoC-wm8978-Add-OF-device-ID-table.patch b/patches.renesas/0149-ASoC-wm8978-Add-OF-device-ID-table.patch new file mode 100644 index 00000000000000..bbef1e5d719c77 --- /dev/null +++ b/patches.renesas/0149-ASoC-wm8978-Add-OF-device-ID-table.patch @@ -0,0 +1,58 @@ +From b4386b538ebb1ae0f5f8d7e5027df0e3c26562f7 Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas <javier@osg.samsung.com> +Date: Tue, 4 Apr 2017 15:26:29 -0400 +Subject: [PATCH 149/286] ASoC: wm8978: Add OF device ID table + +The driver doesn't have a struct of_device_id table but supported devices +are registered via Device Trees. This is working on the assumption that a +I2C device registered via OF will always match a legacy I2C device ID and +that the MODALIAS reported will always be of the form i2c:<device>. + +But this could change in the future so the correct approach is to have an +OF device ID table if the devices are registered via OF. + +Before this patch: + +$ modinfo sound/soc/codecs/snd-soc-wm8978.ko | grep alias +alias: i2c:wm8978 + +After this patch: + +$ modinfo sound/soc/codecs/snd-soc-wm8978.ko | grep alias +alias: i2c:wm8978 +alias: of:N*T*Cwlf,wm8978C* +alias: of:N*T*Cwlf,wm8978 + +Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> +Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 5cf015d9cb02c360582b624497b0a1716881cf28) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + sound/soc/codecs/wm8978.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c +index 90b2d418ef60..cf761e2d7546 100644 +--- a/sound/soc/codecs/wm8978.c ++++ b/sound/soc/codecs/wm8978.c +@@ -1071,9 +1071,16 @@ static const struct i2c_device_id wm8978_i2c_id[] = { + }; + MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id); + ++static const struct of_device_id wm8978_of_match[] = { ++ { .compatible = "wlf,wm8978", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, wm8978_of_match); ++ + static struct i2c_driver wm8978_i2c_driver = { + .driver = { + .name = "wm8978", ++ .of_match_table = wm8978_of_match, + }, + .probe = wm8978_i2c_probe, + .remove = wm8978_i2c_remove, +-- +2.13.3 + diff --git a/patches.renesas/0150-clk-renesas-r8a7795-Add-IMR-clocks.patch b/patches.renesas/0150-clk-renesas-r8a7795-Add-IMR-clocks.patch new file mode 100644 index 00000000000000..c7e30bc0201d26 --- /dev/null +++ b/patches.renesas/0150-clk-renesas-r8a7795-Add-IMR-clocks.patch @@ -0,0 +1,37 @@ +From 30e3de305ef9e331dbfaf2c79dbec3865aaa4553 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 14 Feb 2017 00:06:04 +0300 +Subject: [PATCH 150/286] clk: renesas: r8a7795: Add IMR clocks + +Add the IMR[0-3] clocks to the R8A7795 CPG/MSSR driver. + +Based on the original (and large) patch by Konstantin Kozhevnikov +<Konstantin.Kozhevnikov@cogentembedded.com>. + +Signed-off-by: Konstantin Kozhevnikov <Konstantin.Kozhevnikov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 7d0a7c7bdf7f849ff864a539f1c0c20b8a053f2e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index bfffdb00df97..2add8218e0f7 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -208,6 +208,10 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("vin0", 811, R8A7795_CLK_S2D1), + DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), + DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), ++ DEF_MOD("imr3", 820, R8A7795_CLK_S2D1), ++ DEF_MOD("imr2", 821, R8A7795_CLK_S2D1), ++ DEF_MOD("imr1", 822, R8A7795_CLK_S2D1), ++ DEF_MOD("imr0", 823, R8A7795_CLK_S2D1), + DEF_MOD("gpio7", 905, R8A7795_CLK_CP), + DEF_MOD("gpio6", 906, R8A7795_CLK_CP), + DEF_MOD("gpio5", 907, R8A7795_CLK_CP), +-- +2.13.3 + diff --git a/patches.renesas/0151-clk-renesas-r8a7796-Add-IMR-clocks.patch b/patches.renesas/0151-clk-renesas-r8a7796-Add-IMR-clocks.patch new file mode 100644 index 00000000000000..7db0e0d25f9cbb --- /dev/null +++ b/patches.renesas/0151-clk-renesas-r8a7796-Add-IMR-clocks.patch @@ -0,0 +1,33 @@ +From 5b49a3b7db3995ccfd0e4d3ecf0f76f895a13c47 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Sun, 19 Feb 2017 00:39:26 +0300 +Subject: [PATCH 151/286] clk: renesas: r8a7796: Add IMR clocks + +Add the IMR[0-1] clocks to the R8A7796 CPG/MSSR driver. + +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +[geert: Correct parent clocks] +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> + +(cherry picked from commit 6c8a9312946374947287ac1bd3b94aba850a5d1f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c +index 11e084a56b0d..12a23c18bc1e 100644 +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), + DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), + DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), ++ DEF_MOD("imr1", 822, R8A7796_CLK_S0D2), ++ DEF_MOD("imr0", 823, R8A7796_CLK_S0D2), + DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), + DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), + DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), +-- +2.13.3 + diff --git a/patches.renesas/0152-clk-renesas-r8a7795-Correct-parent-clock-and-sort-or.patch b/patches.renesas/0152-clk-renesas-r8a7795-Correct-parent-clock-and-sort-or.patch new file mode 100644 index 00000000000000..4012d850113adf --- /dev/null +++ b/patches.renesas/0152-clk-renesas-r8a7795-Correct-parent-clock-and-sort-or.patch @@ -0,0 +1,36 @@ +From 4fa7e89f7563e5a33ec36b57f26b36ecbbe2209d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Feb 2017 17:31:59 +0100 +Subject: [PATCH 152/286] clk: renesas: r8a7795: Correct parent clock and sort + order for Audio DMACs + +The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which +maps to S3D1 on R-Car H3 ES1.x. +All module clocks must be sorted by clock ID. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> +(cherry picked from commit a843ed3f6c3e856f9091b042c6b4ed34c02a3187) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index 2add8218e0f7..cde470ce81e4 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("rwdt0", 402, R8A7795_CLK_R), + DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), + DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), +- DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), +- DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), ++ DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), ++ DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), + DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), + DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), +-- +2.13.3 + diff --git a/patches.renesas/0153-clk-renesas-r8a7795-Correct-name-of-watchdog-clock.patch b/patches.renesas/0153-clk-renesas-r8a7795-Correct-name-of-watchdog-clock.patch new file mode 100644 index 00000000000000..793d1e26901f75 --- /dev/null +++ b/patches.renesas/0153-clk-renesas-r8a7795-Correct-name-of-watchdog-clock.patch @@ -0,0 +1,30 @@ +From e52a52c5f5d2af21ae20bd5660dbba54bc94ff01 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Feb 2017 17:17:31 +0100 +Subject: [PATCH 153/286] clk: renesas: r8a7795: Correct name of watchdog clock + +There's only a single watchdog clock, and it's named "rwdt". + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 2122b56d30e4fb25b383f137e83e6b901e5b05ae) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index cde470ce81e4..4e176e7f958b 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -139,7 +139,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), +- DEF_MOD("rwdt0", 402, R8A7795_CLK_R), ++ DEF_MOD("rwdt", 402, R8A7795_CLK_R), + DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), + DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), + DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), +-- +2.13.3 + diff --git a/patches.renesas/0154-clk-renesas-r8a7796-Correct-name-of-watchdog-clock.patch b/patches.renesas/0154-clk-renesas-r8a7796-Correct-name-of-watchdog-clock.patch new file mode 100644 index 00000000000000..7853df1e117b8e --- /dev/null +++ b/patches.renesas/0154-clk-renesas-r8a7796-Correct-name-of-watchdog-clock.patch @@ -0,0 +1,30 @@ +From 2ac5acd948c5dcbf1ef21d6df12c9812160d6cd3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Feb 2017 17:18:08 +0100 +Subject: [PATCH 154/286] clk: renesas: r8a7796: Correct name of watchdog clock + +There's only a single watchdog clock, and it's named "rwdt". + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 89aa58a3951bcf242c7755075a7429d0ed6640de) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c +index 12a23c18bc1e..55003194a256 100644 +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -135,7 +135,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), + DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), + DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), +- DEF_MOD("rwdt0", 402, R8A7796_CLK_R), ++ DEF_MOD("rwdt", 402, R8A7796_CLK_R), + DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), + DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), +-- +2.13.3 + diff --git a/patches.renesas/0155-clk-renesas-r8a7795-Reformat-core-clock-table.patch b/patches.renesas/0155-clk-renesas-r8a7795-Reformat-core-clock-table.patch new file mode 100644 index 00000000000000..e91fcf0c27b21f --- /dev/null +++ b/patches.renesas/0155-clk-renesas-r8a7795-Reformat-core-clock-table.patch @@ -0,0 +1,65 @@ +From e42c0d2b6b6ef37620eeec204862585ea50f070b Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 10 Nov 2016 13:16:57 +0100 +Subject: [PATCH 155/286] clk: renesas: r8a7795: Reformat core clock table + +For easier comparison with other clock drivers. +No functional changes. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 3c969cec16176e98f9d8c976c163d2bb519c7c87) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index 4e176e7f958b..608178618da8 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -53,8 +53,8 @@ enum clk_ids { + + static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { + /* External Clock Inputs */ +- DEF_INPUT("extal", CLK_EXTAL), +- DEF_INPUT("extalr", CLK_EXTALR), ++ DEF_INPUT("extal", CLK_EXTAL), ++ DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), +@@ -89,23 +89,23 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { + DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), + +- DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x0074), +- DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x0078), +- DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x0268), +- DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x026c), ++ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), ++ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), ++ DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), ++ DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), + +- DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), +- DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), + DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), ++ DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), ++ DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), + +- DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), ++ DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + +- DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), ++ DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), + }; + + static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { +-- +2.13.3 + diff --git a/patches.renesas/0156-clk-renesas-r8a7796-Reformat-core-clock-table.patch b/patches.renesas/0156-clk-renesas-r8a7796-Reformat-core-clock-table.patch new file mode 100644 index 00000000000000..55540b60158e20 --- /dev/null +++ b/patches.renesas/0156-clk-renesas-r8a7796-Reformat-core-clock-table.patch @@ -0,0 +1,48 @@ +From b8b1b09ceff9eecfbc0a209c40d46467af8eaa16 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 10 Nov 2016 13:18:25 +0100 +Subject: [PATCH 156/286] clk: renesas: r8a7796: Reformat core clock table + +For easier comparison with other clock drivers. +No functional changes. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit c013fc7d23ca5b29f0cdc37d58b2466ead4fd5f6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c +index 55003194a256..f7787101b8d0 100644 +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -54,8 +54,8 @@ enum clk_ids { + + static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { + /* External Clock Inputs */ +- DEF_INPUT("extal", CLK_EXTAL), +- DEF_INPUT("extalr", CLK_EXTALR), ++ DEF_INPUT("extal", CLK_EXTAL), ++ DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), +@@ -95,10 +95,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { + DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), + DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), + +- DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x0074), +- DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x0078), +- DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x0268), +- DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x026c), ++ DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), ++ DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), ++ DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), ++ DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), + + DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), +-- +2.13.3 + diff --git a/patches.renesas/0157-clk-renesas-rcar-gen3-cpg-Pass-mode-pins-to-rcar_gen.patch b/patches.renesas/0157-clk-renesas-rcar-gen3-cpg-Pass-mode-pins-to-rcar_gen.patch new file mode 100644 index 00000000000000..813a0cb7e34944 --- /dev/null +++ b/patches.renesas/0157-clk-renesas-rcar-gen3-cpg-Pass-mode-pins-to-rcar_gen.patch @@ -0,0 +1,85 @@ +From d80b1edc3d1787a07007fb2842be0462504dad22 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 11:36:33 +0100 +Subject: [PATCH 157/286] clk: renesas: rcar-gen3-cpg: Pass mode pins to + rcar_gen3_cpg_init() + +Pass the mode pin states from the SoC-specific CPG/MSSR driver to the +R-Car Gen3 CPG driver core, as their state will be needed to make some +core clock configuration decisions. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5f3a432a44b135db002d22446827cfa061fc0bfb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +- + drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +- + drivers/clk/renesas/rcar-gen3-cpg.c | 4 +++- + drivers/clk/renesas/rcar-gen3-cpg.h | 2 +- + 4 files changed, 6 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index 608178618da8..4699f416e275 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -330,7 +330,7 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev) + return -EINVAL; + } + +- return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); ++ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); + } + + const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { +diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c +index f7787101b8d0..9d114b31b073 100644 +--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c +@@ -273,7 +273,7 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev) + return -EINVAL; + } + +- return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); ++ return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); + } + + const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = { +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c +index 742f6dc7c156..d395bb8c22f5 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.c ++++ b/drivers/clk/renesas/rcar-gen3-cpg.c +@@ -247,6 +247,7 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, + + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; + static unsigned int cpg_clk_extalr __initdata; ++static u32 cpg_mode __initdata; + + struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, +@@ -334,9 +335,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + } + + int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, +- unsigned int clk_extalr) ++ unsigned int clk_extalr, u32 mode) + { + cpg_pll_config = config; + cpg_clk_extalr = clk_extalr; ++ cpg_mode = mode; + return 0; + } +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h +index f788f481dd42..073be54b5d03 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.h ++++ b/drivers/clk/renesas/rcar-gen3-cpg.h +@@ -37,6 +37,6 @@ struct clk *rcar_gen3_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base); + int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, +- unsigned int clk_extalr); ++ unsigned int clk_extalr, u32 mode); + + #endif +-- +2.13.3 + diff --git a/patches.renesas/0158-clk-renesas-rcar-gen3-Add-workaround-for-PLL0-2-4-er.patch b/patches.renesas/0158-clk-renesas-rcar-gen3-Add-workaround-for-PLL0-2-4-er.patch new file mode 100644 index 00000000000000..33a0090cf2161f --- /dev/null +++ b/patches.renesas/0158-clk-renesas-rcar-gen3-Add-workaround-for-PLL0-2-4-er.patch @@ -0,0 +1,94 @@ +From 268d44e5cee91838fc6558d9ac21ee8d5a93222a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 11:46:10 +0100 +Subject: [PATCH 158/286] clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 + errata on H3 ES1.0 + +Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and +PLL4 clock frequencies are off by a factor of two. + +Inspired by a patch by Dien Pham in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Dien Pham <dien.pham.ry@renesas.com> +(cherry picked from commit cecbe87d73006cb321dec79b349e3fefd1a80962) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/rcar-gen3-cpg.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c +index d395bb8c22f5..e5247e3dc897 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.c ++++ b/drivers/clk/renesas/rcar-gen3-cpg.c +@@ -20,6 +20,7 @@ + #include <linux/init.h> + #include <linux/io.h> + #include <linux/slab.h> ++#include <linux/sys_soc.h> + + #include "renesas-cpg-mssr.h" + #include "rcar-gen3-cpg.h" +@@ -248,6 +249,17 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; + static unsigned int cpg_clk_extalr __initdata; + static u32 cpg_mode __initdata; ++static u32 cpg_quirks __initdata; ++ ++#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ ++ ++static const struct soc_device_attribute cpg_quirks_match[] __initconst = { ++ { ++ .soc_id = "r8a7795", .revision = "ES1.0", ++ .data = (void *)PLL_ERRATA, ++ }, ++ { /* sentinel */ } ++}; + + struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, +@@ -276,6 +288,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + */ + value = readl(base + CPG_PLL0CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; ++ if (cpg_quirks & PLL_ERRATA) ++ mult *= 2; + break; + + case CLK_TYPE_GEN3_PLL1: +@@ -291,6 +305,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + */ + value = readl(base + CPG_PLL2CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; ++ if (cpg_quirks & PLL_ERRATA) ++ mult *= 2; + break; + + case CLK_TYPE_GEN3_PLL3: +@@ -306,6 +322,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + */ + value = readl(base + CPG_PLL4CR); + mult = (((value >> 24) & 0x7f) + 1) * 2; ++ if (cpg_quirks & PLL_ERRATA) ++ mult *= 2; + break; + + case CLK_TYPE_GEN3_SD: +@@ -337,8 +355,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, + unsigned int clk_extalr, u32 mode) + { ++ const struct soc_device_attribute *attr; ++ + cpg_pll_config = config; + cpg_clk_extalr = clk_extalr; + cpg_mode = mode; ++ attr = soc_device_match(cpg_quirks_match); ++ if (attr) ++ cpg_quirks = (uintptr_t)attr->data; ++ pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); + return 0; + } +-- +2.13.3 + diff --git a/patches.renesas/0159-clk-renesas-cpg-mssr-Add-support-for-fixing-up-clock.patch b/patches.renesas/0159-clk-renesas-cpg-mssr-Add-support-for-fixing-up-clock.patch new file mode 100644 index 00000000000000..6d79b6824b2d23 --- /dev/null +++ b/patches.renesas/0159-clk-renesas-cpg-mssr-Add-support-for-fixing-up-clock.patch @@ -0,0 +1,135 @@ +From 8cffac2a1d989312132298af4df07f5685b89c1e Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 29 Sep 2016 14:47:58 +0200 +Subject: [PATCH 159/286] clk: renesas: cpg-mssr: Add support for fixing up + clock tables + +The same SoC may have different clocks and/or module clock parents, +depending on SoC revision. One option is to use different sets of clock +tables for each SoC revision. However, if the differences are small, it +is much more space-efficient to have a single set of clock tables, and +fix those up at runtime instead. + +Hence provide three helpers: + - Two helpers to NULLify core and module clocks that do not exist on + some revisions (NULLified clocks are skipped during the registration + phase), + - One helper to reparent module clocks that have different clock + parents. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 48d0341e41870bcfc42206d38e00a6b1c2fea929) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/renesas-cpg-mssr.c | 50 ++++++++++++++++++++++++++++++++++ + drivers/clk/renesas/renesas-cpg-mssr.h | 22 +++++++++++++++ + 2 files changed, 72 insertions(+) + +diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c +index eadcbd43ff88..99eeec6f24ec 100644 +--- a/drivers/clk/renesas/renesas-cpg-mssr.c ++++ b/drivers/clk/renesas/renesas-cpg-mssr.c +@@ -265,6 +265,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, + WARN_DEBUG(id >= priv->num_core_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + ++ if (!core->name) { ++ /* Skip NULLified clock */ ++ return; ++ } ++ + switch (core->type) { + case CLK_TYPE_IN: + clk = of_clk_get_by_name(priv->dev->of_node, core->name); +@@ -335,6 +340,11 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, + WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); + WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); + ++ if (!mod->name) { ++ /* Skip NULLified clock */ ++ return; ++ } ++ + parent = priv->clks[mod->parent]; + if (IS_ERR(parent)) { + clk = parent; +@@ -734,5 +744,45 @@ static int __init cpg_mssr_init(void) + + subsys_initcall(cpg_mssr_init); + ++void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks, ++ unsigned int num_core_clks, ++ unsigned int first_clk, ++ unsigned int last_clk) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < num_core_clks; i++) ++ if (core_clks[i].id >= first_clk && ++ core_clks[i].id <= last_clk) ++ core_clks[i].name = NULL; ++} ++ ++void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks, ++ unsigned int num_mod_clks, ++ const unsigned int *clks, unsigned int n) ++{ ++ unsigned int i, j; ++ ++ for (i = 0, j = 0; i < num_mod_clks && j < n; i++) ++ if (mod_clks[i].id == clks[j]) { ++ mod_clks[i].name = NULL; ++ j++; ++ } ++} ++ ++void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks, ++ unsigned int num_mod_clks, ++ const struct mssr_mod_reparent *clks, ++ unsigned int n) ++{ ++ unsigned int i, j; ++ ++ for (i = 0, j = 0; i < num_mod_clks && j < n; i++) ++ if (mod_clks[i].id == clks[j].clk) { ++ mod_clks[i].parent = clks[j].parent; ++ j++; ++ } ++} ++ + MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); + MODULE_LICENSE("GPL v2"); +diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h +index 4bb7a80c6469..148f4f0aa2a4 100644 +--- a/drivers/clk/renesas/renesas-cpg-mssr.h ++++ b/drivers/clk/renesas/renesas-cpg-mssr.h +@@ -134,4 +134,26 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; + extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; + extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; + extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; ++ ++ ++ /* ++ * Helpers for fixing up clock tables depending on SoC revision ++ */ ++ ++struct mssr_mod_reparent { ++ unsigned int clk, parent; ++}; ++ ++ ++extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks, ++ unsigned int num_core_clks, ++ unsigned int first_clk, ++ unsigned int last_clk); ++extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks, ++ unsigned int num_mod_clks, ++ const unsigned int *clks, unsigned int n); ++extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks, ++ unsigned int num_mod_clks, ++ const struct mssr_mod_reparent *clks, ++ unsigned int n); + #endif +-- +2.13.3 + diff --git a/patches.renesas/0160-clk-renesas-r8a7795-Add-support-for-R-Car-H3-ES2.0.patch b/patches.renesas/0160-clk-renesas-r8a7795-Add-support-for-R-Car-H3-ES2.0.patch new file mode 100644 index 00000000000000..c80011e88e678c --- /dev/null +++ b/patches.renesas/0160-clk-renesas-r8a7795-Add-support-for-R-Car-H3-ES2.0.patch @@ -0,0 +1,336 @@ +From 512a0c283100056561b9aea4c581c1390723a9ff Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 29 Sep 2016 14:36:11 +0200 +Subject: [PATCH 160/286] clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 + +The Clock Pulse Generator / Module Standby and Software Reset module in +R-Car H3 ES2.0 differs from ES1.x in the following areas: + - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12), + - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR, + SYS-DMAC, VIN, VSPB, VSPI, + - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2, + USB3-IF1, VSPD3, VSPI2, + - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1. + +The goal is twofold: + 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary + for now, + 2. Make it clear which code supports ES1.x, so it can easily be + identified and removed later, when production SoCs are deemed + ubiquitous. + +This is achieved by: + - Updating the clock tables for the latest revision (ES2.0), but not + removing clocks that only exist on earlier revisions (ES1.x), + - Detecting the SoC revision at runtime using the new soc_device_match() + API, and fixing up the clocks tables to match the actual SoC + revision, by: + - NULLifying core and module clocks of modules that do not exist, + - Reparenting module clocks that have a different parent on ES1.x. + +Based on R-Car Gen3 Hardware User's Manual rev. 0.53E. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5573d194128b47334e3edb2db87cb471449d445a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/r8a7795-cpg-mssr.c | 201 +++++++++++++++++++++++++-------- + 1 file changed, 151 insertions(+), 50 deletions(-) + +diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c +index 4699f416e275..eaa98b488f01 100644 +--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c ++++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c +@@ -16,6 +16,7 @@ + #include <linux/init.h> + #include <linux/kernel.h> + #include <linux/soc/renesas/rcar-rst.h> ++#include <linux/sys_soc.h> + + #include <dt-bindings/clock/r8a7795-cpg-mssr.h> + +@@ -24,7 +25,7 @@ + + enum clk_ids { + /* Core Clock Outputs exported to DT */ +- LAST_DT_CORE_CLK = R8A7795_CLK_OSC, ++ LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, + + /* External Input Clocks */ + CLK_EXTAL, +@@ -51,7 +52,7 @@ enum clk_ids { + MOD_CLK_BASE + }; + +-static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { ++static struct cpg_core_clk r8a7795_core_clks[] __initdata = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), +@@ -78,7 +79,12 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { + DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), ++ DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), ++ DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), + DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), ++ DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), ++ DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), ++ DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), + DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), +@@ -108,10 +114,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { + DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), + }; + +-static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { +- DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), +- DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1), +- DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1), ++static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { ++ DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), ++ DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), + DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), + DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), + DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), +@@ -121,9 +127,9 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), + DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), + DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), +- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), +- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), +- DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), ++ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), ++ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), ++ DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), + DEF_MOD("cmt3", 300, R8A7795_CLK_R), + DEF_MOD("cmt2", 301, R8A7795_CLK_R), + DEF_MOD("cmt1", 302, R8A7795_CLK_R), +@@ -135,15 +141,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), + DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), + DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), +- DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), ++ DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ + DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), + DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), + DEF_MOD("rwdt", 402, R8A7795_CLK_R), + DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), + DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), +- DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), +- DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), ++ DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), ++ DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), + DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), + DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), + DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), +@@ -159,35 +165,35 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), + DEF_MOD("thermal", 522, R8A7795_CLK_CP), + DEF_MOD("pwm", 523, R8A7795_CLK_S3D4), +- DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), +- DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), +- DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), +- DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), +- DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), +- DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), +- DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), +- DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), +- DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), +- DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), +- DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), +- DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1), +- DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1), +- DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1), +- DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), +- DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1), +- DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1), ++ DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), ++ DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), ++ DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), ++ DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), ++ DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), ++ DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), ++ DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), ++ DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), ++ DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), ++ DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), ++ DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ ++ DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), ++ DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), + DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), + DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), + DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), + DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), +- DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), ++ DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ + DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), + DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), + DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), +@@ -198,20 +204,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { + DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), + DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), + DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), +- DEF_MOD("vin7", 804, R8A7795_CLK_S2D1), +- DEF_MOD("vin6", 805, R8A7795_CLK_S2D1), +- DEF_MOD("vin5", 806, R8A7795_CLK_S2D1), +- DEF_MOD("vin4", 807, R8A7795_CLK_S2D1), +- DEF_MOD("vin3", 808, R8A7795_CLK_S2D1), +- DEF_MOD("vin2", 809, R8A7795_CLK_S2D1), +- DEF_MOD("vin1", 810, R8A7795_CLK_S2D1), +- DEF_MOD("vin0", 811, R8A7795_CLK_S2D1), +- DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), ++ DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), ++ DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), ++ DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), ++ DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), ++ DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), ++ DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), ++ DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), ++ DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), ++ DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), + DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), +- DEF_MOD("imr3", 820, R8A7795_CLK_S2D1), +- DEF_MOD("imr2", 821, R8A7795_CLK_S2D1), +- DEF_MOD("imr1", 822, R8A7795_CLK_S2D1), +- DEF_MOD("imr0", 823, R8A7795_CLK_S2D1), ++ DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), ++ DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), ++ DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), ++ DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), + DEF_MOD("gpio7", 905, R8A7795_CLK_CP), + DEF_MOD("gpio6", 906, R8A7795_CLK_CP), + DEF_MOD("gpio5", 907, R8A7795_CLK_CP), +@@ -314,6 +320,82 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { + { 2, 192, 192, }, + }; + ++static const struct soc_device_attribute r8a7795es1[] __initconst = { ++ { .soc_id = "r8a7795", .revision = "ES1.*" }, ++ { /* sentinel */ } ++}; ++ ++ ++ /* ++ * Fixups for R-Car H3 ES1.x ++ */ ++ ++static const unsigned int r8a7795es1_mod_nullify[] __initconst = { ++ MOD_CLK_ID(326), /* USB-DMAC3-0 */ ++ MOD_CLK_ID(329), /* USB-DMAC3-1 */ ++ MOD_CLK_ID(700), /* EHCI/OHCI3 */ ++ MOD_CLK_ID(705), /* HS-USB-IF3 */ ++ ++}; ++ ++static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { ++ { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */ ++ { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */ ++ { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ ++ { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ ++ { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ ++ { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ ++ { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ ++ { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */ ++ { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */ ++ { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */ ++ { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */ ++ { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */ ++ { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */ ++ { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */ ++ { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */ ++ { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */ ++ { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */ ++ { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */ ++ { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */ ++ { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */ ++ { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */ ++ { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */ ++ { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */ ++ { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */ ++ { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */ ++ { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */ ++ { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */ ++ { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */ ++ { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */ ++ { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */ ++ { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */ ++ { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */ ++ { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */ ++ { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */ ++ { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */ ++ { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */ ++ { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */ ++}; ++ ++ ++ /* ++ * Fixups for R-Car H3 ES2.x ++ */ ++ ++static const unsigned int r8a7795es2_mod_nullify[] __initconst = { ++ MOD_CLK_ID(117), /* FDP1-2 */ ++ MOD_CLK_ID(327), /* USB3-IF1 */ ++ MOD_CLK_ID(600), /* FCPVD3 */ ++ MOD_CLK_ID(609), /* FCPVI2 */ ++ MOD_CLK_ID(613), /* FCPF2 */ ++ MOD_CLK_ID(616), /* FCPCI1 */ ++ MOD_CLK_ID(617), /* FCPCI0 */ ++ MOD_CLK_ID(620), /* VSPD3 */ ++ MOD_CLK_ID(629), /* VSPI2 */ ++ MOD_CLK_ID(713), /* CSI21 */ ++}; ++ + static int __init r8a7795_cpg_mssr_init(struct device *dev) + { + const struct rcar_gen3_cpg_pll_config *cpg_pll_config; +@@ -330,6 +412,25 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev) + return -EINVAL; + } + ++ if (soc_device_match(r8a7795es1)) { ++ cpg_core_nullify_range(r8a7795_core_clks, ++ ARRAY_SIZE(r8a7795_core_clks), ++ R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); ++ mssr_mod_nullify(r8a7795_mod_clks, ++ ARRAY_SIZE(r8a7795_mod_clks), ++ r8a7795es1_mod_nullify, ++ ARRAY_SIZE(r8a7795es1_mod_nullify)); ++ mssr_mod_reparent(r8a7795_mod_clks, ++ ARRAY_SIZE(r8a7795_mod_clks), ++ r8a7795es1_mod_reparent, ++ ARRAY_SIZE(r8a7795es1_mod_reparent)); ++ } else { ++ mssr_mod_nullify(r8a7795_mod_clks, ++ ARRAY_SIZE(r8a7795_mod_clks), ++ r8a7795es2_mod_nullify, ++ ARRAY_SIZE(r8a7795es2_mod_nullify)); ++ } ++ + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); + } + +-- +2.13.3 + diff --git a/patches.renesas/0161-clk-renesas-rcar-gen3-cpg-Add-support-for-RCLK-on-R-.patch b/patches.renesas/0161-clk-renesas-rcar-gen3-cpg-Add-support-for-RCLK-on-R-.patch new file mode 100644 index 00000000000000..c5083f7266fe06 --- /dev/null +++ b/patches.renesas/0161-clk-renesas-rcar-gen3-cpg-Add-support-for-RCLK-on-R-.patch @@ -0,0 +1,86 @@ +From 2a431d2d667268c052381ca56a0d7f4033cce70a Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 10 Mar 2017 12:13:37 +0100 +Subject: [PATCH 161/286] clk: renesas: rcar-gen3-cpg: Add support for RCLK on + R-Car H3 ES2.0 + +Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. + +Add support for that, but retain the old behavior for R-Car H3 ES1.x and +M3-W ES1.0 using a quirk. + +Inspired by a patch by Takeshi Kihara in the BSP. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> +(cherry picked from commit bb1953067c05be30a605ee1d5b05a2677735bb37) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/clk/renesas/rcar-gen3-cpg.c | 38 ++++++++++++++++++++++++++----------- + 1 file changed, 27 insertions(+), 11 deletions(-) + +diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c +index e5247e3dc897..3dee900522b7 100644 +--- a/drivers/clk/renesas/rcar-gen3-cpg.c ++++ b/drivers/clk/renesas/rcar-gen3-cpg.c +@@ -252,11 +252,20 @@ static u32 cpg_mode __initdata; + static u32 cpg_quirks __initdata; + + #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ ++#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ + + static const struct soc_device_attribute cpg_quirks_match[] __initconst = { + { + .soc_id = "r8a7795", .revision = "ES1.0", +- .data = (void *)PLL_ERRATA, ++ .data = (void *)(PLL_ERRATA | RCKCR_CKSEL), ++ }, ++ { ++ .soc_id = "r8a7795", .revision = "ES1.*", ++ .data = (void *)RCKCR_CKSEL, ++ }, ++ { ++ .soc_id = "r8a7796", .revision = "ES1.0", ++ .data = (void *)RCKCR_CKSEL, + }, + { /* sentinel */ } + }; +@@ -330,18 +339,25 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, + return cpg_sd_clk_register(core, base, __clk_get_name(parent)); + + case CLK_TYPE_GEN3_R: +- /* +- * RINT is default. +- * Only if EXTALR is populated, we switch to it. +- */ +- value = readl(base + CPG_RCKCR) & 0x3f; +- +- if (clk_get_rate(clks[cpg_clk_extalr])) { +- parent = clks[cpg_clk_extalr]; +- value |= BIT(15); ++ if (cpg_quirks & RCKCR_CKSEL) { ++ /* ++ * RINT is default. ++ * Only if EXTALR is populated, we switch to it. ++ */ ++ value = readl(base + CPG_RCKCR) & 0x3f; ++ ++ if (clk_get_rate(clks[cpg_clk_extalr])) { ++ parent = clks[cpg_clk_extalr]; ++ value |= BIT(15); ++ } ++ ++ writel(value, base + CPG_RCKCR); ++ break; + } + +- writel(value, base + CPG_RCKCR); ++ /* Select parent clock of RCLK by MD28 */ ++ if (cpg_mode & BIT(28)) ++ parent = clks[cpg_clk_extalr]; + break; + + default: +-- +2.13.3 + diff --git a/patches.renesas/0162-pinctrl-sh-pfc-r8a7795-Fix-hscif2_clk_b-and-hscif4_c.patch b/patches.renesas/0162-pinctrl-sh-pfc-r8a7795-Fix-hscif2_clk_b-and-hscif4_c.patch new file mode 100644 index 00000000000000..5b5688670adf43 --- /dev/null +++ b/patches.renesas/0162-pinctrl-sh-pfc-r8a7795-Fix-hscif2_clk_b-and-hscif4_c.patch @@ -0,0 +1,41 @@ +From f448442eccb681d866c97c37d5e1b1b7dfe3a35d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Sat, 11 Mar 2017 12:26:09 +0100 +Subject: [PATCH 162/286] pinctrl: sh-pfc: r8a7795: Fix hscif2_clk_b and + hscif4_ctrl + +Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[]. + +Fixes: a56069c46c102710 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 4324b6084f45b9faebda8d6563d8625d22b4b5df) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 504d0c3d7f74..6ba7ed15a461 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -2167,7 +2167,7 @@ static const unsigned int hscif2_clk_b_pins[] = { + RCAR_GP_PIN(6, 21), + }; + static const unsigned int hscif2_clk_b_mux[] = { +- HSCK1_B_MARK, ++ HSCK2_B_MARK, + }; + static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ +@@ -2240,7 +2240,7 @@ static const unsigned int hscif4_ctrl_pins[] = { + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), + }; + static const unsigned int hscif4_ctrl_mux[] = { +- HRTS4_N_MARK, HCTS3_N_MARK, ++ HRTS4_N_MARK, HCTS4_N_MARK, + }; + + static const unsigned int hscif4_data_b_pins[] = { +-- +2.13.3 + diff --git a/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch b/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch new file mode 100644 index 00000000000000..7f6b226205d99d --- /dev/null +++ b/patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch @@ -0,0 +1,263 @@ +From 7863a44c091770b60aecd923d72ccbacc5c06d6f Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Sat, 11 Mar 2017 12:12:43 +0100 +Subject: [PATCH 163/286] pinctrl: sh-pfc: r8a7795: Restore sort order + +Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong +positions. Restore sort order (alphabetically, per group). + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit b332da51a929de9081058b17d108008cd6a0d15f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 171 ++++++++++++++++++----------------- + 1 file changed, 86 insertions(+), 85 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 6ba7ed15a461..3d1c32cca16a 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -3101,6 +3101,55 @@ static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, + }; + ++/* - QSPI0 ------------------------------------------------------------------ */ ++static const unsigned int qspi0_ctrl_pins[] = { ++ /* QSPI0_SPCLK, QSPI0_SSL */ ++ PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), ++}; ++static const unsigned int qspi0_ctrl_mux[] = { ++ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, ++}; ++static const unsigned int qspi0_data2_pins[] = { ++ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ ++ PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), ++}; ++static const unsigned int qspi0_data2_mux[] = { ++ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, ++}; ++static const unsigned int qspi0_data4_pins[] = { ++ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ ++ PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), ++ PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), ++}; ++static const unsigned int qspi0_data4_mux[] = { ++ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, ++ QSPI0_IO2_MARK, QSPI0_IO3_MARK, ++}; ++/* - QSPI1 ------------------------------------------------------------------ */ ++static const unsigned int qspi1_ctrl_pins[] = { ++ /* QSPI1_SPCLK, QSPI1_SSL */ ++ PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), ++}; ++static const unsigned int qspi1_ctrl_mux[] = { ++ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, ++}; ++static const unsigned int qspi1_data2_pins[] = { ++ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ ++ PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), ++}; ++static const unsigned int qspi1_data2_mux[] = { ++ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, ++}; ++static const unsigned int qspi1_data4_pins[] = { ++ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ ++ PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), ++ PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), ++}; ++static const unsigned int qspi1_data4_mux[] = { ++ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, ++ QSPI1_IO2_MARK, QSPI1_IO3_MARK, ++}; ++ + /* - SATA --------------------------------------------------------------------*/ + static const unsigned int sata0_devslp_a_pins[] = { + /* DEVSLP */ +@@ -3299,6 +3348,23 @@ static const unsigned int scif5_clk_pins[] = { + static const unsigned int scif5_clk_mux[] = { + SCK5_MARK, + }; ++ ++/* - SCIF Clock ------------------------------------------------------------- */ ++static const unsigned int scif_clk_a_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(6, 23), ++}; ++static const unsigned int scif_clk_a_mux[] = { ++ SCIF_CLK_A_MARK, ++}; ++static const unsigned int scif_clk_b_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int scif_clk_b_mux[] = { ++ SCIF_CLK_B_MARK, ++}; ++ + /* - SDHI0 ------------------------------------------------------------------ */ + static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ +@@ -3506,22 +3572,6 @@ static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, + }; + +-/* - SCIF Clock ------------------------------------------------------------- */ +-static const unsigned int scif_clk_a_pins[] = { +- /* SCIF_CLK */ +- RCAR_GP_PIN(6, 23), +-}; +-static const unsigned int scif_clk_a_mux[] = { +- SCIF_CLK_A_MARK, +-}; +-static const unsigned int scif_clk_b_pins[] = { +- /* SCIF_CLK */ +- RCAR_GP_PIN(5, 9), +-}; +-static const unsigned int scif_clk_b_mux[] = { +- SCIF_CLK_B_MARK, +-}; +- + /* - SSI -------------------------------------------------------------------- */ + static const unsigned int ssi0_data_pins[] = { + /* SDATA */ +@@ -3724,55 +3774,6 @@ static const unsigned int usb2_mux[] = { + USB2_PWEN_MARK, USB2_OVC_MARK, + }; + +-/* - QSPI0 ------------------------------------------------------------------ */ +-static const unsigned int qspi0_ctrl_pins[] = { +- /* QSPI0_SPCLK, QSPI0_SSL */ +- PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), +-}; +-static const unsigned int qspi0_ctrl_mux[] = { +- QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +-}; +-static const unsigned int qspi0_data2_pins[] = { +- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ +- PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), +-}; +-static const unsigned int qspi0_data2_mux[] = { +- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +-}; +-static const unsigned int qspi0_data4_pins[] = { +- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ +- PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), +- PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), +-}; +-static const unsigned int qspi0_data4_mux[] = { +- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +- QSPI0_IO2_MARK, QSPI0_IO3_MARK, +-}; +-/* - QSPI1 ------------------------------------------------------------------ */ +-static const unsigned int qspi1_ctrl_pins[] = { +- /* QSPI1_SPCLK, QSPI1_SSL */ +- PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), +-}; +-static const unsigned int qspi1_ctrl_mux[] = { +- QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +-}; +-static const unsigned int qspi1_data2_pins[] = { +- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ +- PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), +-}; +-static const unsigned int qspi1_data2_mux[] = { +- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +-}; +-static const unsigned int qspi1_data4_pins[] = { +- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ +- PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), +- PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), +-}; +-static const unsigned int qspi1_data4_mux[] = { +- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +- QSPI1_IO2_MARK, QSPI1_IO3_MARK, +-}; +- + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), +@@ -3990,6 +3991,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), ++ SH_PFC_PIN_GROUP(qspi0_ctrl), ++ SH_PFC_PIN_GROUP(qspi0_data2), ++ SH_PFC_PIN_GROUP(qspi0_data4), ++ SH_PFC_PIN_GROUP(qspi1_ctrl), ++ SH_PFC_PIN_GROUP(qspi1_data2), ++ SH_PFC_PIN_GROUP(qspi1_data4), + SH_PFC_PIN_GROUP(sata0_devslp_a), + SH_PFC_PIN_GROUP(sata0_devslp_b), + SH_PFC_PIN_GROUP(scif0_data), +@@ -4073,12 +4080,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), +- SH_PFC_PIN_GROUP(qspi0_ctrl), +- SH_PFC_PIN_GROUP(qspi0_data2), +- SH_PFC_PIN_GROUP(qspi0_data4), +- SH_PFC_PIN_GROUP(qspi1_ctrl), +- SH_PFC_PIN_GROUP(qspi1_data2), +- SH_PFC_PIN_GROUP(qspi1_data4), + }; + + static const char * const audio_clk_groups[] = { +@@ -4393,6 +4394,18 @@ static const char * const pwm6_groups[] = { + "pwm6_b", + }; + ++static const char * const qspi0_groups[] = { ++ "qspi0_ctrl", ++ "qspi0_data2", ++ "qspi0_data4", ++}; ++ ++static const char * const qspi1_groups[] = { ++ "qspi1_ctrl", ++ "qspi1_data2", ++ "qspi1_data4", ++}; ++ + static const char * const sata0_groups[] = { + "sata0_devslp_a", + "sata0_devslp_b", +@@ -4524,18 +4537,6 @@ static const char * const usb2_groups[] = { + "usb2", + }; + +-static const char * const qspi0_groups[] = { +- "qspi0_ctrl", +- "qspi0_data2", +- "qspi0_data4", +-}; +- +-static const char * const qspi1_groups[] = { +- "qspi1_ctrl", +- "qspi1_data2", +- "qspi1_data4", +-}; +- + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), +@@ -4569,6 +4570,8 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), ++ SH_PFC_FUNCTION(qspi0), ++ SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(sata0), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +@@ -4585,8 +4588,6 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), +- SH_PFC_FUNCTION(qspi0), +- SH_PFC_FUNCTION(qspi1), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +2.13.3 + diff --git a/patches.renesas/0164-pinctrl-sh-pfc-Update-info-pointer-after-SoC-specifi.patch b/patches.renesas/0164-pinctrl-sh-pfc-Update-info-pointer-after-SoC-specifi.patch new file mode 100644 index 00000000000000..20ade9f43e9e09 --- /dev/null +++ b/patches.renesas/0164-pinctrl-sh-pfc-Update-info-pointer-after-SoC-specifi.patch @@ -0,0 +1,36 @@ +From 71cf9371dde08af8cdf7edea3cf25061e1787891 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 9 Mar 2017 19:20:48 +0100 +Subject: [PATCH 164/286] pinctrl: sh-pfc: Update info pointer after + SoC-specific init + +Update the sh_pfc_soc_info pointer after calling the SoC-specific +initialization function, as it may have been updated to e.g. handle +different SoC revisions. This makes sure the correct subdriver name is +printed later. + +Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 3091ae775fae17084013021d01513bc1ad274e6a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c +index cf80ce1dd7ce..4a5a0feb931b 100644 +--- a/drivers/pinctrl/sh-pfc/core.c ++++ b/drivers/pinctrl/sh-pfc/core.c +@@ -586,6 +586,9 @@ static int sh_pfc_probe(struct platform_device *pdev) + ret = info->ops->init(pfc); + if (ret < 0) + return ret; ++ ++ /* .init() may have overridden pfc->info */ ++ info = pfc->info; + } + + /* Enable dummy states for those platforms without pinctrl support */ +-- +2.13.3 + diff --git a/patches.renesas/0165-pinctrl-sh-pfc-r8a7795-Add-support-for-R-Car-H3-ES2..patch b/patches.renesas/0165-pinctrl-sh-pfc-r8a7795-Add-support-for-R-Car-H3-ES2..patch new file mode 100644 index 00000000000000..3a6e275480cbad --- /dev/null +++ b/patches.renesas/0165-pinctrl-sh-pfc-r8a7795-Add-support-for-R-Car-H3-ES2..patch @@ -0,0 +1,10839 @@ +From 3442a66c50cd9af39485629f0a4224cd630af46d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Oct 2016 14:49:57 +0200 +Subject: [PATCH 165/286] pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 + ES2.0 + +The Pin Function Controller module in the R-Car H3 ES2.0 differs from +ES1.x in many ways. + +The goal is twofold: + 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary + for now, + 2. Make it clear which code supports ES1.x, so it can easily be + identified and removed later, when production SoCs are deemed + ubiquitous. + +Hence this patch: + 1. Extracts the support for R-Car H3 ES1.x into a separate file, as + the differences are quite large, + 2. Adds code for detecting the SoC revision at runtime using the new + soc_device_match() API, and selecting pinctrl tables for the actual + SoC revision, + 3. Replaces the core register and bitfield definitions by their + counterparts for R-Car H3 ES2.0. + +The addition of pins, groups, and functions for the various on-chip +devices is left to subsequent patches. + +The R-Car H3 ES2.0 register and bitfield definitions were extracted from +a patch in the BSP by Takeshi Kihara. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> +(cherry picked from commit b205914c8f822ef2464b741c64e892823d685ad6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/Makefile | 1 + + drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 5705 ++++++++++++++++++++++++++++++ + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4780 +++++-------------------- + drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + + 4 files changed, 6603 insertions(+), 3884 deletions(-) + create mode 100644 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c + +diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile +index 2dda8c63f3cf..8e08684774af 100644 +--- a/drivers/pinctrl/sh-pfc/Makefile ++++ b/drivers/pinctrl/sh-pfc/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o + obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o + obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o + obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o ++obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o + obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o + obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o + obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +new file mode 100644 +index 000000000000..081efda9a280 +--- /dev/null ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +@@ -0,0 +1,5705 @@ ++/* ++ * R8A7795 ES1.x processor support - PFC hardware block. ++ * ++ * Copyright (C) 2015 Renesas Electronics Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#include <linux/kernel.h> ++ ++#include "core.h" ++#include "sh_pfc.h" ++ ++#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \ ++ SH_PFC_PIN_CFG_PULL_UP | \ ++ SH_PFC_PIN_CFG_PULL_DOWN) ++ ++#define CPU_ALL_PORT(fn, sfx) \ ++ PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ ++ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ ++ PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \ ++ PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS) ++/* ++ * F_() : just information ++ * FM() : macro for FN_xxx / xxx_MARK ++ */ ++ ++/* GPSR0 */ ++#define GPSR0_15 F_(D15, IP7_11_8) ++#define GPSR0_14 F_(D14, IP7_7_4) ++#define GPSR0_13 F_(D13, IP7_3_0) ++#define GPSR0_12 F_(D12, IP6_31_28) ++#define GPSR0_11 F_(D11, IP6_27_24) ++#define GPSR0_10 F_(D10, IP6_23_20) ++#define GPSR0_9 F_(D9, IP6_19_16) ++#define GPSR0_8 F_(D8, IP6_15_12) ++#define GPSR0_7 F_(D7, IP6_11_8) ++#define GPSR0_6 F_(D6, IP6_7_4) ++#define GPSR0_5 F_(D5, IP6_3_0) ++#define GPSR0_4 F_(D4, IP5_31_28) ++#define GPSR0_3 F_(D3, IP5_27_24) ++#define GPSR0_2 F_(D2, IP5_23_20) ++#define GPSR0_1 F_(D1, IP5_19_16) ++#define GPSR0_0 F_(D0, IP5_15_12) ++ ++/* GPSR1 */ ++#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8) ++#define GPSR1_26 F_(WE1_N, IP5_7_4) ++#define GPSR1_25 F_(WE0_N, IP5_3_0) ++#define GPSR1_24 F_(RD_WR_N, IP4_31_28) ++#define GPSR1_23 F_(RD_N, IP4_27_24) ++#define GPSR1_22 F_(BS_N, IP4_23_20) ++#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) ++#define GPSR1_20 F_(CS0_N, IP4_15_12) ++#define GPSR1_19 F_(A19, IP4_11_8) ++#define GPSR1_18 F_(A18, IP4_7_4) ++#define GPSR1_17 F_(A17, IP4_3_0) ++#define GPSR1_16 F_(A16, IP3_31_28) ++#define GPSR1_15 F_(A15, IP3_27_24) ++#define GPSR1_14 F_(A14, IP3_23_20) ++#define GPSR1_13 F_(A13, IP3_19_16) ++#define GPSR1_12 F_(A12, IP3_15_12) ++#define GPSR1_11 F_(A11, IP3_11_8) ++#define GPSR1_10 F_(A10, IP3_7_4) ++#define GPSR1_9 F_(A9, IP3_3_0) ++#define GPSR1_8 F_(A8, IP2_31_28) ++#define GPSR1_7 F_(A7, IP2_27_24) ++#define GPSR1_6 F_(A6, IP2_23_20) ++#define GPSR1_5 F_(A5, IP2_19_16) ++#define GPSR1_4 F_(A4, IP2_15_12) ++#define GPSR1_3 F_(A3, IP2_11_8) ++#define GPSR1_2 F_(A2, IP2_7_4) ++#define GPSR1_1 F_(A1, IP2_3_0) ++#define GPSR1_0 F_(A0, IP1_31_28) ++ ++/* GPSR2 */ ++#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20) ++#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16) ++#define GPSR2_12 F_(AVB_LINK, IP0_15_12) ++#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8) ++#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4) ++#define GPSR2_9 F_(AVB_MDC, IP0_3_0) ++#define GPSR2_8 F_(PWM2_A, IP1_27_24) ++#define GPSR2_7 F_(PWM1_A, IP1_23_20) ++#define GPSR2_6 F_(PWM0, IP1_19_16) ++#define GPSR2_5 F_(IRQ5, IP1_15_12) ++#define GPSR2_4 F_(IRQ4, IP1_11_8) ++#define GPSR2_3 F_(IRQ3, IP1_7_4) ++#define GPSR2_2 F_(IRQ2, IP1_3_0) ++#define GPSR2_1 F_(IRQ1, IP0_31_28) ++#define GPSR2_0 F_(IRQ0, IP0_27_24) ++ ++/* GPSR3 */ ++#define GPSR3_15 F_(SD1_WP, IP10_23_20) ++#define GPSR3_14 F_(SD1_CD, IP10_19_16) ++#define GPSR3_13 F_(SD0_WP, IP10_15_12) ++#define GPSR3_12 F_(SD0_CD, IP10_11_8) ++#define GPSR3_11 F_(SD1_DAT3, IP8_31_28) ++#define GPSR3_10 F_(SD1_DAT2, IP8_27_24) ++#define GPSR3_9 F_(SD1_DAT1, IP8_23_20) ++#define GPSR3_8 F_(SD1_DAT0, IP8_19_16) ++#define GPSR3_7 F_(SD1_CMD, IP8_15_12) ++#define GPSR3_6 F_(SD1_CLK, IP8_11_8) ++#define GPSR3_5 F_(SD0_DAT3, IP8_7_4) ++#define GPSR3_4 F_(SD0_DAT2, IP8_3_0) ++#define GPSR3_3 F_(SD0_DAT1, IP7_31_28) ++#define GPSR3_2 F_(SD0_DAT0, IP7_27_24) ++#define GPSR3_1 F_(SD0_CMD, IP7_23_20) ++#define GPSR3_0 F_(SD0_CLK, IP7_19_16) ++ ++/* GPSR4 */ ++#define GPSR4_17 FM(SD3_DS) ++#define GPSR4_16 F_(SD3_DAT7, IP10_7_4) ++#define GPSR4_15 F_(SD3_DAT6, IP10_3_0) ++#define GPSR4_14 F_(SD3_DAT5, IP9_31_28) ++#define GPSR4_13 F_(SD3_DAT4, IP9_27_24) ++#define GPSR4_12 FM(SD3_DAT3) ++#define GPSR4_11 FM(SD3_DAT2) ++#define GPSR4_10 FM(SD3_DAT1) ++#define GPSR4_9 FM(SD3_DAT0) ++#define GPSR4_8 FM(SD3_CMD) ++#define GPSR4_7 FM(SD3_CLK) ++#define GPSR4_6 F_(SD2_DS, IP9_23_20) ++#define GPSR4_5 F_(SD2_DAT3, IP9_19_16) ++#define GPSR4_4 F_(SD2_DAT2, IP9_15_12) ++#define GPSR4_3 F_(SD2_DAT1, IP9_11_8) ++#define GPSR4_2 F_(SD2_DAT0, IP9_7_4) ++#define GPSR4_1 FM(SD2_CMD) ++#define GPSR4_0 F_(SD2_CLK, IP9_3_0) ++ ++/* GPSR5 */ ++#define GPSR5_25 F_(MLB_DAT, IP13_19_16) ++#define GPSR5_24 F_(MLB_SIG, IP13_15_12) ++#define GPSR5_23 F_(MLB_CLK, IP13_11_8) ++#define GPSR5_22 FM(MSIOF0_RXD) ++#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4) ++#define GPSR5_20 FM(MSIOF0_TXD) ++#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0) ++#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28) ++#define GPSR5_17 FM(MSIOF0_SCK) ++#define GPSR5_16 F_(HRTS0_N, IP12_27_24) ++#define GPSR5_15 F_(HCTS0_N, IP12_23_20) ++#define GPSR5_14 F_(HTX0, IP12_19_16) ++#define GPSR5_13 F_(HRX0, IP12_15_12) ++#define GPSR5_12 F_(HSCK0, IP12_11_8) ++#define GPSR5_11 F_(RX2_A, IP12_7_4) ++#define GPSR5_10 F_(TX2_A, IP12_3_0) ++#define GPSR5_9 F_(SCK2, IP11_31_28) ++#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24) ++#define GPSR5_7 F_(CTS1_N, IP11_23_20) ++#define GPSR5_6 F_(TX1_A, IP11_19_16) ++#define GPSR5_5 F_(RX1_A, IP11_15_12) ++#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8) ++#define GPSR5_3 F_(CTS0_N, IP11_7_4) ++#define GPSR5_2 F_(TX0, IP11_3_0) ++#define GPSR5_1 F_(RX0, IP10_31_28) ++#define GPSR5_0 F_(SCK0, IP10_27_24) ++ ++/* GPSR6 */ ++#define GPSR6_31 F_(USB31_OVC, IP17_7_4) ++#define GPSR6_30 F_(USB31_PWEN, IP17_3_0) ++#define GPSR6_29 F_(USB30_OVC, IP16_31_28) ++#define GPSR6_28 F_(USB30_PWEN, IP16_27_24) ++#define GPSR6_27 F_(USB1_OVC, IP16_23_20) ++#define GPSR6_26 F_(USB1_PWEN, IP16_19_16) ++#define GPSR6_25 F_(USB0_OVC, IP16_15_12) ++#define GPSR6_24 F_(USB0_PWEN, IP16_11_8) ++#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4) ++#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0) ++#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28) ++#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24) ++#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20) ++#define GPSR6_18 F_(SSI_WS78, IP15_19_16) ++#define GPSR6_17 F_(SSI_SCK78, IP15_15_12) ++#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8) ++#define GPSR6_15 F_(SSI_WS6, IP15_7_4) ++#define GPSR6_14 F_(SSI_SCK6, IP15_3_0) ++#define GPSR6_13 FM(SSI_SDATA5) ++#define GPSR6_12 FM(SSI_WS5) ++#define GPSR6_11 FM(SSI_SCK5) ++#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28) ++#define GPSR6_9 F_(SSI_WS4, IP14_27_24) ++#define GPSR6_8 F_(SSI_SCK4, IP14_23_20) ++#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16) ++#define GPSR6_6 F_(SSI_WS34, IP14_15_12) ++#define GPSR6_5 F_(SSI_SCK34, IP14_11_8) ++#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) ++#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) ++#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) ++#define GPSR6_1 F_(SSI_WS01239, IP13_27_24) ++#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20) ++ ++/* GPSR7 */ ++#define GPSR7_3 FM(HDMI1_CEC) ++#define GPSR7_2 FM(HDMI0_CEC) ++#define GPSR7_1 FM(AVS2) ++#define GPSR7_0 FM(AVS1) ++ ++ ++/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ ++#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++ ++/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ ++#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++ ++/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ ++#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++ ++/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ ++#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++ ++#define PINMUX_GPSR \ ++\ ++ GPSR6_31 \ ++ GPSR6_30 \ ++ GPSR6_29 \ ++ GPSR6_28 \ ++ GPSR1_27 GPSR6_27 \ ++ GPSR1_26 GPSR6_26 \ ++ GPSR1_25 GPSR5_25 GPSR6_25 \ ++ GPSR1_24 GPSR5_24 GPSR6_24 \ ++ GPSR1_23 GPSR5_23 GPSR6_23 \ ++ GPSR1_22 GPSR5_22 GPSR6_22 \ ++ GPSR1_21 GPSR5_21 GPSR6_21 \ ++ GPSR1_20 GPSR5_20 GPSR6_20 \ ++ GPSR1_19 GPSR5_19 GPSR6_19 \ ++ GPSR1_18 GPSR5_18 GPSR6_18 \ ++ GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \ ++ GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \ ++GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \ ++GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \ ++GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \ ++GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \ ++GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \ ++GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \ ++GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ ++GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ ++GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ ++GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ ++GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ ++GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ ++GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \ ++GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \ ++GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \ ++GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 ++ ++#define PINMUX_IPSR \ ++\ ++FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ ++FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ ++FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ ++FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ ++FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ ++FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ ++FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ ++FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ ++\ ++FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ ++FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ ++FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ ++FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ ++FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ ++FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ ++FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ ++FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ ++\ ++FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ ++FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ ++FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ ++FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ ++FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ ++FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ ++FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ ++FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ ++\ ++FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \ ++FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \ ++FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \ ++FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \ ++FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \ ++FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \ ++FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ ++FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ ++\ ++FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \ ++FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \ ++FM(IP16_11_8) IP16_11_8 \ ++FM(IP16_15_12) IP16_15_12 \ ++FM(IP16_19_16) IP16_19_16 \ ++FM(IP16_23_20) IP16_23_20 \ ++FM(IP16_27_24) IP16_27_24 \ ++FM(IP16_31_28) IP16_31_28 ++ ++/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ ++#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) ++#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) ++#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) ++#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) ++#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) ++#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) ++#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1) ++#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1) ++#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) ++#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) ++#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) ++#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) ++#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1) ++#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1) ++#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) ++#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) ++#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) ++#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) ++#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) ++#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) ++#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3) ++ ++/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ ++#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) ++#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) ++#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) ++#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) ++#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) ++#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) ++#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1) ++#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3) ++#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1) ++#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) ++#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) ++#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) ++#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) ++#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) ++#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) ++#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) ++#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) ++#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1) ++#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1) ++#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1) ++#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) ++#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) ++ ++/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ ++#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) ++#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) ++#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) ++#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) ++ ++#define PINMUX_MOD_SELS\ ++\ ++ MOD_SEL1_31_30 MOD_SEL2_31 \ ++MOD_SEL0_30_29 MOD_SEL2_30 \ ++ MOD_SEL1_29_28_27 MOD_SEL2_29 \ ++MOD_SEL0_28_27 \ ++\ ++MOD_SEL0_26_25_24 MOD_SEL1_26 \ ++ MOD_SEL1_25_24 \ ++\ ++MOD_SEL0_23 MOD_SEL1_23_22_21 \ ++MOD_SEL0_22 \ ++MOD_SEL0_21_20 \ ++ MOD_SEL1_20 \ ++MOD_SEL0_19 MOD_SEL1_19 \ ++MOD_SEL0_18 MOD_SEL1_18_17 \ ++MOD_SEL0_17 \ ++MOD_SEL0_16_15 MOD_SEL1_16 \ ++ MOD_SEL1_15_14 \ ++MOD_SEL0_14 \ ++MOD_SEL0_13 MOD_SEL1_13 \ ++MOD_SEL0_12 MOD_SEL1_12 \ ++MOD_SEL0_11 MOD_SEL1_11 \ ++MOD_SEL0_10 MOD_SEL1_10 \ ++MOD_SEL0_9 MOD_SEL1_9 \ ++MOD_SEL0_8 \ ++MOD_SEL0_7_6 \ ++ MOD_SEL1_6 \ ++MOD_SEL0_5_4 MOD_SEL1_5 \ ++ MOD_SEL1_4 \ ++MOD_SEL0_3 MOD_SEL1_3 \ ++MOD_SEL0_2_1 MOD_SEL1_2 \ ++ MOD_SEL1_1 \ ++ MOD_SEL1_0 MOD_SEL2_0 ++ ++/* ++ * These pins are not able to be muxed but have other properties ++ * that can be set, such as drive-strength or pull-up/pull-down enable. ++ */ ++#define PINMUX_STATIC \ ++ FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \ ++ FM(QSPI0_IO2) FM(QSPI0_IO3) \ ++ FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \ ++ FM(QSPI1_IO2) FM(QSPI1_IO3) \ ++ FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \ ++ FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \ ++ FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ ++ FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ ++ FM(CLKOUT) FM(PRESETOUT) \ ++ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ ++ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) ++ ++enum { ++ PINMUX_RESERVED = 0, ++ ++ PINMUX_DATA_BEGIN, ++ GP_ALL(DATA), ++ PINMUX_DATA_END, ++ ++#define F_(x, y) ++#define FM(x) FN_##x, ++ PINMUX_FUNCTION_BEGIN, ++ GP_ALL(FN), ++ PINMUX_GPSR ++ PINMUX_IPSR ++ PINMUX_MOD_SELS ++ PINMUX_FUNCTION_END, ++#undef F_ ++#undef FM ++ ++#define F_(x, y) ++#define FM(x) x##_MARK, ++ PINMUX_MARK_BEGIN, ++ PINMUX_GPSR ++ PINMUX_IPSR ++ PINMUX_MOD_SELS ++ PINMUX_STATIC ++ PINMUX_MARK_END, ++#undef F_ ++#undef FM ++}; ++ ++static const u16 pinmux_data[] = { ++ PINMUX_DATA_GP_ALL(), ++ ++ PINMUX_SINGLE(AVS1), ++ PINMUX_SINGLE(AVS2), ++ PINMUX_SINGLE(HDMI0_CEC), ++ PINMUX_SINGLE(HDMI1_CEC), ++ PINMUX_SINGLE(I2C_SEL_0_1), ++ PINMUX_SINGLE(I2C_SEL_3_1), ++ PINMUX_SINGLE(I2C_SEL_5_1), ++ PINMUX_SINGLE(MSIOF0_RXD), ++ PINMUX_SINGLE(MSIOF0_SCK), ++ PINMUX_SINGLE(MSIOF0_TXD), ++ PINMUX_SINGLE(SD2_CMD), ++ PINMUX_SINGLE(SD3_CLK), ++ PINMUX_SINGLE(SD3_CMD), ++ PINMUX_SINGLE(SD3_DAT0), ++ PINMUX_SINGLE(SD3_DAT1), ++ PINMUX_SINGLE(SD3_DAT2), ++ PINMUX_SINGLE(SD3_DAT3), ++ PINMUX_SINGLE(SD3_DS), ++ PINMUX_SINGLE(SSI_SCK5), ++ PINMUX_SINGLE(SSI_SDATA5), ++ PINMUX_SINGLE(SSI_WS5), ++ ++ /* IPSR0 */ ++ PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC), ++ PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2), ++ ++ PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC), ++ PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2), ++ PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0), ++ ++ PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT), ++ PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2), ++ PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0), ++ ++ PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK), ++ PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), ++ PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), ++ ++ PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), ++ PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), ++ PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), ++ ++ PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), ++ PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), ++ PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0), ++ ++ PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), ++ PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), ++ PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE), ++ PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), ++ PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), ++ ++ PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), ++ PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), ++ PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP), ++ PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), ++ PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), ++ ++ /* IPSR1 */ ++ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), ++ PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE), ++ PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), ++ PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), ++ ++ PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), ++ PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), ++ PINMUX_IPSR_GPSR(IP1_7_4, A25), ++ PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), ++ PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), ++ ++ PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), ++ PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), ++ PINMUX_IPSR_GPSR(IP1_11_8, A24), ++ PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), ++ PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), ++ ++ PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), ++ PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), ++ PINMUX_IPSR_GPSR(IP1_15_12, A23), ++ PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), ++ PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), ++ ++ PINMUX_IPSR_GPSR(IP1_19_16, PWM0), ++ PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), ++ PINMUX_IPSR_GPSR(IP1_19_16, A22), ++ PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), ++ ++ PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), ++ PINMUX_IPSR_GPSR(IP1_23_20, A21), ++ PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), ++ PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), ++ PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), ++ ++ PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), ++ PINMUX_IPSR_GPSR(IP1_27_24, A20), ++ PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), ++ PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), ++ ++ PINMUX_IPSR_GPSR(IP1_31_28, A0), ++ PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), ++ PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8), ++ PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0), ++ PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0), ++ ++ /* IPSR2 */ ++ PINMUX_IPSR_GPSR(IP2_3_0, A1), ++ PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17), ++ PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9), ++ PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1), ++ PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0), ++ ++ PINMUX_IPSR_GPSR(IP2_7_4, A2), ++ PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18), ++ PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10), ++ PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2), ++ PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0), ++ ++ PINMUX_IPSR_GPSR(IP2_11_8, A3), ++ PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19), ++ PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11), ++ PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3), ++ PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0), ++ ++ PINMUX_IPSR_GPSR(IP2_15_12, A4), ++ PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20), ++ PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12), ++ PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12), ++ PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4), ++ ++ PINMUX_IPSR_GPSR(IP2_19_16, A5), ++ PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21), ++ PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1), ++ PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1), ++ PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13), ++ PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13), ++ PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5), ++ ++ PINMUX_IPSR_GPSR(IP2_23_20, A6), ++ PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22), ++ PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1), ++ PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14), ++ PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14), ++ PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6), ++ ++ PINMUX_IPSR_GPSR(IP2_27_24, A7), ++ PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23), ++ PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1), ++ PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15), ++ PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15), ++ PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7), ++ ++ PINMUX_IPSR_GPSR(IP2_31_28, A8), ++ PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1), ++ PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1), ++ PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0), ++ PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1), ++ PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1), ++ ++ /* IPSR3 */ ++ PINMUX_IPSR_GPSR(IP3_3_0, A9), ++ PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1), ++ PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N), ++ ++ PINMUX_IPSR_GPSR(IP3_7_4, A10), ++ PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1), ++ PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N), ++ ++ PINMUX_IPSR_GPSR(IP3_11_8, A11), ++ PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1), ++ PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0), ++ PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1), ++ PINMUX_IPSR_GPSR(IP3_11_8, HSCK4), ++ PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD), ++ PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0), ++ PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1), ++ PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1), ++ ++ PINMUX_IPSR_GPSR(IP3_15_12, A12), ++ PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12), ++ PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2), ++ PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0), ++ PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8), ++ PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4), ++ ++ PINMUX_IPSR_GPSR(IP3_19_16, A13), ++ PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13), ++ PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2), ++ PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0), ++ PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9), ++ PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5), ++ ++ PINMUX_IPSR_GPSR(IP3_23_20, A14), ++ PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14), ++ PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2), ++ PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N), ++ PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10), ++ PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6), ++ ++ PINMUX_IPSR_GPSR(IP3_27_24, A15), ++ PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15), ++ PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2), ++ PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N), ++ PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11), ++ PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7), ++ ++ PINMUX_IPSR_GPSR(IP3_31_28, A16), ++ PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8), ++ PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD), ++ PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0), ++ ++ /* IPSR4 */ ++ PINMUX_IPSR_GPSR(IP4_3_0, A17), ++ PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9), ++ PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N), ++ PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1), ++ ++ PINMUX_IPSR_GPSR(IP4_7_4, A18), ++ PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10), ++ PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N), ++ PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2), ++ ++ PINMUX_IPSR_GPSR(IP4_11_8, A19), ++ PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11), ++ PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB), ++ PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3), ++ ++ PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), ++ PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), ++ ++ PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), ++ PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), ++ PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), ++ ++ PINMUX_IPSR_GPSR(IP4_23_20, BS_N), ++ PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS), ++ PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3), ++ PINMUX_IPSR_GPSR(IP4_23_20, SCK3), ++ PINMUX_IPSR_GPSR(IP4_23_20, HSCK3), ++ PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX), ++ PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX), ++ PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0), ++ ++ PINMUX_IPSR_GPSR(IP4_27_24, RD_N), ++ PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3), ++ PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0), ++ PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0), ++ PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0), ++ PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0), ++ ++ PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N), ++ PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3), ++ PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0), ++ PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0), ++ PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0), ++ PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0), ++ ++ /* IPSR5 */ ++ PINMUX_IPSR_GPSR(IP5_3_0, WE0_N), ++ PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3), ++ PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N), ++ PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N), ++ PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1), ++ PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK), ++ PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0), ++ ++ PINMUX_IPSR_GPSR(IP5_7_4, WE1_N), ++ PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3), ++ PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS), ++ PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N), ++ PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1), ++ PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX), ++ PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX), ++ PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0), ++ ++ PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0), ++ PINMUX_IPSR_GPSR(IP5_11_8, QCLK), ++ PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK), ++ PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0), ++ ++ PINMUX_IPSR_GPSR(IP5_15_12, D0), ++ PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16), ++ PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0), ++ ++ PINMUX_IPSR_GPSR(IP5_19_16, D1), ++ PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17), ++ PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1), ++ ++ PINMUX_IPSR_GPSR(IP5_23_20, D2), ++ PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18), ++ PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2), ++ ++ PINMUX_IPSR_GPSR(IP5_27_24, D3), ++ PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19), ++ PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3), ++ ++ PINMUX_IPSR_GPSR(IP5_31_28, D4), ++ PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20), ++ PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4), ++ ++ /* IPSR6 */ ++ PINMUX_IPSR_GPSR(IP6_3_0, D5), ++ PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), ++ PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), ++ ++ PINMUX_IPSR_GPSR(IP6_7_4, D6), ++ PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), ++ PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), ++ ++ PINMUX_IPSR_GPSR(IP6_11_8, D7), ++ PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), ++ PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), ++ ++ PINMUX_IPSR_GPSR(IP6_15_12, D8), ++ PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), ++ PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), ++ ++ PINMUX_IPSR_GPSR(IP6_19_16, D9), ++ PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), ++ PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), ++ ++ PINMUX_IPSR_GPSR(IP6_23_20, D10), ++ PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), ++ PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), ++ PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), ++ PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), ++ PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), ++ ++ PINMUX_IPSR_GPSR(IP6_27_24, D11), ++ PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), ++ PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), ++ PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), ++ PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), ++ PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), ++ ++ PINMUX_IPSR_GPSR(IP6_31_28, D12), ++ PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), ++ PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), ++ ++ /* IPSR7 */ ++ PINMUX_IPSR_GPSR(IP7_3_0, D13), ++ PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), ++ PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), ++ ++ PINMUX_IPSR_GPSR(IP7_7_4, D14), ++ PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), ++ PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), ++ PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), ++ PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), ++ ++ PINMUX_IPSR_GPSR(IP7_11_8, D15), ++ PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), ++ PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), ++ PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), ++ PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), ++ ++ PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), ++ ++ PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), ++ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), ++ ++ PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), ++ PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), ++ ++ PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), ++ PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), ++ ++ PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), ++ PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), ++ ++ /* IPSR8 */ ++ PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), ++ PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), ++ ++ PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), ++ PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), ++ ++ PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), ++ PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), ++ ++ PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), ++ PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), ++ PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), ++ ++ PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), ++ PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), ++ PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), ++ ++ PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), ++ PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), ++ PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), ++ ++ PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), ++ PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), ++ PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), ++ ++ PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), ++ PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), ++ PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), ++ ++ /* IPSR9 */ ++ PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), ++ ++ PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0), ++ ++ PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1), ++ ++ PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2), ++ ++ PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3), ++ ++ PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS), ++ PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1), ++ ++ PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4), ++ PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), ++ ++ PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5), ++ PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0), ++ ++ /* IPSR10 */ ++ PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6), ++ PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD), ++ ++ PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7), ++ PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP), ++ ++ PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD), ++ PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1), ++ PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0), ++ ++ PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), ++ PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), ++ ++ PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD), ++ PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), ++ ++ PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP), ++ PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), ++ ++ PINMUX_IPSR_GPSR(IP10_27_24, SCK0), ++ PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), ++ PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), ++ PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), ++ PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2), ++ ++ PINMUX_IPSR_GPSR(IP10_31_28, RX0), ++ PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), ++ ++ /* IPSR11 */ ++ PINMUX_IPSR_GPSR(IP11_3_0, TX0), ++ PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), ++ ++ PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N), ++ PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), ++ PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), ++ PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), ++ ++ PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS), ++ PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0), ++ PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), ++ PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1), ++ ++ PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2), ++ ++ PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2), ++ ++ PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N), ++ PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), ++ ++ PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), ++ PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0), ++ ++ PINMUX_IPSR_GPSR(IP11_31_28, SCK2), ++ PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP11_31_28, ADICLK), ++ ++ /* IPSR12 */ ++ PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1), ++ PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0), ++ PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0), ++ PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2), ++ PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1), ++ ++ PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1), ++ PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0), ++ PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0), ++ PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2), ++ PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1), ++ ++ PINMUX_IPSR_GPSR(IP12_11_8, HSCK0), ++ PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0), ++ PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2), ++ ++ PINMUX_IPSR_GPSR(IP12_15_12, HRX0), ++ PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2), ++ ++ PINMUX_IPSR_GPSR(IP12_19_16, HTX0), ++ PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2), ++ ++ PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N), ++ PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2), ++ PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0), ++ ++ PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N), ++ PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0), ++ PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0), ++ ++ PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), ++ PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0), ++ ++ /* IPSR13 */ ++ PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), ++ PINMUX_IPSR_GPSR(IP13_3_0, RX5), ++ PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2), ++ PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0), ++ PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1), ++ ++ PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), ++ PINMUX_IPSR_GPSR(IP13_7_4, TX5), ++ PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0), ++ PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3), ++ PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), ++ ++ PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK), ++ PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), ++ PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1), ++ ++ PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG), ++ PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), ++ PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1), ++ ++ PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT), ++ PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239), ++ PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239), ++ PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0), ++ PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), ++ ++ /* IPSR14 */ ++ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0), ++ ++ PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), ++ ++ PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34), ++ PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), ++ ++ PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34), ++ PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), ++ ++ PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3), ++ PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4), ++ PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4), ++ PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4), ++ PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0), ++ ++ /* IPSR15 */ ++ PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6), ++ PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN), ++ PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3), ++ ++ PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6), ++ PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC), ++ PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3), ++ ++ PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6), ++ PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), ++ PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0), ++ ++ PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78), ++ PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78), ++ PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7), ++ PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0), ++ ++ PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8), ++ PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1), ++ PINMUX_IPSR_GPSR(IP15_31_28, SCK1), ++ PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_GPSR(IP15_31_28, SCK5), ++ ++ /* IPSR16 */ ++ PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), ++ PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT), ++ ++ PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0), ++ PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0), ++ ++ PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN), ++ PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1), ++ ++ PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC), ++ PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1), ++ ++ PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN), ++ PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1), ++ PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), ++ ++ PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC), ++ PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1), ++ PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1), ++ ++ PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN), ++ PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), ++ PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), ++ PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0), ++ ++ PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC), ++ PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1), ++ PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1), ++ PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1), ++ ++ /* IPSR17 */ ++ PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN), ++ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1), ++ PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2), ++ ++ PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC), ++ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1), ++ PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), ++ PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3), ++ ++/* ++ * Static pins can not be muxed between different functions but ++ * still needs a mark entry in the pinmux list. Add each static ++ * pin to the list without an associated function. The sh-pfc ++ * core will do the right thing and skip trying to mux then pin ++ * while still applying configuration to it ++ */ ++#define FM(x) PINMUX_DATA(x##_MARK, 0), ++ PINMUX_STATIC ++#undef FM ++}; ++ ++/* ++ * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. ++ * Physical layout rows: A - AW, cols: 1 - 39. ++ */ ++#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) ++#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) ++#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) ++ ++static const struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), ++ ++ /* ++ * Pins not associated with a GPIO port. ++ * ++ * The pin positions are different between different r8a7795 ++ * packages, all that is needed for the pfc driver is a unique ++ * number for each pin. To this end use the pin layout from ++ * R-Car H3SiP to calculate a unique number for each pin. ++ */ ++ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), ++}; ++ ++/* - AUDIO CLOCK ------------------------------------------------------------ */ ++static const unsigned int audio_clk_a_a_pins[] = { ++ /* CLK A */ ++ RCAR_GP_PIN(6, 22), ++}; ++static const unsigned int audio_clk_a_a_mux[] = { ++ AUDIO_CLKA_A_MARK, ++}; ++static const unsigned int audio_clk_a_b_pins[] = { ++ /* CLK A */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int audio_clk_a_b_mux[] = { ++ AUDIO_CLKA_B_MARK, ++}; ++static const unsigned int audio_clk_a_c_pins[] = { ++ /* CLK A */ ++ RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int audio_clk_a_c_mux[] = { ++ AUDIO_CLKA_C_MARK, ++}; ++static const unsigned int audio_clk_b_a_pins[] = { ++ /* CLK B */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int audio_clk_b_a_mux[] = { ++ AUDIO_CLKB_A_MARK, ++}; ++static const unsigned int audio_clk_b_b_pins[] = { ++ /* CLK B */ ++ RCAR_GP_PIN(6, 23), ++}; ++static const unsigned int audio_clk_b_b_mux[] = { ++ AUDIO_CLKB_B_MARK, ++}; ++static const unsigned int audio_clk_c_a_pins[] = { ++ /* CLK C */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int audio_clk_c_a_mux[] = { ++ AUDIO_CLKC_A_MARK, ++}; ++static const unsigned int audio_clk_c_b_pins[] = { ++ /* CLK C */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int audio_clk_c_b_mux[] = { ++ AUDIO_CLKC_B_MARK, ++}; ++static const unsigned int audio_clkout_a_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(5, 18), ++}; ++static const unsigned int audio_clkout_a_mux[] = { ++ AUDIO_CLKOUT_A_MARK, ++}; ++static const unsigned int audio_clkout_b_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(6, 28), ++}; ++static const unsigned int audio_clkout_b_mux[] = { ++ AUDIO_CLKOUT_B_MARK, ++}; ++static const unsigned int audio_clkout_c_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int audio_clkout_c_mux[] = { ++ AUDIO_CLKOUT_C_MARK, ++}; ++static const unsigned int audio_clkout_d_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int audio_clkout_d_mux[] = { ++ AUDIO_CLKOUT_D_MARK, ++}; ++static const unsigned int audio_clkout1_a_pins[] = { ++ /* CLKOUT1 */ ++ RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int audio_clkout1_a_mux[] = { ++ AUDIO_CLKOUT1_A_MARK, ++}; ++static const unsigned int audio_clkout1_b_pins[] = { ++ /* CLKOUT1 */ ++ RCAR_GP_PIN(6, 29), ++}; ++static const unsigned int audio_clkout1_b_mux[] = { ++ AUDIO_CLKOUT1_B_MARK, ++}; ++static const unsigned int audio_clkout2_a_pins[] = { ++ /* CLKOUT2 */ ++ RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int audio_clkout2_a_mux[] = { ++ AUDIO_CLKOUT2_A_MARK, ++}; ++static const unsigned int audio_clkout2_b_pins[] = { ++ /* CLKOUT2 */ ++ RCAR_GP_PIN(6, 30), ++}; ++static const unsigned int audio_clkout2_b_mux[] = { ++ AUDIO_CLKOUT2_B_MARK, ++}; ++ ++static const unsigned int audio_clkout3_a_pins[] = { ++ /* CLKOUT3 */ ++ RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int audio_clkout3_a_mux[] = { ++ AUDIO_CLKOUT3_A_MARK, ++}; ++static const unsigned int audio_clkout3_b_pins[] = { ++ /* CLKOUT3 */ ++ RCAR_GP_PIN(6, 31), ++}; ++static const unsigned int audio_clkout3_b_mux[] = { ++ AUDIO_CLKOUT3_B_MARK, ++}; ++ ++/* - EtherAVB --------------------------------------------------------------- */ ++static const unsigned int avb_link_pins[] = { ++ /* AVB_LINK */ ++ RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int avb_link_mux[] = { ++ AVB_LINK_MARK, ++}; ++static const unsigned int avb_magic_pins[] = { ++ /* AVB_MAGIC_ */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int avb_magic_mux[] = { ++ AVB_MAGIC_MARK, ++}; ++static const unsigned int avb_phy_int_pins[] = { ++ /* AVB_PHY_INT */ ++ RCAR_GP_PIN(2, 11), ++}; ++static const unsigned int avb_phy_int_mux[] = { ++ AVB_PHY_INT_MARK, ++}; ++static const unsigned int avb_mdc_pins[] = { ++ /* AVB_MDC, AVB_MDIO */ ++ RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), ++}; ++static const unsigned int avb_mdc_mux[] = { ++ AVB_MDC_MARK, AVB_MDIO_MARK, ++}; ++static const unsigned int avb_mii_pins[] = { ++ /* ++ * AVB_TX_CTL, AVB_TXC, AVB_TD0, ++ * AVB_TD1, AVB_TD2, AVB_TD3, ++ * AVB_RX_CTL, AVB_RXC, AVB_RD0, ++ * AVB_RD1, AVB_RD2, AVB_RD3, ++ * AVB_TXCREFCLK ++ */ ++ PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), ++ PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), ++ PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), ++ PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), ++ PIN_NUMBER('A', 12), ++ ++}; ++static const unsigned int avb_mii_mux[] = { ++ AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, ++ AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, ++ AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, ++ AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, ++ AVB_TXCREFCLK_MARK, ++}; ++static const unsigned int avb_avtp_pps_pins[] = { ++ /* AVB_AVTP_PPS */ ++ RCAR_GP_PIN(2, 6), ++}; ++static const unsigned int avb_avtp_pps_mux[] = { ++ AVB_AVTP_PPS_MARK, ++}; ++static const unsigned int avb_avtp_match_a_pins[] = { ++ /* AVB_AVTP_MATCH_A */ ++ RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int avb_avtp_match_a_mux[] = { ++ AVB_AVTP_MATCH_A_MARK, ++}; ++static const unsigned int avb_avtp_capture_a_pins[] = { ++ /* AVB_AVTP_CAPTURE_A */ ++ RCAR_GP_PIN(2, 14), ++}; ++static const unsigned int avb_avtp_capture_a_mux[] = { ++ AVB_AVTP_CAPTURE_A_MARK, ++}; ++static const unsigned int avb_avtp_match_b_pins[] = { ++ /* AVB_AVTP_MATCH_B */ ++ RCAR_GP_PIN(1, 8), ++}; ++static const unsigned int avb_avtp_match_b_mux[] = { ++ AVB_AVTP_MATCH_B_MARK, ++}; ++static const unsigned int avb_avtp_capture_b_pins[] = { ++ /* AVB_AVTP_CAPTURE_B */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int avb_avtp_capture_b_mux[] = { ++ AVB_AVTP_CAPTURE_B_MARK, ++}; ++ ++/* - CAN ------------------------------------------------------------------ */ ++static const unsigned int can0_data_a_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int can0_data_a_mux[] = { ++ CAN0_TX_A_MARK, CAN0_RX_A_MARK, ++}; ++static const unsigned int can0_data_b_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int can0_data_b_mux[] = { ++ CAN0_TX_B_MARK, CAN0_RX_B_MARK, ++}; ++static const unsigned int can1_data_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int can1_data_mux[] = { ++ CAN1_TX_MARK, CAN1_RX_MARK, ++}; ++ ++/* - CAN Clock -------------------------------------------------------------- */ ++static const unsigned int can_clk_pins[] = { ++ /* CLK */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int can_clk_mux[] = { ++ CAN_CLK_MARK, ++}; ++ ++/* - CAN FD --------------------------------------------------------------- */ ++static const unsigned int canfd0_data_a_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int canfd0_data_a_mux[] = { ++ CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, ++}; ++static const unsigned int canfd0_data_b_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int canfd0_data_b_mux[] = { ++ CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, ++}; ++static const unsigned int canfd1_data_pins[] = { ++ /* TX, RX */ ++ RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int canfd1_data_mux[] = { ++ CANFD1_TX_MARK, CANFD1_RX_MARK, ++}; ++ ++/* - DRIF0 --------------------------------------------------------------- */ ++static const unsigned int drif0_ctrl_a_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int drif0_ctrl_a_mux[] = { ++ RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, ++}; ++static const unsigned int drif0_data0_a_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int drif0_data0_a_mux[] = { ++ RIF0_D0_A_MARK, ++}; ++static const unsigned int drif0_data1_a_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int drif0_data1_a_mux[] = { ++ RIF0_D1_A_MARK, ++}; ++static const unsigned int drif0_ctrl_b_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int drif0_ctrl_b_mux[] = { ++ RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, ++}; ++static const unsigned int drif0_data0_b_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(5, 1), ++}; ++static const unsigned int drif0_data0_b_mux[] = { ++ RIF0_D0_B_MARK, ++}; ++static const unsigned int drif0_data1_b_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int drif0_data1_b_mux[] = { ++ RIF0_D1_B_MARK, ++}; ++static const unsigned int drif0_ctrl_c_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int drif0_ctrl_c_mux[] = { ++ RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, ++}; ++static const unsigned int drif0_data0_c_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(5, 13), ++}; ++static const unsigned int drif0_data0_c_mux[] = { ++ RIF0_D0_C_MARK, ++}; ++static const unsigned int drif0_data1_c_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int drif0_data1_c_mux[] = { ++ RIF0_D1_C_MARK, ++}; ++/* - DRIF1 --------------------------------------------------------------- */ ++static const unsigned int drif1_ctrl_a_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int drif1_ctrl_a_mux[] = { ++ RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, ++}; ++static const unsigned int drif1_data0_a_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int drif1_data0_a_mux[] = { ++ RIF1_D0_A_MARK, ++}; ++static const unsigned int drif1_data1_a_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 20), ++}; ++static const unsigned int drif1_data1_a_mux[] = { ++ RIF1_D1_A_MARK, ++}; ++static const unsigned int drif1_ctrl_b_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int drif1_ctrl_b_mux[] = { ++ RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, ++}; ++static const unsigned int drif1_data0_b_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int drif1_data0_b_mux[] = { ++ RIF1_D0_B_MARK, ++}; ++static const unsigned int drif1_data1_b_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(5, 8), ++}; ++static const unsigned int drif1_data1_b_mux[] = { ++ RIF1_D1_B_MARK, ++}; ++static const unsigned int drif1_ctrl_c_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), ++}; ++static const unsigned int drif1_ctrl_c_mux[] = { ++ RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, ++}; ++static const unsigned int drif1_data0_c_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int drif1_data0_c_mux[] = { ++ RIF1_D0_C_MARK, ++}; ++static const unsigned int drif1_data1_c_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int drif1_data1_c_mux[] = { ++ RIF1_D1_C_MARK, ++}; ++/* - DRIF2 --------------------------------------------------------------- */ ++static const unsigned int drif2_ctrl_a_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int drif2_ctrl_a_mux[] = { ++ RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, ++}; ++static const unsigned int drif2_data0_a_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int drif2_data0_a_mux[] = { ++ RIF2_D0_A_MARK, ++}; ++static const unsigned int drif2_data1_a_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int drif2_data1_a_mux[] = { ++ RIF2_D1_A_MARK, ++}; ++static const unsigned int drif2_ctrl_b_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int drif2_ctrl_b_mux[] = { ++ RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, ++}; ++static const unsigned int drif2_data0_b_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 30), ++}; ++static const unsigned int drif2_data0_b_mux[] = { ++ RIF2_D0_B_MARK, ++}; ++static const unsigned int drif2_data1_b_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 31), ++}; ++static const unsigned int drif2_data1_b_mux[] = { ++ RIF2_D1_B_MARK, ++}; ++/* - DRIF3 --------------------------------------------------------------- */ ++static const unsigned int drif3_ctrl_a_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int drif3_ctrl_a_mux[] = { ++ RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, ++}; ++static const unsigned int drif3_data0_a_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int drif3_data0_a_mux[] = { ++ RIF3_D0_A_MARK, ++}; ++static const unsigned int drif3_data1_a_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 20), ++}; ++static const unsigned int drif3_data1_a_mux[] = { ++ RIF3_D1_A_MARK, ++}; ++static const unsigned int drif3_ctrl_b_pins[] = { ++ /* CLK, SYNC */ ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), ++}; ++static const unsigned int drif3_ctrl_b_mux[] = { ++ RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, ++}; ++static const unsigned int drif3_data0_b_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(6, 28), ++}; ++static const unsigned int drif3_data0_b_mux[] = { ++ RIF3_D0_B_MARK, ++}; ++static const unsigned int drif3_data1_b_pins[] = { ++ /* D1 */ ++ RCAR_GP_PIN(6, 29), ++}; ++static const unsigned int drif3_data1_b_mux[] = { ++ RIF3_D1_B_MARK, ++}; ++ ++/* - DU --------------------------------------------------------------------- */ ++static const unsigned int du_rgb666_pins[] = { ++ /* R[7:2], G[7:2], B[7:2] */ ++ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), ++ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), ++ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), ++ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int du_rgb666_mux[] = { ++ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, ++ DU_DR3_MARK, DU_DR2_MARK, ++ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, ++ DU_DG3_MARK, DU_DG2_MARK, ++ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, ++ DU_DB3_MARK, DU_DB2_MARK, ++}; ++static const unsigned int du_rgb888_pins[] = { ++ /* R[7:0], G[7:0], B[7:0] */ ++ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), ++ RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), ++ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), ++ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), ++ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), ++ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), ++ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int du_rgb888_mux[] = { ++ DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, ++ DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, ++ DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, ++ DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, ++ DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, ++ DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, ++}; ++static const unsigned int du_clk_out_0_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(1, 27), ++}; ++static const unsigned int du_clk_out_0_mux[] = { ++ DU_DOTCLKOUT0_MARK ++}; ++static const unsigned int du_clk_out_1_pins[] = { ++ /* CLKOUT */ ++ RCAR_GP_PIN(2, 3), ++}; ++static const unsigned int du_clk_out_1_mux[] = { ++ DU_DOTCLKOUT1_MARK ++}; ++static const unsigned int du_sync_pins[] = { ++ /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ ++ RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), ++}; ++static const unsigned int du_sync_mux[] = { ++ DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK ++}; ++static const unsigned int du_oddf_pins[] = { ++ /* EXDISP/EXODDF/EXCDE */ ++ RCAR_GP_PIN(2, 2), ++}; ++static const unsigned int du_oddf_mux[] = { ++ DU_EXODDF_DU_ODDF_DISP_CDE_MARK, ++}; ++static const unsigned int du_cde_pins[] = { ++ /* CDE */ ++ RCAR_GP_PIN(2, 0), ++}; ++static const unsigned int du_cde_mux[] = { ++ DU_CDE_MARK, ++}; ++static const unsigned int du_disp_pins[] = { ++ /* DISP */ ++ RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int du_disp_mux[] = { ++ DU_DISP_MARK, ++}; ++/* - HSCIF0 ----------------------------------------------------------------- */ ++static const unsigned int hscif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int hscif0_data_mux[] = { ++ HRX0_MARK, HTX0_MARK, ++}; ++static const unsigned int hscif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int hscif0_clk_mux[] = { ++ HSCK0_MARK, ++}; ++static const unsigned int hscif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int hscif0_ctrl_mux[] = { ++ HRTS0_N_MARK, HCTS0_N_MARK, ++}; ++/* - HSCIF1 ----------------------------------------------------------------- */ ++static const unsigned int hscif1_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int hscif1_data_a_mux[] = { ++ HRX1_A_MARK, HTX1_A_MARK, ++}; ++static const unsigned int hscif1_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int hscif1_clk_a_mux[] = { ++ HSCK1_A_MARK, ++}; ++static const unsigned int hscif1_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int hscif1_ctrl_a_mux[] = { ++ HRTS1_N_A_MARK, HCTS1_N_A_MARK, ++}; ++ ++static const unsigned int hscif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int hscif1_data_b_mux[] = { ++ HRX1_B_MARK, HTX1_B_MARK, ++}; ++static const unsigned int hscif1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int hscif1_clk_b_mux[] = { ++ HSCK1_B_MARK, ++}; ++static const unsigned int hscif1_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int hscif1_ctrl_b_mux[] = { ++ HRTS1_N_B_MARK, HCTS1_N_B_MARK, ++}; ++/* - HSCIF2 ----------------------------------------------------------------- */ ++static const unsigned int hscif2_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int hscif2_data_a_mux[] = { ++ HRX2_A_MARK, HTX2_A_MARK, ++}; ++static const unsigned int hscif2_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int hscif2_clk_a_mux[] = { ++ HSCK2_A_MARK, ++}; ++static const unsigned int hscif2_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int hscif2_ctrl_a_mux[] = { ++ HRTS2_N_A_MARK, HCTS2_N_A_MARK, ++}; ++ ++static const unsigned int hscif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int hscif2_data_b_mux[] = { ++ HRX2_B_MARK, HTX2_B_MARK, ++}; ++static const unsigned int hscif2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int hscif2_clk_b_mux[] = { ++ HSCK2_B_MARK, ++}; ++static const unsigned int hscif2_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int hscif2_ctrl_b_mux[] = { ++ HRTS2_N_B_MARK, HCTS2_N_B_MARK, ++}; ++/* - HSCIF3 ----------------------------------------------------------------- */ ++static const unsigned int hscif3_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int hscif3_data_a_mux[] = { ++ HRX3_A_MARK, HTX3_A_MARK, ++}; ++static const unsigned int hscif3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int hscif3_clk_mux[] = { ++ HSCK3_MARK, ++}; ++static const unsigned int hscif3_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int hscif3_ctrl_mux[] = { ++ HRTS3_N_MARK, HCTS3_N_MARK, ++}; ++ ++static const unsigned int hscif3_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int hscif3_data_b_mux[] = { ++ HRX3_B_MARK, HTX3_B_MARK, ++}; ++static const unsigned int hscif3_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int hscif3_data_c_mux[] = { ++ HRX3_C_MARK, HTX3_C_MARK, ++}; ++static const unsigned int hscif3_data_d_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), ++}; ++static const unsigned int hscif3_data_d_mux[] = { ++ HRX3_D_MARK, HTX3_D_MARK, ++}; ++/* - HSCIF4 ----------------------------------------------------------------- */ ++static const unsigned int hscif4_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int hscif4_data_a_mux[] = { ++ HRX4_A_MARK, HTX4_A_MARK, ++}; ++static const unsigned int hscif4_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int hscif4_clk_mux[] = { ++ HSCK4_MARK, ++}; ++static const unsigned int hscif4_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), ++}; ++static const unsigned int hscif4_ctrl_mux[] = { ++ HRTS4_N_MARK, HCTS4_N_MARK, ++}; ++ ++static const unsigned int hscif4_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int hscif4_data_b_mux[] = { ++ HRX4_B_MARK, HTX4_B_MARK, ++}; ++ ++/* - I2C -------------------------------------------------------------------- */ ++static const unsigned int i2c1_a_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int i2c1_a_mux[] = { ++ SDA1_A_MARK, SCL1_A_MARK, ++}; ++static const unsigned int i2c1_b_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int i2c1_b_mux[] = { ++ SDA1_B_MARK, SCL1_B_MARK, ++}; ++static const unsigned int i2c2_a_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int i2c2_a_mux[] = { ++ SDA2_A_MARK, SCL2_A_MARK, ++}; ++static const unsigned int i2c2_b_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), ++}; ++static const unsigned int i2c2_b_mux[] = { ++ SDA2_B_MARK, SCL2_B_MARK, ++}; ++static const unsigned int i2c6_a_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int i2c6_a_mux[] = { ++ SDA6_A_MARK, SCL6_A_MARK, ++}; ++static const unsigned int i2c6_b_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int i2c6_b_mux[] = { ++ SDA6_B_MARK, SCL6_B_MARK, ++}; ++static const unsigned int i2c6_c_pins[] = { ++ /* SDA, SCL */ ++ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), ++}; ++static const unsigned int i2c6_c_mux[] = { ++ SDA6_C_MARK, SCL6_C_MARK, ++}; ++ ++/* - INTC-EX ---------------------------------------------------------------- */ ++static const unsigned int intc_ex_irq0_pins[] = { ++ /* IRQ0 */ ++ RCAR_GP_PIN(2, 0), ++}; ++static const unsigned int intc_ex_irq0_mux[] = { ++ IRQ0_MARK, ++}; ++static const unsigned int intc_ex_irq1_pins[] = { ++ /* IRQ1 */ ++ RCAR_GP_PIN(2, 1), ++}; ++static const unsigned int intc_ex_irq1_mux[] = { ++ IRQ1_MARK, ++}; ++static const unsigned int intc_ex_irq2_pins[] = { ++ /* IRQ2 */ ++ RCAR_GP_PIN(2, 2), ++}; ++static const unsigned int intc_ex_irq2_mux[] = { ++ IRQ2_MARK, ++}; ++static const unsigned int intc_ex_irq3_pins[] = { ++ /* IRQ3 */ ++ RCAR_GP_PIN(2, 3), ++}; ++static const unsigned int intc_ex_irq3_mux[] = { ++ IRQ3_MARK, ++}; ++static const unsigned int intc_ex_irq4_pins[] = { ++ /* IRQ4 */ ++ RCAR_GP_PIN(2, 4), ++}; ++static const unsigned int intc_ex_irq4_mux[] = { ++ IRQ4_MARK, ++}; ++static const unsigned int intc_ex_irq5_pins[] = { ++ /* IRQ5 */ ++ RCAR_GP_PIN(2, 5), ++}; ++static const unsigned int intc_ex_irq5_mux[] = { ++ IRQ5_MARK, ++}; ++ ++/* - MSIOF0 ----------------------------------------------------------------- */ ++static const unsigned int msiof0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 17), ++}; ++static const unsigned int msiof0_clk_mux[] = { ++ MSIOF0_SCK_MARK, ++}; ++static const unsigned int msiof0_sync_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 18), ++}; ++static const unsigned int msiof0_sync_mux[] = { ++ MSIOF0_SYNC_MARK, ++}; ++static const unsigned int msiof0_ss1_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 19), ++}; ++static const unsigned int msiof0_ss1_mux[] = { ++ MSIOF0_SS1_MARK, ++}; ++static const unsigned int msiof0_ss2_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int msiof0_ss2_mux[] = { ++ MSIOF0_SS2_MARK, ++}; ++static const unsigned int msiof0_txd_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 20), ++}; ++static const unsigned int msiof0_txd_mux[] = { ++ MSIOF0_TXD_MARK, ++}; ++static const unsigned int msiof0_rxd_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 22), ++}; ++static const unsigned int msiof0_rxd_mux[] = { ++ MSIOF0_RXD_MARK, ++}; ++/* - MSIOF1 ----------------------------------------------------------------- */ ++static const unsigned int msiof1_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 8), ++}; ++static const unsigned int msiof1_clk_a_mux[] = { ++ MSIOF1_SCK_A_MARK, ++}; ++static const unsigned int msiof1_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int msiof1_sync_a_mux[] = { ++ MSIOF1_SYNC_A_MARK, ++}; ++static const unsigned int msiof1_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 5), ++}; ++static const unsigned int msiof1_ss1_a_mux[] = { ++ MSIOF1_SS1_A_MARK, ++}; ++static const unsigned int msiof1_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int msiof1_ss2_a_mux[] = { ++ MSIOF1_SS2_A_MARK, ++}; ++static const unsigned int msiof1_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int msiof1_txd_a_mux[] = { ++ MSIOF1_TXD_A_MARK, ++}; ++static const unsigned int msiof1_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int msiof1_rxd_a_mux[] = { ++ MSIOF1_RXD_A_MARK, ++}; ++static const unsigned int msiof1_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int msiof1_clk_b_mux[] = { ++ MSIOF1_SCK_B_MARK, ++}; ++static const unsigned int msiof1_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int msiof1_sync_b_mux[] = { ++ MSIOF1_SYNC_B_MARK, ++}; ++static const unsigned int msiof1_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 4), ++}; ++static const unsigned int msiof1_ss1_b_mux[] = { ++ MSIOF1_SS1_B_MARK, ++}; ++static const unsigned int msiof1_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int msiof1_ss2_b_mux[] = { ++ MSIOF1_SS2_B_MARK, ++}; ++static const unsigned int msiof1_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 8), ++}; ++static const unsigned int msiof1_txd_b_mux[] = { ++ MSIOF1_TXD_B_MARK, ++}; ++static const unsigned int msiof1_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int msiof1_rxd_b_mux[] = { ++ MSIOF1_RXD_B_MARK, ++}; ++static const unsigned int msiof1_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 17), ++}; ++static const unsigned int msiof1_clk_c_mux[] = { ++ MSIOF1_SCK_C_MARK, ++}; ++static const unsigned int msiof1_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int msiof1_sync_c_mux[] = { ++ MSIOF1_SYNC_C_MARK, ++}; ++static const unsigned int msiof1_ss1_c_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int msiof1_ss1_c_mux[] = { ++ MSIOF1_SS1_C_MARK, ++}; ++static const unsigned int msiof1_ss2_c_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int msiof1_ss2_c_mux[] = { ++ MSIOF1_SS2_C_MARK, ++}; ++static const unsigned int msiof1_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 20), ++}; ++static const unsigned int msiof1_txd_c_mux[] = { ++ MSIOF1_TXD_C_MARK, ++}; ++static const unsigned int msiof1_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int msiof1_rxd_c_mux[] = { ++ MSIOF1_RXD_C_MARK, ++}; ++static const unsigned int msiof1_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int msiof1_clk_d_mux[] = { ++ MSIOF1_SCK_D_MARK, ++}; ++static const unsigned int msiof1_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 15), ++}; ++static const unsigned int msiof1_sync_d_mux[] = { ++ MSIOF1_SYNC_D_MARK, ++}; ++static const unsigned int msiof1_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int msiof1_ss1_d_mux[] = { ++ MSIOF1_SS1_D_MARK, ++}; ++static const unsigned int msiof1_ss2_d_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int msiof1_ss2_d_mux[] = { ++ MSIOF1_SS2_D_MARK, ++}; ++static const unsigned int msiof1_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int msiof1_txd_d_mux[] = { ++ MSIOF1_TXD_D_MARK, ++}; ++static const unsigned int msiof1_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 13), ++}; ++static const unsigned int msiof1_rxd_d_mux[] = { ++ MSIOF1_RXD_D_MARK, ++}; ++static const unsigned int msiof1_clk_e_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 0), ++}; ++static const unsigned int msiof1_clk_e_mux[] = { ++ MSIOF1_SCK_E_MARK, ++}; ++static const unsigned int msiof1_sync_e_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(3, 1), ++}; ++static const unsigned int msiof1_sync_e_mux[] = { ++ MSIOF1_SYNC_E_MARK, ++}; ++static const unsigned int msiof1_ss1_e_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(3, 4), ++}; ++static const unsigned int msiof1_ss1_e_mux[] = { ++ MSIOF1_SS1_E_MARK, ++}; ++static const unsigned int msiof1_ss2_e_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(3, 5), ++}; ++static const unsigned int msiof1_ss2_e_mux[] = { ++ MSIOF1_SS2_E_MARK, ++}; ++static const unsigned int msiof1_txd_e_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(3, 3), ++}; ++static const unsigned int msiof1_txd_e_mux[] = { ++ MSIOF1_TXD_E_MARK, ++}; ++static const unsigned int msiof1_rxd_e_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(3, 2), ++}; ++static const unsigned int msiof1_rxd_e_mux[] = { ++ MSIOF1_RXD_E_MARK, ++}; ++static const unsigned int msiof1_clk_f_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 23), ++}; ++static const unsigned int msiof1_clk_f_mux[] = { ++ MSIOF1_SCK_F_MARK, ++}; ++static const unsigned int msiof1_sync_f_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(5, 24), ++}; ++static const unsigned int msiof1_sync_f_mux[] = { ++ MSIOF1_SYNC_F_MARK, ++}; ++static const unsigned int msiof1_ss1_f_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(6, 1), ++}; ++static const unsigned int msiof1_ss1_f_mux[] = { ++ MSIOF1_SS1_F_MARK, ++}; ++static const unsigned int msiof1_ss2_f_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(6, 2), ++}; ++static const unsigned int msiof1_ss2_f_mux[] = { ++ MSIOF1_SS2_F_MARK, ++}; ++static const unsigned int msiof1_txd_f_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(6, 0), ++}; ++static const unsigned int msiof1_txd_f_mux[] = { ++ MSIOF1_TXD_F_MARK, ++}; ++static const unsigned int msiof1_rxd_f_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int msiof1_rxd_f_mux[] = { ++ MSIOF1_RXD_F_MARK, ++}; ++static const unsigned int msiof1_clk_g_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(3, 6), ++}; ++static const unsigned int msiof1_clk_g_mux[] = { ++ MSIOF1_SCK_G_MARK, ++}; ++static const unsigned int msiof1_sync_g_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int msiof1_sync_g_mux[] = { ++ MSIOF1_SYNC_G_MARK, ++}; ++static const unsigned int msiof1_ss1_g_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(3, 10), ++}; ++static const unsigned int msiof1_ss1_g_mux[] = { ++ MSIOF1_SS1_G_MARK, ++}; ++static const unsigned int msiof1_ss2_g_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(3, 11), ++}; ++static const unsigned int msiof1_ss2_g_mux[] = { ++ MSIOF1_SS2_G_MARK, ++}; ++static const unsigned int msiof1_txd_g_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(3, 9), ++}; ++static const unsigned int msiof1_txd_g_mux[] = { ++ MSIOF1_TXD_G_MARK, ++}; ++static const unsigned int msiof1_rxd_g_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(3, 8), ++}; ++static const unsigned int msiof1_rxd_g_mux[] = { ++ MSIOF1_RXD_G_MARK, ++}; ++/* - MSIOF2 ----------------------------------------------------------------- */ ++static const unsigned int msiof2_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 9), ++}; ++static const unsigned int msiof2_clk_a_mux[] = { ++ MSIOF2_SCK_A_MARK, ++}; ++static const unsigned int msiof2_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 8), ++}; ++static const unsigned int msiof2_sync_a_mux[] = { ++ MSIOF2_SYNC_A_MARK, ++}; ++static const unsigned int msiof2_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 6), ++}; ++static const unsigned int msiof2_ss1_a_mux[] = { ++ MSIOF2_SS1_A_MARK, ++}; ++static const unsigned int msiof2_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(1, 7), ++}; ++static const unsigned int msiof2_ss2_a_mux[] = { ++ MSIOF2_SS2_A_MARK, ++}; ++static const unsigned int msiof2_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int msiof2_txd_a_mux[] = { ++ MSIOF2_TXD_A_MARK, ++}; ++static const unsigned int msiof2_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 10), ++}; ++static const unsigned int msiof2_rxd_a_mux[] = { ++ MSIOF2_RXD_A_MARK, ++}; ++static const unsigned int msiof2_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 4), ++}; ++static const unsigned int msiof2_clk_b_mux[] = { ++ MSIOF2_SCK_B_MARK, ++}; ++static const unsigned int msiof2_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 5), ++}; ++static const unsigned int msiof2_sync_b_mux[] = { ++ MSIOF2_SYNC_B_MARK, ++}; ++static const unsigned int msiof2_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int msiof2_ss1_b_mux[] = { ++ MSIOF2_SS1_B_MARK, ++}; ++static const unsigned int msiof2_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 1), ++}; ++static const unsigned int msiof2_ss2_b_mux[] = { ++ MSIOF2_SS2_B_MARK, ++}; ++static const unsigned int msiof2_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 7), ++}; ++static const unsigned int msiof2_txd_b_mux[] = { ++ MSIOF2_TXD_B_MARK, ++}; ++static const unsigned int msiof2_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 6), ++}; ++static const unsigned int msiof2_rxd_b_mux[] = { ++ MSIOF2_RXD_B_MARK, ++}; ++static const unsigned int msiof2_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int msiof2_clk_c_mux[] = { ++ MSIOF2_SCK_C_MARK, ++}; ++static const unsigned int msiof2_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(2, 11), ++}; ++static const unsigned int msiof2_sync_c_mux[] = { ++ MSIOF2_SYNC_C_MARK, ++}; ++static const unsigned int msiof2_ss1_c_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int msiof2_ss1_c_mux[] = { ++ MSIOF2_SS1_C_MARK, ++}; ++static const unsigned int msiof2_ss2_c_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(2, 9), ++}; ++static const unsigned int msiof2_ss2_c_mux[] = { ++ MSIOF2_SS2_C_MARK, ++}; ++static const unsigned int msiof2_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(2, 14), ++}; ++static const unsigned int msiof2_txd_c_mux[] = { ++ MSIOF2_TXD_C_MARK, ++}; ++static const unsigned int msiof2_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int msiof2_rxd_c_mux[] = { ++ MSIOF2_RXD_C_MARK, ++}; ++static const unsigned int msiof2_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 8), ++}; ++static const unsigned int msiof2_clk_d_mux[] = { ++ MSIOF2_SCK_D_MARK, ++}; ++static const unsigned int msiof2_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 9), ++}; ++static const unsigned int msiof2_sync_d_mux[] = { ++ MSIOF2_SYNC_D_MARK, ++}; ++static const unsigned int msiof2_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 12), ++}; ++static const unsigned int msiof2_ss1_d_mux[] = { ++ MSIOF2_SS1_D_MARK, ++}; ++static const unsigned int msiof2_ss2_d_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int msiof2_ss2_d_mux[] = { ++ MSIOF2_SS2_D_MARK, ++}; ++static const unsigned int msiof2_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 11), ++}; ++static const unsigned int msiof2_txd_d_mux[] = { ++ MSIOF2_TXD_D_MARK, ++}; ++static const unsigned int msiof2_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int msiof2_rxd_d_mux[] = { ++ MSIOF2_RXD_D_MARK, ++}; ++/* - MSIOF3 ----------------------------------------------------------------- */ ++static const unsigned int msiof3_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 0), ++}; ++static const unsigned int msiof3_clk_a_mux[] = { ++ MSIOF3_SCK_A_MARK, ++}; ++static const unsigned int msiof3_sync_a_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(0, 1), ++}; ++static const unsigned int msiof3_sync_a_mux[] = { ++ MSIOF3_SYNC_A_MARK, ++}; ++static const unsigned int msiof3_ss1_a_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(0, 14), ++}; ++static const unsigned int msiof3_ss1_a_mux[] = { ++ MSIOF3_SS1_A_MARK, ++}; ++static const unsigned int msiof3_ss2_a_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(0, 15), ++}; ++static const unsigned int msiof3_ss2_a_mux[] = { ++ MSIOF3_SS2_A_MARK, ++}; ++static const unsigned int msiof3_txd_a_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(0, 3), ++}; ++static const unsigned int msiof3_txd_a_mux[] = { ++ MSIOF3_TXD_A_MARK, ++}; ++static const unsigned int msiof3_rxd_a_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(0, 2), ++}; ++static const unsigned int msiof3_rxd_a_mux[] = { ++ MSIOF3_RXD_A_MARK, ++}; ++static const unsigned int msiof3_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int msiof3_clk_b_mux[] = { ++ MSIOF3_SCK_B_MARK, ++}; ++static const unsigned int msiof3_sync_b_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int msiof3_sync_b_mux[] = { ++ MSIOF3_SYNC_B_MARK, ++}; ++static const unsigned int msiof3_ss1_b_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 4), ++}; ++static const unsigned int msiof3_ss1_b_mux[] = { ++ MSIOF3_SS1_B_MARK, ++}; ++static const unsigned int msiof3_ss2_b_pins[] = { ++ /* SS2 */ ++ RCAR_GP_PIN(1, 5), ++}; ++static const unsigned int msiof3_ss2_b_mux[] = { ++ MSIOF3_SS2_B_MARK, ++}; ++static const unsigned int msiof3_txd_b_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 1), ++}; ++static const unsigned int msiof3_txd_b_mux[] = { ++ MSIOF3_TXD_B_MARK, ++}; ++static const unsigned int msiof3_rxd_b_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 3), ++}; ++static const unsigned int msiof3_rxd_b_mux[] = { ++ MSIOF3_RXD_B_MARK, ++}; ++static const unsigned int msiof3_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 12), ++}; ++static const unsigned int msiof3_clk_c_mux[] = { ++ MSIOF3_SCK_C_MARK, ++}; ++static const unsigned int msiof3_sync_c_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 13), ++}; ++static const unsigned int msiof3_sync_c_mux[] = { ++ MSIOF3_SYNC_C_MARK, ++}; ++static const unsigned int msiof3_txd_c_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 15), ++}; ++static const unsigned int msiof3_txd_c_mux[] = { ++ MSIOF3_TXD_C_MARK, ++}; ++static const unsigned int msiof3_rxd_c_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 14), ++}; ++static const unsigned int msiof3_rxd_c_mux[] = { ++ MSIOF3_RXD_C_MARK, ++}; ++static const unsigned int msiof3_clk_d_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int msiof3_clk_d_mux[] = { ++ MSIOF3_SCK_D_MARK, ++}; ++static const unsigned int msiof3_sync_d_pins[] = { ++ /* SYNC */ ++ RCAR_GP_PIN(1, 23), ++}; ++static const unsigned int msiof3_sync_d_mux[] = { ++ MSIOF3_SYNC_D_MARK, ++}; ++static const unsigned int msiof3_ss1_d_pins[] = { ++ /* SS1 */ ++ RCAR_GP_PIN(1, 26), ++}; ++static const unsigned int msiof3_ss1_d_mux[] = { ++ MSIOF3_SS1_D_MARK, ++}; ++static const unsigned int msiof3_txd_d_pins[] = { ++ /* TXD */ ++ RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int msiof3_txd_d_mux[] = { ++ MSIOF3_TXD_D_MARK, ++}; ++static const unsigned int msiof3_rxd_d_pins[] = { ++ /* RXD */ ++ RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int msiof3_rxd_d_mux[] = { ++ MSIOF3_RXD_D_MARK, ++}; ++ ++/* - PWM0 --------------------------------------------------------------------*/ ++static const unsigned int pwm0_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 6), ++}; ++static const unsigned int pwm0_mux[] = { ++ PWM0_MARK, ++}; ++/* - PWM1 --------------------------------------------------------------------*/ ++static const unsigned int pwm1_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 7), ++}; ++static const unsigned int pwm1_a_mux[] = { ++ PWM1_A_MARK, ++}; ++static const unsigned int pwm1_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 8), ++}; ++static const unsigned int pwm1_b_mux[] = { ++ PWM1_B_MARK, ++}; ++/* - PWM2 --------------------------------------------------------------------*/ ++static const unsigned int pwm2_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 8), ++}; ++static const unsigned int pwm2_a_mux[] = { ++ PWM2_A_MARK, ++}; ++static const unsigned int pwm2_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int pwm2_b_mux[] = { ++ PWM2_B_MARK, ++}; ++/* - PWM3 --------------------------------------------------------------------*/ ++static const unsigned int pwm3_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 0), ++}; ++static const unsigned int pwm3_a_mux[] = { ++ PWM3_A_MARK, ++}; ++static const unsigned int pwm3_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 2), ++}; ++static const unsigned int pwm3_b_mux[] = { ++ PWM3_B_MARK, ++}; ++/* - PWM4 --------------------------------------------------------------------*/ ++static const unsigned int pwm4_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 1), ++}; ++static const unsigned int pwm4_a_mux[] = { ++ PWM4_A_MARK, ++}; ++static const unsigned int pwm4_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 3), ++}; ++static const unsigned int pwm4_b_mux[] = { ++ PWM4_B_MARK, ++}; ++/* - PWM5 --------------------------------------------------------------------*/ ++static const unsigned int pwm5_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 2), ++}; ++static const unsigned int pwm5_a_mux[] = { ++ PWM5_A_MARK, ++}; ++static const unsigned int pwm5_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 4), ++}; ++static const unsigned int pwm5_b_mux[] = { ++ PWM5_B_MARK, ++}; ++/* - PWM6 --------------------------------------------------------------------*/ ++static const unsigned int pwm6_a_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(1, 3), ++}; ++static const unsigned int pwm6_a_mux[] = { ++ PWM6_A_MARK, ++}; ++static const unsigned int pwm6_b_pins[] = { ++ /* PWM */ ++ RCAR_GP_PIN(2, 5), ++}; ++static const unsigned int pwm6_b_mux[] = { ++ PWM6_B_MARK, ++}; ++ ++/* - QSPI0 ------------------------------------------------------------------ */ ++static const unsigned int qspi0_ctrl_pins[] = { ++ /* QSPI0_SPCLK, QSPI0_SSL */ ++ PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), ++}; ++static const unsigned int qspi0_ctrl_mux[] = { ++ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, ++}; ++static const unsigned int qspi0_data2_pins[] = { ++ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ ++ PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), ++}; ++static const unsigned int qspi0_data2_mux[] = { ++ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, ++}; ++static const unsigned int qspi0_data4_pins[] = { ++ /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ ++ PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), ++ PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), ++}; ++static const unsigned int qspi0_data4_mux[] = { ++ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, ++ QSPI0_IO2_MARK, QSPI0_IO3_MARK, ++}; ++/* - QSPI1 ------------------------------------------------------------------ */ ++static const unsigned int qspi1_ctrl_pins[] = { ++ /* QSPI1_SPCLK, QSPI1_SSL */ ++ PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), ++}; ++static const unsigned int qspi1_ctrl_mux[] = { ++ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, ++}; ++static const unsigned int qspi1_data2_pins[] = { ++ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ ++ PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), ++}; ++static const unsigned int qspi1_data2_mux[] = { ++ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, ++}; ++static const unsigned int qspi1_data4_pins[] = { ++ /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ ++ PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), ++ PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), ++}; ++static const unsigned int qspi1_data4_mux[] = { ++ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, ++ QSPI1_IO2_MARK, QSPI1_IO3_MARK, ++}; ++ ++/* - SATA --------------------------------------------------------------------*/ ++static const unsigned int sata0_devslp_a_pins[] = { ++ /* DEVSLP */ ++ RCAR_GP_PIN(6, 16), ++}; ++static const unsigned int sata0_devslp_a_mux[] = { ++ SATA_DEVSLP_A_MARK, ++}; ++static const unsigned int sata0_devslp_b_pins[] = { ++ /* DEVSLP */ ++ RCAR_GP_PIN(4, 6), ++}; ++static const unsigned int sata0_devslp_b_mux[] = { ++ SATA_DEVSLP_B_MARK, ++}; ++ ++/* - SCIF0 ------------------------------------------------------------------ */ ++static const unsigned int scif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scif0_data_mux[] = { ++ RX0_MARK, TX0_MARK, ++}; ++static const unsigned int scif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int scif0_clk_mux[] = { ++ SCK0_MARK, ++}; ++static const unsigned int scif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int scif0_ctrl_mux[] = { ++ RTS0_N_TANS_MARK, CTS0_N_MARK, ++}; ++/* - SCIF1 ------------------------------------------------------------------ */ ++static const unsigned int scif1_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int scif1_data_a_mux[] = { ++ RX1_A_MARK, TX1_A_MARK, ++}; ++static const unsigned int scif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int scif1_clk_mux[] = { ++ SCK1_MARK, ++}; ++static const unsigned int scif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int scif1_ctrl_mux[] = { ++ RTS1_N_TANS_MARK, CTS1_N_MARK, ++}; ++ ++static const unsigned int scif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int scif1_data_b_mux[] = { ++ RX1_B_MARK, TX1_B_MARK, ++}; ++/* - SCIF2 ------------------------------------------------------------------ */ ++static const unsigned int scif2_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int scif2_data_a_mux[] = { ++ RX2_A_MARK, TX2_A_MARK, ++}; ++static const unsigned int scif2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int scif2_clk_mux[] = { ++ SCK2_MARK, ++}; ++static const unsigned int scif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int scif2_data_b_mux[] = { ++ RX2_B_MARK, TX2_B_MARK, ++}; ++/* - SCIF3 ------------------------------------------------------------------ */ ++static const unsigned int scif3_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int scif3_data_a_mux[] = { ++ RX3_A_MARK, TX3_A_MARK, ++}; ++static const unsigned int scif3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int scif3_clk_mux[] = { ++ SCK3_MARK, ++}; ++static const unsigned int scif3_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int scif3_ctrl_mux[] = { ++ RTS3_N_TANS_MARK, CTS3_N_MARK, ++}; ++static const unsigned int scif3_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int scif3_data_b_mux[] = { ++ RX3_B_MARK, TX3_B_MARK, ++}; ++/* - SCIF4 ------------------------------------------------------------------ */ ++static const unsigned int scif4_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int scif4_data_a_mux[] = { ++ RX4_A_MARK, TX4_A_MARK, ++}; ++static const unsigned int scif4_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int scif4_clk_a_mux[] = { ++ SCK4_A_MARK, ++}; ++static const unsigned int scif4_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int scif4_ctrl_a_mux[] = { ++ RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, ++}; ++static const unsigned int scif4_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), ++}; ++static const unsigned int scif4_data_b_mux[] = { ++ RX4_B_MARK, TX4_B_MARK, ++}; ++static const unsigned int scif4_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 5), ++}; ++static const unsigned int scif4_clk_b_mux[] = { ++ SCK4_B_MARK, ++}; ++static const unsigned int scif4_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), ++}; ++static const unsigned int scif4_ctrl_b_mux[] = { ++ RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, ++}; ++static const unsigned int scif4_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int scif4_data_c_mux[] = { ++ RX4_C_MARK, TX4_C_MARK, ++}; ++static const unsigned int scif4_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 8), ++}; ++static const unsigned int scif4_clk_c_mux[] = { ++ SCK4_C_MARK, ++}; ++static const unsigned int scif4_ctrl_c_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int scif4_ctrl_c_mux[] = { ++ RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, ++}; ++/* - SCIF5 ------------------------------------------------------------------ */ ++static const unsigned int scif5_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int scif5_data_mux[] = { ++ RX5_MARK, TX5_MARK, ++}; ++static const unsigned int scif5_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int scif5_clk_mux[] = { ++ SCK5_MARK, ++}; ++ ++/* - SCIF Clock ------------------------------------------------------------- */ ++static const unsigned int scif_clk_a_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(6, 23), ++}; ++static const unsigned int scif_clk_a_mux[] = { ++ SCIF_CLK_A_MARK, ++}; ++static const unsigned int scif_clk_b_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int scif_clk_b_mux[] = { ++ SCIF_CLK_B_MARK, ++}; ++ ++/* - SDHI0 ------------------------------------------------------------------ */ ++static const unsigned int sdhi0_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 2), ++}; ++static const unsigned int sdhi0_data1_mux[] = { ++ SD0_DAT0_MARK, ++}; ++static const unsigned int sdhi0_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), ++ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), ++}; ++static const unsigned int sdhi0_data4_mux[] = { ++ SD0_DAT0_MARK, SD0_DAT1_MARK, ++ SD0_DAT2_MARK, SD0_DAT3_MARK, ++}; ++static const unsigned int sdhi0_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), ++}; ++static const unsigned int sdhi0_ctrl_mux[] = { ++ SD0_CLK_MARK, SD0_CMD_MARK, ++}; ++static const unsigned int sdhi0_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 12), ++}; ++static const unsigned int sdhi0_cd_mux[] = { ++ SD0_CD_MARK, ++}; ++static const unsigned int sdhi0_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 13), ++}; ++static const unsigned int sdhi0_wp_mux[] = { ++ SD0_WP_MARK, ++}; ++/* - SDHI1 ------------------------------------------------------------------ */ ++static const unsigned int sdhi1_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(3, 8), ++}; ++static const unsigned int sdhi1_data1_mux[] = { ++ SD1_DAT0_MARK, ++}; ++static const unsigned int sdhi1_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), ++}; ++static const unsigned int sdhi1_data4_mux[] = { ++ SD1_DAT0_MARK, SD1_DAT1_MARK, ++ SD1_DAT2_MARK, SD1_DAT3_MARK, ++}; ++static const unsigned int sdhi1_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), ++}; ++static const unsigned int sdhi1_ctrl_mux[] = { ++ SD1_CLK_MARK, SD1_CMD_MARK, ++}; ++static const unsigned int sdhi1_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(3, 14), ++}; ++static const unsigned int sdhi1_cd_mux[] = { ++ SD1_CD_MARK, ++}; ++static const unsigned int sdhi1_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(3, 15), ++}; ++static const unsigned int sdhi1_wp_mux[] = { ++ SD1_WP_MARK, ++}; ++/* - SDHI2 ------------------------------------------------------------------ */ ++static const unsigned int sdhi2_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(4, 2), ++}; ++static const unsigned int sdhi2_data1_mux[] = { ++ SD2_DAT0_MARK, ++}; ++static const unsigned int sdhi2_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), ++ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), ++}; ++static const unsigned int sdhi2_data4_mux[] = { ++ SD2_DAT0_MARK, SD2_DAT1_MARK, ++ SD2_DAT2_MARK, SD2_DAT3_MARK, ++}; ++static const unsigned int sdhi2_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), ++ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), ++ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), ++ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), ++}; ++static const unsigned int sdhi2_data8_mux[] = { ++ SD2_DAT0_MARK, SD2_DAT1_MARK, ++ SD2_DAT2_MARK, SD2_DAT3_MARK, ++ SD2_DAT4_MARK, SD2_DAT5_MARK, ++ SD2_DAT6_MARK, SD2_DAT7_MARK, ++}; ++static const unsigned int sdhi2_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), ++}; ++static const unsigned int sdhi2_ctrl_mux[] = { ++ SD2_CLK_MARK, SD2_CMD_MARK, ++}; ++static const unsigned int sdhi2_cd_a_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(4, 13), ++}; ++static const unsigned int sdhi2_cd_a_mux[] = { ++ SD2_CD_A_MARK, ++}; ++static const unsigned int sdhi2_cd_b_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int sdhi2_cd_b_mux[] = { ++ SD2_CD_B_MARK, ++}; ++static const unsigned int sdhi2_wp_a_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(4, 14), ++}; ++static const unsigned int sdhi2_wp_a_mux[] = { ++ SD2_WP_A_MARK, ++}; ++static const unsigned int sdhi2_wp_b_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(5, 11), ++}; ++static const unsigned int sdhi2_wp_b_mux[] = { ++ SD2_WP_B_MARK, ++}; ++static const unsigned int sdhi2_ds_pins[] = { ++ /* DS */ ++ RCAR_GP_PIN(4, 6), ++}; ++static const unsigned int sdhi2_ds_mux[] = { ++ SD2_DS_MARK, ++}; ++/* - SDHI3 ------------------------------------------------------------------ */ ++static const unsigned int sdhi3_data1_pins[] = { ++ /* D0 */ ++ RCAR_GP_PIN(4, 9), ++}; ++static const unsigned int sdhi3_data1_mux[] = { ++ SD3_DAT0_MARK, ++}; ++static const unsigned int sdhi3_data4_pins[] = { ++ /* D[0:3] */ ++ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), ++ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), ++}; ++static const unsigned int sdhi3_data4_mux[] = { ++ SD3_DAT0_MARK, SD3_DAT1_MARK, ++ SD3_DAT2_MARK, SD3_DAT3_MARK, ++}; ++static const unsigned int sdhi3_data8_pins[] = { ++ /* D[0:7] */ ++ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), ++ RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), ++ RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), ++ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), ++}; ++static const unsigned int sdhi3_data8_mux[] = { ++ SD3_DAT0_MARK, SD3_DAT1_MARK, ++ SD3_DAT2_MARK, SD3_DAT3_MARK, ++ SD3_DAT4_MARK, SD3_DAT5_MARK, ++ SD3_DAT6_MARK, SD3_DAT7_MARK, ++}; ++static const unsigned int sdhi3_ctrl_pins[] = { ++ /* CLK, CMD */ ++ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), ++}; ++static const unsigned int sdhi3_ctrl_mux[] = { ++ SD3_CLK_MARK, SD3_CMD_MARK, ++}; ++static const unsigned int sdhi3_cd_pins[] = { ++ /* CD */ ++ RCAR_GP_PIN(4, 15), ++}; ++static const unsigned int sdhi3_cd_mux[] = { ++ SD3_CD_MARK, ++}; ++static const unsigned int sdhi3_wp_pins[] = { ++ /* WP */ ++ RCAR_GP_PIN(4, 16), ++}; ++static const unsigned int sdhi3_wp_mux[] = { ++ SD3_WP_MARK, ++}; ++static const unsigned int sdhi3_ds_pins[] = { ++ /* DS */ ++ RCAR_GP_PIN(4, 17), ++}; ++static const unsigned int sdhi3_ds_mux[] = { ++ SD3_DS_MARK, ++}; ++ ++/* - SSI -------------------------------------------------------------------- */ ++static const unsigned int ssi0_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 2), ++}; ++static const unsigned int ssi0_data_mux[] = { ++ SSI_SDATA0_MARK, ++}; ++static const unsigned int ssi01239_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), ++}; ++static const unsigned int ssi01239_ctrl_mux[] = { ++ SSI_SCK01239_MARK, SSI_WS01239_MARK, ++}; ++static const unsigned int ssi1_data_a_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 3), ++}; ++static const unsigned int ssi1_data_a_mux[] = { ++ SSI_SDATA1_A_MARK, ++}; ++static const unsigned int ssi1_data_b_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(5, 12), ++}; ++static const unsigned int ssi1_data_b_mux[] = { ++ SSI_SDATA1_B_MARK, ++}; ++static const unsigned int ssi1_ctrl_a_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int ssi1_ctrl_a_mux[] = { ++ SSI_SCK1_A_MARK, SSI_WS1_A_MARK, ++}; ++static const unsigned int ssi1_ctrl_b_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int ssi1_ctrl_b_mux[] = { ++ SSI_SCK1_B_MARK, SSI_WS1_B_MARK, ++}; ++static const unsigned int ssi2_data_a_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 4), ++}; ++static const unsigned int ssi2_data_a_mux[] = { ++ SSI_SDATA2_A_MARK, ++}; ++static const unsigned int ssi2_data_b_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(5, 13), ++}; ++static const unsigned int ssi2_data_b_mux[] = { ++ SSI_SDATA2_B_MARK, ++}; ++static const unsigned int ssi2_ctrl_a_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int ssi2_ctrl_a_mux[] = { ++ SSI_SCK2_A_MARK, SSI_WS2_A_MARK, ++}; ++static const unsigned int ssi2_ctrl_b_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), ++}; ++static const unsigned int ssi2_ctrl_b_mux[] = { ++ SSI_SCK2_B_MARK, SSI_WS2_B_MARK, ++}; ++static const unsigned int ssi3_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 7), ++}; ++static const unsigned int ssi3_data_mux[] = { ++ SSI_SDATA3_MARK, ++}; ++static const unsigned int ssi34_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), ++}; ++static const unsigned int ssi34_ctrl_mux[] = { ++ SSI_SCK34_MARK, SSI_WS34_MARK, ++}; ++static const unsigned int ssi4_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 10), ++}; ++static const unsigned int ssi4_data_mux[] = { ++ SSI_SDATA4_MARK, ++}; ++static const unsigned int ssi4_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), ++}; ++static const unsigned int ssi4_ctrl_mux[] = { ++ SSI_SCK4_MARK, SSI_WS4_MARK, ++}; ++static const unsigned int ssi5_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 13), ++}; ++static const unsigned int ssi5_data_mux[] = { ++ SSI_SDATA5_MARK, ++}; ++static const unsigned int ssi5_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), ++}; ++static const unsigned int ssi5_ctrl_mux[] = { ++ SSI_SCK5_MARK, SSI_WS5_MARK, ++}; ++static const unsigned int ssi6_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 16), ++}; ++static const unsigned int ssi6_data_mux[] = { ++ SSI_SDATA6_MARK, ++}; ++static const unsigned int ssi6_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), ++}; ++static const unsigned int ssi6_ctrl_mux[] = { ++ SSI_SCK6_MARK, SSI_WS6_MARK, ++}; ++static const unsigned int ssi7_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 19), ++}; ++static const unsigned int ssi7_data_mux[] = { ++ SSI_SDATA7_MARK, ++}; ++static const unsigned int ssi78_ctrl_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), ++}; ++static const unsigned int ssi78_ctrl_mux[] = { ++ SSI_SCK78_MARK, SSI_WS78_MARK, ++}; ++static const unsigned int ssi8_data_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 20), ++}; ++static const unsigned int ssi8_data_mux[] = { ++ SSI_SDATA8_MARK, ++}; ++static const unsigned int ssi9_data_a_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int ssi9_data_a_mux[] = { ++ SSI_SDATA9_A_MARK, ++}; ++static const unsigned int ssi9_data_b_pins[] = { ++ /* SDATA */ ++ RCAR_GP_PIN(5, 14), ++}; ++static const unsigned int ssi9_data_b_mux[] = { ++ SSI_SDATA9_B_MARK, ++}; ++static const unsigned int ssi9_ctrl_a_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int ssi9_ctrl_a_mux[] = { ++ SSI_SCK9_A_MARK, SSI_WS9_A_MARK, ++}; ++static const unsigned int ssi9_ctrl_b_pins[] = { ++ /* SCK, WS */ ++ RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), ++}; ++static const unsigned int ssi9_ctrl_b_mux[] = { ++ SSI_SCK9_B_MARK, SSI_WS9_B_MARK, ++}; ++ ++/* - USB0 ------------------------------------------------------------------- */ ++static const unsigned int usb0_pins[] = { ++ /* PWEN, OVC */ ++ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), ++}; ++static const unsigned int usb0_mux[] = { ++ USB0_PWEN_MARK, USB0_OVC_MARK, ++}; ++/* - USB1 ------------------------------------------------------------------- */ ++static const unsigned int usb1_pins[] = { ++ /* PWEN, OVC */ ++ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), ++}; ++static const unsigned int usb1_mux[] = { ++ USB1_PWEN_MARK, USB1_OVC_MARK, ++}; ++/* - USB2 ------------------------------------------------------------------- */ ++static const unsigned int usb2_pins[] = { ++ /* PWEN, OVC */ ++ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), ++}; ++static const unsigned int usb2_mux[] = { ++ USB2_PWEN_MARK, USB2_OVC_MARK, ++}; ++ ++static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(audio_clk_a_a), ++ SH_PFC_PIN_GROUP(audio_clk_a_b), ++ SH_PFC_PIN_GROUP(audio_clk_a_c), ++ SH_PFC_PIN_GROUP(audio_clk_b_a), ++ SH_PFC_PIN_GROUP(audio_clk_b_b), ++ SH_PFC_PIN_GROUP(audio_clk_c_a), ++ SH_PFC_PIN_GROUP(audio_clk_c_b), ++ SH_PFC_PIN_GROUP(audio_clkout_a), ++ SH_PFC_PIN_GROUP(audio_clkout_b), ++ SH_PFC_PIN_GROUP(audio_clkout_c), ++ SH_PFC_PIN_GROUP(audio_clkout_d), ++ SH_PFC_PIN_GROUP(audio_clkout1_a), ++ SH_PFC_PIN_GROUP(audio_clkout1_b), ++ SH_PFC_PIN_GROUP(audio_clkout2_a), ++ SH_PFC_PIN_GROUP(audio_clkout2_b), ++ SH_PFC_PIN_GROUP(audio_clkout3_a), ++ SH_PFC_PIN_GROUP(audio_clkout3_b), ++ SH_PFC_PIN_GROUP(avb_link), ++ SH_PFC_PIN_GROUP(avb_magic), ++ SH_PFC_PIN_GROUP(avb_phy_int), ++ SH_PFC_PIN_GROUP(avb_mdc), ++ SH_PFC_PIN_GROUP(avb_mii), ++ SH_PFC_PIN_GROUP(avb_avtp_pps), ++ SH_PFC_PIN_GROUP(avb_avtp_match_a), ++ SH_PFC_PIN_GROUP(avb_avtp_capture_a), ++ SH_PFC_PIN_GROUP(avb_avtp_match_b), ++ SH_PFC_PIN_GROUP(avb_avtp_capture_b), ++ SH_PFC_PIN_GROUP(can0_data_a), ++ SH_PFC_PIN_GROUP(can0_data_b), ++ SH_PFC_PIN_GROUP(can1_data), ++ SH_PFC_PIN_GROUP(can_clk), ++ SH_PFC_PIN_GROUP(canfd0_data_a), ++ SH_PFC_PIN_GROUP(canfd0_data_b), ++ SH_PFC_PIN_GROUP(canfd1_data), ++ SH_PFC_PIN_GROUP(drif0_ctrl_a), ++ SH_PFC_PIN_GROUP(drif0_data0_a), ++ SH_PFC_PIN_GROUP(drif0_data1_a), ++ SH_PFC_PIN_GROUP(drif0_ctrl_b), ++ SH_PFC_PIN_GROUP(drif0_data0_b), ++ SH_PFC_PIN_GROUP(drif0_data1_b), ++ SH_PFC_PIN_GROUP(drif0_ctrl_c), ++ SH_PFC_PIN_GROUP(drif0_data0_c), ++ SH_PFC_PIN_GROUP(drif0_data1_c), ++ SH_PFC_PIN_GROUP(drif1_ctrl_a), ++ SH_PFC_PIN_GROUP(drif1_data0_a), ++ SH_PFC_PIN_GROUP(drif1_data1_a), ++ SH_PFC_PIN_GROUP(drif1_ctrl_b), ++ SH_PFC_PIN_GROUP(drif1_data0_b), ++ SH_PFC_PIN_GROUP(drif1_data1_b), ++ SH_PFC_PIN_GROUP(drif1_ctrl_c), ++ SH_PFC_PIN_GROUP(drif1_data0_c), ++ SH_PFC_PIN_GROUP(drif1_data1_c), ++ SH_PFC_PIN_GROUP(drif2_ctrl_a), ++ SH_PFC_PIN_GROUP(drif2_data0_a), ++ SH_PFC_PIN_GROUP(drif2_data1_a), ++ SH_PFC_PIN_GROUP(drif2_ctrl_b), ++ SH_PFC_PIN_GROUP(drif2_data0_b), ++ SH_PFC_PIN_GROUP(drif2_data1_b), ++ SH_PFC_PIN_GROUP(drif3_ctrl_a), ++ SH_PFC_PIN_GROUP(drif3_data0_a), ++ SH_PFC_PIN_GROUP(drif3_data1_a), ++ SH_PFC_PIN_GROUP(drif3_ctrl_b), ++ SH_PFC_PIN_GROUP(drif3_data0_b), ++ SH_PFC_PIN_GROUP(drif3_data1_b), ++ SH_PFC_PIN_GROUP(du_rgb666), ++ SH_PFC_PIN_GROUP(du_rgb888), ++ SH_PFC_PIN_GROUP(du_clk_out_0), ++ SH_PFC_PIN_GROUP(du_clk_out_1), ++ SH_PFC_PIN_GROUP(du_sync), ++ SH_PFC_PIN_GROUP(du_oddf), ++ SH_PFC_PIN_GROUP(du_cde), ++ SH_PFC_PIN_GROUP(du_disp), ++ SH_PFC_PIN_GROUP(hscif0_data), ++ SH_PFC_PIN_GROUP(hscif0_clk), ++ SH_PFC_PIN_GROUP(hscif0_ctrl), ++ SH_PFC_PIN_GROUP(hscif1_data_a), ++ SH_PFC_PIN_GROUP(hscif1_clk_a), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif1_data_b), ++ SH_PFC_PIN_GROUP(hscif1_clk_b), ++ SH_PFC_PIN_GROUP(hscif1_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif2_data_a), ++ SH_PFC_PIN_GROUP(hscif2_clk_a), ++ SH_PFC_PIN_GROUP(hscif2_ctrl_a), ++ SH_PFC_PIN_GROUP(hscif2_data_b), ++ SH_PFC_PIN_GROUP(hscif2_clk_b), ++ SH_PFC_PIN_GROUP(hscif2_ctrl_b), ++ SH_PFC_PIN_GROUP(hscif3_data_a), ++ SH_PFC_PIN_GROUP(hscif3_clk), ++ SH_PFC_PIN_GROUP(hscif3_ctrl), ++ SH_PFC_PIN_GROUP(hscif3_data_b), ++ SH_PFC_PIN_GROUP(hscif3_data_c), ++ SH_PFC_PIN_GROUP(hscif3_data_d), ++ SH_PFC_PIN_GROUP(hscif4_data_a), ++ SH_PFC_PIN_GROUP(hscif4_clk), ++ SH_PFC_PIN_GROUP(hscif4_ctrl), ++ SH_PFC_PIN_GROUP(hscif4_data_b), ++ SH_PFC_PIN_GROUP(i2c1_a), ++ SH_PFC_PIN_GROUP(i2c1_b), ++ SH_PFC_PIN_GROUP(i2c2_a), ++ SH_PFC_PIN_GROUP(i2c2_b), ++ SH_PFC_PIN_GROUP(i2c6_a), ++ SH_PFC_PIN_GROUP(i2c6_b), ++ SH_PFC_PIN_GROUP(i2c6_c), ++ SH_PFC_PIN_GROUP(intc_ex_irq0), ++ SH_PFC_PIN_GROUP(intc_ex_irq1), ++ SH_PFC_PIN_GROUP(intc_ex_irq2), ++ SH_PFC_PIN_GROUP(intc_ex_irq3), ++ SH_PFC_PIN_GROUP(intc_ex_irq4), ++ SH_PFC_PIN_GROUP(intc_ex_irq5), ++ SH_PFC_PIN_GROUP(msiof0_clk), ++ SH_PFC_PIN_GROUP(msiof0_sync), ++ SH_PFC_PIN_GROUP(msiof0_ss1), ++ SH_PFC_PIN_GROUP(msiof0_ss2), ++ SH_PFC_PIN_GROUP(msiof0_txd), ++ SH_PFC_PIN_GROUP(msiof0_rxd), ++ SH_PFC_PIN_GROUP(msiof1_clk_a), ++ SH_PFC_PIN_GROUP(msiof1_sync_a), ++ SH_PFC_PIN_GROUP(msiof1_ss1_a), ++ SH_PFC_PIN_GROUP(msiof1_ss2_a), ++ SH_PFC_PIN_GROUP(msiof1_txd_a), ++ SH_PFC_PIN_GROUP(msiof1_rxd_a), ++ SH_PFC_PIN_GROUP(msiof1_clk_b), ++ SH_PFC_PIN_GROUP(msiof1_sync_b), ++ SH_PFC_PIN_GROUP(msiof1_ss1_b), ++ SH_PFC_PIN_GROUP(msiof1_ss2_b), ++ SH_PFC_PIN_GROUP(msiof1_txd_b), ++ SH_PFC_PIN_GROUP(msiof1_rxd_b), ++ SH_PFC_PIN_GROUP(msiof1_clk_c), ++ SH_PFC_PIN_GROUP(msiof1_sync_c), ++ SH_PFC_PIN_GROUP(msiof1_ss1_c), ++ SH_PFC_PIN_GROUP(msiof1_ss2_c), ++ SH_PFC_PIN_GROUP(msiof1_txd_c), ++ SH_PFC_PIN_GROUP(msiof1_rxd_c), ++ SH_PFC_PIN_GROUP(msiof1_clk_d), ++ SH_PFC_PIN_GROUP(msiof1_sync_d), ++ SH_PFC_PIN_GROUP(msiof1_ss1_d), ++ SH_PFC_PIN_GROUP(msiof1_ss2_d), ++ SH_PFC_PIN_GROUP(msiof1_txd_d), ++ SH_PFC_PIN_GROUP(msiof1_rxd_d), ++ SH_PFC_PIN_GROUP(msiof1_clk_e), ++ SH_PFC_PIN_GROUP(msiof1_sync_e), ++ SH_PFC_PIN_GROUP(msiof1_ss1_e), ++ SH_PFC_PIN_GROUP(msiof1_ss2_e), ++ SH_PFC_PIN_GROUP(msiof1_txd_e), ++ SH_PFC_PIN_GROUP(msiof1_rxd_e), ++ SH_PFC_PIN_GROUP(msiof1_clk_f), ++ SH_PFC_PIN_GROUP(msiof1_sync_f), ++ SH_PFC_PIN_GROUP(msiof1_ss1_f), ++ SH_PFC_PIN_GROUP(msiof1_ss2_f), ++ SH_PFC_PIN_GROUP(msiof1_txd_f), ++ SH_PFC_PIN_GROUP(msiof1_rxd_f), ++ SH_PFC_PIN_GROUP(msiof1_clk_g), ++ SH_PFC_PIN_GROUP(msiof1_sync_g), ++ SH_PFC_PIN_GROUP(msiof1_ss1_g), ++ SH_PFC_PIN_GROUP(msiof1_ss2_g), ++ SH_PFC_PIN_GROUP(msiof1_txd_g), ++ SH_PFC_PIN_GROUP(msiof1_rxd_g), ++ SH_PFC_PIN_GROUP(msiof2_clk_a), ++ SH_PFC_PIN_GROUP(msiof2_sync_a), ++ SH_PFC_PIN_GROUP(msiof2_ss1_a), ++ SH_PFC_PIN_GROUP(msiof2_ss2_a), ++ SH_PFC_PIN_GROUP(msiof2_txd_a), ++ SH_PFC_PIN_GROUP(msiof2_rxd_a), ++ SH_PFC_PIN_GROUP(msiof2_clk_b), ++ SH_PFC_PIN_GROUP(msiof2_sync_b), ++ SH_PFC_PIN_GROUP(msiof2_ss1_b), ++ SH_PFC_PIN_GROUP(msiof2_ss2_b), ++ SH_PFC_PIN_GROUP(msiof2_txd_b), ++ SH_PFC_PIN_GROUP(msiof2_rxd_b), ++ SH_PFC_PIN_GROUP(msiof2_clk_c), ++ SH_PFC_PIN_GROUP(msiof2_sync_c), ++ SH_PFC_PIN_GROUP(msiof2_ss1_c), ++ SH_PFC_PIN_GROUP(msiof2_ss2_c), ++ SH_PFC_PIN_GROUP(msiof2_txd_c), ++ SH_PFC_PIN_GROUP(msiof2_rxd_c), ++ SH_PFC_PIN_GROUP(msiof2_clk_d), ++ SH_PFC_PIN_GROUP(msiof2_sync_d), ++ SH_PFC_PIN_GROUP(msiof2_ss1_d), ++ SH_PFC_PIN_GROUP(msiof2_ss2_d), ++ SH_PFC_PIN_GROUP(msiof2_txd_d), ++ SH_PFC_PIN_GROUP(msiof2_rxd_d), ++ SH_PFC_PIN_GROUP(msiof3_clk_a), ++ SH_PFC_PIN_GROUP(msiof3_sync_a), ++ SH_PFC_PIN_GROUP(msiof3_ss1_a), ++ SH_PFC_PIN_GROUP(msiof3_ss2_a), ++ SH_PFC_PIN_GROUP(msiof3_txd_a), ++ SH_PFC_PIN_GROUP(msiof3_rxd_a), ++ SH_PFC_PIN_GROUP(msiof3_clk_b), ++ SH_PFC_PIN_GROUP(msiof3_sync_b), ++ SH_PFC_PIN_GROUP(msiof3_ss1_b), ++ SH_PFC_PIN_GROUP(msiof3_ss2_b), ++ SH_PFC_PIN_GROUP(msiof3_txd_b), ++ SH_PFC_PIN_GROUP(msiof3_rxd_b), ++ SH_PFC_PIN_GROUP(msiof3_clk_c), ++ SH_PFC_PIN_GROUP(msiof3_sync_c), ++ SH_PFC_PIN_GROUP(msiof3_txd_c), ++ SH_PFC_PIN_GROUP(msiof3_rxd_c), ++ SH_PFC_PIN_GROUP(msiof3_clk_d), ++ SH_PFC_PIN_GROUP(msiof3_sync_d), ++ SH_PFC_PIN_GROUP(msiof3_ss1_d), ++ SH_PFC_PIN_GROUP(msiof3_txd_d), ++ SH_PFC_PIN_GROUP(msiof3_rxd_d), ++ SH_PFC_PIN_GROUP(pwm0), ++ SH_PFC_PIN_GROUP(pwm1_a), ++ SH_PFC_PIN_GROUP(pwm1_b), ++ SH_PFC_PIN_GROUP(pwm2_a), ++ SH_PFC_PIN_GROUP(pwm2_b), ++ SH_PFC_PIN_GROUP(pwm3_a), ++ SH_PFC_PIN_GROUP(pwm3_b), ++ SH_PFC_PIN_GROUP(pwm4_a), ++ SH_PFC_PIN_GROUP(pwm4_b), ++ SH_PFC_PIN_GROUP(pwm5_a), ++ SH_PFC_PIN_GROUP(pwm5_b), ++ SH_PFC_PIN_GROUP(pwm6_a), ++ SH_PFC_PIN_GROUP(pwm6_b), ++ SH_PFC_PIN_GROUP(qspi0_ctrl), ++ SH_PFC_PIN_GROUP(qspi0_data2), ++ SH_PFC_PIN_GROUP(qspi0_data4), ++ SH_PFC_PIN_GROUP(qspi1_ctrl), ++ SH_PFC_PIN_GROUP(qspi1_data2), ++ SH_PFC_PIN_GROUP(qspi1_data4), ++ SH_PFC_PIN_GROUP(sata0_devslp_a), ++ SH_PFC_PIN_GROUP(sata0_devslp_b), ++ SH_PFC_PIN_GROUP(scif0_data), ++ SH_PFC_PIN_GROUP(scif0_clk), ++ SH_PFC_PIN_GROUP(scif0_ctrl), ++ SH_PFC_PIN_GROUP(scif1_data_a), ++ SH_PFC_PIN_GROUP(scif1_clk), ++ SH_PFC_PIN_GROUP(scif1_ctrl), ++ SH_PFC_PIN_GROUP(scif1_data_b), ++ SH_PFC_PIN_GROUP(scif2_data_a), ++ SH_PFC_PIN_GROUP(scif2_clk), ++ SH_PFC_PIN_GROUP(scif2_data_b), ++ SH_PFC_PIN_GROUP(scif3_data_a), ++ SH_PFC_PIN_GROUP(scif3_clk), ++ SH_PFC_PIN_GROUP(scif3_ctrl), ++ SH_PFC_PIN_GROUP(scif3_data_b), ++ SH_PFC_PIN_GROUP(scif4_data_a), ++ SH_PFC_PIN_GROUP(scif4_clk_a), ++ SH_PFC_PIN_GROUP(scif4_ctrl_a), ++ SH_PFC_PIN_GROUP(scif4_data_b), ++ SH_PFC_PIN_GROUP(scif4_clk_b), ++ SH_PFC_PIN_GROUP(scif4_ctrl_b), ++ SH_PFC_PIN_GROUP(scif4_data_c), ++ SH_PFC_PIN_GROUP(scif4_clk_c), ++ SH_PFC_PIN_GROUP(scif4_ctrl_c), ++ SH_PFC_PIN_GROUP(scif5_data), ++ SH_PFC_PIN_GROUP(scif5_clk), ++ SH_PFC_PIN_GROUP(scif_clk_a), ++ SH_PFC_PIN_GROUP(scif_clk_b), ++ SH_PFC_PIN_GROUP(sdhi0_data1), ++ SH_PFC_PIN_GROUP(sdhi0_data4), ++ SH_PFC_PIN_GROUP(sdhi0_ctrl), ++ SH_PFC_PIN_GROUP(sdhi0_cd), ++ SH_PFC_PIN_GROUP(sdhi0_wp), ++ SH_PFC_PIN_GROUP(sdhi1_data1), ++ SH_PFC_PIN_GROUP(sdhi1_data4), ++ SH_PFC_PIN_GROUP(sdhi1_ctrl), ++ SH_PFC_PIN_GROUP(sdhi1_cd), ++ SH_PFC_PIN_GROUP(sdhi1_wp), ++ SH_PFC_PIN_GROUP(sdhi2_data1), ++ SH_PFC_PIN_GROUP(sdhi2_data4), ++ SH_PFC_PIN_GROUP(sdhi2_data8), ++ SH_PFC_PIN_GROUP(sdhi2_ctrl), ++ SH_PFC_PIN_GROUP(sdhi2_cd_a), ++ SH_PFC_PIN_GROUP(sdhi2_wp_a), ++ SH_PFC_PIN_GROUP(sdhi2_cd_b), ++ SH_PFC_PIN_GROUP(sdhi2_wp_b), ++ SH_PFC_PIN_GROUP(sdhi2_ds), ++ SH_PFC_PIN_GROUP(sdhi3_data1), ++ SH_PFC_PIN_GROUP(sdhi3_data4), ++ SH_PFC_PIN_GROUP(sdhi3_data8), ++ SH_PFC_PIN_GROUP(sdhi3_ctrl), ++ SH_PFC_PIN_GROUP(sdhi3_cd), ++ SH_PFC_PIN_GROUP(sdhi3_wp), ++ SH_PFC_PIN_GROUP(sdhi3_ds), ++ SH_PFC_PIN_GROUP(ssi0_data), ++ SH_PFC_PIN_GROUP(ssi01239_ctrl), ++ SH_PFC_PIN_GROUP(ssi1_data_a), ++ SH_PFC_PIN_GROUP(ssi1_data_b), ++ SH_PFC_PIN_GROUP(ssi1_ctrl_a), ++ SH_PFC_PIN_GROUP(ssi1_ctrl_b), ++ SH_PFC_PIN_GROUP(ssi2_data_a), ++ SH_PFC_PIN_GROUP(ssi2_data_b), ++ SH_PFC_PIN_GROUP(ssi2_ctrl_a), ++ SH_PFC_PIN_GROUP(ssi2_ctrl_b), ++ SH_PFC_PIN_GROUP(ssi3_data), ++ SH_PFC_PIN_GROUP(ssi34_ctrl), ++ SH_PFC_PIN_GROUP(ssi4_data), ++ SH_PFC_PIN_GROUP(ssi4_ctrl), ++ SH_PFC_PIN_GROUP(ssi5_data), ++ SH_PFC_PIN_GROUP(ssi5_ctrl), ++ SH_PFC_PIN_GROUP(ssi6_data), ++ SH_PFC_PIN_GROUP(ssi6_ctrl), ++ SH_PFC_PIN_GROUP(ssi7_data), ++ SH_PFC_PIN_GROUP(ssi78_ctrl), ++ SH_PFC_PIN_GROUP(ssi8_data), ++ SH_PFC_PIN_GROUP(ssi9_data_a), ++ SH_PFC_PIN_GROUP(ssi9_data_b), ++ SH_PFC_PIN_GROUP(ssi9_ctrl_a), ++ SH_PFC_PIN_GROUP(ssi9_ctrl_b), ++ SH_PFC_PIN_GROUP(usb0), ++ SH_PFC_PIN_GROUP(usb1), ++ SH_PFC_PIN_GROUP(usb2), ++}; ++ ++static const char * const audio_clk_groups[] = { ++ "audio_clk_a_a", ++ "audio_clk_a_b", ++ "audio_clk_a_c", ++ "audio_clk_b_a", ++ "audio_clk_b_b", ++ "audio_clk_c_a", ++ "audio_clk_c_b", ++ "audio_clkout_a", ++ "audio_clkout_b", ++ "audio_clkout_c", ++ "audio_clkout_d", ++ "audio_clkout1_a", ++ "audio_clkout1_b", ++ "audio_clkout2_a", ++ "audio_clkout2_b", ++ "audio_clkout3_a", ++ "audio_clkout3_b", ++}; ++ ++static const char * const avb_groups[] = { ++ "avb_link", ++ "avb_magic", ++ "avb_phy_int", ++ "avb_mdc", ++ "avb_mii", ++ "avb_avtp_pps", ++ "avb_avtp_match_a", ++ "avb_avtp_capture_a", ++ "avb_avtp_match_b", ++ "avb_avtp_capture_b", ++}; ++ ++static const char * const can0_groups[] = { ++ "can0_data_a", ++ "can0_data_b", ++}; ++ ++static const char * const can1_groups[] = { ++ "can1_data", ++}; ++ ++static const char * const can_clk_groups[] = { ++ "can_clk", ++}; ++ ++static const char * const canfd0_groups[] = { ++ "canfd0_data_a", ++ "canfd0_data_b", ++}; ++ ++static const char * const canfd1_groups[] = { ++ "canfd1_data", ++}; ++ ++static const char * const drif0_groups[] = { ++ "drif0_ctrl_a", ++ "drif0_data0_a", ++ "drif0_data1_a", ++ "drif0_ctrl_b", ++ "drif0_data0_b", ++ "drif0_data1_b", ++ "drif0_ctrl_c", ++ "drif0_data0_c", ++ "drif0_data1_c", ++}; ++ ++static const char * const drif1_groups[] = { ++ "drif1_ctrl_a", ++ "drif1_data0_a", ++ "drif1_data1_a", ++ "drif1_ctrl_b", ++ "drif1_data0_b", ++ "drif1_data1_b", ++ "drif1_ctrl_c", ++ "drif1_data0_c", ++ "drif1_data1_c", ++}; ++ ++static const char * const drif2_groups[] = { ++ "drif2_ctrl_a", ++ "drif2_data0_a", ++ "drif2_data1_a", ++ "drif2_ctrl_b", ++ "drif2_data0_b", ++ "drif2_data1_b", ++}; ++ ++static const char * const drif3_groups[] = { ++ "drif3_ctrl_a", ++ "drif3_data0_a", ++ "drif3_data1_a", ++ "drif3_ctrl_b", ++ "drif3_data0_b", ++ "drif3_data1_b", ++}; ++ ++static const char * const du_groups[] = { ++ "du_rgb666", ++ "du_rgb888", ++ "du_clk_out_0", ++ "du_clk_out_1", ++ "du_sync", ++ "du_oddf", ++ "du_cde", ++ "du_disp", ++}; ++ ++static const char * const hscif0_groups[] = { ++ "hscif0_data", ++ "hscif0_clk", ++ "hscif0_ctrl", ++}; ++ ++static const char * const hscif1_groups[] = { ++ "hscif1_data_a", ++ "hscif1_clk_a", ++ "hscif1_ctrl_a", ++ "hscif1_data_b", ++ "hscif1_clk_b", ++ "hscif1_ctrl_b", ++}; ++ ++static const char * const hscif2_groups[] = { ++ "hscif2_data_a", ++ "hscif2_clk_a", ++ "hscif2_ctrl_a", ++ "hscif2_data_b", ++ "hscif2_clk_b", ++ "hscif2_ctrl_b", ++}; ++ ++static const char * const hscif3_groups[] = { ++ "hscif3_data_a", ++ "hscif3_clk", ++ "hscif3_ctrl", ++ "hscif3_data_b", ++ "hscif3_data_c", ++ "hscif3_data_d", ++}; ++ ++static const char * const hscif4_groups[] = { ++ "hscif4_data_a", ++ "hscif4_clk", ++ "hscif4_ctrl", ++ "hscif4_data_b", ++}; ++ ++static const char * const i2c1_groups[] = { ++ "i2c1_a", ++ "i2c1_b", ++}; ++ ++static const char * const i2c2_groups[] = { ++ "i2c2_a", ++ "i2c2_b", ++}; ++ ++static const char * const i2c6_groups[] = { ++ "i2c6_a", ++ "i2c6_b", ++ "i2c6_c", ++}; ++ ++static const char * const intc_ex_groups[] = { ++ "intc_ex_irq0", ++ "intc_ex_irq1", ++ "intc_ex_irq2", ++ "intc_ex_irq3", ++ "intc_ex_irq4", ++ "intc_ex_irq5", ++}; ++ ++static const char * const msiof0_groups[] = { ++ "msiof0_clk", ++ "msiof0_sync", ++ "msiof0_ss1", ++ "msiof0_ss2", ++ "msiof0_txd", ++ "msiof0_rxd", ++}; ++ ++static const char * const msiof1_groups[] = { ++ "msiof1_clk_a", ++ "msiof1_sync_a", ++ "msiof1_ss1_a", ++ "msiof1_ss2_a", ++ "msiof1_txd_a", ++ "msiof1_rxd_a", ++ "msiof1_clk_b", ++ "msiof1_sync_b", ++ "msiof1_ss1_b", ++ "msiof1_ss2_b", ++ "msiof1_txd_b", ++ "msiof1_rxd_b", ++ "msiof1_clk_c", ++ "msiof1_sync_c", ++ "msiof1_ss1_c", ++ "msiof1_ss2_c", ++ "msiof1_txd_c", ++ "msiof1_rxd_c", ++ "msiof1_clk_d", ++ "msiof1_sync_d", ++ "msiof1_ss1_d", ++ "msiof1_ss2_d", ++ "msiof1_txd_d", ++ "msiof1_rxd_d", ++ "msiof1_clk_e", ++ "msiof1_sync_e", ++ "msiof1_ss1_e", ++ "msiof1_ss2_e", ++ "msiof1_txd_e", ++ "msiof1_rxd_e", ++ "msiof1_clk_f", ++ "msiof1_sync_f", ++ "msiof1_ss1_f", ++ "msiof1_ss2_f", ++ "msiof1_txd_f", ++ "msiof1_rxd_f", ++ "msiof1_clk_g", ++ "msiof1_sync_g", ++ "msiof1_ss1_g", ++ "msiof1_ss2_g", ++ "msiof1_txd_g", ++ "msiof1_rxd_g", ++}; ++ ++static const char * const msiof2_groups[] = { ++ "msiof2_clk_a", ++ "msiof2_sync_a", ++ "msiof2_ss1_a", ++ "msiof2_ss2_a", ++ "msiof2_txd_a", ++ "msiof2_rxd_a", ++ "msiof2_clk_b", ++ "msiof2_sync_b", ++ "msiof2_ss1_b", ++ "msiof2_ss2_b", ++ "msiof2_txd_b", ++ "msiof2_rxd_b", ++ "msiof2_clk_c", ++ "msiof2_sync_c", ++ "msiof2_ss1_c", ++ "msiof2_ss2_c", ++ "msiof2_txd_c", ++ "msiof2_rxd_c", ++ "msiof2_clk_d", ++ "msiof2_sync_d", ++ "msiof2_ss1_d", ++ "msiof2_ss2_d", ++ "msiof2_txd_d", ++ "msiof2_rxd_d", ++}; ++ ++static const char * const msiof3_groups[] = { ++ "msiof3_clk_a", ++ "msiof3_sync_a", ++ "msiof3_ss1_a", ++ "msiof3_ss2_a", ++ "msiof3_txd_a", ++ "msiof3_rxd_a", ++ "msiof3_clk_b", ++ "msiof3_sync_b", ++ "msiof3_ss1_b", ++ "msiof3_ss2_b", ++ "msiof3_txd_b", ++ "msiof3_rxd_b", ++ "msiof3_clk_c", ++ "msiof3_sync_c", ++ "msiof3_txd_c", ++ "msiof3_rxd_c", ++ "msiof3_clk_d", ++ "msiof3_sync_d", ++ "msiof3_ss1_d", ++ "msiof3_txd_d", ++ "msiof3_rxd_d", ++}; ++ ++static const char * const pwm0_groups[] = { ++ "pwm0", ++}; ++ ++static const char * const pwm1_groups[] = { ++ "pwm1_a", ++ "pwm1_b", ++}; ++ ++static const char * const pwm2_groups[] = { ++ "pwm2_a", ++ "pwm2_b", ++}; ++ ++static const char * const pwm3_groups[] = { ++ "pwm3_a", ++ "pwm3_b", ++}; ++ ++static const char * const pwm4_groups[] = { ++ "pwm4_a", ++ "pwm4_b", ++}; ++ ++static const char * const pwm5_groups[] = { ++ "pwm5_a", ++ "pwm5_b", ++}; ++ ++static const char * const pwm6_groups[] = { ++ "pwm6_a", ++ "pwm6_b", ++}; ++ ++static const char * const qspi0_groups[] = { ++ "qspi0_ctrl", ++ "qspi0_data2", ++ "qspi0_data4", ++}; ++ ++static const char * const qspi1_groups[] = { ++ "qspi1_ctrl", ++ "qspi1_data2", ++ "qspi1_data4", ++}; ++ ++static const char * const sata0_groups[] = { ++ "sata0_devslp_a", ++ "sata0_devslp_b", ++}; ++ ++static const char * const scif0_groups[] = { ++ "scif0_data", ++ "scif0_clk", ++ "scif0_ctrl", ++}; ++ ++static const char * const scif1_groups[] = { ++ "scif1_data_a", ++ "scif1_clk", ++ "scif1_ctrl", ++ "scif1_data_b", ++}; ++ ++static const char * const scif2_groups[] = { ++ "scif2_data_a", ++ "scif2_clk", ++ "scif2_data_b", ++}; ++ ++static const char * const scif3_groups[] = { ++ "scif3_data_a", ++ "scif3_clk", ++ "scif3_ctrl", ++ "scif3_data_b", ++}; ++ ++static const char * const scif4_groups[] = { ++ "scif4_data_a", ++ "scif4_clk_a", ++ "scif4_ctrl_a", ++ "scif4_data_b", ++ "scif4_clk_b", ++ "scif4_ctrl_b", ++ "scif4_data_c", ++ "scif4_clk_c", ++ "scif4_ctrl_c", ++}; ++ ++static const char * const scif5_groups[] = { ++ "scif5_data", ++ "scif5_clk", ++}; ++ ++static const char * const scif_clk_groups[] = { ++ "scif_clk_a", ++ "scif_clk_b", ++}; ++ ++static const char * const sdhi0_groups[] = { ++ "sdhi0_data1", ++ "sdhi0_data4", ++ "sdhi0_ctrl", ++ "sdhi0_cd", ++ "sdhi0_wp", ++}; ++ ++static const char * const sdhi1_groups[] = { ++ "sdhi1_data1", ++ "sdhi1_data4", ++ "sdhi1_ctrl", ++ "sdhi1_cd", ++ "sdhi1_wp", ++}; ++ ++static const char * const sdhi2_groups[] = { ++ "sdhi2_data1", ++ "sdhi2_data4", ++ "sdhi2_data8", ++ "sdhi2_ctrl", ++ "sdhi2_cd_a", ++ "sdhi2_wp_a", ++ "sdhi2_cd_b", ++ "sdhi2_wp_b", ++ "sdhi2_ds", ++}; ++ ++static const char * const sdhi3_groups[] = { ++ "sdhi3_data1", ++ "sdhi3_data4", ++ "sdhi3_data8", ++ "sdhi3_ctrl", ++ "sdhi3_cd", ++ "sdhi3_wp", ++ "sdhi3_ds", ++}; ++ ++static const char * const ssi_groups[] = { ++ "ssi0_data", ++ "ssi01239_ctrl", ++ "ssi1_data_a", ++ "ssi1_data_b", ++ "ssi1_ctrl_a", ++ "ssi1_ctrl_b", ++ "ssi2_data_a", ++ "ssi2_data_b", ++ "ssi2_ctrl_a", ++ "ssi2_ctrl_b", ++ "ssi3_data", ++ "ssi34_ctrl", ++ "ssi4_data", ++ "ssi4_ctrl", ++ "ssi5_data", ++ "ssi5_ctrl", ++ "ssi6_data", ++ "ssi6_ctrl", ++ "ssi7_data", ++ "ssi78_ctrl", ++ "ssi8_data", ++ "ssi9_data_a", ++ "ssi9_data_b", ++ "ssi9_ctrl_a", ++ "ssi9_ctrl_b", ++}; ++ ++static const char * const usb0_groups[] = { ++ "usb0", ++}; ++ ++static const char * const usb1_groups[] = { ++ "usb1", ++}; ++ ++static const char * const usb2_groups[] = { ++ "usb2", ++}; ++ ++static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(audio_clk), ++ SH_PFC_FUNCTION(avb), ++ SH_PFC_FUNCTION(can0), ++ SH_PFC_FUNCTION(can1), ++ SH_PFC_FUNCTION(can_clk), ++ SH_PFC_FUNCTION(canfd0), ++ SH_PFC_FUNCTION(canfd1), ++ SH_PFC_FUNCTION(drif0), ++ SH_PFC_FUNCTION(drif1), ++ SH_PFC_FUNCTION(drif2), ++ SH_PFC_FUNCTION(drif3), ++ SH_PFC_FUNCTION(du), ++ SH_PFC_FUNCTION(hscif0), ++ SH_PFC_FUNCTION(hscif1), ++ SH_PFC_FUNCTION(hscif2), ++ SH_PFC_FUNCTION(hscif3), ++ SH_PFC_FUNCTION(hscif4), ++ SH_PFC_FUNCTION(i2c1), ++ SH_PFC_FUNCTION(i2c2), ++ SH_PFC_FUNCTION(i2c6), ++ SH_PFC_FUNCTION(intc_ex), ++ SH_PFC_FUNCTION(msiof0), ++ SH_PFC_FUNCTION(msiof1), ++ SH_PFC_FUNCTION(msiof2), ++ SH_PFC_FUNCTION(msiof3), ++ SH_PFC_FUNCTION(pwm0), ++ SH_PFC_FUNCTION(pwm1), ++ SH_PFC_FUNCTION(pwm2), ++ SH_PFC_FUNCTION(pwm3), ++ SH_PFC_FUNCTION(pwm4), ++ SH_PFC_FUNCTION(pwm5), ++ SH_PFC_FUNCTION(pwm6), ++ SH_PFC_FUNCTION(qspi0), ++ SH_PFC_FUNCTION(qspi1), ++ SH_PFC_FUNCTION(sata0), ++ SH_PFC_FUNCTION(scif0), ++ SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scif2), ++ SH_PFC_FUNCTION(scif3), ++ SH_PFC_FUNCTION(scif4), ++ SH_PFC_FUNCTION(scif5), ++ SH_PFC_FUNCTION(scif_clk), ++ SH_PFC_FUNCTION(sdhi0), ++ SH_PFC_FUNCTION(sdhi1), ++ SH_PFC_FUNCTION(sdhi2), ++ SH_PFC_FUNCTION(sdhi3), ++ SH_PFC_FUNCTION(ssi), ++ SH_PFC_FUNCTION(usb0), ++ SH_PFC_FUNCTION(usb1), ++ SH_PFC_FUNCTION(usb2), ++}; ++ ++static const struct pinmux_cfg_reg pinmux_config_regs[] = { ++#define F_(x, y) FN_##y ++#define FM(x) FN_##x ++ { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_0_15_FN, GPSR0_15, ++ GP_0_14_FN, GPSR0_14, ++ GP_0_13_FN, GPSR0_13, ++ GP_0_12_FN, GPSR0_12, ++ GP_0_11_FN, GPSR0_11, ++ GP_0_10_FN, GPSR0_10, ++ GP_0_9_FN, GPSR0_9, ++ GP_0_8_FN, GPSR0_8, ++ GP_0_7_FN, GPSR0_7, ++ GP_0_6_FN, GPSR0_6, ++ GP_0_5_FN, GPSR0_5, ++ GP_0_4_FN, GPSR0_4, ++ GP_0_3_FN, GPSR0_3, ++ GP_0_2_FN, GPSR0_2, ++ GP_0_1_FN, GPSR0_1, ++ GP_0_0_FN, GPSR0_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_1_27_FN, GPSR1_27, ++ GP_1_26_FN, GPSR1_26, ++ GP_1_25_FN, GPSR1_25, ++ GP_1_24_FN, GPSR1_24, ++ GP_1_23_FN, GPSR1_23, ++ GP_1_22_FN, GPSR1_22, ++ GP_1_21_FN, GPSR1_21, ++ GP_1_20_FN, GPSR1_20, ++ GP_1_19_FN, GPSR1_19, ++ GP_1_18_FN, GPSR1_18, ++ GP_1_17_FN, GPSR1_17, ++ GP_1_16_FN, GPSR1_16, ++ GP_1_15_FN, GPSR1_15, ++ GP_1_14_FN, GPSR1_14, ++ GP_1_13_FN, GPSR1_13, ++ GP_1_12_FN, GPSR1_12, ++ GP_1_11_FN, GPSR1_11, ++ GP_1_10_FN, GPSR1_10, ++ GP_1_9_FN, GPSR1_9, ++ GP_1_8_FN, GPSR1_8, ++ GP_1_7_FN, GPSR1_7, ++ GP_1_6_FN, GPSR1_6, ++ GP_1_5_FN, GPSR1_5, ++ GP_1_4_FN, GPSR1_4, ++ GP_1_3_FN, GPSR1_3, ++ GP_1_2_FN, GPSR1_2, ++ GP_1_1_FN, GPSR1_1, ++ GP_1_0_FN, GPSR1_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_2_14_FN, GPSR2_14, ++ GP_2_13_FN, GPSR2_13, ++ GP_2_12_FN, GPSR2_12, ++ GP_2_11_FN, GPSR2_11, ++ GP_2_10_FN, GPSR2_10, ++ GP_2_9_FN, GPSR2_9, ++ GP_2_8_FN, GPSR2_8, ++ GP_2_7_FN, GPSR2_7, ++ GP_2_6_FN, GPSR2_6, ++ GP_2_5_FN, GPSR2_5, ++ GP_2_4_FN, GPSR2_4, ++ GP_2_3_FN, GPSR2_3, ++ GP_2_2_FN, GPSR2_2, ++ GP_2_1_FN, GPSR2_1, ++ GP_2_0_FN, GPSR2_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_3_15_FN, GPSR3_15, ++ GP_3_14_FN, GPSR3_14, ++ GP_3_13_FN, GPSR3_13, ++ GP_3_12_FN, GPSR3_12, ++ GP_3_11_FN, GPSR3_11, ++ GP_3_10_FN, GPSR3_10, ++ GP_3_9_FN, GPSR3_9, ++ GP_3_8_FN, GPSR3_8, ++ GP_3_7_FN, GPSR3_7, ++ GP_3_6_FN, GPSR3_6, ++ GP_3_5_FN, GPSR3_5, ++ GP_3_4_FN, GPSR3_4, ++ GP_3_3_FN, GPSR3_3, ++ GP_3_2_FN, GPSR3_2, ++ GP_3_1_FN, GPSR3_1, ++ GP_3_0_FN, GPSR3_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_4_17_FN, GPSR4_17, ++ GP_4_16_FN, GPSR4_16, ++ GP_4_15_FN, GPSR4_15, ++ GP_4_14_FN, GPSR4_14, ++ GP_4_13_FN, GPSR4_13, ++ GP_4_12_FN, GPSR4_12, ++ GP_4_11_FN, GPSR4_11, ++ GP_4_10_FN, GPSR4_10, ++ GP_4_9_FN, GPSR4_9, ++ GP_4_8_FN, GPSR4_8, ++ GP_4_7_FN, GPSR4_7, ++ GP_4_6_FN, GPSR4_6, ++ GP_4_5_FN, GPSR4_5, ++ GP_4_4_FN, GPSR4_4, ++ GP_4_3_FN, GPSR4_3, ++ GP_4_2_FN, GPSR4_2, ++ GP_4_1_FN, GPSR4_1, ++ GP_4_0_FN, GPSR4_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_5_25_FN, GPSR5_25, ++ GP_5_24_FN, GPSR5_24, ++ GP_5_23_FN, GPSR5_23, ++ GP_5_22_FN, GPSR5_22, ++ GP_5_21_FN, GPSR5_21, ++ GP_5_20_FN, GPSR5_20, ++ GP_5_19_FN, GPSR5_19, ++ GP_5_18_FN, GPSR5_18, ++ GP_5_17_FN, GPSR5_17, ++ GP_5_16_FN, GPSR5_16, ++ GP_5_15_FN, GPSR5_15, ++ GP_5_14_FN, GPSR5_14, ++ GP_5_13_FN, GPSR5_13, ++ GP_5_12_FN, GPSR5_12, ++ GP_5_11_FN, GPSR5_11, ++ GP_5_10_FN, GPSR5_10, ++ GP_5_9_FN, GPSR5_9, ++ GP_5_8_FN, GPSR5_8, ++ GP_5_7_FN, GPSR5_7, ++ GP_5_6_FN, GPSR5_6, ++ GP_5_5_FN, GPSR5_5, ++ GP_5_4_FN, GPSR5_4, ++ GP_5_3_FN, GPSR5_3, ++ GP_5_2_FN, GPSR5_2, ++ GP_5_1_FN, GPSR5_1, ++ GP_5_0_FN, GPSR5_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { ++ GP_6_31_FN, GPSR6_31, ++ GP_6_30_FN, GPSR6_30, ++ GP_6_29_FN, GPSR6_29, ++ GP_6_28_FN, GPSR6_28, ++ GP_6_27_FN, GPSR6_27, ++ GP_6_26_FN, GPSR6_26, ++ GP_6_25_FN, GPSR6_25, ++ GP_6_24_FN, GPSR6_24, ++ GP_6_23_FN, GPSR6_23, ++ GP_6_22_FN, GPSR6_22, ++ GP_6_21_FN, GPSR6_21, ++ GP_6_20_FN, GPSR6_20, ++ GP_6_19_FN, GPSR6_19, ++ GP_6_18_FN, GPSR6_18, ++ GP_6_17_FN, GPSR6_17, ++ GP_6_16_FN, GPSR6_16, ++ GP_6_15_FN, GPSR6_15, ++ GP_6_14_FN, GPSR6_14, ++ GP_6_13_FN, GPSR6_13, ++ GP_6_12_FN, GPSR6_12, ++ GP_6_11_FN, GPSR6_11, ++ GP_6_10_FN, GPSR6_10, ++ GP_6_9_FN, GPSR6_9, ++ GP_6_8_FN, GPSR6_8, ++ GP_6_7_FN, GPSR6_7, ++ GP_6_6_FN, GPSR6_6, ++ GP_6_5_FN, GPSR6_5, ++ GP_6_4_FN, GPSR6_4, ++ GP_6_3_FN, GPSR6_3, ++ GP_6_2_FN, GPSR6_2, ++ GP_6_1_FN, GPSR6_1, ++ GP_6_0_FN, GPSR6_0, } ++ }, ++ { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ 0, 0, ++ GP_7_3_FN, GPSR7_3, ++ GP_7_2_FN, GPSR7_2, ++ GP_7_1_FN, GPSR7_1, ++ GP_7_0_FN, GPSR7_0, } ++ }, ++#undef F_ ++#undef FM ++ ++#define F_(x, y) x, ++#define FM(x) FN_##x, ++ { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { ++ IP0_31_28 ++ IP0_27_24 ++ IP0_23_20 ++ IP0_19_16 ++ IP0_15_12 ++ IP0_11_8 ++ IP0_7_4 ++ IP0_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { ++ IP1_31_28 ++ IP1_27_24 ++ IP1_23_20 ++ IP1_19_16 ++ IP1_15_12 ++ IP1_11_8 ++ IP1_7_4 ++ IP1_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { ++ IP2_31_28 ++ IP2_27_24 ++ IP2_23_20 ++ IP2_19_16 ++ IP2_15_12 ++ IP2_11_8 ++ IP2_7_4 ++ IP2_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { ++ IP3_31_28 ++ IP3_27_24 ++ IP3_23_20 ++ IP3_19_16 ++ IP3_15_12 ++ IP3_11_8 ++ IP3_7_4 ++ IP3_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { ++ IP4_31_28 ++ IP4_27_24 ++ IP4_23_20 ++ IP4_19_16 ++ IP4_15_12 ++ IP4_11_8 ++ IP4_7_4 ++ IP4_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { ++ IP5_31_28 ++ IP5_27_24 ++ IP5_23_20 ++ IP5_19_16 ++ IP5_15_12 ++ IP5_11_8 ++ IP5_7_4 ++ IP5_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { ++ IP6_31_28 ++ IP6_27_24 ++ IP6_23_20 ++ IP6_19_16 ++ IP6_15_12 ++ IP6_11_8 ++ IP6_7_4 ++ IP6_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { ++ IP7_31_28 ++ IP7_27_24 ++ IP7_23_20 ++ IP7_19_16 ++ IP7_15_12 ++ IP7_11_8 ++ IP7_7_4 ++ IP7_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { ++ IP8_31_28 ++ IP8_27_24 ++ IP8_23_20 ++ IP8_19_16 ++ IP8_15_12 ++ IP8_11_8 ++ IP8_7_4 ++ IP8_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { ++ IP9_31_28 ++ IP9_27_24 ++ IP9_23_20 ++ IP9_19_16 ++ IP9_15_12 ++ IP9_11_8 ++ IP9_7_4 ++ IP9_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { ++ IP10_31_28 ++ IP10_27_24 ++ IP10_23_20 ++ IP10_19_16 ++ IP10_15_12 ++ IP10_11_8 ++ IP10_7_4 ++ IP10_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { ++ IP11_31_28 ++ IP11_27_24 ++ IP11_23_20 ++ IP11_19_16 ++ IP11_15_12 ++ IP11_11_8 ++ IP11_7_4 ++ IP11_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { ++ IP12_31_28 ++ IP12_27_24 ++ IP12_23_20 ++ IP12_19_16 ++ IP12_15_12 ++ IP12_11_8 ++ IP12_7_4 ++ IP12_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { ++ IP13_31_28 ++ IP13_27_24 ++ IP13_23_20 ++ IP13_19_16 ++ IP13_15_12 ++ IP13_11_8 ++ IP13_7_4 ++ IP13_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { ++ IP14_31_28 ++ IP14_27_24 ++ IP14_23_20 ++ IP14_19_16 ++ IP14_15_12 ++ IP14_11_8 ++ IP14_7_4 ++ IP14_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { ++ IP15_31_28 ++ IP15_27_24 ++ IP15_23_20 ++ IP15_19_16 ++ IP15_15_12 ++ IP15_11_8 ++ IP15_7_4 ++ IP15_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { ++ IP16_31_28 ++ IP16_27_24 ++ IP16_23_20 ++ IP16_19_16 ++ IP16_15_12 ++ IP16_11_8 ++ IP16_7_4 ++ IP16_3_0 } ++ }, ++ { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { ++ /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ IP17_7_4 ++ IP17_3_0 } ++ }, ++#undef F_ ++#undef FM ++ ++#define F_(x, y) x, ++#define FM(x) FN_##x, ++ { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, ++ 1, 2, 2, 3, 1, 1, 2, 1, 1, 1, ++ 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) { ++ 0, 0, /* RESERVED 31 */ ++ MOD_SEL0_30_29 ++ MOD_SEL0_28_27 ++ MOD_SEL0_26_25_24 ++ MOD_SEL0_23 ++ MOD_SEL0_22 ++ MOD_SEL0_21_20 ++ MOD_SEL0_19 ++ MOD_SEL0_18 ++ MOD_SEL0_17 ++ MOD_SEL0_16_15 ++ MOD_SEL0_14 ++ MOD_SEL0_13 ++ MOD_SEL0_12 ++ MOD_SEL0_11 ++ MOD_SEL0_10 ++ MOD_SEL0_9 ++ MOD_SEL0_8 ++ MOD_SEL0_7_6 ++ MOD_SEL0_5_4 ++ MOD_SEL0_3 ++ MOD_SEL0_2_1 ++ 0, 0, /* RESERVED 0 */ } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, ++ 2, 3, 1, 2, 3, 1, 1, 2, 1, ++ 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { ++ MOD_SEL1_31_30 ++ MOD_SEL1_29_28_27 ++ MOD_SEL1_26 ++ MOD_SEL1_25_24 ++ MOD_SEL1_23_22_21 ++ MOD_SEL1_20 ++ MOD_SEL1_19 ++ MOD_SEL1_18_17 ++ MOD_SEL1_16 ++ MOD_SEL1_15_14 ++ MOD_SEL1_13 ++ MOD_SEL1_12 ++ MOD_SEL1_11 ++ MOD_SEL1_10 ++ MOD_SEL1_9 ++ 0, 0, 0, 0, /* RESERVED 8, 7 */ ++ MOD_SEL1_6 ++ MOD_SEL1_5 ++ MOD_SEL1_4 ++ MOD_SEL1_3 ++ MOD_SEL1_2 ++ MOD_SEL1_1 ++ MOD_SEL1_0 } ++ }, ++ { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, ++ 1, 1, 1, 1, 4, 4, 4, ++ 4, 4, 4, 1, 2, 1) { ++ MOD_SEL2_31 ++ MOD_SEL2_30 ++ MOD_SEL2_29 ++ /* RESERVED 28 */ ++ 0, 0, ++ /* RESERVED 27, 26, 25, 24 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 23, 22, 21, 20 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 19, 18, 17, 16 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 15, 14, 13, 12 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 11, 10, 9, 8 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 7, 6, 5, 4 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ /* RESERVED 3 */ ++ 0, 0, ++ /* RESERVED 2, 1 */ ++ 0, 0, 0, 0, ++ MOD_SEL2_0 } ++ }, ++ { }, ++}; ++ ++static const struct pinmux_drive_reg pinmux_drive_regs[] = { ++ { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) { ++ { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */ ++ { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */ ++ { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */ ++ { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */ ++ { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */ ++ { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */ ++ { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */ ++ { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) { ++ { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */ ++ { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */ ++ { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */ ++ { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */ ++ { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */ ++ { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */ ++ { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */ ++ { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) { ++ { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */ ++ { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */ ++ { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */ ++ { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */ ++ { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */ ++ { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */ ++ { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */ ++ { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) { ++ { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */ ++ { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */ ++ { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */ ++ { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */ ++ { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */ ++ { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ ++ { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) { ++ { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ ++ { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ ++ { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ ++ { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) { ++ { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ ++ { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ ++ { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ ++ { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ ++ { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ ++ { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) { ++ { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ ++ { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ ++ { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ ++ { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ ++ { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ ++ { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ ++ { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ ++ { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) { ++ { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ ++ { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ ++ { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ ++ { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ ++ { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ ++ { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ ++ { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ ++ { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { ++ { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */ ++ { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ ++ { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ ++ { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ ++ { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ ++ { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ ++ { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ ++ { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { ++ { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ ++ { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */ ++ { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ ++ { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ ++ { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ ++ { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ ++ { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ ++ { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { ++ { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ ++ { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ ++ { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ ++ { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ ++ { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ ++ { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ ++ { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ ++ { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) { ++ { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ ++ { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ ++ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ ++ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ ++ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ ++ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { ++ { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */ ++ { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */ ++ { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */ ++ { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) { ++ { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */ ++ { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */ ++ { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ ++ { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) { ++ { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) { ++ { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) { ++ { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ ++ { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) { ++ { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ ++ { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ ++ { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ ++ { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) { ++ { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */ ++ { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ ++ { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ ++ { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ ++ { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */ ++ { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ ++ { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) { ++ { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ ++ { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ ++ { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) { ++ { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ ++ { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ ++ { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */ ++ { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) { ++ { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ ++ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ ++ { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) { ++ { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) { ++ { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ ++ { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ ++ { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ ++ { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ ++ } }, ++ { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) { ++ { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ ++ { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */ ++ { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */ ++ } }, ++ { }, ++}; ++ ++static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, ++ u32 *pocctrl) ++{ ++ int bit = -EINVAL; ++ ++ *pocctrl = 0xe6060380; ++ ++ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) ++ bit = pin & 0x1f; ++ ++ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) ++ bit = (pin & 0x1f) + 12; ++ ++ return bit; ++} ++ ++#define PUEN 0xe6060400 ++#define PUD 0xe6060440 ++ ++#define PU0 0x00 ++#define PU1 0x04 ++#define PU2 0x08 ++#define PU3 0x0c ++#define PU4 0x10 ++#define PU5 0x14 ++#define PU6 0x18 ++ ++static const struct sh_pfc_bias_info bias_info[] = { ++ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ ++ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ ++ { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ ++ { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ ++ { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ ++ { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ ++ { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ ++ { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ ++ { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ ++ { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ ++ { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ ++ { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ ++ { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ ++ { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ ++ { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ ++ { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ ++ { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ ++ { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ ++ { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ ++ { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ ++ { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ ++ { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ ++ { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ ++ { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ ++ { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ ++ { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ ++ { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ ++ { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ ++ { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ ++ { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ ++ ++ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ ++ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ ++ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ ++ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ ++ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ ++ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ ++ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ ++ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ ++ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ ++ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ ++ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ ++ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ ++ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ ++ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ ++ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ ++ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ ++ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ ++ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ ++ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ ++ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ ++ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ ++ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ ++ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ ++ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ ++ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ ++ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ ++ ++ { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ ++ { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ ++ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ ++ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ ++ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ ++ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ ++ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ ++ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ ++ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ ++ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ ++ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ ++ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ ++ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ ++ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ ++ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ ++ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ ++ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ ++ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ ++ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ ++ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ ++ { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ ++ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ ++ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ ++ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ ++ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ ++ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ ++ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ ++ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ ++ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ ++ { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ ++ ++ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ ++ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ ++ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ ++ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ ++ { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ ++ /* bit 8 n/a */ ++ { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ ++ { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ ++ { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ ++ { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ ++ { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ ++ { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ ++ { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ ++ { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ ++ ++ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ ++ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ ++ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ ++ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ ++ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ ++ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ ++ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ ++ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ ++ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ ++ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ ++ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ ++ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ ++ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ ++ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ ++ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ ++ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ ++ ++ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ ++ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ ++ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ ++ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ ++ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ ++ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ ++ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ ++ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ ++ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ ++ { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ ++ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ ++ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ ++ ++ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ ++ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ ++ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ ++}; ++ ++static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, ++ unsigned int pin) ++{ ++ const struct sh_pfc_bias_info *info; ++ u32 reg; ++ u32 bit; ++ ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) ++ return PIN_CONFIG_BIAS_DISABLE; ++ ++ reg = info->reg; ++ bit = BIT(info->bit); ++ ++ if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) ++ return PIN_CONFIG_BIAS_DISABLE; ++ else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) ++ return PIN_CONFIG_BIAS_PULL_UP; ++ else ++ return PIN_CONFIG_BIAS_PULL_DOWN; ++} ++ ++static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, ++ unsigned int bias) ++{ ++ const struct sh_pfc_bias_info *info; ++ u32 enable, updown; ++ u32 reg; ++ u32 bit; ++ ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) ++ return; ++ ++ reg = info->reg; ++ bit = BIT(info->bit); ++ ++ enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; ++ if (bias != PIN_CONFIG_BIAS_DISABLE) ++ enable |= bit; ++ ++ updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; ++ if (bias == PIN_CONFIG_BIAS_PULL_UP) ++ updown |= bit; ++ ++ sh_pfc_write_reg(pfc, PUD + reg, 32, updown); ++ sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); ++} ++ ++static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { ++ .pin_to_pocctrl = r8a7795es1_pin_to_pocctrl, ++ .get_bias = r8a7795es1_pinmux_get_bias, ++ .set_bias = r8a7795es1_pinmux_set_bias, ++}; ++ ++const struct sh_pfc_soc_info r8a7795es1_pinmux_info = { ++ .name = "r8a77950_pfc", ++ .ops = &r8a7795es1_pinmux_ops, ++ .unlock_reg = 0xe6060000, /* PMMR */ ++ ++ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, ++ ++ .pins = pinmux_pins, ++ .nr_pins = ARRAY_SIZE(pinmux_pins), ++ .groups = pinmux_groups, ++ .nr_groups = ARRAY_SIZE(pinmux_groups), ++ .functions = pinmux_functions, ++ .nr_functions = ARRAY_SIZE(pinmux_functions), ++ ++ .cfg_regs = pinmux_config_regs, ++ .drive_regs = pinmux_drive_regs, ++ ++ .pinmux_data = pinmux_data, ++ .pinmux_data_size = ARRAY_SIZE(pinmux_data), ++}; +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 3d1c32cca16a..6caaed53938c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -1,7 +1,7 @@ + /* +- * R8A7795 processor support - PFC hardware block. ++ * R8A7795 ES2.0+ processor support - PFC hardware block. + * +- * Copyright (C) 2015 Renesas Electronics Corporation ++ * Copyright (C) 2015-2016 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -9,6 +9,7 @@ + */ + + #include <linux/kernel.h> ++#include <linux/sys_soc.h> + + #include "core.h" + #include "sh_pfc.h" +@@ -101,10 +102,10 @@ + #define GPSR2_0 F_(IRQ0, IP0_27_24) + + /* GPSR3 */ +-#define GPSR3_15 F_(SD1_WP, IP10_23_20) +-#define GPSR3_14 F_(SD1_CD, IP10_19_16) +-#define GPSR3_13 F_(SD0_WP, IP10_15_12) +-#define GPSR3_12 F_(SD0_CD, IP10_11_8) ++#define GPSR3_15 F_(SD1_WP, IP11_23_20) ++#define GPSR3_14 F_(SD1_CD, IP11_19_16) ++#define GPSR3_13 F_(SD0_WP, IP11_15_12) ++#define GPSR3_12 F_(SD0_CD, IP11_11_8) + #define GPSR3_11 F_(SD1_DAT3, IP8_31_28) + #define GPSR3_10 F_(SD1_DAT2, IP8_27_24) + #define GPSR3_9 F_(SD1_DAT1, IP8_23_20) +@@ -119,86 +120,86 @@ + #define GPSR3_0 F_(SD0_CLK, IP7_19_16) + + /* GPSR4 */ +-#define GPSR4_17 FM(SD3_DS) +-#define GPSR4_16 F_(SD3_DAT7, IP10_7_4) +-#define GPSR4_15 F_(SD3_DAT6, IP10_3_0) +-#define GPSR4_14 F_(SD3_DAT5, IP9_31_28) +-#define GPSR4_13 F_(SD3_DAT4, IP9_27_24) +-#define GPSR4_12 FM(SD3_DAT3) +-#define GPSR4_11 FM(SD3_DAT2) +-#define GPSR4_10 FM(SD3_DAT1) +-#define GPSR4_9 FM(SD3_DAT0) +-#define GPSR4_8 FM(SD3_CMD) +-#define GPSR4_7 FM(SD3_CLK) +-#define GPSR4_6 F_(SD2_DS, IP9_23_20) +-#define GPSR4_5 F_(SD2_DAT3, IP9_19_16) +-#define GPSR4_4 F_(SD2_DAT2, IP9_15_12) +-#define GPSR4_3 F_(SD2_DAT1, IP9_11_8) +-#define GPSR4_2 F_(SD2_DAT0, IP9_7_4) +-#define GPSR4_1 FM(SD2_CMD) ++#define GPSR4_17 F_(SD3_DS, IP11_7_4) ++#define GPSR4_16 F_(SD3_DAT7, IP11_3_0) ++#define GPSR4_15 F_(SD3_DAT6, IP10_31_28) ++#define GPSR4_14 F_(SD3_DAT5, IP10_27_24) ++#define GPSR4_13 F_(SD3_DAT4, IP10_23_20) ++#define GPSR4_12 F_(SD3_DAT3, IP10_19_16) ++#define GPSR4_11 F_(SD3_DAT2, IP10_15_12) ++#define GPSR4_10 F_(SD3_DAT1, IP10_11_8) ++#define GPSR4_9 F_(SD3_DAT0, IP10_7_4) ++#define GPSR4_8 F_(SD3_CMD, IP10_3_0) ++#define GPSR4_7 F_(SD3_CLK, IP9_31_28) ++#define GPSR4_6 F_(SD2_DS, IP9_27_24) ++#define GPSR4_5 F_(SD2_DAT3, IP9_23_20) ++#define GPSR4_4 F_(SD2_DAT2, IP9_19_16) ++#define GPSR4_3 F_(SD2_DAT1, IP9_15_12) ++#define GPSR4_2 F_(SD2_DAT0, IP9_11_8) ++#define GPSR4_1 F_(SD2_CMD, IP9_7_4) + #define GPSR4_0 F_(SD2_CLK, IP9_3_0) + + /* GPSR5 */ +-#define GPSR5_25 F_(MLB_DAT, IP13_19_16) +-#define GPSR5_24 F_(MLB_SIG, IP13_15_12) +-#define GPSR5_23 F_(MLB_CLK, IP13_11_8) ++#define GPSR5_25 F_(MLB_DAT, IP14_19_16) ++#define GPSR5_24 F_(MLB_SIG, IP14_15_12) ++#define GPSR5_23 F_(MLB_CLK, IP14_11_8) + #define GPSR5_22 FM(MSIOF0_RXD) +-#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4) ++#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4) + #define GPSR5_20 FM(MSIOF0_TXD) +-#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0) +-#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28) ++#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0) ++#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28) + #define GPSR5_17 FM(MSIOF0_SCK) +-#define GPSR5_16 F_(HRTS0_N, IP12_27_24) +-#define GPSR5_15 F_(HCTS0_N, IP12_23_20) +-#define GPSR5_14 F_(HTX0, IP12_19_16) +-#define GPSR5_13 F_(HRX0, IP12_15_12) +-#define GPSR5_12 F_(HSCK0, IP12_11_8) +-#define GPSR5_11 F_(RX2_A, IP12_7_4) +-#define GPSR5_10 F_(TX2_A, IP12_3_0) +-#define GPSR5_9 F_(SCK2, IP11_31_28) +-#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24) +-#define GPSR5_7 F_(CTS1_N, IP11_23_20) +-#define GPSR5_6 F_(TX1_A, IP11_19_16) +-#define GPSR5_5 F_(RX1_A, IP11_15_12) +-#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8) +-#define GPSR5_3 F_(CTS0_N, IP11_7_4) +-#define GPSR5_2 F_(TX0, IP11_3_0) +-#define GPSR5_1 F_(RX0, IP10_31_28) +-#define GPSR5_0 F_(SCK0, IP10_27_24) ++#define GPSR5_16 F_(HRTS0_N, IP13_27_24) ++#define GPSR5_15 F_(HCTS0_N, IP13_23_20) ++#define GPSR5_14 F_(HTX0, IP13_19_16) ++#define GPSR5_13 F_(HRX0, IP13_15_12) ++#define GPSR5_12 F_(HSCK0, IP13_11_8) ++#define GPSR5_11 F_(RX2_A, IP13_7_4) ++#define GPSR5_10 F_(TX2_A, IP13_3_0) ++#define GPSR5_9 F_(SCK2, IP12_31_28) ++#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24) ++#define GPSR5_7 F_(CTS1_N, IP12_23_20) ++#define GPSR5_6 F_(TX1_A, IP12_19_16) ++#define GPSR5_5 F_(RX1_A, IP12_15_12) ++#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8) ++#define GPSR5_3 F_(CTS0_N, IP12_7_4) ++#define GPSR5_2 F_(TX0, IP12_3_0) ++#define GPSR5_1 F_(RX0, IP11_31_28) ++#define GPSR5_0 F_(SCK0, IP11_27_24) + + /* GPSR6 */ +-#define GPSR6_31 F_(USB31_OVC, IP17_7_4) +-#define GPSR6_30 F_(USB31_PWEN, IP17_3_0) +-#define GPSR6_29 F_(USB30_OVC, IP16_31_28) +-#define GPSR6_28 F_(USB30_PWEN, IP16_27_24) +-#define GPSR6_27 F_(USB1_OVC, IP16_23_20) +-#define GPSR6_26 F_(USB1_PWEN, IP16_19_16) +-#define GPSR6_25 F_(USB0_OVC, IP16_15_12) +-#define GPSR6_24 F_(USB0_PWEN, IP16_11_8) +-#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4) +-#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0) +-#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28) +-#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24) +-#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20) +-#define GPSR6_18 F_(SSI_WS78, IP15_19_16) +-#define GPSR6_17 F_(SSI_SCK78, IP15_15_12) +-#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8) +-#define GPSR6_15 F_(SSI_WS6, IP15_7_4) +-#define GPSR6_14 F_(SSI_SCK6, IP15_3_0) ++#define GPSR6_31 F_(USB3_OVC, IP18_7_4) ++#define GPSR6_30 F_(USB3_PWEN, IP18_3_0) ++#define GPSR6_29 F_(USB30_OVC, IP17_31_28) ++#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) ++#define GPSR6_27 F_(USB1_OVC, IP17_23_20) ++#define GPSR6_26 F_(USB1_PWEN, IP17_19_16) ++#define GPSR6_25 F_(USB0_OVC, IP17_15_12) ++#define GPSR6_24 F_(USB0_PWEN, IP17_11_8) ++#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4) ++#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0) ++#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28) ++#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24) ++#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20) ++#define GPSR6_18 F_(SSI_WS78, IP16_19_16) ++#define GPSR6_17 F_(SSI_SCK78, IP16_15_12) ++#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8) ++#define GPSR6_15 F_(SSI_WS6, IP16_7_4) ++#define GPSR6_14 F_(SSI_SCK6, IP16_3_0) + #define GPSR6_13 FM(SSI_SDATA5) + #define GPSR6_12 FM(SSI_WS5) + #define GPSR6_11 FM(SSI_SCK5) +-#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28) +-#define GPSR6_9 F_(SSI_WS4, IP14_27_24) +-#define GPSR6_8 F_(SSI_SCK4, IP14_23_20) +-#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16) +-#define GPSR6_6 F_(SSI_WS34, IP14_15_12) +-#define GPSR6_5 F_(SSI_SCK34, IP14_11_8) +-#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) +-#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) +-#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) +-#define GPSR6_1 F_(SSI_WS01239, IP13_27_24) +-#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20) ++#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28) ++#define GPSR6_9 F_(SSI_WS4, IP15_27_24) ++#define GPSR6_8 F_(SSI_SCK4, IP15_23_20) ++#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) ++#define GPSR6_6 F_(SSI_WS34, IP15_15_12) ++#define GPSR6_5 F_(SSI_SCK34, IP15_11_8) ++#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) ++#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) ++#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) ++#define GPSR6_1 F_(SSI_WS01239, IP14_27_24) ++#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) + + /* GPSR7 */ + #define GPSR7_3 FM(HDMI1_CEC) +@@ -212,14 +213,14 @@ + #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +@@ -279,79 +280,89 @@ + #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + + /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ +-#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +-#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0) ++#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++ ++/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ ++#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) ++#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) ++#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) ++#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) ++#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) ++#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) ++#define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) + + #define PINMUX_GPSR \ + \ +@@ -426,37 +437,34 @@ FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM + FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ + FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \ + \ +-FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \ +-FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \ +-FM(IP16_11_8) IP16_11_8 \ +-FM(IP16_15_12) IP16_15_12 \ +-FM(IP16_19_16) IP16_19_16 \ +-FM(IP16_23_20) IP16_23_20 \ +-FM(IP16_27_24) IP16_27_24 \ +-FM(IP16_31_28) IP16_31_28 ++FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \ ++FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \ ++FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \ ++FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \ ++FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \ ++FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \ ++FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \ ++FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 + + /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +-#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) ++#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0) + #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3) + #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0) + #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1) + #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1) +-#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) +-#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1) +-#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1) +-#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) +-#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) +-#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) +-#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) +-#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1) +-#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1) +-#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) +-#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) +-#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) +-#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) +-#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) +-#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) +-#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3) ++#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1) ++#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) ++#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) ++#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) ++#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) ++#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) ++#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) ++#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) ++#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) ++#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) ++#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) ++#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) ++#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) + + /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ + #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) +@@ -486,40 +494,46 @@ FM(IP16_31_28) IP16_31_28 + #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) + #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) + #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) ++#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) ++#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) ++#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ++#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) ++#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) ++#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) ++#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) ++#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) ++#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) + #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) + +-#define PINMUX_MOD_SELS\ ++#define PINMUX_MOD_SELS \ + \ +- MOD_SEL1_31_30 MOD_SEL2_31 \ +-MOD_SEL0_30_29 MOD_SEL2_30 \ ++MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \ ++ MOD_SEL2_30 \ + MOD_SEL1_29_28_27 MOD_SEL2_29 \ +-MOD_SEL0_28_27 \ +-\ +-MOD_SEL0_26_25_24 MOD_SEL1_26 \ +- MOD_SEL1_25_24 \ +-\ ++MOD_SEL0_28_27 MOD_SEL2_28_27 \ ++MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ ++ MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ + MOD_SEL0_23 MOD_SEL1_23_22_21 \ +-MOD_SEL0_22 \ +-MOD_SEL0_21_20 \ +- MOD_SEL1_20 \ +-MOD_SEL0_19 MOD_SEL1_19 \ +-MOD_SEL0_18 MOD_SEL1_18_17 \ +-MOD_SEL0_17 \ +-MOD_SEL0_16_15 MOD_SEL1_16 \ ++MOD_SEL0_22 MOD_SEL2_22 \ ++MOD_SEL0_21 MOD_SEL2_21 \ ++MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ ++MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ ++MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ ++ MOD_SEL2_17 \ ++MOD_SEL0_16 MOD_SEL1_16 \ + MOD_SEL1_15_14 \ +-MOD_SEL0_14 \ +-MOD_SEL0_13 MOD_SEL1_13 \ ++MOD_SEL0_14_13 \ ++ MOD_SEL1_13 \ + MOD_SEL0_12 MOD_SEL1_12 \ + MOD_SEL0_11 MOD_SEL1_11 \ + MOD_SEL0_10 MOD_SEL1_10 \ +-MOD_SEL0_9 MOD_SEL1_9 \ +-MOD_SEL0_8 \ ++MOD_SEL0_9_8 MOD_SEL1_9 \ + MOD_SEL0_7_6 \ + MOD_SEL1_6 \ +-MOD_SEL0_5_4 MOD_SEL1_5 \ +- MOD_SEL1_4 \ +-MOD_SEL0_3 MOD_SEL1_3 \ +-MOD_SEL0_2_1 MOD_SEL1_2 \ ++MOD_SEL0_5 MOD_SEL1_5 \ ++MOD_SEL0_4_3 MOD_SEL1_4 \ ++ MOD_SEL1_3 \ ++ MOD_SEL1_2 \ + MOD_SEL1_1 \ + MOD_SEL1_0 MOD_SEL2_0 + +@@ -583,14 +597,6 @@ static const u16 pinmux_data[] = { + PINMUX_SINGLE(MSIOF0_RXD), + PINMUX_SINGLE(MSIOF0_SCK), + PINMUX_SINGLE(MSIOF0_TXD), +- PINMUX_SINGLE(SD2_CMD), +- PINMUX_SINGLE(SD3_CLK), +- PINMUX_SINGLE(SD3_CMD), +- PINMUX_SINGLE(SD3_DAT0), +- PINMUX_SINGLE(SD3_DAT1), +- PINMUX_SINGLE(SD3_DAT2), +- PINMUX_SINGLE(SD3_DAT3), +- PINMUX_SINGLE(SD3_DS), + PINMUX_SINGLE(SSI_SCK5), + PINMUX_SINGLE(SSI_SDATA5), + PINMUX_SINGLE(SSI_WS5), +@@ -614,6 +620,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), ++ PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), + + PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), +@@ -625,6 +632,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1), ++ PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP0_31_28, IRQ1), + PINMUX_IPSR_GPSR(IP0_31_28, QPOLA), +@@ -632,6 +640,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), + PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), ++ PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), + + /* IPSR1 */ + PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), +@@ -639,6 +648,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1), ++ PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_7_4, IRQ3), + PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE), +@@ -646,6 +656,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1), + PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1), ++ PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), + PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS), +@@ -653,6 +664,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1), ++ PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_15_12, IRQ5), + PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE), +@@ -660,6 +672,8 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1), + PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1), ++ PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B), ++ PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4), + + PINMUX_IPSR_GPSR(IP1_19_16, PWM0), + PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS), +@@ -902,3692 +916,670 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21), + PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5), + +- PINMUX_IPSR_GPSR(IP6_7_4, D6), +- PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), +- PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), +- PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), +- +- PINMUX_IPSR_GPSR(IP6_11_8, D7), +- PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), +- PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), +- PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), +- +- PINMUX_IPSR_GPSR(IP6_15_12, D8), +- PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), +- PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), +- PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), +- +- PINMUX_IPSR_GPSR(IP6_19_16, D9), +- PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), +- PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), +- +- PINMUX_IPSR_GPSR(IP6_23_20, D10), +- PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), +- PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), +- PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), +- PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), +- PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), +- +- PINMUX_IPSR_GPSR(IP6_27_24, D11), +- PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), +- PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), +- PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), +- PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), +- PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), +- +- PINMUX_IPSR_GPSR(IP6_31_28, D12), +- PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), +- PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), +- PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), +- +- /* IPSR7 */ +- PINMUX_IPSR_GPSR(IP7_3_0, D13), +- PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), +- PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), +- PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), +- PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), +- +- PINMUX_IPSR_GPSR(IP7_7_4, D14), +- PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), +- PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), +- PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), +- PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), +- PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), +- +- PINMUX_IPSR_GPSR(IP7_11_8, D15), +- PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), +- PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), +- PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), +- PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), +- PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), +- PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), +- +- PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), +- +- PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), +- PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), +- +- PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), +- PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), +- +- PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), +- PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), +- PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), +- +- PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), +- PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), +- PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), +- +- /* IPSR8 */ +- PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), +- PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), +- PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), +- +- PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), +- PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), +- PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), +- PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), +- +- PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), +- PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), +- +- PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), +- PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), +- PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), +- +- PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), +- PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), +- PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), +- PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), +- +- PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), +- PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), +- PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), +- PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), +- +- PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), +- PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), +- PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), +- PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), +- +- PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), +- PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), +- PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), +- PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), +- PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), +- +- /* IPSR9 */ +- PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), +- +- PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0), +- +- PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1), +- +- PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2), +- +- PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3), +- +- PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS), +- PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1), +- +- PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4), +- PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0), +- +- PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5), +- PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0), +- +- /* IPSR10 */ +- PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6), +- PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD), +- +- PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7), +- PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP), +- +- PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD), +- PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1), +- PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0), +- +- PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP), +- PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1), +- +- PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD), +- PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1), +- +- PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP), +- PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1), +- +- PINMUX_IPSR_GPSR(IP10_27_24, SCK0), +- PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1), +- PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), +- PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1), +- PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), +- PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2), +- +- PINMUX_IPSR_GPSR(IP10_31_28, RX0), +- PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1), +- PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2), +- PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), +- +- /* IPSR11 */ +- PINMUX_IPSR_GPSR(IP11_3_0, TX0), +- PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1), +- PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), +- PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), +- +- PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N), +- PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1), +- PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), +- PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1), +- PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2), +- PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP), +- +- PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS), +- PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1), +- PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0), +- PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1), +- PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1), +- +- PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0), +- PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0), +- PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2), +- PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2), +- +- PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0), +- PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0), +- PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2), +- PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2), +- +- PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N), +- PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0), +- PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2), +- PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1), +- PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA), +- +- PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), +- PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0), +- PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2), +- PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1), +- PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0), +- +- PINMUX_IPSR_GPSR(IP11_31_28, SCK2), +- PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1), +- PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), +- PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2), +- PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1), +- PINMUX_IPSR_GPSR(IP11_31_28, ADICLK), +- +- /* IPSR12 */ +- PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0), +- PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1), +- PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0), +- PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0), +- PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2), +- PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1), +- +- PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0), +- PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1), +- PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0), +- PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0), +- PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2), +- PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1), +- +- PINMUX_IPSR_GPSR(IP12_11_8, HSCK0), +- PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0), +- PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3), +- PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2), +- +- PINMUX_IPSR_GPSR(IP12_15_12, HRX0), +- PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3), +- PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2), +- +- PINMUX_IPSR_GPSR(IP12_19_16, HTX0), +- PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3), +- PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2), +- +- PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N), +- PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1), +- PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), +- PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2), +- PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0), +- +- PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N), +- PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1), +- PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0), +- PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0), +- +- PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), +- PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0), +- +- /* IPSR13 */ +- PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1), +- PINMUX_IPSR_GPSR(IP13_3_0, RX5), +- PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2), +- PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), +- PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0), +- PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1), +- +- PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2), +- PINMUX_IPSR_GPSR(IP13_7_4, TX5), +- PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), +- PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0), +- PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), +- PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3), +- PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), +- +- PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK), +- PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), +- PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1), +- +- PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG), +- PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1), +- PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), +- PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1), +- +- PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT), +- PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1), +- PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), +- +- PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239), +- PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), +- +- PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239), +- PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), +- +- PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0), +- PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), +- +- /* IPSR14 */ +- PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0), +- +- PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), +- +- PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34), +- PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), +- +- PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34), +- PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), +- PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), +- +- PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3), +- PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0), +- PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0), +- PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), +- PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0), +- PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0), +- +- PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4), +- PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0), +- PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0), +- PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0), +- PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0), +- PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0), +- +- PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4), +- PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0), +- PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0), +- PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), +- PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0), +- PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0), +- +- PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4), +- PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0), +- PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), +- PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), +- PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), +- PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0), +- PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0), +- +- /* IPSR15 */ +- PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6), +- PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN), +- PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3), +- +- PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6), +- PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC), +- PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3), +- +- PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6), +- PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3), +- PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0), +- +- PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78), +- PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1), +- PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0), +- PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), +- PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0), +- PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0), +- +- PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78), +- PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1), +- PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0), +- PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0), +- PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0), +- PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0), +- +- PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7), +- PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1), +- PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0), +- PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), +- PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0), +- PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0), +- PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0), +- +- PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8), +- PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1), +- PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), +- PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), +- PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0), +- PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0), +- +- PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1), +- PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0), +- PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1), +- PINMUX_IPSR_GPSR(IP15_31_28, SCK1), +- PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), +- PINMUX_IPSR_GPSR(IP15_31_28, SCK5), +- +- /* IPSR16 */ +- PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0), +- PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT), +- +- PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0), +- PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), +- PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0), +- PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0), +- +- PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN), +- PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2), +- PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3), +- PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), +- PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1), +- PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1), +- +- PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC), +- PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2), +- PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3), +- PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3), +- PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1), +- +- PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN), +- PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2), +- PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4), +- PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1), +- PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1), +- PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), +- +- PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC), +- PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), +- PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0), +- PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4), +- PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1), +- PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1), +- PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1), +- +- PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN), +- PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3), +- PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), +- PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1), +- PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1), +- PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0), +- +- PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC), +- PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), +- PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), +- PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1), +- PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1), +- PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1), +- +- /* IPSR17 */ +- PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN), +- PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4), +- PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1), +- PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2), +- +- PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC), +- PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1), +- PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1), +- PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), +- PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), +- PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1), +- PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3), +- +-/* +- * Static pins can not be muxed between different functions but +- * still needs a mark entry in the pinmux list. Add each static +- * pin to the list without an associated function. The sh-pfc +- * core will do the right thing and skip trying to mux then pin +- * while still applying configuration to it +- */ +-#define FM(x) PINMUX_DATA(x##_MARK, 0), +- PINMUX_STATIC +-#undef FM +-}; +- +-/* +- * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. +- * Physical layout rows: A - AW, cols: 1 - 39. +- */ +-#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) +-#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) +-#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +- +-static const struct sh_pfc_pin pinmux_pins[] = { +- PINMUX_GPIO_GP_ALL(), +- +- /* +- * Pins not associated with a GPIO port. +- * +- * The pin positions are different between different r8a7795 +- * packages, all that is needed for the pfc driver is a unique +- * number for each pin. To this end use the pin layout from +- * R-Car H3SiP to calculate a unique number for each pin. +- */ +- SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), +- SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), +-}; +- +-/* - AUDIO CLOCK ------------------------------------------------------------ */ +-static const unsigned int audio_clk_a_a_pins[] = { +- /* CLK A */ +- RCAR_GP_PIN(6, 22), +-}; +-static const unsigned int audio_clk_a_a_mux[] = { +- AUDIO_CLKA_A_MARK, +-}; +-static const unsigned int audio_clk_a_b_pins[] = { +- /* CLK A */ +- RCAR_GP_PIN(5, 4), +-}; +-static const unsigned int audio_clk_a_b_mux[] = { +- AUDIO_CLKA_B_MARK, +-}; +-static const unsigned int audio_clk_a_c_pins[] = { +- /* CLK A */ +- RCAR_GP_PIN(5, 19), +-}; +-static const unsigned int audio_clk_a_c_mux[] = { +- AUDIO_CLKA_C_MARK, +-}; +-static const unsigned int audio_clk_b_a_pins[] = { +- /* CLK B */ +- RCAR_GP_PIN(5, 12), +-}; +-static const unsigned int audio_clk_b_a_mux[] = { +- AUDIO_CLKB_A_MARK, +-}; +-static const unsigned int audio_clk_b_b_pins[] = { +- /* CLK B */ +- RCAR_GP_PIN(6, 23), +-}; +-static const unsigned int audio_clk_b_b_mux[] = { +- AUDIO_CLKB_B_MARK, +-}; +-static const unsigned int audio_clk_c_a_pins[] = { +- /* CLK C */ +- RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int audio_clk_c_a_mux[] = { +- AUDIO_CLKC_A_MARK, +-}; +-static const unsigned int audio_clk_c_b_pins[] = { +- /* CLK C */ +- RCAR_GP_PIN(5, 0), +-}; +-static const unsigned int audio_clk_c_b_mux[] = { +- AUDIO_CLKC_B_MARK, +-}; +-static const unsigned int audio_clkout_a_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(5, 18), +-}; +-static const unsigned int audio_clkout_a_mux[] = { +- AUDIO_CLKOUT_A_MARK, +-}; +-static const unsigned int audio_clkout_b_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(6, 28), +-}; +-static const unsigned int audio_clkout_b_mux[] = { +- AUDIO_CLKOUT_B_MARK, +-}; +-static const unsigned int audio_clkout_c_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(5, 3), +-}; +-static const unsigned int audio_clkout_c_mux[] = { +- AUDIO_CLKOUT_C_MARK, +-}; +-static const unsigned int audio_clkout_d_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int audio_clkout_d_mux[] = { +- AUDIO_CLKOUT_D_MARK, +-}; +-static const unsigned int audio_clkout1_a_pins[] = { +- /* CLKOUT1 */ +- RCAR_GP_PIN(5, 15), +-}; +-static const unsigned int audio_clkout1_a_mux[] = { +- AUDIO_CLKOUT1_A_MARK, +-}; +-static const unsigned int audio_clkout1_b_pins[] = { +- /* CLKOUT1 */ +- RCAR_GP_PIN(6, 29), +-}; +-static const unsigned int audio_clkout1_b_mux[] = { +- AUDIO_CLKOUT1_B_MARK, +-}; +-static const unsigned int audio_clkout2_a_pins[] = { +- /* CLKOUT2 */ +- RCAR_GP_PIN(5, 16), +-}; +-static const unsigned int audio_clkout2_a_mux[] = { +- AUDIO_CLKOUT2_A_MARK, +-}; +-static const unsigned int audio_clkout2_b_pins[] = { +- /* CLKOUT2 */ +- RCAR_GP_PIN(6, 30), +-}; +-static const unsigned int audio_clkout2_b_mux[] = { +- AUDIO_CLKOUT2_B_MARK, +-}; +- +-static const unsigned int audio_clkout3_a_pins[] = { +- /* CLKOUT3 */ +- RCAR_GP_PIN(5, 19), +-}; +-static const unsigned int audio_clkout3_a_mux[] = { +- AUDIO_CLKOUT3_A_MARK, +-}; +-static const unsigned int audio_clkout3_b_pins[] = { +- /* CLKOUT3 */ +- RCAR_GP_PIN(6, 31), +-}; +-static const unsigned int audio_clkout3_b_mux[] = { +- AUDIO_CLKOUT3_B_MARK, +-}; +- +-/* - EtherAVB --------------------------------------------------------------- */ +-static const unsigned int avb_link_pins[] = { +- /* AVB_LINK */ +- RCAR_GP_PIN(2, 12), +-}; +-static const unsigned int avb_link_mux[] = { +- AVB_LINK_MARK, +-}; +-static const unsigned int avb_magic_pins[] = { +- /* AVB_MAGIC_ */ +- RCAR_GP_PIN(2, 10), +-}; +-static const unsigned int avb_magic_mux[] = { +- AVB_MAGIC_MARK, +-}; +-static const unsigned int avb_phy_int_pins[] = { +- /* AVB_PHY_INT */ +- RCAR_GP_PIN(2, 11), +-}; +-static const unsigned int avb_phy_int_mux[] = { +- AVB_PHY_INT_MARK, +-}; +-static const unsigned int avb_mdc_pins[] = { +- /* AVB_MDC, AVB_MDIO */ +- RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), +-}; +-static const unsigned int avb_mdc_mux[] = { +- AVB_MDC_MARK, AVB_MDIO_MARK, +-}; +-static const unsigned int avb_mii_pins[] = { +- /* +- * AVB_TX_CTL, AVB_TXC, AVB_TD0, +- * AVB_TD1, AVB_TD2, AVB_TD3, +- * AVB_RX_CTL, AVB_RXC, AVB_RD0, +- * AVB_RD1, AVB_RD2, AVB_RD3, +- * AVB_TXCREFCLK +- */ +- PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), +- PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), +- PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), +- PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), +- PIN_NUMBER('A', 12), +- +-}; +-static const unsigned int avb_mii_mux[] = { +- AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, +- AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, +- AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, +- AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, +- AVB_TXCREFCLK_MARK, +-}; +-static const unsigned int avb_avtp_pps_pins[] = { +- /* AVB_AVTP_PPS */ +- RCAR_GP_PIN(2, 6), +-}; +-static const unsigned int avb_avtp_pps_mux[] = { +- AVB_AVTP_PPS_MARK, +-}; +-static const unsigned int avb_avtp_match_a_pins[] = { +- /* AVB_AVTP_MATCH_A */ +- RCAR_GP_PIN(2, 13), +-}; +-static const unsigned int avb_avtp_match_a_mux[] = { +- AVB_AVTP_MATCH_A_MARK, +-}; +-static const unsigned int avb_avtp_capture_a_pins[] = { +- /* AVB_AVTP_CAPTURE_A */ +- RCAR_GP_PIN(2, 14), +-}; +-static const unsigned int avb_avtp_capture_a_mux[] = { +- AVB_AVTP_CAPTURE_A_MARK, +-}; +-static const unsigned int avb_avtp_match_b_pins[] = { +- /* AVB_AVTP_MATCH_B */ +- RCAR_GP_PIN(1, 8), +-}; +-static const unsigned int avb_avtp_match_b_mux[] = { +- AVB_AVTP_MATCH_B_MARK, +-}; +-static const unsigned int avb_avtp_capture_b_pins[] = { +- /* AVB_AVTP_CAPTURE_B */ +- RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int avb_avtp_capture_b_mux[] = { +- AVB_AVTP_CAPTURE_B_MARK, +-}; +- +-/* - CAN ------------------------------------------------------------------ */ +-static const unsigned int can0_data_a_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +-}; +-static const unsigned int can0_data_a_mux[] = { +- CAN0_TX_A_MARK, CAN0_RX_A_MARK, +-}; +-static const unsigned int can0_data_b_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +-}; +-static const unsigned int can0_data_b_mux[] = { +- CAN0_TX_B_MARK, CAN0_RX_B_MARK, +-}; +-static const unsigned int can1_data_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +-}; +-static const unsigned int can1_data_mux[] = { +- CAN1_TX_MARK, CAN1_RX_MARK, +-}; +- +-/* - CAN Clock -------------------------------------------------------------- */ +-static const unsigned int can_clk_pins[] = { +- /* CLK */ +- RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int can_clk_mux[] = { +- CAN_CLK_MARK, +-}; +- +-/* - CAN FD --------------------------------------------------------------- */ +-static const unsigned int canfd0_data_a_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +-}; +-static const unsigned int canfd0_data_a_mux[] = { +- CANFD0_TX_A_MARK, CANFD0_RX_A_MARK, +-}; +-static const unsigned int canfd0_data_b_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), +-}; +-static const unsigned int canfd0_data_b_mux[] = { +- CANFD0_TX_B_MARK, CANFD0_RX_B_MARK, +-}; +-static const unsigned int canfd1_data_pins[] = { +- /* TX, RX */ +- RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26), +-}; +-static const unsigned int canfd1_data_mux[] = { +- CANFD1_TX_MARK, CANFD1_RX_MARK, +-}; +- +-/* - DRIF0 --------------------------------------------------------------- */ +-static const unsigned int drif0_ctrl_a_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +-}; +-static const unsigned int drif0_ctrl_a_mux[] = { +- RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, +-}; +-static const unsigned int drif0_data0_a_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 10), +-}; +-static const unsigned int drif0_data0_a_mux[] = { +- RIF0_D0_A_MARK, +-}; +-static const unsigned int drif0_data1_a_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 7), +-}; +-static const unsigned int drif0_data1_a_mux[] = { +- RIF0_D1_A_MARK, +-}; +-static const unsigned int drif0_ctrl_b_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +-}; +-static const unsigned int drif0_ctrl_b_mux[] = { +- RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, +-}; +-static const unsigned int drif0_data0_b_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(5, 1), +-}; +-static const unsigned int drif0_data0_b_mux[] = { +- RIF0_D0_B_MARK, +-}; +-static const unsigned int drif0_data1_b_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(5, 2), +-}; +-static const unsigned int drif0_data1_b_mux[] = { +- RIF0_D1_B_MARK, +-}; +-static const unsigned int drif0_ctrl_c_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), +-}; +-static const unsigned int drif0_ctrl_c_mux[] = { +- RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, +-}; +-static const unsigned int drif0_data0_c_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(5, 13), +-}; +-static const unsigned int drif0_data0_c_mux[] = { +- RIF0_D0_C_MARK, +-}; +-static const unsigned int drif0_data1_c_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(5, 14), +-}; +-static const unsigned int drif0_data1_c_mux[] = { +- RIF0_D1_C_MARK, +-}; +-/* - DRIF1 --------------------------------------------------------------- */ +-static const unsigned int drif1_ctrl_a_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +-}; +-static const unsigned int drif1_ctrl_a_mux[] = { +- RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, +-}; +-static const unsigned int drif1_data0_a_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 19), +-}; +-static const unsigned int drif1_data0_a_mux[] = { +- RIF1_D0_A_MARK, +-}; +-static const unsigned int drif1_data1_a_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 20), +-}; +-static const unsigned int drif1_data1_a_mux[] = { +- RIF1_D1_A_MARK, +-}; +-static const unsigned int drif1_ctrl_b_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), +-}; +-static const unsigned int drif1_ctrl_b_mux[] = { +- RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, +-}; +-static const unsigned int drif1_data0_b_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(5, 7), +-}; +-static const unsigned int drif1_data0_b_mux[] = { +- RIF1_D0_B_MARK, +-}; +-static const unsigned int drif1_data1_b_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(5, 8), +-}; +-static const unsigned int drif1_data1_b_mux[] = { +- RIF1_D1_B_MARK, +-}; +-static const unsigned int drif1_ctrl_c_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), +-}; +-static const unsigned int drif1_ctrl_c_mux[] = { +- RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, +-}; +-static const unsigned int drif1_data0_c_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(5, 6), +-}; +-static const unsigned int drif1_data0_c_mux[] = { +- RIF1_D0_C_MARK, +-}; +-static const unsigned int drif1_data1_c_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(5, 10), +-}; +-static const unsigned int drif1_data1_c_mux[] = { +- RIF1_D1_C_MARK, +-}; +-/* - DRIF2 --------------------------------------------------------------- */ +-static const unsigned int drif2_ctrl_a_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +-}; +-static const unsigned int drif2_ctrl_a_mux[] = { +- RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, +-}; +-static const unsigned int drif2_data0_a_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 7), +-}; +-static const unsigned int drif2_data0_a_mux[] = { +- RIF2_D0_A_MARK, +-}; +-static const unsigned int drif2_data1_a_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 10), +-}; +-static const unsigned int drif2_data1_a_mux[] = { +- RIF2_D1_A_MARK, +-}; +-static const unsigned int drif2_ctrl_b_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +-}; +-static const unsigned int drif2_ctrl_b_mux[] = { +- RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, +-}; +-static const unsigned int drif2_data0_b_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 30), +-}; +-static const unsigned int drif2_data0_b_mux[] = { +- RIF2_D0_B_MARK, +-}; +-static const unsigned int drif2_data1_b_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 31), +-}; +-static const unsigned int drif2_data1_b_mux[] = { +- RIF2_D1_B_MARK, +-}; +-/* - DRIF3 --------------------------------------------------------------- */ +-static const unsigned int drif3_ctrl_a_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +-}; +-static const unsigned int drif3_ctrl_a_mux[] = { +- RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, +-}; +-static const unsigned int drif3_data0_a_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 19), +-}; +-static const unsigned int drif3_data0_a_mux[] = { +- RIF3_D0_A_MARK, +-}; +-static const unsigned int drif3_data1_a_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 20), +-}; +-static const unsigned int drif3_data1_a_mux[] = { +- RIF3_D1_A_MARK, +-}; +-static const unsigned int drif3_ctrl_b_pins[] = { +- /* CLK, SYNC */ +- RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +-}; +-static const unsigned int drif3_ctrl_b_mux[] = { +- RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, +-}; +-static const unsigned int drif3_data0_b_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(6, 28), +-}; +-static const unsigned int drif3_data0_b_mux[] = { +- RIF3_D0_B_MARK, +-}; +-static const unsigned int drif3_data1_b_pins[] = { +- /* D1 */ +- RCAR_GP_PIN(6, 29), +-}; +-static const unsigned int drif3_data1_b_mux[] = { +- RIF3_D1_B_MARK, +-}; +- +-/* - DU --------------------------------------------------------------------- */ +-static const unsigned int du_rgb666_pins[] = { +- /* R[7:2], G[7:2], B[7:2] */ +- RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), +- RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), +- RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +- RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), +- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +-}; +-static const unsigned int du_rgb666_mux[] = { +- DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, +- DU_DR3_MARK, DU_DR2_MARK, +- DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, +- DU_DG3_MARK, DU_DG2_MARK, +- DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, +- DU_DB3_MARK, DU_DB2_MARK, +-}; +-static const unsigned int du_rgb888_pins[] = { +- /* R[7:0], G[7:0], B[7:0] */ +- RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), +- RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), +- RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), +- RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), +- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), +- RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), +- RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), +- RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +- RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +-}; +-static const unsigned int du_rgb888_mux[] = { +- DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, +- DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, +- DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, +- DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, +- DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, +- DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, +-}; +-static const unsigned int du_clk_out_0_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(1, 27), +-}; +-static const unsigned int du_clk_out_0_mux[] = { +- DU_DOTCLKOUT0_MARK +-}; +-static const unsigned int du_clk_out_1_pins[] = { +- /* CLKOUT */ +- RCAR_GP_PIN(2, 3), +-}; +-static const unsigned int du_clk_out_1_mux[] = { +- DU_DOTCLKOUT1_MARK +-}; +-static const unsigned int du_sync_pins[] = { +- /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ +- RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +-}; +-static const unsigned int du_sync_mux[] = { +- DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK +-}; +-static const unsigned int du_oddf_pins[] = { +- /* EXDISP/EXODDF/EXCDE */ +- RCAR_GP_PIN(2, 2), +-}; +-static const unsigned int du_oddf_mux[] = { +- DU_EXODDF_DU_ODDF_DISP_CDE_MARK, +-}; +-static const unsigned int du_cde_pins[] = { +- /* CDE */ +- RCAR_GP_PIN(2, 0), +-}; +-static const unsigned int du_cde_mux[] = { +- DU_CDE_MARK, +-}; +-static const unsigned int du_disp_pins[] = { +- /* DISP */ +- RCAR_GP_PIN(2, 1), +-}; +-static const unsigned int du_disp_mux[] = { +- DU_DISP_MARK, +-}; +-/* - HSCIF0 ----------------------------------------------------------------- */ +-static const unsigned int hscif0_data_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +-}; +-static const unsigned int hscif0_data_mux[] = { +- HRX0_MARK, HTX0_MARK, +-}; +-static const unsigned int hscif0_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 12), +-}; +-static const unsigned int hscif0_clk_mux[] = { +- HSCK0_MARK, +-}; +-static const unsigned int hscif0_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +-}; +-static const unsigned int hscif0_ctrl_mux[] = { +- HRTS0_N_MARK, HCTS0_N_MARK, +-}; +-/* - HSCIF1 ----------------------------------------------------------------- */ +-static const unsigned int hscif1_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +-}; +-static const unsigned int hscif1_data_a_mux[] = { +- HRX1_A_MARK, HTX1_A_MARK, +-}; +-static const unsigned int hscif1_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int hscif1_clk_a_mux[] = { +- HSCK1_A_MARK, +-}; +-static const unsigned int hscif1_ctrl_a_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +-}; +-static const unsigned int hscif1_ctrl_a_mux[] = { +- HRTS1_N_A_MARK, HCTS1_N_A_MARK, +-}; +- +-static const unsigned int hscif1_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +-}; +-static const unsigned int hscif1_data_b_mux[] = { +- HRX1_B_MARK, HTX1_B_MARK, +-}; +-static const unsigned int hscif1_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 0), +-}; +-static const unsigned int hscif1_clk_b_mux[] = { +- HSCK1_B_MARK, +-}; +-static const unsigned int hscif1_ctrl_b_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +-}; +-static const unsigned int hscif1_ctrl_b_mux[] = { +- HRTS1_N_B_MARK, HCTS1_N_B_MARK, +-}; +-/* - HSCIF2 ----------------------------------------------------------------- */ +-static const unsigned int hscif2_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +-}; +-static const unsigned int hscif2_data_a_mux[] = { +- HRX2_A_MARK, HTX2_A_MARK, +-}; +-static const unsigned int hscif2_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 10), +-}; +-static const unsigned int hscif2_clk_a_mux[] = { +- HSCK2_A_MARK, +-}; +-static const unsigned int hscif2_ctrl_a_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +-}; +-static const unsigned int hscif2_ctrl_a_mux[] = { +- HRTS2_N_A_MARK, HCTS2_N_A_MARK, +-}; +- +-static const unsigned int hscif2_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +-}; +-static const unsigned int hscif2_data_b_mux[] = { +- HRX2_B_MARK, HTX2_B_MARK, +-}; +-static const unsigned int hscif2_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int hscif2_clk_b_mux[] = { +- HSCK2_B_MARK, +-}; +-static const unsigned int hscif2_ctrl_b_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), +-}; +-static const unsigned int hscif2_ctrl_b_mux[] = { +- HRTS2_N_B_MARK, HCTS2_N_B_MARK, +-}; +-/* - HSCIF3 ----------------------------------------------------------------- */ +-static const unsigned int hscif3_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +-}; +-static const unsigned int hscif3_data_a_mux[] = { +- HRX3_A_MARK, HTX3_A_MARK, +-}; +-static const unsigned int hscif3_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 22), +-}; +-static const unsigned int hscif3_clk_mux[] = { +- HSCK3_MARK, +-}; +-static const unsigned int hscif3_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int hscif3_ctrl_mux[] = { +- HRTS3_N_MARK, HCTS3_N_MARK, +-}; +- +-static const unsigned int hscif3_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), +-}; +-static const unsigned int hscif3_data_b_mux[] = { +- HRX3_B_MARK, HTX3_B_MARK, +-}; +-static const unsigned int hscif3_data_c_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +-}; +-static const unsigned int hscif3_data_c_mux[] = { +- HRX3_C_MARK, HTX3_C_MARK, +-}; +-static const unsigned int hscif3_data_d_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +-}; +-static const unsigned int hscif3_data_d_mux[] = { +- HRX3_D_MARK, HTX3_D_MARK, +-}; +-/* - HSCIF4 ----------------------------------------------------------------- */ +-static const unsigned int hscif4_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +-}; +-static const unsigned int hscif4_data_a_mux[] = { +- HRX4_A_MARK, HTX4_A_MARK, +-}; +-static const unsigned int hscif4_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int hscif4_clk_mux[] = { +- HSCK4_MARK, +-}; +-static const unsigned int hscif4_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +-}; +-static const unsigned int hscif4_ctrl_mux[] = { +- HRTS4_N_MARK, HCTS4_N_MARK, +-}; +- +-static const unsigned int hscif4_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int hscif4_data_b_mux[] = { +- HRX4_B_MARK, HTX4_B_MARK, +-}; +- +-/* - I2C -------------------------------------------------------------------- */ +-static const unsigned int i2c1_a_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +-}; +-static const unsigned int i2c1_a_mux[] = { +- SDA1_A_MARK, SCL1_A_MARK, +-}; +-static const unsigned int i2c1_b_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), +-}; +-static const unsigned int i2c1_b_mux[] = { +- SDA1_B_MARK, SCL1_B_MARK, +-}; +-static const unsigned int i2c2_a_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +-}; +-static const unsigned int i2c2_a_mux[] = { +- SDA2_A_MARK, SCL2_A_MARK, +-}; +-static const unsigned int i2c2_b_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +-}; +-static const unsigned int i2c2_b_mux[] = { +- SDA2_B_MARK, SCL2_B_MARK, +-}; +-static const unsigned int i2c6_a_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int i2c6_a_mux[] = { +- SDA6_A_MARK, SCL6_A_MARK, +-}; +-static const unsigned int i2c6_b_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int i2c6_b_mux[] = { +- SDA6_B_MARK, SCL6_B_MARK, +-}; +-static const unsigned int i2c6_c_pins[] = { +- /* SDA, SCL */ +- RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +-}; +-static const unsigned int i2c6_c_mux[] = { +- SDA6_C_MARK, SCL6_C_MARK, +-}; +- +-/* - INTC-EX ---------------------------------------------------------------- */ +-static const unsigned int intc_ex_irq0_pins[] = { +- /* IRQ0 */ +- RCAR_GP_PIN(2, 0), +-}; +-static const unsigned int intc_ex_irq0_mux[] = { +- IRQ0_MARK, +-}; +-static const unsigned int intc_ex_irq1_pins[] = { +- /* IRQ1 */ +- RCAR_GP_PIN(2, 1), +-}; +-static const unsigned int intc_ex_irq1_mux[] = { +- IRQ1_MARK, +-}; +-static const unsigned int intc_ex_irq2_pins[] = { +- /* IRQ2 */ +- RCAR_GP_PIN(2, 2), +-}; +-static const unsigned int intc_ex_irq2_mux[] = { +- IRQ2_MARK, +-}; +-static const unsigned int intc_ex_irq3_pins[] = { +- /* IRQ3 */ +- RCAR_GP_PIN(2, 3), +-}; +-static const unsigned int intc_ex_irq3_mux[] = { +- IRQ3_MARK, +-}; +-static const unsigned int intc_ex_irq4_pins[] = { +- /* IRQ4 */ +- RCAR_GP_PIN(2, 4), +-}; +-static const unsigned int intc_ex_irq4_mux[] = { +- IRQ4_MARK, +-}; +-static const unsigned int intc_ex_irq5_pins[] = { +- /* IRQ5 */ +- RCAR_GP_PIN(2, 5), +-}; +-static const unsigned int intc_ex_irq5_mux[] = { +- IRQ5_MARK, +-}; +- +-/* - MSIOF0 ----------------------------------------------------------------- */ +-static const unsigned int msiof0_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 17), +-}; +-static const unsigned int msiof0_clk_mux[] = { +- MSIOF0_SCK_MARK, +-}; +-static const unsigned int msiof0_sync_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(5, 18), +-}; +-static const unsigned int msiof0_sync_mux[] = { +- MSIOF0_SYNC_MARK, +-}; +-static const unsigned int msiof0_ss1_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(5, 19), +-}; +-static const unsigned int msiof0_ss1_mux[] = { +- MSIOF0_SS1_MARK, +-}; +-static const unsigned int msiof0_ss2_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int msiof0_ss2_mux[] = { +- MSIOF0_SS2_MARK, +-}; +-static const unsigned int msiof0_txd_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(5, 20), +-}; +-static const unsigned int msiof0_txd_mux[] = { +- MSIOF0_TXD_MARK, +-}; +-static const unsigned int msiof0_rxd_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(5, 22), +-}; +-static const unsigned int msiof0_rxd_mux[] = { +- MSIOF0_RXD_MARK, +-}; +-/* - MSIOF1 ----------------------------------------------------------------- */ +-static const unsigned int msiof1_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 8), +-}; +-static const unsigned int msiof1_clk_a_mux[] = { +- MSIOF1_SCK_A_MARK, +-}; +-static const unsigned int msiof1_sync_a_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(6, 9), +-}; +-static const unsigned int msiof1_sync_a_mux[] = { +- MSIOF1_SYNC_A_MARK, +-}; +-static const unsigned int msiof1_ss1_a_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(6, 5), +-}; +-static const unsigned int msiof1_ss1_a_mux[] = { +- MSIOF1_SS1_A_MARK, +-}; +-static const unsigned int msiof1_ss2_a_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(6, 6), +-}; +-static const unsigned int msiof1_ss2_a_mux[] = { +- MSIOF1_SS2_A_MARK, +-}; +-static const unsigned int msiof1_txd_a_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(6, 7), +-}; +-static const unsigned int msiof1_txd_a_mux[] = { +- MSIOF1_TXD_A_MARK, +-}; +-static const unsigned int msiof1_rxd_a_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(6, 10), +-}; +-static const unsigned int msiof1_rxd_a_mux[] = { +- MSIOF1_RXD_A_MARK, +-}; +-static const unsigned int msiof1_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 9), +-}; +-static const unsigned int msiof1_clk_b_mux[] = { +- MSIOF1_SCK_B_MARK, +-}; +-static const unsigned int msiof1_sync_b_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(5, 3), +-}; +-static const unsigned int msiof1_sync_b_mux[] = { +- MSIOF1_SYNC_B_MARK, +-}; +-static const unsigned int msiof1_ss1_b_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(5, 4), +-}; +-static const unsigned int msiof1_ss1_b_mux[] = { +- MSIOF1_SS1_B_MARK, +-}; +-static const unsigned int msiof1_ss2_b_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(5, 0), +-}; +-static const unsigned int msiof1_ss2_b_mux[] = { +- MSIOF1_SS2_B_MARK, +-}; +-static const unsigned int msiof1_txd_b_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(5, 8), +-}; +-static const unsigned int msiof1_txd_b_mux[] = { +- MSIOF1_TXD_B_MARK, +-}; +-static const unsigned int msiof1_rxd_b_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(5, 7), +-}; +-static const unsigned int msiof1_rxd_b_mux[] = { +- MSIOF1_RXD_B_MARK, +-}; +-static const unsigned int msiof1_clk_c_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 17), +-}; +-static const unsigned int msiof1_clk_c_mux[] = { +- MSIOF1_SCK_C_MARK, +-}; +-static const unsigned int msiof1_sync_c_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(6, 18), +-}; +-static const unsigned int msiof1_sync_c_mux[] = { +- MSIOF1_SYNC_C_MARK, +-}; +-static const unsigned int msiof1_ss1_c_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int msiof1_ss1_c_mux[] = { +- MSIOF1_SS1_C_MARK, +-}; +-static const unsigned int msiof1_ss2_c_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(6, 27), +-}; +-static const unsigned int msiof1_ss2_c_mux[] = { +- MSIOF1_SS2_C_MARK, +-}; +-static const unsigned int msiof1_txd_c_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(6, 20), +-}; +-static const unsigned int msiof1_txd_c_mux[] = { +- MSIOF1_TXD_C_MARK, +-}; +-static const unsigned int msiof1_rxd_c_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(6, 19), +-}; +-static const unsigned int msiof1_rxd_c_mux[] = { +- MSIOF1_RXD_C_MARK, +-}; +-static const unsigned int msiof1_clk_d_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 12), +-}; +-static const unsigned int msiof1_clk_d_mux[] = { +- MSIOF1_SCK_D_MARK, +-}; +-static const unsigned int msiof1_sync_d_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(5, 15), +-}; +-static const unsigned int msiof1_sync_d_mux[] = { +- MSIOF1_SYNC_D_MARK, +-}; +-static const unsigned int msiof1_ss1_d_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(5, 16), +-}; +-static const unsigned int msiof1_ss1_d_mux[] = { +- MSIOF1_SS1_D_MARK, +-}; +-static const unsigned int msiof1_ss2_d_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int msiof1_ss2_d_mux[] = { +- MSIOF1_SS2_D_MARK, +-}; +-static const unsigned int msiof1_txd_d_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(5, 14), +-}; +-static const unsigned int msiof1_txd_d_mux[] = { +- MSIOF1_TXD_D_MARK, +-}; +-static const unsigned int msiof1_rxd_d_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(5, 13), +-}; +-static const unsigned int msiof1_rxd_d_mux[] = { +- MSIOF1_RXD_D_MARK, +-}; +-static const unsigned int msiof1_clk_e_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(3, 0), +-}; +-static const unsigned int msiof1_clk_e_mux[] = { +- MSIOF1_SCK_E_MARK, +-}; +-static const unsigned int msiof1_sync_e_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(3, 1), +-}; +-static const unsigned int msiof1_sync_e_mux[] = { +- MSIOF1_SYNC_E_MARK, +-}; +-static const unsigned int msiof1_ss1_e_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(3, 4), +-}; +-static const unsigned int msiof1_ss1_e_mux[] = { +- MSIOF1_SS1_E_MARK, +-}; +-static const unsigned int msiof1_ss2_e_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(3, 5), +-}; +-static const unsigned int msiof1_ss2_e_mux[] = { +- MSIOF1_SS2_E_MARK, +-}; +-static const unsigned int msiof1_txd_e_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(3, 3), +-}; +-static const unsigned int msiof1_txd_e_mux[] = { +- MSIOF1_TXD_E_MARK, +-}; +-static const unsigned int msiof1_rxd_e_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(3, 2), +-}; +-static const unsigned int msiof1_rxd_e_mux[] = { +- MSIOF1_RXD_E_MARK, +-}; +-static const unsigned int msiof1_clk_f_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 23), +-}; +-static const unsigned int msiof1_clk_f_mux[] = { +- MSIOF1_SCK_F_MARK, +-}; +-static const unsigned int msiof1_sync_f_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(5, 24), +-}; +-static const unsigned int msiof1_sync_f_mux[] = { +- MSIOF1_SYNC_F_MARK, +-}; +-static const unsigned int msiof1_ss1_f_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(6, 1), +-}; +-static const unsigned int msiof1_ss1_f_mux[] = { +- MSIOF1_SS1_F_MARK, +-}; +-static const unsigned int msiof1_ss2_f_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(6, 2), +-}; +-static const unsigned int msiof1_ss2_f_mux[] = { +- MSIOF1_SS2_F_MARK, +-}; +-static const unsigned int msiof1_txd_f_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(6, 0), +-}; +-static const unsigned int msiof1_txd_f_mux[] = { +- MSIOF1_TXD_F_MARK, +-}; +-static const unsigned int msiof1_rxd_f_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(5, 25), +-}; +-static const unsigned int msiof1_rxd_f_mux[] = { +- MSIOF1_RXD_F_MARK, +-}; +-static const unsigned int msiof1_clk_g_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(3, 6), +-}; +-static const unsigned int msiof1_clk_g_mux[] = { +- MSIOF1_SCK_G_MARK, +-}; +-static const unsigned int msiof1_sync_g_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(3, 7), +-}; +-static const unsigned int msiof1_sync_g_mux[] = { +- MSIOF1_SYNC_G_MARK, +-}; +-static const unsigned int msiof1_ss1_g_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(3, 10), +-}; +-static const unsigned int msiof1_ss1_g_mux[] = { +- MSIOF1_SS1_G_MARK, +-}; +-static const unsigned int msiof1_ss2_g_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(3, 11), +-}; +-static const unsigned int msiof1_ss2_g_mux[] = { +- MSIOF1_SS2_G_MARK, +-}; +-static const unsigned int msiof1_txd_g_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(3, 9), +-}; +-static const unsigned int msiof1_txd_g_mux[] = { +- MSIOF1_TXD_G_MARK, +-}; +-static const unsigned int msiof1_rxd_g_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(3, 8), +-}; +-static const unsigned int msiof1_rxd_g_mux[] = { +- MSIOF1_RXD_G_MARK, +-}; +-/* - MSIOF2 ----------------------------------------------------------------- */ +-static const unsigned int msiof2_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 9), +-}; +-static const unsigned int msiof2_clk_a_mux[] = { +- MSIOF2_SCK_A_MARK, +-}; +-static const unsigned int msiof2_sync_a_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(1, 8), +-}; +-static const unsigned int msiof2_sync_a_mux[] = { +- MSIOF2_SYNC_A_MARK, +-}; +-static const unsigned int msiof2_ss1_a_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(1, 6), +-}; +-static const unsigned int msiof2_ss1_a_mux[] = { +- MSIOF2_SS1_A_MARK, +-}; +-static const unsigned int msiof2_ss2_a_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(1, 7), +-}; +-static const unsigned int msiof2_ss2_a_mux[] = { +- MSIOF2_SS2_A_MARK, +-}; +-static const unsigned int msiof2_txd_a_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int msiof2_txd_a_mux[] = { +- MSIOF2_TXD_A_MARK, +-}; +-static const unsigned int msiof2_rxd_a_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(1, 10), +-}; +-static const unsigned int msiof2_rxd_a_mux[] = { +- MSIOF2_RXD_A_MARK, +-}; +-static const unsigned int msiof2_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(0, 4), +-}; +-static const unsigned int msiof2_clk_b_mux[] = { +- MSIOF2_SCK_B_MARK, +-}; +-static const unsigned int msiof2_sync_b_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(0, 5), +-}; +-static const unsigned int msiof2_sync_b_mux[] = { +- MSIOF2_SYNC_B_MARK, +-}; +-static const unsigned int msiof2_ss1_b_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(0, 0), +-}; +-static const unsigned int msiof2_ss1_b_mux[] = { +- MSIOF2_SS1_B_MARK, +-}; +-static const unsigned int msiof2_ss2_b_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(0, 1), +-}; +-static const unsigned int msiof2_ss2_b_mux[] = { +- MSIOF2_SS2_B_MARK, +-}; +-static const unsigned int msiof2_txd_b_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(0, 7), +-}; +-static const unsigned int msiof2_txd_b_mux[] = { +- MSIOF2_TXD_B_MARK, +-}; +-static const unsigned int msiof2_rxd_b_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(0, 6), +-}; +-static const unsigned int msiof2_rxd_b_mux[] = { +- MSIOF2_RXD_B_MARK, +-}; +-static const unsigned int msiof2_clk_c_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(2, 12), +-}; +-static const unsigned int msiof2_clk_c_mux[] = { +- MSIOF2_SCK_C_MARK, +-}; +-static const unsigned int msiof2_sync_c_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(2, 11), +-}; +-static const unsigned int msiof2_sync_c_mux[] = { +- MSIOF2_SYNC_C_MARK, +-}; +-static const unsigned int msiof2_ss1_c_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(2, 10), +-}; +-static const unsigned int msiof2_ss1_c_mux[] = { +- MSIOF2_SS1_C_MARK, +-}; +-static const unsigned int msiof2_ss2_c_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(2, 9), +-}; +-static const unsigned int msiof2_ss2_c_mux[] = { +- MSIOF2_SS2_C_MARK, +-}; +-static const unsigned int msiof2_txd_c_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(2, 14), +-}; +-static const unsigned int msiof2_txd_c_mux[] = { +- MSIOF2_TXD_C_MARK, +-}; +-static const unsigned int msiof2_rxd_c_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(2, 13), +-}; +-static const unsigned int msiof2_rxd_c_mux[] = { +- MSIOF2_RXD_C_MARK, +-}; +-static const unsigned int msiof2_clk_d_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(0, 8), +-}; +-static const unsigned int msiof2_clk_d_mux[] = { +- MSIOF2_SCK_D_MARK, +-}; +-static const unsigned int msiof2_sync_d_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(0, 9), +-}; +-static const unsigned int msiof2_sync_d_mux[] = { +- MSIOF2_SYNC_D_MARK, +-}; +-static const unsigned int msiof2_ss1_d_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(0, 12), +-}; +-static const unsigned int msiof2_ss1_d_mux[] = { +- MSIOF2_SS1_D_MARK, +-}; +-static const unsigned int msiof2_ss2_d_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(0, 13), +-}; +-static const unsigned int msiof2_ss2_d_mux[] = { +- MSIOF2_SS2_D_MARK, +-}; +-static const unsigned int msiof2_txd_d_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(0, 11), +-}; +-static const unsigned int msiof2_txd_d_mux[] = { +- MSIOF2_TXD_D_MARK, +-}; +-static const unsigned int msiof2_rxd_d_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(0, 10), +-}; +-static const unsigned int msiof2_rxd_d_mux[] = { +- MSIOF2_RXD_D_MARK, +-}; +-/* - MSIOF3 ----------------------------------------------------------------- */ +-static const unsigned int msiof3_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(0, 0), +-}; +-static const unsigned int msiof3_clk_a_mux[] = { +- MSIOF3_SCK_A_MARK, +-}; +-static const unsigned int msiof3_sync_a_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(0, 1), +-}; +-static const unsigned int msiof3_sync_a_mux[] = { +- MSIOF3_SYNC_A_MARK, +-}; +-static const unsigned int msiof3_ss1_a_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(0, 14), +-}; +-static const unsigned int msiof3_ss1_a_mux[] = { +- MSIOF3_SS1_A_MARK, +-}; +-static const unsigned int msiof3_ss2_a_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(0, 15), +-}; +-static const unsigned int msiof3_ss2_a_mux[] = { +- MSIOF3_SS2_A_MARK, +-}; +-static const unsigned int msiof3_txd_a_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(0, 3), +-}; +-static const unsigned int msiof3_txd_a_mux[] = { +- MSIOF3_TXD_A_MARK, +-}; +-static const unsigned int msiof3_rxd_a_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(0, 2), +-}; +-static const unsigned int msiof3_rxd_a_mux[] = { +- MSIOF3_RXD_A_MARK, +-}; +-static const unsigned int msiof3_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 2), +-}; +-static const unsigned int msiof3_clk_b_mux[] = { +- MSIOF3_SCK_B_MARK, +-}; +-static const unsigned int msiof3_sync_b_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(1, 0), +-}; +-static const unsigned int msiof3_sync_b_mux[] = { +- MSIOF3_SYNC_B_MARK, +-}; +-static const unsigned int msiof3_ss1_b_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(1, 4), +-}; +-static const unsigned int msiof3_ss1_b_mux[] = { +- MSIOF3_SS1_B_MARK, +-}; +-static const unsigned int msiof3_ss2_b_pins[] = { +- /* SS2 */ +- RCAR_GP_PIN(1, 5), +-}; +-static const unsigned int msiof3_ss2_b_mux[] = { +- MSIOF3_SS2_B_MARK, +-}; +-static const unsigned int msiof3_txd_b_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(1, 1), +-}; +-static const unsigned int msiof3_txd_b_mux[] = { +- MSIOF3_TXD_B_MARK, +-}; +-static const unsigned int msiof3_rxd_b_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(1, 3), +-}; +-static const unsigned int msiof3_rxd_b_mux[] = { +- MSIOF3_RXD_B_MARK, +-}; +-static const unsigned int msiof3_clk_c_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 12), +-}; +-static const unsigned int msiof3_clk_c_mux[] = { +- MSIOF3_SCK_C_MARK, +-}; +-static const unsigned int msiof3_sync_c_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(1, 13), +-}; +-static const unsigned int msiof3_sync_c_mux[] = { +- MSIOF3_SYNC_C_MARK, +-}; +-static const unsigned int msiof3_txd_c_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(1, 15), +-}; +-static const unsigned int msiof3_txd_c_mux[] = { +- MSIOF3_TXD_C_MARK, +-}; +-static const unsigned int msiof3_rxd_c_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(1, 14), +-}; +-static const unsigned int msiof3_rxd_c_mux[] = { +- MSIOF3_RXD_C_MARK, +-}; +-static const unsigned int msiof3_clk_d_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 22), +-}; +-static const unsigned int msiof3_clk_d_mux[] = { +- MSIOF3_SCK_D_MARK, +-}; +-static const unsigned int msiof3_sync_d_pins[] = { +- /* SYNC */ +- RCAR_GP_PIN(1, 23), +-}; +-static const unsigned int msiof3_sync_d_mux[] = { +- MSIOF3_SYNC_D_MARK, +-}; +-static const unsigned int msiof3_ss1_d_pins[] = { +- /* SS1 */ +- RCAR_GP_PIN(1, 26), +-}; +-static const unsigned int msiof3_ss1_d_mux[] = { +- MSIOF3_SS1_D_MARK, +-}; +-static const unsigned int msiof3_txd_d_pins[] = { +- /* TXD */ +- RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int msiof3_txd_d_mux[] = { +- MSIOF3_TXD_D_MARK, +-}; +-static const unsigned int msiof3_rxd_d_pins[] = { +- /* RXD */ +- RCAR_GP_PIN(1, 24), +-}; +-static const unsigned int msiof3_rxd_d_mux[] = { +- MSIOF3_RXD_D_MARK, +-}; +- +-/* - PWM0 --------------------------------------------------------------------*/ +-static const unsigned int pwm0_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 6), +-}; +-static const unsigned int pwm0_mux[] = { +- PWM0_MARK, +-}; +-/* - PWM1 --------------------------------------------------------------------*/ +-static const unsigned int pwm1_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 7), +-}; +-static const unsigned int pwm1_a_mux[] = { +- PWM1_A_MARK, +-}; +-static const unsigned int pwm1_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 8), +-}; +-static const unsigned int pwm1_b_mux[] = { +- PWM1_B_MARK, +-}; +-/* - PWM2 --------------------------------------------------------------------*/ +-static const unsigned int pwm2_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 8), +-}; +-static const unsigned int pwm2_a_mux[] = { +- PWM2_A_MARK, +-}; +-static const unsigned int pwm2_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int pwm2_b_mux[] = { +- PWM2_B_MARK, +-}; +-/* - PWM3 --------------------------------------------------------------------*/ +-static const unsigned int pwm3_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 0), +-}; +-static const unsigned int pwm3_a_mux[] = { +- PWM3_A_MARK, +-}; +-static const unsigned int pwm3_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 2), +-}; +-static const unsigned int pwm3_b_mux[] = { +- PWM3_B_MARK, +-}; +-/* - PWM4 --------------------------------------------------------------------*/ +-static const unsigned int pwm4_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 1), +-}; +-static const unsigned int pwm4_a_mux[] = { +- PWM4_A_MARK, +-}; +-static const unsigned int pwm4_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 3), +-}; +-static const unsigned int pwm4_b_mux[] = { +- PWM4_B_MARK, +-}; +-/* - PWM5 --------------------------------------------------------------------*/ +-static const unsigned int pwm5_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 2), +-}; +-static const unsigned int pwm5_a_mux[] = { +- PWM5_A_MARK, +-}; +-static const unsigned int pwm5_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 4), +-}; +-static const unsigned int pwm5_b_mux[] = { +- PWM5_B_MARK, +-}; +-/* - PWM6 --------------------------------------------------------------------*/ +-static const unsigned int pwm6_a_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(1, 3), +-}; +-static const unsigned int pwm6_a_mux[] = { +- PWM6_A_MARK, +-}; +-static const unsigned int pwm6_b_pins[] = { +- /* PWM */ +- RCAR_GP_PIN(2, 5), +-}; +-static const unsigned int pwm6_b_mux[] = { +- PWM6_B_MARK, +-}; +- +-/* - QSPI0 ------------------------------------------------------------------ */ +-static const unsigned int qspi0_ctrl_pins[] = { +- /* QSPI0_SPCLK, QSPI0_SSL */ +- PIN_NUMBER('W', 3), PIN_NUMBER('Y', 3), +-}; +-static const unsigned int qspi0_ctrl_mux[] = { +- QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +-}; +-static const unsigned int qspi0_data2_pins[] = { +- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ +- PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), +-}; +-static const unsigned int qspi0_data2_mux[] = { +- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +-}; +-static const unsigned int qspi0_data4_pins[] = { +- /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ +- PIN_A_NUMBER('C', 5), PIN_A_NUMBER('B', 4), +- PIN_NUMBER('Y', 6), PIN_A_NUMBER('B', 6), +-}; +-static const unsigned int qspi0_data4_mux[] = { +- QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +- QSPI0_IO2_MARK, QSPI0_IO3_MARK, +-}; +-/* - QSPI1 ------------------------------------------------------------------ */ +-static const unsigned int qspi1_ctrl_pins[] = { +- /* QSPI1_SPCLK, QSPI1_SSL */ +- PIN_NUMBER('V', 3), PIN_NUMBER('V', 5), +-}; +-static const unsigned int qspi1_ctrl_mux[] = { +- QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +-}; +-static const unsigned int qspi1_data2_pins[] = { +- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ +- PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), +-}; +-static const unsigned int qspi1_data2_mux[] = { +- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +-}; +-static const unsigned int qspi1_data4_pins[] = { +- /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ +- PIN_A_NUMBER('C', 7), PIN_A_NUMBER('E', 5), +- PIN_A_NUMBER('E', 4), PIN_A_NUMBER('C', 3), +-}; +-static const unsigned int qspi1_data4_mux[] = { +- QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +- QSPI1_IO2_MARK, QSPI1_IO3_MARK, +-}; +- +-/* - SATA --------------------------------------------------------------------*/ +-static const unsigned int sata0_devslp_a_pins[] = { +- /* DEVSLP */ +- RCAR_GP_PIN(6, 16), +-}; +-static const unsigned int sata0_devslp_a_mux[] = { +- SATA_DEVSLP_A_MARK, +-}; +-static const unsigned int sata0_devslp_b_pins[] = { +- /* DEVSLP */ +- RCAR_GP_PIN(4, 6), +-}; +-static const unsigned int sata0_devslp_b_mux[] = { +- SATA_DEVSLP_B_MARK, +-}; +- +-/* - SCIF0 ------------------------------------------------------------------ */ +-static const unsigned int scif0_data_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +-}; +-static const unsigned int scif0_data_mux[] = { +- RX0_MARK, TX0_MARK, +-}; +-static const unsigned int scif0_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 0), +-}; +-static const unsigned int scif0_clk_mux[] = { +- SCK0_MARK, +-}; +-static const unsigned int scif0_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +-}; +-static const unsigned int scif0_ctrl_mux[] = { +- RTS0_N_TANS_MARK, CTS0_N_MARK, +-}; +-/* - SCIF1 ------------------------------------------------------------------ */ +-static const unsigned int scif1_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +-}; +-static const unsigned int scif1_data_a_mux[] = { +- RX1_A_MARK, TX1_A_MARK, +-}; +-static const unsigned int scif1_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int scif1_clk_mux[] = { +- SCK1_MARK, +-}; +-static const unsigned int scif1_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +-}; +-static const unsigned int scif1_ctrl_mux[] = { +- RTS1_N_TANS_MARK, CTS1_N_MARK, +-}; +- +-static const unsigned int scif1_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +-}; +-static const unsigned int scif1_data_b_mux[] = { +- RX1_B_MARK, TX1_B_MARK, +-}; +-/* - SCIF2 ------------------------------------------------------------------ */ +-static const unsigned int scif2_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +-}; +-static const unsigned int scif2_data_a_mux[] = { +- RX2_A_MARK, TX2_A_MARK, +-}; +-static const unsigned int scif2_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(5, 9), +-}; +-static const unsigned int scif2_clk_mux[] = { +- SCK2_MARK, +-}; +-static const unsigned int scif2_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +-}; +-static const unsigned int scif2_data_b_mux[] = { +- RX2_B_MARK, TX2_B_MARK, +-}; +-/* - SCIF3 ------------------------------------------------------------------ */ +-static const unsigned int scif3_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +-}; +-static const unsigned int scif3_data_a_mux[] = { +- RX3_A_MARK, TX3_A_MARK, +-}; +-static const unsigned int scif3_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 22), +-}; +-static const unsigned int scif3_clk_mux[] = { +- SCK3_MARK, +-}; +-static const unsigned int scif3_ctrl_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +-}; +-static const unsigned int scif3_ctrl_mux[] = { +- RTS3_N_TANS_MARK, CTS3_N_MARK, +-}; +-static const unsigned int scif3_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +-}; +-static const unsigned int scif3_data_b_mux[] = { +- RX3_B_MARK, TX3_B_MARK, +-}; +-/* - SCIF4 ------------------------------------------------------------------ */ +-static const unsigned int scif4_data_a_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), +-}; +-static const unsigned int scif4_data_a_mux[] = { +- RX4_A_MARK, TX4_A_MARK, +-}; +-static const unsigned int scif4_clk_a_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(2, 10), +-}; +-static const unsigned int scif4_clk_a_mux[] = { +- SCK4_A_MARK, +-}; +-static const unsigned int scif4_ctrl_a_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), +-}; +-static const unsigned int scif4_ctrl_a_mux[] = { +- RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, +-}; +-static const unsigned int scif4_data_b_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +-}; +-static const unsigned int scif4_data_b_mux[] = { +- RX4_B_MARK, TX4_B_MARK, +-}; +-static const unsigned int scif4_clk_b_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(1, 5), +-}; +-static const unsigned int scif4_clk_b_mux[] = { +- SCK4_B_MARK, +-}; +-static const unsigned int scif4_ctrl_b_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), +-}; +-static const unsigned int scif4_ctrl_b_mux[] = { +- RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, +-}; +-static const unsigned int scif4_data_c_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +-}; +-static const unsigned int scif4_data_c_mux[] = { +- RX4_C_MARK, TX4_C_MARK, +-}; +-static const unsigned int scif4_clk_c_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(0, 8), +-}; +-static const unsigned int scif4_clk_c_mux[] = { +- SCK4_C_MARK, +-}; +-static const unsigned int scif4_ctrl_c_pins[] = { +- /* RTS, CTS */ +- RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), +-}; +-static const unsigned int scif4_ctrl_c_mux[] = { +- RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, +-}; +-/* - SCIF5 ------------------------------------------------------------------ */ +-static const unsigned int scif5_data_pins[] = { +- /* RX, TX */ +- RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int scif5_data_mux[] = { +- RX5_MARK, TX5_MARK, +-}; +-static const unsigned int scif5_clk_pins[] = { +- /* SCK */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int scif5_clk_mux[] = { +- SCK5_MARK, +-}; +- +-/* - SCIF Clock ------------------------------------------------------------- */ +-static const unsigned int scif_clk_a_pins[] = { +- /* SCIF_CLK */ +- RCAR_GP_PIN(6, 23), +-}; +-static const unsigned int scif_clk_a_mux[] = { +- SCIF_CLK_A_MARK, +-}; +-static const unsigned int scif_clk_b_pins[] = { +- /* SCIF_CLK */ +- RCAR_GP_PIN(5, 9), +-}; +-static const unsigned int scif_clk_b_mux[] = { +- SCIF_CLK_B_MARK, +-}; +- +-/* - SDHI0 ------------------------------------------------------------------ */ +-static const unsigned int sdhi0_data1_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(3, 2), +-}; +-static const unsigned int sdhi0_data1_mux[] = { +- SD0_DAT0_MARK, +-}; +-static const unsigned int sdhi0_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), +- RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +-}; +-static const unsigned int sdhi0_data4_mux[] = { +- SD0_DAT0_MARK, SD0_DAT1_MARK, +- SD0_DAT2_MARK, SD0_DAT3_MARK, +-}; +-static const unsigned int sdhi0_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +-}; +-static const unsigned int sdhi0_ctrl_mux[] = { +- SD0_CLK_MARK, SD0_CMD_MARK, +-}; +-static const unsigned int sdhi0_cd_pins[] = { +- /* CD */ +- RCAR_GP_PIN(3, 12), +-}; +-static const unsigned int sdhi0_cd_mux[] = { +- SD0_CD_MARK, +-}; +-static const unsigned int sdhi0_wp_pins[] = { +- /* WP */ +- RCAR_GP_PIN(3, 13), +-}; +-static const unsigned int sdhi0_wp_mux[] = { +- SD0_WP_MARK, +-}; +-/* - SDHI1 ------------------------------------------------------------------ */ +-static const unsigned int sdhi1_data1_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(3, 8), +-}; +-static const unsigned int sdhi1_data1_mux[] = { +- SD1_DAT0_MARK, +-}; +-static const unsigned int sdhi1_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +- RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +-}; +-static const unsigned int sdhi1_data4_mux[] = { +- SD1_DAT0_MARK, SD1_DAT1_MARK, +- SD1_DAT2_MARK, SD1_DAT3_MARK, +-}; +-static const unsigned int sdhi1_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +-}; +-static const unsigned int sdhi1_ctrl_mux[] = { +- SD1_CLK_MARK, SD1_CMD_MARK, +-}; +-static const unsigned int sdhi1_cd_pins[] = { +- /* CD */ +- RCAR_GP_PIN(3, 14), +-}; +-static const unsigned int sdhi1_cd_mux[] = { +- SD1_CD_MARK, +-}; +-static const unsigned int sdhi1_wp_pins[] = { +- /* WP */ +- RCAR_GP_PIN(3, 15), +-}; +-static const unsigned int sdhi1_wp_mux[] = { +- SD1_WP_MARK, +-}; +-/* - SDHI2 ------------------------------------------------------------------ */ +-static const unsigned int sdhi2_data1_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(4, 2), +-}; +-static const unsigned int sdhi2_data1_mux[] = { +- SD2_DAT0_MARK, +-}; +-static const unsigned int sdhi2_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +- RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +-}; +-static const unsigned int sdhi2_data4_mux[] = { +- SD2_DAT0_MARK, SD2_DAT1_MARK, +- SD2_DAT2_MARK, SD2_DAT3_MARK, +-}; +-static const unsigned int sdhi2_data8_pins[] = { +- /* D[0:7] */ +- RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), +- RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +- RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), +- RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +-}; +-static const unsigned int sdhi2_data8_mux[] = { +- SD2_DAT0_MARK, SD2_DAT1_MARK, +- SD2_DAT2_MARK, SD2_DAT3_MARK, +- SD2_DAT4_MARK, SD2_DAT5_MARK, +- SD2_DAT6_MARK, SD2_DAT7_MARK, +-}; +-static const unsigned int sdhi2_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +-}; +-static const unsigned int sdhi2_ctrl_mux[] = { +- SD2_CLK_MARK, SD2_CMD_MARK, +-}; +-static const unsigned int sdhi2_cd_a_pins[] = { +- /* CD */ +- RCAR_GP_PIN(4, 13), +-}; +-static const unsigned int sdhi2_cd_a_mux[] = { +- SD2_CD_A_MARK, +-}; +-static const unsigned int sdhi2_cd_b_pins[] = { +- /* CD */ +- RCAR_GP_PIN(5, 10), +-}; +-static const unsigned int sdhi2_cd_b_mux[] = { +- SD2_CD_B_MARK, +-}; +-static const unsigned int sdhi2_wp_a_pins[] = { +- /* WP */ +- RCAR_GP_PIN(4, 14), +-}; +-static const unsigned int sdhi2_wp_a_mux[] = { +- SD2_WP_A_MARK, +-}; +-static const unsigned int sdhi2_wp_b_pins[] = { +- /* WP */ +- RCAR_GP_PIN(5, 11), +-}; +-static const unsigned int sdhi2_wp_b_mux[] = { +- SD2_WP_B_MARK, +-}; +-static const unsigned int sdhi2_ds_pins[] = { +- /* DS */ +- RCAR_GP_PIN(4, 6), +-}; +-static const unsigned int sdhi2_ds_mux[] = { +- SD2_DS_MARK, +-}; +-/* - SDHI3 ------------------------------------------------------------------ */ +-static const unsigned int sdhi3_data1_pins[] = { +- /* D0 */ +- RCAR_GP_PIN(4, 9), +-}; +-static const unsigned int sdhi3_data1_mux[] = { +- SD3_DAT0_MARK, +-}; +-static const unsigned int sdhi3_data4_pins[] = { +- /* D[0:3] */ +- RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), +- RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +-}; +-static const unsigned int sdhi3_data4_mux[] = { +- SD3_DAT0_MARK, SD3_DAT1_MARK, +- SD3_DAT2_MARK, SD3_DAT3_MARK, +-}; +-static const unsigned int sdhi3_data8_pins[] = { +- /* D[0:7] */ +- RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), +- RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +- RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), +- RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +-}; +-static const unsigned int sdhi3_data8_mux[] = { +- SD3_DAT0_MARK, SD3_DAT1_MARK, +- SD3_DAT2_MARK, SD3_DAT3_MARK, +- SD3_DAT4_MARK, SD3_DAT5_MARK, +- SD3_DAT6_MARK, SD3_DAT7_MARK, +-}; +-static const unsigned int sdhi3_ctrl_pins[] = { +- /* CLK, CMD */ +- RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +-}; +-static const unsigned int sdhi3_ctrl_mux[] = { +- SD3_CLK_MARK, SD3_CMD_MARK, +-}; +-static const unsigned int sdhi3_cd_pins[] = { +- /* CD */ +- RCAR_GP_PIN(4, 15), +-}; +-static const unsigned int sdhi3_cd_mux[] = { +- SD3_CD_MARK, +-}; +-static const unsigned int sdhi3_wp_pins[] = { +- /* WP */ +- RCAR_GP_PIN(4, 16), +-}; +-static const unsigned int sdhi3_wp_mux[] = { +- SD3_WP_MARK, +-}; +-static const unsigned int sdhi3_ds_pins[] = { +- /* DS */ +- RCAR_GP_PIN(4, 17), +-}; +-static const unsigned int sdhi3_ds_mux[] = { +- SD3_DS_MARK, +-}; +- +-/* - SSI -------------------------------------------------------------------- */ +-static const unsigned int ssi0_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 2), +-}; +-static const unsigned int ssi0_data_mux[] = { +- SSI_SDATA0_MARK, +-}; +-static const unsigned int ssi01239_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +-}; +-static const unsigned int ssi01239_ctrl_mux[] = { +- SSI_SCK01239_MARK, SSI_WS01239_MARK, +-}; +-static const unsigned int ssi1_data_a_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 3), +-}; +-static const unsigned int ssi1_data_a_mux[] = { +- SSI_SDATA1_A_MARK, +-}; +-static const unsigned int ssi1_data_b_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(5, 12), +-}; +-static const unsigned int ssi1_data_b_mux[] = { +- SSI_SDATA1_B_MARK, +-}; +-static const unsigned int ssi1_ctrl_a_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +-}; +-static const unsigned int ssi1_ctrl_a_mux[] = { +- SSI_SCK1_A_MARK, SSI_WS1_A_MARK, +-}; +-static const unsigned int ssi1_ctrl_b_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int ssi1_ctrl_b_mux[] = { +- SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +-}; +-static const unsigned int ssi2_data_a_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 4), +-}; +-static const unsigned int ssi2_data_a_mux[] = { +- SSI_SDATA2_A_MARK, +-}; +-static const unsigned int ssi2_data_b_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(5, 13), +-}; +-static const unsigned int ssi2_data_b_mux[] = { +- SSI_SDATA2_B_MARK, +-}; +-static const unsigned int ssi2_ctrl_a_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +-}; +-static const unsigned int ssi2_ctrl_a_mux[] = { +- SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +-}; +-static const unsigned int ssi2_ctrl_b_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +-}; +-static const unsigned int ssi2_ctrl_b_mux[] = { +- SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +-}; +-static const unsigned int ssi3_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 7), +-}; +-static const unsigned int ssi3_data_mux[] = { +- SSI_SDATA3_MARK, +-}; +-static const unsigned int ssi34_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +-}; +-static const unsigned int ssi34_ctrl_mux[] = { +- SSI_SCK34_MARK, SSI_WS34_MARK, +-}; +-static const unsigned int ssi4_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 10), +-}; +-static const unsigned int ssi4_data_mux[] = { +- SSI_SDATA4_MARK, +-}; +-static const unsigned int ssi4_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +-}; +-static const unsigned int ssi4_ctrl_mux[] = { +- SSI_SCK4_MARK, SSI_WS4_MARK, +-}; +-static const unsigned int ssi5_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 13), +-}; +-static const unsigned int ssi5_data_mux[] = { +- SSI_SDATA5_MARK, +-}; +-static const unsigned int ssi5_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +-}; +-static const unsigned int ssi5_ctrl_mux[] = { +- SSI_SCK5_MARK, SSI_WS5_MARK, +-}; +-static const unsigned int ssi6_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 16), +-}; +-static const unsigned int ssi6_data_mux[] = { +- SSI_SDATA6_MARK, +-}; +-static const unsigned int ssi6_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +-}; +-static const unsigned int ssi6_ctrl_mux[] = { +- SSI_SCK6_MARK, SSI_WS6_MARK, +-}; +-static const unsigned int ssi7_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 19), +-}; +-static const unsigned int ssi7_data_mux[] = { +- SSI_SDATA7_MARK, +-}; +-static const unsigned int ssi78_ctrl_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +-}; +-static const unsigned int ssi78_ctrl_mux[] = { +- SSI_SCK78_MARK, SSI_WS78_MARK, +-}; +-static const unsigned int ssi8_data_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 20), +-}; +-static const unsigned int ssi8_data_mux[] = { +- SSI_SDATA8_MARK, +-}; +-static const unsigned int ssi9_data_a_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(6, 21), +-}; +-static const unsigned int ssi9_data_a_mux[] = { +- SSI_SDATA9_A_MARK, +-}; +-static const unsigned int ssi9_data_b_pins[] = { +- /* SDATA */ +- RCAR_GP_PIN(5, 14), +-}; +-static const unsigned int ssi9_data_b_mux[] = { +- SSI_SDATA9_B_MARK, +-}; +-static const unsigned int ssi9_ctrl_a_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +-}; +-static const unsigned int ssi9_ctrl_a_mux[] = { +- SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +-}; +-static const unsigned int ssi9_ctrl_b_pins[] = { +- /* SCK, WS */ +- RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +-}; +-static const unsigned int ssi9_ctrl_b_mux[] = { +- SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +-}; +- +-/* - USB0 ------------------------------------------------------------------- */ +-static const unsigned int usb0_pins[] = { +- /* PWEN, OVC */ +- RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +-}; +-static const unsigned int usb0_mux[] = { +- USB0_PWEN_MARK, USB0_OVC_MARK, +-}; +-/* - USB1 ------------------------------------------------------------------- */ +-static const unsigned int usb1_pins[] = { +- /* PWEN, OVC */ +- RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +-}; +-static const unsigned int usb1_mux[] = { +- USB1_PWEN_MARK, USB1_OVC_MARK, +-}; +-/* - USB2 ------------------------------------------------------------------- */ +-static const unsigned int usb2_pins[] = { +- /* PWEN, OVC */ +- RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +-}; +-static const unsigned int usb2_mux[] = { +- USB2_PWEN_MARK, USB2_OVC_MARK, +-}; +- +-static const struct sh_pfc_pin_group pinmux_groups[] = { +- SH_PFC_PIN_GROUP(audio_clk_a_a), +- SH_PFC_PIN_GROUP(audio_clk_a_b), +- SH_PFC_PIN_GROUP(audio_clk_a_c), +- SH_PFC_PIN_GROUP(audio_clk_b_a), +- SH_PFC_PIN_GROUP(audio_clk_b_b), +- SH_PFC_PIN_GROUP(audio_clk_c_a), +- SH_PFC_PIN_GROUP(audio_clk_c_b), +- SH_PFC_PIN_GROUP(audio_clkout_a), +- SH_PFC_PIN_GROUP(audio_clkout_b), +- SH_PFC_PIN_GROUP(audio_clkout_c), +- SH_PFC_PIN_GROUP(audio_clkout_d), +- SH_PFC_PIN_GROUP(audio_clkout1_a), +- SH_PFC_PIN_GROUP(audio_clkout1_b), +- SH_PFC_PIN_GROUP(audio_clkout2_a), +- SH_PFC_PIN_GROUP(audio_clkout2_b), +- SH_PFC_PIN_GROUP(audio_clkout3_a), +- SH_PFC_PIN_GROUP(audio_clkout3_b), +- SH_PFC_PIN_GROUP(avb_link), +- SH_PFC_PIN_GROUP(avb_magic), +- SH_PFC_PIN_GROUP(avb_phy_int), +- SH_PFC_PIN_GROUP(avb_mdc), +- SH_PFC_PIN_GROUP(avb_mii), +- SH_PFC_PIN_GROUP(avb_avtp_pps), +- SH_PFC_PIN_GROUP(avb_avtp_match_a), +- SH_PFC_PIN_GROUP(avb_avtp_capture_a), +- SH_PFC_PIN_GROUP(avb_avtp_match_b), +- SH_PFC_PIN_GROUP(avb_avtp_capture_b), +- SH_PFC_PIN_GROUP(can0_data_a), +- SH_PFC_PIN_GROUP(can0_data_b), +- SH_PFC_PIN_GROUP(can1_data), +- SH_PFC_PIN_GROUP(can_clk), +- SH_PFC_PIN_GROUP(canfd0_data_a), +- SH_PFC_PIN_GROUP(canfd0_data_b), +- SH_PFC_PIN_GROUP(canfd1_data), +- SH_PFC_PIN_GROUP(drif0_ctrl_a), +- SH_PFC_PIN_GROUP(drif0_data0_a), +- SH_PFC_PIN_GROUP(drif0_data1_a), +- SH_PFC_PIN_GROUP(drif0_ctrl_b), +- SH_PFC_PIN_GROUP(drif0_data0_b), +- SH_PFC_PIN_GROUP(drif0_data1_b), +- SH_PFC_PIN_GROUP(drif0_ctrl_c), +- SH_PFC_PIN_GROUP(drif0_data0_c), +- SH_PFC_PIN_GROUP(drif0_data1_c), +- SH_PFC_PIN_GROUP(drif1_ctrl_a), +- SH_PFC_PIN_GROUP(drif1_data0_a), +- SH_PFC_PIN_GROUP(drif1_data1_a), +- SH_PFC_PIN_GROUP(drif1_ctrl_b), +- SH_PFC_PIN_GROUP(drif1_data0_b), +- SH_PFC_PIN_GROUP(drif1_data1_b), +- SH_PFC_PIN_GROUP(drif1_ctrl_c), +- SH_PFC_PIN_GROUP(drif1_data0_c), +- SH_PFC_PIN_GROUP(drif1_data1_c), +- SH_PFC_PIN_GROUP(drif2_ctrl_a), +- SH_PFC_PIN_GROUP(drif2_data0_a), +- SH_PFC_PIN_GROUP(drif2_data1_a), +- SH_PFC_PIN_GROUP(drif2_ctrl_b), +- SH_PFC_PIN_GROUP(drif2_data0_b), +- SH_PFC_PIN_GROUP(drif2_data1_b), +- SH_PFC_PIN_GROUP(drif3_ctrl_a), +- SH_PFC_PIN_GROUP(drif3_data0_a), +- SH_PFC_PIN_GROUP(drif3_data1_a), +- SH_PFC_PIN_GROUP(drif3_ctrl_b), +- SH_PFC_PIN_GROUP(drif3_data0_b), +- SH_PFC_PIN_GROUP(drif3_data1_b), +- SH_PFC_PIN_GROUP(du_rgb666), +- SH_PFC_PIN_GROUP(du_rgb888), +- SH_PFC_PIN_GROUP(du_clk_out_0), +- SH_PFC_PIN_GROUP(du_clk_out_1), +- SH_PFC_PIN_GROUP(du_sync), +- SH_PFC_PIN_GROUP(du_oddf), +- SH_PFC_PIN_GROUP(du_cde), +- SH_PFC_PIN_GROUP(du_disp), +- SH_PFC_PIN_GROUP(hscif0_data), +- SH_PFC_PIN_GROUP(hscif0_clk), +- SH_PFC_PIN_GROUP(hscif0_ctrl), +- SH_PFC_PIN_GROUP(hscif1_data_a), +- SH_PFC_PIN_GROUP(hscif1_clk_a), +- SH_PFC_PIN_GROUP(hscif1_ctrl_a), +- SH_PFC_PIN_GROUP(hscif1_data_b), +- SH_PFC_PIN_GROUP(hscif1_clk_b), +- SH_PFC_PIN_GROUP(hscif1_ctrl_b), +- SH_PFC_PIN_GROUP(hscif2_data_a), +- SH_PFC_PIN_GROUP(hscif2_clk_a), +- SH_PFC_PIN_GROUP(hscif2_ctrl_a), +- SH_PFC_PIN_GROUP(hscif2_data_b), +- SH_PFC_PIN_GROUP(hscif2_clk_b), +- SH_PFC_PIN_GROUP(hscif2_ctrl_b), +- SH_PFC_PIN_GROUP(hscif3_data_a), +- SH_PFC_PIN_GROUP(hscif3_clk), +- SH_PFC_PIN_GROUP(hscif3_ctrl), +- SH_PFC_PIN_GROUP(hscif3_data_b), +- SH_PFC_PIN_GROUP(hscif3_data_c), +- SH_PFC_PIN_GROUP(hscif3_data_d), +- SH_PFC_PIN_GROUP(hscif4_data_a), +- SH_PFC_PIN_GROUP(hscif4_clk), +- SH_PFC_PIN_GROUP(hscif4_ctrl), +- SH_PFC_PIN_GROUP(hscif4_data_b), +- SH_PFC_PIN_GROUP(i2c1_a), +- SH_PFC_PIN_GROUP(i2c1_b), +- SH_PFC_PIN_GROUP(i2c2_a), +- SH_PFC_PIN_GROUP(i2c2_b), +- SH_PFC_PIN_GROUP(i2c6_a), +- SH_PFC_PIN_GROUP(i2c6_b), +- SH_PFC_PIN_GROUP(i2c6_c), +- SH_PFC_PIN_GROUP(intc_ex_irq0), +- SH_PFC_PIN_GROUP(intc_ex_irq1), +- SH_PFC_PIN_GROUP(intc_ex_irq2), +- SH_PFC_PIN_GROUP(intc_ex_irq3), +- SH_PFC_PIN_GROUP(intc_ex_irq4), +- SH_PFC_PIN_GROUP(intc_ex_irq5), +- SH_PFC_PIN_GROUP(msiof0_clk), +- SH_PFC_PIN_GROUP(msiof0_sync), +- SH_PFC_PIN_GROUP(msiof0_ss1), +- SH_PFC_PIN_GROUP(msiof0_ss2), +- SH_PFC_PIN_GROUP(msiof0_txd), +- SH_PFC_PIN_GROUP(msiof0_rxd), +- SH_PFC_PIN_GROUP(msiof1_clk_a), +- SH_PFC_PIN_GROUP(msiof1_sync_a), +- SH_PFC_PIN_GROUP(msiof1_ss1_a), +- SH_PFC_PIN_GROUP(msiof1_ss2_a), +- SH_PFC_PIN_GROUP(msiof1_txd_a), +- SH_PFC_PIN_GROUP(msiof1_rxd_a), +- SH_PFC_PIN_GROUP(msiof1_clk_b), +- SH_PFC_PIN_GROUP(msiof1_sync_b), +- SH_PFC_PIN_GROUP(msiof1_ss1_b), +- SH_PFC_PIN_GROUP(msiof1_ss2_b), +- SH_PFC_PIN_GROUP(msiof1_txd_b), +- SH_PFC_PIN_GROUP(msiof1_rxd_b), +- SH_PFC_PIN_GROUP(msiof1_clk_c), +- SH_PFC_PIN_GROUP(msiof1_sync_c), +- SH_PFC_PIN_GROUP(msiof1_ss1_c), +- SH_PFC_PIN_GROUP(msiof1_ss2_c), +- SH_PFC_PIN_GROUP(msiof1_txd_c), +- SH_PFC_PIN_GROUP(msiof1_rxd_c), +- SH_PFC_PIN_GROUP(msiof1_clk_d), +- SH_PFC_PIN_GROUP(msiof1_sync_d), +- SH_PFC_PIN_GROUP(msiof1_ss1_d), +- SH_PFC_PIN_GROUP(msiof1_ss2_d), +- SH_PFC_PIN_GROUP(msiof1_txd_d), +- SH_PFC_PIN_GROUP(msiof1_rxd_d), +- SH_PFC_PIN_GROUP(msiof1_clk_e), +- SH_PFC_PIN_GROUP(msiof1_sync_e), +- SH_PFC_PIN_GROUP(msiof1_ss1_e), +- SH_PFC_PIN_GROUP(msiof1_ss2_e), +- SH_PFC_PIN_GROUP(msiof1_txd_e), +- SH_PFC_PIN_GROUP(msiof1_rxd_e), +- SH_PFC_PIN_GROUP(msiof1_clk_f), +- SH_PFC_PIN_GROUP(msiof1_sync_f), +- SH_PFC_PIN_GROUP(msiof1_ss1_f), +- SH_PFC_PIN_GROUP(msiof1_ss2_f), +- SH_PFC_PIN_GROUP(msiof1_txd_f), +- SH_PFC_PIN_GROUP(msiof1_rxd_f), +- SH_PFC_PIN_GROUP(msiof1_clk_g), +- SH_PFC_PIN_GROUP(msiof1_sync_g), +- SH_PFC_PIN_GROUP(msiof1_ss1_g), +- SH_PFC_PIN_GROUP(msiof1_ss2_g), +- SH_PFC_PIN_GROUP(msiof1_txd_g), +- SH_PFC_PIN_GROUP(msiof1_rxd_g), +- SH_PFC_PIN_GROUP(msiof2_clk_a), +- SH_PFC_PIN_GROUP(msiof2_sync_a), +- SH_PFC_PIN_GROUP(msiof2_ss1_a), +- SH_PFC_PIN_GROUP(msiof2_ss2_a), +- SH_PFC_PIN_GROUP(msiof2_txd_a), +- SH_PFC_PIN_GROUP(msiof2_rxd_a), +- SH_PFC_PIN_GROUP(msiof2_clk_b), +- SH_PFC_PIN_GROUP(msiof2_sync_b), +- SH_PFC_PIN_GROUP(msiof2_ss1_b), +- SH_PFC_PIN_GROUP(msiof2_ss2_b), +- SH_PFC_PIN_GROUP(msiof2_txd_b), +- SH_PFC_PIN_GROUP(msiof2_rxd_b), +- SH_PFC_PIN_GROUP(msiof2_clk_c), +- SH_PFC_PIN_GROUP(msiof2_sync_c), +- SH_PFC_PIN_GROUP(msiof2_ss1_c), +- SH_PFC_PIN_GROUP(msiof2_ss2_c), +- SH_PFC_PIN_GROUP(msiof2_txd_c), +- SH_PFC_PIN_GROUP(msiof2_rxd_c), +- SH_PFC_PIN_GROUP(msiof2_clk_d), +- SH_PFC_PIN_GROUP(msiof2_sync_d), +- SH_PFC_PIN_GROUP(msiof2_ss1_d), +- SH_PFC_PIN_GROUP(msiof2_ss2_d), +- SH_PFC_PIN_GROUP(msiof2_txd_d), +- SH_PFC_PIN_GROUP(msiof2_rxd_d), +- SH_PFC_PIN_GROUP(msiof3_clk_a), +- SH_PFC_PIN_GROUP(msiof3_sync_a), +- SH_PFC_PIN_GROUP(msiof3_ss1_a), +- SH_PFC_PIN_GROUP(msiof3_ss2_a), +- SH_PFC_PIN_GROUP(msiof3_txd_a), +- SH_PFC_PIN_GROUP(msiof3_rxd_a), +- SH_PFC_PIN_GROUP(msiof3_clk_b), +- SH_PFC_PIN_GROUP(msiof3_sync_b), +- SH_PFC_PIN_GROUP(msiof3_ss1_b), +- SH_PFC_PIN_GROUP(msiof3_ss2_b), +- SH_PFC_PIN_GROUP(msiof3_txd_b), +- SH_PFC_PIN_GROUP(msiof3_rxd_b), +- SH_PFC_PIN_GROUP(msiof3_clk_c), +- SH_PFC_PIN_GROUP(msiof3_sync_c), +- SH_PFC_PIN_GROUP(msiof3_txd_c), +- SH_PFC_PIN_GROUP(msiof3_rxd_c), +- SH_PFC_PIN_GROUP(msiof3_clk_d), +- SH_PFC_PIN_GROUP(msiof3_sync_d), +- SH_PFC_PIN_GROUP(msiof3_ss1_d), +- SH_PFC_PIN_GROUP(msiof3_txd_d), +- SH_PFC_PIN_GROUP(msiof3_rxd_d), +- SH_PFC_PIN_GROUP(pwm0), +- SH_PFC_PIN_GROUP(pwm1_a), +- SH_PFC_PIN_GROUP(pwm1_b), +- SH_PFC_PIN_GROUP(pwm2_a), +- SH_PFC_PIN_GROUP(pwm2_b), +- SH_PFC_PIN_GROUP(pwm3_a), +- SH_PFC_PIN_GROUP(pwm3_b), +- SH_PFC_PIN_GROUP(pwm4_a), +- SH_PFC_PIN_GROUP(pwm4_b), +- SH_PFC_PIN_GROUP(pwm5_a), +- SH_PFC_PIN_GROUP(pwm5_b), +- SH_PFC_PIN_GROUP(pwm6_a), +- SH_PFC_PIN_GROUP(pwm6_b), +- SH_PFC_PIN_GROUP(qspi0_ctrl), +- SH_PFC_PIN_GROUP(qspi0_data2), +- SH_PFC_PIN_GROUP(qspi0_data4), +- SH_PFC_PIN_GROUP(qspi1_ctrl), +- SH_PFC_PIN_GROUP(qspi1_data2), +- SH_PFC_PIN_GROUP(qspi1_data4), +- SH_PFC_PIN_GROUP(sata0_devslp_a), +- SH_PFC_PIN_GROUP(sata0_devslp_b), +- SH_PFC_PIN_GROUP(scif0_data), +- SH_PFC_PIN_GROUP(scif0_clk), +- SH_PFC_PIN_GROUP(scif0_ctrl), +- SH_PFC_PIN_GROUP(scif1_data_a), +- SH_PFC_PIN_GROUP(scif1_clk), +- SH_PFC_PIN_GROUP(scif1_ctrl), +- SH_PFC_PIN_GROUP(scif1_data_b), +- SH_PFC_PIN_GROUP(scif2_data_a), +- SH_PFC_PIN_GROUP(scif2_clk), +- SH_PFC_PIN_GROUP(scif2_data_b), +- SH_PFC_PIN_GROUP(scif3_data_a), +- SH_PFC_PIN_GROUP(scif3_clk), +- SH_PFC_PIN_GROUP(scif3_ctrl), +- SH_PFC_PIN_GROUP(scif3_data_b), +- SH_PFC_PIN_GROUP(scif4_data_a), +- SH_PFC_PIN_GROUP(scif4_clk_a), +- SH_PFC_PIN_GROUP(scif4_ctrl_a), +- SH_PFC_PIN_GROUP(scif4_data_b), +- SH_PFC_PIN_GROUP(scif4_clk_b), +- SH_PFC_PIN_GROUP(scif4_ctrl_b), +- SH_PFC_PIN_GROUP(scif4_data_c), +- SH_PFC_PIN_GROUP(scif4_clk_c), +- SH_PFC_PIN_GROUP(scif4_ctrl_c), +- SH_PFC_PIN_GROUP(scif5_data), +- SH_PFC_PIN_GROUP(scif5_clk), +- SH_PFC_PIN_GROUP(scif_clk_a), +- SH_PFC_PIN_GROUP(scif_clk_b), +- SH_PFC_PIN_GROUP(sdhi0_data1), +- SH_PFC_PIN_GROUP(sdhi0_data4), +- SH_PFC_PIN_GROUP(sdhi0_ctrl), +- SH_PFC_PIN_GROUP(sdhi0_cd), +- SH_PFC_PIN_GROUP(sdhi0_wp), +- SH_PFC_PIN_GROUP(sdhi1_data1), +- SH_PFC_PIN_GROUP(sdhi1_data4), +- SH_PFC_PIN_GROUP(sdhi1_ctrl), +- SH_PFC_PIN_GROUP(sdhi1_cd), +- SH_PFC_PIN_GROUP(sdhi1_wp), +- SH_PFC_PIN_GROUP(sdhi2_data1), +- SH_PFC_PIN_GROUP(sdhi2_data4), +- SH_PFC_PIN_GROUP(sdhi2_data8), +- SH_PFC_PIN_GROUP(sdhi2_ctrl), +- SH_PFC_PIN_GROUP(sdhi2_cd_a), +- SH_PFC_PIN_GROUP(sdhi2_wp_a), +- SH_PFC_PIN_GROUP(sdhi2_cd_b), +- SH_PFC_PIN_GROUP(sdhi2_wp_b), +- SH_PFC_PIN_GROUP(sdhi2_ds), +- SH_PFC_PIN_GROUP(sdhi3_data1), +- SH_PFC_PIN_GROUP(sdhi3_data4), +- SH_PFC_PIN_GROUP(sdhi3_data8), +- SH_PFC_PIN_GROUP(sdhi3_ctrl), +- SH_PFC_PIN_GROUP(sdhi3_cd), +- SH_PFC_PIN_GROUP(sdhi3_wp), +- SH_PFC_PIN_GROUP(sdhi3_ds), +- SH_PFC_PIN_GROUP(ssi0_data), +- SH_PFC_PIN_GROUP(ssi01239_ctrl), +- SH_PFC_PIN_GROUP(ssi1_data_a), +- SH_PFC_PIN_GROUP(ssi1_data_b), +- SH_PFC_PIN_GROUP(ssi1_ctrl_a), +- SH_PFC_PIN_GROUP(ssi1_ctrl_b), +- SH_PFC_PIN_GROUP(ssi2_data_a), +- SH_PFC_PIN_GROUP(ssi2_data_b), +- SH_PFC_PIN_GROUP(ssi2_ctrl_a), +- SH_PFC_PIN_GROUP(ssi2_ctrl_b), +- SH_PFC_PIN_GROUP(ssi3_data), +- SH_PFC_PIN_GROUP(ssi34_ctrl), +- SH_PFC_PIN_GROUP(ssi4_data), +- SH_PFC_PIN_GROUP(ssi4_ctrl), +- SH_PFC_PIN_GROUP(ssi5_data), +- SH_PFC_PIN_GROUP(ssi5_ctrl), +- SH_PFC_PIN_GROUP(ssi6_data), +- SH_PFC_PIN_GROUP(ssi6_ctrl), +- SH_PFC_PIN_GROUP(ssi7_data), +- SH_PFC_PIN_GROUP(ssi78_ctrl), +- SH_PFC_PIN_GROUP(ssi8_data), +- SH_PFC_PIN_GROUP(ssi9_data_a), +- SH_PFC_PIN_GROUP(ssi9_data_b), +- SH_PFC_PIN_GROUP(ssi9_ctrl_a), +- SH_PFC_PIN_GROUP(ssi9_ctrl_b), +- SH_PFC_PIN_GROUP(usb0), +- SH_PFC_PIN_GROUP(usb1), +- SH_PFC_PIN_GROUP(usb2), +-}; +- +-static const char * const audio_clk_groups[] = { +- "audio_clk_a_a", +- "audio_clk_a_b", +- "audio_clk_a_c", +- "audio_clk_b_a", +- "audio_clk_b_b", +- "audio_clk_c_a", +- "audio_clk_c_b", +- "audio_clkout_a", +- "audio_clkout_b", +- "audio_clkout_c", +- "audio_clkout_d", +- "audio_clkout1_a", +- "audio_clkout1_b", +- "audio_clkout2_a", +- "audio_clkout2_b", +- "audio_clkout3_a", +- "audio_clkout3_b", +-}; ++ PINMUX_IPSR_GPSR(IP6_7_4, D6), ++ PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22), ++ PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6), + +-static const char * const avb_groups[] = { +- "avb_link", +- "avb_magic", +- "avb_phy_int", +- "avb_mdc", +- "avb_mii", +- "avb_avtp_pps", +- "avb_avtp_match_a", +- "avb_avtp_capture_a", +- "avb_avtp_match_b", +- "avb_avtp_capture_b", +-}; ++ PINMUX_IPSR_GPSR(IP6_11_8, D7), ++ PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1), ++ PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23), ++ PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7), + +-static const char * const can0_groups[] = { +- "can0_data_a", +- "can0_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP6_15_12, D8), ++ PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0), ++ PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0), + +-static const char * const can1_groups[] = { +- "can1_data", +-}; ++ PINMUX_IPSR_GPSR(IP6_19_16, D9), ++ PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1), ++ PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1), + +-static const char * const can_clk_groups[] = { +- "can_clk", +-}; ++ PINMUX_IPSR_GPSR(IP6_23_20, D10), ++ PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2), ++ PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1), ++ PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0), ++ PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2), ++ PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2), + +-static const char * const canfd0_groups[] = { +- "canfd0_data_a", +- "canfd0_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP6_27_24, D11), ++ PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3), ++ PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1), ++ PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0), ++ PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), ++ PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3), + +-static const char * const canfd1_groups[] = { +- "canfd1_data", +-}; ++ PINMUX_IPSR_GPSR(IP6_31_28, D12), ++ PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4), ++ PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4), + +-static const char * const drif0_groups[] = { +- "drif0_ctrl_a", +- "drif0_data0_a", +- "drif0_data1_a", +- "drif0_ctrl_b", +- "drif0_data0_b", +- "drif0_data1_b", +- "drif0_ctrl_c", +- "drif0_data0_c", +- "drif0_data1_c", +-}; ++ /* IPSR7 */ ++ PINMUX_IPSR_GPSR(IP7_3_0, D13), ++ PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5), ++ PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3), ++ PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2), ++ PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5), + +-static const char * const drif1_groups[] = { +- "drif1_ctrl_a", +- "drif1_data0_a", +- "drif1_data1_a", +- "drif1_ctrl_b", +- "drif1_data0_b", +- "drif1_data1_b", +- "drif1_ctrl_c", +- "drif1_data0_c", +- "drif1_data1_c", +-}; ++ PINMUX_IPSR_GPSR(IP7_7_4, D14), ++ PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6), ++ PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2), ++ PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6), ++ PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2), + +-static const char * const drif2_groups[] = { +- "drif2_ctrl_a", +- "drif2_data0_a", +- "drif2_data1_a", +- "drif2_ctrl_b", +- "drif2_data0_b", +- "drif2_data1_b", +-}; ++ PINMUX_IPSR_GPSR(IP7_11_8, D15), ++ PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7), ++ PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0), ++ PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2), ++ PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0), ++ PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), ++ PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), + +-static const char * const drif3_groups[] = { +- "drif3_ctrl_a", +- "drif3_data0_a", +- "drif3_data1_a", +- "drif3_ctrl_b", +- "drif3_data0_b", +- "drif3_data1_b", +-}; ++ PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST), + +-static const char * const du_groups[] = { +- "du_rgb666", +- "du_rgb888", +- "du_clk_out_0", +- "du_clk_out_1", +- "du_sync", +- "du_oddf", +- "du_cde", +- "du_disp", +-}; ++ PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), ++ PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), + +-static const char * const hscif0_groups[] = { +- "hscif0_data", +- "hscif0_clk", +- "hscif0_ctrl", +-}; ++ PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD), ++ PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1), + +-static const char * const hscif1_groups[] = { +- "hscif1_data_a", +- "hscif1_clk_a", +- "hscif1_ctrl_a", +- "hscif1_data_b", +- "hscif1_clk_b", +- "hscif1_ctrl_b", +-}; ++ PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0), ++ PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1), + +-static const char * const hscif2_groups[] = { +- "hscif2_data_a", +- "hscif2_clk_a", +- "hscif2_ctrl_a", +- "hscif2_data_b", +- "hscif2_clk_b", +- "hscif2_ctrl_b", +-}; ++ PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1), ++ PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1), + +-static const char * const hscif3_groups[] = { +- "hscif3_data_a", +- "hscif3_clk", +- "hscif3_ctrl", +- "hscif3_data_b", +- "hscif3_data_c", +- "hscif3_data_d", +-}; ++ /* IPSR8 */ ++ PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2), ++ PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1), + +-static const char * const hscif4_groups[] = { +- "hscif4_data_a", +- "hscif4_clk", +- "hscif4_ctrl", +- "hscif4_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3), ++ PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4), ++ PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1), ++ PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1), + +-static const char * const i2c1_groups[] = { +- "i2c1_a", +- "i2c1_b", +-}; ++ PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK), ++ PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0), + +-static const char * const i2c2_groups[] = { +- "i2c2_a", +- "i2c2_b", +-}; ++ PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), ++ PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), ++ PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), ++ PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), + +-static const char * const i2c6_groups[] = { +- "i2c6_a", +- "i2c6_b", +- "i2c6_c", +-}; ++ PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), ++ PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), ++ PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), ++ PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), + +-static const char * const intc_ex_groups[] = { +- "intc_ex_irq0", +- "intc_ex_irq1", +- "intc_ex_irq2", +- "intc_ex_irq3", +- "intc_ex_irq4", +- "intc_ex_irq5", +-}; ++ PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), ++ PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), ++ PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), ++ PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), + +-static const char * const msiof0_groups[] = { +- "msiof0_clk", +- "msiof0_sync", +- "msiof0_ss1", +- "msiof0_ss2", +- "msiof0_txd", +- "msiof0_rxd", +-}; ++ PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), ++ PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), ++ PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), ++ PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), + +-static const char * const msiof1_groups[] = { +- "msiof1_clk_a", +- "msiof1_sync_a", +- "msiof1_ss1_a", +- "msiof1_ss2_a", +- "msiof1_txd_a", +- "msiof1_rxd_a", +- "msiof1_clk_b", +- "msiof1_sync_b", +- "msiof1_ss1_b", +- "msiof1_ss2_b", +- "msiof1_txd_b", +- "msiof1_rxd_b", +- "msiof1_clk_c", +- "msiof1_sync_c", +- "msiof1_ss1_c", +- "msiof1_ss2_c", +- "msiof1_txd_c", +- "msiof1_rxd_c", +- "msiof1_clk_d", +- "msiof1_sync_d", +- "msiof1_ss1_d", +- "msiof1_ss2_d", +- "msiof1_txd_d", +- "msiof1_rxd_d", +- "msiof1_clk_e", +- "msiof1_sync_e", +- "msiof1_ss1_e", +- "msiof1_ss2_e", +- "msiof1_txd_e", +- "msiof1_rxd_e", +- "msiof1_clk_f", +- "msiof1_sync_f", +- "msiof1_ss1_f", +- "msiof1_ss2_f", +- "msiof1_txd_f", +- "msiof1_rxd_f", +- "msiof1_clk_g", +- "msiof1_sync_g", +- "msiof1_ss1_g", +- "msiof1_ss2_g", +- "msiof1_txd_g", +- "msiof1_rxd_g", +-}; ++ PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), ++ PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), ++ PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), ++ PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), ++ PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), ++ PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), + +-static const char * const msiof2_groups[] = { +- "msiof2_clk_a", +- "msiof2_sync_a", +- "msiof2_ss1_a", +- "msiof2_ss2_a", +- "msiof2_txd_a", +- "msiof2_rxd_a", +- "msiof2_clk_b", +- "msiof2_sync_b", +- "msiof2_ss1_b", +- "msiof2_ss2_b", +- "msiof2_txd_b", +- "msiof2_rxd_b", +- "msiof2_clk_c", +- "msiof2_sync_c", +- "msiof2_ss1_c", +- "msiof2_ss2_c", +- "msiof2_txd_c", +- "msiof2_rxd_c", +- "msiof2_clk_d", +- "msiof2_sync_d", +- "msiof2_ss1_d", +- "msiof2_ss2_d", +- "msiof2_txd_d", +- "msiof2_rxd_d", +-}; ++ /* IPSR9 */ ++ PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK), ++ PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8), + +-static const char * const msiof3_groups[] = { +- "msiof3_clk_a", +- "msiof3_sync_a", +- "msiof3_ss1_a", +- "msiof3_ss2_a", +- "msiof3_txd_a", +- "msiof3_rxd_a", +- "msiof3_clk_b", +- "msiof3_sync_b", +- "msiof3_ss1_b", +- "msiof3_ss2_b", +- "msiof3_txd_b", +- "msiof3_rxd_b", +- "msiof3_clk_c", +- "msiof3_sync_c", +- "msiof3_txd_c", +- "msiof3_rxd_c", +- "msiof3_clk_d", +- "msiof3_sync_d", +- "msiof3_ss1_d", +- "msiof3_txd_d", +- "msiof3_rxd_d", +-}; ++ PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD), ++ PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9), + +-static const char * const pwm0_groups[] = { +- "pwm0", +-}; ++ PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0), ++ PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10), + +-static const char * const pwm1_groups[] = { +- "pwm1_a", +- "pwm1_b", +-}; ++ PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1), ++ PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11), + +-static const char * const pwm2_groups[] = { +- "pwm2_a", +- "pwm2_b", +-}; ++ PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2), ++ PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12), + +-static const char * const pwm3_groups[] = { +- "pwm3_a", +- "pwm3_b", +-}; ++ PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3), ++ PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13), + +-static const char * const pwm4_groups[] = { +- "pwm4_a", +- "pwm4_b", +-}; ++ PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS), ++ PINMUX_IPSR_GPSR(IP9_27_24, NFALE), ++ PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B), + +-static const char * const pwm5_groups[] = { +- "pwm5_a", +- "pwm5_b", +-}; ++ PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK), ++ PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N), + +-static const char * const pwm6_groups[] = { +- "pwm6_a", +- "pwm6_b", +-}; ++ /* IPSR10 */ ++ PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD), ++ PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N), + +-static const char * const qspi0_groups[] = { +- "qspi0_ctrl", +- "qspi0_data2", +- "qspi0_data4", +-}; ++ PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0), ++ PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0), + +-static const char * const qspi1_groups[] = { +- "qspi1_ctrl", +- "qspi1_data2", +- "qspi1_data4", +-}; ++ PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1), ++ PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1), + +-static const char * const sata0_groups[] = { +- "sata0_devslp_a", +- "sata0_devslp_b", +-}; ++ PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2), ++ PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2), + +-static const char * const scif0_groups[] = { +- "scif0_data", +- "scif0_clk", +- "scif0_ctrl", +-}; ++ PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3), ++ PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3), + +-static const char * const scif1_groups[] = { +- "scif1_data_a", +- "scif1_clk", +- "scif1_ctrl", +- "scif1_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4), ++ PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0), ++ PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4), + +-static const char * const scif2_groups[] = { +- "scif2_data_a", +- "scif2_clk", +- "scif2_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5), ++ PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0), ++ PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5), + +-static const char * const scif3_groups[] = { +- "scif3_data_a", +- "scif3_clk", +- "scif3_ctrl", +- "scif3_data_b", +-}; ++ PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6), ++ PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD), ++ PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6), + +-static const char * const scif4_groups[] = { +- "scif4_data_a", +- "scif4_clk_a", +- "scif4_ctrl_a", +- "scif4_data_b", +- "scif4_clk_b", +- "scif4_ctrl_b", +- "scif4_data_c", +- "scif4_clk_c", +- "scif4_ctrl_c", +-}; ++ /* IPSR11 */ ++ PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7), ++ PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP), ++ PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7), ++ ++ PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS), ++ PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), ++ ++ PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), ++ PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), ++ PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), ++ ++ PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), ++ PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), ++ ++ PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), ++ PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), ++ ++ PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), ++ PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), ++ ++ PINMUX_IPSR_GPSR(IP11_27_24, SCK0), ++ PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), ++ PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), ++ PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), ++ PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1), ++ PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2), ++ PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1), ++ ++ PINMUX_IPSR_GPSR(IP11_31_28, RX0), ++ PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1), + +-static const char * const scif5_groups[] = { +- "scif5_data", +- "scif5_clk", +-}; ++ /* IPSR12 */ ++ PINMUX_IPSR_GPSR(IP12_3_0, TX0), ++ PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1), ++ ++ PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N), ++ PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C), ++ PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP), ++ ++ PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS), ++ PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), ++ PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), ++ PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), ++ PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), ++ PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), ++ ++ PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2), ++ ++ PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2), ++ PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2), ++ ++ PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N), ++ PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA), ++ ++ PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS), ++ PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), ++ ++ PINMUX_IPSR_GPSR(IP12_31_28, SCK2), ++ PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), ++ PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), ++ PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1), ++ PINMUX_IPSR_GPSR(IP12_31_28, ADICLK), + +-static const char * const scif_clk_groups[] = { +- "scif_clk_a", +- "scif_clk_b", +-}; ++ /* IPSR13 */ ++ PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1), ++ PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), ++ PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), ++ PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), ++ PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N), ++ ++ PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), ++ PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), ++ PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), ++ PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), ++ PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N), ++ ++ PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), ++ PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), ++ PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2), ++ PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1), ++ ++ PINMUX_IPSR_GPSR(IP13_15_12, HRX0), ++ PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2), ++ ++ PINMUX_IPSR_GPSR(IP13_19_16, HTX0), ++ PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2), ++ ++ PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N), ++ PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3), ++ PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2), ++ PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A), ++ ++ PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N), ++ PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1), ++ PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0), ++ PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A), ++ ++ PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC), ++ PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A), ++ PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1), ++ PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3), + +-static const char * const sdhi0_groups[] = { +- "sdhi0_data1", +- "sdhi0_data4", +- "sdhi0_ctrl", +- "sdhi0_cd", +- "sdhi0_wp", +-}; ++ /* IPSR14 */ ++ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), ++ PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), ++ PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), ++ PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), ++ PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), ++ PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), ++ PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), ++ ++ PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), ++ PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), ++ PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), ++ PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), ++ PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), ++ PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), ++ PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1), ++ ++ PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK), ++ PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5), ++ PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1), ++ ++ PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG), ++ PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5), ++ PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1), ++ ++ PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT), ++ PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), ++ PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), ++ PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), ++ PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), ++ ++ PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), ++ PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5), + +-static const char * const sdhi1_groups[] = { +- "sdhi1_data1", +- "sdhi1_data4", +- "sdhi1_ctrl", +- "sdhi1_cd", +- "sdhi1_wp", +-}; ++ /* IPSR15 */ ++ PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0), ++ ++ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), ++ ++ PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34), ++ PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), ++ ++ PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34), ++ PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), ++ ++ PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3), ++ PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4), ++ PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4), ++ PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0), ++ ++ PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4), ++ PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0), ++ PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0), + +-static const char * const sdhi2_groups[] = { +- "sdhi2_data1", +- "sdhi2_data4", +- "sdhi2_data8", +- "sdhi2_ctrl", +- "sdhi2_cd_a", +- "sdhi2_wp_a", +- "sdhi2_cd_b", +- "sdhi2_wp_b", +- "sdhi2_ds", +-}; ++ /* IPSR16 */ ++ PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6), ++ PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN), ++ PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3), ++ ++ PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6), ++ PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC), ++ PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3), ++ ++ PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6), ++ PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3), ++ PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A), ++ ++ PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78), ++ PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78), ++ PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7), ++ PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), ++ PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), ++ ++ PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), ++ PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0), ++ PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0), ++ PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0), ++ ++ PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1), ++ PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0), ++ PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), ++ PINMUX_IPSR_GPSR(IP16_31_28, SCK1), ++ PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), ++ PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), + +-static const char * const sdhi3_groups[] = { +- "sdhi3_data1", +- "sdhi3_data4", +- "sdhi3_data8", +- "sdhi3_ctrl", +- "sdhi3_cd", +- "sdhi3_wp", +- "sdhi3_ds", +-}; ++ /* IPSR17 */ ++ PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), ++ PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), ++ ++ PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), ++ PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), ++ PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), ++ PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), ++ ++ PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), ++ PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1), ++ PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2), ++ ++ PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC), ++ PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1), ++ PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2), ++ ++ PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN), ++ PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2), ++ PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1), ++ PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0), ++ PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2), ++ ++ PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC), ++ PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2), ++ PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0), ++ PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1), ++ PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1), ++ PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1), ++ PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2), ++ ++ PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN), ++ PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), ++ PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), ++ PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), ++ PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), ++ PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), ++ PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), ++ PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), ++ ++ PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC), ++ PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B), ++ PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3), ++ PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), ++ PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), ++ PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N), ++ PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), ++ ++ /* IPSR18 */ ++ PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN), ++ PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), ++ PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), ++ PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), ++ PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), ++ PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), ++ ++ PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC), ++ PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), ++ PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), ++ PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), ++ PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), ++ PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), ++ PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), ++ PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), ++ PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), + +-static const char * const ssi_groups[] = { +- "ssi0_data", +- "ssi01239_ctrl", +- "ssi1_data_a", +- "ssi1_data_b", +- "ssi1_ctrl_a", +- "ssi1_ctrl_b", +- "ssi2_data_a", +- "ssi2_data_b", +- "ssi2_ctrl_a", +- "ssi2_ctrl_b", +- "ssi3_data", +- "ssi34_ctrl", +- "ssi4_data", +- "ssi4_ctrl", +- "ssi5_data", +- "ssi5_ctrl", +- "ssi6_data", +- "ssi6_ctrl", +- "ssi7_data", +- "ssi78_ctrl", +- "ssi8_data", +- "ssi9_data_a", +- "ssi9_data_b", +- "ssi9_ctrl_a", +- "ssi9_ctrl_b", ++/* ++ * Static pins can not be muxed between different functions but ++ * still needs a mark entry in the pinmux list. Add each static ++ * pin to the list without an associated function. The sh-pfc ++ * core will do the right thing and skip trying to mux then pin ++ * while still applying configuration to it ++ */ ++#define FM(x) PINMUX_DATA(x##_MARK, 0), ++ PINMUX_STATIC ++#undef FM + }; + +-static const char * const usb0_groups[] = { +- "usb0", +-}; ++/* ++ * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. ++ * Physical layout rows: A - AW, cols: 1 - 39. ++ */ ++#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) ++#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) ++#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) ++ ++static const struct sh_pfc_pin pinmux_pins[] = { ++ PINMUX_GPIO_GP_ALL(), + +-static const char * const usb1_groups[] = { +- "usb1", ++ /* ++ * Pins not associated with a GPIO port. ++ * ++ * The pin positions are different between different r8a7795 ++ * packages, all that is needed for the pfc driver is a unique ++ * number for each pin. To this end use the pin layout from ++ * R-Car H3SiP to calculate a unique number for each pin. ++ */ ++ SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH), ++ SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + }; + +-static const char * const usb2_groups[] = { +- "usb2", ++static const struct sh_pfc_pin_group pinmux_groups[] = { + }; + + static const struct sh_pfc_function pinmux_functions[] = { +- SH_PFC_FUNCTION(audio_clk), +- SH_PFC_FUNCTION(avb), +- SH_PFC_FUNCTION(can0), +- SH_PFC_FUNCTION(can1), +- SH_PFC_FUNCTION(can_clk), +- SH_PFC_FUNCTION(canfd0), +- SH_PFC_FUNCTION(canfd1), +- SH_PFC_FUNCTION(drif0), +- SH_PFC_FUNCTION(drif1), +- SH_PFC_FUNCTION(drif2), +- SH_PFC_FUNCTION(drif3), +- SH_PFC_FUNCTION(du), +- SH_PFC_FUNCTION(hscif0), +- SH_PFC_FUNCTION(hscif1), +- SH_PFC_FUNCTION(hscif2), +- SH_PFC_FUNCTION(hscif3), +- SH_PFC_FUNCTION(hscif4), +- SH_PFC_FUNCTION(i2c1), +- SH_PFC_FUNCTION(i2c2), +- SH_PFC_FUNCTION(i2c6), +- SH_PFC_FUNCTION(intc_ex), +- SH_PFC_FUNCTION(msiof0), +- SH_PFC_FUNCTION(msiof1), +- SH_PFC_FUNCTION(msiof2), +- SH_PFC_FUNCTION(msiof3), +- SH_PFC_FUNCTION(pwm0), +- SH_PFC_FUNCTION(pwm1), +- SH_PFC_FUNCTION(pwm2), +- SH_PFC_FUNCTION(pwm3), +- SH_PFC_FUNCTION(pwm4), +- SH_PFC_FUNCTION(pwm5), +- SH_PFC_FUNCTION(pwm6), +- SH_PFC_FUNCTION(qspi0), +- SH_PFC_FUNCTION(qspi1), +- SH_PFC_FUNCTION(sata0), +- SH_PFC_FUNCTION(scif0), +- SH_PFC_FUNCTION(scif1), +- SH_PFC_FUNCTION(scif2), +- SH_PFC_FUNCTION(scif3), +- SH_PFC_FUNCTION(scif4), +- SH_PFC_FUNCTION(scif5), +- SH_PFC_FUNCTION(scif_clk), +- SH_PFC_FUNCTION(sdhi0), +- SH_PFC_FUNCTION(sdhi1), +- SH_PFC_FUNCTION(sdhi2), +- SH_PFC_FUNCTION(sdhi3), +- SH_PFC_FUNCTION(ssi), +- SH_PFC_FUNCTION(usb0), +- SH_PFC_FUNCTION(usb1), +- SH_PFC_FUNCTION(usb2), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +@@ -5041,46 +2033,54 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + IP16_3_0 } + }, + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { +- /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ IP17_31_28 ++ IP17_27_24 ++ IP17_23_20 ++ IP17_19_16 ++ IP17_15_12 ++ IP17_11_8 + IP17_7_4 + IP17_3_0 } + }, ++ { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { ++ /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ IP18_7_4 ++ IP18_3_0 } ++ }, + #undef F_ + #undef FM + + #define F_(x, y) x, + #define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, +- 1, 2, 2, 3, 1, 1, 2, 1, 1, 1, +- 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) { +- 0, 0, /* RESERVED 31 */ +- MOD_SEL0_30_29 ++ 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, ++ 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { ++ MOD_SEL0_31_30_29 + MOD_SEL0_28_27 + MOD_SEL0_26_25_24 + MOD_SEL0_23 + MOD_SEL0_22 +- MOD_SEL0_21_20 ++ MOD_SEL0_21 ++ MOD_SEL0_20 + MOD_SEL0_19 +- MOD_SEL0_18 +- MOD_SEL0_17 +- MOD_SEL0_16_15 +- MOD_SEL0_14 +- MOD_SEL0_13 ++ MOD_SEL0_18_17 ++ MOD_SEL0_16 ++ 0, 0, /* RESERVED 15 */ ++ MOD_SEL0_14_13 + MOD_SEL0_12 + MOD_SEL0_11 + MOD_SEL0_10 +- MOD_SEL0_9 +- MOD_SEL0_8 ++ MOD_SEL0_9_8 + MOD_SEL0_7_6 +- MOD_SEL0_5_4 +- MOD_SEL0_3 +- MOD_SEL0_2_1 +- 0, 0, /* RESERVED 0 */ } ++ MOD_SEL0_5 ++ MOD_SEL0_4_3 ++ /* RESERVED 2, 1, 0 */ ++ 0, 0, 0, 0, 0, 0, 0, 0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, + 2, 3, 1, 2, 3, 1, 1, 2, 1, +@@ -5110,22 +2110,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + MOD_SEL1_0 } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, +- 1, 1, 1, 1, 4, 4, 4, +- 4, 4, 4, 1, 2, 1) { ++ 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, ++ 4, 4, 4, 3, 1) { + MOD_SEL2_31 + MOD_SEL2_30 + MOD_SEL2_29 +- /* RESERVED 28 */ ++ MOD_SEL2_28_27 ++ MOD_SEL2_26 ++ MOD_SEL2_25_24_23 ++ MOD_SEL2_22 ++ MOD_SEL2_21 ++ MOD_SEL2_20 ++ MOD_SEL2_19 ++ MOD_SEL2_18 ++ MOD_SEL2_17 ++ /* RESERVED 16 */ + 0, 0, +- /* RESERVED 27, 26, 25, 24 */ +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESERVED 23, 22, 21, 20 */ +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESERVED 19, 18, 17, 16 */ +- 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +@@ -5135,10 +2135,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* RESERVED 7, 6, 5, 4 */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +- /* RESERVED 3 */ +- 0, 0, +- /* RESERVED 2, 1 */ +- 0, 0, 0, 0, ++ /* RESERVED 3, 2, 1 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL2_0 } + }, + { }, +@@ -5387,8 +2385,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ + { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ +- { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */ +- { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */ ++ { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */ ++ { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */ + } }, + { }, + }; +@@ -5618,8 +2616,8 @@ static const struct sh_pfc_bias_info bias_info[] = { + { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ + { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ + +- { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ +- { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ ++ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */ ++ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */ + { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ + { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ + { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ +@@ -5676,14 +2674,28 @@ static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + } + ++static const struct soc_device_attribute r8a7795es1[] = { ++ { .soc_id = "r8a7795", .revision = "ES1.*" }, ++ { /* sentinel */ } ++}; ++ ++static int r8a7795_pinmux_init(struct sh_pfc *pfc) ++{ ++ if (soc_device_match(r8a7795es1)) ++ pfc->info = &r8a7795es1_pinmux_info; ++ ++ return 0; ++} ++ + static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = { ++ .init = r8a7795_pinmux_init, + .pin_to_pocctrl = r8a7795_pin_to_pocctrl, + .get_bias = r8a7795_pinmux_get_bias, + .set_bias = r8a7795_pinmux_set_bias, + }; + + const struct sh_pfc_soc_info r8a7795_pinmux_info = { +- .name = "r8a77950_pfc", ++ .name = "r8a77951_pfc", + .ops = &r8a7795_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + +diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h +index e42cc7a8d10e..f31eb6c1e87d 100644 +--- a/drivers/pinctrl/sh-pfc/sh_pfc.h ++++ b/drivers/pinctrl/sh-pfc/sh_pfc.h +@@ -267,6 +267,7 @@ extern const struct sh_pfc_soc_info r8a7792_pinmux_info; + extern const struct sh_pfc_soc_info r8a7793_pinmux_info; + extern const struct sh_pfc_soc_info r8a7794_pinmux_info; + extern const struct sh_pfc_soc_info r8a7795_pinmux_info; ++extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; + extern const struct sh_pfc_soc_info r8a7796_pinmux_info; + extern const struct sh_pfc_soc_info sh7203_pinmux_info; + extern const struct sh_pfc_soc_info sh7264_pinmux_info; +-- +2.13.3 + diff --git a/patches.renesas/0166-pinctrl-sh-pfc-r8a7795-Add-SCIF-support.patch b/patches.renesas/0166-pinctrl-sh-pfc-r8a7795-Add-SCIF-support.patch new file mode 100644 index 00000000000000..a6e56be288f0ce --- /dev/null +++ b/patches.renesas/0166-pinctrl-sh-pfc-r8a7795-Add-SCIF-support.patch @@ -0,0 +1,311 @@ +From 0ac79cf3378edb359fddcaf995d0c7def7400cd6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 13 Mar 2017 11:28:33 +0100 +Subject: [PATCH 166/286] pinctrl: sh-pfc: r8a7795: Add SCIF support + +Add pins, groups, and functions for all SCIF serial ports on R-Car H3 +ES2.0. + +Extracted from a big patch in the BSP by Takeshi Kihara. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> +(cherry picked from commit e7ad4d3c1dd9dd6881d4470dd6586d5cc84b8e0c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 275 +++++++++++++++++++++++++++++++++++ + 1 file changed, 275 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 6caaed53938c..996cacee99c3 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -1576,10 +1576,285 @@ static const struct sh_pfc_pin pinmux_pins[] = { + SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), + }; + ++/* - SCIF0 ------------------------------------------------------------------ */ ++static const unsigned int scif0_data_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), ++}; ++static const unsigned int scif0_data_mux[] = { ++ RX0_MARK, TX0_MARK, ++}; ++static const unsigned int scif0_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int scif0_clk_mux[] = { ++ SCK0_MARK, ++}; ++static const unsigned int scif0_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), ++}; ++static const unsigned int scif0_ctrl_mux[] = { ++ RTS0_N_TANS_MARK, CTS0_N_MARK, ++}; ++/* - SCIF1 ------------------------------------------------------------------ */ ++static const unsigned int scif1_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), ++}; ++static const unsigned int scif1_data_a_mux[] = { ++ RX1_A_MARK, TX1_A_MARK, ++}; ++static const unsigned int scif1_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int scif1_clk_mux[] = { ++ SCK1_MARK, ++}; ++static const unsigned int scif1_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), ++}; ++static const unsigned int scif1_ctrl_mux[] = { ++ RTS1_N_TANS_MARK, CTS1_N_MARK, ++}; ++ ++static const unsigned int scif1_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), ++}; ++static const unsigned int scif1_data_b_mux[] = { ++ RX1_B_MARK, TX1_B_MARK, ++}; ++/* - SCIF2 ------------------------------------------------------------------ */ ++static const unsigned int scif2_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), ++}; ++static const unsigned int scif2_data_a_mux[] = { ++ RX2_A_MARK, TX2_A_MARK, ++}; ++static const unsigned int scif2_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int scif2_clk_mux[] = { ++ SCK2_MARK, ++}; ++static const unsigned int scif2_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), ++}; ++static const unsigned int scif2_data_b_mux[] = { ++ RX2_B_MARK, TX2_B_MARK, ++}; ++/* - SCIF3 ------------------------------------------------------------------ */ ++static const unsigned int scif3_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), ++}; ++static const unsigned int scif3_data_a_mux[] = { ++ RX3_A_MARK, TX3_A_MARK, ++}; ++static const unsigned int scif3_clk_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 22), ++}; ++static const unsigned int scif3_clk_mux[] = { ++ SCK3_MARK, ++}; ++static const unsigned int scif3_ctrl_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), ++}; ++static const unsigned int scif3_ctrl_mux[] = { ++ RTS3_N_TANS_MARK, CTS3_N_MARK, ++}; ++static const unsigned int scif3_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), ++}; ++static const unsigned int scif3_data_b_mux[] = { ++ RX3_B_MARK, TX3_B_MARK, ++}; ++/* - SCIF4 ------------------------------------------------------------------ */ ++static const unsigned int scif4_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), ++}; ++static const unsigned int scif4_data_a_mux[] = { ++ RX4_A_MARK, TX4_A_MARK, ++}; ++static const unsigned int scif4_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(2, 10), ++}; ++static const unsigned int scif4_clk_a_mux[] = { ++ SCK4_A_MARK, ++}; ++static const unsigned int scif4_ctrl_a_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), ++}; ++static const unsigned int scif4_ctrl_a_mux[] = { ++ RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, ++}; ++static const unsigned int scif4_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), ++}; ++static const unsigned int scif4_data_b_mux[] = { ++ RX4_B_MARK, TX4_B_MARK, ++}; ++static const unsigned int scif4_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(1, 5), ++}; ++static const unsigned int scif4_clk_b_mux[] = { ++ SCK4_B_MARK, ++}; ++static const unsigned int scif4_ctrl_b_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9), ++}; ++static const unsigned int scif4_ctrl_b_mux[] = { ++ RTS4_N_TANS_B_MARK, CTS4_N_B_MARK, ++}; ++static const unsigned int scif4_data_c_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), ++}; ++static const unsigned int scif4_data_c_mux[] = { ++ RX4_C_MARK, TX4_C_MARK, ++}; ++static const unsigned int scif4_clk_c_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(0, 8), ++}; ++static const unsigned int scif4_clk_c_mux[] = { ++ SCK4_C_MARK, ++}; ++static const unsigned int scif4_ctrl_c_pins[] = { ++ /* RTS, CTS */ ++ RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), ++}; ++static const unsigned int scif4_ctrl_c_mux[] = { ++ RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, ++}; ++/* - SCIF5 ------------------------------------------------------------------ */ ++static const unsigned int scif5_data_a_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), ++}; ++static const unsigned int scif5_data_a_mux[] = { ++ RX5_A_MARK, TX5_A_MARK, ++}; ++static const unsigned int scif5_clk_a_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(6, 21), ++}; ++static const unsigned int scif5_clk_a_mux[] = { ++ SCK5_A_MARK, ++}; ++static const unsigned int scif5_data_b_pins[] = { ++ /* RX, TX */ ++ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18), ++}; ++static const unsigned int scif5_data_b_mux[] = { ++ RX5_B_MARK, TX5_B_MARK, ++}; ++static const unsigned int scif5_clk_b_pins[] = { ++ /* SCK */ ++ RCAR_GP_PIN(5, 0), ++}; ++static const unsigned int scif5_clk_b_mux[] = { ++ SCK5_B_MARK, ++}; ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { ++ SH_PFC_PIN_GROUP(scif0_data), ++ SH_PFC_PIN_GROUP(scif0_clk), ++ SH_PFC_PIN_GROUP(scif0_ctrl), ++ SH_PFC_PIN_GROUP(scif1_data_a), ++ SH_PFC_PIN_GROUP(scif1_clk), ++ SH_PFC_PIN_GROUP(scif1_ctrl), ++ SH_PFC_PIN_GROUP(scif1_data_b), ++ SH_PFC_PIN_GROUP(scif2_data_a), ++ SH_PFC_PIN_GROUP(scif2_clk), ++ SH_PFC_PIN_GROUP(scif2_data_b), ++ SH_PFC_PIN_GROUP(scif3_data_a), ++ SH_PFC_PIN_GROUP(scif3_clk), ++ SH_PFC_PIN_GROUP(scif3_ctrl), ++ SH_PFC_PIN_GROUP(scif3_data_b), ++ SH_PFC_PIN_GROUP(scif4_data_a), ++ SH_PFC_PIN_GROUP(scif4_clk_a), ++ SH_PFC_PIN_GROUP(scif4_ctrl_a), ++ SH_PFC_PIN_GROUP(scif4_data_b), ++ SH_PFC_PIN_GROUP(scif4_clk_b), ++ SH_PFC_PIN_GROUP(scif4_ctrl_b), ++ SH_PFC_PIN_GROUP(scif4_data_c), ++ SH_PFC_PIN_GROUP(scif4_clk_c), ++ SH_PFC_PIN_GROUP(scif4_ctrl_c), ++ SH_PFC_PIN_GROUP(scif5_data_a), ++ SH_PFC_PIN_GROUP(scif5_clk_a), ++ SH_PFC_PIN_GROUP(scif5_data_b), ++ SH_PFC_PIN_GROUP(scif5_clk_b), ++}; ++ ++static const char * const scif0_groups[] = { ++ "scif0_data", ++ "scif0_clk", ++ "scif0_ctrl", ++}; ++ ++static const char * const scif1_groups[] = { ++ "scif1_data_a", ++ "scif1_clk", ++ "scif1_ctrl", ++ "scif1_data_b", ++}; ++ ++static const char * const scif2_groups[] = { ++ "scif2_data_a", ++ "scif2_clk", ++ "scif2_data_b", ++}; ++ ++static const char * const scif3_groups[] = { ++ "scif3_data_a", ++ "scif3_clk", ++ "scif3_ctrl", ++ "scif3_data_b", ++}; ++ ++static const char * const scif4_groups[] = { ++ "scif4_data_a", ++ "scif4_clk_a", ++ "scif4_ctrl_a", ++ "scif4_data_b", ++ "scif4_clk_b", ++ "scif4_ctrl_b", ++ "scif4_data_c", ++ "scif4_clk_c", ++ "scif4_ctrl_c", ++}; ++ ++static const char * const scif5_groups[] = { ++ "scif5_data_a", ++ "scif5_clk_a", ++ "scif5_data_b", ++ "scif5_clk_b", + }; + + static const struct sh_pfc_function pinmux_functions[] = { ++ SH_PFC_FUNCTION(scif0), ++ SH_PFC_FUNCTION(scif1), ++ SH_PFC_FUNCTION(scif2), ++ SH_PFC_FUNCTION(scif3), ++ SH_PFC_FUNCTION(scif4), ++ SH_PFC_FUNCTION(scif5), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +2.13.3 + diff --git a/patches.renesas/0167-pinctrl-sh-pfc-r8a7795-Add-SCIF_CLK-support.patch b/patches.renesas/0167-pinctrl-sh-pfc-r8a7795-Add-SCIF_CLK-support.patch new file mode 100644 index 00000000000000..4bac280b668a59 --- /dev/null +++ b/patches.renesas/0167-pinctrl-sh-pfc-r8a7795-Add-SCIF_CLK-support.patch @@ -0,0 +1,78 @@ +From 7beacd9e07c79c5ce325c5e8e4ceb1eff76ccf66 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 13 Mar 2017 11:28:39 +0100 +Subject: [PATCH 167/286] pinctrl: sh-pfc: r8a7795: Add SCIF_CLK support + +Add pins, groups, and a function for SCIF_CLK on R-Car H3 ES2.0. +SCIF_CLK is the external clock source for the Baud Rate Generator for +External Clock (BRG) on (H)SCIF serial ports. + +Extracted from a big patch in the BSP by Takeshi Kihara. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> +(cherry picked from commit d14a39edf757f5bdd73cf25d0155d7cfb271e782) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +index 996cacee99c3..0454f31c0831 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -1773,6 +1773,22 @@ static const unsigned int scif5_clk_b_mux[] = { + SCK5_B_MARK, + }; + ++/* - SCIF Clock ------------------------------------------------------------- */ ++static const unsigned int scif_clk_a_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(6, 23), ++}; ++static const unsigned int scif_clk_a_mux[] = { ++ SCIF_CLK_A_MARK, ++}; ++static const unsigned int scif_clk_b_pins[] = { ++ /* SCIF_CLK */ ++ RCAR_GP_PIN(5, 9), ++}; ++static const unsigned int scif_clk_b_mux[] = { ++ SCIF_CLK_B_MARK, ++}; ++ + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), +@@ -1801,6 +1817,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(scif5_clk_a), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scif5_clk_b), ++ SH_PFC_PIN_GROUP(scif_clk_a), ++ SH_PFC_PIN_GROUP(scif_clk_b), + }; + + static const char * const scif0_groups[] = { +@@ -1848,6 +1866,11 @@ static const char * const scif5_groups[] = { + "scif5_clk_b", + }; + ++static const char * const scif_clk_groups[] = { ++ "scif_clk_a", ++ "scif_clk_b", ++}; ++ + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), +@@ -1855,6 +1878,7 @@ static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), ++ SH_PFC_FUNCTION(scif_clk), + }; + + static const struct pinmux_cfg_reg pinmux_config_regs[] = { +-- +2.13.3 + diff --git a/patches.renesas/0168-pinctrl-sh-pfc-r8a7791-Add-missing-HSCIF1-pinmux-dat.patch b/patches.renesas/0168-pinctrl-sh-pfc-r8a7791-Add-missing-HSCIF1-pinmux-dat.patch new file mode 100644 index 00000000000000..00c0d42c862d9a --- /dev/null +++ b/patches.renesas/0168-pinctrl-sh-pfc-r8a7791-Add-missing-HSCIF1-pinmux-dat.patch @@ -0,0 +1,52 @@ +From 0e1c9e8e6eff51a650699a24a70559729ea01498 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 29 Mar 2017 21:36:50 +0300 +Subject: [PATCH 168/286] pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux + data + +The R8A7791 PFC driver was apparently based on the preliminary revisions +of the user's manual, which omitted the HSCIF1 group E signals in the +IPSR4 register description. This would cause HSCIF1's probe to fail with +the messages like below: + +sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989 +sh-sci e62c8000.serial: Error applying setting, reverse things back +sh-sci: probe of e62c8000.serial failed with error -22 + +Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E, +HCTS1#_E, and HRTS1#_E signals... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit da7a692fbbab07f4e9798b5b52798f6e3256dd8f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index 841cecdca7ea..cc852e68162c 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), ++ PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), + PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), + PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), ++ PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), + PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), ++ PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), + PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), + PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), + PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), +-- +2.13.3 + diff --git a/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-missing-DVC_MUTE-signal.patch b/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-missing-DVC_MUTE-signal.patch new file mode 100644 index 00000000000000..aea58b7b97e563 --- /dev/null +++ b/patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-missing-DVC_MUTE-signal.patch @@ -0,0 +1,61 @@ +From e623e96e9d8f94460fcb2488613e64c9583ca4d0 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Wed, 29 Mar 2017 21:36:51 +0300 +Subject: [PATCH 169/286] pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal + +The R8A7791 PFC driver was apparently based on the preliminary revisions +of the user's manual, which omitted the DVC_MUTE signal altogether in +the PFC section. The modern manual has the signal described, so just add +the necassary data to the driver... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 3908632fb829d73317c64c3d04f584b49f62e4ae) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index cc852e68162c..41ac1a3b1964 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -203,7 +203,7 @@ enum { + + /* IPSR6 */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, +- FN_SCIF_CLK, FN_BPFCLK_E, ++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, + FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, + FN_SCIFA2_RXD, FN_FMIN_E, + FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, +@@ -573,7 +573,7 @@ enum { + + /* IPSR6 */ + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, +- SCIF_CLK_MARK, BPFCLK_E_MARK, ++ SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, + AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK, + AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, +@@ -1093,6 +1093,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), + PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), ++ PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), + PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), + PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), +@@ -5899,7 +5900,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, + /* IP6_2_0 [3] */ + FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, +- FN_SCIF_CLK, 0, FN_BPFCLK_E, ++ FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, +-- +2.13.3 + diff --git a/patches.renesas/0170-pinctrl-sh-pfc-r8a7791-Fix-SCIF2-pinmux-data.patch b/patches.renesas/0170-pinctrl-sh-pfc-r8a7791-Fix-SCIF2-pinmux-data.patch new file mode 100644 index 00000000000000..c16ecb29c55df8 --- /dev/null +++ b/patches.renesas/0170-pinctrl-sh-pfc-r8a7791-Fix-SCIF2-pinmux-data.patch @@ -0,0 +1,33 @@ +From 6ccc9616097306424a0da7460e4a9042dc81fe58 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Thu, 30 Mar 2017 23:20:48 +0300 +Subject: [PATCH 170/286] pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux data + +PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong +1st argument -- most probably a result of cut&paste programming... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 58439280f84e6b39fd7d61f25ab30489c1aaf0a9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index 41ac1a3b1964..437238691d16 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -1103,7 +1103,7 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), + PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), +- PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0), ++ PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), + PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), + PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), + PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), +-- +2.13.3 + diff --git a/patches.renesas/0171-pinctrl-sh-pfc-r8a7791-Fix-IPSR-comment-typos.patch b/patches.renesas/0171-pinctrl-sh-pfc-r8a7791-Fix-IPSR-comment-typos.patch new file mode 100644 index 00000000000000..cd6eb552142b5f --- /dev/null +++ b/patches.renesas/0171-pinctrl-sh-pfc-r8a7791-Fix-IPSR-comment-typos.patch @@ -0,0 +1,51 @@ +From 782ab75e31402a584270aecee91764660a6de41f Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Fri, 31 Mar 2017 23:29:23 +0300 +Subject: [PATCH 171/286] pinctrl: sh-pfc: r8a7791: Fix IPSR comment typos + +The IPSR field names in the comments have been fat-fingered in a couple +places -- fix those silly typos... + +Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 0cbdc11482d72ad164e33ef7cc57b01e8b61e40d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +index 437238691d16..2ed7eeb50aac 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +@@ -5711,7 +5711,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, + 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { +- /* IP2_31_20 [2] */ ++ /* IP2_31_30 [2] */ + 0, 0, 0, 0, + /* IP2_29_27 [3] */ + FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, +@@ -5731,7 +5731,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP2_15_13 [3] */ + FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, + 0, 0, 0, +- /* IP2_12_0 [3] */ ++ /* IP2_12_10 [3] */ + FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, + 0, 0, 0, + /* IP2_9_7 [3] */ +@@ -6042,7 +6042,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + /* IP10_24_22 [3] */ + FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N, + 0, 0, 0, +- /* IP10_21_29 [3] */ ++ /* IP10_21_19 [3] */ + FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, + FN_TS_SDATA0_C, FN_ATACS11_N, + 0, 0, 0, +-- +2.13.3 + diff --git a/patches.renesas/0172-pinctrl-sh-pfc-r8a7794-Swap-ATA-signals.patch b/patches.renesas/0172-pinctrl-sh-pfc-r8a7794-Swap-ATA-signals.patch new file mode 100644 index 00000000000000..d6038b1b457580 --- /dev/null +++ b/patches.renesas/0172-pinctrl-sh-pfc-r8a7794-Swap-ATA-signals.patch @@ -0,0 +1,75 @@ +From 5fe6e9d9a8917a5ecdcabfc60c35b66136e40d28 Mon Sep 17 00:00:00 2001 +From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Date: Tue, 4 Apr 2017 23:20:16 +0300 +Subject: [PATCH 172/286] pinctrl: sh-pfc: r8a7794: Swap ATA signals + +All R8A7794 manuals I have here (0.50 and 1.10) agree that the PFC driver +has ATAG0# and ATAWR0# signals in IPSR12 swapped -- fix this. + +Fixes: 43c4436e2f18 ("pinctrl: sh-pfc: add R8A7794 PFC support") +Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +(cherry picked from commit 5f4c8cafe1148f8a91287072815df8f0b66f0e5c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +index ed734f560c84..ef093ac0cf2f 100644 +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +@@ -281,8 +281,8 @@ enum { + FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, + FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, + FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, +- FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, +- FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B, ++ FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, ++ FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B, + + /* IPSR13 */ + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, +@@ -575,8 +575,8 @@ enum { + ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, + VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, + SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, +- ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, +- VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK, ++ ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, ++ VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK, + + /* IPSR13 */ + SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, +@@ -1413,13 +1413,13 @@ static const u16 pinmux_data[] = { + PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), + PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), +- PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N), ++ PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), + PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), + PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), + PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), + PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), + PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), +- PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N), ++ PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), + PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), + + /* IPSR13 */ +@@ -4938,10 +4938,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, +- FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0, ++ FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, + /* IP12_26_24 [3] */ + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, +- FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0, ++ FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, + /* IP12_23_21 [3] */ + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, + FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, +-- +2.13.3 + diff --git a/patches.renesas/0173-net-phy-micrel-Restore-led_mode-and-clk_sel-on-resum.patch b/patches.renesas/0173-net-phy-micrel-Restore-led_mode-and-clk_sel-on-resum.patch new file mode 100644 index 00000000000000..d17bdfc54db0d3 --- /dev/null +++ b/patches.renesas/0173-net-phy-micrel-Restore-led_mode-and-clk_sel-on-resum.patch @@ -0,0 +1,101 @@ +From 1e3c864a163ae8b999df3cdf65338d2d628dd3c8 Mon Sep 17 00:00:00 2001 +From: Leonard Crestez <leonard.crestez@nxp.com> +Date: Wed, 31 May 2017 13:29:30 +0300 +Subject: [PATCH 173/286] net: phy: micrel: Restore led_mode and clk_sel on + resume + +These bits seem to be lost after a suspend/resume cycle so just set them +again. Do this by splitting the handling of these bits into a function +that is also called on resume. + +This patch fixes ethernet suspend/resume on imx6ul-14x14-evk boards. + +Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 79e498a9c7da0737829ff864aae44df434105676) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/phy/micrel.c | 42 ++++++++++++++++++++++++++++-------------- + 1 file changed, 28 insertions(+), 14 deletions(-) + +diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c +index da5b39268370..d18d631c9fed 100644 +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -268,23 +268,12 @@ static int kszphy_nand_tree_disable(struct phy_device *phydev) + return ret; + } + +-static int kszphy_config_init(struct phy_device *phydev) ++/* Some config bits need to be set again on resume, handle them here. */ ++static int kszphy_config_reset(struct phy_device *phydev) + { + struct kszphy_priv *priv = phydev->priv; +- const struct kszphy_type *type; + int ret; + +- if (!priv) +- return 0; +- +- type = priv->type; +- +- if (type->has_broadcast_disable) +- kszphy_broadcast_disable(phydev); +- +- if (type->has_nand_tree_disable) +- kszphy_nand_tree_disable(phydev); +- + if (priv->rmii_ref_clk_sel) { + ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); + if (ret) { +@@ -295,11 +284,30 @@ static int kszphy_config_init(struct phy_device *phydev) + } + + if (priv->led_mode >= 0) +- kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); ++ kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); + + return 0; + } + ++static int kszphy_config_init(struct phy_device *phydev) ++{ ++ struct kszphy_priv *priv = phydev->priv; ++ const struct kszphy_type *type; ++ ++ if (!priv) ++ return 0; ++ ++ type = priv->type; ++ ++ if (type->has_broadcast_disable) ++ kszphy_broadcast_disable(phydev); ++ ++ if (type->has_nand_tree_disable) ++ kszphy_nand_tree_disable(phydev); ++ ++ return kszphy_config_reset(phydev); ++} ++ + static int ksz8041_config_init(struct phy_device *phydev) + { + struct device_node *of_node = phydev->mdio.dev.of_node; +@@ -701,8 +709,14 @@ static int kszphy_suspend(struct phy_device *phydev) + + static int kszphy_resume(struct phy_device *phydev) + { ++ int ret; ++ + genphy_resume(phydev); + ++ ret = kszphy_config_reset(phydev); ++ if (ret) ++ return ret; ++ + /* Enable PHY Interrupts */ + if (phy_interrupt_is_valid(phydev)) { + phydev->interrupts = PHY_INTERRUPT_ENABLED; +-- +2.13.3 + diff --git a/patches.renesas/0174-soc-renesas-rcar-sysc-Add-support-for-fixing-up-powe.patch b/patches.renesas/0174-soc-renesas-rcar-sysc-Add-support-for-fixing-up-powe.patch new file mode 100644 index 00000000000000..dd0abe0daa2d74 --- /dev/null +++ b/patches.renesas/0174-soc-renesas-rcar-sysc-Add-support-for-fixing-up-powe.patch @@ -0,0 +1,112 @@ +From 0b6f708e3ef268a78ac16a600b28f593ffe222ac Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 31 Mar 2017 11:01:55 +0200 +Subject: [PATCH 174/286] soc: renesas: rcar-sysc: Add support for fixing up + power area tables + +The same SoC may have different power areas, depending on SoC revision. +One option is to use different sets of power area tables for each SoC +revision. However, if the differences are small, it is much more +space-efficient to have a single set of tables, and fix those up at +runtime instead. + +Hence provide a helper to NULLify power areas that do not exist on some +revisions (NULLified power areas are skipped during the registration +phase), and support for an optional initialization callback to e.g. fix +up power area tables. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit afa6f53df6052968ce3934ad324777c0057e31d1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/soc/renesas/rcar-sysc.c | 25 ++++++++++++++++++++++++- + drivers/soc/renesas/rcar-sysc.h | 10 ++++++++++ + 2 files changed, 34 insertions(+), 1 deletion(-) + +diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c +index 225c35c79d9a..528a13742aeb 100644 +--- a/drivers/soc/renesas/rcar-sysc.c ++++ b/drivers/soc/renesas/rcar-sysc.c +@@ -2,7 +2,7 @@ + * R-Car SYSC Power management support + * + * Copyright (C) 2014 Magnus Damm +- * Copyright (C) 2015-2016 Glider bvba ++ * Copyright (C) 2015-2017 Glider bvba + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive +@@ -334,6 +334,12 @@ static int __init rcar_sysc_pd_init(void) + + info = match->data; + ++ if (info->init) { ++ error = info->init(); ++ if (error) ++ return error; ++ } ++ + has_cpg_mstp = of_find_compatible_node(NULL, NULL, + "renesas,cpg-mstp-clocks"); + +@@ -377,6 +383,11 @@ static int __init rcar_sysc_pd_init(void) + const struct rcar_sysc_area *area = &info->areas[i]; + struct rcar_sysc_pd *pd; + ++ if (!area->name) { ++ /* Skip NULLified area */ ++ continue; ++ } ++ + pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL); + if (!pd) { + error = -ENOMEM; +@@ -406,6 +417,18 @@ static int __init rcar_sysc_pd_init(void) + } + early_initcall(rcar_sysc_pd_init); + ++void __init rcar_sysc_nullify(struct rcar_sysc_area *areas, ++ unsigned int num_areas, u8 id) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < num_areas; i++) ++ if (areas[i].isr_bit == id) { ++ areas[i].name = NULL; ++ return; ++ } ++} ++ + void __init rcar_sysc_init(phys_addr_t base, u32 syscier) + { + u32 syscimr; +diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h +index f6e842e2976e..07edb049a401 100644 +--- a/drivers/soc/renesas/rcar-sysc.h ++++ b/drivers/soc/renesas/rcar-sysc.h +@@ -46,6 +46,7 @@ struct rcar_sysc_area { + */ + + struct rcar_sysc_info { ++ int (*init)(void); /* Optional */ + const struct rcar_sysc_area *areas; + unsigned int num_areas; + }; +@@ -59,4 +60,13 @@ extern const struct rcar_sysc_info r8a7792_sysc_info; + extern const struct rcar_sysc_info r8a7794_sysc_info; + extern const struct rcar_sysc_info r8a7795_sysc_info; + extern const struct rcar_sysc_info r8a7796_sysc_info; ++ ++ ++ /* ++ * Helpers for fixing up power area tables depending on SoC revision ++ */ ++ ++extern void rcar_sysc_nullify(struct rcar_sysc_area *areas, ++ unsigned int num_areas, u8 id); ++ + #endif /* __SOC_RENESAS_RCAR_SYSC_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0175-soc-renesas-rcar-sysc-Add-support-for-R-Car-H3-ES2.0.patch b/patches.renesas/0175-soc-renesas-rcar-sysc-Add-support-for-R-Car-H3-ES2.0.patch new file mode 100644 index 00000000000000..42e9d8a2f45130 --- /dev/null +++ b/patches.renesas/0175-soc-renesas-rcar-sysc-Add-support-for-R-Car-H3-ES2.0.patch @@ -0,0 +1,107 @@ +From d2a85d448dc0d4fff9fdbab27ed4008e6d52a4c7 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Fri, 31 Mar 2017 11:01:56 +0200 +Subject: [PATCH 175/286] soc: renesas: rcar-sysc: Add support for R-Car H3 + ES2.0 + +Power area A2VC0 was removed in revision ES2.0, cfr. R-Car Gen3 Hardware +User's Manual rev. 0.53E. + +Hence remove it from the power area table when not running on ES1.x. + +This is in line with the goal to: + 1. Support both the ES1.x and ES2.0 SoC revisions in a single binary + for now, + 2. Make it clear which code supports ES1.x, so it can easily be + identified and removed later, when production SoCs are deemed + ubiquitous. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit fcb87087261e1be51b4c03677f39246bdc312b1c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/soc/renesas/r8a7795-sysc.c | 26 ++++++++++++++++++++++++-- + include/dt-bindings/power/r8a7795-sysc.h | 2 +- + 2 files changed, 25 insertions(+), 3 deletions(-) + +diff --git a/drivers/soc/renesas/r8a7795-sysc.c b/drivers/soc/renesas/r8a7795-sysc.c +index 5e7537c96f7b..7412666187b3 100644 +--- a/drivers/soc/renesas/r8a7795-sysc.c ++++ b/drivers/soc/renesas/r8a7795-sysc.c +@@ -1,7 +1,7 @@ + /* + * Renesas R-Car H3 System Controller + * +- * Copyright (C) 2016 Glider bvba ++ * Copyright (C) 2016-2017 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -10,12 +10,13 @@ + + #include <linux/bug.h> + #include <linux/kernel.h> ++#include <linux/sys_soc.h> + + #include <dt-bindings/power/r8a7795-sysc.h> + + #include "rcar-sysc.h" + +-static const struct rcar_sysc_area r8a7795_areas[] __initconst = { ++static struct rcar_sysc_area r8a7795_areas[] __initdata = { + { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, + { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON, + PD_SCU }, +@@ -40,6 +41,7 @@ static const struct rcar_sysc_area r8a7795_areas[] __initconst = { + { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON }, + { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON }, + { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON }, ++ /* A2VC0 exists on ES1.x only */ + { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC }, + { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC }, + { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON }, +@@ -50,7 +52,27 @@ static const struct rcar_sysc_area r8a7795_areas[] __initconst = { + { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON }, + }; + ++ ++ /* ++ * Fixups for R-Car H3 revisions after ES1.x ++ */ ++ ++static const struct soc_device_attribute r8a7795es1[] __initconst = { ++ { .soc_id = "r8a7795", .revision = "ES1.*" }, ++ { /* sentinel */ } ++}; ++ ++static int __init r8a7795_sysc_init(void) ++{ ++ if (!soc_device_match(r8a7795es1)) ++ rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas), ++ R8A7795_PD_A2VC0); ++ ++ return 0; ++} ++ + const struct rcar_sysc_info r8a7795_sysc_info __initconst = { ++ .init = r8a7795_sysc_init, + .areas = r8a7795_areas, + .num_areas = ARRAY_SIZE(r8a7795_areas), + }; +diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h +index ee2e26ba605e..ad679eeda137 100644 +--- a/include/dt-bindings/power/r8a7795-sysc.h ++++ b/include/dt-bindings/power/r8a7795-sysc.h +@@ -33,7 +33,7 @@ + #define R8A7795_PD_CA53_SCU 21 + #define R8A7795_PD_3DG_E 22 + #define R8A7795_PD_A3IR 24 +-#define R8A7795_PD_A2VC0 25 ++#define R8A7795_PD_A2VC0 25 /* ES1.x only */ + #define R8A7795_PD_A2VC1 26 + + /* Always-on power area */ +-- +2.13.3 + diff --git a/patches.renesas/0176-usb-xhci-plat-Enable-async-suspend-resume.patch b/patches.renesas/0176-usb-xhci-plat-Enable-async-suspend-resume.patch new file mode 100644 index 00000000000000..6f144665b8fee1 --- /dev/null +++ b/patches.renesas/0176-usb-xhci-plat-Enable-async-suspend-resume.patch @@ -0,0 +1,40 @@ +From 1c9d9aa71732d17d6d0653992f6332d52fa5b72d Mon Sep 17 00:00:00 2001 +From: Andrew Bresticker <abrestic@chromium.org> +Date: Fri, 7 Apr 2017 17:56:49 +0300 +Subject: [PATCH 176/286] usb: xhci: plat: Enable async suspend/resume + +USB host controllers can take a significant amount of time to suspend +and resume, adding several hundred miliseconds to the kernel resume +time. Since the XHCI controller has no outside dependencies (other than +clocks, which are suspended late/resumed early), allow it to suspend and +resume asynchronously. + +Signed-off-by: Andrew Bresticker <abrestic@chromium.org> +Tested-by: Andrew Bresticker <abrestic@chromium.org> +Tested-by: Robert Foss <robert.foss@collabora.com> +Signed-off-by: Robert Foss <robert.foss@collabora.com> +Reviewed-by: Baolin Wang <baolin.wang@linaro.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit c70a1529b29cb1362ade5dd113313fb945e32c3e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 66ddd080a2a8..37f59a975dd9 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -258,6 +258,8 @@ static int xhci_plat_probe(struct platform_device *pdev) + if (ret) + goto dealloc_usb2_hcd; + ++ device_enable_async_suspend(&pdev->dev); ++ + return 0; + + +-- +2.13.3 + diff --git a/patches.renesas/0177-usb-xhci-clear-EINT-bit-in-status-correctly.patch b/patches.renesas/0177-usb-xhci-clear-EINT-bit-in-status-correctly.patch new file mode 100644 index 00000000000000..419292ea6c2845 --- /dev/null +++ b/patches.renesas/0177-usb-xhci-clear-EINT-bit-in-status-correctly.patch @@ -0,0 +1,55 @@ +From cf710c5355d76e66ab14457e5dd69666feb959e2 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:56:50 +0300 +Subject: [PATCH 177/286] usb: xhci: clear EINT bit in status correctly + +EINT(Event Interrupt) is a write-1-to-clear type of bit in xhci +status register. It should be cleared by writing a 1. Writing 0 +to this bit has no effect. + +Xhci driver tries to clear this bit by writing 0 to it. This is +not the right way to go. This patch corrects this by reading the +register first, then clearing all RO/RW1C/RsvZ bits and setting +the clearing bit, and writing back the new value at last. + +Xhci spec requires that software that uses EINT shall clear it +prior to clearing any IP flags in section 5.4.2. This is the +reason why this patch is CC'ed stable as well. + +[old way didn't cause any issues, skip stable, send to next -Mathias] + +Cc: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d1001ab41064c7fe7bffbc1d7c3921912f3ec32d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 304ee6bbe80c..cb3871c93004 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -721,7 +721,7 @@ void xhci_stop(struct usb_hcd *hcd) + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "// Disabling event ring interrupts"); + temp = readl(&xhci->op_regs->status); +- writel(temp & ~STS_EINT, &xhci->op_regs->status); ++ writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); + temp = readl(&xhci->ir_set->irq_pending); + writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); + xhci_print_ir_set(xhci, 0); +@@ -1054,7 +1054,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) + + xhci_dbg(xhci, "// Disabling event ring interrupts\n"); + temp = readl(&xhci->op_regs->status); +- writel(temp & ~STS_EINT, &xhci->op_regs->status); ++ writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); + temp = readl(&xhci->ir_set->irq_pending); + writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); + xhci_print_ir_set(xhci, 0); +-- +2.13.3 + diff --git a/patches.renesas/0178-usb-xhci-Add-helper-function-xhci_set_power_on.patch b/patches.renesas/0178-usb-xhci-Add-helper-function-xhci_set_power_on.patch new file mode 100644 index 00000000000000..29d47b4cddbec4 --- /dev/null +++ b/patches.renesas/0178-usb-xhci-Add-helper-function-xhci_set_power_on.patch @@ -0,0 +1,114 @@ +From 2f52c448c1b08f807620823deb0a096a26b754d0 Mon Sep 17 00:00:00 2001 +From: Guoqing Zhang <guoqing.zhang@intel.com> +Date: Fri, 7 Apr 2017 17:56:51 +0300 +Subject: [PATCH 178/286] usb: xhci: Add helper function xhci_set_power_on(). + +Refactoring port power on/off related code into +a helper function xhci_set_power_on() which can +be reused when enabling test mode. + +[set port state to neutral before writing port power -Mathias] +Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit a6ff6cbf1fabe7500d8ac25e133e3346db0a0fca) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 66 ++++++++++++++++++++++++++++++--------------- + 1 file changed, 45 insertions(+), 21 deletions(-) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index 3bddeaa1e2d7..04344c14180c 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -540,6 +540,49 @@ static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) + return max_ports; + } + ++static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index) ++{ ++ __le32 __iomem **port_array; ++ ++ xhci_get_ports(hcd, &port_array); ++ return port_array[index]; ++} ++ ++/* ++ * xhci_set_port_power() must be called with xhci->lock held. ++ * It will release and re-aquire the lock while calling ACPI ++ * method. ++ */ ++static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, ++ u16 index, bool on) ++{ ++ __le32 __iomem *addr; ++ u32 temp; ++ unsigned long flags = 0; ++ ++ addr = xhci_get_port_io_addr(hcd, index); ++ temp = readl(addr); ++ temp = xhci_port_state_to_neutral(temp); ++ if (on) { ++ /* Power on */ ++ writel(temp | PORT_POWER, addr); ++ temp = readl(addr); ++ xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", ++ index, temp); ++ } else { ++ /* Power off */ ++ writel(temp & ~PORT_POWER, addr); ++ } ++ ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ temp = usb_acpi_power_manageable(hcd->self.root_hub, ++ index); ++ if (temp) ++ usb_acpi_set_power_state(hcd->self.root_hub, ++ index, on); ++ spin_lock_irqsave(&xhci->lock, flags); ++} ++ + void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, + int port_id, u32 link_state) + { +@@ -1092,18 +1135,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + * However, hub_wq will ignore the roothub events until + * the roothub is registered. + */ +- writel(temp | PORT_POWER, port_array[wIndex]); +- +- temp = readl(port_array[wIndex]); +- xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); +- +- spin_unlock_irqrestore(&xhci->lock, flags); +- temp = usb_acpi_power_manageable(hcd->self.root_hub, +- wIndex); +- if (temp) +- usb_acpi_set_power_state(hcd->self.root_hub, +- wIndex, true); +- spin_lock_irqsave(&xhci->lock, flags); ++ xhci_set_port_power(xhci, hcd, wIndex, true); + break; + case USB_PORT_FEAT_RESET: + temp = (temp | PORT_RESET); +@@ -1207,15 +1239,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + port_array[wIndex], temp); + break; + case USB_PORT_FEAT_POWER: +- writel(temp & ~PORT_POWER, port_array[wIndex]); +- +- spin_unlock_irqrestore(&xhci->lock, flags); +- temp = usb_acpi_power_manageable(hcd->self.root_hub, +- wIndex); +- if (temp) +- usb_acpi_set_power_state(hcd->self.root_hub, +- wIndex, false); +- spin_lock_irqsave(&xhci->lock, flags); ++ xhci_set_port_power(xhci, hcd, wIndex, false); + break; + default: + goto error; +-- +2.13.3 + diff --git a/patches.renesas/0179-usb-xhci-Add-helper-function-xhci_disable_slot.patch b/patches.renesas/0179-usb-xhci-Add-helper-function-xhci_disable_slot.patch new file mode 100644 index 00000000000000..df6f4d5e1ca1d5 --- /dev/null +++ b/patches.renesas/0179-usb-xhci-Add-helper-function-xhci_disable_slot.patch @@ -0,0 +1,126 @@ +From 77e05bb8ebc2487f8bd850acb5e383265364ca95 Mon Sep 17 00:00:00 2001 +From: Guoqing Zhang <guoqing.zhang@intel.com> +Date: Fri, 7 Apr 2017 17:56:52 +0300 +Subject: [PATCH 179/286] usb: xhci: Add helper function xhci_disable_slot(). + +Refactoring slot disable related code into a helper +function xhci_disable_slot() which can be used when +enabling test mode. + +Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit f9e609b82479ef48469d42b022b0951abc00dcd1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 49 +++++++++++++++++++++++++++++++------------------ + drivers/usb/host/xhci.h | 2 ++ + 2 files changed, 33 insertions(+), 18 deletions(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index cb3871c93004..ccd6f330ad38 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -3558,8 +3558,6 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct xhci_virt_device *virt_dev; +- unsigned long flags; +- u32 state; + int i, ret; + struct xhci_command *command; + +@@ -3594,30 +3592,50 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) + del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); + } + ++ xhci_disable_slot(xhci, command, udev->slot_id); ++ /* ++ * Event command completion handler will free any data structures ++ * associated with the slot. XXX Can free sleep? ++ */ ++} ++ ++int xhci_disable_slot(struct xhci_hcd *xhci, struct xhci_command *command, ++ u32 slot_id) ++{ ++ unsigned long flags; ++ u32 state; ++ int ret = 0; ++ struct xhci_virt_device *virt_dev; ++ ++ virt_dev = xhci->devs[slot_id]; ++ if (!virt_dev) ++ return -EINVAL; ++ if (!command) ++ command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); ++ if (!command) ++ return -ENOMEM; ++ + spin_lock_irqsave(&xhci->lock, flags); + /* Don't disable the slot if the host controller is dead. */ + state = readl(&xhci->op_regs->status); + if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || + (xhci->xhc_state & XHCI_STATE_HALTED)) { +- xhci_free_virt_device(xhci, udev->slot_id); ++ xhci_free_virt_device(xhci, slot_id); + spin_unlock_irqrestore(&xhci->lock, flags); + kfree(command); +- return; ++ return ret; + } + +- if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, +- udev->slot_id)) { ++ ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, ++ slot_id); ++ if (ret) { + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); +- return; ++ return ret; + } + xhci_ring_cmd_db(xhci); + spin_unlock_irqrestore(&xhci->lock, flags); +- +- /* +- * Event command completion handler will free any data structures +- * associated with the slot. XXX Can free sleep? +- */ ++ return ret; + } + + /* +@@ -3724,15 +3742,10 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) + + disable_slot: + /* Disable slot, if we can do it without mem alloc */ +- spin_lock_irqsave(&xhci->lock, flags); + kfree(command->completion); + command->completion = NULL; + command->status = 0; +- if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, +- udev->slot_id)) +- xhci_ring_cmd_db(xhci); +- spin_unlock_irqrestore(&xhci->lock, flags); +- return 0; ++ return xhci_disable_slot(xhci, command, udev->slot_id); + } + + /* +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 2496bd6304ca..e2eec806eafc 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2019,6 +2019,8 @@ void xhci_shutdown(struct usb_hcd *hcd); + int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); + void xhci_init_driver(struct hc_driver *drv, + const struct xhci_driver_overrides *over); ++int xhci_disable_slot(struct xhci_hcd *xhci, ++ struct xhci_command *command, u32 slot_id); + + #ifdef CONFIG_PM + int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); +-- +2.13.3 + diff --git a/patches.renesas/0180-usb-xhci-Expose-xhci_start-function.patch b/patches.renesas/0180-usb-xhci-Expose-xhci_start-function.patch new file mode 100644 index 00000000000000..1f67259dc08898 --- /dev/null +++ b/patches.renesas/0180-usb-xhci-Expose-xhci_start-function.patch @@ -0,0 +1,46 @@ +From 407c4183a2e2e2c535b18f5630a2f573aa9e4a7c Mon Sep 17 00:00:00 2001 +From: Guoqing Zhang <guoqing.zhang@intel.com> +Date: Fri, 7 Apr 2017 17:56:53 +0300 +Subject: [PATCH 180/286] usb: xhci: Expose xhci_start() function. + +Change the visability of xhci_start() so that it +can be used when enabling test mode. + +Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 26bba5c767de6724f330cdc2ad28bb783674f5a0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 2 +- + drivers/usb/host/xhci.h | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index ccd6f330ad38..0f9edee7bab3 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -125,7 +125,7 @@ int xhci_halt(struct xhci_hcd *xhci) + /* + * Set the run bit and wait for the host to be running. + */ +-static int xhci_start(struct xhci_hcd *xhci) ++int xhci_start(struct xhci_hcd *xhci) + { + u32 temp; + int ret; +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index e2eec806eafc..93e1dc1a6812 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2011,6 +2011,7 @@ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); + int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); + void xhci_quiesce(struct xhci_hcd *xhci); + int xhci_halt(struct xhci_hcd *xhci); ++int xhci_start(struct xhci_hcd *xhci); + int xhci_reset(struct xhci_hcd *xhci); + int xhci_init(struct usb_hcd *hcd); + int xhci_run(struct usb_hcd *hcd); +-- +2.13.3 + diff --git a/patches.renesas/0181-usb-xhci-Add-port-test-modes-support-for-usb2.patch b/patches.renesas/0181-usb-xhci-Add-port-test-modes-support-for-usb2.patch new file mode 100644 index 00000000000000..02c1831af57da0 --- /dev/null +++ b/patches.renesas/0181-usb-xhci-Add-port-test-modes-support-for-usb2.patch @@ -0,0 +1,180 @@ +From 3021ef9ba9976ecfde9527caace0ee50534191d2 Mon Sep 17 00:00:00 2001 +From: Guoqing Zhang <guoqing.zhang@intel.com> +Date: Fri, 7 Apr 2017 17:56:54 +0300 +Subject: [PATCH 181/286] usb: xhci: Add port test modes support for usb2. + +For usb2 ports, the port test mode Test_J_State, Test_K_State, +Test_Packet, Test_SE0_NAK and Test_Force_En can be enabled +as described in usb2 spec. + +USB2 test mode is a required hardware feature for system integrators +validating their hardware according to USB spec, regarding signal +strength and stuff. It is purely a hardware test feature. + +Usually you need an oscilloscope and have to enable those test modes on +the hardware. This will send some specific test patterns on D+/D-. There +is no report available (in Linux itself) as it is purely externally +visible. Regular USB usage is not possible at that time. +Anyone (well access to e.g. /dev/bus/usb/001/001 provided) can use it by +sending appropriate USB_PORT_FEAT_TEST requests to the hub. + +[Add better commit message by Alexander Stein -Mathias] +Signed-off-by: Guoqing Zhang <guoqing.zhang@intel.com> +Cc: Alexander Stein <alexander.stein@systec-electronic.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit 0f1d832ed1fb9527a4cc5fcb8511e85fd0a85185) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ + drivers/usb/host/xhci.h | 2 ++ + 2 files changed, 87 insertions(+) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index 04344c14180c..a0545fc367ca 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -583,6 +583,77 @@ static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, + spin_lock_irqsave(&xhci->lock, flags); + } + ++static void xhci_port_set_test_mode(struct xhci_hcd *xhci, ++ u16 test_mode, u16 wIndex) ++{ ++ u32 temp; ++ __le32 __iomem *addr; ++ ++ /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */ ++ addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex); ++ temp = readl(addr + PORTPMSC); ++ temp |= test_mode << PORT_TEST_MODE_SHIFT; ++ writel(temp, addr + PORTPMSC); ++ xhci->test_mode = test_mode; ++ if (test_mode == TEST_FORCE_EN) ++ xhci_start(xhci); ++} ++ ++static int xhci_enter_test_mode(struct xhci_hcd *xhci, ++ u16 test_mode, u16 wIndex) ++{ ++ int i, retval; ++ ++ /* Disable all Device Slots */ ++ xhci_dbg(xhci, "Disable all slots\n"); ++ for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { ++ retval = xhci_disable_slot(xhci, NULL, i); ++ if (retval) ++ xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", ++ i, retval); ++ } ++ /* Put all ports to the Disable state by clear PP */ ++ xhci_dbg(xhci, "Disable all port (PP = 0)\n"); ++ /* Power off USB3 ports*/ ++ for (i = 0; i < xhci->num_usb3_ports; i++) ++ xhci_set_port_power(xhci, xhci->shared_hcd, i, false); ++ /* Power off USB2 ports*/ ++ for (i = 0; i < xhci->num_usb2_ports; i++) ++ xhci_set_port_power(xhci, xhci->main_hcd, i, false); ++ /* Stop the controller */ ++ xhci_dbg(xhci, "Stop controller\n"); ++ retval = xhci_halt(xhci); ++ if (retval) ++ return retval; ++ /* Disable runtime PM for test mode */ ++ pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); ++ /* Set PORTPMSC.PTC field to enter selected test mode */ ++ /* Port is selected by wIndex. port_id = wIndex + 1 */ ++ xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", ++ test_mode, wIndex + 1); ++ xhci_port_set_test_mode(xhci, test_mode, wIndex); ++ return retval; ++} ++ ++static int xhci_exit_test_mode(struct xhci_hcd *xhci) ++{ ++ int retval; ++ ++ if (!xhci->test_mode) { ++ xhci_err(xhci, "Not in test mode, do nothing.\n"); ++ return 0; ++ } ++ if (xhci->test_mode == TEST_FORCE_EN && ++ !(xhci->xhc_state & XHCI_STATE_HALTED)) { ++ retval = xhci_halt(xhci); ++ if (retval) ++ return retval; ++ } ++ pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); ++ xhci->test_mode = 0; ++ return xhci_reset(xhci); ++} ++ + void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, + int port_id, u32 link_state) + { +@@ -938,6 +1009,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + u16 link_state = 0; + u16 wake_mask = 0; + u16 timeout = 0; ++ u16 test_mode = 0; + + max_ports = xhci_get_ports(hcd, &port_array); + bus_state = &xhci->bus_state[hcd_index(hcd)]; +@@ -1011,6 +1083,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + link_state = (wIndex & 0xff00) >> 3; + if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) + wake_mask = wIndex & 0xff00; ++ if (wValue == USB_PORT_FEAT_TEST) ++ test_mode = (wIndex & 0xff00) >> 8; + /* The MSB of wIndex is the U1/U2 timeout */ + timeout = (wIndex & 0xff00) >> 8; + wIndex &= 0xff; +@@ -1174,6 +1248,14 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + temp |= PORT_U2_TIMEOUT(timeout); + writel(temp, port_array[wIndex] + PORTPMSC); + break; ++ case USB_PORT_FEAT_TEST: ++ /* 4.19.6 Port Test Modes (USB2 Test Mode) */ ++ if (hcd->speed != HCD_USB2) ++ goto error; ++ if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) ++ goto error; ++ retval = xhci_enter_test_mode(xhci, test_mode, wIndex); ++ break; + default: + goto error; + } +@@ -1241,6 +1323,9 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + case USB_PORT_FEAT_POWER: + xhci_set_port_power(xhci, hcd, wIndex, false); + break; ++ case USB_PORT_FEAT_TEST: ++ retval = xhci_exit_test_mode(xhci); ++ break; + default: + goto error; + } +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 93e1dc1a6812..b65429aa6da4 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -425,6 +425,7 @@ struct xhci_op_regs { + #define PORT_L1DS_MASK (0xff << 8) + #define PORT_L1DS(p) (((p) & 0xff) << 8) + #define PORT_HLE (1 << 16) ++#define PORT_TEST_MODE_SHIFT 28 + + /* USB3 Protocol PORTLI Port Link Information */ + #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) +@@ -1844,6 +1845,7 @@ struct xhci_hcd { + /* Compliance Mode Recovery Data */ + struct timer_list comp_mode_recovery_timer; + u32 port_status_u0; ++ u16 test_mode; + /* Compliance Mode Timer Triggered every 2 seconds */ + #define COMP_MODE_RCVRY_MSECS 2000 + +-- +2.13.3 + diff --git a/patches.renesas/0182-usb-host-xhci-extract-xhci_slot_state_string.patch b/patches.renesas/0182-usb-host-xhci-extract-xhci_slot_state_string.patch new file mode 100644 index 00000000000000..5acce8fffff688 --- /dev/null +++ b/patches.renesas/0182-usb-host-xhci-extract-xhci_slot_state_string.patch @@ -0,0 +1,75 @@ +From d6bf529c90df506b55c22350b59230489e2e47f1 Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Fri, 7 Apr 2017 17:56:56 +0300 +Subject: [PATCH 182/286] usb: host: xhci: extract xhci_slot_state_string() + +By extracting and exposing xhci_slot_state_string() in a header file, we +can re-use it to print Slot Context State from our tracepoints, which +can aid in tracking down problems related to command execution. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 52407729fbeabb654d38c0c99661a41a481092d1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 14 ++------------ + drivers/usb/host/xhci.h | 16 ++++++++++++++++ + 2 files changed, 18 insertions(+), 12 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index 2b4a00fa735d..4cfdd51340d4 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -451,19 +451,9 @@ char *xhci_get_slot_state(struct xhci_hcd *xhci, + struct xhci_container_ctx *ctx) + { + struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); ++ int state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)); + +- switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) { +- case SLOT_STATE_ENABLED: +- return "enabled/disabled"; +- case SLOT_STATE_DEFAULT: +- return "default"; +- case SLOT_STATE_ADDRESSED: +- return "addressed"; +- case SLOT_STATE_CONFIGURED: +- return "configured"; +- default: +- return "reserved"; +- } ++ return xhci_slot_state_string(state); + } + + static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index b65429aa6da4..facdae3ea5bb 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2159,6 +2159,22 @@ static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, + urb->stream_id); + } + ++static inline char *xhci_slot_state_string(u32 state) ++{ ++ switch (state) { ++ case SLOT_STATE_ENABLED: ++ return "enabled/disabled"; ++ case SLOT_STATE_DEFAULT: ++ return "default"; ++ case SLOT_STATE_ADDRESSED: ++ return "addressed"; ++ case SLOT_STATE_CONFIGURED: ++ return "configured"; ++ default: ++ return "reserved"; ++ } ++} ++ + static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + u32 field3) + { +-- +2.13.3 + diff --git a/patches.renesas/0183-usb-host-xhci-add-Slot-and-EP-Context-tracers.patch b/patches.renesas/0183-usb-host-xhci-add-Slot-and-EP-Context-tracers.patch new file mode 100644 index 00000000000000..6a9b1c30f20bb1 --- /dev/null +++ b/patches.renesas/0183-usb-host-xhci-add-Slot-and-EP-Context-tracers.patch @@ -0,0 +1,503 @@ +From 48ecaf14091fa21627c3837d4488d166fe588fba Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Fri, 7 Apr 2017 17:56:57 +0300 +Subject: [PATCH 183/286] usb: host: xhci: add Slot and EP Context tracers + +With these, we can track what's happening with the HW while executing +each and every command. It will give us visibility into how the +different contexts are being modified by xHC which can bring insight +into problems while debugging. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 19a7d0d65c4a813069f4bc4ca701d6a163c337e9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 42 ++++++++++++ + drivers/usb/host/xhci-trace.h | 101 +++++++++++++++++++++++++++++ + drivers/usb/host/xhci.c | 15 ++++- + drivers/usb/host/xhci.h | 146 ++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 302 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index a3309aa02993..2f700c9893bd 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -689,6 +689,8 @@ static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, + struct xhci_virt_ep *ep; + struct xhci_td *cur_td = NULL; + struct xhci_td *last_unlinked_td; ++ struct xhci_ep_ctx *ep_ctx; ++ struct xhci_virt_device *vdev; + + struct xhci_dequeue_state deq_state; + +@@ -702,6 +704,11 @@ static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, + + memset(&deq_state, 0, sizeof(deq_state)); + ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); ++ ++ vdev = xhci->devs[slot_id]; ++ ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); ++ trace_xhci_handle_cmd_stop_ep(ep_ctx); ++ + ep = &xhci->devs[slot_id]->eps[ep_index]; + last_unlinked_td = list_last_entry(&ep->cancelled_td_list, + struct xhci_td, cancelled_td_list); +@@ -1029,6 +1036,8 @@ static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, + + ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); + slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); ++ trace_xhci_handle_cmd_set_deq(slot_ctx); ++ trace_xhci_handle_cmd_set_deq_ep(ep_ctx); + + if (cmd_comp_code != COMP_SUCCESS) { + unsigned int ep_state; +@@ -1099,9 +1108,15 @@ static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, + static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, + union xhci_trb *trb, u32 cmd_comp_code) + { ++ struct xhci_virt_device *vdev; ++ struct xhci_ep_ctx *ep_ctx; + unsigned int ep_index; + + ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); ++ vdev = xhci->devs[slot_id]; ++ ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); ++ trace_xhci_handle_cmd_reset_ep(ep_ctx); ++ + /* This command will only fail if the endpoint wasn't halted, + * but we don't care. + */ +@@ -1143,10 +1158,15 @@ static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, + static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) + { + struct xhci_virt_device *virt_dev; ++ struct xhci_slot_ctx *slot_ctx; + + virt_dev = xhci->devs[slot_id]; + if (!virt_dev) + return; ++ ++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); ++ trace_xhci_handle_cmd_disable_slot(slot_ctx); ++ + if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) + /* Delete default control endpoint resources */ + xhci_free_device_endpoint_resources(xhci, virt_dev, true); +@@ -1158,6 +1178,7 @@ static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, + { + struct xhci_virt_device *virt_dev; + struct xhci_input_control_ctx *ctrl_ctx; ++ struct xhci_ep_ctx *ep_ctx; + unsigned int ep_index; + unsigned int ep_state; + u32 add_flags, drop_flags; +@@ -1182,6 +1203,9 @@ static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, + /* Input ctx add_flags are the endpoint index plus one */ + ep_index = xhci_last_valid_endpoint(add_flags) - 1; + ++ ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); ++ trace_xhci_handle_cmd_config_ep(ep_ctx); ++ + /* A usb_set_interface() call directly after clearing a halted + * condition may race on this quirky hardware. Not worth + * worrying about, since this is prototype hardware. Not sure +@@ -1206,9 +1230,26 @@ static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, + return; + } + ++static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) ++{ ++ struct xhci_virt_device *vdev; ++ struct xhci_slot_ctx *slot_ctx; ++ ++ vdev = xhci->devs[slot_id]; ++ slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); ++ trace_xhci_handle_cmd_addr_dev(slot_ctx); ++} ++ + static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, + struct xhci_event_cmd *event) + { ++ struct xhci_virt_device *vdev; ++ struct xhci_slot_ctx *slot_ctx; ++ ++ vdev = xhci->devs[slot_id]; ++ slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); ++ trace_xhci_handle_cmd_reset_dev(slot_ctx); ++ + xhci_dbg(xhci, "Completed reset device command.\n"); + if (!xhci->devs[slot_id]) + xhci_warn(xhci, "Reset device command completion " +@@ -1384,6 +1425,7 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, + case TRB_EVAL_CONTEXT: + break; + case TRB_ADDR_DEV: ++ xhci_handle_cmd_addr_dev(xhci, slot_id); + break; + case TRB_STOP_RING: + WARN_ON(slot_id != TRB_TO_SLOT_ID( +diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h +index fecd226b422d..f24a45ae153d 100644 +--- a/drivers/usb/host/xhci-trace.h ++++ b/drivers/usb/host/xhci-trace.h +@@ -285,6 +285,107 @@ DEFINE_EVENT(xhci_log_urb, xhci_urb_dequeue, + TP_ARGS(urb) + ); + ++DECLARE_EVENT_CLASS(xhci_log_ep_ctx, ++ TP_PROTO(struct xhci_ep_ctx *ctx), ++ TP_ARGS(ctx), ++ TP_STRUCT__entry( ++ __field(u32, info) ++ __field(u32, info2) ++ __field(u64, deq) ++ __field(u32, tx_info) ++ ), ++ TP_fast_assign( ++ __entry->info = le32_to_cpu(ctx->ep_info); ++ __entry->info2 = le32_to_cpu(ctx->ep_info2); ++ __entry->deq = le64_to_cpu(ctx->deq); ++ __entry->tx_info = le32_to_cpu(ctx->tx_info); ++ ), ++ TP_printk("%s", xhci_decode_ep_context(__entry->info, ++ __entry->info2, __entry->deq, __entry->tx_info) ++ ) ++); ++ ++DEFINE_EVENT(xhci_log_ep_ctx, xhci_handle_cmd_stop_ep, ++ TP_PROTO(struct xhci_ep_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_ep_ctx, xhci_handle_cmd_set_deq_ep, ++ TP_PROTO(struct xhci_ep_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_ep_ctx, xhci_handle_cmd_reset_ep, ++ TP_PROTO(struct xhci_ep_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_ep_ctx, xhci_handle_cmd_config_ep, ++ TP_PROTO(struct xhci_ep_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DECLARE_EVENT_CLASS(xhci_log_slot_ctx, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx), ++ TP_STRUCT__entry( ++ __field(u32, info) ++ __field(u32, info2) ++ __field(u32, tt_info) ++ __field(u32, state) ++ ), ++ TP_fast_assign( ++ __entry->info = le32_to_cpu(ctx->dev_info); ++ __entry->info2 = le32_to_cpu(ctx->dev_info2); ++ __entry->tt_info = le64_to_cpu(ctx->tt_info); ++ __entry->state = le32_to_cpu(ctx->dev_state); ++ ), ++ TP_printk("%s", xhci_decode_slot_context(__entry->info, ++ __entry->info2, __entry->tt_info, ++ __entry->state) ++ ) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_alloc_dev, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_free_dev, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_disable_slot, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_discover_or_reset_device, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_setup_device_slot, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_addr_dev, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_reset_dev, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ ++DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_set_deq, ++ TP_PROTO(struct xhci_slot_ctx *ctx), ++ TP_ARGS(ctx) ++); ++ + #endif /* __XHCI_TRACE_H */ + + /* this part must be outside header guard */ +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 0f9edee7bab3..6c4cef7e51c9 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -3443,6 +3443,8 @@ int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) + SLOT_STATE_DISABLED) + return 0; + ++ trace_xhci_discover_or_reset_device(slot_ctx); ++ + xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); + /* Allocate the command structure that holds the struct completion. + * Assume we're in process context, since the normal device reset +@@ -3558,6 +3560,7 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct xhci_virt_device *virt_dev; ++ struct xhci_slot_ctx *slot_ctx; + int i, ret; + struct xhci_command *command; + +@@ -3585,6 +3588,8 @@ void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) + } + + virt_dev = xhci->devs[udev->slot_id]; ++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); ++ trace_xhci_free_dev(slot_ctx); + + /* Stop any wayward timer functions (which may grab the lock) */ + for (i = 0; i < 31; i++) { +@@ -3668,6 +3673,8 @@ static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) + int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ struct xhci_virt_device *vdev; ++ struct xhci_slot_ctx *slot_ctx; + unsigned long flags; + int ret, slot_id; + struct xhci_command *command; +@@ -3723,6 +3730,10 @@ int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) + xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); + goto disable_slot; + } ++ vdev = xhci->devs[slot_id]; ++ slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); ++ trace_xhci_alloc_dev(slot_ctx); ++ + udev->slot_id = slot_id; + + #ifndef CONFIG_USB_DEFAULT_PERSIST +@@ -3792,9 +3803,10 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + ret = -EINVAL; + goto out; + } ++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); ++ trace_xhci_setup_device_slot(slot_ctx); + + if (setup == SETUP_CONTEXT_ONLY) { +- slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); + if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == + SLOT_STATE_DEFAULT) { + xhci_dbg(xhci, "Slot already in default state\n"); +@@ -3915,7 +3927,6 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + * USB core uses address 1 for the roothubs, so we add one to the + * address given back to us by the HC. + */ +- slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); + trace_xhci_address_ctx(xhci, virt_dev->out_ctx, + le32_to_cpu(slot_ctx->dev_info) >> 27); + /* Zero the input context control for later use */ +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index facdae3ea5bb..2acb6fe64892 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -618,6 +618,7 @@ struct xhci_slot_ctx { + #define ROUTE_STRING_MASK (0xfffff) + /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ + #define DEV_SPEED (0xf << 20) ++#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) + /* bit 24 reserved */ + /* Is this LS/FS device connected through a HS hub? - bit 25 */ + #define DEV_MTT (0x1 << 25) +@@ -638,6 +639,7 @@ struct xhci_slot_ctx { + #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) + /* Maximum number of ports under a hub device */ + #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) ++#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) + + /* tt_info bitmasks */ + /* +@@ -652,6 +654,7 @@ struct xhci_slot_ctx { + */ + #define TT_PORT (0xff << 8) + #define TT_THINK_TIME(p) (((p) & 0x3) << 16) ++#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) + + /* dev_state bitmasks */ + /* USB device address - assigned by the HC */ +@@ -2381,5 +2384,148 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + return str; + } + ++static inline const char *xhci_decode_slot_context(u32 info, u32 info2, ++ u32 tt_info, u32 state) ++{ ++ static char str[1024]; ++ u32 speed; ++ u32 hub; ++ u32 mtt; ++ int ret = 0; ++ ++ speed = info & DEV_SPEED; ++ hub = info & DEV_HUB; ++ mtt = info & DEV_MTT; ++ ++ ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", ++ info & ROUTE_STRING_MASK, ++ ({ char *s; ++ switch (speed) { ++ case SLOT_SPEED_FS: ++ s = "full-speed"; ++ break; ++ case SLOT_SPEED_LS: ++ s = "low-speed"; ++ break; ++ case SLOT_SPEED_HS: ++ s = "high-speed"; ++ break; ++ case SLOT_SPEED_SS: ++ s = "super-speed"; ++ break; ++ case SLOT_SPEED_SSP: ++ s = "super-speed plus"; ++ break; ++ default: ++ s = "UNKNOWN speed"; ++ } s; }), ++ mtt ? " multi-TT" : "", ++ hub ? " Hub" : "", ++ (info & LAST_CTX_MASK) >> 27, ++ info2 & MAX_EXIT, ++ DEVINFO_TO_ROOT_HUB_PORT(info2), ++ DEVINFO_TO_MAX_PORTS(info2)); ++ ++ ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", ++ tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, ++ GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), ++ state & DEV_ADDR_MASK, ++ xhci_slot_state_string(GET_SLOT_STATE(state))); ++ ++ return str; ++} ++ ++static inline const char *xhci_ep_state_string(u8 state) ++{ ++ switch (state) { ++ case EP_STATE_DISABLED: ++ return "disabled"; ++ case EP_STATE_RUNNING: ++ return "running"; ++ case EP_STATE_HALTED: ++ return "halted"; ++ case EP_STATE_STOPPED: ++ return "stopped"; ++ case EP_STATE_ERROR: ++ return "error"; ++ default: ++ return "INVALID"; ++ } ++} ++ ++static inline const char *xhci_ep_type_string(u8 type) ++{ ++ switch (type) { ++ case ISOC_OUT_EP: ++ return "Isoc OUT"; ++ case BULK_OUT_EP: ++ return "Bulk OUT"; ++ case INT_OUT_EP: ++ return "Int OUT"; ++ case CTRL_EP: ++ return "Ctrl"; ++ case ISOC_IN_EP: ++ return "Isoc IN"; ++ case BULK_IN_EP: ++ return "Bulk IN"; ++ case INT_IN_EP: ++ return "Int IN"; ++ default: ++ return "INVALID"; ++ } ++} ++ ++static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, ++ u32 tx_info) ++{ ++ static char str[1024]; ++ int ret; ++ ++ u32 esit; ++ u16 maxp; ++ u16 avg; ++ ++ u8 max_pstr; ++ u8 ep_state; ++ u8 interval; ++ u8 ep_type; ++ u8 burst; ++ u8 cerr; ++ u8 mult; ++ u8 lsa; ++ u8 hid; ++ ++ esit = EP_MAX_ESIT_PAYLOAD_HI(info) << 16 | ++ EP_MAX_ESIT_PAYLOAD_LO(tx_info); ++ ++ ep_state = info & EP_STATE_MASK; ++ max_pstr = info & EP_MAXPSTREAMS_MASK; ++ interval = CTX_TO_EP_INTERVAL(info); ++ mult = CTX_TO_EP_MULT(info) + 1; ++ lsa = info & EP_HAS_LSA; ++ ++ cerr = (info2 & (3 << 1)) >> 1; ++ ep_type = CTX_TO_EP_TYPE(info2); ++ hid = info2 & (1 << 7); ++ burst = CTX_TO_MAX_BURST(info2); ++ maxp = MAX_PACKET_DECODED(info2); ++ ++ avg = EP_AVG_TRB_LENGTH(tx_info); ++ ++ ret = sprintf(str, "State %s mult %d max P. Streams %d %s", ++ xhci_ep_state_string(ep_state), mult, ++ max_pstr, lsa ? "LSA " : ""); ++ ++ ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", ++ (1 << interval) * 125, esit, cerr); ++ ++ ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", ++ xhci_ep_type_string(ep_type), hid ? "HID" : "", ++ burst, maxp, deq); ++ ++ ret += sprintf(str + ret, "avg trb len %d", avg); ++ ++ return str; ++} + + #endif /* __LINUX_XHCI_HCD_H */ +-- +2.13.3 + diff --git a/patches.renesas/0184-usb-host-xhci-fix-up-Control-Transfer-TRB-decoder.patch b/patches.renesas/0184-usb-host-xhci-fix-up-Control-Transfer-TRB-decoder.patch new file mode 100644 index 00000000000000..08f8aa3313c831 --- /dev/null +++ b/patches.renesas/0184-usb-host-xhci-fix-up-Control-Transfer-TRB-decoder.patch @@ -0,0 +1,93 @@ +From 3f5f8b07ba901696ac318c4f2014c5faa8e73d7b Mon Sep 17 00:00:00 2001 +From: Felipe Balbi <felipe.balbi@linux.intel.com> +Date: Fri, 7 Apr 2017 17:56:58 +0300 +Subject: [PATCH 184/286] usb: host: xhci: fix up Control Transfer TRB decoder + +Format for each TRB in each control transfer stage differs. Let's make +sure we correctly pretty print these fields to avoid confusion. + +Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5d062aba0d399c57e2d793603d6e372adb09b4d7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.h | 59 +++++++++++++++++++++++++++++++------------------ + 1 file changed, 37 insertions(+), 22 deletions(-) + +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 2acb6fe64892..82fce191b500 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2218,31 +2218,46 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + + break; + case TRB_SETUP: +- sprintf(str, +- "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", +- field0 & 0xff, +- (field0 & 0xff00) >> 8, +- (field0 & 0xff000000) >> 24, +- (field0 & 0xff0000) >> 16, +- (field1 & 0xff00) >> 8, +- field1 & 0xff, +- (field1 & 0xff000000) >> 16 | +- (field1 & 0xff0000) >> 16, +- TRB_LEN(field2), GET_TD_SIZE(field2), +- GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), +- field3 & TRB_BEI ? 'B' : 'b', +- field3 & TRB_IDT ? 'I' : 'i', +- field3 & TRB_IOC ? 'I' : 'i', +- field3 & TRB_CHAIN ? 'C' : 'c', +- field3 & TRB_NO_SNOOP ? 'S' : 's', +- field3 & TRB_ISP ? 'I' : 'i', +- field3 & TRB_ENT ? 'E' : 'e', +- field3 & TRB_CYCLE ? 'C' : 'c'); ++ sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", ++ field0 & 0xff, ++ (field0 & 0xff00) >> 8, ++ (field0 & 0xff000000) >> 24, ++ (field0 & 0xff0000) >> 16, ++ (field1 & 0xff00) >> 8, ++ field1 & 0xff, ++ (field1 & 0xff000000) >> 16 | ++ (field1 & 0xff0000) >> 16, ++ TRB_LEN(field2), GET_TD_SIZE(field2), ++ GET_INTR_TARGET(field2), ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_IDT ? 'I' : 'i', ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CYCLE ? 'C' : 'c'); + break; +- case TRB_NORMAL: + case TRB_DATA: ++ sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", ++ field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), ++ GET_INTR_TARGET(field2), ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_IDT ? 'I' : 'i', ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CHAIN ? 'C' : 'c', ++ field3 & TRB_NO_SNOOP ? 'S' : 's', ++ field3 & TRB_ISP ? 'I' : 'i', ++ field3 & TRB_ENT ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; + case TRB_STATUS: ++ sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", ++ field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), ++ GET_INTR_TARGET(field2), ++ xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CHAIN ? 'C' : 'c', ++ field3 & TRB_ENT ? 'E' : 'e', ++ field3 & TRB_CYCLE ? 'C' : 'c'); ++ break; ++ case TRB_NORMAL: + case TRB_ISOC: + case TRB_EVENT_DATA: + case TRB_TR_NOOP: +-- +2.13.3 + diff --git a/patches.renesas/0185-xhci-add-slot-and-endpoint-numbers-to-debug-messages.patch b/patches.renesas/0185-xhci-add-slot-and-endpoint-numbers-to-debug-messages.patch new file mode 100644 index 00000000000000..e867ef212d4430 --- /dev/null +++ b/patches.renesas/0185-xhci-add-slot-and-endpoint-numbers-to-debug-messages.patch @@ -0,0 +1,207 @@ +From c46ad5147130acb8a3088dc3c05a2a8d32fcf765 Mon Sep 17 00:00:00 2001 +From: Zhengjun Xing <zhengjun.xing@linux.intel.com> +Date: Fri, 7 Apr 2017 17:56:59 +0300 +Subject: [PATCH 185/286] xhci: add slot and endpoint numbers to debug messages + in handle_tx_event + +There's one annoyance in how xhci prints debug messages, we often +get logs with messages but it's hard to say from which device and +endpoint the message originates. Add slot_id, ep_index messages +in handle_tx_event. + +Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b7f769ae1b126086c5ec6686734924bac1dc0a9f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 80 ++++++++++++++++++++++++++++++-------------- + 1 file changed, 55 insertions(+), 25 deletions(-) + +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 2f700c9893bd..d45f533772ee 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2285,7 +2285,8 @@ static int handle_tx_event(struct xhci_hcd *xhci, + slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); + xdev = xhci->devs[slot_id]; + if (!xdev) { +- xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); ++ xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", ++ slot_id); + xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", + (unsigned long long) xhci_trb_virt_to_dma( + xhci->event_ring->deq_seg, +@@ -2305,8 +2306,9 @@ static int handle_tx_event(struct xhci_hcd *xhci, + ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); + ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); + if (!ep_ring || GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { +- xhci_err(xhci, "ERROR Transfer event for disabled endpoint " +- "or incorrect stream ring\n"); ++ xhci_err(xhci, ++ "ERROR Transfer event for disabled endpoint slot %u ep %u or incorrect stream ring\n", ++ slot_id, ep_index); + xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", + (unsigned long long) xhci_trb_virt_to_dma( + xhci->event_ring->deq_seg, +@@ -2340,45 +2342,62 @@ static int handle_tx_event(struct xhci_hcd *xhci, + trb_comp_code = COMP_SHORT_PACKET; + else + xhci_warn_ratelimited(xhci, +- "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); ++ "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", ++ slot_id, ep_index); + case COMP_SHORT_PACKET: + break; + case COMP_STOPPED: +- xhci_dbg(xhci, "Stopped on Transfer TRB\n"); ++ xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", ++ slot_id, ep_index); + break; + case COMP_STOPPED_LENGTH_INVALID: +- xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); ++ xhci_dbg(xhci, ++ "Stopped on No-op or Link TRB for slot %u ep %u\n", ++ slot_id, ep_index); + break; + case COMP_STOPPED_SHORT_PACKET: +- xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); ++ xhci_dbg(xhci, ++ "Stopped with short packet transfer detected for slot %u ep %u\n", ++ slot_id, ep_index); + break; + case COMP_STALL_ERROR: +- xhci_dbg(xhci, "Stalled endpoint\n"); ++ xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, ++ ep_index); + ep->ep_state |= EP_HALTED; + status = -EPIPE; + break; + case COMP_TRB_ERROR: +- xhci_warn(xhci, "WARN: TRB error on endpoint\n"); ++ xhci_warn(xhci, ++ "WARN: TRB error for slot %u ep %u on endpoint\n", ++ slot_id, ep_index); + status = -EILSEQ; + break; + case COMP_SPLIT_TRANSACTION_ERROR: + case COMP_USB_TRANSACTION_ERROR: +- xhci_dbg(xhci, "Transfer error on endpoint\n"); ++ xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", ++ slot_id, ep_index); + status = -EPROTO; + break; + case COMP_BABBLE_DETECTED_ERROR: +- xhci_dbg(xhci, "Babble error on endpoint\n"); ++ xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", ++ slot_id, ep_index); + status = -EOVERFLOW; + break; + case COMP_DATA_BUFFER_ERROR: +- xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); ++ xhci_warn(xhci, ++ "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", ++ slot_id, ep_index); + status = -ENOSR; + break; + case COMP_BANDWIDTH_OVERRUN_ERROR: +- xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); ++ xhci_warn(xhci, ++ "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", ++ slot_id, ep_index); + break; + case COMP_ISOCH_BUFFER_OVERRUN: +- xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); ++ xhci_warn(xhci, ++ "WARN: buffer overrun event for slot %u ep %u on endpoint", ++ slot_id, ep_index); + break; + case COMP_RING_UNDERRUN: + /* +@@ -2402,7 +2421,9 @@ static int handle_tx_event(struct xhci_hcd *xhci, + ep_index); + goto cleanup; + case COMP_INCOMPATIBLE_DEVICE_ERROR: +- xhci_warn(xhci, "WARN: detect an incompatible device"); ++ xhci_warn(xhci, ++ "WARN: detect an incompatible device for slot %u ep %u", ++ slot_id, ep_index); + status = -EPROTO; + break; + case COMP_MISSED_SERVICE_ERROR: +@@ -2413,19 +2434,24 @@ static int handle_tx_event(struct xhci_hcd *xhci, + * short transfer when process the ep_ring next time. + */ + ep->skip = true; +- xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); ++ xhci_dbg(xhci, ++ "Miss service interval error for slot %u ep %u, set skip flag\n", ++ slot_id, ep_index); + goto cleanup; + case COMP_NO_PING_RESPONSE_ERROR: + ep->skip = true; +- xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); ++ xhci_dbg(xhci, ++ "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", ++ slot_id, ep_index); + goto cleanup; + default: + if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { + status = 0; + break; + } +- xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", +- trb_comp_code); ++ xhci_warn(xhci, ++ "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", ++ trb_comp_code, slot_id, ep_index); + goto cleanup; + } + +@@ -2451,8 +2477,8 @@ static int handle_tx_event(struct xhci_hcd *xhci, + } + if (ep->skip) { + ep->skip = false; +- xhci_dbg(xhci, "td_list is empty while skip " +- "flag set. Clear skip flag.\n"); ++ xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", ++ slot_id, ep_index); + } + goto cleanup; + } +@@ -2460,8 +2486,8 @@ static int handle_tx_event(struct xhci_hcd *xhci, + /* We've skipped all the TDs on the ep ring when ep->skip set */ + if (ep->skip && td_num == 0) { + ep->skip = false; +- xhci_dbg(xhci, "All tds on the ep_ring skipped. " +- "Clear skip flag.\n"); ++ xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", ++ slot_id, ep_index); + goto cleanup; + } + +@@ -2520,7 +2546,9 @@ static int handle_tx_event(struct xhci_hcd *xhci, + ep_ring->last_td_was_short = false; + + if (ep->skip) { +- xhci_dbg(xhci, "Found td. Clear skip flag.\n"); ++ xhci_dbg(xhci, ++ "Found td. Clear skip flag for slot %u ep %u.\n", ++ slot_id, ep_index); + ep->skip = false; + } + +@@ -2537,7 +2565,9 @@ static int handle_tx_event(struct xhci_hcd *xhci, + * the TD. + */ + if (trb_is_noop(ep_trb)) { +- xhci_dbg(xhci, "ep_trb is a no-op TRB. Skip it\n"); ++ xhci_dbg(xhci, ++ "ep_trb is a no-op TRB. Skip it for slot %u ep %u\n", ++ slot_id, ep_index); + goto cleanup; + } + +-- +2.13.3 + diff --git a/patches.renesas/0186-xhci-Do-not-halt-the-host-until-both-HCD-have-discon.patch b/patches.renesas/0186-xhci-Do-not-halt-the-host-until-both-HCD-have-discon.patch new file mode 100644 index 00000000000000..de03157a813bc7 --- /dev/null +++ b/patches.renesas/0186-xhci-Do-not-halt-the-host-until-both-HCD-have-discon.patch @@ -0,0 +1,64 @@ +From c2e1abb35b37a2b46220ea0af7c8d70d8c09edf6 Mon Sep 17 00:00:00 2001 +From: Joel Stanley <joel@jms.id.au> +Date: Fri, 7 Apr 2017 17:57:00 +0300 +Subject: [PATCH 186/286] xhci: Do not halt the host until both HCD have + disconnected their devices. + +We can't halt the host controller immediately when first HCD is removed as +it will cause problems if we have devices attached to the second (primary) +HCD, like a keyboard. + +We've been carrying this in our Linux-as-a-bootloader environment for a +little while now. The machines all have the same TI TUSB73x0 part, +and when we kexec the devices don't come back until a system power cycle. + +[minor adjustments, code comments and remove HALT check -Mathias] +Signed-off-by: Joel Stanley <joel@jms.id.au> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> + +(cherry picked from commit fe190ed0d60260e44f48d8b0b04f26a8c8898a02) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 6c4cef7e51c9..8d8c02f4a3a6 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -689,21 +689,21 @@ void xhci_stop(struct usb_hcd *hcd) + + mutex_lock(&xhci->mutex); + +- if (!(xhci->xhc_state & XHCI_STATE_HALTED)) { +- spin_lock_irq(&xhci->lock); +- +- xhci->xhc_state |= XHCI_STATE_HALTED; +- xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; +- xhci_halt(xhci); +- xhci_reset(xhci); +- spin_unlock_irq(&xhci->lock); +- } +- ++ /* Only halt host and free memory after both hcds are removed */ + if (!usb_hcd_is_primary_hcd(hcd)) { ++ /* usb core will free this hcd shortly, unset pointer */ ++ xhci->shared_hcd = NULL; + mutex_unlock(&xhci->mutex); + return; + } + ++ spin_lock_irq(&xhci->lock); ++ xhci->xhc_state |= XHCI_STATE_HALTED; ++ xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; ++ xhci_halt(xhci); ++ xhci_reset(xhci); ++ spin_unlock_irq(&xhci->lock); ++ + xhci_cleanup_msix(xhci); + + /* Deleting Compliance Mode Recovery Timer */ +-- +2.13.3 + diff --git a/patches.renesas/0187-xhci-Rework-how-we-handle-unresponsive-or-hoptlug-re.patch b/patches.renesas/0187-xhci-Rework-how-we-handle-unresponsive-or-hoptlug-re.patch new file mode 100644 index 00000000000000..97b94a4f70f3e4 --- /dev/null +++ b/patches.renesas/0187-xhci-Rework-how-we-handle-unresponsive-or-hoptlug-re.patch @@ -0,0 +1,317 @@ +From e5442e57435a715f1ac56397b375bd38e67f7971 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:01 +0300 +Subject: [PATCH 187/286] xhci: Rework how we handle unresponsive or hoptlug + removed hosts + +Introduce a new xhci_hc_died() function that takes care of handling +pending commands and URBs if a host controller becomes unresponsive. + +This addresses issues on hotpluggable xhci controllers that disappear +from the bus suddenly, often while the bus (PCI) remove function is +still being processed. + +xhci_hc_died() sets a XHCI_STATUS_DYING flag to prevent new URBs and +commands or to be queued. The flag also ensures xhci_hc_died() will +give back pending commands and URBs once. + +Host is considered dead if register read returns 0xffffffff, or host +fails to abort the command ring, or fails stopping an endpoint after +trying for 5 seconds. + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d9f11ba9f107aa335091ab8d7ba5eea714e46e8b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 12 +++-- + drivers/usb/host/xhci-ring.c | 118 +++++++++++++++++++++---------------------- + drivers/usb/host/xhci.c | 16 +++++- + drivers/usb/host/xhci.h | 1 + + 4 files changed, 80 insertions(+), 67 deletions(-) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index a0545fc367ca..0b88e76251eb 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -1050,7 +1050,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + goto error; + wIndex--; + temp = readl(port_array[wIndex]); +- if (temp == 0xffffffff) { ++ if (temp == ~(u32)0) { ++ xhci_hc_died(xhci); + retval = -ENODEV; + break; + } +@@ -1092,7 +1093,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + goto error; + wIndex--; + temp = readl(port_array[wIndex]); +- if (temp == 0xffffffff) { ++ if (temp == ~(u32)0) { ++ xhci_hc_died(xhci); + retval = -ENODEV; + break; + } +@@ -1267,7 +1269,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + goto error; + wIndex--; + temp = readl(port_array[wIndex]); +- if (temp == 0xffffffff) { ++ if (temp == ~(u32)0) { ++ xhci_hc_died(xhci); + retval = -ENODEV; + break; + } +@@ -1378,7 +1381,8 @@ int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) + /* For each port, did anything change? If so, set that bit in buf. */ + for (i = 0; i < max_ports; i++) { + temp = readl(port_array[i]); +- if (temp == 0xffffffff) { ++ if (temp == ~(u32)0) { ++ xhci_hc_died(xhci); + retval = -ENODEV; + break; + } +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index d45f533772ee..c8910fd9b34c 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -359,21 +359,19 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) + xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, + &xhci->op_regs->cmd_ring); + +- /* Section 4.6.1.2 of xHCI 1.0 spec says software should +- * time the completion od all xHCI commands, including +- * the Command Abort operation. If software doesn't see +- * CRR negated in a timely manner (e.g. longer than 5 +- * seconds), then it should assume that the there are +- * larger problems with the xHC and assert HCRST. ++ /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the ++ * completion of the Command Abort operation. If CRR is not negated in 5 ++ * seconds then driver handles it as if host died (-ENODEV). ++ * In the future we should distinguish between -ENODEV and -ETIMEDOUT ++ * and try to recover a -ETIMEDOUT with a host controller reset. + */ + ret = xhci_handshake(&xhci->op_regs->cmd_ring, + CMD_RING_RUNNING, 0, 5 * 1000 * 1000); + if (ret < 0) { +- xhci_err(xhci, +- "Stop command ring failed, maybe the host is dead\n"); +- xhci->xhc_state |= XHCI_STATE_DYING; ++ xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); + xhci_halt(xhci); +- return -ESHUTDOWN; ++ xhci_hc_died(xhci); ++ return ret; + } + /* + * Writing the CMD_RING_ABORT bit should cause a cmd completion event, +@@ -873,6 +871,40 @@ static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, + } + } + ++/* ++ * host controller died, register read returns 0xffffffff ++ * Complete pending commands, mark them ABORTED. ++ * URBs need to be given back as usb core might be waiting with device locks ++ * held for the URBs to finish during device disconnect, blocking host remove. ++ * ++ * Call with xhci->lock held. ++ * lock is relased and re-acquired while giving back urb. ++ */ ++void xhci_hc_died(struct xhci_hcd *xhci) ++{ ++ int i, j; ++ ++ if (xhci->xhc_state & XHCI_STATE_DYING) ++ return; ++ ++ xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); ++ xhci->xhc_state |= XHCI_STATE_DYING; ++ ++ xhci_cleanup_command_queue(xhci); ++ ++ /* return any pending urbs, remove may be waiting for them */ ++ for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { ++ if (!xhci->devs[i]) ++ continue; ++ for (j = 0; j < 31; j++) ++ xhci_kill_endpoint_urbs(xhci, i, j); ++ } ++ ++ /* inform usb core hc died if PCI remove isn't already handling it */ ++ if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) ++ usb_hc_died(xhci_to_hcd(xhci)); ++} ++ + /* Watchdog timer function for when a stop endpoint command fails to complete. + * In this case, we assume the host controller is broken or dying or dead. The + * host may still be completing some other events, so we have to be careful to +@@ -894,7 +926,6 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg) + { + struct xhci_hcd *xhci; + struct xhci_virt_ep *ep; +- int ret, i, j; + unsigned long flags; + + ep = (struct xhci_virt_ep *) arg; +@@ -911,52 +942,22 @@ void xhci_stop_endpoint_command_watchdog(unsigned long arg) + } + + xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); +- xhci_warn(xhci, "Assuming host is dying, halting host.\n"); +- /* Oops, HC is dead or dying or at least not responding to the stop +- * endpoint command. +- */ +- +- xhci->xhc_state |= XHCI_STATE_DYING; + ep->ep_state &= ~EP_STOP_CMD_PENDING; + +- /* Disable interrupts from the host controller and start halting it */ +- xhci_quiesce(xhci); +- spin_unlock_irqrestore(&xhci->lock, flags); ++ xhci_halt(xhci); + +- ret = xhci_halt(xhci); ++ /* ++ * handle a stop endpoint cmd timeout as if host died (-ENODEV). ++ * In the future we could distinguish between -ENODEV and -ETIMEDOUT ++ * and try to recover a -ETIMEDOUT with a host controller reset ++ */ ++ xhci_hc_died(xhci); + +- spin_lock_irqsave(&xhci->lock, flags); +- if (ret < 0) { +- /* This is bad; the host is not responding to commands and it's +- * not allowing itself to be halted. At least interrupts are +- * disabled. If we call usb_hc_died(), it will attempt to +- * disconnect all device drivers under this host. Those +- * disconnect() methods will wait for all URBs to be unlinked, +- * so we must complete them. +- */ +- xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); +- xhci_warn(xhci, "Completing active URBs anyway.\n"); +- /* We could turn all TDs on the rings to no-ops. This won't +- * help if the host has cached part of the ring, and is slow if +- * we want to preserve the cycle bit. Skip it and hope the host +- * doesn't touch the memory. +- */ +- } +- for (i = 0; i < MAX_HC_SLOTS; i++) { +- if (!xhci->devs[i]) +- continue; +- for (j = 0; j < 31; j++) +- xhci_kill_endpoint_urbs(xhci, i, j); +- } + spin_unlock_irqrestore(&xhci->lock, flags); + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, +- "Calling usb_hc_died()"); +- usb_hc_died(xhci_to_hcd(xhci)); +- xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, + "xHCI host controller is dead."); + } + +- + static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, + struct xhci_virt_device *dev, + struct xhci_ring *ep_ring, +@@ -1291,7 +1292,6 @@ void xhci_cleanup_command_queue(struct xhci_hcd *xhci) + void xhci_handle_command_timeout(struct work_struct *work) + { + struct xhci_hcd *xhci; +- int ret; + unsigned long flags; + u64 hw_ring_state; + +@@ -1312,22 +1312,17 @@ void xhci_handle_command_timeout(struct work_struct *work) + + /* Make sure command ring is running before aborting it */ + hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); ++ if (hw_ring_state == ~(u64)0) { ++ xhci_hc_died(xhci); ++ goto time_out_completed; ++ } ++ + if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && + (hw_ring_state & CMD_RING_RUNNING)) { + /* Prevent new doorbell, and start command abort */ + xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; + xhci_dbg(xhci, "Command timeout\n"); +- ret = xhci_abort_cmd_ring(xhci, flags); +- if (unlikely(ret == -ESHUTDOWN)) { +- xhci_err(xhci, "Abort command ring failed\n"); +- xhci_cleanup_command_queue(xhci); +- spin_unlock_irqrestore(&xhci->lock, flags); +- usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); +- xhci_dbg(xhci, "xHCI host controller is dead.\n"); +- +- return; +- } +- ++ xhci_abort_cmd_ring(xhci, flags); + goto time_out_completed; + } + +@@ -2695,7 +2690,8 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) + spin_lock(&xhci->lock); + /* Check if the xHC generated the interrupt, or the irq is shared */ + status = readl(&xhci->op_regs->status); +- if (status == 0xffffffff) { ++ if (status == ~(u32)0) { ++ xhci_hc_died(xhci); + ret = IRQ_HANDLED; + goto out; + } +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 8d8c02f4a3a6..388bf2f1b661 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1501,10 +1501,16 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + if (!ep || !ep_ring) + goto err_giveback; + ++ /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */ + temp = readl(&xhci->op_regs->status); +- if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { ++ if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) { ++ xhci_hc_died(xhci); ++ goto done; ++ } ++ ++ if (xhci->xhc_state & XHCI_STATE_HALTED) { + xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, +- "HW died, freeing TD."); ++ "HC halted, freeing TD manually."); + for (i = urb_priv->num_tds_done; + i < urb_priv->num_tds; + i++) { +@@ -2595,6 +2601,12 @@ static int xhci_configure_endpoint(struct xhci_hcd *xhci, + return -EINVAL; + + spin_lock_irqsave(&xhci->lock, flags); ++ ++ if (xhci->xhc_state & XHCI_STATE_DYING) { ++ spin_unlock_irqrestore(&xhci->lock, flags); ++ return -ESHUTDOWN; ++ } ++ + virt_dev = xhci->devs[udev->slot_id]; + + ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 82fce191b500..9e24d2890b4d 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2132,6 +2132,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, + char *buf, u16 wLength); + int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); + int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); ++void xhci_hc_died(struct xhci_hcd *xhci); + + #ifdef CONFIG_PM + int xhci_bus_suspend(struct usb_hcd *hcd); +-- +2.13.3 + diff --git a/patches.renesas/0188-usb-xhci-add-xhci_log_ring-trace-events.patch b/patches.renesas/0188-usb-xhci-add-xhci_log_ring-trace-events.patch new file mode 100644 index 00000000000000..ccb11efa8a2593 --- /dev/null +++ b/patches.renesas/0188-usb-xhci-add-xhci_log_ring-trace-events.patch @@ -0,0 +1,159 @@ +From 200abe368c59bdfe1fce263d7700e04efb0b7ef3 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:02 +0300 +Subject: [PATCH 188/286] usb: xhci: add xhci_log_ring trace events + +This patch creates a new event class called xhci_log_ring, and +defines the events used for tracing the change of all kinds of +rings used by an xhci host. An xHCI ring is basically a memory +block shared between software and hardware. By tracing changes +of rings, it makes the life easier for debugging hardware or +software problems. + +This info can be used, later, to print, in a human readable way, +the life cycle of an xHCI ring using the trace-cmd tool and the +appropriate plugin. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Reviewed-by: Felipe Balbi <felipe.balbi@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b2d6edbb95487e90ffc22072879b0865ccb89a80) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 4 +++ + drivers/usb/host/xhci-ring.c | 5 ++++ + drivers/usb/host/xhci-trace.h | 65 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 74 insertions(+) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 4f28cfebe302..3fc323b92cc8 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -288,6 +288,8 @@ void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) + if (!ring) + return; + ++ trace_xhci_ring_free(ring); ++ + if (ring->first_seg) { + if (ring->type == TYPE_STREAM) + xhci_remove_stream_mapping(ring); +@@ -400,6 +402,7 @@ static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, + cpu_to_le32(LINK_TOGGLE); + } + xhci_initialize_ring_info(ring, cycle_state); ++ trace_xhci_ring_alloc(ring); + return ring; + + fail: +@@ -504,6 +507,7 @@ int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, + } + + xhci_link_rings(xhci, ring, first, last, num_segs); ++ trace_xhci_ring_expansion(ring); + xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, + "ring expansion succeed, now has %d segments", + ring->num_segs); +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index c8910fd9b34c..28ea69338ed1 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -191,6 +191,9 @@ static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) + ring->deq_seg = ring->deq_seg->next; + ring->dequeue = ring->deq_seg->trbs; + } ++ ++ trace_xhci_inc_deq(ring); ++ + return; + } + +@@ -259,6 +262,8 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, + ring->enqueue = ring->enq_seg->trbs; + next = ring->enqueue; + } ++ ++ trace_xhci_inc_enq(ring); + } + + /* +diff --git a/drivers/usb/host/xhci-trace.h b/drivers/usb/host/xhci-trace.h +index f24a45ae153d..3c14b9e27c49 100644 +--- a/drivers/usb/host/xhci-trace.h ++++ b/drivers/usb/host/xhci-trace.h +@@ -386,6 +386,71 @@ DEFINE_EVENT(xhci_log_slot_ctx, xhci_handle_cmd_set_deq, + TP_ARGS(ctx) + ); + ++DECLARE_EVENT_CLASS(xhci_log_ring, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring), ++ TP_STRUCT__entry( ++ __field(u32, type) ++ __field(void *, ring) ++ __field(dma_addr_t, enq) ++ __field(dma_addr_t, deq) ++ __field(dma_addr_t, enq_seg) ++ __field(dma_addr_t, deq_seg) ++ __field(unsigned int, num_segs) ++ __field(unsigned int, stream_id) ++ __field(unsigned int, cycle_state) ++ __field(unsigned int, num_trbs_free) ++ __field(unsigned int, bounce_buf_len) ++ ), ++ TP_fast_assign( ++ __entry->ring = ring; ++ __entry->type = ring->type; ++ __entry->num_segs = ring->num_segs; ++ __entry->stream_id = ring->stream_id; ++ __entry->enq_seg = ring->enq_seg->dma; ++ __entry->deq_seg = ring->deq_seg->dma; ++ __entry->cycle_state = ring->cycle_state; ++ __entry->num_trbs_free = ring->num_trbs_free; ++ __entry->bounce_buf_len = ring->bounce_buf_len; ++ __entry->enq = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); ++ __entry->deq = xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); ++ ), ++ TP_printk("%s %p: enq %pad(%pad) deq %pad(%pad) segs %d stream %d free_trbs %d bounce %d cycle %d", ++ xhci_ring_type_string(__entry->type), __entry->ring, ++ &__entry->enq, &__entry->enq_seg, ++ &__entry->deq, &__entry->deq_seg, ++ __entry->num_segs, ++ __entry->stream_id, ++ __entry->num_trbs_free, ++ __entry->bounce_buf_len, ++ __entry->cycle_state ++ ) ++); ++ ++DEFINE_EVENT(xhci_log_ring, xhci_ring_alloc, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring) ++); ++ ++DEFINE_EVENT(xhci_log_ring, xhci_ring_free, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring) ++); ++ ++DEFINE_EVENT(xhci_log_ring, xhci_ring_expansion, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring) ++); ++ ++DEFINE_EVENT(xhci_log_ring, xhci_inc_enq, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring) ++); ++ ++DEFINE_EVENT(xhci_log_ring, xhci_inc_deq, ++ TP_PROTO(struct xhci_ring *ring), ++ TP_ARGS(ring) ++); + #endif /* __XHCI_TRACE_H */ + + /* this part must be outside header guard */ +-- +2.13.3 + diff --git a/patches.renesas/0189-usb-xhci-remove-xhci_dbg_ep_rings.patch b/patches.renesas/0189-usb-xhci-remove-xhci_dbg_ep_rings.patch new file mode 100644 index 00000000000000..54b03f0014f3af --- /dev/null +++ b/patches.renesas/0189-usb-xhci-remove-xhci_dbg_ep_rings.patch @@ -0,0 +1,70 @@ +From 3c08379f5b4a56f27173a64e2179d5557ae5462f Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:03 +0300 +Subject: [PATCH 189/286] usb: xhci: remove xhci_dbg_ep_rings() + +xhci_dbg_ep_rings() isn't used in xhci driver anymore. Remove +it to reduce the module binary size. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b7d09fe863561014085503986cb202f4111be347) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 24 ------------------------ + drivers/usb/host/xhci.h | 3 --- + 2 files changed, 27 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index 4cfdd51340d4..f6d30314348d 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -381,30 +381,6 @@ void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring) + xhci_debug_segment(xhci, seg); + } + +-void xhci_dbg_ep_rings(struct xhci_hcd *xhci, +- unsigned int slot_id, unsigned int ep_index, +- struct xhci_virt_ep *ep) +-{ +- int i; +- struct xhci_ring *ring; +- +- if (ep->ep_state & EP_HAS_STREAMS) { +- for (i = 1; i < ep->stream_info->num_streams; i++) { +- ring = ep->stream_info->stream_rings[i]; +- xhci_dbg(xhci, "Dev %d endpoint %d stream ID %d:\n", +- slot_id, ep_index, i); +- xhci_debug_segment(xhci, ring->deq_seg); +- } +- } else { +- ring = ep->ring; +- if (!ring) +- return; +- xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", +- slot_id, ep_index); +- xhci_debug_segment(xhci, ring->deq_seg); +- } +-} +- + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) + { + u64 addr = erst->erst_dma_addr; +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 9e24d2890b4d..f5ed359ad8e9 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1934,9 +1934,6 @@ void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); + void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); + char *xhci_get_slot_state(struct xhci_hcd *xhci, + struct xhci_container_ctx *ctx); +-void xhci_dbg_ep_rings(struct xhci_hcd *xhci, +- unsigned int slot_id, unsigned int ep_index, +- struct xhci_virt_ep *ep); + void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), + const char *fmt, ...); + +-- +2.13.3 + diff --git a/patches.renesas/0190-usb-xhci-make-several-functions-static.patch b/patches.renesas/0190-usb-xhci-make-several-functions-static.patch new file mode 100644 index 00000000000000..f117db15952ce1 --- /dev/null +++ b/patches.renesas/0190-usb-xhci-make-several-functions-static.patch @@ -0,0 +1,367 @@ +From ccd1c25032c5707877cc11c2925debaa0c58adee Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:04 +0300 +Subject: [PATCH 190/286] usb: xhci: make several functions static + +Several functions have a single user in the same file where it +is defined. There's no need to expose it anywhere else. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 3969384cf88aa2726afb05ad5d1c6ec27e670f07) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.c | 59 +++++++++++++++++++++++++------------------------ + drivers/usb/host/xhci.h | 41 ---------------------------------- + 2 files changed, 30 insertions(+), 70 deletions(-) + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 388bf2f1b661..7867b2d3b693 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -539,7 +539,7 @@ static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) + * device contexts (?), set up a command ring segment (or two?), create event + * ring (one for now). + */ +-int xhci_init(struct usb_hcd *hcd) ++static int xhci_init(struct usb_hcd *hcd) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + int retval = 0; +@@ -682,7 +682,7 @@ EXPORT_SYMBOL_GPL(xhci_run); + * Disable device contexts, disable IRQs, and quiesce the HC. + * Reset the HC, finish any completed transactions, and cleanup memory. + */ +-void xhci_stop(struct usb_hcd *hcd) ++static void xhci_stop(struct usb_hcd *hcd) + { + u32 temp; + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -743,7 +743,7 @@ void xhci_stop(struct usb_hcd *hcd) + * + * This will only ever be called with the main usb_hcd (the USB3 roothub). + */ +-void xhci_shutdown(struct usb_hcd *hcd) ++static void xhci_shutdown(struct usb_hcd *hcd) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + +@@ -1176,7 +1176,7 @@ unsigned int xhci_get_endpoint_address(unsigned int ep_index) + * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is + * bit 1, etc. + */ +-unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) ++static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) + { + return 1 << (xhci_get_endpoint_index(desc) + 1); + } +@@ -1185,7 +1185,7 @@ unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) + * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is + * bit 1, etc. + */ +-unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) ++static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) + { + return 1 << (ep_index + 1); + } +@@ -1329,7 +1329,7 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, + * non-error returns are a promise to giveback() the urb later + * we drop ownership so next owner (or urb unlink) can get it + */ +-int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) ++static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + unsigned long flags; +@@ -1465,7 +1465,7 @@ int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) + * Note that this function can be called in any context, or so says + * usb_hcd_unlink_urb() + */ +-int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + { + unsigned long flags; + int ret, i; +@@ -1582,7 +1582,7 @@ int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + * disabled, so there's no need for mutual exclusion to protect + * the xhci->devs[slot_id] structure. + */ +-int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, ++static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, + struct usb_host_endpoint *ep) + { + struct xhci_hcd *xhci; +@@ -1665,7 +1665,7 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, + * configuration or alt setting is installed in the device, so there's no need + * for mutual exclusion to protect the xhci->devs[slot_id] structure. + */ +-int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, ++static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, + struct usb_host_endpoint *ep) + { + struct xhci_hcd *xhci; +@@ -2336,7 +2336,7 @@ static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) + + } + +-void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, ++static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, + struct xhci_bw_info *ep_bw, + struct xhci_interval_bw_table *bw_table, + struct usb_device *udev, +@@ -2701,7 +2701,7 @@ static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, + * else should be touching the xhci->devs[slot_id] structure, so we + * don't need to take the xhci->lock for manipulating that. + */ +-int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) + { + int i; + int ret = 0; +@@ -2805,7 +2805,7 @@ int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) + return ret; + } + +-void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) ++static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci; + struct xhci_virt_device *virt_dev; +@@ -2931,7 +2931,7 @@ void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, + * Context: in_interrupt + */ + +-void xhci_endpoint_reset(struct usb_hcd *hcd, ++static void xhci_endpoint_reset(struct usb_hcd *hcd, + struct usb_host_endpoint *ep) + { + struct xhci_hcd *xhci; +@@ -3107,7 +3107,7 @@ static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, + * hardware or endpoints claim they can't support the number of requested + * stream IDs. + */ +-int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, ++static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, + struct usb_host_endpoint **eps, unsigned int num_eps, + unsigned int num_streams, gfp_t mem_flags) + { +@@ -3271,7 +3271,7 @@ int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, + * Modify the endpoint context state, submit a configure endpoint command, + * and free all endpoint rings for streams if that completes successfully. + */ +-int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, ++static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, + struct usb_host_endpoint **eps, unsigned int num_eps, + gfp_t mem_flags) + { +@@ -3403,7 +3403,8 @@ void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, + * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to + * re-allocate the device. + */ +-int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_discover_or_reset_device(struct usb_hcd *hcd, ++ struct usb_device *udev) + { + int ret, i; + unsigned long flags; +@@ -3568,7 +3569,7 @@ int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) + * disconnected, and all traffic has been stopped and the endpoints have been + * disabled. Free any HC data structures associated with that device. + */ +-void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) ++static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct xhci_virt_device *virt_dev; +@@ -3957,12 +3958,12 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + return ret; + } + +-int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) + { + return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); + } + +-int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) + { + return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); + } +@@ -4119,7 +4120,7 @@ static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) + return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); + } + +-int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, ++static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, + struct usb_device *udev, int enable) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -4243,7 +4244,7 @@ static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, + return 0; + } + +-int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + int portnum = udev->portnum - 1; +@@ -4652,7 +4653,7 @@ static int calculate_max_exit_latency(struct usb_device *udev, + } + + /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ +-int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, ++static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, + struct usb_device *udev, enum usb3_link_state state) + { + struct xhci_hcd *xhci; +@@ -4683,7 +4684,7 @@ int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, + return hub_encoded_timeout; + } + +-int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, ++static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, + struct usb_device *udev, enum usb3_link_state state) + { + struct xhci_hcd *xhci; +@@ -4699,24 +4700,24 @@ int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, + } + #else /* CONFIG_PM */ + +-int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, ++static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, + struct usb_device *udev, int enable) + { + return 0; + } + +-int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) ++static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) + { + return 0; + } + +-int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, ++static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, + struct usb_device *udev, enum usb3_link_state state) + { + return USB3_LPM_DISABLED; + } + +-int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, ++static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, + struct usb_device *udev, enum usb3_link_state state) + { + return 0; +@@ -4728,7 +4729,7 @@ int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, + /* Once a hub descriptor is fetched for a device, we need to update the xHC's + * internal data structures for the device. + */ +-int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, ++static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, + struct usb_tt *tt, gfp_t mem_flags) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -4834,7 +4835,7 @@ int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, + return ret; + } + +-int xhci_get_frame(struct usb_hcd *hcd) ++static int xhci_get_frame(struct usb_hcd *hcd) + { + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + /* EHCI mods by the periodic size. Why? */ +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index f5ed359ad8e9..8b360f60d81e 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1947,16 +1947,8 @@ void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, + struct usb_device *udev); + unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); + unsigned int xhci_get_endpoint_address(unsigned int ep_index); +-unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); +-unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); + unsigned int xhci_last_valid_endpoint(u32 added_ctxs); + void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); +-void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, +- struct xhci_bw_info *ep_bw, +- struct xhci_interval_bw_table *bw_table, +- struct usb_device *udev, +- struct xhci_virt_ep *virt_ep, +- struct xhci_tt_bw_info *tt_info); + void xhci_update_tt_active_eps(struct xhci_hcd *xhci, + struct xhci_virt_device *virt_dev, + int old_active_eps); +@@ -2015,10 +2007,7 @@ void xhci_quiesce(struct xhci_hcd *xhci); + int xhci_halt(struct xhci_hcd *xhci); + int xhci_start(struct xhci_hcd *xhci); + int xhci_reset(struct xhci_hcd *xhci); +-int xhci_init(struct usb_hcd *hcd); + int xhci_run(struct usb_hcd *hcd); +-void xhci_stop(struct usb_hcd *hcd); +-void xhci_shutdown(struct usb_hcd *hcd); + int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); + void xhci_init_driver(struct hc_driver *drv, + const struct xhci_driver_overrides *over); +@@ -2033,36 +2022,13 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated); + #define xhci_resume NULL + #endif + +-int xhci_get_frame(struct usb_hcd *hcd); + irqreturn_t xhci_irq(struct usb_hcd *hcd); + irqreturn_t xhci_msi_irq(int irq, void *hcd); + int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); +-void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); + int xhci_alloc_tt_info(struct xhci_hcd *xhci, + struct xhci_virt_device *virt_dev, + struct usb_device *hdev, + struct usb_tt *tt, gfp_t mem_flags); +-int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, +- struct usb_host_endpoint **eps, unsigned int num_eps, +- unsigned int num_streams, gfp_t mem_flags); +-int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, +- struct usb_host_endpoint **eps, unsigned int num_eps, +- gfp_t mem_flags); +-int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); +-int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); +-int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); +-int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, +- struct usb_device *udev, int enable); +-int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, +- struct usb_tt *tt, gfp_t mem_flags); +-int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); +-int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); +-int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); +-int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); +-void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); +-int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); +-int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); +-void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); + + /* xHCI ring, segment, TRB, and TD functions */ + dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); +@@ -2106,9 +2072,6 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, + struct xhci_dequeue_state *deq_state); + void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, + unsigned int ep_index, struct xhci_td *td); +-void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, +- unsigned int slot_id, unsigned int ep_index, +- struct xhci_dequeue_state *deq_state); + void xhci_stop_endpoint_command_watchdog(unsigned long arg); + void xhci_handle_command_timeout(struct work_struct *work); + +@@ -2119,10 +2082,6 @@ void xhci_cleanup_command_queue(struct xhci_hcd *xhci); + /* xHCI roothub code */ + void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, + int port_id, u32 link_state); +-int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, +- struct usb_device *udev, enum usb3_link_state state); +-int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, +- struct usb_device *udev, enum usb3_link_state state); + void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, + int port_id, u32 port_bit); + int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, +-- +2.13.3 + diff --git a/patches.renesas/0191-usb-xhci-remove-error-messages-for-failed-memory-all.patch b/patches.renesas/0191-usb-xhci-remove-error-messages-for-failed-memory-all.patch new file mode 100644 index 00000000000000..e0c607acfe24c8 --- /dev/null +++ b/patches.renesas/0191-usb-xhci-remove-error-messages-for-failed-memory-all.patch @@ -0,0 +1,126 @@ +From ecc072c0aa5f3cc28ab1f8b14c57a8b138394bfa Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:05 +0300 +Subject: [PATCH 191/286] usb: xhci: remove error messages for failed memory + allocation + +Omit extra messages for memory allocation failure. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 74e0b5649c26428a4b87f496cef0df8307eff364) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 4 +--- + drivers/usb/host/xhci-mem.c | 1 - + drivers/usb/host/xhci-ring.c | 10 ++++------ + drivers/usb/host/xhci.c | 13 +++++++------ + 4 files changed, 12 insertions(+), 16 deletions(-) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index 0b88e76251eb..ab818bd5d0ac 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -392,10 +392,8 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) + trace_xhci_stop_device(virt_dev); + + cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); +- if (!cmd) { +- xhci_dbg(xhci, "Couldn't allocate command structure.\n"); ++ if (!cmd) + return -ENOMEM; +- } + + spin_lock_irqsave(&xhci->lock, flags); + for (i = LAST_EP_INDEX; i > 0; i--) { +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 3fc323b92cc8..e2e27a332e9a 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -2619,7 +2619,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + return 0; + + fail: +- xhci_warn(xhci, "Couldn't initialize memory\n"); + xhci_halt(xhci); + xhci_reset(xhci); + xhci_mem_cleanup(xhci); +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 28ea69338ed1..deb318e0c679 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1135,11 +1135,11 @@ static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, + */ + if (xhci->quirks & XHCI_RESET_EP_QUIRK) { + struct xhci_command *command; ++ + command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); +- if (!command) { +- xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); ++ if (!command) + return; +- } ++ + xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, + "Queueing configure endpoint command"); + xhci_queue_configure_endpoint(xhci, command, +@@ -4015,10 +4015,8 @@ void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, + + /* This function gets called from contexts where it cannot sleep */ + cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); +- if (!cmd) { +- xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); ++ if (!cmd) + return; +- } + + ep->queued_deq_seg = deq_state->new_deq_seg; + ep->queued_deq_ptr = deq_state->new_deq_ptr; +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 7867b2d3b693..e0392564ed33 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -661,9 +661,11 @@ int xhci_run(struct usb_hcd *hcd) + + if (xhci->quirks & XHCI_NEC_HOST) { + struct xhci_command *command; ++ + command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); + if (!command) + return -ENOMEM; ++ + xhci_queue_vendor_command(xhci, command, 0, 0, 0, + TRB_TYPE(TRB_NEC_GET_FW)); + } +@@ -3141,10 +3143,9 @@ static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, + } + + config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); +- if (!config_cmd) { +- xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); ++ if (!config_cmd) + return -ENOMEM; +- } ++ + ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); + if (!ctrl_ctx) { + xhci_warn(xhci, "%s: Could not get input context, bad type.\n", +@@ -4750,11 +4751,11 @@ static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, + xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); + return -EINVAL; + } ++ + config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); +- if (!config_cmd) { +- xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); ++ if (!config_cmd) + return -ENOMEM; +- } ++ + ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); + if (!ctrl_ctx) { + xhci_warn(xhci, "%s: Could not get input context, bad type.\n", +-- +2.13.3 + diff --git a/patches.renesas/0192-usb-xhci-remove-enq_updates-and-deq_updates-from-rin.patch b/patches.renesas/0192-usb-xhci-remove-enq_updates-and-deq_updates-from-rin.patch new file mode 100644 index 00000000000000..94ab3faf582c37 --- /dev/null +++ b/patches.renesas/0192-usb-xhci-remove-enq_updates-and-deq_updates-from-rin.patch @@ -0,0 +1,107 @@ +From 3785f93447efda502d8ace0118e23959d18d38c5 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:06 +0300 +Subject: [PATCH 192/286] usb: xhci: remove enq_updates and deq_updates from + ring + +enq_updates and deq_updates were introduced in the first place +to check whether an xhci hardware is able to respond to trbs +enqueued in the ring. We now have trb tracers to trace every +single enqueue/dequeue trb. It's time to remove them and the +associated debugging code. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit cd12fd9f6d05d1b2b9ff2630802c55b5fd2e534c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 8 -------- + drivers/usb/host/xhci-mem.c | 3 --- + drivers/usb/host/xhci-ring.c | 3 --- + drivers/usb/host/xhci.h | 2 -- + 4 files changed, 16 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index f6d30314348d..21c563f9a98d 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -347,14 +347,10 @@ void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring) + ring->dequeue, + (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg, + ring->dequeue)); +- xhci_dbg(xhci, "Ring deq updated %u times\n", +- ring->deq_updates); + xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n", + ring->enqueue, + (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg, + ring->enqueue)); +- xhci_dbg(xhci, "Ring enq updated %u times\n", +- ring->enq_updates); + } + + /** +@@ -373,10 +369,6 @@ void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring) + struct xhci_segment *first_seg = ring->first_seg; + xhci_debug_segment(xhci, first_seg); + +- if (!ring->enq_updates && !ring->deq_updates) { +- xhci_dbg(xhci, " Ring has not been updated\n"); +- return; +- } + for (seg = first_seg->next; seg != first_seg; seg = seg->next) + xhci_debug_segment(xhci, seg); + } +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index e2e27a332e9a..9b37ef13bf3a 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -315,9 +315,6 @@ static void xhci_initialize_ring_info(struct xhci_ring *ring, + * handling ring expansion, set the cycle state equal to the old ring. + */ + ring->cycle_state = cycle_state; +- /* Not necessary for new rings, but needed for re-initialized rings */ +- ring->enq_updates = 0; +- ring->deq_updates = 0; + + /* + * Each segment has a link TRB, and leave an extra TRB for SW +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index deb318e0c679..b382cf071562 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -167,8 +167,6 @@ static void next_trb(struct xhci_hcd *xhci, + */ + static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) + { +- ring->deq_updates++; +- + /* event ring doesn't have link trbs, check for last trb */ + if (ring->type == TYPE_EVENT) { + if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { +@@ -226,7 +224,6 @@ static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, + ring->num_trbs_free--; + next = ++(ring->enqueue); + +- ring->enq_updates++; + /* Update the dequeue pointer further if that was a link TRB */ + while (trb_is_link(next)) { + +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 8b360f60d81e..770947b4e9a8 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1566,10 +1566,8 @@ struct xhci_ring { + struct xhci_segment *last_seg; + union xhci_trb *enqueue; + struct xhci_segment *enq_seg; +- unsigned int enq_updates; + union xhci_trb *dequeue; + struct xhci_segment *deq_seg; +- unsigned int deq_updates; + struct list_head td_list; + /* + * Write the cycle state into the TRB cycle field to give ownership of +-- +2.13.3 + diff --git a/patches.renesas/0193-usb-xhci-remove-ring-debugging-code.patch b/patches.renesas/0193-usb-xhci-remove-ring-debugging-code.patch new file mode 100644 index 00000000000000..d23bd94f8a709b --- /dev/null +++ b/patches.renesas/0193-usb-xhci-remove-ring-debugging-code.patch @@ -0,0 +1,156 @@ +From d64e53c04b734498ee72b6a47c31e784d002054c Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:07 +0300 +Subject: [PATCH 193/286] usb: xhci: remove ring debugging code + +XHCI ring changes have already been traced by the ring trace +events. It's unnecessary to put the same messages in kernel +log. This patch removes the debugging code for a ring. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 121dcf11908ecea252776c8268aab117f91aa1f5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 62 -------------------------------------------- + drivers/usb/host/xhci-ring.c | 4 --- + drivers/usb/host/xhci.c | 6 ----- + drivers/usb/host/xhci.h | 3 --- + 4 files changed, 75 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index 21c563f9a98d..77f80ceeccab 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -311,68 +311,6 @@ void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) + } + } + +-/** +- * Debug a segment with an xHCI ring. +- * +- * @return The Link TRB of the segment, or NULL if there is no Link TRB +- * (which is a bug, since all segments must have a Link TRB). +- * +- * Prints out all TRBs in the segment, even those after the Link TRB. +- * +- * XXX: should we print out TRBs that the HC owns? As long as we don't +- * write, that should be fine... We shouldn't expect that the memory pointed to +- * by the TRB is valid at all. Do we care about ones the HC owns? Probably, +- * for HC debugging. +- */ +-void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg) +-{ +- int i; +- u64 addr = seg->dma; +- union xhci_trb *trb = seg->trbs; +- +- for (i = 0; i < TRBS_PER_SEGMENT; i++) { +- trb = &seg->trbs[i]; +- xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr, +- lower_32_bits(le64_to_cpu(trb->link.segment_ptr)), +- upper_32_bits(le64_to_cpu(trb->link.segment_ptr)), +- le32_to_cpu(trb->link.intr_target), +- le32_to_cpu(trb->link.control)); +- addr += sizeof(*trb); +- } +-} +- +-void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring) +-{ +- xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n", +- ring->dequeue, +- (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg, +- ring->dequeue)); +- xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n", +- ring->enqueue, +- (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg, +- ring->enqueue)); +-} +- +-/** +- * Debugging for an xHCI ring, which is a queue broken into multiple segments. +- * +- * Print out each segment in the ring. Check that the DMA address in +- * each link segment actually matches the segment's stored DMA address. +- * Check that the link end bit is only set at the end of the ring. +- * Check that the dequeue and enqueue pointers point to real data in this ring +- * (not some other ring). +- */ +-void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring) +-{ +- /* FIXME: Throw an error if any segment doesn't have a Link TRB */ +- struct xhci_segment *seg; +- struct xhci_segment *first_seg = ring->first_seg; +- xhci_debug_segment(xhci, first_seg); +- +- for (seg = first_seg->next; seg != first_seg; seg = seg->next) +- xhci_debug_segment(xhci, seg); +-} +- + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) + { + u64 addr = erst->erst_dma_addr; +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index b382cf071562..a2bfd75b1ae6 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2292,8 +2292,6 @@ static int handle_tx_event(struct xhci_hcd *xhci, + upper_32_bits(le64_to_cpu(event->buffer)), + le32_to_cpu(event->transfer_len), + le32_to_cpu(event->flags)); +- xhci_dbg(xhci, "Event ring:\n"); +- xhci_debug_segment(xhci, xhci->event_ring->deq_seg); + return -ENODEV; + } + +@@ -2314,8 +2312,6 @@ static int handle_tx_event(struct xhci_hcd *xhci, + upper_32_bits(le64_to_cpu(event->buffer)), + le32_to_cpu(event->transfer_len), + le32_to_cpu(event->flags)); +- xhci_dbg(xhci, "Event ring:\n"); +- xhci_debug_segment(xhci, xhci->event_ring->deq_seg); + return -ENODEV; + } + +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index e0392564ed33..7ac9a84376dc 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -619,16 +619,10 @@ int xhci_run(struct usb_hcd *hcd) + if (ret) + return ret; + +- xhci_dbg(xhci, "Command ring memory map follows:\n"); +- xhci_debug_ring(xhci, xhci->cmd_ring); +- xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); + xhci_dbg_cmd_ptrs(xhci); + + xhci_dbg(xhci, "ERST memory map follows:\n"); + xhci_dbg_erst(xhci, &xhci->erst); +- xhci_dbg(xhci, "Event ring:\n"); +- xhci_debug_ring(xhci, xhci->event_ring); +- xhci_dbg_ring_ptrs(xhci, xhci->event_ring); + temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); + temp_64 &= ~ERST_PTR_MASK; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 770947b4e9a8..b7338a303e40 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1924,11 +1924,8 @@ void xhci_dbg_regs(struct xhci_hcd *xhci); + void xhci_print_run_regs(struct xhci_hcd *xhci); + void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); + void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); +-void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); +-void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); + void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); +-void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); + void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); + char *xhci_get_slot_state(struct xhci_hcd *xhci, + struct xhci_container_ctx *ctx); +-- +2.13.3 + diff --git a/patches.renesas/0194-usb-xhci-remove-xhci_debug_trb.patch b/patches.renesas/0194-usb-xhci-remove-xhci_debug_trb.patch new file mode 100644 index 00000000000000..7b299402b23c4a --- /dev/null +++ b/patches.renesas/0194-usb-xhci-remove-xhci_debug_trb.patch @@ -0,0 +1,119 @@ +From 72f4433f7378cc35088913722628673571273ed7 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:08 +0300 +Subject: [PATCH 194/286] usb: xhci: remove xhci_debug_trb() + +Every XHCI TRB has already been traced by the trb trace events. +It is unnecessary to put the same message in kernel log. This +patch removes xhci_debug_trb(). + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 8c10152ec52b850f9806c5c2f5a93ebe38838959) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 57 -------------------------------------------- + drivers/usb/host/xhci-ring.c | 4 ---- + drivers/usb/host/xhci.h | 2 -- + 3 files changed, 63 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index 77f80ceeccab..dc0194b87b74 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -254,63 +254,6 @@ void xhci_print_registers(struct xhci_hcd *xhci) + xhci_print_ports(xhci); + } + +-void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb) +-{ +- int i; +- for (i = 0; i < 4; i++) +- xhci_dbg(xhci, "Offset 0x%x = 0x%x\n", +- i*4, trb->generic.field[i]); +-} +- +-/** +- * Debug a transfer request block (TRB). +- */ +-void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) +-{ +- u64 address; +- u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK; +- +- switch (type) { +- case TRB_TYPE(TRB_LINK): +- xhci_dbg(xhci, "Link TRB:\n"); +- xhci_print_trb_offsets(xhci, trb); +- +- address = le64_to_cpu(trb->link.segment_ptr); +- xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address); +- +- xhci_dbg(xhci, "Interrupter target = 0x%x\n", +- GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target))); +- xhci_dbg(xhci, "Cycle bit = %u\n", +- le32_to_cpu(trb->link.control) & TRB_CYCLE); +- xhci_dbg(xhci, "Toggle cycle bit = %u\n", +- le32_to_cpu(trb->link.control) & LINK_TOGGLE); +- xhci_dbg(xhci, "No Snoop bit = %u\n", +- le32_to_cpu(trb->link.control) & TRB_NO_SNOOP); +- break; +- case TRB_TYPE(TRB_TRANSFER): +- address = le64_to_cpu(trb->trans_event.buffer); +- /* +- * FIXME: look at flags to figure out if it's an address or if +- * the data is directly in the buffer field. +- */ +- xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address); +- break; +- case TRB_TYPE(TRB_COMPLETION): +- address = le64_to_cpu(trb->event_cmd.cmd_trb); +- xhci_dbg(xhci, "Command TRB pointer = %llu\n", address); +- xhci_dbg(xhci, "Completion status = %u\n", +- GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status))); +- xhci_dbg(xhci, "Flags = 0x%x\n", +- le32_to_cpu(trb->event_cmd.flags)); +- break; +- default: +- xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n", +- (unsigned int) type>>10); +- xhci_print_trb_offsets(xhci, trb); +- break; +- } +-} +- + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) + { + u64 addr = erst->erst_dma_addr; +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index a2bfd75b1ae6..74bf5c60a260 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2463,10 +2463,6 @@ static int handle_tx_event(struct xhci_hcd *xhci, + xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", + TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), + ep_index); +- xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", +- (le32_to_cpu(event->flags) & +- TRB_TYPE_BITMASK)>>10); +- xhci_print_trb_offsets(xhci, (union xhci_trb *) event); + } + if (ep->skip) { + ep->skip = false; +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index b7338a303e40..ed6d094381af 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1922,8 +1922,6 @@ void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); + void xhci_print_registers(struct xhci_hcd *xhci); + void xhci_dbg_regs(struct xhci_hcd *xhci); + void xhci_print_run_regs(struct xhci_hcd *xhci); +-void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); +-void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); + void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); + void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); +-- +2.13.3 + diff --git a/patches.renesas/0195-usb-xhci-remove-xhci_dbg_ctx.patch b/patches.renesas/0195-usb-xhci-remove-xhci_dbg_ctx.patch new file mode 100644 index 00000000000000..f380edff1e179b --- /dev/null +++ b/patches.renesas/0195-usb-xhci-remove-xhci_dbg_ctx.patch @@ -0,0 +1,334 @@ +From d28bc3b64ca7c8cc5b061893105679fe20c54542 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:09 +0300 +Subject: [PATCH 195/286] usb: xhci: remove xhci_dbg_ctx() + +XHCI context changes have already been traced by the trace +events. It's unnecessary to put the same message in kernel +log. This patch removes the use of xhci_dbg_ctx(). + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit c8844f2ddb0d2bc42a813c567ad4240759f373bd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-dbg.c | 143 -------------------------------------------- + drivers/usb/host/xhci.c | 37 ------------ + drivers/usb/host/xhci.h | 1 - + 3 files changed, 181 deletions(-) + +diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c +index dc0194b87b74..2c83b37ae8f2 100644 +--- a/drivers/usb/host/xhci-dbg.c ++++ b/drivers/usb/host/xhci-dbg.c +@@ -283,19 +283,6 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci) + upper_32_bits(val)); + } + +-/* Print the last 32 bytes for 64-byte contexts */ +-static void dbg_rsvd64(struct xhci_hcd *xhci, u64 *ctx, dma_addr_t dma) +-{ +- int i; +- for (i = 0; i < 4; i++) { +- xhci_dbg(xhci, "@%p (virt) @%08llx " +- "(dma) %#08llx - rsvd64[%d]\n", +- &ctx[4 + i], (unsigned long long)dma, +- ctx[4 + i], i); +- dma += 8; +- } +-} +- + char *xhci_get_slot_state(struct xhci_hcd *xhci, + struct xhci_container_ctx *ctx) + { +@@ -305,136 +292,6 @@ char *xhci_get_slot_state(struct xhci_hcd *xhci, + return xhci_slot_state_string(state); + } + +-static void xhci_dbg_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx) +-{ +- /* Fields are 32 bits wide, DMA addresses are in bytes */ +- int field_size = 32 / 8; +- int i; +- +- struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx); +- dma_addr_t dma = ctx->dma + +- ((unsigned long)slot_ctx - (unsigned long)ctx->bytes); +- int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params); +- +- xhci_dbg(xhci, "Slot Context:\n"); +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n", +- &slot_ctx->dev_info, +- (unsigned long long)dma, slot_ctx->dev_info); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n", +- &slot_ctx->dev_info2, +- (unsigned long long)dma, slot_ctx->dev_info2); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n", +- &slot_ctx->tt_info, +- (unsigned long long)dma, slot_ctx->tt_info); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n", +- &slot_ctx->dev_state, +- (unsigned long long)dma, slot_ctx->dev_state); +- dma += field_size; +- for (i = 0; i < 4; i++) { +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", +- &slot_ctx->reserved[i], (unsigned long long)dma, +- slot_ctx->reserved[i], i); +- dma += field_size; +- } +- +- if (csz) +- dbg_rsvd64(xhci, (u64 *)slot_ctx, dma); +-} +- +-static void xhci_dbg_ep_ctx(struct xhci_hcd *xhci, +- struct xhci_container_ctx *ctx, +- unsigned int last_ep) +-{ +- int i, j; +- int last_ep_ctx = 31; +- /* Fields are 32 bits wide, DMA addresses are in bytes */ +- int field_size = 32 / 8; +- int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params); +- +- if (last_ep < 31) +- last_ep_ctx = last_ep + 1; +- for (i = 0; i < last_ep_ctx; i++) { +- unsigned int epaddr = xhci_get_endpoint_address(i); +- struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, ctx, i); +- dma_addr_t dma = ctx->dma + +- ((unsigned long)ep_ctx - (unsigned long)ctx->bytes); +- +- xhci_dbg(xhci, "%s Endpoint %02d Context (ep_index %02d):\n", +- usb_endpoint_out(epaddr) ? "OUT" : "IN", +- epaddr & USB_ENDPOINT_NUMBER_MASK, i); +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n", +- &ep_ctx->ep_info, +- (unsigned long long)dma, ep_ctx->ep_info); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n", +- &ep_ctx->ep_info2, +- (unsigned long long)dma, ep_ctx->ep_info2); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08llx - deq\n", +- &ep_ctx->deq, +- (unsigned long long)dma, ep_ctx->deq); +- dma += 2*field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n", +- &ep_ctx->tx_info, +- (unsigned long long)dma, ep_ctx->tx_info); +- dma += field_size; +- for (j = 0; j < 3; j++) { +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n", +- &ep_ctx->reserved[j], +- (unsigned long long)dma, +- ep_ctx->reserved[j], j); +- dma += field_size; +- } +- +- if (csz) +- dbg_rsvd64(xhci, (u64 *)ep_ctx, dma); +- } +-} +- +-void xhci_dbg_ctx(struct xhci_hcd *xhci, +- struct xhci_container_ctx *ctx, +- unsigned int last_ep) +-{ +- int i; +- /* Fields are 32 bits wide, DMA addresses are in bytes */ +- int field_size = 32 / 8; +- dma_addr_t dma = ctx->dma; +- int csz = HCC_64BYTE_CONTEXT(xhci->hcc_params); +- +- if (ctx->type == XHCI_CTX_TYPE_INPUT) { +- struct xhci_input_control_ctx *ctrl_ctx = +- xhci_get_input_control_ctx(ctx); +- if (!ctrl_ctx) { +- xhci_warn(xhci, "Could not get input context, bad type.\n"); +- return; +- } +- +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n", +- &ctrl_ctx->drop_flags, (unsigned long long)dma, +- ctrl_ctx->drop_flags); +- dma += field_size; +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n", +- &ctrl_ctx->add_flags, (unsigned long long)dma, +- ctrl_ctx->add_flags); +- dma += field_size; +- for (i = 0; i < 6; i++) { +- xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd2[%d]\n", +- &ctrl_ctx->rsvd2[i], (unsigned long long)dma, +- ctrl_ctx->rsvd2[i], i); +- dma += field_size; +- } +- +- if (csz) +- dbg_rsvd64(xhci, (u64 *)ctrl_ctx, dma); +- } +- +- xhci_dbg_slot_ctx(xhci, ctx); +- xhci_dbg_ep_ctx(xhci, ctx, last_ep); +-} +- + void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), + const char *fmt, ...) + { +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 7ac9a84376dc..dd2b42f52d99 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1302,11 +1302,6 @@ static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, + ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); + ctrl_ctx->drop_flags = 0; + +- xhci_dbg(xhci, "Slot %d input context\n", slot_id); +- xhci_dbg_ctx(xhci, command->in_ctx, ep_index); +- xhci_dbg(xhci, "Slot %d output context\n", slot_id); +- xhci_dbg_ctx(xhci, out_ctx, ep_index); +- + ret = xhci_configure_endpoint(xhci, urb->dev, command, + true, false); + +@@ -1854,7 +1849,6 @@ static int xhci_evaluate_context_result(struct xhci_hcd *xhci, + struct usb_device *udev, u32 *cmd_status) + { + int ret; +- struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; + + switch (*cmd_status) { + case COMP_COMMAND_ABORTED: +@@ -1875,7 +1869,6 @@ static int xhci_evaluate_context_result(struct xhci_hcd *xhci, + case COMP_CONTEXT_STATE_ERROR: + dev_warn(&udev->dev, + "WARN: invalid context state for evaluate context command.\n"); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); + ret = -EINVAL; + break; + case COMP_INCOMPATIBLE_DEVICE_ERROR: +@@ -2754,9 +2747,6 @@ static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) + break; + } + } +- xhci_dbg(xhci, "New Input Control Context:\n"); +- xhci_dbg_ctx(xhci, virt_dev->in_ctx, +- LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); + + ret = xhci_configure_endpoint(xhci, udev, command, + false, false); +@@ -2764,10 +2754,6 @@ static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) + /* Callee should call reset_bandwidth() */ + goto command_cleanup; + +- xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, +- LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); +- + /* Free any rings that were dropped, but not changed. */ + for (i = 1; i < 31; i++) { + if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && +@@ -2834,9 +2820,6 @@ static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, + ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); + xhci_slot_copy(xhci, in_ctx, out_ctx); + ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); +- +- xhci_dbg(xhci, "Input Context:\n"); +- xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); + } + + static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, +@@ -3549,9 +3532,6 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd, + } + /* If necessary, update the number of active TTs on this root port */ + xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); +- +- xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); + ret = 0; + + command_cleanup: +@@ -3851,8 +3831,6 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); + ctrl_ctx->drop_flags = 0; + +- xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); + trace_xhci_address_ctx(xhci, virt_dev->in_ctx, + le32_to_cpu(slot_ctx->dev_info) >> 27); + +@@ -3905,8 +3883,6 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + xhci_err(xhci, + "ERROR: unexpected setup %s command completion code 0x%x.\n", + act, command->status); +- xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); + trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); + ret = -EINVAL; + break; +@@ -3925,12 +3901,8 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + xhci_dbg_trace(xhci, trace_xhci_dbg_address, + "Output Context DMA address = %#08llx", + (unsigned long long)virt_dev->out_ctx->dma); +- xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); + trace_xhci_address_ctx(xhci, virt_dev->in_ctx, + le32_to_cpu(slot_ctx->dev_info) >> 27); +- xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); + /* + * USB core uses address 1 for the roothubs, so we add one to the + * address given back to us by the HC. +@@ -4035,14 +4007,10 @@ static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, + + xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, + "Set up evaluate context for LPM MEL change."); +- xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, command->in_ctx, 0); + + /* Issue and wait for the evaluate context command. */ + ret = xhci_configure_endpoint(xhci, udev, command, + true, true); +- xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id); +- xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0); + + if (!ret) { + spin_lock_irqsave(&xhci->lock, flags); +@@ -4810,8 +4778,6 @@ static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, + xhci_dbg(xhci, "Set up %s for hub device.\n", + (xhci->hci_version > 0x95) ? + "configure endpoint" : "evaluate context"); +- xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id); +- xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0); + + /* Issue and wait for the configure endpoint or + * evaluate context command. +@@ -4823,9 +4789,6 @@ static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, + ret = xhci_configure_endpoint(xhci, hdev, config_cmd, + true, false); + +- xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id); +- xhci_dbg_ctx(xhci, vdev->out_ctx, 0); +- + xhci_free_command(xhci, config_cmd); + return ret; + } +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index ed6d094381af..064d48afe496 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1924,7 +1924,6 @@ void xhci_dbg_regs(struct xhci_hcd *xhci); + void xhci_print_run_regs(struct xhci_hcd *xhci); + void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); + void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); +-void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); + char *xhci_get_slot_state(struct xhci_hcd *xhci, + struct xhci_container_ctx *ctx); + void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), +-- +2.13.3 + diff --git a/patches.renesas/0196-usb-xhci-fix-link-trb-decoding.patch b/patches.renesas/0196-usb-xhci-fix-link-trb-decoding.patch new file mode 100644 index 00000000000000..c077d4daf1aaba --- /dev/null +++ b/patches.renesas/0196-usb-xhci-fix-link-trb-decoding.patch @@ -0,0 +1,45 @@ +From 248f2891d24f12be25f879ff27496cd2516de5c3 Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:10 +0300 +Subject: [PATCH 196/286] usb: xhci: fix link trb decoding + +xhci_decode_trb() treats a link trb in the same way as that for +an event trb. This patch fixes this by decoding the link trb +according to the spec. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 96d9a6eb97d77d6a3768f101f400c42743799bb2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.h | 12 +++++------- + 1 file changed, 5 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 064d48afe496..fcf72937e5ec 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2136,14 +2136,12 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + switch (type) { + case TRB_LINK: + sprintf(str, +- "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", +- field1, field0, +- xhci_trb_comp_code_string(GET_COMP_CODE(field2)), +- EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), +- /* Macro decrements 1, maybe it shouldn't?!? */ +- TRB_TO_EP_INDEX(field3) + 1, ++ "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", ++ field1, field0, GET_INTR_TARGET(field2), + xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), +- field3 & EVENT_DATA ? 'E' : 'e', ++ field3 & TRB_IOC ? 'I' : 'i', ++ field3 & TRB_CHAIN ? 'C' : 'c', ++ field3 & TRB_TC ? 'T' : 't', + field3 & TRB_CYCLE ? 'C' : 'c'); + break; + case TRB_TRANSFER: +-- +2.13.3 + diff --git a/patches.renesas/0197-usb-xhci-refine-xhci_decode_trb.patch b/patches.renesas/0197-usb-xhci-refine-xhci_decode_trb.patch new file mode 100644 index 00000000000000..250d17a99b3df0 --- /dev/null +++ b/patches.renesas/0197-usb-xhci-refine-xhci_decode_trb.patch @@ -0,0 +1,200 @@ +From 78d15a9ca068a20a9884df7da237740b0cfac1ea Mon Sep 17 00:00:00 2001 +From: Lu Baolu <baolu.lu@linux.intel.com> +Date: Fri, 7 Apr 2017 17:57:11 +0300 +Subject: [PATCH 197/286] usb: xhci: refine xhci_decode_trb() + +Replace 'TRB_FIELD_TO_TYPE(field3)' with 'type' to simplify +code. + +Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d2561626b9d126a94753ad6f048114bab702f02f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci.h | 40 ++++++++++++++++++++-------------------- + 1 file changed, 20 insertions(+), 20 deletions(-) + +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index fcf72937e5ec..914968c662c9 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2138,7 +2138,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + sprintf(str, + "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", + field1, field0, GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_TC ? 'T' : 't', +@@ -2159,7 +2159,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), + /* Macro decrements 1, maybe it shouldn't?!? */ + TRB_TO_EP_INDEX(field3) + 1, +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & EVENT_DATA ? 'E' : 'e', + field3 & TRB_CYCLE ? 'C' : 'c'); + +@@ -2176,7 +2176,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + (field1 & 0xff0000) >> 16, + TRB_LEN(field2), GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_IDT ? 'I' : 'i', + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CYCLE ? 'C' : 'c'); +@@ -2185,7 +2185,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", + field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_IDT ? 'I' : 'i', + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', +@@ -2198,7 +2198,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", + field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_ENT ? 'E' : 'e', +@@ -2212,7 +2212,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", + field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_BEI ? 'B' : 'b', + field3 & TRB_IDT ? 'I' : 'i', + field3 & TRB_IOC ? 'I' : 'i', +@@ -2227,21 +2227,21 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_ENABLE_SLOT: + sprintf(str, + "%s: flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field3 & TRB_CYCLE ? 'C' : 'c'); + break; + case TRB_DISABLE_SLOT: + case TRB_NEG_BANDWIDTH: + sprintf(str, + "%s: slot %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); + break; + case TRB_ADDR_DEV: + sprintf(str, + "%s: ctx %08x%08x slot %d flags %c:%c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_BSR ? 'B' : 'b', +@@ -2250,7 +2250,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_CONFIG_EP: + sprintf(str, + "%s: ctx %08x%08x slot %d flags %c:%c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_DC ? 'D' : 'd', +@@ -2259,7 +2259,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_EVAL_CONTEXT: + sprintf(str, + "%s: ctx %08x%08x slot %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); +@@ -2267,7 +2267,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_RESET_EP: + sprintf(str, + "%s: ctx %08x%08x slot %d ep %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_SLOT_ID(field3), + /* Macro decrements 1, maybe it shouldn't?!? */ +@@ -2277,7 +2277,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_STOP_RING: + sprintf(str, + "%s: slot %d sp %d ep %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + TRB_TO_SLOT_ID(field3), + TRB_TO_SUSPEND_PORT(field3), + /* Macro decrements 1, maybe it shouldn't?!? */ +@@ -2287,7 +2287,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_SET_DEQ: + sprintf(str, + "%s: deq %08x%08x stream %d slot %d ep %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_STREAM_ID(field2), + TRB_TO_SLOT_ID(field3), +@@ -2298,14 +2298,14 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_RESET_DEV: + sprintf(str, + "%s: slot %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); + break; + case TRB_FORCE_EVENT: + sprintf(str, + "%s: event %08x%08x vf intr %d vf id %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_VF_INTR_TARGET(field2), + TRB_TO_VF_ID(field3), +@@ -2314,14 +2314,14 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_SET_LT: + sprintf(str, + "%s: belt %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + TRB_TO_BELT(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); + break; + case TRB_GET_BW: + sprintf(str, + "%s: ctx %08x%08x slot %d speed %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field1, field0, + TRB_TO_SLOT_ID(field3), + TRB_TO_DEV_SPEED(field3), +@@ -2330,7 +2330,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + case TRB_FORCE_HEADER: + sprintf(str, + "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field2, field1, field0 & 0xffffffe0, + TRB_TO_PACKET_TYPE(field0), + TRB_TO_ROOTHUB_PORT(field3), +@@ -2339,7 +2339,7 @@ static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, + default: + sprintf(str, + "type '%s' -> raw %08x %08x %08x %08x", +- xhci_trb_type_string(TRB_FIELD_TO_TYPE(field3)), ++ xhci_trb_type_string(type), + field0, field1, field2, field3); + } + +-- +2.13.3 + diff --git a/patches.renesas/0198-usb-xhci-bInterval-quirk-for-TI-TUSB73x0.patch b/patches.renesas/0198-usb-xhci-bInterval-quirk-for-TI-TUSB73x0.patch new file mode 100644 index 00000000000000..3f795fe07d7efa --- /dev/null +++ b/patches.renesas/0198-usb-xhci-bInterval-quirk-for-TI-TUSB73x0.patch @@ -0,0 +1,50 @@ +From dec687bcc93701a13e19a359c687e20c33a382a3 Mon Sep 17 00:00:00 2001 +From: Roger Quadros <rogerq@ti.com> +Date: Fri, 7 Apr 2017 17:57:12 +0300 +Subject: [PATCH 198/286] usb: xhci: bInterval quirk for TI TUSB73x0 + +As per [1] issue #4, +"The periodic EP scheduler always tries to schedule the EPs +that have large intervals (interval equal to or greater than +128 microframes) into different microframes. So it maintains +an internal counter and increments for each large interval +EP added. When the counter is greater than 128, the scheduler +rejects the new EP. So when the hub re-enumerated 128 times, +it triggers this condition." + +This results in Bandwidth error when devices with periodic +endpoints (ISO/INT) having bInterval > 7 are plugged and +unplugged several times on a TUSB73x0 XHCI host. + +Workaround this issue by limiting the bInterval to 7 +(i.e. interval to 6) for High-speed or faster periodic endpoints. + +[1] - http://www.ti.com/lit/er/sllz076/sllz076.pdf + +Cc: stable <stable@vger.kernel.org> +Signed-off-by: Roger Quadros <rogerq@ti.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 69307ccb9ad7ccb653e332de68effdeaaab6907d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-pci.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c +index 69864ba38698..8b390cc5167f 100644 +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -208,6 +208,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) + if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) + xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; + ++ if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ++ xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; ++ + if (xhci->quirks & XHCI_RESET_ON_RESUME) + xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, + "QUIRK: Resetting on resume"); +-- +2.13.3 + diff --git a/patches.renesas/0199-xhci-use-correct-flags-for-spin_lock_irqrestore-when.patch b/patches.renesas/0199-xhci-use-correct-flags-for-spin_lock_irqrestore-when.patch new file mode 100644 index 00000000000000..c4229fbb61fabe --- /dev/null +++ b/patches.renesas/0199-xhci-use-correct-flags-for-spin_lock_irqrestore-when.patch @@ -0,0 +1,114 @@ +From 073324c8d390be34710adb3e1bb9eecc82cce9ce Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Thu, 13 Apr 2017 14:01:04 +0300 +Subject: [PATCH 199/286] xhci: use correct flags for spin_lock_irqrestore() + when setting port power + +commit a6ff6cbf1fab ("usb: xhci: Add helper function xhci_set_power_on().") +created a helper to control port power that needs to be called with +xhci->lock held and interrupts disabled. +It released the lock with spin_unlock_irqrestore using a new zero flag +variable instead of the original flag from spin_lock_irqsave. +This regression triggered a static checker warning about bogus flags, and +a null pointer dereference on armada-385. + +Fix it by passing a pointer to the correct flags and using it instead + +Fixes: a6ff6cbf1fab ("usb: xhci: Add helper function xhci_set_power_on().") +Cc: Guoqing Zhang <guoqing.zhang@intel.com> +Reported-by: Ralph Sennhauser <ralph.sennhauser@gmail.com> +Tested-by: Ralph Sennhauser <ralph.sennhauser@gmail.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit ec1dafe8ec5f846d6b1b280309d8b03d25b096fd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index ab818bd5d0ac..5e3e9d4c6956 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -552,11 +552,10 @@ static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index) + * method. + */ + static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, +- u16 index, bool on) ++ u16 index, bool on, unsigned long *flags) + { + __le32 __iomem *addr; + u32 temp; +- unsigned long flags = 0; + + addr = xhci_get_port_io_addr(hcd, index); + temp = readl(addr); +@@ -572,13 +571,13 @@ static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, + writel(temp & ~PORT_POWER, addr); + } + +- spin_unlock_irqrestore(&xhci->lock, flags); ++ spin_unlock_irqrestore(&xhci->lock, *flags); + temp = usb_acpi_power_manageable(hcd->self.root_hub, + index); + if (temp) + usb_acpi_set_power_state(hcd->self.root_hub, + index, on); +- spin_lock_irqsave(&xhci->lock, flags); ++ spin_lock_irqsave(&xhci->lock, *flags); + } + + static void xhci_port_set_test_mode(struct xhci_hcd *xhci, +@@ -598,7 +597,7 @@ static void xhci_port_set_test_mode(struct xhci_hcd *xhci, + } + + static int xhci_enter_test_mode(struct xhci_hcd *xhci, +- u16 test_mode, u16 wIndex) ++ u16 test_mode, u16 wIndex, unsigned long *flags) + { + int i, retval; + +@@ -614,10 +613,10 @@ static int xhci_enter_test_mode(struct xhci_hcd *xhci, + xhci_dbg(xhci, "Disable all port (PP = 0)\n"); + /* Power off USB3 ports*/ + for (i = 0; i < xhci->num_usb3_ports; i++) +- xhci_set_port_power(xhci, xhci->shared_hcd, i, false); ++ xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); + /* Power off USB2 ports*/ + for (i = 0; i < xhci->num_usb2_ports; i++) +- xhci_set_port_power(xhci, xhci->main_hcd, i, false); ++ xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); + /* Stop the controller */ + xhci_dbg(xhci, "Stop controller\n"); + retval = xhci_halt(xhci); +@@ -1209,7 +1208,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + * However, hub_wq will ignore the roothub events until + * the roothub is registered. + */ +- xhci_set_port_power(xhci, hcd, wIndex, true); ++ xhci_set_port_power(xhci, hcd, wIndex, true, &flags); + break; + case USB_PORT_FEAT_RESET: + temp = (temp | PORT_RESET); +@@ -1254,7 +1253,8 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + goto error; + if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) + goto error; +- retval = xhci_enter_test_mode(xhci, test_mode, wIndex); ++ retval = xhci_enter_test_mode(xhci, test_mode, wIndex, ++ &flags); + break; + default: + goto error; +@@ -1322,7 +1322,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + port_array[wIndex], temp); + break; + case USB_PORT_FEAT_POWER: +- xhci_set_port_power(xhci, hcd, wIndex, false); ++ xhci_set_port_power(xhci, hcd, wIndex, false, &flags); + break; + case USB_PORT_FEAT_TEST: + retval = xhci_exit_test_mode(xhci); +-- +2.13.3 + diff --git a/patches.renesas/0200-usb-host-plat-Enable-xHCI-plat-runtime-PM.patch b/patches.renesas/0200-usb-host-plat-Enable-xHCI-plat-runtime-PM.patch new file mode 100644 index 00000000000000..4a86a8a98169b1 --- /dev/null +++ b/patches.renesas/0200-usb-host-plat-Enable-xHCI-plat-runtime-PM.patch @@ -0,0 +1,130 @@ +From 48814bc6ea992e21c21315c5dbafc7ca723dbb0b Mon Sep 17 00:00:00 2001 +From: Baolin Wang <baolin.wang@linaro.org> +Date: Wed, 19 Apr 2017 16:55:45 +0300 +Subject: [PATCH 200/286] usb: host: plat: Enable xHCI plat runtime PM + +Enable the xHCI plat runtime PM for parent device to suspend/resume +xHCI. Also call pm_runtime_forbid() in probe() function to force users +to explicitly enable runtime pm using power/control in sysfs, in case +some parent devices didn't implement runtime PM callbacks. + +[set do_wakeup to true when runtime suspending -Mathias] +Signed-off-by: Baolin Wang <baolin.wang@linaro.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit b0c69b4bace3703a29e08dda2b5a10e1073cb9cd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> + +Conflicts: + drivers/usb/host/xhci-plat.c +--- + drivers/usb/host/xhci-plat.c | 53 ++++++++++++++++++++++++++++++++++++++------ + 1 file changed, 46 insertions(+), 7 deletions(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 37f59a975dd9..6046ae3712fa 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -179,9 +179,15 @@ static int xhci_plat_probe(struct platform_device *pdev) + return ret; + } + ++ pm_runtime_set_active(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_noresume(&pdev->dev); ++ + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); +- if (!hcd) +- return -ENOMEM; ++ if (!hcd) { ++ ret = -ENOMEM; ++ goto disable_runtime; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + hcd->regs = devm_ioremap_resource(&pdev->dev, res); +@@ -259,6 +265,13 @@ static int xhci_plat_probe(struct platform_device *pdev) + goto dealloc_usb2_hcd; + + device_enable_async_suspend(&pdev->dev); ++ pm_runtime_put_noidle(&pdev->dev); ++ ++ /* ++ * Prevent runtime pm from being on as default, users should enable ++ * runtime pm using power/control in sysfs. ++ */ ++ pm_runtime_forbid(&pdev->dev); + + return 0; + +@@ -279,6 +292,10 @@ static int xhci_plat_probe(struct platform_device *pdev) + put_hcd: + usb_put_hcd(hcd); + ++disable_runtime: ++ pm_runtime_put_noidle(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ + return ret; + } + +@@ -300,6 +317,9 @@ static int xhci_plat_remove(struct platform_device *dev) + clk_disable_unprepare(clk); + usb_put_hcd(hcd); + ++ pm_runtime_set_suspended(&dev->dev); ++ pm_runtime_disable(&dev->dev); ++ + return 0; + } + +@@ -327,14 +347,33 @@ static int xhci_plat_resume(struct device *dev) + + return xhci_resume(xhci, 0); + } ++#endif /* CONFIG_PM_SLEEP */ ++ ++#ifdef CONFIG_PM ++static int xhci_plat_runtime_suspend(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ ++ return xhci_suspend(xhci, true); ++} ++ ++static int xhci_plat_runtime_resume(struct device *dev) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ ++ return xhci_resume(xhci, 0); ++} ++#endif /* CONFIG_PM */ + + static const struct dev_pm_ops xhci_plat_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(xhci_plat_suspend, xhci_plat_resume) ++ ++ SET_RUNTIME_PM_OPS(xhci_plat_runtime_suspend, ++ xhci_plat_runtime_resume, ++ NULL) + }; +-#define DEV_PM_OPS (&xhci_plat_pm_ops) +-#else +-#define DEV_PM_OPS NULL +-#endif /* CONFIG_PM */ + + static const struct acpi_device_id usb_xhci_acpi_match[] = { + /* XHCI-compliant USB Controller */ +@@ -349,7 +388,7 @@ static struct platform_driver usb_xhci_driver = { + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "xhci-hcd", +- .pm = DEV_PM_OPS, ++ .pm = &xhci_plat_pm_ops, + .of_match_table = of_match_ptr(usb_xhci_of_match), + .acpi_match_table = ACPI_PTR(usb_xhci_acpi_match), + }, +-- +2.13.3 + diff --git a/patches.renesas/0201-usb-host-xhci-plat-enable-clk-in-resume-timing.patch b/patches.renesas/0201-usb-host-xhci-plat-enable-clk-in-resume-timing.patch new file mode 100644 index 00000000000000..0e6e66687d3c5e --- /dev/null +++ b/patches.renesas/0201-usb-host-xhci-plat-enable-clk-in-resume-timing.patch @@ -0,0 +1,57 @@ +From 61d5b51b6425b09da807e2ce31232e8c56f172c9 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 19 Apr 2017 16:55:46 +0300 +Subject: [PATCH 201/286] usb: host: xhci-plat: enable clk in resume timing + +This patch enables the clk in resume timing when device_may_wakeup() +is false. Otherwise, kernel panic happens when R-Car resumes the system +from Suspend-to-RAM because the clk is disabled. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 835e4241e714fbd659838618466766b132823da3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 6046ae3712fa..89898eae82ae 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -328,6 +328,7 @@ static int xhci_plat_suspend(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ int ret; + + /* + * xhci_suspend() needs `do_wakeup` to know whether host is allowed +@@ -337,7 +338,12 @@ static int xhci_plat_suspend(struct device *dev) + * reconsider this when xhci_plat_suspend enlarges its scope, e.g., + * also applies to runtime suspend. + */ +- return xhci_suspend(xhci, device_may_wakeup(dev)); ++ ret = xhci_suspend(xhci, device_may_wakeup(dev)); ++ ++ if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk)) ++ clk_disable_unprepare(xhci->clk); ++ ++ return ret; + } + + static int xhci_plat_resume(struct device *dev) +@@ -345,6 +351,9 @@ static int xhci_plat_resume(struct device *dev) + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + ++ if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk)) ++ clk_prepare_enable(xhci->clk); ++ + return xhci_resume(xhci, 0); + } + #endif /* CONFIG_PM_SLEEP */ +-- +2.13.3 + diff --git a/patches.renesas/0202-usb-host-xhci-plat-add-resume_quirk.patch b/patches.renesas/0202-usb-host-xhci-plat-add-resume_quirk.patch new file mode 100644 index 00000000000000..1213638996de9f --- /dev/null +++ b/patches.renesas/0202-usb-host-xhci-plat-add-resume_quirk.patch @@ -0,0 +1,70 @@ +From 851c48ee8cb0166ef723eb677d6b4120956215d4 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 19 Apr 2017 16:55:47 +0300 +Subject: [PATCH 202/286] usb: host: xhci-plat: add resume_quirk() + +This patch adds resume_quirk() to do platform specific process in +resume timing. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 98c0a3ffa30c4b389257f7e7ee80ab9e90b78924) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 15 +++++++++++++++ + drivers/usb/host/xhci-plat.h | 1 + + 2 files changed, 16 insertions(+) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 89898eae82ae..96fcba325b93 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -54,6 +54,16 @@ static int xhci_priv_init_quirk(struct usb_hcd *hcd) + return priv->init_quirk(hcd); + } + ++static int xhci_priv_resume_quirk(struct usb_hcd *hcd) ++{ ++ struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); ++ ++ if (!priv->resume_quirk) ++ return 0; ++ ++ return priv->resume_quirk(hcd); ++} ++ + static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) + { + /* +@@ -350,10 +360,15 @@ static int xhci_plat_resume(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ int ret; + + if (!device_may_wakeup(dev) && !IS_ERR(xhci->clk)) + clk_prepare_enable(xhci->clk); + ++ ret = xhci_priv_resume_quirk(hcd); ++ if (ret) ++ return ret; ++ + return xhci_resume(xhci, 0); + } + #endif /* CONFIG_PM_SLEEP */ +diff --git a/drivers/usb/host/xhci-plat.h b/drivers/usb/host/xhci-plat.h +index 9af0cb48053f..29b227895b07 100644 +--- a/drivers/usb/host/xhci-plat.h ++++ b/drivers/usb/host/xhci-plat.h +@@ -17,6 +17,7 @@ struct xhci_plat_priv { + const char *firmware_name; + void (*plat_start)(struct usb_hcd *); + int (*init_quirk)(struct usb_hcd *); ++ int (*resume_quirk)(struct usb_hcd *); + }; + + #define hcd_to_xhci_priv(h) ((struct xhci_plat_priv *)hcd_to_xhci(h)->priv) +-- +2.13.3 + diff --git a/patches.renesas/0203-usb-host-xhci-plat-set-resume_quirk-for-R-Car-contro.patch b/patches.renesas/0203-usb-host-xhci-plat-set-resume_quirk-for-R-Car-contro.patch new file mode 100644 index 00000000000000..830b48cba6e5ea --- /dev/null +++ b/patches.renesas/0203-usb-host-xhci-plat-set-resume_quirk-for-R-Car-contro.patch @@ -0,0 +1,93 @@ +From 174e9a14644894909e20cf6a9ff8646563bf7513 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Date: Wed, 19 Apr 2017 16:55:48 +0300 +Subject: [PATCH 203/286] usb: host: xhci-plat: set resume_quirk() for R-Car + controllers + +This patch sets resume_quirk() for R-Car controllers to re-download +the firmware in resume timing. Otherwise, if the controller's power +is down in suspend timing, the firmware in the controller goes away, +and then the controller doesn't work after resume. + +Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 435cc1138ec94af7497ea68c8eb8b0c17cfcf002) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 3 +++ + drivers/usb/host/xhci-rcar.c | 11 +++++++++++ + drivers/usb/host/xhci-rcar.h | 6 ++++++ + 3 files changed, 20 insertions(+) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 96fcba325b93..8728ce7bf245 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -102,18 +102,21 @@ static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = { + .firmware_name = XHCI_RCAR_FIRMWARE_NAME_V1, + .init_quirk = xhci_rcar_init_quirk, + .plat_start = xhci_rcar_start, ++ .resume_quirk = xhci_rcar_resume_quirk, + }; + + static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = { + .firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2, + .init_quirk = xhci_rcar_init_quirk, + .plat_start = xhci_rcar_start, ++ .resume_quirk = xhci_rcar_resume_quirk, + }; + + static const struct xhci_plat_priv xhci_plat_renesas_rcar_r8a7796 = { + .firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3, + .init_quirk = xhci_rcar_init_quirk, + .plat_start = xhci_rcar_start, ++ .resume_quirk = xhci_rcar_resume_quirk, + }; + + static const struct of_device_id usb_xhci_of_match[] = { +diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c +index d28df386e780..07278228214b 100644 +--- a/drivers/usb/host/xhci-rcar.c ++++ b/drivers/usb/host/xhci-rcar.c +@@ -198,3 +198,14 @@ int xhci_rcar_init_quirk(struct usb_hcd *hcd) + + return xhci_rcar_download_firmware(hcd); + } ++ ++int xhci_rcar_resume_quirk(struct usb_hcd *hcd) ++{ ++ int ret; ++ ++ ret = xhci_rcar_download_firmware(hcd); ++ if (!ret) ++ xhci_rcar_start(hcd); ++ ++ return ret; ++} +diff --git a/drivers/usb/host/xhci-rcar.h b/drivers/usb/host/xhci-rcar.h +index d2ffe20401cf..d247951147a1 100644 +--- a/drivers/usb/host/xhci-rcar.h ++++ b/drivers/usb/host/xhci-rcar.h +@@ -18,6 +18,7 @@ + #if IS_ENABLED(CONFIG_USB_XHCI_RCAR) + void xhci_rcar_start(struct usb_hcd *hcd); + int xhci_rcar_init_quirk(struct usb_hcd *hcd); ++int xhci_rcar_resume_quirk(struct usb_hcd *hcd); + #else + static inline void xhci_rcar_start(struct usb_hcd *hcd) + { +@@ -27,5 +28,10 @@ static inline int xhci_rcar_init_quirk(struct usb_hcd *hcd) + { + return 0; + } ++ ++static inline int xhci_rcar_resume_quirk(struct usb_hcd *hcd) ++{ ++ return 0; ++} + #endif + #endif /* _XHCI_RCAR_H */ +-- +2.13.3 + diff --git a/patches.renesas/0204-usb-host-xhci-using-correct-specification-chapter-re.patch b/patches.renesas/0204-usb-host-xhci-using-correct-specification-chapter-re.patch new file mode 100644 index 00000000000000..08c2a63cc5f0f9 --- /dev/null +++ b/patches.renesas/0204-usb-host-xhci-using-correct-specification-chapter-re.patch @@ -0,0 +1,34 @@ +From 518c497272f31e9b43f2ba7dcd69b0b02001ef64 Mon Sep 17 00:00:00 2001 +From: Peter Chen <peter.chen@nxp.com> +Date: Wed, 19 Apr 2017 16:55:50 +0300 +Subject: [PATCH 204/286] usb: host: xhci: using correct specification chapter + reference for DCBAAP + +Using correct specification chapter reference for DCBAAP +(Device Context Base Address Array Pointer). + +Signed-off-by: Peter Chen <peter.chen@nxp.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 724e882daeb67d58d04a3d0f8cccdd33775bb9bb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 9b37ef13bf3a..87169f5dd4de 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -2434,7 +2434,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) + writel(val, &xhci->op_regs->config_reg); + + /* +- * Section 5.4.8 - doorbell array must be ++ * xHCI section 5.4.6 - doorbell array must be + * "physically contiguous and 64-byte (cache line) aligned". + */ + xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, +-- +2.13.3 + diff --git a/patches.renesas/0205-usb-host-xhci-delete-sp_dma_buffers-for-scratchpad.patch b/patches.renesas/0205-usb-host-xhci-delete-sp_dma_buffers-for-scratchpad.patch new file mode 100644 index 00000000000000..26a3c8c39df5ba --- /dev/null +++ b/patches.renesas/0205-usb-host-xhci-delete-sp_dma_buffers-for-scratchpad.patch @@ -0,0 +1,88 @@ +From 061a8f44430c7be41c541a35e8993150e0412248 Mon Sep 17 00:00:00 2001 +From: Peter Chen <peter.chen@nxp.com> +Date: Wed, 19 Apr 2017 16:55:51 +0300 +Subject: [PATCH 205/286] usb: host: xhci: delete sp_dma_buffers for scratchpad + +We already have sp_array to store each scratch buffer address for xHC, +it doesn't need another sp_dma_buffers array to store it. + +Signed-off-by: Peter Chen <peter.chen@nxp.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 314eaf7dec13b975e51c8faf980f7b0f4e20b3e9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 18 ++++-------------- + drivers/usb/host/xhci.h | 1 - + 2 files changed, 4 insertions(+), 15 deletions(-) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index 87169f5dd4de..ea1308a7b814 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -1721,36 +1721,27 @@ static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) + if (!xhci->scratchpad->sp_buffers) + goto fail_sp3; + +- xhci->scratchpad->sp_dma_buffers = +- kzalloc(sizeof(dma_addr_t) * num_sp, flags); +- +- if (!xhci->scratchpad->sp_dma_buffers) +- goto fail_sp4; +- + xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); + for (i = 0; i < num_sp; i++) { + dma_addr_t dma; + void *buf = dma_zalloc_coherent(dev, xhci->page_size, &dma, + flags); + if (!buf) +- goto fail_sp5; ++ goto fail_sp4; + + xhci->scratchpad->sp_array[i] = dma; + xhci->scratchpad->sp_buffers[i] = buf; +- xhci->scratchpad->sp_dma_buffers[i] = dma; + } + + return 0; + +- fail_sp5: ++ fail_sp4: + for (i = i - 1; i >= 0; i--) { + dma_free_coherent(dev, xhci->page_size, + xhci->scratchpad->sp_buffers[i], +- xhci->scratchpad->sp_dma_buffers[i]); ++ xhci->scratchpad->sp_array[i]); + } +- kfree(xhci->scratchpad->sp_dma_buffers); + +- fail_sp4: + kfree(xhci->scratchpad->sp_buffers); + + fail_sp3: +@@ -1780,9 +1771,8 @@ static void scratchpad_free(struct xhci_hcd *xhci) + for (i = 0; i < num_sp; i++) { + dma_free_coherent(dev, xhci->page_size, + xhci->scratchpad->sp_buffers[i], +- xhci->scratchpad->sp_dma_buffers[i]); ++ xhci->scratchpad->sp_array[i]); + } +- kfree(xhci->scratchpad->sp_dma_buffers); + kfree(xhci->scratchpad->sp_buffers); + dma_free_coherent(dev, num_sp * sizeof(u64), + xhci->scratchpad->sp_array, +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index 914968c662c9..c23d5312c714 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1606,7 +1606,6 @@ struct xhci_scratchpad { + u64 *sp_array; + dma_addr_t sp_dma; + void **sp_buffers; +- dma_addr_t *sp_dma_buffers; + }; + + struct urb_priv { +-- +2.13.3 + diff --git a/patches.renesas/0206-usb-host-xhci-remove-ifdef-around-PM-functions.patch b/patches.renesas/0206-usb-host-xhci-remove-ifdef-around-PM-functions.patch new file mode 100644 index 00000000000000..21489a1b0ef385 --- /dev/null +++ b/patches.renesas/0206-usb-host-xhci-remove-ifdef-around-PM-functions.patch @@ -0,0 +1,97 @@ +From 5106e20c153d4a513b44cef20545120449099563 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Fri, 21 Apr 2017 23:42:54 +0200 +Subject: [PATCH 206/286] usb: host: xhci: remove #ifdef around PM functions + +The #ifdef is slightly wrong as it doesn't cover the xhci_priv_resume_quirk() +function, causing a harmless warning: + +drivers/usb/host/xhci-plat.c:58:12: error: 'xhci_priv_resume_quirk' defined but not used [-Werror=unused-function] + static int xhci_priv_resume_quirk(struct usb_hcd *hcd) + +A simpler way to do this correctly is to use __maybe_unused annotations +that let the compiler silently drop the functions when there is no +reference. + +Fixes: b0c69b4bace3 ("usb: host: plat: Enable xHCI plat runtime PM") +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit d852ed98f62e0d44f594adb850b3d6cedb5c9292) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-plat.c | 12 ++++-------- + drivers/usb/host/xhci.h | 5 ----- + 2 files changed, 4 insertions(+), 13 deletions(-) + +diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c +index 8728ce7bf245..f6a97f67f5ad 100644 +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -336,8 +336,7 @@ static int xhci_plat_remove(struct platform_device *dev) + return 0; + } + +-#ifdef CONFIG_PM_SLEEP +-static int xhci_plat_suspend(struct device *dev) ++static int __maybe_unused xhci_plat_suspend(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -359,7 +358,7 @@ static int xhci_plat_suspend(struct device *dev) + return ret; + } + +-static int xhci_plat_resume(struct device *dev) ++static int __maybe_unused xhci_plat_resume(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -374,10 +373,8 @@ static int xhci_plat_resume(struct device *dev) + + return xhci_resume(xhci, 0); + } +-#endif /* CONFIG_PM_SLEEP */ + +-#ifdef CONFIG_PM +-static int xhci_plat_runtime_suspend(struct device *dev) ++static int __maybe_unused xhci_plat_runtime_suspend(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); +@@ -385,14 +382,13 @@ static int xhci_plat_runtime_suspend(struct device *dev) + return xhci_suspend(xhci, true); + } + +-static int xhci_plat_runtime_resume(struct device *dev) ++static int __maybe_unused xhci_plat_runtime_resume(struct device *dev) + { + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + + return xhci_resume(xhci, 0); + } +-#endif /* CONFIG_PM */ + + static const struct dev_pm_ops xhci_plat_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(xhci_plat_suspend, xhci_plat_resume) +diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h +index c23d5312c714..88350319b952 100644 +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -2005,13 +2005,8 @@ void xhci_init_driver(struct hc_driver *drv, + int xhci_disable_slot(struct xhci_hcd *xhci, + struct xhci_command *command, u32 slot_id); + +-#ifdef CONFIG_PM + int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); + int xhci_resume(struct xhci_hcd *xhci, bool hibernated); +-#else +-#define xhci_suspend NULL +-#define xhci_resume NULL +-#endif + + irqreturn_t xhci_irq(struct usb_hcd *hcd); + irqreturn_t xhci_msi_irq(int irq, void *hcd); +-- +2.13.3 + diff --git a/patches.renesas/0207-media-v4l-Add-metadata-buffer-type-and-format.patch b/patches.renesas/0207-media-v4l-Add-metadata-buffer-type-and-format.patch new file mode 100644 index 00000000000000..cdd036c1e9e451 --- /dev/null +++ b/patches.renesas/0207-media-v4l-Add-metadata-buffer-type-and-format.patch @@ -0,0 +1,505 @@ +From dcb49656a8af3d454bb75c06cb30a2eb8651c081 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 12 Apr 2016 19:40:46 -0300 +Subject: [PATCH 207/286] [media] v4l: Add metadata buffer type and format + +The metadata buffer type is used to transfer metadata between userspace +and kernelspace through a V4L2 buffers queue. It comes with a new +metadata capture capability and format description. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Guennadi Liakhovetski <guennadi.liakhovetski@intel.com> +Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +[hans.verkuil@cisco.com: removed left-over 'experimental' note] +[hans.verkuil@cisco.com: add newline after _v4l2-meta-format label] + +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit fb9ffa6a7f7ef39cc0f14f417b66411be5492512) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/media/uapi/v4l/buffer.rst | 3 ++ + Documentation/media/uapi/v4l/dev-meta.rst | 58 ++++++++++++++++++++++++ + Documentation/media/uapi/v4l/devices.rst | 1 + + Documentation/media/uapi/v4l/vidioc-querycap.rst | 3 ++ + Documentation/media/videodev2.h.rst.exceptions | 2 + + drivers/media/v4l2-core/v4l2-compat-ioctl32.c | 19 ++++++++ + drivers/media/v4l2-core/v4l2-dev.c | 16 ++++--- + drivers/media/v4l2-core/v4l2-ioctl.c | 34 ++++++++++++++ + drivers/media/v4l2-core/videobuf2-v4l2.c | 3 ++ + include/media/v4l2-ioctl.h | 17 +++++++ + include/trace/events/v4l2.h | 1 + + include/uapi/linux/videodev2.h | 13 ++++++ + 12 files changed, 164 insertions(+), 6 deletions(-) + create mode 100644 Documentation/media/uapi/v4l/dev-meta.rst + +diff --git a/Documentation/media/uapi/v4l/buffer.rst b/Documentation/media/uapi/v4l/buffer.rst +index ac58966ccb9b..537fd65daffd 100644 +--- a/Documentation/media/uapi/v4l/buffer.rst ++++ b/Documentation/media/uapi/v4l/buffer.rst +@@ -330,6 +330,9 @@ enum v4l2_buf_type + - 12 + - Buffer for Software Defined Radio (SDR) output stream, see + :ref:`sdr`. ++ * - ``V4L2_BUF_TYPE_META_CAPTURE`` ++ - 13 ++ - Buffer for metadata capture, see :ref:`metadata`. + + + +diff --git a/Documentation/media/uapi/v4l/dev-meta.rst b/Documentation/media/uapi/v4l/dev-meta.rst +new file mode 100644 +index 000000000000..62518adfe37b +--- /dev/null ++++ b/Documentation/media/uapi/v4l/dev-meta.rst +@@ -0,0 +1,58 @@ ++.. -*- coding: utf-8; mode: rst -*- ++ ++.. _metadata: ++ ++****************** ++Metadata Interface ++****************** ++ ++Metadata refers to any non-image data that supplements video frames with ++additional information. This may include statistics computed over the image ++or frame capture parameters supplied by the image source. This interface is ++intended for transfer of metadata to userspace and control of that operation. ++ ++The metadata interface is implemented on video capture device nodes. The device ++can be dedicated to metadata or can implement both video and metadata capture ++as specified in its reported capabilities. ++ ++Querying Capabilities ++===================== ++ ++Device nodes supporting the metadata interface set the ``V4L2_CAP_META_CAPTURE`` ++flag in the ``device_caps`` field of the ++:c:type:`v4l2_capability` structure returned by the :c:func:`VIDIOC_QUERYCAP` ++ioctl. That flag means the device can capture metadata to memory. ++ ++At least one of the read/write or streaming I/O methods must be supported. ++ ++ ++Data Format Negotiation ++======================= ++ ++The metadata device uses the :ref:`format` ioctls to select the capture format. ++The metadata buffer content format is bound to that selected format. In addition ++to the basic :ref:`format` ioctls, the :c:func:`VIDIOC_ENUM_FMT` ioctl must be ++supported as well. ++ ++To use the :ref:`format` ioctls applications set the ``type`` field of the ++:c:type:`v4l2_format` structure to ``V4L2_BUF_TYPE_META_CAPTURE`` and use the ++:c:type:`v4l2_meta_format` ``meta`` member of the ``fmt`` union as needed per ++the desired operation. Both drivers and applications must set the remainder of ++the :c:type:`v4l2_format` structure to 0. ++ ++.. _v4l2-meta-format: ++ ++.. flat-table:: struct v4l2_meta_format ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``dataformat`` ++ - The data format, set by the application. This is a little endian ++ :ref:`four character code <v4l2-fourcc>`. V4L2 defines metadata formats ++ in :ref:`meta-formats`. ++ * - __u32 ++ - ``buffersize`` ++ - Maximum buffer size in bytes required for data. The value is set by the ++ driver. +diff --git a/Documentation/media/uapi/v4l/devices.rst b/Documentation/media/uapi/v4l/devices.rst +index 5c3d6c29e12c..fb7f8c26cf09 100644 +--- a/Documentation/media/uapi/v4l/devices.rst ++++ b/Documentation/media/uapi/v4l/devices.rst +@@ -25,3 +25,4 @@ Interfaces + dev-touch + dev-event + dev-subdev ++ dev-meta +diff --git a/Documentation/media/uapi/v4l/vidioc-querycap.rst b/Documentation/media/uapi/v4l/vidioc-querycap.rst +index 165d8314327e..12e0d9a63cd8 100644 +--- a/Documentation/media/uapi/v4l/vidioc-querycap.rst ++++ b/Documentation/media/uapi/v4l/vidioc-querycap.rst +@@ -236,6 +236,9 @@ specification the ioctl returns an ``EINVAL`` error code. + * - ``V4L2_CAP_SDR_OUTPUT`` + - 0x00400000 + - The device supports the :ref:`SDR Output <sdr>` interface. ++ * - ``V4L2_CAP_META_CAPTURE`` ++ - 0x00800000 ++ - The device supports the :ref:`metadata` capture interface. + * - ``V4L2_CAP_READWRITE`` + - 0x01000000 + - The device supports the :ref:`read() <rw>` and/or +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index 1d3f27d922b2..20f72a201ca5 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -27,6 +27,7 @@ replace symbol V4L2_FIELD_SEQ_TB :c:type:`v4l2_field` + replace symbol V4L2_FIELD_TOP :c:type:`v4l2_field` + + # Documented enum v4l2_buf_type ++replace symbol V4L2_BUF_TYPE_META_CAPTURE :c:type:`v4l2_buf_type` + replace symbol V4L2_BUF_TYPE_SDR_CAPTURE :c:type:`v4l2_buf_type` + replace symbol V4L2_BUF_TYPE_SDR_OUTPUT :c:type:`v4l2_buf_type` + replace symbol V4L2_BUF_TYPE_SLICED_VBI_CAPTURE :c:type:`v4l2_buf_type` +@@ -148,6 +149,7 @@ replace define V4L2_CAP_MODULATOR device-capabilities + replace define V4L2_CAP_SDR_CAPTURE device-capabilities + replace define V4L2_CAP_EXT_PIX_FORMAT device-capabilities + replace define V4L2_CAP_SDR_OUTPUT device-capabilities ++replace define V4L2_CAP_META_CAPTURE device-capabilities + replace define V4L2_CAP_READWRITE device-capabilities + replace define V4L2_CAP_ASYNCIO device-capabilities + replace define V4L2_CAP_STREAMING device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +index bacecbd68a6d..da2d836e8887 100644 +--- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c ++++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c +@@ -161,6 +161,20 @@ static inline int put_v4l2_sdr_format(struct v4l2_sdr_format *kp, struct v4l2_sd + return 0; + } + ++static inline int get_v4l2_meta_format(struct v4l2_meta_format *kp, struct v4l2_meta_format __user *up) ++{ ++ if (copy_from_user(kp, up, sizeof(struct v4l2_meta_format))) ++ return -EFAULT; ++ return 0; ++} ++ ++static inline int put_v4l2_meta_format(struct v4l2_meta_format *kp, struct v4l2_meta_format __user *up) ++{ ++ if (copy_to_user(up, kp, sizeof(struct v4l2_meta_format))) ++ return -EFAULT; ++ return 0; ++} ++ + struct v4l2_format32 { + __u32 type; /* enum v4l2_buf_type */ + union { +@@ -170,6 +184,7 @@ struct v4l2_format32 { + struct v4l2_vbi_format vbi; + struct v4l2_sliced_vbi_format sliced; + struct v4l2_sdr_format sdr; ++ struct v4l2_meta_format meta; + __u8 raw_data[200]; /* user-defined */ + } fmt; + }; +@@ -216,6 +231,8 @@ static int __get_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __us + case V4L2_BUF_TYPE_SDR_CAPTURE: + case V4L2_BUF_TYPE_SDR_OUTPUT: + return get_v4l2_sdr_format(&kp->fmt.sdr, &up->fmt.sdr); ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ return get_v4l2_meta_format(&kp->fmt.meta, &up->fmt.meta); + default: + pr_info("compat_ioctl32: unexpected VIDIOC_FMT type %d\n", + kp->type); +@@ -263,6 +280,8 @@ static int __put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __us + case V4L2_BUF_TYPE_SDR_CAPTURE: + case V4L2_BUF_TYPE_SDR_OUTPUT: + return put_v4l2_sdr_format(&kp->fmt.sdr, &up->fmt.sdr); ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ return put_v4l2_meta_format(&kp->fmt.meta, &up->fmt.meta); + default: + pr_info("compat_ioctl32: unexpected VIDIOC_FMT type %d\n", + kp->type); +diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c +index 8be561ab2615..6541d5597966 100644 +--- a/drivers/media/v4l2-core/v4l2-dev.c ++++ b/drivers/media/v4l2-core/v4l2-dev.c +@@ -575,30 +575,34 @@ static void determine_valid_ioctls(struct video_device *vdev) + set_bit(_IOC_NR(VIDIOC_ENUM_FREQ_BANDS), valid_ioctls); + + if (is_vid || is_tch) { +- /* video specific ioctls */ ++ /* video and metadata specific ioctls */ + if ((is_rx && (ops->vidioc_enum_fmt_vid_cap || + ops->vidioc_enum_fmt_vid_cap_mplane || +- ops->vidioc_enum_fmt_vid_overlay)) || ++ ops->vidioc_enum_fmt_vid_overlay || ++ ops->vidioc_enum_fmt_meta_cap)) || + (is_tx && (ops->vidioc_enum_fmt_vid_out || + ops->vidioc_enum_fmt_vid_out_mplane))) + set_bit(_IOC_NR(VIDIOC_ENUM_FMT), valid_ioctls); + if ((is_rx && (ops->vidioc_g_fmt_vid_cap || + ops->vidioc_g_fmt_vid_cap_mplane || +- ops->vidioc_g_fmt_vid_overlay)) || ++ ops->vidioc_g_fmt_vid_overlay || ++ ops->vidioc_g_fmt_meta_cap)) || + (is_tx && (ops->vidioc_g_fmt_vid_out || + ops->vidioc_g_fmt_vid_out_mplane || + ops->vidioc_g_fmt_vid_out_overlay))) + set_bit(_IOC_NR(VIDIOC_G_FMT), valid_ioctls); + if ((is_rx && (ops->vidioc_s_fmt_vid_cap || + ops->vidioc_s_fmt_vid_cap_mplane || +- ops->vidioc_s_fmt_vid_overlay)) || ++ ops->vidioc_s_fmt_vid_overlay || ++ ops->vidioc_s_fmt_meta_cap)) || + (is_tx && (ops->vidioc_s_fmt_vid_out || + ops->vidioc_s_fmt_vid_out_mplane || + ops->vidioc_s_fmt_vid_out_overlay))) + set_bit(_IOC_NR(VIDIOC_S_FMT), valid_ioctls); + if ((is_rx && (ops->vidioc_try_fmt_vid_cap || + ops->vidioc_try_fmt_vid_cap_mplane || +- ops->vidioc_try_fmt_vid_overlay)) || ++ ops->vidioc_try_fmt_vid_overlay || ++ ops->vidioc_try_fmt_meta_cap)) || + (is_tx && (ops->vidioc_try_fmt_vid_out || + ops->vidioc_try_fmt_vid_out_mplane || + ops->vidioc_try_fmt_vid_out_overlay))) +@@ -664,7 +668,7 @@ static void determine_valid_ioctls(struct video_device *vdev) + } + + if (is_vid || is_vbi || is_sdr || is_tch) { +- /* ioctls valid for video, vbi or sdr */ ++ /* ioctls valid for video, metadata, vbi or sdr */ + SET_VALID_IOCTL(ops, VIDIOC_REQBUFS, vidioc_reqbufs); + SET_VALID_IOCTL(ops, VIDIOC_QUERYBUF, vidioc_querybuf); + SET_VALID_IOCTL(ops, VIDIOC_QBUF, vidioc_qbuf); +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index 5c49351af7ae..b1e4fff556f0 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -155,6 +155,7 @@ const char *v4l2_type_names[] = { + [V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE] = "vid-out-mplane", + [V4L2_BUF_TYPE_SDR_CAPTURE] = "sdr-cap", + [V4L2_BUF_TYPE_SDR_OUTPUT] = "sdr-out", ++ [V4L2_BUF_TYPE_META_CAPTURE] = "meta-cap", + }; + EXPORT_SYMBOL(v4l2_type_names); + +@@ -249,6 +250,7 @@ static void v4l_print_format(const void *arg, bool write_only) + const struct v4l2_sliced_vbi_format *sliced; + const struct v4l2_window *win; + const struct v4l2_sdr_format *sdr; ++ const struct v4l2_meta_format *meta; + unsigned i; + + pr_cont("type=%s", prt_names(p->type, v4l2_type_names)); +@@ -336,6 +338,15 @@ static void v4l_print_format(const void *arg, bool write_only) + (sdr->pixelformat >> 16) & 0xff, + (sdr->pixelformat >> 24) & 0xff); + break; ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ meta = &p->fmt.meta; ++ pr_cont(", dataformat=%c%c%c%c, buffersize=%u\n", ++ (meta->dataformat >> 0) & 0xff, ++ (meta->dataformat >> 8) & 0xff, ++ (meta->dataformat >> 16) & 0xff, ++ (meta->dataformat >> 24) & 0xff, ++ meta->buffersize); ++ break; + } + } + +@@ -982,6 +993,10 @@ static int check_fmt(struct file *file, enum v4l2_buf_type type) + if (is_sdr && is_tx && ops->vidioc_g_fmt_sdr_out) + return 0; + break; ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ if (is_vid && is_rx && ops->vidioc_g_fmt_meta_cap) ++ return 0; ++ break; + default: + break; + } +@@ -1357,6 +1372,11 @@ static int v4l_enum_fmt(const struct v4l2_ioctl_ops *ops, + break; + ret = ops->vidioc_enum_fmt_sdr_out(file, fh, arg); + break; ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ if (unlikely(!is_rx || !is_vid || !ops->vidioc_enum_fmt_meta_cap)) ++ break; ++ ret = ops->vidioc_enum_fmt_meta_cap(file, fh, arg); ++ break; + } + if (ret == 0) + v4l_fill_fmtdesc(p); +@@ -1456,6 +1476,10 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops, + if (unlikely(!is_tx || !is_sdr || !ops->vidioc_g_fmt_sdr_out)) + break; + return ops->vidioc_g_fmt_sdr_out(file, fh, arg); ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ if (unlikely(!is_rx || !is_vid || !ops->vidioc_g_fmt_meta_cap)) ++ break; ++ return ops->vidioc_g_fmt_meta_cap(file, fh, arg); + } + return -EINVAL; + } +@@ -1561,6 +1585,11 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_s_fmt_sdr_out(file, fh, arg); ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ if (unlikely(!is_rx || !is_vid || !ops->vidioc_s_fmt_meta_cap)) ++ break; ++ CLEAR_AFTER_FIELD(p, fmt.meta); ++ return ops->vidioc_s_fmt_meta_cap(file, fh, arg); + } + return -EINVAL; + } +@@ -1646,6 +1675,11 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, + break; + CLEAR_AFTER_FIELD(p, fmt.sdr); + return ops->vidioc_try_fmt_sdr_out(file, fh, arg); ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ if (unlikely(!is_rx || !is_vid || !ops->vidioc_try_fmt_meta_cap)) ++ break; ++ CLEAR_AFTER_FIELD(p, fmt.meta); ++ return ops->vidioc_try_fmt_meta_cap(file, fh, arg); + } + return -EINVAL; + } +diff --git a/drivers/media/v4l2-core/videobuf2-v4l2.c b/drivers/media/v4l2-core/videobuf2-v4l2.c +index 52ef8833f6b6..12e12f932b6b 100644 +--- a/drivers/media/v4l2-core/videobuf2-v4l2.c ++++ b/drivers/media/v4l2-core/videobuf2-v4l2.c +@@ -546,6 +546,9 @@ int vb2_create_bufs(struct vb2_queue *q, struct v4l2_create_buffers *create) + case V4L2_BUF_TYPE_SDR_OUTPUT: + requested_sizes[0] = f->fmt.sdr.buffersize; + break; ++ case V4L2_BUF_TYPE_META_CAPTURE: ++ requested_sizes[0] = f->fmt.meta.buffersize; ++ break; + default: + return -EINVAL; + } +diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h +index 574ff2ae94be..b6433cc5964b 100644 +--- a/include/media/v4l2-ioctl.h ++++ b/include/media/v4l2-ioctl.h +@@ -43,6 +43,9 @@ struct v4l2_fh; + * @vidioc_enum_fmt_sdr_out: pointer to the function that implements + * :ref:`VIDIOC_ENUM_FMT <vidioc_enum_fmt>` ioctl logic + * for Software Defined Radio output ++ * @vidioc_enum_fmt_meta_cap: pointer to the function that implements ++ * :ref:`VIDIOC_ENUM_FMT <vidioc_enum_fmt>` ioctl logic ++ * for metadata capture + * @vidioc_g_fmt_vid_cap: pointer to the function that implements + * :ref:`VIDIOC_G_FMT <vidioc_g_fmt>` ioctl logic for video capture + * in single plane mode +@@ -73,6 +76,8 @@ struct v4l2_fh; + * @vidioc_g_fmt_sdr_out: pointer to the function that implements + * :ref:`VIDIOC_G_FMT <vidioc_g_fmt>` ioctl logic for Software Defined + * Radio output ++ * @vidioc_g_fmt_meta_cap: pointer to the function that implements ++ * :ref:`VIDIOC_G_FMT <vidioc_g_fmt>` ioctl logic for metadata capture + * @vidioc_s_fmt_vid_cap: pointer to the function that implements + * :ref:`VIDIOC_S_FMT <vidioc_g_fmt>` ioctl logic for video capture + * in single plane mode +@@ -103,6 +108,8 @@ struct v4l2_fh; + * @vidioc_s_fmt_sdr_out: pointer to the function that implements + * :ref:`VIDIOC_S_FMT <vidioc_g_fmt>` ioctl logic for Software Defined + * Radio output ++ * @vidioc_s_fmt_meta_cap: pointer to the function that implements ++ * :ref:`VIDIOC_S_FMT <vidioc_g_fmt>` ioctl logic for metadata capture + * @vidioc_try_fmt_vid_cap: pointer to the function that implements + * :ref:`VIDIOC_TRY_FMT <vidioc_g_fmt>` ioctl logic for video capture + * in single plane mode +@@ -135,6 +142,8 @@ struct v4l2_fh; + * @vidioc_try_fmt_sdr_out: pointer to the function that implements + * :ref:`VIDIOC_TRY_FMT <vidioc_g_fmt>` ioctl logic for Software Defined + * Radio output ++ * @vidioc_try_fmt_meta_cap: pointer to the function that implements ++ * :ref:`VIDIOC_TRY_FMT <vidioc_g_fmt>` ioctl logic for metadata capture + * @vidioc_reqbufs: pointer to the function that implements + * :ref:`VIDIOC_REQBUFS <vidioc_reqbufs>` ioctl + * @vidioc_querybuf: pointer to the function that implements +@@ -305,6 +314,8 @@ struct v4l2_ioctl_ops { + struct v4l2_fmtdesc *f); + int (*vidioc_enum_fmt_sdr_out)(struct file *file, void *fh, + struct v4l2_fmtdesc *f); ++ int (*vidioc_enum_fmt_meta_cap)(struct file *file, void *fh, ++ struct v4l2_fmtdesc *f); + + /* VIDIOC_G_FMT handlers */ + int (*vidioc_g_fmt_vid_cap)(struct file *file, void *fh, +@@ -331,6 +342,8 @@ struct v4l2_ioctl_ops { + struct v4l2_format *f); + int (*vidioc_g_fmt_sdr_out)(struct file *file, void *fh, + struct v4l2_format *f); ++ int (*vidioc_g_fmt_meta_cap)(struct file *file, void *fh, ++ struct v4l2_format *f); + + /* VIDIOC_S_FMT handlers */ + int (*vidioc_s_fmt_vid_cap)(struct file *file, void *fh, +@@ -357,6 +370,8 @@ struct v4l2_ioctl_ops { + struct v4l2_format *f); + int (*vidioc_s_fmt_sdr_out)(struct file *file, void *fh, + struct v4l2_format *f); ++ int (*vidioc_s_fmt_meta_cap)(struct file *file, void *fh, ++ struct v4l2_format *f); + + /* VIDIOC_TRY_FMT handlers */ + int (*vidioc_try_fmt_vid_cap)(struct file *file, void *fh, +@@ -383,6 +398,8 @@ struct v4l2_ioctl_ops { + struct v4l2_format *f); + int (*vidioc_try_fmt_sdr_out)(struct file *file, void *fh, + struct v4l2_format *f); ++ int (*vidioc_try_fmt_meta_cap)(struct file *file, void *fh, ++ struct v4l2_format *f); + + /* Buffer handlers */ + int (*vidioc_reqbufs)(struct file *file, void *fh, +diff --git a/include/trace/events/v4l2.h b/include/trace/events/v4l2.h +index ee7754c6e4a1..b3a85b3df53e 100644 +--- a/include/trace/events/v4l2.h ++++ b/include/trace/events/v4l2.h +@@ -29,6 +29,7 @@ + EM( V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, "VIDEO_OUTPUT_MPLANE" ) \ + EM( V4L2_BUF_TYPE_SDR_CAPTURE, "SDR_CAPTURE" ) \ + EM( V4L2_BUF_TYPE_SDR_OUTPUT, "SDR_OUTPUT" ) \ ++ EM( V4L2_BUF_TYPE_META_CAPTURE, "META_CAPTURE" ) \ + EMe(V4L2_BUF_TYPE_PRIVATE, "PRIVATE" ) + + SHOW_TYPE +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 803e58c1c0b1..2e0c8a9df8af 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -143,6 +143,7 @@ enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10, + V4L2_BUF_TYPE_SDR_CAPTURE = 11, + V4L2_BUF_TYPE_SDR_OUTPUT = 12, ++ V4L2_BUF_TYPE_META_CAPTURE = 13, + /* Deprecated, do not use */ + V4L2_BUF_TYPE_PRIVATE = 0x80, + }; +@@ -453,6 +454,7 @@ struct v4l2_capability { + #define V4L2_CAP_SDR_CAPTURE 0x00100000 /* Is a SDR capture device */ + #define V4L2_CAP_EXT_PIX_FORMAT 0x00200000 /* Supports the extended pixel format */ + #define V4L2_CAP_SDR_OUTPUT 0x00400000 /* Is a SDR output device */ ++#define V4L2_CAP_META_CAPTURE 0x00800000 /* Is a metadata capture device */ + + #define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ + #define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ +@@ -2049,6 +2051,16 @@ struct v4l2_sdr_format { + } __attribute__ ((packed)); + + /** ++ * struct v4l2_meta_format - metadata format definition ++ * @dataformat: little endian four character code (fourcc) ++ * @buffersize: maximum size in bytes required for data ++ */ ++struct v4l2_meta_format { ++ __u32 dataformat; ++ __u32 buffersize; ++} __attribute__ ((packed)); ++ ++/** + * struct v4l2_format - stream data format + * @type: enum v4l2_buf_type; type of the data stream + * @pix: definition of an image format +@@ -2067,6 +2079,7 @@ struct v4l2_format { + struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ + struct v4l2_sliced_vbi_format sliced; /* V4L2_BUF_TYPE_SLICED_VBI_CAPTURE */ + struct v4l2_sdr_format sdr; /* V4L2_BUF_TYPE_SDR_CAPTURE */ ++ struct v4l2_meta_format meta; /* V4L2_BUF_TYPE_META_CAPTURE */ + __u8 raw_data[200]; /* user-defined */ + } fmt; + }; +-- +2.13.3 + diff --git a/patches.renesas/0208-media-v4l-vsp1-Add-histogram-support.patch b/patches.renesas/0208-media-v4l-vsp1-Add-histogram-support.patch new file mode 100644 index 00000000000000..2d14d8099ab6ae --- /dev/null +++ b/patches.renesas/0208-media-v4l-vsp1-Add-histogram-support.patch @@ -0,0 +1,790 @@ +From 3bb2173f582e52b15ed1529d1d08d723b39ca8b2 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 7 Sep 2016 08:58:49 -0300 +Subject: [PATCH 208/286] [media] v4l: vsp1: Add histogram support + +The histogram common code will be used to implement support for both the +HGO and HGT histogram computation engines. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 99362e32332b5ce591a67a632073668754f28b0d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/Kconfig | 1 + + drivers/media/platform/vsp1/Makefile | 1 + + drivers/media/platform/vsp1/vsp1_histo.c | 646 +++++++++++++++++++++++++++++++ + drivers/media/platform/vsp1/vsp1_histo.h | 84 ++++ + 4 files changed, 732 insertions(+) + create mode 100644 drivers/media/platform/vsp1/vsp1_histo.c + create mode 100644 drivers/media/platform/vsp1/vsp1_histo.h + +diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig +index f898862e2c69..d5f9e18b09af 100644 +--- a/drivers/media/platform/Kconfig ++++ b/drivers/media/platform/Kconfig +@@ -334,6 +334,7 @@ config VIDEO_RENESAS_VSP1 + depends on (ARCH_RENESAS && OF) || COMPILE_TEST + depends on (!ARM64 && !VIDEO_RENESAS_FCP) || VIDEO_RENESAS_FCP + select VIDEOBUF2_DMA_CONTIG ++ select VIDEOBUF2_VMALLOC + ---help--- + This is a V4L2 driver for the Renesas VSP1 video processing engine. + +diff --git a/drivers/media/platform/vsp1/Makefile b/drivers/media/platform/vsp1/Makefile +index 1328e1bd2143..c559536f7867 100644 +--- a/drivers/media/platform/vsp1/Makefile ++++ b/drivers/media/platform/vsp1/Makefile +@@ -3,6 +3,7 @@ vsp1-y += vsp1_dl.o vsp1_drm.o vsp1_video.o + vsp1-y += vsp1_rpf.o vsp1_rwpf.o vsp1_wpf.o + vsp1-y += vsp1_clu.o vsp1_hsit.o vsp1_lut.o + vsp1-y += vsp1_bru.o vsp1_sru.o vsp1_uds.o ++vsp1-y += vsp1_histo.o + vsp1-y += vsp1_lif.o + + obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1.o +diff --git a/drivers/media/platform/vsp1/vsp1_histo.c b/drivers/media/platform/vsp1/vsp1_histo.c +new file mode 100644 +index 000000000000..afab77cf4fa5 +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_histo.c +@@ -0,0 +1,646 @@ ++/* ++ * vsp1_histo.c -- R-Car VSP1 Histogram API ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Copyright (C) 2016 Laurent Pinchart ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/device.h> ++#include <linux/gfp.h> ++ ++#include <media/v4l2-ioctl.h> ++#include <media/v4l2-subdev.h> ++#include <media/videobuf2-vmalloc.h> ++ ++#include "vsp1.h" ++#include "vsp1_histo.h" ++#include "vsp1_pipe.h" ++ ++#define HISTO_MIN_SIZE 4U ++#define HISTO_MAX_SIZE 8192U ++ ++/* ----------------------------------------------------------------------------- ++ * Buffer Operations ++ */ ++ ++static inline struct vsp1_histogram_buffer * ++to_vsp1_histogram_buffer(struct vb2_v4l2_buffer *vbuf) ++{ ++ return container_of(vbuf, struct vsp1_histogram_buffer, buf); ++} ++ ++struct vsp1_histogram_buffer * ++vsp1_histogram_buffer_get(struct vsp1_histogram *histo) ++{ ++ struct vsp1_histogram_buffer *buf = NULL; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&histo->irqlock, flags); ++ ++ if (list_empty(&histo->irqqueue)) ++ goto done; ++ ++ buf = list_first_entry(&histo->irqqueue, struct vsp1_histogram_buffer, ++ queue); ++ list_del(&buf->queue); ++ histo->readout = true; ++ ++done: ++ spin_unlock_irqrestore(&histo->irqlock, flags); ++ return buf; ++} ++ ++void vsp1_histogram_buffer_complete(struct vsp1_histogram *histo, ++ struct vsp1_histogram_buffer *buf, ++ size_t size) ++{ ++ struct vsp1_pipeline *pipe = histo->pipe; ++ unsigned long flags; ++ ++ /* ++ * The pipeline pointer is guaranteed to be valid as this function is ++ * called from the frame completion interrupt handler, which can only ++ * occur when video streaming is active. ++ */ ++ buf->buf.sequence = pipe->sequence; ++ buf->buf.vb2_buf.timestamp = ktime_get_ns(); ++ vb2_set_plane_payload(&buf->buf.vb2_buf, 0, size); ++ vb2_buffer_done(&buf->buf.vb2_buf, VB2_BUF_STATE_DONE); ++ ++ spin_lock_irqsave(&histo->irqlock, flags); ++ histo->readout = false; ++ wake_up(&histo->wait_queue); ++ spin_unlock_irqrestore(&histo->irqlock, flags); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * videobuf2 Queue Operations ++ */ ++ ++static int histo_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct vsp1_histogram *histo = vb2_get_drv_priv(vq); ++ ++ if (*nplanes) { ++ if (*nplanes != 1) ++ return -EINVAL; ++ ++ if (sizes[0] < histo->data_size) ++ return -EINVAL; ++ ++ return 0; ++ } ++ ++ *nplanes = 1; ++ sizes[0] = histo->data_size; ++ ++ return 0; ++} ++ ++static int histo_buffer_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct vsp1_histogram *histo = vb2_get_drv_priv(vb->vb2_queue); ++ struct vsp1_histogram_buffer *buf = to_vsp1_histogram_buffer(vbuf); ++ ++ if (vb->num_planes != 1) ++ return -EINVAL; ++ ++ if (vb2_plane_size(vb, 0) < histo->data_size) ++ return -EINVAL; ++ ++ buf->addr = vb2_plane_vaddr(vb, 0); ++ ++ return 0; ++} ++ ++static void histo_buffer_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct vsp1_histogram *histo = vb2_get_drv_priv(vb->vb2_queue); ++ struct vsp1_histogram_buffer *buf = to_vsp1_histogram_buffer(vbuf); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&histo->irqlock, flags); ++ list_add_tail(&buf->queue, &histo->irqqueue); ++ spin_unlock_irqrestore(&histo->irqlock, flags); ++} ++ ++static int histo_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ return 0; ++} ++ ++static void histo_stop_streaming(struct vb2_queue *vq) ++{ ++ struct vsp1_histogram *histo = vb2_get_drv_priv(vq); ++ struct vsp1_histogram_buffer *buffer; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&histo->irqlock, flags); ++ ++ /* Remove all buffers from the IRQ queue. */ ++ list_for_each_entry(buffer, &histo->irqqueue, queue) ++ vb2_buffer_done(&buffer->buf.vb2_buf, VB2_BUF_STATE_ERROR); ++ INIT_LIST_HEAD(&histo->irqqueue); ++ ++ /* Wait for the buffer being read out (if any) to complete. */ ++ wait_event_lock_irq(histo->wait_queue, !histo->readout, histo->irqlock); ++ ++ spin_unlock_irqrestore(&histo->irqlock, flags); ++} ++ ++static const struct vb2_ops histo_video_queue_qops = { ++ .queue_setup = histo_queue_setup, ++ .buf_prepare = histo_buffer_prepare, ++ .buf_queue = histo_buffer_queue, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++ .start_streaming = histo_start_streaming, ++ .stop_streaming = histo_stop_streaming, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * V4L2 Subdevice Operations ++ */ ++ ++static int histo_enum_mbus_code(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_mbus_code_enum *code) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ ++ if (code->pad == HISTO_PAD_SOURCE) { ++ code->code = MEDIA_BUS_FMT_FIXED; ++ return 0; ++ } ++ ++ return vsp1_subdev_enum_mbus_code(subdev, cfg, code, histo->formats, ++ histo->num_formats); ++} ++ ++static int histo_enum_frame_size(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_frame_size_enum *fse) ++{ ++ if (fse->pad != HISTO_PAD_SINK) ++ return -EINVAL; ++ ++ return vsp1_subdev_enum_frame_size(subdev, cfg, fse, HISTO_MIN_SIZE, ++ HISTO_MIN_SIZE, HISTO_MAX_SIZE, ++ HISTO_MAX_SIZE); ++} ++ ++static int histo_get_selection(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ struct v4l2_subdev_pad_config *config; ++ struct v4l2_mbus_framefmt *format; ++ struct v4l2_rect *crop; ++ int ret = 0; ++ ++ if (sel->pad != HISTO_PAD_SINK) ++ return -EINVAL; ++ ++ mutex_lock(&histo->entity.lock); ++ ++ config = vsp1_entity_get_pad_config(&histo->entity, cfg, sel->which); ++ if (!config) { ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ switch (sel->target) { ++ case V4L2_SEL_TGT_COMPOSE_BOUNDS: ++ case V4L2_SEL_TGT_COMPOSE_DEFAULT: ++ crop = vsp1_entity_get_pad_selection(&histo->entity, config, ++ HISTO_PAD_SINK, ++ V4L2_SEL_TGT_CROP); ++ sel->r.left = 0; ++ sel->r.top = 0; ++ sel->r.width = crop->width; ++ sel->r.height = crop->height; ++ break; ++ ++ case V4L2_SEL_TGT_CROP_BOUNDS: ++ case V4L2_SEL_TGT_CROP_DEFAULT: ++ format = vsp1_entity_get_pad_format(&histo->entity, config, ++ HISTO_PAD_SINK); ++ sel->r.left = 0; ++ sel->r.top = 0; ++ sel->r.width = format->width; ++ sel->r.height = format->height; ++ break; ++ ++ case V4L2_SEL_TGT_COMPOSE: ++ case V4L2_SEL_TGT_CROP: ++ sel->r = *vsp1_entity_get_pad_selection(&histo->entity, config, ++ sel->pad, sel->target); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++done: ++ mutex_unlock(&histo->entity.lock); ++ return ret; ++} ++ ++static int histo_set_crop(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *config, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ struct v4l2_mbus_framefmt *format; ++ struct v4l2_rect *selection; ++ ++ /* The crop rectangle must be inside the input frame. */ ++ format = vsp1_entity_get_pad_format(&histo->entity, config, ++ HISTO_PAD_SINK); ++ sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1); ++ sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1); ++ sel->r.width = clamp_t(unsigned int, sel->r.width, HISTO_MIN_SIZE, ++ format->width - sel->r.left); ++ sel->r.height = clamp_t(unsigned int, sel->r.height, HISTO_MIN_SIZE, ++ format->height - sel->r.top); ++ ++ /* Set the crop rectangle and reset the compose rectangle. */ ++ selection = vsp1_entity_get_pad_selection(&histo->entity, config, ++ sel->pad, V4L2_SEL_TGT_CROP); ++ *selection = sel->r; ++ ++ selection = vsp1_entity_get_pad_selection(&histo->entity, config, ++ sel->pad, ++ V4L2_SEL_TGT_COMPOSE); ++ *selection = sel->r; ++ ++ return 0; ++} ++ ++static int histo_set_compose(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *config, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ struct v4l2_rect *compose; ++ struct v4l2_rect *crop; ++ unsigned int ratio; ++ ++ /* ++ * The compose rectangle is used to configure downscaling, the top left ++ * corner is fixed to (0,0) and the size to 1/2 or 1/4 of the crop ++ * rectangle. ++ */ ++ sel->r.left = 0; ++ sel->r.top = 0; ++ ++ crop = vsp1_entity_get_pad_selection(&histo->entity, config, sel->pad, ++ V4L2_SEL_TGT_CROP); ++ ++ /* ++ * Clamp the width and height to acceptable values first and then ++ * compute the closest rounded dividing ratio. ++ * ++ * Ratio Rounded ratio ++ * -------------------------- ++ * [1.0 1.5[ 1 ++ * [1.5 3.0[ 2 ++ * [3.0 4.0] 4 ++ * ++ * The rounded ratio can be computed using ++ * ++ * 1 << (ceil(ratio * 2) / 3) ++ */ ++ sel->r.width = clamp(sel->r.width, crop->width / 4, crop->width); ++ ratio = 1 << (crop->width * 2 / sel->r.width / 3); ++ sel->r.width = crop->width / ratio; ++ ++ ++ sel->r.height = clamp(sel->r.height, crop->height / 4, crop->height); ++ ratio = 1 << (crop->height * 2 / sel->r.height / 3); ++ sel->r.height = crop->height / ratio; ++ ++ compose = vsp1_entity_get_pad_selection(&histo->entity, config, ++ sel->pad, ++ V4L2_SEL_TGT_COMPOSE); ++ *compose = sel->r; ++ ++ return 0; ++} ++ ++static int histo_set_selection(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ struct v4l2_subdev_pad_config *config; ++ int ret; ++ ++ if (sel->pad != HISTO_PAD_SINK) ++ return -EINVAL; ++ ++ mutex_lock(&histo->entity.lock); ++ ++ config = vsp1_entity_get_pad_config(&histo->entity, cfg, sel->which); ++ if (!config) { ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ if (sel->target == V4L2_SEL_TGT_CROP) ++ ret = histo_set_crop(subdev, config, sel); ++ else if (sel->target == V4L2_SEL_TGT_COMPOSE) ++ ret = histo_set_compose(subdev, config, sel); ++ else ++ ret = -EINVAL; ++ ++done: ++ mutex_unlock(&histo->entity.lock); ++ return ret; ++} ++ ++static int histo_get_format(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_format *fmt) ++{ ++ if (fmt->pad == HISTO_PAD_SOURCE) { ++ fmt->format.code = MEDIA_BUS_FMT_FIXED; ++ fmt->format.width = 0; ++ fmt->format.height = 0; ++ fmt->format.field = V4L2_FIELD_NONE; ++ fmt->format.colorspace = V4L2_COLORSPACE_RAW; ++ return 0; ++ } ++ ++ return vsp1_subdev_get_pad_format(subdev, cfg, fmt); ++} ++ ++static int histo_set_format(struct v4l2_subdev *subdev, ++ struct v4l2_subdev_pad_config *cfg, ++ struct v4l2_subdev_format *fmt) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(subdev); ++ struct v4l2_subdev_pad_config *config; ++ struct v4l2_mbus_framefmt *format; ++ struct v4l2_rect *selection; ++ unsigned int i; ++ int ret = 0; ++ ++ if (fmt->pad != HISTO_PAD_SINK) ++ return histo_get_format(subdev, cfg, fmt); ++ ++ mutex_lock(&histo->entity.lock); ++ ++ config = vsp1_entity_get_pad_config(&histo->entity, cfg, fmt->which); ++ if (!config) { ++ ret = -EINVAL; ++ goto done; ++ } ++ ++ /* ++ * Default to the first format if the requested format is not ++ * supported. ++ */ ++ for (i = 0; i < histo->num_formats; ++i) { ++ if (fmt->format.code == histo->formats[i]) ++ break; ++ } ++ if (i == histo->num_formats) ++ fmt->format.code = histo->formats[0]; ++ ++ format = vsp1_entity_get_pad_format(&histo->entity, config, fmt->pad); ++ ++ format->code = fmt->format.code; ++ format->width = clamp_t(unsigned int, fmt->format.width, ++ HISTO_MIN_SIZE, HISTO_MAX_SIZE); ++ format->height = clamp_t(unsigned int, fmt->format.height, ++ HISTO_MIN_SIZE, HISTO_MAX_SIZE); ++ format->field = V4L2_FIELD_NONE; ++ format->colorspace = V4L2_COLORSPACE_SRGB; ++ ++ fmt->format = *format; ++ ++ /* Reset the crop and compose rectangles */ ++ selection = vsp1_entity_get_pad_selection(&histo->entity, config, ++ fmt->pad, V4L2_SEL_TGT_CROP); ++ selection->left = 0; ++ selection->top = 0; ++ selection->width = format->width; ++ selection->height = format->height; ++ ++ selection = vsp1_entity_get_pad_selection(&histo->entity, config, ++ fmt->pad, ++ V4L2_SEL_TGT_COMPOSE); ++ selection->left = 0; ++ selection->top = 0; ++ selection->width = format->width; ++ selection->height = format->height; ++ ++done: ++ mutex_unlock(&histo->entity.lock); ++ return ret; ++} ++ ++static const struct v4l2_subdev_pad_ops histo_pad_ops = { ++ .enum_mbus_code = histo_enum_mbus_code, ++ .enum_frame_size = histo_enum_frame_size, ++ .get_fmt = histo_get_format, ++ .set_fmt = histo_set_format, ++ .get_selection = histo_get_selection, ++ .set_selection = histo_set_selection, ++}; ++ ++static const struct v4l2_subdev_ops histo_ops = { ++ .pad = &histo_pad_ops, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * V4L2 ioctls ++ */ ++ ++static int histo_v4l2_querycap(struct file *file, void *fh, ++ struct v4l2_capability *cap) ++{ ++ struct v4l2_fh *vfh = file->private_data; ++ struct vsp1_histogram *histo = vdev_to_histo(vfh->vdev); ++ ++ cap->capabilities = V4L2_CAP_DEVICE_CAPS | V4L2_CAP_STREAMING ++ | V4L2_CAP_VIDEO_CAPTURE_MPLANE ++ | V4L2_CAP_VIDEO_OUTPUT_MPLANE ++ | V4L2_CAP_META_CAPTURE; ++ cap->device_caps = V4L2_CAP_META_CAPTURE ++ | V4L2_CAP_STREAMING; ++ ++ strlcpy(cap->driver, "vsp1", sizeof(cap->driver)); ++ strlcpy(cap->card, histo->video.name, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", ++ dev_name(histo->entity.vsp1->dev)); ++ ++ return 0; ++} ++ ++static int histo_v4l2_enum_format(struct file *file, void *fh, ++ struct v4l2_fmtdesc *f) ++{ ++ struct v4l2_fh *vfh = file->private_data; ++ struct vsp1_histogram *histo = vdev_to_histo(vfh->vdev); ++ ++ if (f->index > 0 || f->type != histo->queue.type) ++ return -EINVAL; ++ ++ f->pixelformat = histo->meta_format; ++ ++ return 0; ++} ++ ++static int histo_v4l2_get_format(struct file *file, void *fh, ++ struct v4l2_format *format) ++{ ++ struct v4l2_fh *vfh = file->private_data; ++ struct vsp1_histogram *histo = vdev_to_histo(vfh->vdev); ++ struct v4l2_meta_format *meta = &format->fmt.meta; ++ ++ if (format->type != histo->queue.type) ++ return -EINVAL; ++ ++ memset(meta, 0, sizeof(*meta)); ++ ++ meta->dataformat = histo->meta_format; ++ meta->buffersize = histo->data_size; ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops histo_v4l2_ioctl_ops = { ++ .vidioc_querycap = histo_v4l2_querycap, ++ .vidioc_enum_fmt_meta_cap = histo_v4l2_enum_format, ++ .vidioc_g_fmt_meta_cap = histo_v4l2_get_format, ++ .vidioc_s_fmt_meta_cap = histo_v4l2_get_format, ++ .vidioc_try_fmt_meta_cap = histo_v4l2_get_format, ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * V4L2 File Operations ++ */ ++ ++static const struct v4l2_file_operations histo_v4l2_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = video_ioctl2, ++ .open = v4l2_fh_open, ++ .release = vb2_fop_release, ++ .poll = vb2_fop_poll, ++ .mmap = vb2_fop_mmap, ++}; ++ ++static void vsp1_histogram_cleanup(struct vsp1_histogram *histo) ++{ ++ if (video_is_registered(&histo->video)) ++ video_unregister_device(&histo->video); ++ ++ media_entity_cleanup(&histo->video.entity); ++} ++ ++void vsp1_histogram_destroy(struct vsp1_entity *entity) ++{ ++ struct vsp1_histogram *histo = subdev_to_histo(&entity->subdev); ++ ++ vsp1_histogram_cleanup(histo); ++} ++ ++int vsp1_histogram_init(struct vsp1_device *vsp1, struct vsp1_histogram *histo, ++ enum vsp1_entity_type type, const char *name, ++ const struct vsp1_entity_operations *ops, ++ const unsigned int *formats, unsigned int num_formats, ++ size_t data_size, u32 meta_format) ++{ ++ int ret; ++ ++ histo->formats = formats; ++ histo->num_formats = num_formats; ++ histo->data_size = data_size; ++ histo->meta_format = meta_format; ++ ++ histo->pad.flags = MEDIA_PAD_FL_SINK; ++ histo->video.vfl_dir = VFL_DIR_RX; ++ ++ mutex_init(&histo->lock); ++ spin_lock_init(&histo->irqlock); ++ INIT_LIST_HEAD(&histo->irqqueue); ++ init_waitqueue_head(&histo->wait_queue); ++ ++ /* Initialize the VSP entity... */ ++ histo->entity.ops = ops; ++ histo->entity.type = type; ++ ++ ret = vsp1_entity_init(vsp1, &histo->entity, name, 2, &histo_ops, ++ MEDIA_ENT_F_PROC_VIDEO_STATISTICS); ++ if (ret < 0) ++ return ret; ++ ++ /* ... and the media entity... */ ++ ret = media_entity_pads_init(&histo->video.entity, 1, &histo->pad); ++ if (ret < 0) ++ return ret; ++ ++ /* ... and the video node... */ ++ histo->video.v4l2_dev = &vsp1->v4l2_dev; ++ histo->video.fops = &histo_v4l2_fops; ++ snprintf(histo->video.name, sizeof(histo->video.name), ++ "%s histo", histo->entity.subdev.name); ++ histo->video.vfl_type = VFL_TYPE_GRABBER; ++ histo->video.release = video_device_release_empty; ++ histo->video.ioctl_ops = &histo_v4l2_ioctl_ops; ++ ++ video_set_drvdata(&histo->video, histo); ++ ++ /* ... and the buffers queue... */ ++ histo->queue.type = V4L2_BUF_TYPE_META_CAPTURE; ++ histo->queue.io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; ++ histo->queue.lock = &histo->lock; ++ histo->queue.drv_priv = histo; ++ histo->queue.buf_struct_size = sizeof(struct vsp1_histogram_buffer); ++ histo->queue.ops = &histo_video_queue_qops; ++ histo->queue.mem_ops = &vb2_vmalloc_memops; ++ histo->queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ histo->queue.dev = vsp1->dev; ++ ret = vb2_queue_init(&histo->queue); ++ if (ret < 0) { ++ dev_err(vsp1->dev, "failed to initialize vb2 queue\n"); ++ goto error; ++ } ++ ++ /* ... and register the video device. */ ++ histo->video.queue = &histo->queue; ++ ret = video_register_device(&histo->video, VFL_TYPE_GRABBER, -1); ++ if (ret < 0) { ++ dev_err(vsp1->dev, "failed to register video device\n"); ++ goto error; ++ } ++ ++ return 0; ++ ++error: ++ vsp1_histogram_cleanup(histo); ++ return ret; ++} +diff --git a/drivers/media/platform/vsp1/vsp1_histo.h b/drivers/media/platform/vsp1/vsp1_histo.h +new file mode 100644 +index 000000000000..af2874f6031d +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_histo.h +@@ -0,0 +1,84 @@ ++/* ++ * vsp1_histo.h -- R-Car VSP1 Histogram API ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * Copyright (C) 2016 Laurent Pinchart ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef __VSP1_HISTO_H__ ++#define __VSP1_HISTO_H__ ++ ++#include <linux/list.h> ++#include <linux/mutex.h> ++#include <linux/spinlock.h> ++ ++#include <media/media-entity.h> ++#include <media/v4l2-dev.h> ++#include <media/videobuf2-v4l2.h> ++ ++#include "vsp1_entity.h" ++ ++struct vsp1_device; ++struct vsp1_pipeline; ++ ++#define HISTO_PAD_SINK 0 ++#define HISTO_PAD_SOURCE 1 ++ ++struct vsp1_histogram_buffer { ++ struct vb2_v4l2_buffer buf; ++ struct list_head queue; ++ void *addr; ++}; ++ ++struct vsp1_histogram { ++ struct vsp1_pipeline *pipe; ++ ++ struct vsp1_entity entity; ++ struct video_device video; ++ struct media_pad pad; ++ ++ const u32 *formats; ++ unsigned int num_formats; ++ size_t data_size; ++ u32 meta_format; ++ ++ struct mutex lock; ++ struct vb2_queue queue; ++ ++ spinlock_t irqlock; ++ struct list_head irqqueue; ++ ++ wait_queue_head_t wait_queue; ++ bool readout; ++}; ++ ++static inline struct vsp1_histogram *vdev_to_histo(struct video_device *vdev) ++{ ++ return container_of(vdev, struct vsp1_histogram, video); ++} ++ ++static inline struct vsp1_histogram *subdev_to_histo(struct v4l2_subdev *subdev) ++{ ++ return container_of(subdev, struct vsp1_histogram, entity.subdev); ++} ++ ++int vsp1_histogram_init(struct vsp1_device *vsp1, struct vsp1_histogram *histo, ++ enum vsp1_entity_type type, const char *name, ++ const struct vsp1_entity_operations *ops, ++ const unsigned int *formats, unsigned int num_formats, ++ size_t data_size, u32 meta_format); ++void vsp1_histogram_destroy(struct vsp1_entity *entity); ++ ++struct vsp1_histogram_buffer * ++vsp1_histogram_buffer_get(struct vsp1_histogram *histo); ++void vsp1_histogram_buffer_complete(struct vsp1_histogram *histo, ++ struct vsp1_histogram_buffer *buf, ++ size_t size); ++ ++#endif /* __VSP1_HISTO_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0209-media-v4l-vsp1-Support-histogram-generators-in-pipel.patch b/patches.renesas/0209-media-v4l-vsp1-Support-histogram-generators-in-pipel.patch new file mode 100644 index 00000000000000..607c8020e52575 --- /dev/null +++ b/patches.renesas/0209-media-v4l-vsp1-Support-histogram-generators-in-pipel.patch @@ -0,0 +1,341 @@ +From d501b911bf10e28e5227dda7eb071f0799465eb7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 7 Sep 2016 09:09:53 -0300 +Subject: [PATCH 209/286] [media] v4l: vsp1: Support histogram generators in + pipeline configuration + +Histogram generators are single-pad entities that branch as leaf nodes +at any point in the pipeline. Make sure that pipeline traversal and +routing configuration support them correctly. + +Support for the actual HGO and HGT operation will come later. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit c8663c8e15c95a351296d9d284b0cad5d373234c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_drm.c | 2 +- + drivers/media/platform/vsp1/vsp1_drv.c | 4 +- + drivers/media/platform/vsp1/vsp1_entity.c | 124 ++++++++++++++++++++++++++---- + drivers/media/platform/vsp1/vsp1_entity.h | 8 +- + drivers/media/platform/vsp1/vsp1_pipe.c | 6 +- + drivers/media/platform/vsp1/vsp1_video.c | 18 ++--- + 6 files changed, 134 insertions(+), 28 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_drm.c b/drivers/media/platform/vsp1/vsp1_drm.c +index 6e161347088e..14215051cef4 100644 +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -496,7 +496,7 @@ void vsp1_du_atomic_flush(struct device *dev) + } + } + +- vsp1_entity_route_setup(entity, dl); ++ vsp1_entity_route_setup(entity, pipe, dl); + + if (entity->ops->configure) { + entity->ops->configure(entity, pipe, dl, +diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c +index 8d1e61b353bb..83a6669a6328 100644 +--- a/drivers/media/platform/vsp1/vsp1_drv.c ++++ b/drivers/media/platform/vsp1/vsp1_drv.c +@@ -105,7 +105,9 @@ static int vsp1_create_sink_links(struct vsp1_device *vsp1, + if (source->type == sink->type) + continue; + +- if (source->type == VSP1_ENTITY_LIF || ++ if (source->type == VSP1_ENTITY_HGO || ++ source->type == VSP1_ENTITY_HGT || ++ source->type == VSP1_ENTITY_LIF || + source->type == VSP1_ENTITY_WPF) + continue; + +diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c +index 12eca5660d6e..88a2aae182ba 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.c ++++ b/drivers/media/platform/vsp1/vsp1_entity.c +@@ -21,6 +21,8 @@ + #include "vsp1.h" + #include "vsp1_dl.h" + #include "vsp1_entity.h" ++#include "vsp1_pipe.h" ++#include "vsp1_rwpf.h" + + static inline struct vsp1_entity * + media_entity_to_vsp1_entity(struct media_entity *entity) +@@ -28,11 +30,14 @@ media_entity_to_vsp1_entity(struct media_entity *entity) + return container_of(entity, struct vsp1_entity, subdev.entity); + } + +-void vsp1_entity_route_setup(struct vsp1_entity *source, ++void vsp1_entity_route_setup(struct vsp1_entity *entity, ++ struct vsp1_pipeline *pipe, + struct vsp1_dl_list *dl) + { ++ struct vsp1_entity *source; + struct vsp1_entity *sink; + ++ source = entity; + if (source->route->reg == 0) + return; + +@@ -283,25 +288,32 @@ int vsp1_subdev_enum_frame_size(struct v4l2_subdev *subdev, + * Media Operations + */ + +-int vsp1_entity_link_setup(struct media_entity *entity, +- const struct media_pad *local, +- const struct media_pad *remote, u32 flags) ++static int vsp1_entity_link_setup_source(const struct media_pad *source_pad, ++ const struct media_pad *sink_pad, ++ u32 flags) + { + struct vsp1_entity *source; + +- if (!(local->flags & MEDIA_PAD_FL_SOURCE)) +- return 0; +- +- source = media_entity_to_vsp1_entity(local->entity); ++ source = media_entity_to_vsp1_entity(source_pad->entity); + + if (!source->route) + return 0; + + if (flags & MEDIA_LNK_FL_ENABLED) { +- if (source->sink) +- return -EBUSY; +- source->sink = remote->entity; +- source->sink_pad = remote->index; ++ struct vsp1_entity *sink ++ = media_entity_to_vsp1_entity(sink_pad->entity); ++ ++ /* ++ * Fan-out is limited to one for the normal data path plus ++ * optional HGO and HGT. We ignore the HGO and HGT here. ++ */ ++ if (sink->type != VSP1_ENTITY_HGO && ++ sink->type != VSP1_ENTITY_HGT) { ++ if (source->sink) ++ return -EBUSY; ++ source->sink = sink_pad->entity; ++ source->sink_pad = sink_pad->index; ++ } + } else { + source->sink = NULL; + source->sink_pad = 0; +@@ -310,6 +322,85 @@ int vsp1_entity_link_setup(struct media_entity *entity, + return 0; + } + ++static int vsp1_entity_link_setup_sink(const struct media_pad *source_pad, ++ const struct media_pad *sink_pad, ++ u32 flags) ++{ ++ struct vsp1_entity *sink; ++ ++ sink = media_entity_to_vsp1_entity(sink_pad->entity); ++ ++ if (flags & MEDIA_LNK_FL_ENABLED) { ++ /* Fan-in is limited to one. */ ++ if (sink->sources[sink_pad->index]) ++ return -EBUSY; ++ ++ sink->sources[sink_pad->index] = source_pad->entity; ++ } else { ++ sink->sources[sink_pad->index] = NULL; ++ } ++ ++ return 0; ++} ++ ++int vsp1_entity_link_setup(struct media_entity *entity, ++ const struct media_pad *local, ++ const struct media_pad *remote, u32 flags) ++{ ++ if (local->flags & MEDIA_PAD_FL_SOURCE) ++ return vsp1_entity_link_setup_source(local, remote, flags); ++ else ++ return vsp1_entity_link_setup_sink(remote, local, flags); ++} ++ ++/** ++ * vsp1_entity_remote_pad - Find the pad at the remote end of a link ++ * @pad: Pad at the local end of the link ++ * ++ * Search for a remote pad connected to the given pad by iterating over all ++ * links originating or terminating at that pad until an enabled link is found. ++ * ++ * Our link setup implementation guarantees that the output fan-out will not be ++ * higher than one for the data pipelines, except for the links to the HGO and ++ * HGT that can be enabled in addition to a regular data link. When traversing ++ * outgoing links this function ignores HGO and HGT entities and should thus be ++ * used in place of the generic media_entity_remote_pad() function to traverse ++ * data pipelines. ++ * ++ * Return a pointer to the pad at the remote end of the first found enabled ++ * link, or NULL if no enabled link has been found. ++ */ ++struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad) ++{ ++ struct media_link *link; ++ ++ list_for_each_entry(link, &pad->entity->links, list) { ++ struct vsp1_entity *entity; ++ ++ if (!(link->flags & MEDIA_LNK_FL_ENABLED)) ++ continue; ++ ++ /* If we're the sink the source will never be an HGO or HGT. */ ++ if (link->sink == pad) ++ return link->source; ++ ++ if (link->source != pad) ++ continue; ++ ++ /* If the sink isn't a subdevice it can't be an HGO or HGT. */ ++ if (!is_media_entity_v4l2_subdev(link->sink->entity)) ++ return link->sink; ++ ++ entity = media_entity_to_vsp1_entity(link->sink->entity); ++ if (entity->type != VSP1_ENTITY_HGO && ++ entity->type != VSP1_ENTITY_HGT) ++ return link->sink; ++ } ++ ++ return NULL; ++ ++} ++ + /* ----------------------------------------------------------------------------- + * Initialization + */ +@@ -388,7 +479,14 @@ int vsp1_entity_init(struct vsp1_device *vsp1, struct vsp1_entity *entity, + for (i = 0; i < num_pads - 1; ++i) + entity->pads[i].flags = MEDIA_PAD_FL_SINK; + +- entity->pads[num_pads - 1].flags = MEDIA_PAD_FL_SOURCE; ++ entity->sources = devm_kcalloc(vsp1->dev, max(num_pads - 1, 1U), ++ sizeof(*entity->sources), GFP_KERNEL); ++ if (entity->sources == NULL) ++ return -ENOMEM; ++ ++ /* Single-pad entities only have a sink. */ ++ entity->pads[num_pads - 1].flags = num_pads > 1 ? MEDIA_PAD_FL_SOURCE ++ : MEDIA_PAD_FL_SINK; + + /* Initialize the media entity. */ + ret = media_entity_pads_init(&entity->subdev.entity, num_pads, +diff --git a/drivers/media/platform/vsp1/vsp1_entity.h b/drivers/media/platform/vsp1/vsp1_entity.h +index 901146f807b9..c169a060b6d2 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.h ++++ b/drivers/media/platform/vsp1/vsp1_entity.h +@@ -25,6 +25,8 @@ struct vsp1_pipeline; + enum vsp1_entity_type { + VSP1_ENTITY_BRU, + VSP1_ENTITY_CLU, ++ VSP1_ENTITY_HGO, ++ VSP1_ENTITY_HGT, + VSP1_ENTITY_HSI, + VSP1_ENTITY_HST, + VSP1_ENTITY_LIF, +@@ -102,6 +104,7 @@ struct vsp1_entity { + struct media_pad *pads; + unsigned int source_pad; + ++ struct media_entity **sources; + struct media_entity *sink; + unsigned int sink_pad; + +@@ -142,9 +145,12 @@ vsp1_entity_get_pad_selection(struct vsp1_entity *entity, + int vsp1_entity_init_cfg(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg); + +-void vsp1_entity_route_setup(struct vsp1_entity *source, ++void vsp1_entity_route_setup(struct vsp1_entity *entity, ++ struct vsp1_pipeline *pipe, + struct vsp1_dl_list *dl); + ++struct media_pad *vsp1_entity_remote_pad(struct media_pad *pad); ++ + int vsp1_subdev_get_pad_format(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt); +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c +index 35364f594e19..b5a765cbfc86 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.c ++++ b/drivers/media/platform/vsp1/vsp1_pipe.c +@@ -252,6 +252,7 @@ bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe) + + int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + { ++ struct vsp1_device *vsp1 = pipe->output->entity.vsp1; + struct vsp1_entity *entity; + unsigned long flags; + int ret; +@@ -261,8 +262,7 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + * When using display lists in continuous frame mode the only + * way to stop the pipeline is to reset the hardware. + */ +- ret = vsp1_reset_wpf(pipe->output->entity.vsp1, +- pipe->output->entity.index); ++ ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index); + if (ret == 0) { + spin_lock_irqsave(&pipe->irqlock, flags); + pipe->state = VSP1_PIPELINE_STOPPED; +@@ -282,7 +282,7 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + + list_for_each_entry(entity, &pipe->entities, list_pipe) { + if (entity->route && entity->route->reg) +- vsp1_write(entity->vsp1, entity->route->reg, ++ vsp1_write(vsp1, entity->route->reg, + VI6_DPR_NODE_UNUSED); + } + +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 79f48a025546..1a98bc91d1e2 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -486,7 +486,12 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe, + if (ret < 0) + return ret; + +- pad = media_entity_remote_pad(&input->entity.pads[RWPF_PAD_SOURCE]); ++ /* ++ * The main data path doesn't include the HGO or HGT, use ++ * vsp1_entity_remote_pad() to traverse the graph. ++ */ ++ ++ pad = vsp1_entity_remote_pad(&input->entity.pads[RWPF_PAD_SOURCE]); + + while (1) { + if (pad == NULL) { +@@ -539,14 +544,9 @@ static int vsp1_video_pipeline_build_branch(struct vsp1_pipeline *pipe, + : &input->entity; + } + +- /* +- * Follow the source link. The link setup operations ensure +- * that the output fan-out can't be more than one, there is thus +- * no need to verify here that only a single source link is +- * activated. +- */ ++ /* Follow the source link, ignoring any HGO or HGT. */ + pad = &entity->pads[entity->source_pad]; +- pad = media_entity_remote_pad(pad); ++ pad = vsp1_entity_remote_pad(pad); + } + + /* The last entity must be the output WPF. */ +@@ -800,7 +800,7 @@ static int vsp1_video_setup_pipeline(struct vsp1_pipeline *pipe) + } + + list_for_each_entry(entity, &pipe->entities, list_pipe) { +- vsp1_entity_route_setup(entity, pipe->dl); ++ vsp1_entity_route_setup(entity, pipe, pipe->dl); + + if (entity->ops->configure) + entity->ops->configure(entity, pipe, pipe->dl, +-- +2.13.3 + diff --git a/patches.renesas/0210-media-v4l-vsp1-Fix-HGO-and-HGT-routing-register-addr.patch b/patches.renesas/0210-media-v4l-vsp1-Fix-HGO-and-HGT-routing-register-addr.patch new file mode 100644 index 00000000000000..d830c9668d7a52 --- /dev/null +++ b/patches.renesas/0210-media-v4l-vsp1-Fix-HGO-and-HGT-routing-register-addr.patch @@ -0,0 +1,34 @@ +From ce8020eb50029756f4a36c7850aac90d70666c06 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 7 Sep 2016 09:36:31 -0300 +Subject: [PATCH 210/286] [media] v4l: vsp1: Fix HGO and HGT routing register + addresses + +The addresses are incorrect, fix them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 98eee2550f7b5e800641e90469f400a8c06fde73) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_regs.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index 47b1dee044fb..61369e267667 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -328,8 +328,8 @@ + #define VI6_DPR_ROUTE_RT_MASK (0x3f << 0) + #define VI6_DPR_ROUTE_RT_SHIFT 0 + +-#define VI6_DPR_HGO_SMPPT 0x2050 +-#define VI6_DPR_HGT_SMPPT 0x2054 ++#define VI6_DPR_HGO_SMPPT 0x2054 ++#define VI6_DPR_HGT_SMPPT 0x2058 + #define VI6_DPR_SMPPT_TGW_MASK (7 << 8) + #define VI6_DPR_SMPPT_TGW_SHIFT 8 + #define VI6_DPR_SMPPT_PT_MASK (0x3f << 0) +-- +2.13.3 + diff --git a/patches.renesas/0211-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-1.patch b/patches.renesas/0211-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-1.patch new file mode 100644 index 00000000000000..56f1870b08515f --- /dev/null +++ b/patches.renesas/0211-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-1.patch @@ -0,0 +1,258 @@ +From 96b1fe62230c19e2304dab807b5b284333ac9eb3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 10 Apr 2016 04:37:48 -0300 +Subject: [PATCH 211/286] [media] v4l: Define a pixel format for the R-Car VSP1 + 1-D histogram engine + +The format is used on the R-Car VSP1 video queues that carry +1-D histogram statistics data. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 14d66538716574f8899b22bff24a68301e65f08d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/media/uapi/v4l/meta-formats.rst | 15 ++ + .../media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst | 168 +++++++++++++++++++++ + Documentation/media/uapi/v4l/pixfmt.rst | 1 + + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/uapi/linux/videodev2.h | 3 + + 5 files changed, 188 insertions(+) + create mode 100644 Documentation/media/uapi/v4l/meta-formats.rst + create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst + +diff --git a/Documentation/media/uapi/v4l/meta-formats.rst b/Documentation/media/uapi/v4l/meta-formats.rst +new file mode 100644 +index 000000000000..05ab91e12f10 +--- /dev/null ++++ b/Documentation/media/uapi/v4l/meta-formats.rst +@@ -0,0 +1,15 @@ ++.. -*- coding: utf-8; mode: rst -*- ++ ++.. _meta-formats: ++ ++**************** ++Metadata Formats ++**************** ++ ++These formats are used for the :ref:`metadata` interface only. ++ ++ ++.. toctree:: ++ :maxdepth: 1 ++ ++ pixfmt-meta-vsp1-hgo +diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst +new file mode 100644 +index 000000000000..8d37bb313493 +--- /dev/null ++++ b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst +@@ -0,0 +1,168 @@ ++.. -*- coding: utf-8; mode: rst -*- ++ ++.. _v4l2-meta-fmt-vsp1-hgo: ++ ++******************************* ++V4L2_META_FMT_VSP1_HGO ('VSPH') ++******************************* ++ ++Renesas R-Car VSP1 1-D Histogram Data ++ ++ ++Description ++=========== ++ ++This format describes histogram data generated by the Renesas R-Car VSP1 1-D ++Histogram (HGO) engine. ++ ++The VSP1 HGO is a histogram computation engine that can operate on RGB, YCrCb ++or HSV data. It operates on a possibly cropped and subsampled input image and ++computes the minimum, maximum and sum of all pixels as well as per-channel ++histograms. ++ ++The HGO can compute histograms independently per channel, on the maximum of the ++three channels (RGB data only) or on the Y channel only (YCbCr only). It can ++additionally output the histogram with 64 or 256 bins, resulting in four ++possible modes of operation. ++ ++- In *64 bins normal mode*, the HGO operates on the three channels independently ++ to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are ++ supported. ++- In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B) ++ channels to compute a single 64-bins histogram. Only the RGB image format is ++ supported. ++- In *256 bins normal mode*, the HGO operates on the Y channel to compute a ++ single 256-bins histogram. Only the YCbCr image format is supported. ++- In *256 bins maximum mode*, the HGO operates on the maximum of the (R, G, B) ++ channels to compute a single 256-bins histogram. Only the RGB image format is ++ supported. ++ ++**Byte Order.** ++All data is stored in memory in little endian format. Each cell in the tables ++contains one byte. ++ ++.. flat-table:: VSP1 HGO Data - 64 Bins, Normal Mode (792 bytes) ++ :header-rows: 2 ++ :stub-columns: 0 ++ ++ * - Offset ++ - :cspan:`4` Memory ++ * - ++ - [31:24] ++ - [23:16] ++ - [15:8] ++ - [7:0] ++ * - 0 ++ - - ++ - R/Cr/H max [7:0] ++ - - ++ - R/Cr/H min [7:0] ++ * - 4 ++ - - ++ - G/Y/S max [7:0] ++ - - ++ - G/Y/S min [7:0] ++ * - 8 ++ - - ++ - B/Cb/V max [7:0] ++ - - ++ - B/Cb/V min [7:0] ++ * - 12 ++ - :cspan:`4` R/Cr/H sum [31:0] ++ * - 16 ++ - :cspan:`4` G/Y/S sum [31:0] ++ * - 20 ++ - :cspan:`4` B/Cb/V sum [31:0] ++ * - 24 ++ - :cspan:`4` R/Cr/H bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 276 ++ - :cspan:`4` R/Cr/H bin 63 [31:0] ++ * - 280 ++ - :cspan:`4` G/Y/S bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 532 ++ - :cspan:`4` G/Y/S bin 63 [31:0] ++ * - 536 ++ - :cspan:`4` B/Cb/V bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 788 ++ - :cspan:`4` B/Cb/V bin 63 [31:0] ++ ++.. flat-table:: VSP1 HGO Data - 64 Bins, Max Mode (264 bytes) ++ :header-rows: 2 ++ :stub-columns: 0 ++ ++ * - Offset ++ - :cspan:`4` Memory ++ * - ++ - [31:24] ++ - [23:16] ++ - [15:8] ++ - [7:0] ++ * - 0 ++ - - ++ - max(R,G,B) max [7:0] ++ - - ++ - max(R,G,B) min [7:0] ++ * - 4 ++ - :cspan:`4` max(R,G,B) sum [31:0] ++ * - 8 ++ - :cspan:`4` max(R,G,B) bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 260 ++ - :cspan:`4` max(R,G,B) bin 63 [31:0] ++ ++.. flat-table:: VSP1 HGO Data - 256 Bins, Normal Mode (1032 bytes) ++ :header-rows: 2 ++ :stub-columns: 0 ++ ++ * - Offset ++ - :cspan:`4` Memory ++ * - ++ - [31:24] ++ - [23:16] ++ - [15:8] ++ - [7:0] ++ * - 0 ++ - - ++ - Y max [7:0] ++ - - ++ - Y min [7:0] ++ * - 4 ++ - :cspan:`4` Y sum [31:0] ++ * - 8 ++ - :cspan:`4` Y bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 1028 ++ - :cspan:`4` Y bin 255 [31:0] ++ ++.. flat-table:: VSP1 HGO Data - 256 Bins, Max Mode (1032 bytes) ++ :header-rows: 2 ++ :stub-columns: 0 ++ ++ * - Offset ++ - :cspan:`4` Memory ++ * - ++ - [31:24] ++ - [23:16] ++ - [15:8] ++ - [7:0] ++ * - 0 ++ - - ++ - max(R,G,B) max [7:0] ++ - - ++ - max(R,G,B) min [7:0] ++ * - 4 ++ - :cspan:`4` max(R,G,B) sum [31:0] ++ * - 8 ++ - :cspan:`4` max(R,G,B) bin 0 [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 1028 ++ - :cspan:`4` max(R,G,B) bin 255 [31:0] +diff --git a/Documentation/media/uapi/v4l/pixfmt.rst b/Documentation/media/uapi/v4l/pixfmt.rst +index 4d297f6eb5f1..126fcd0faa7f 100644 +--- a/Documentation/media/uapi/v4l/pixfmt.rst ++++ b/Documentation/media/uapi/v4l/pixfmt.rst +@@ -33,4 +33,5 @@ see also :ref:`VIDIOC_G_FBUF <VIDIOC_G_FBUF>`.) + pixfmt-013 + sdr-formats + tch-formats ++ meta-formats + pixfmt-reserved +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index b1e4fff556f0..9f51ae56e4c3 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1265,6 +1265,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_TCH_FMT_DELTA_TD08: descr = "8-bit signed deltas"; break; + case V4L2_TCH_FMT_TU16: descr = "16-bit unsigned touch data"; break; + case V4L2_TCH_FMT_TU08: descr = "8-bit unsigned touch data"; break; ++ case V4L2_META_FMT_VSP1_HGO: descr = "R-Car VSP1 1-D Histogram"; break; + + default: + /* Compressed formats */ +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 2e0c8a9df8af..b4dc1bea942c 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -672,6 +672,9 @@ struct v4l2_pix_format { + #define V4L2_TCH_FMT_TU16 v4l2_fourcc('T', 'U', '1', '6') /* 16-bit unsigned touch data */ + #define V4L2_TCH_FMT_TU08 v4l2_fourcc('T', 'U', '0', '8') /* 8-bit unsigned touch data */ + ++/* Meta-data formats */ ++#define V4L2_META_FMT_VSP1_HGO v4l2_fourcc('V', 'S', 'P', 'H') /* R-Car VSP1 Histogram */ ++ + /* priv field value to indicates that subsequent fields are valid. */ + #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe + +-- +2.13.3 + diff --git a/patches.renesas/0212-media-v4l-vsp1-Add-HGO-support.patch b/patches.renesas/0212-media-v4l-vsp1-Add-HGO-support.patch new file mode 100644 index 00000000000000..1f8e2dd9a60a7d --- /dev/null +++ b/patches.renesas/0212-media-v4l-vsp1-Add-HGO-support.patch @@ -0,0 +1,636 @@ +From a701a78aa7955e562a42e1f8748d193750efb158 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Wed, 24 Feb 2016 20:40:22 -0300 +Subject: [PATCH 212/286] [media] v4l: vsp1: Add HGO support + +The HGO is a Histogram Generator One-Dimension. It computes per-channel +histograms over a configurable region of the image with optional +subsampling. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit f2421521de185c0281799712863db8e23d29a375) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/Makefile | 2 +- + drivers/media/platform/vsp1/vsp1.h | 3 + + drivers/media/platform/vsp1/vsp1_drv.c | 42 ++++-- + drivers/media/platform/vsp1/vsp1_entity.c | 16 +++ + drivers/media/platform/vsp1/vsp1_hgo.c | 228 ++++++++++++++++++++++++++++++ + drivers/media/platform/vsp1/vsp1_hgo.h | 45 ++++++ + drivers/media/platform/vsp1/vsp1_pipe.c | 16 +++ + drivers/media/platform/vsp1/vsp1_pipe.h | 2 + + drivers/media/platform/vsp1/vsp1_regs.h | 20 ++- + drivers/media/platform/vsp1/vsp1_video.c | 6 + + 10 files changed, 367 insertions(+), 13 deletions(-) + create mode 100644 drivers/media/platform/vsp1/vsp1_hgo.c + create mode 100644 drivers/media/platform/vsp1/vsp1_hgo.h + +diff --git a/drivers/media/platform/vsp1/Makefile b/drivers/media/platform/vsp1/Makefile +index c559536f7867..8ab6a063569e 100644 +--- a/drivers/media/platform/vsp1/Makefile ++++ b/drivers/media/platform/vsp1/Makefile +@@ -3,7 +3,7 @@ vsp1-y += vsp1_dl.o vsp1_drm.o vsp1_video.o + vsp1-y += vsp1_rpf.o vsp1_rwpf.o vsp1_wpf.o + vsp1-y += vsp1_clu.o vsp1_hsit.o vsp1_lut.o + vsp1-y += vsp1_bru.o vsp1_sru.o vsp1_uds.o +-vsp1-y += vsp1_histo.o ++vsp1-y += vsp1_hgo.o vsp1_histo.o + vsp1-y += vsp1_lif.o + + obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1.o +diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h +index b23fa879a9aa..0ba7521c01b4 100644 +--- a/drivers/media/platform/vsp1/vsp1.h ++++ b/drivers/media/platform/vsp1/vsp1.h +@@ -32,6 +32,7 @@ struct vsp1_entity; + struct vsp1_platform_data; + struct vsp1_bru; + struct vsp1_clu; ++struct vsp1_hgo; + struct vsp1_hsit; + struct vsp1_lif; + struct vsp1_lut; +@@ -50,6 +51,7 @@ struct vsp1_uds; + #define VSP1_HAS_CLU (1 << 4) + #define VSP1_HAS_WPF_VFLIP (1 << 5) + #define VSP1_HAS_WPF_HFLIP (1 << 6) ++#define VSP1_HAS_HGO (1 << 7) + + struct vsp1_device_info { + u32 version; +@@ -73,6 +75,7 @@ struct vsp1_device { + + struct vsp1_bru *bru; + struct vsp1_clu *clu; ++ struct vsp1_hgo *hgo; + struct vsp1_hsit *hsi; + struct vsp1_hsit *hst; + struct vsp1_lif *lif; +diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c +index 83a6669a6328..0acc8ed6ac59 100644 +--- a/drivers/media/platform/vsp1/vsp1_drv.c ++++ b/drivers/media/platform/vsp1/vsp1_drv.c +@@ -30,6 +30,7 @@ + #include "vsp1_clu.h" + #include "vsp1_dl.h" + #include "vsp1_drm.h" ++#include "vsp1_hgo.h" + #include "vsp1_hsit.h" + #include "vsp1_lif.h" + #include "vsp1_lut.h" +@@ -150,6 +151,16 @@ static int vsp1_uapi_create_links(struct vsp1_device *vsp1) + return ret; + } + ++ if (vsp1->hgo) { ++ ret = media_create_pad_link(&vsp1->hgo->histo.entity.subdev.entity, ++ HISTO_PAD_SOURCE, ++ &vsp1->hgo->histo.video.entity, 0, ++ MEDIA_LNK_FL_ENABLED | ++ MEDIA_LNK_FL_IMMUTABLE); ++ if (ret < 0) ++ return ret; ++ } ++ + if (vsp1->lif) { + ret = media_create_pad_link(&vsp1->wpf[0]->entity.subdev.entity, + RWPF_PAD_SOURCE, +@@ -283,6 +294,17 @@ static int vsp1_create_entities(struct vsp1_device *vsp1) + + list_add_tail(&vsp1->hst->entity.list_dev, &vsp1->entities); + ++ if (vsp1->info->features & VSP1_HAS_HGO && vsp1->info->uapi) { ++ vsp1->hgo = vsp1_hgo_create(vsp1); ++ if (IS_ERR(vsp1->hgo)) { ++ ret = PTR_ERR(vsp1->hgo); ++ goto done; ++ } ++ ++ list_add_tail(&vsp1->hgo->histo.entity.list_dev, ++ &vsp1->entities); ++ } ++ + /* + * The LIF is only supported when used in conjunction with the DU, in + * which case the userspace API is disabled. If the userspace API is +@@ -568,8 +590,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPS_H2, + .model = "VSP1-S", + .gen = 2, +- .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_LUT +- | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, ++ .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO ++ | VSP1_HAS_LUT | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, + .rpf_count = 5, + .uds_count = 3, + .wpf_count = 4, +@@ -589,7 +611,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPD_GEN2, + .model = "VSP1-D", + .gen = 2, +- .features = VSP1_HAS_BRU | VSP1_HAS_LIF | VSP1_HAS_LUT, ++ .features = VSP1_HAS_BRU | VSP1_HAS_HGO | VSP1_HAS_LIF ++ | VSP1_HAS_LUT, + .rpf_count = 4, + .uds_count = 1, + .wpf_count = 1, +@@ -599,8 +622,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPS_M2, + .model = "VSP1-S", + .gen = 2, +- .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_LUT +- | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, ++ .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO ++ | VSP1_HAS_LUT | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, + .rpf_count = 5, + .uds_count = 1, + .wpf_count = 4, +@@ -632,8 +655,9 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPI_GEN3, + .model = "VSP2-I", + .gen = 3, +- .features = VSP1_HAS_CLU | VSP1_HAS_LUT | VSP1_HAS_SRU +- | VSP1_HAS_WPF_HFLIP | VSP1_HAS_WPF_VFLIP, ++ .features = VSP1_HAS_CLU | VSP1_HAS_HGO | VSP1_HAS_LUT ++ | VSP1_HAS_SRU | VSP1_HAS_WPF_HFLIP ++ | VSP1_HAS_WPF_VFLIP, + .rpf_count = 1, + .uds_count = 1, + .wpf_count = 1, +@@ -651,8 +675,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPBC_GEN3, + .model = "VSP2-BC", + .gen = 3, +- .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_LUT +- | VSP1_HAS_WPF_VFLIP, ++ .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO ++ | VSP1_HAS_LUT | VSP1_HAS_WPF_VFLIP, + .rpf_count = 5, + .wpf_count = 1, + .num_bru_inputs = 5, +diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c +index 88a2aae182ba..c1587e3f01cb 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.c ++++ b/drivers/media/platform/vsp1/vsp1_entity.c +@@ -37,6 +37,21 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity, + struct vsp1_entity *source; + struct vsp1_entity *sink; + ++ if (entity->type == VSP1_ENTITY_HGO) { ++ u32 smppt; ++ ++ /* ++ * The HGO is a special case, its routing is configured on the ++ * sink pad. ++ */ ++ source = media_entity_to_vsp1_entity(entity->sources[0]); ++ smppt = (pipe->output->entity.index << VI6_DPR_SMPPT_TGW_SHIFT) ++ | (source->route->output << VI6_DPR_SMPPT_PT_SHIFT); ++ ++ vsp1_dl_list_write(dl, VI6_DPR_HGO_SMPPT, smppt); ++ return; ++ } ++ + source = entity; + if (source->route->reg == 0) + return; +@@ -427,6 +442,7 @@ static const struct vsp1_route vsp1_routes[] = { + VI6_DPR_NODE_BRU_IN(2), VI6_DPR_NODE_BRU_IN(3), + VI6_DPR_NODE_BRU_IN(4) }, VI6_DPR_NODE_BRU_OUT }, + VSP1_ENTITY_ROUTE(CLU), ++ { VSP1_ENTITY_HGO, 0, 0, { 0, }, 0 }, + VSP1_ENTITY_ROUTE(HSI), + VSP1_ENTITY_ROUTE(HST), + { VSP1_ENTITY_LIF, 0, 0, { VI6_DPR_NODE_LIF, }, VI6_DPR_NODE_LIF }, +diff --git a/drivers/media/platform/vsp1/vsp1_hgo.c b/drivers/media/platform/vsp1/vsp1_hgo.c +new file mode 100644 +index 000000000000..a138c6b7fb05 +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_hgo.c +@@ -0,0 +1,228 @@ ++/* ++ * vsp1_hgo.c -- R-Car VSP1 Histogram Generator 1D ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/device.h> ++#include <linux/gfp.h> ++ ++#include <media/v4l2-subdev.h> ++#include <media/videobuf2-vmalloc.h> ++ ++#include "vsp1.h" ++#include "vsp1_dl.h" ++#include "vsp1_hgo.h" ++ ++#define HGO_DATA_SIZE ((2 + 256) * 4) ++ ++/* ----------------------------------------------------------------------------- ++ * Device Access ++ */ ++ ++static inline u32 vsp1_hgo_read(struct vsp1_hgo *hgo, u32 reg) ++{ ++ return vsp1_read(hgo->histo.entity.vsp1, reg); ++} ++ ++static inline void vsp1_hgo_write(struct vsp1_hgo *hgo, struct vsp1_dl_list *dl, ++ u32 reg, u32 data) ++{ ++ vsp1_dl_list_write(dl, reg, data); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Frame End Handler ++ */ ++ ++void vsp1_hgo_frame_end(struct vsp1_entity *entity) ++{ ++ struct vsp1_hgo *hgo = to_hgo(&entity->subdev); ++ struct vsp1_histogram_buffer *buf; ++ unsigned int i; ++ size_t size; ++ u32 *data; ++ ++ buf = vsp1_histogram_buffer_get(&hgo->histo); ++ if (!buf) ++ return; ++ ++ data = buf->addr; ++ ++ if (hgo->num_bins == 256) { ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM); ++ ++ for (i = 0; i < 256; ++i) { ++ vsp1_write(hgo->histo.entity.vsp1, ++ VI6_HGO_EXT_HIST_ADDR, i); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_EXT_HIST_DATA); ++ } ++ ++ size = (2 + 256) * sizeof(u32); ++ } else if (hgo->max_rgb) { ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM); ++ ++ for (i = 0; i < 64; ++i) ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i)); ++ ++ size = (2 + 64) * sizeof(u32); ++ } else { ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_R_MAXMIN); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_MAXMIN); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_B_MAXMIN); ++ ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_R_SUM); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_G_SUM); ++ *data++ = vsp1_hgo_read(hgo, VI6_HGO_B_SUM); ++ ++ for (i = 0; i < 64; ++i) { ++ data[i] = vsp1_hgo_read(hgo, VI6_HGO_R_HISTO(i)); ++ data[i+64] = vsp1_hgo_read(hgo, VI6_HGO_G_HISTO(i)); ++ data[i+128] = vsp1_hgo_read(hgo, VI6_HGO_B_HISTO(i)); ++ } ++ ++ size = (6 + 64 * 3) * sizeof(u32); ++ } ++ ++ vsp1_histogram_buffer_complete(&hgo->histo, buf, size); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Controls ++ */ ++ ++#define V4L2_CID_VSP1_HGO_MAX_RGB (V4L2_CID_USER_BASE | 0x1001) ++#define V4L2_CID_VSP1_HGO_NUM_BINS (V4L2_CID_USER_BASE | 0x1002) ++ ++static const struct v4l2_ctrl_config hgo_max_rgb_control = { ++ .id = V4L2_CID_VSP1_HGO_MAX_RGB, ++ .name = "Maximum RGB Mode", ++ .type = V4L2_CTRL_TYPE_BOOLEAN, ++ .min = 0, ++ .max = 1, ++ .def = 0, ++ .step = 1, ++}; ++ ++static const s64 hgo_num_bins[] = { ++ 64, 256, ++}; ++ ++static const struct v4l2_ctrl_config hgo_num_bins_control = { ++ .id = V4L2_CID_VSP1_HGO_NUM_BINS, ++ .name = "Number of Bins", ++ .type = V4L2_CTRL_TYPE_INTEGER_MENU, ++ .min = 0, ++ .max = 1, ++ .def = 0, ++ .qmenu_int = hgo_num_bins, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * VSP1 Entity Operations ++ */ ++ ++static void hgo_configure(struct vsp1_entity *entity, ++ struct vsp1_pipeline *pipe, ++ struct vsp1_dl_list *dl, ++ enum vsp1_entity_params params) ++{ ++ struct vsp1_hgo *hgo = to_hgo(&entity->subdev); ++ struct v4l2_rect *compose; ++ struct v4l2_rect *crop; ++ unsigned int hratio; ++ unsigned int vratio; ++ ++ if (params != VSP1_ENTITY_PARAMS_INIT) ++ return; ++ ++ crop = vsp1_entity_get_pad_selection(entity, entity->config, ++ HISTO_PAD_SINK, V4L2_SEL_TGT_CROP); ++ compose = vsp1_entity_get_pad_selection(entity, entity->config, ++ HISTO_PAD_SINK, ++ V4L2_SEL_TGT_COMPOSE); ++ ++ vsp1_hgo_write(hgo, dl, VI6_HGO_REGRST, VI6_HGO_REGRST_RCLEA); ++ ++ vsp1_hgo_write(hgo, dl, VI6_HGO_OFFSET, ++ (crop->left << VI6_HGO_OFFSET_HOFFSET_SHIFT) | ++ (crop->top << VI6_HGO_OFFSET_VOFFSET_SHIFT)); ++ vsp1_hgo_write(hgo, dl, VI6_HGO_SIZE, ++ (crop->width << VI6_HGO_SIZE_HSIZE_SHIFT) | ++ (crop->height << VI6_HGO_SIZE_VSIZE_SHIFT)); ++ ++ mutex_lock(hgo->ctrls.handler.lock); ++ hgo->max_rgb = hgo->ctrls.max_rgb->cur.val; ++ if (hgo->ctrls.num_bins) ++ hgo->num_bins = hgo_num_bins[hgo->ctrls.num_bins->cur.val]; ++ mutex_unlock(hgo->ctrls.handler.lock); ++ ++ hratio = crop->width * 2 / compose->width / 3; ++ vratio = crop->height * 2 / compose->height / 3; ++ vsp1_hgo_write(hgo, dl, VI6_HGO_MODE, ++ (hgo->num_bins == 256 ? VI6_HGO_MODE_STEP : 0) | ++ (hgo->max_rgb ? VI6_HGO_MODE_MAXRGB : 0) | ++ (hratio << VI6_HGO_MODE_HRATIO_SHIFT) | ++ (vratio << VI6_HGO_MODE_VRATIO_SHIFT)); ++} ++ ++static const struct vsp1_entity_operations hgo_entity_ops = { ++ .configure = hgo_configure, ++ .destroy = vsp1_histogram_destroy, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * Initialization and Cleanup ++ */ ++ ++static const unsigned int hgo_mbus_formats[] = { ++ MEDIA_BUS_FMT_AYUV8_1X32, ++ MEDIA_BUS_FMT_ARGB8888_1X32, ++ MEDIA_BUS_FMT_AHSV8888_1X32, ++}; ++ ++struct vsp1_hgo *vsp1_hgo_create(struct vsp1_device *vsp1) ++{ ++ struct vsp1_hgo *hgo; ++ int ret; ++ ++ hgo = devm_kzalloc(vsp1->dev, sizeof(*hgo), GFP_KERNEL); ++ if (hgo == NULL) ++ return ERR_PTR(-ENOMEM); ++ ++ /* Initialize the control handler. */ ++ v4l2_ctrl_handler_init(&hgo->ctrls.handler, ++ vsp1->info->gen == 3 ? 2 : 1); ++ hgo->ctrls.max_rgb = v4l2_ctrl_new_custom(&hgo->ctrls.handler, ++ &hgo_max_rgb_control, NULL); ++ if (vsp1->info->gen == 3) ++ hgo->ctrls.num_bins = ++ v4l2_ctrl_new_custom(&hgo->ctrls.handler, ++ &hgo_num_bins_control, NULL); ++ ++ hgo->max_rgb = false; ++ hgo->num_bins = 64; ++ ++ hgo->histo.entity.subdev.ctrl_handler = &hgo->ctrls.handler; ++ ++ /* Initialize the video device and queue for statistics data. */ ++ ret = vsp1_histogram_init(vsp1, &hgo->histo, VSP1_ENTITY_HGO, "hgo", ++ &hgo_entity_ops, hgo_mbus_formats, ++ ARRAY_SIZE(hgo_mbus_formats), ++ HGO_DATA_SIZE, V4L2_META_FMT_VSP1_HGO); ++ if (ret < 0) { ++ vsp1_entity_destroy(&hgo->histo.entity); ++ return ERR_PTR(ret); ++ } ++ ++ return hgo; ++} +diff --git a/drivers/media/platform/vsp1/vsp1_hgo.h b/drivers/media/platform/vsp1/vsp1_hgo.h +new file mode 100644 +index 000000000000..c6c0b7a80e0c +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_hgo.h +@@ -0,0 +1,45 @@ ++/* ++ * vsp1_hgo.h -- R-Car VSP1 Histogram Generator 1D ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef __VSP1_HGO_H__ ++#define __VSP1_HGO_H__ ++ ++#include <media/media-entity.h> ++#include <media/v4l2-ctrls.h> ++#include <media/v4l2-subdev.h> ++ ++#include "vsp1_histo.h" ++ ++struct vsp1_device; ++ ++struct vsp1_hgo { ++ struct vsp1_histogram histo; ++ ++ struct { ++ struct v4l2_ctrl_handler handler; ++ struct v4l2_ctrl *max_rgb; ++ struct v4l2_ctrl *num_bins; ++ } ctrls; ++ ++ bool max_rgb; ++ unsigned int num_bins; ++}; ++ ++static inline struct vsp1_hgo *to_hgo(struct v4l2_subdev *subdev) ++{ ++ return container_of(subdev, struct vsp1_hgo, histo.entity.subdev); ++} ++ ++struct vsp1_hgo *vsp1_hgo_create(struct vsp1_device *vsp1); ++void vsp1_hgo_frame_end(struct vsp1_entity *hgo); ++ ++#endif /* __VSP1_HGO_H__ */ +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c +index b5a765cbfc86..bc0460c24397 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.c ++++ b/drivers/media/platform/vsp1/vsp1_pipe.c +@@ -23,6 +23,7 @@ + #include "vsp1_bru.h" + #include "vsp1_dl.h" + #include "vsp1_entity.h" ++#include "vsp1_hgo.h" + #include "vsp1_pipe.h" + #include "vsp1_rwpf.h" + #include "vsp1_uds.h" +@@ -204,11 +205,18 @@ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) + pipe->output = NULL; + } + ++ if (pipe->hgo) { ++ struct vsp1_hgo *hgo = to_hgo(&pipe->hgo->subdev); ++ ++ hgo->histo.pipe = NULL; ++ } ++ + INIT_LIST_HEAD(&pipe->entities); + pipe->state = VSP1_PIPELINE_STOPPED; + pipe->buffers_ready = 0; + pipe->num_inputs = 0; + pipe->bru = NULL; ++ pipe->hgo = NULL; + pipe->lif = NULL; + pipe->uds = NULL; + } +@@ -286,6 +294,11 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + VI6_DPR_NODE_UNUSED); + } + ++ if (pipe->hgo) ++ vsp1_write(vsp1, VI6_DPR_HGO_SMPPT, ++ (7 << VI6_DPR_SMPPT_TGW_SHIFT) | ++ (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); ++ + v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0); + + return ret; +@@ -309,6 +322,9 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) + + vsp1_dlm_irq_frame_end(pipe->output->dlm); + ++ if (pipe->hgo) ++ vsp1_hgo_frame_end(pipe->hgo); ++ + if (pipe->frame_end) + pipe->frame_end(pipe); + +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h +index 1144bf1e671a..4d91088c386b 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.h ++++ b/drivers/media/platform/vsp1/vsp1_pipe.h +@@ -73,6 +73,7 @@ enum vsp1_pipeline_state { + * @inputs: array of RPFs in the pipeline (indexed by RPF index) + * @output: WPF at the output of the pipeline + * @bru: BRU entity, if present ++ * @hgo: HGO entity, if present + * @lif: LIF entity, if present + * @uds: UDS entity, if present + * @uds_input: entity at the input of the UDS, if the UDS is present +@@ -101,6 +102,7 @@ struct vsp1_pipeline { + struct vsp1_rwpf *inputs[VSP1_MAX_RPF]; + struct vsp1_rwpf *output; + struct vsp1_entity *bru; ++ struct vsp1_entity *hgo; + struct vsp1_entity *lif; + struct vsp1_entity *uds; + struct vsp1_entity *uds_input; +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index 61369e267667..5414e519f7d8 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -590,24 +590,38 @@ + */ + + #define VI6_HGO_OFFSET 0x3000 ++#define VI6_HGO_OFFSET_HOFFSET_SHIFT 16 ++#define VI6_HGO_OFFSET_VOFFSET_SHIFT 0 + #define VI6_HGO_SIZE 0x3004 ++#define VI6_HGO_SIZE_HSIZE_SHIFT 16 ++#define VI6_HGO_SIZE_VSIZE_SHIFT 0 + #define VI6_HGO_MODE 0x3008 ++#define VI6_HGO_MODE_STEP (1 << 10) ++#define VI6_HGO_MODE_MAXRGB (1 << 7) ++#define VI6_HGO_MODE_OFSB_R (1 << 6) ++#define VI6_HGO_MODE_OFSB_G (1 << 5) ++#define VI6_HGO_MODE_OFSB_B (1 << 4) ++#define VI6_HGO_MODE_HRATIO_SHIFT 2 ++#define VI6_HGO_MODE_VRATIO_SHIFT 0 + #define VI6_HGO_LB_TH 0x300c + #define VI6_HGO_LBn_H(n) (0x3010 + (n) * 8) + #define VI6_HGO_LBn_V(n) (0x3014 + (n) * 8) +-#define VI6_HGO_R_HISTO 0x3030 ++#define VI6_HGO_R_HISTO(n) (0x3030 + (n) * 4) + #define VI6_HGO_R_MAXMIN 0x3130 + #define VI6_HGO_R_SUM 0x3134 + #define VI6_HGO_R_LB_DET 0x3138 +-#define VI6_HGO_G_HISTO 0x3140 ++#define VI6_HGO_G_HISTO(n) (0x3140 + (n) * 4) + #define VI6_HGO_G_MAXMIN 0x3240 + #define VI6_HGO_G_SUM 0x3244 + #define VI6_HGO_G_LB_DET 0x3248 +-#define VI6_HGO_B_HISTO 0x3250 ++#define VI6_HGO_B_HISTO(n) (0x3250 + (n) * 4) + #define VI6_HGO_B_MAXMIN 0x3350 + #define VI6_HGO_B_SUM 0x3354 + #define VI6_HGO_B_LB_DET 0x3358 ++#define VI6_HGO_EXT_HIST_ADDR 0x335c ++#define VI6_HGO_EXT_HIST_DATA 0x3360 + #define VI6_HGO_REGRST 0x33fc ++#define VI6_HGO_REGRST_RCLEA (1 << 0) + + /* ----------------------------------------------------------------------------- + * HGT Control Registers +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index 1a98bc91d1e2..d47b93f2af79 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -31,6 +31,7 @@ + #include "vsp1_bru.h" + #include "vsp1_dl.h" + #include "vsp1_entity.h" ++#include "vsp1_hgo.h" + #include "vsp1_pipe.h" + #include "vsp1_rwpf.h" + #include "vsp1_uds.h" +@@ -601,6 +602,11 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe, + pipe->lif = e; + } else if (e->type == VSP1_ENTITY_BRU) { + pipe->bru = e; ++ } else if (e->type == VSP1_ENTITY_HGO) { ++ struct vsp1_hgo *hgo = to_hgo(subdev); ++ ++ pipe->hgo = e; ++ hgo->histo.pipe = pipe; + } + } + +-- +2.13.3 + diff --git a/patches.renesas/0213-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-2.patch b/patches.renesas/0213-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-2.patch new file mode 100644 index 00000000000000..ae9d9606a4522c --- /dev/null +++ b/patches.renesas/0213-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-2.patch @@ -0,0 +1,191 @@ +From 69f764f419f6d1c31bfdf23df8f39760e7faf332 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Tue, 6 Sep 2016 11:38:55 -0300 +Subject: [PATCH 213/286] [media] v4l: Define a pixel format for the R-Car VSP1 + 2-D histogram engine +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The format is used on the R-Car VSP1 video queues that carry +2-D histogram statistics data. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 5deb1c04c9f2cc3fe4b355a55a8fad244683a54a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/media/uapi/v4l/meta-formats.rst | 1 + + .../media/uapi/v4l/pixfmt-meta-vsp1-hgt.rst | 120 +++++++++++++++++++++ + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/uapi/linux/videodev2.h | 3 +- + 4 files changed, 124 insertions(+), 1 deletion(-) + create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgt.rst + +diff --git a/Documentation/media/uapi/v4l/meta-formats.rst b/Documentation/media/uapi/v4l/meta-formats.rst +index 05ab91e12f10..01e24e3df571 100644 +--- a/Documentation/media/uapi/v4l/meta-formats.rst ++++ b/Documentation/media/uapi/v4l/meta-formats.rst +@@ -13,3 +13,4 @@ These formats are used for the :ref:`metadata` interface only. + :maxdepth: 1 + + pixfmt-meta-vsp1-hgo ++ pixfmt-meta-vsp1-hgt +diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgt.rst b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgt.rst +new file mode 100644 +index 000000000000..fb9f79466319 +--- /dev/null ++++ b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgt.rst +@@ -0,0 +1,120 @@ ++.. -*- coding: utf-8; mode: rst -*- ++ ++.. _v4l2-meta-fmt-vsp1-hgt: ++ ++******************************* ++V4L2_META_FMT_VSP1_HGT ('VSPT') ++******************************* ++ ++Renesas R-Car VSP1 2-D Histogram Data ++ ++ ++Description ++=========== ++ ++This format describes histogram data generated by the Renesas R-Car VSP1 ++2-D Histogram (HGT) engine. ++ ++The VSP1 HGT is a histogram computation engine that operates on HSV ++data. It operates on a possibly cropped and subsampled input image and ++computes the sum, maximum and minimum of the S component as well as a ++weighted frequency histogram based on the H and S components. ++ ++The histogram is a matrix of 6 Hue and 32 Saturation buckets, 192 in ++total. Each HSV value is added to one or more buckets with a weight ++between 1 and 16 depending on the Hue areas configuration. Finding the ++corresponding buckets is done by inspecting the H and S value independently. ++ ++The Saturation position **n** (0 - 31) of the bucket in the matrix is ++found by the expression: ++ ++ n = S / 8 ++ ++The Hue position **m** (0 - 5) of the bucket in the matrix depends on ++how the HGT Hue areas are configured. There are 6 user configurable Hue ++Areas which can be configured to cover overlapping Hue values: ++ ++:: ++ ++ Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 ++ ________ ________ ________ ________ ________ ________ ++ \ /| |\ /| |\ /| |\ /| |\ /| |\ /| |\ / ++ \ / | | \ / | | \ / | | \ / | | \ / | | \ / | | \ / ++ X | | X | | X | | X | | X | | X | | X ++ / \ | | / \ | | / \ | | / \ | | / \ | | / \ | | / \ ++ / \| |/ \| |/ \| |/ \| |/ \| |/ \| |/ \ ++ 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L ++ <0..............................Hue Value............................255> ++ ++When two consecutive areas don't overlap (n+1L is equal to nU) the boundary ++value is considered as part of the lower area. ++ ++Pixels with a hue value included in the centre of an area (between nL and nU ++included) are attributed to that single area and given a weight of 16. Pixels ++with a hue value included in the overlapping region between two areas (between ++n+1L and nU excluded) are attributed to both areas and given a weight for each ++of these areas proportional to their position along the diagonal lines ++(rounded down). ++ ++The Hue area setup must match one of the following constrains: ++ ++:: ++ ++ 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U ++ ++:: ++ ++ 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U <= 0L ++ ++**Byte Order.** ++All data is stored in memory in little endian format. Each cell in the tables ++contains one byte. ++ ++.. flat-table:: VSP1 HGT Data - (776 bytes) ++ :header-rows: 2 ++ :stub-columns: 0 ++ ++ * - Offset ++ - :cspan:`4` Memory ++ * - ++ - [31:24] ++ - [23:16] ++ - [15:8] ++ - [7:0] ++ * - 0 ++ - - ++ - S max [7:0] ++ - - ++ - S min [7:0] ++ * - 4 ++ - :cspan:`4` S sum [31:0] ++ * - 8 ++ - :cspan:`4` Histogram bucket (m=0, n=0) [31:0] ++ * - 12 ++ - :cspan:`4` Histogram bucket (m=0, n=1) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 132 ++ - :cspan:`4` Histogram bucket (m=0, n=31) [31:0] ++ * - 136 ++ - :cspan:`4` Histogram bucket (m=1, n=0) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 264 ++ - :cspan:`4` Histogram bucket (m=2, n=0) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 392 ++ - :cspan:`4` Histogram bucket (m=3, n=0) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 520 ++ - :cspan:`4` Histogram bucket (m=4, n=0) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 648 ++ - :cspan:`4` Histogram bucket (m=5, n=0) [31:0] ++ * - ++ - :cspan:`4` ... ++ * - 772 ++ - :cspan:`4` Histogram bucket (m=5, n=31) [31:0] +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index 9f51ae56e4c3..89567468f4e8 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1266,6 +1266,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_TCH_FMT_TU16: descr = "16-bit unsigned touch data"; break; + case V4L2_TCH_FMT_TU08: descr = "8-bit unsigned touch data"; break; + case V4L2_META_FMT_VSP1_HGO: descr = "R-Car VSP1 1-D Histogram"; break; ++ case V4L2_META_FMT_VSP1_HGT: descr = "R-Car VSP1 2-D Histogram"; break; + + default: + /* Compressed formats */ +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index b4dc1bea942c..0a875bab5c54 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -673,7 +673,8 @@ struct v4l2_pix_format { + #define V4L2_TCH_FMT_TU08 v4l2_fourcc('T', 'U', '0', '8') /* 8-bit unsigned touch data */ + + /* Meta-data formats */ +-#define V4L2_META_FMT_VSP1_HGO v4l2_fourcc('V', 'S', 'P', 'H') /* R-Car VSP1 Histogram */ ++#define V4L2_META_FMT_VSP1_HGO v4l2_fourcc('V', 'S', 'P', 'H') /* R-Car VSP1 1-D Histogram */ ++#define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */ + + /* priv field value to indicates that subsequent fields are valid. */ + #define V4L2_PIX_FMT_PRIV_MAGIC 0xfeedcafe +-- +2.13.3 + diff --git a/patches.renesas/0214-media-v4l-vsp1-Add-HGT-support.patch b/patches.renesas/0214-media-v4l-vsp1-Add-HGT-support.patch new file mode 100644 index 00000000000000..7fb6aef488a9f2 --- /dev/null +++ b/patches.renesas/0214-media-v4l-vsp1-Add-HGT-support.patch @@ -0,0 +1,592 @@ +From 46fb484fe23b9463b2e5fbc3e23252cd1060903c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + <niklas.soderlund+renesas@ragnatech.se> +Date: Tue, 6 Sep 2016 11:38:56 -0300 +Subject: [PATCH 214/286] [media] v4l: vsp1: Add HGT support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The HGT is a Histogram Generator Two-Dimensions. It computes a weighted +frequency histograms for hue and saturation areas over a configurable +region of the image with optional subsampling. + +Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 0ac702d5b903d441ef64e61f453de7c0ce1322fa) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/Makefile | 2 +- + drivers/media/platform/vsp1/vsp1.h | 3 + + drivers/media/platform/vsp1/vsp1_drv.c | 32 ++++- + drivers/media/platform/vsp1/vsp1_entity.c | 14 ++ + drivers/media/platform/vsp1/vsp1_hgt.c | 222 ++++++++++++++++++++++++++++++ + drivers/media/platform/vsp1/vsp1_hgt.h | 42 ++++++ + drivers/media/platform/vsp1/vsp1_pipe.c | 16 +++ + drivers/media/platform/vsp1/vsp1_pipe.h | 2 + + drivers/media/platform/vsp1/vsp1_regs.h | 9 ++ + drivers/media/platform/vsp1/vsp1_video.c | 6 + + 10 files changed, 343 insertions(+), 5 deletions(-) + create mode 100644 drivers/media/platform/vsp1/vsp1_hgt.c + create mode 100644 drivers/media/platform/vsp1/vsp1_hgt.h + +diff --git a/drivers/media/platform/vsp1/Makefile b/drivers/media/platform/vsp1/Makefile +index 8ab6a063569e..a33afc385a48 100644 +--- a/drivers/media/platform/vsp1/Makefile ++++ b/drivers/media/platform/vsp1/Makefile +@@ -3,7 +3,7 @@ vsp1-y += vsp1_dl.o vsp1_drm.o vsp1_video.o + vsp1-y += vsp1_rpf.o vsp1_rwpf.o vsp1_wpf.o + vsp1-y += vsp1_clu.o vsp1_hsit.o vsp1_lut.o + vsp1-y += vsp1_bru.o vsp1_sru.o vsp1_uds.o +-vsp1-y += vsp1_hgo.o vsp1_histo.o ++vsp1-y += vsp1_hgo.o vsp1_hgt.o vsp1_histo.o + vsp1-y += vsp1_lif.o + + obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1.o +diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h +index 0ba7521c01b4..85387a64179a 100644 +--- a/drivers/media/platform/vsp1/vsp1.h ++++ b/drivers/media/platform/vsp1/vsp1.h +@@ -33,6 +33,7 @@ struct vsp1_platform_data; + struct vsp1_bru; + struct vsp1_clu; + struct vsp1_hgo; ++struct vsp1_hgt; + struct vsp1_hsit; + struct vsp1_lif; + struct vsp1_lut; +@@ -52,6 +53,7 @@ struct vsp1_uds; + #define VSP1_HAS_WPF_VFLIP (1 << 5) + #define VSP1_HAS_WPF_HFLIP (1 << 6) + #define VSP1_HAS_HGO (1 << 7) ++#define VSP1_HAS_HGT (1 << 8) + + struct vsp1_device_info { + u32 version; +@@ -76,6 +78,7 @@ struct vsp1_device { + struct vsp1_bru *bru; + struct vsp1_clu *clu; + struct vsp1_hgo *hgo; ++ struct vsp1_hgt *hgt; + struct vsp1_hsit *hsi; + struct vsp1_hsit *hst; + struct vsp1_lif *lif; +diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c +index 0acc8ed6ac59..048446af5ae7 100644 +--- a/drivers/media/platform/vsp1/vsp1_drv.c ++++ b/drivers/media/platform/vsp1/vsp1_drv.c +@@ -31,6 +31,7 @@ + #include "vsp1_dl.h" + #include "vsp1_drm.h" + #include "vsp1_hgo.h" ++#include "vsp1_hgt.h" + #include "vsp1_hsit.h" + #include "vsp1_lif.h" + #include "vsp1_lut.h" +@@ -161,6 +162,16 @@ static int vsp1_uapi_create_links(struct vsp1_device *vsp1) + return ret; + } + ++ if (vsp1->hgt) { ++ ret = media_create_pad_link(&vsp1->hgt->histo.entity.subdev.entity, ++ HISTO_PAD_SOURCE, ++ &vsp1->hgt->histo.video.entity, 0, ++ MEDIA_LNK_FL_ENABLED | ++ MEDIA_LNK_FL_IMMUTABLE); ++ if (ret < 0) ++ return ret; ++ } ++ + if (vsp1->lif) { + ret = media_create_pad_link(&vsp1->wpf[0]->entity.subdev.entity, + RWPF_PAD_SOURCE, +@@ -305,6 +316,17 @@ static int vsp1_create_entities(struct vsp1_device *vsp1) + &vsp1->entities); + } + ++ if (vsp1->info->features & VSP1_HAS_HGT && vsp1->info->uapi) { ++ vsp1->hgt = vsp1_hgt_create(vsp1); ++ if (IS_ERR(vsp1->hgt)) { ++ ret = PTR_ERR(vsp1->hgt); ++ goto done; ++ } ++ ++ list_add_tail(&vsp1->hgt->histo.entity.list_dev, ++ &vsp1->entities); ++ } ++ + /* + * The LIF is only supported when used in conjunction with the DU, in + * which case the userspace API is disabled. If the userspace API is +@@ -591,7 +613,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .model = "VSP1-S", + .gen = 2, + .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO +- | VSP1_HAS_LUT | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, ++ | VSP1_HAS_HGT | VSP1_HAS_LUT | VSP1_HAS_SRU ++ | VSP1_HAS_WPF_VFLIP, + .rpf_count = 5, + .uds_count = 3, + .wpf_count = 4, +@@ -623,7 +646,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .model = "VSP1-S", + .gen = 2, + .features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO +- | VSP1_HAS_LUT | VSP1_HAS_SRU | VSP1_HAS_WPF_VFLIP, ++ | VSP1_HAS_HGT | VSP1_HAS_LUT | VSP1_HAS_SRU ++ | VSP1_HAS_WPF_VFLIP, + .rpf_count = 5, + .uds_count = 1, + .wpf_count = 4, +@@ -655,8 +679,8 @@ static const struct vsp1_device_info vsp1_device_infos[] = { + .version = VI6_IP_VERSION_MODEL_VSPI_GEN3, + .model = "VSP2-I", + .gen = 3, +- .features = VSP1_HAS_CLU | VSP1_HAS_HGO | VSP1_HAS_LUT +- | VSP1_HAS_SRU | VSP1_HAS_WPF_HFLIP ++ .features = VSP1_HAS_CLU | VSP1_HAS_HGO | VSP1_HAS_HGT ++ | VSP1_HAS_LUT | VSP1_HAS_SRU | VSP1_HAS_WPF_HFLIP + | VSP1_HAS_WPF_VFLIP, + .rpf_count = 1, + .uds_count = 1, +diff --git a/drivers/media/platform/vsp1/vsp1_entity.c b/drivers/media/platform/vsp1/vsp1_entity.c +index c1587e3f01cb..4bdb3b141611 100644 +--- a/drivers/media/platform/vsp1/vsp1_entity.c ++++ b/drivers/media/platform/vsp1/vsp1_entity.c +@@ -50,6 +50,19 @@ void vsp1_entity_route_setup(struct vsp1_entity *entity, + + vsp1_dl_list_write(dl, VI6_DPR_HGO_SMPPT, smppt); + return; ++ } else if (entity->type == VSP1_ENTITY_HGT) { ++ u32 smppt; ++ ++ /* ++ * The HGT is a special case, its routing is configured on the ++ * sink pad. ++ */ ++ source = media_entity_to_vsp1_entity(entity->sources[0]); ++ smppt = (pipe->output->entity.index << VI6_DPR_SMPPT_TGW_SHIFT) ++ | (source->route->output << VI6_DPR_SMPPT_PT_SHIFT); ++ ++ vsp1_dl_list_write(dl, VI6_DPR_HGT_SMPPT, smppt); ++ return; + } + + source = entity; +@@ -443,6 +456,7 @@ static const struct vsp1_route vsp1_routes[] = { + VI6_DPR_NODE_BRU_IN(4) }, VI6_DPR_NODE_BRU_OUT }, + VSP1_ENTITY_ROUTE(CLU), + { VSP1_ENTITY_HGO, 0, 0, { 0, }, 0 }, ++ { VSP1_ENTITY_HGT, 0, 0, { 0, }, 0 }, + VSP1_ENTITY_ROUTE(HSI), + VSP1_ENTITY_ROUTE(HST), + { VSP1_ENTITY_LIF, 0, 0, { VI6_DPR_NODE_LIF, }, VI6_DPR_NODE_LIF }, +diff --git a/drivers/media/platform/vsp1/vsp1_hgt.c b/drivers/media/platform/vsp1/vsp1_hgt.c +new file mode 100644 +index 000000000000..b5ce305e3e6f +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_hgt.c +@@ -0,0 +1,222 @@ ++/* ++ * vsp1_hgt.c -- R-Car VSP1 Histogram Generator 2D ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Niklas Söderlund (niklas.soderlund@ragnatech.se) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/device.h> ++#include <linux/gfp.h> ++ ++#include <media/v4l2-subdev.h> ++#include <media/videobuf2-vmalloc.h> ++ ++#include "vsp1.h" ++#include "vsp1_dl.h" ++#include "vsp1_hgt.h" ++ ++#define HGT_DATA_SIZE ((2 + 6 * 32) * 4) ++ ++/* ----------------------------------------------------------------------------- ++ * Device Access ++ */ ++ ++static inline u32 vsp1_hgt_read(struct vsp1_hgt *hgt, u32 reg) ++{ ++ return vsp1_read(hgt->histo.entity.vsp1, reg); ++} ++ ++static inline void vsp1_hgt_write(struct vsp1_hgt *hgt, struct vsp1_dl_list *dl, ++ u32 reg, u32 data) ++{ ++ vsp1_dl_list_write(dl, reg, data); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Frame End Handler ++ */ ++ ++void vsp1_hgt_frame_end(struct vsp1_entity *entity) ++{ ++ struct vsp1_hgt *hgt = to_hgt(&entity->subdev); ++ struct vsp1_histogram_buffer *buf; ++ unsigned int m; ++ unsigned int n; ++ u32 *data; ++ ++ buf = vsp1_histogram_buffer_get(&hgt->histo); ++ if (!buf) ++ return; ++ ++ data = buf->addr; ++ ++ *data++ = vsp1_hgt_read(hgt, VI6_HGT_MAXMIN); ++ *data++ = vsp1_hgt_read(hgt, VI6_HGT_SUM); ++ ++ for (m = 0; m < 6; ++m) ++ for (n = 0; n < 32; ++n) ++ *data++ = vsp1_hgt_read(hgt, VI6_HGT_HISTO(m, n)); ++ ++ vsp1_histogram_buffer_complete(&hgt->histo, buf, HGT_DATA_SIZE); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Controls ++ */ ++ ++#define V4L2_CID_VSP1_HGT_HUE_AREAS (V4L2_CID_USER_BASE | 0x1001) ++ ++static int hgt_hue_areas_try_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ const u8 *values = ctrl->p_new.p_u8; ++ unsigned int i; ++ ++ /* ++ * The hardware has constraints on the hue area boundaries beyond the ++ * control min, max and step. The values must match one of the following ++ * expressions. ++ * ++ * 0L <= 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U ++ * 0U <= 1L <= 1U <= 2L <= 2U <= 3L <= 3U <= 4L <= 4U <= 5L <= 5U <= 0L ++ * ++ * Start by verifying the common part... ++ */ ++ for (i = 1; i < (HGT_NUM_HUE_AREAS * 2) - 1; ++i) { ++ if (values[i] > values[i+1]) ++ return -EINVAL; ++ } ++ ++ /* ... and handle 0L separately. */ ++ if (values[0] > values[1] && values[11] > values[0]) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int hgt_hue_areas_s_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct vsp1_hgt *hgt = container_of(ctrl->handler, struct vsp1_hgt, ++ ctrls); ++ ++ memcpy(hgt->hue_areas, ctrl->p_new.p_u8, sizeof(hgt->hue_areas)); ++ return 0; ++} ++ ++static const struct v4l2_ctrl_ops hgt_hue_areas_ctrl_ops = { ++ .try_ctrl = hgt_hue_areas_try_ctrl, ++ .s_ctrl = hgt_hue_areas_s_ctrl, ++}; ++ ++static const struct v4l2_ctrl_config hgt_hue_areas = { ++ .ops = &hgt_hue_areas_ctrl_ops, ++ .id = V4L2_CID_VSP1_HGT_HUE_AREAS, ++ .name = "Boundary Values for Hue Area", ++ .type = V4L2_CTRL_TYPE_U8, ++ .min = 0, ++ .max = 255, ++ .def = 0, ++ .step = 1, ++ .dims = { 12 }, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * VSP1 Entity Operations ++ */ ++ ++static void hgt_configure(struct vsp1_entity *entity, ++ struct vsp1_pipeline *pipe, ++ struct vsp1_dl_list *dl, ++ enum vsp1_entity_params params) ++{ ++ struct vsp1_hgt *hgt = to_hgt(&entity->subdev); ++ struct v4l2_rect *compose; ++ struct v4l2_rect *crop; ++ unsigned int hratio; ++ unsigned int vratio; ++ u8 lower; ++ u8 upper; ++ unsigned int i; ++ ++ if (params != VSP1_ENTITY_PARAMS_INIT) ++ return; ++ ++ crop = vsp1_entity_get_pad_selection(entity, entity->config, ++ HISTO_PAD_SINK, V4L2_SEL_TGT_CROP); ++ compose = vsp1_entity_get_pad_selection(entity, entity->config, ++ HISTO_PAD_SINK, ++ V4L2_SEL_TGT_COMPOSE); ++ ++ vsp1_hgt_write(hgt, dl, VI6_HGT_REGRST, VI6_HGT_REGRST_RCLEA); ++ ++ vsp1_hgt_write(hgt, dl, VI6_HGT_OFFSET, ++ (crop->left << VI6_HGT_OFFSET_HOFFSET_SHIFT) | ++ (crop->top << VI6_HGT_OFFSET_VOFFSET_SHIFT)); ++ vsp1_hgt_write(hgt, dl, VI6_HGT_SIZE, ++ (crop->width << VI6_HGT_SIZE_HSIZE_SHIFT) | ++ (crop->height << VI6_HGT_SIZE_VSIZE_SHIFT)); ++ ++ mutex_lock(hgt->ctrls.lock); ++ for (i = 0; i < HGT_NUM_HUE_AREAS; ++i) { ++ lower = hgt->hue_areas[i*2 + 0]; ++ upper = hgt->hue_areas[i*2 + 1]; ++ vsp1_hgt_write(hgt, dl, VI6_HGT_HUE_AREA(i), ++ (lower << VI6_HGT_HUE_AREA_LOWER_SHIFT) | ++ (upper << VI6_HGT_HUE_AREA_UPPER_SHIFT)); ++ } ++ mutex_unlock(hgt->ctrls.lock); ++ ++ hratio = crop->width * 2 / compose->width / 3; ++ vratio = crop->height * 2 / compose->height / 3; ++ vsp1_hgt_write(hgt, dl, VI6_HGT_MODE, ++ (hratio << VI6_HGT_MODE_HRATIO_SHIFT) | ++ (vratio << VI6_HGT_MODE_VRATIO_SHIFT)); ++} ++ ++static const struct vsp1_entity_operations hgt_entity_ops = { ++ .configure = hgt_configure, ++ .destroy = vsp1_histogram_destroy, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * Initialization and Cleanup ++ */ ++ ++static const unsigned int hgt_mbus_formats[] = { ++ MEDIA_BUS_FMT_AHSV8888_1X32, ++}; ++ ++struct vsp1_hgt *vsp1_hgt_create(struct vsp1_device *vsp1) ++{ ++ struct vsp1_hgt *hgt; ++ int ret; ++ ++ hgt = devm_kzalloc(vsp1->dev, sizeof(*hgt), GFP_KERNEL); ++ if (hgt == NULL) ++ return ERR_PTR(-ENOMEM); ++ ++ /* Initialize the control handler. */ ++ v4l2_ctrl_handler_init(&hgt->ctrls, 1); ++ v4l2_ctrl_new_custom(&hgt->ctrls, &hgt_hue_areas, NULL); ++ ++ hgt->histo.entity.subdev.ctrl_handler = &hgt->ctrls; ++ ++ /* Initialize the video device and queue for statistics data. */ ++ ret = vsp1_histogram_init(vsp1, &hgt->histo, VSP1_ENTITY_HGT, "hgt", ++ &hgt_entity_ops, hgt_mbus_formats, ++ ARRAY_SIZE(hgt_mbus_formats), ++ HGT_DATA_SIZE, V4L2_META_FMT_VSP1_HGT); ++ if (ret < 0) { ++ vsp1_entity_destroy(&hgt->histo.entity); ++ return ERR_PTR(ret); ++ } ++ ++ v4l2_ctrl_handler_setup(&hgt->ctrls); ++ ++ return hgt; ++} +diff --git a/drivers/media/platform/vsp1/vsp1_hgt.h b/drivers/media/platform/vsp1/vsp1_hgt.h +new file mode 100644 +index 000000000000..83f2e130942a +--- /dev/null ++++ b/drivers/media/platform/vsp1/vsp1_hgt.h +@@ -0,0 +1,42 @@ ++/* ++ * vsp1_hgt.h -- R-Car VSP1 Histogram Generator 2D ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Niklas Söderlund (niklas.soderlund@ragnatech.se) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef __VSP1_HGT_H__ ++#define __VSP1_HGT_H__ ++ ++#include <media/media-entity.h> ++#include <media/v4l2-ctrls.h> ++#include <media/v4l2-subdev.h> ++ ++#include "vsp1_histo.h" ++ ++struct vsp1_device; ++ ++#define HGT_NUM_HUE_AREAS 6 ++ ++struct vsp1_hgt { ++ struct vsp1_histogram histo; ++ ++ struct v4l2_ctrl_handler ctrls; ++ ++ u8 hue_areas[HGT_NUM_HUE_AREAS * 2]; ++}; ++ ++static inline struct vsp1_hgt *to_hgt(struct v4l2_subdev *subdev) ++{ ++ return container_of(subdev, struct vsp1_hgt, histo.entity.subdev); ++} ++ ++struct vsp1_hgt *vsp1_hgt_create(struct vsp1_device *vsp1); ++void vsp1_hgt_frame_end(struct vsp1_entity *hgt); ++ ++#endif /* __VSP1_HGT_H__ */ +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c +index bc0460c24397..edebf3fa926f 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.c ++++ b/drivers/media/platform/vsp1/vsp1_pipe.c +@@ -24,6 +24,7 @@ + #include "vsp1_dl.h" + #include "vsp1_entity.h" + #include "vsp1_hgo.h" ++#include "vsp1_hgt.h" + #include "vsp1_pipe.h" + #include "vsp1_rwpf.h" + #include "vsp1_uds.h" +@@ -211,12 +212,19 @@ void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) + hgo->histo.pipe = NULL; + } + ++ if (pipe->hgt) { ++ struct vsp1_hgt *hgt = to_hgt(&pipe->hgt->subdev); ++ ++ hgt->histo.pipe = NULL; ++ } ++ + INIT_LIST_HEAD(&pipe->entities); + pipe->state = VSP1_PIPELINE_STOPPED; + pipe->buffers_ready = 0; + pipe->num_inputs = 0; + pipe->bru = NULL; + pipe->hgo = NULL; ++ pipe->hgt = NULL; + pipe->lif = NULL; + pipe->uds = NULL; + } +@@ -299,6 +307,11 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe) + (7 << VI6_DPR_SMPPT_TGW_SHIFT) | + (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); + ++ if (pipe->hgt) ++ vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, ++ (7 << VI6_DPR_SMPPT_TGW_SHIFT) | ++ (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT)); ++ + v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0); + + return ret; +@@ -325,6 +338,9 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe) + if (pipe->hgo) + vsp1_hgo_frame_end(pipe->hgo); + ++ if (pipe->hgt) ++ vsp1_hgt_frame_end(pipe->hgt); ++ + if (pipe->frame_end) + pipe->frame_end(pipe); + +diff --git a/drivers/media/platform/vsp1/vsp1_pipe.h b/drivers/media/platform/vsp1/vsp1_pipe.h +index 4d91088c386b..91a784a13422 100644 +--- a/drivers/media/platform/vsp1/vsp1_pipe.h ++++ b/drivers/media/platform/vsp1/vsp1_pipe.h +@@ -74,6 +74,7 @@ enum vsp1_pipeline_state { + * @output: WPF at the output of the pipeline + * @bru: BRU entity, if present + * @hgo: HGO entity, if present ++ * @hgt: HGT entity, if present + * @lif: LIF entity, if present + * @uds: UDS entity, if present + * @uds_input: entity at the input of the UDS, if the UDS is present +@@ -103,6 +104,7 @@ struct vsp1_pipeline { + struct vsp1_rwpf *output; + struct vsp1_entity *bru; + struct vsp1_entity *hgo; ++ struct vsp1_entity *hgt; + struct vsp1_entity *lif; + struct vsp1_entity *uds; + struct vsp1_entity *uds_input; +diff --git a/drivers/media/platform/vsp1/vsp1_regs.h b/drivers/media/platform/vsp1/vsp1_regs.h +index 5414e519f7d8..cd3e32af6e3b 100644 +--- a/drivers/media/platform/vsp1/vsp1_regs.h ++++ b/drivers/media/platform/vsp1/vsp1_regs.h +@@ -628,9 +628,17 @@ + */ + + #define VI6_HGT_OFFSET 0x3400 ++#define VI6_HGT_OFFSET_HOFFSET_SHIFT 16 ++#define VI6_HGT_OFFSET_VOFFSET_SHIFT 0 + #define VI6_HGT_SIZE 0x3404 ++#define VI6_HGT_SIZE_HSIZE_SHIFT 16 ++#define VI6_HGT_SIZE_VSIZE_SHIFT 0 + #define VI6_HGT_MODE 0x3408 ++#define VI6_HGT_MODE_HRATIO_SHIFT 2 ++#define VI6_HGT_MODE_VRATIO_SHIFT 0 + #define VI6_HGT_HUE_AREA(n) (0x340c + (n) * 4) ++#define VI6_HGT_HUE_AREA_LOWER_SHIFT 16 ++#define VI6_HGT_HUE_AREA_UPPER_SHIFT 0 + #define VI6_HGT_LB_TH 0x3424 + #define VI6_HGT_LBn_H(n) (0x3438 + (n) * 8) + #define VI6_HGT_LBn_V(n) (0x342c + (n) * 8) +@@ -639,6 +647,7 @@ + #define VI6_HGT_SUM 0x3754 + #define VI6_HGT_LB_DET 0x3758 + #define VI6_HGT_REGRST 0x37fc ++#define VI6_HGT_REGRST_RCLEA (1 << 0) + + /* ----------------------------------------------------------------------------- + * LIF Control Registers +diff --git a/drivers/media/platform/vsp1/vsp1_video.c b/drivers/media/platform/vsp1/vsp1_video.c +index d47b93f2af79..58593f13d246 100644 +--- a/drivers/media/platform/vsp1/vsp1_video.c ++++ b/drivers/media/platform/vsp1/vsp1_video.c +@@ -32,6 +32,7 @@ + #include "vsp1_dl.h" + #include "vsp1_entity.h" + #include "vsp1_hgo.h" ++#include "vsp1_hgt.h" + #include "vsp1_pipe.h" + #include "vsp1_rwpf.h" + #include "vsp1_uds.h" +@@ -607,6 +608,11 @@ static int vsp1_video_pipeline_build(struct vsp1_pipeline *pipe, + + pipe->hgo = e; + hgo->histo.pipe = pipe; ++ } else if (e->type == VSP1_ENTITY_HGT) { ++ struct vsp1_hgt *hgt = to_hgt(subdev); ++ ++ pipe->hgt = e; ++ hgt->histo.pipe = pipe; + } + } + +-- +2.13.3 + diff --git a/patches.renesas/0215-media-videodev.h-add-V4L2_CTRL_FLAG_MODIFY_LAYOUT.patch b/patches.renesas/0215-media-videodev.h-add-V4L2_CTRL_FLAG_MODIFY_LAYOUT.patch new file mode 100644 index 00000000000000..15daae101e730d --- /dev/null +++ b/patches.renesas/0215-media-videodev.h-add-V4L2_CTRL_FLAG_MODIFY_LAYOUT.patch @@ -0,0 +1,32 @@ +From 9d979d0fa80c7756b5f7f55fdfe6af60a46cccae Mon Sep 17 00:00:00 2001 +From: Hans Verkuil <hans.verkuil@cisco.com> +Date: Mon, 10 Apr 2017 16:15:26 -0300 +Subject: [PATCH 215/286] [media] videodev.h: add V4L2_CTRL_FLAG_MODIFY_LAYOUT + +Add new flag to indicate that changing this control will change the +buffer/mediabus layout as well. + +Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 6df8be763115a0ce6b486ea304742e5646f74287) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/uapi/linux/videodev2.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 0a875bab5c54..dd3778256d0d 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -1622,6 +1622,7 @@ struct v4l2_querymenu { + #define V4L2_CTRL_FLAG_VOLATILE 0x0080 + #define V4L2_CTRL_FLAG_HAS_PAYLOAD 0x0100 + #define V4L2_CTRL_FLAG_EXECUTE_ON_WRITE 0x0200 ++#define V4L2_CTRL_FLAG_MODIFY_LAYOUT 0x0400 + + /* Query flags, to be ORed with the control ID */ + #define V4L2_CTRL_FLAG_NEXT_CTRL 0x80000000 +-- +2.13.3 + diff --git a/patches.renesas/0216-media-vsp1-set-V4L2_CTRL_FLAG_MODIFY_LAYOUT-for-hist.patch b/patches.renesas/0216-media-vsp1-set-V4L2_CTRL_FLAG_MODIFY_LAYOUT-for-hist.patch new file mode 100644 index 00000000000000..ab2de7a4cbe257 --- /dev/null +++ b/patches.renesas/0216-media-vsp1-set-V4L2_CTRL_FLAG_MODIFY_LAYOUT-for-hist.patch @@ -0,0 +1,41 @@ +From e64b3bc96390b5bd3341a0000a2561bda1109c9b Mon Sep 17 00:00:00 2001 +From: Hans Verkuil <hans.verkuil@cisco.com> +Date: Mon, 10 Apr 2017 16:18:06 -0300 +Subject: [PATCH 216/286] [media] vsp1: set V4L2_CTRL_FLAG_MODIFY_LAYOUT for + histogram controls + +The two histogram controls will modify the layout of the +metadata, so this flag should be set. + +Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 6c1c0afd19317a15d6f2ae4965a73be7240aba18) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/media/platform/vsp1/vsp1_hgo.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/media/platform/vsp1/vsp1_hgo.c b/drivers/media/platform/vsp1/vsp1_hgo.c +index a138c6b7fb05..50309c053b78 100644 +--- a/drivers/media/platform/vsp1/vsp1_hgo.c ++++ b/drivers/media/platform/vsp1/vsp1_hgo.c +@@ -111,6 +111,7 @@ static const struct v4l2_ctrl_config hgo_max_rgb_control = { + .max = 1, + .def = 0, + .step = 1, ++ .flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT, + }; + + static const s64 hgo_num_bins[] = { +@@ -125,6 +126,7 @@ static const struct v4l2_ctrl_config hgo_num_bins_control = { + .max = 1, + .def = 0, + .qmenu_int = hgo_num_bins, ++ .flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT, + }; + + /* ----------------------------------------------------------------------------- +-- +2.13.3 + diff --git a/patches.renesas/0217-media-pixfmt-meta-vsp1-hgo.rst-remove-spurious.patch b/patches.renesas/0217-media-pixfmt-meta-vsp1-hgo.rst-remove-spurious.patch new file mode 100644 index 00000000000000..920fa28004b098 --- /dev/null +++ b/patches.renesas/0217-media-pixfmt-meta-vsp1-hgo.rst-remove-spurious.patch @@ -0,0 +1,91 @@ +From b393dc54a098c960c91c5b6a12557703005b4288 Mon Sep 17 00:00:00 2001 +From: Mauro Carvalho Chehab <mchehab@s-opensource.com> +Date: Wed, 19 Apr 2017 08:01:18 -0300 +Subject: [PATCH 217/286] [media] pixfmt-meta-vsp1-hgo.rst: remove spurious '-' + +Remove spurious '-' in the VSP1 hgo table. + +This resulted in a weird dot character that also caused +the row to be double-height. + +We used to have it on other tables, but we got rid of them +on changeset 8ed29e302dd1 ("[media] subdev-formats.rst: remove +spurious '-'"). + +Fixes: 14d665387165 ("[media] v4l: Define a pixel format for the R-Car VSP1 1-D histogram engine") +Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +(cherry picked from commit 242b0c4cc96f97d0a3b96343acd21613b63fa4a6) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst | 24 +++++++++++----------- + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst +index 8d37bb313493..67796594fd48 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-meta-vsp1-hgo.rst +@@ -53,19 +53,19 @@ contains one byte. + - [15:8] + - [7:0] + * - 0 +- - - ++ - + - R/Cr/H max [7:0] +- - - ++ - + - R/Cr/H min [7:0] + * - 4 +- - - ++ - + - G/Y/S max [7:0] +- - - ++ - + - G/Y/S min [7:0] + * - 8 +- - - ++ - + - B/Cb/V max [7:0] +- - - ++ - + - B/Cb/V min [7:0] + * - 12 + - :cspan:`4` R/Cr/H sum [31:0] +@@ -104,9 +104,9 @@ contains one byte. + - [15:8] + - [7:0] + * - 0 +- - - ++ - + - max(R,G,B) max [7:0] +- - - ++ - + - max(R,G,B) min [7:0] + * - 4 + - :cspan:`4` max(R,G,B) sum [31:0] +@@ -129,9 +129,9 @@ contains one byte. + - [15:8] + - [7:0] + * - 0 +- - - ++ - + - Y max [7:0] +- - - ++ - + - Y min [7:0] + * - 4 + - :cspan:`4` Y sum [31:0] +@@ -154,9 +154,9 @@ contains one byte. + - [15:8] + - [7:0] + * - 0 +- - - ++ - + - max(R,G,B) max [7:0] +- - - ++ - + - max(R,G,B) min [7:0] + * - 4 + - :cspan:`4` max(R,G,B) sum [31:0] +-- +2.13.3 + diff --git a/patches.renesas/0218-USB-host-xhci-use-max-port-define.patch b/patches.renesas/0218-USB-host-xhci-use-max-port-define.patch new file mode 100644 index 00000000000000..d6664e82f4e70e --- /dev/null +++ b/patches.renesas/0218-USB-host-xhci-use-max-port-define.patch @@ -0,0 +1,38 @@ +From 6aa7a961938db0c6a530a035fb0812f9330aafcb Mon Sep 17 00:00:00 2001 +From: Johan Hovold <johan@kernel.org> +Date: Wed, 10 May 2017 18:18:30 +0200 +Subject: [PATCH 218/286] USB: host: xhci: use max-port define + +Use the new define for the maximum number of SuperSpeed ports instead of +a constant when allocating xHCI root hubs. + +Signed-off-by: Johan Hovold <johan@kernel.org> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 5120a266928a07231d198bb518f6fe73148786a3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-mem.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c +index ea1308a7b814..66e67355d84d 100644 +--- a/drivers/usb/host/xhci-mem.c ++++ b/drivers/usb/host/xhci-mem.c +@@ -2310,10 +2310,11 @@ static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) + /* Place limits on the number of roothub ports so that the hub + * descriptors aren't longer than the USB core will allocate. + */ +- if (xhci->num_usb3_ports > 15) { ++ if (xhci->num_usb3_ports > USB_SS_MAXPORTS) { + xhci_dbg_trace(xhci, trace_xhci_dbg_init, +- "Limiting USB 3.0 roothub ports to 15."); +- xhci->num_usb3_ports = 15; ++ "Limiting USB 3.0 roothub ports to %u.", ++ USB_SS_MAXPORTS); ++ xhci->num_usb3_ports = USB_SS_MAXPORTS; + } + if (xhci->num_usb2_ports > USB_MAXCHILDREN) { + xhci_dbg_trace(xhci, trace_xhci_dbg_init, +-- +2.13.3 + diff --git a/patches.renesas/0219-usb-xhci-trace-URB-before-giving-it-back-instead-of-.patch b/patches.renesas/0219-usb-xhci-trace-URB-before-giving-it-back-instead-of-.patch new file mode 100644 index 00000000000000..5545e441638707 --- /dev/null +++ b/patches.renesas/0219-usb-xhci-trace-URB-before-giving-it-back-instead-of-.patch @@ -0,0 +1,34 @@ +From c298f0d2ac685b2f1d02dfbd0c40df99ec0c5c9a Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Wed, 17 May 2017 18:31:59 +0300 +Subject: [PATCH 219/286] usb: xhci: trace URB before giving it back instead of + after + +Don't access any members of a URB after giving it back. +URB might be freed by then already. + +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 7bc5d5aff356f3ba16c4d1e9eaf95cc99b7574ab) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 74bf5c60a260..507ba7734b94 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -641,8 +641,8 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, + xhci_urb_free_priv(urb_priv); + usb_hcd_unlink_urb_from_ep(hcd, urb); + spin_unlock(&xhci->lock); +- usb_hcd_giveback_urb(hcd, urb, status); + trace_xhci_urb_giveback(urb); ++ usb_hcd_giveback_urb(hcd, urb, status); + spin_lock(&xhci->lock); + } + +-- +2.13.3 + diff --git a/patches.renesas/0220-usb-host-xhci-ring-don-t-need-to-clear-interrupt-pen.patch b/patches.renesas/0220-usb-host-xhci-ring-don-t-need-to-clear-interrupt-pen.patch new file mode 100644 index 00000000000000..1c31e960b60345 --- /dev/null +++ b/patches.renesas/0220-usb-host-xhci-ring-don-t-need-to-clear-interrupt-pen.patch @@ -0,0 +1,80 @@ +From 3c19b50440734aca43db7be3feea45aa431b9da4 Mon Sep 17 00:00:00 2001 +From: Peter Chen <peter.chen@nxp.com> +Date: Wed, 17 May 2017 18:32:02 +0300 +Subject: [PATCH 220/286] usb: host: xhci-ring: don't need to clear interrupt + pending for MSI enabled hcd + +According to xHCI spec Figure 30: Interrupt Throttle Flow Diagram + + If PCI Message Signaled Interrupts (MSI or MSI-X) are enabled, + then the assertion of the Interrupt Pending (IP) flag in Figure 30 + generates a PCI Dword write. The IP flag is automatically cleared + by the completion of the PCI write. + +the MSI enabled HCs don't need to clear interrupt pending bit, but +hcd->irq = 0 doesn't equal to MSI enabled HCD. At some Dual-role +controller software designs, it sets hcd->irq as 0 to avoid HCD +requesting interrupt, and they want to decide when to call usb_hcd_irq +by software. + +Signed-off-by: Peter Chen <peter.chen@nxp.com> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 6a29beef9d1b16c762e469d77e28c3de3f5c3dbb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 5 +---- + drivers/usb/host/xhci.c | 5 +++-- + include/linux/usb/hcd.h | 1 + + 3 files changed, 5 insertions(+), 6 deletions(-) + +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 507ba7734b94..0830b25f9499 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2707,12 +2707,9 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) + */ + status |= STS_EINT; + writel(status, &xhci->op_regs->status); +- /* FIXME when MSI-X is supported and there are multiple vectors */ +- /* Clear the MSI-X event interrupt status */ + +- if (hcd->irq) { ++ if (!hcd->msi_enabled) { + u32 irq_pending; +- /* Acknowledge the PCI interrupt */ + irq_pending = readl(&xhci->ir_set->irq_pending); + irq_pending |= IMAN_IP; + writel(irq_pending, &xhci->ir_set->irq_pending); +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index dd2b42f52d99..716bd2e7e674 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -398,9 +398,10 @@ static int xhci_try_enable_msi(struct usb_hcd *hcd) + /* fall back to msi*/ + ret = xhci_setup_msi(xhci); + +- if (!ret) +- /* hcd->irq is 0, we have MSI */ ++ if (!ret) { ++ hcd->msi_enabled = 1; + return 0; ++ } + + if (!pdev->irq) { + xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); +diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h +index 66fc13705ab7..287cb491a887 100644 +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -148,6 +148,7 @@ struct usb_hcd { + unsigned rh_registered:1;/* is root hub registered? */ + unsigned rh_pollable:1; /* may we poll the root hub? */ + unsigned msix_enabled:1; /* driver has MSI-X enabled? */ ++ unsigned msi_enabled:1; /* driver has MSI enabled? */ + unsigned remove_phy:1; /* auto-remove USB phy */ + + /* The next flag is a stopgap, to be removed when all the HCDs +-- +2.13.3 + diff --git a/patches.renesas/0221-USB-xhci-fix-lock-inversion-problem.patch b/patches.renesas/0221-USB-xhci-fix-lock-inversion-problem.patch new file mode 100644 index 00000000000000..34a8b71b24c199 --- /dev/null +++ b/patches.renesas/0221-USB-xhci-fix-lock-inversion-problem.patch @@ -0,0 +1,95 @@ +From 496faf29f63753730016a168773c24173f818c45 Mon Sep 17 00:00:00 2001 +From: Alan Stern <stern@rowland.harvard.edu> +Date: Wed, 17 May 2017 18:32:03 +0300 +Subject: [PATCH 221/286] USB: xhci: fix lock-inversion problem + +With threaded interrupts, bottom-half handlers are called with +interrupts enabled. Therefore they can't safely use spin_lock(); they +have to use spin_lock_irqsave(). Lockdep warns about a violation +occurring in xhci_irq(): + +========================================================= +[ INFO: possible irq lock inversion dependency detected ] +4.11.0-rc8-dbg+ #1 Not tainted +--------------------------------------------------------- +swapper/7/0 just changed the state of lock: + (&(&ehci->lock)->rlock){-.-...}, at: [<ffffffffa0130a69>] +ehci_hrtimer_func+0x29/0xc0 [ehci_hcd] +but this lock took another, HARDIRQ-unsafe lock in the past: + (hcd_urb_list_lock){+.....} + +and interrupts could create inverse lock ordering between them. + +other info that might help us debug this: + Possible interrupt unsafe locking scenario: + + CPU0 CPU1 + ---- ---- + lock(hcd_urb_list_lock); + local_irq_disable(); + lock(&(&ehci->lock)->rlock); + lock(hcd_urb_list_lock); + <Interrupt> + lock(&(&ehci->lock)->rlock); + *** DEADLOCK *** + +no locks held by swapper/7/0. +the shortest dependencies between 2nd lock and 1st lock: + -> (hcd_urb_list_lock){+.....} ops: 252 { + HARDIRQ-ON-W at: + __lock_acquire+0x602/0x1280 + lock_acquire+0xd5/0x1c0 + _raw_spin_lock+0x2f/0x40 + usb_hcd_unlink_urb_from_ep+0x1b/0x60 [usbcore] + xhci_giveback_urb_in_irq.isra.45+0x70/0x1b0 [xhci_hcd] + finish_td.constprop.60+0x1d8/0x2e0 [xhci_hcd] + xhci_irq+0xdd6/0x1fa0 [xhci_hcd] + usb_hcd_irq+0x26/0x40 [usbcore] + irq_forced_thread_fn+0x2f/0x70 + irq_thread+0x149/0x1d0 + kthread+0x113/0x150 + ret_from_fork+0x2e/0x40 + +This patch fixes the problem. + +Signed-off-by: Alan Stern <stern@rowland.harvard.edu> +Reported-and-tested-by: Bart Van Assche <bart.vanassche@sandisk.com> +CC: <stable@vger.kernel.org> +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 63aea0dbab90a2461faaae357cbc8cfd6c8de9fe) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-ring.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 0830b25f9499..6d2492c1c643 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -2677,11 +2677,12 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + union xhci_trb *event_ring_deq; + irqreturn_t ret = IRQ_NONE; ++ unsigned long flags; + dma_addr_t deq; + u64 temp_64; + u32 status; + +- spin_lock(&xhci->lock); ++ spin_lock_irqsave(&xhci->lock, flags); + /* Check if the xHC generated the interrupt, or the irq is shared */ + status = readl(&xhci->op_regs->status); + if (status == ~(u32)0) { +@@ -2754,7 +2755,7 @@ irqreturn_t xhci_irq(struct usb_hcd *hcd) + ret = IRQ_HANDLED; + + out: +- spin_unlock(&xhci->lock); ++ spin_unlock_irqrestore(&xhci->lock, flags); + + return ret; + } +-- +2.13.3 + diff --git a/patches.renesas/0222-xhci-Fix-command-ring-stop-regression-in-4.11.patch b/patches.renesas/0222-xhci-Fix-command-ring-stop-regression-in-4.11.patch new file mode 100644 index 00000000000000..4c1b718890e31c --- /dev/null +++ b/patches.renesas/0222-xhci-Fix-command-ring-stop-regression-in-4.11.patch @@ -0,0 +1,113 @@ +From 77c768faf176fe66ffbd6d37f237eca6bc7ff4d2 Mon Sep 17 00:00:00 2001 +From: Mathias Nyman <mathias.nyman@linux.intel.com> +Date: Wed, 17 May 2017 18:32:05 +0300 +Subject: [PATCH 222/286] xhci: Fix command ring stop regression in 4.11 + +In 4.11 TRB completion codes were renamed to match spec. + +Completion codes for command ring stopped and endpoint stopped +were mixed, leading to failures while handling a stopped command ring. + +Use the correct completion code for command ring stopped events. + +Fixes: 0b7c105a04ca ("usb: host: xhci: rename completion codes to match spec") +Cc: <stable@vger.kernel.org> # 4.11 +Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +(cherry picked from commit 604d02a2a66ab7f93fd3b2bde3698c29ef057b65) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/usb/host/xhci-hub.c | 2 +- + drivers/usb/host/xhci-ring.c | 8 ++++---- + drivers/usb/host/xhci.c | 8 ++++---- + 3 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c +index 5e3e9d4c6956..0dde49c35dd2 100644 +--- a/drivers/usb/host/xhci-hub.c ++++ b/drivers/usb/host/xhci-hub.c +@@ -419,7 +419,7 @@ static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) + wait_for_completion(cmd->completion); + + if (cmd->status == COMP_COMMAND_ABORTED || +- cmd->status == COMP_STOPPED) { ++ cmd->status == COMP_COMMAND_RING_STOPPED) { + xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); + ret = -ETIME; + } +diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c +index 6d2492c1c643..03f63f50afb6 100644 +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -323,7 +323,7 @@ static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, + if (i_cmd->status != COMP_COMMAND_ABORTED) + continue; + +- i_cmd->status = COMP_STOPPED; ++ i_cmd->status = COMP_COMMAND_RING_STOPPED; + + xhci_dbg(xhci, "Turn aborted command %p to no-op\n", + i_cmd->command_trb); +@@ -1380,7 +1380,7 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, + cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); + + /* If CMD ring stopped we own the trbs between enqueue and dequeue */ +- if (cmd_comp_code == COMP_STOPPED) { ++ if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { + complete_all(&xhci->cmd_ring_stop_completion); + return; + } +@@ -1436,8 +1436,8 @@ static void handle_cmd_completion(struct xhci_hcd *xhci, + break; + case TRB_CMD_NOOP: + /* Is this an aborted command turned to NO-OP? */ +- if (cmd->status == COMP_STOPPED) +- cmd_comp_code = COMP_STOPPED; ++ if (cmd->status == COMP_COMMAND_RING_STOPPED) ++ cmd_comp_code = COMP_COMMAND_RING_STOPPED; + break; + case TRB_RESET_EP: + WARN_ON(slot_id != TRB_TO_SLOT_ID( +diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c +index 716bd2e7e674..5c9e69cb8ea6 100644 +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -1803,7 +1803,7 @@ static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, + + switch (*cmd_status) { + case COMP_COMMAND_ABORTED: +- case COMP_STOPPED: ++ case COMP_COMMAND_RING_STOPPED: + xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); + ret = -ETIME; + break; +@@ -1853,7 +1853,7 @@ static int xhci_evaluate_context_result(struct xhci_hcd *xhci, + + switch (*cmd_status) { + case COMP_COMMAND_ABORTED: +- case COMP_STOPPED: ++ case COMP_COMMAND_RING_STOPPED: + xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); + ret = -ETIME; + break; +@@ -3472,7 +3472,7 @@ static int xhci_discover_or_reset_device(struct usb_hcd *hcd, + ret = reset_device_cmd->status; + switch (ret) { + case COMP_COMMAND_ABORTED: +- case COMP_STOPPED: ++ case COMP_COMMAND_RING_STOPPED: + xhci_warn(xhci, "Timeout waiting for reset device command\n"); + ret = -ETIME; + goto command_cleanup; +@@ -3857,7 +3857,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, + */ + switch (command->status) { + case COMP_COMMAND_ABORTED: +- case COMP_STOPPED: ++ case COMP_COMMAND_RING_STOPPED: + xhci_warn(xhci, "Timeout while waiting for setup device command\n"); + ret = -ETIME; + break; +-- +2.13.3 + diff --git a/patches.renesas/0223-dt-bindings-net-sms911x-Add-missing-optional-VDD-reg.patch b/patches.renesas/0223-dt-bindings-net-sms911x-Add-missing-optional-VDD-reg.patch new file mode 100644 index 00000000000000..ec77dd5d40d8a9 --- /dev/null +++ b/patches.renesas/0223-dt-bindings-net-sms911x-Add-missing-optional-VDD-reg.patch @@ -0,0 +1,35 @@ +From 8c90cec31f212d5979130e8634fc8c118167f414 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski <krzk@kernel.org> +Date: Mon, 19 Jun 2017 18:05:41 +0200 +Subject: [PATCH 223/286] dt-bindings: net: sms911x: Add missing optional VDD + regulators + +The lan911x family of devices require supplying from 3.3 V power +supplies (connected to VDD_IO, VDD_A and VREG_3.3 pins). The existing +driver however obtains only VDD_IO and VDD_A regulators in an optional +way so document this in bindings. + +Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> +Reviewed-by: Linus Walleij <linus.walleij@linaro.org> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit 7e113321eccba2b52c0e9d11129d370c9511e4db) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/net/smsc911x.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt +index 16c3a9501f5d..acfafc8e143c 100644 +--- a/Documentation/devicetree/bindings/net/smsc911x.txt ++++ b/Documentation/devicetree/bindings/net/smsc911x.txt +@@ -27,6 +27,7 @@ Optional properties: + of the device. On many systems this is wired high so the device goes + out of reset at power-on, but if it is under program control, this + optional GPIO can wake up in response to it. ++- vdd33a-supply, vddvario-supply : 3.3V analog and IO logic power supplies + + Examples: + +-- +2.13.3 + diff --git a/patches.renesas/0224-net-phy-micrel-configure-intterupts-after-autoneg-wo.patch b/patches.renesas/0224-net-phy-micrel-configure-intterupts-after-autoneg-wo.patch new file mode 100644 index 00000000000000..a6f1e5788cfb7f --- /dev/null +++ b/patches.renesas/0224-net-phy-micrel-configure-intterupts-after-autoneg-wo.patch @@ -0,0 +1,40 @@ +From 042ca95f3db3b29670607a3afe3e360a60ad6300 Mon Sep 17 00:00:00 2001 +From: Zach Brown <zach.brown@ni.com> +Date: Tue, 20 Jun 2017 12:48:11 -0500 +Subject: [PATCH 224/286] net/phy: micrel: configure intterupts after autoneg + workaround + +The commit ("net/phy: micrel: Add workaround for bad autoneg") fixes an +autoneg failure case by resetting the hardware. This turns off +intterupts. Things will work themselves out if the phy polls, as it will +figure out it's state during a poll. However if the phy uses only +intterupts, the phy will stall, since interrupts are off. This patch +fixes the issue by calling config_intr after resetting the phy. + +Fixes: d2fd719bcb0e ("net/phy: micrel: Add workaround for bad autoneg ") +Signed-off-by: Zach Brown <zach.brown@ni.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +(cherry picked from commit b866203d872d5deeafcecd25ea429d6748b5bd56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/net/phy/micrel.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c +index d18d631c9fed..a630728fa430 100644 +--- a/drivers/net/phy/micrel.c ++++ b/drivers/net/phy/micrel.c +@@ -619,6 +619,8 @@ static int ksz9031_read_status(struct phy_device *phydev) + if ((regval & 0xFF) == 0xFF) { + phy_init_hw(phydev); + phydev->link = 0; ++ if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) ++ phydev->drv->config_intr(phydev); + } + + return 0; +-- +2.13.3 + diff --git a/patches.renesas/0225-drm-bridge-dw-hdmi-Remove-unused-functions.patch b/patches.renesas/0225-drm-bridge-dw-hdmi-Remove-unused-functions.patch new file mode 100644 index 00000000000000..37b387876d6266 --- /dev/null +++ b/patches.renesas/0225-drm-bridge-dw-hdmi-Remove-unused-functions.patch @@ -0,0 +1,59 @@ +From 4c38bfb1e3c44dde0ec6f5deea23ac9a53ea0996 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 3 Mar 2017 19:19:58 +0200 +Subject: [PATCH 225/286] drm: bridge: dw-hdmi: Remove unused functions + +Most of the hdmi_phy_test_*() functions are unused. Remove them. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Tested-by: Nickey Yang <nickey.yang@rock-chips.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-2-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 12a3a328eeb1467ef7170b9a710c0b53ee0273eb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 26 -------------------------- + 1 file changed, 26 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index 9a9ec27d9e28..ce7496399ccf 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -837,32 +837,6 @@ static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, + HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); + } + +-static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi, +- unsigned char bit) +-{ +- hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, +- HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); +-} +- +-static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi, +- unsigned char bit) +-{ +- hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, +- HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); +-} +- +-static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi, +- unsigned char bit) +-{ +- hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); +-} +- +-static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi, +- unsigned char bit) +-{ +- hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); +-} +- + static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) + { + u32 val; +-- +2.13.3 + diff --git a/patches.renesas/0226-drm-bridge-dw-hdmi-Move-CSC-configuration-out-of-PHY.patch b/patches.renesas/0226-drm-bridge-dw-hdmi-Move-CSC-configuration-out-of-PHY.patch new file mode 100644 index 00000000000000..03f94d1cb3de2d --- /dev/null +++ b/patches.renesas/0226-drm-bridge-dw-hdmi-Move-CSC-configuration-out-of-PHY.patch @@ -0,0 +1,87 @@ +From ca1317a0341e6dfef2ee6e2bfde30acf52d4cf48 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 3 Mar 2017 19:19:59 +0200 +Subject: [PATCH 226/286] drm: bridge: dw-hdmi: Move CSC configuration out of + PHY code + +The color space converter isn't part of the PHY, move its configuration +out of PHY code. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-3-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 8b9e1c0de3d81c7b2118f8c403a84fad758c3305) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 25 ++++++++++--------------- + 1 file changed, 10 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index ce7496399ccf..906583beb08b 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -914,7 +914,7 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) + HDMI_PHY_CONF0_SELDIPIF_MASK); + } + +-static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) ++static int hdmi_phy_configure(struct dw_hdmi *hdmi) + { + u8 val, msec; + const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; +@@ -946,14 +946,6 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) + return -EINVAL; + } + +- /* Enable csc path */ +- if (cscon) +- val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH; +- else +- val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS; +- +- hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL); +- + /* gen2 tx power off */ + dw_hdmi_phy_gen2_txpwron(hdmi, 0); + +@@ -1028,10 +1020,6 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) + static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) + { + int i, ret; +- bool cscon; +- +- /*check csc whether needed activated in HDMI mode */ +- cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi); + + /* HDMI Phy spec says to do the phy initialization sequence twice */ + for (i = 0; i < 2; i++) { +@@ -1040,8 +1028,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) + dw_hdmi_phy_enable_tmds(hdmi, 0); + dw_hdmi_phy_enable_powerdown(hdmi, true); + +- /* Enable CSC */ +- ret = hdmi_phy_configure(hdmi, cscon); ++ ret = hdmi_phy_configure(hdmi); + if (ret) + return ret; + } +@@ -1303,6 +1290,14 @@ static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) + clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; + hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); + } ++ ++ /* Enable color space conversion if needed (for HDMI sinks only). */ ++ if (hdmi->sink_is_hdmi && is_color_space_conversion(hdmi)) ++ hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, ++ HDMI_MC_FLOWCTRL); ++ else ++ hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, ++ HDMI_MC_FLOWCTRL); + } + + static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) +-- +2.13.3 + diff --git a/patches.renesas/0227-drm-bridge-dw-hdmi-Enable-CSC-even-for-DVI.patch b/patches.renesas/0227-drm-bridge-dw-hdmi-Enable-CSC-even-for-DVI.patch new file mode 100644 index 00000000000000..226b39215a41e0 --- /dev/null +++ b/patches.renesas/0227-drm-bridge-dw-hdmi-Enable-CSC-even-for-DVI.patch @@ -0,0 +1,39 @@ +From 4bb5b02aea8ddaeabf767383bb17e3682e23b91f Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Fri, 3 Mar 2017 19:20:00 +0200 +Subject: [PATCH 227/286] drm: bridge: dw-hdmi: Enable CSC even for DVI + +If the input pixel format is not RGB, the CSC must be enabled in order to +provide valid pixel to DVI sinks. +This patch removes the hdmi only dependency on the CSC enabling. + +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-4-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 14247d7ce769cfc2269a8b6a58157abb26813f3e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index 906583beb08b..d863b3393aee 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -1291,8 +1291,8 @@ static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) + hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); + } + +- /* Enable color space conversion if needed (for HDMI sinks only). */ +- if (hdmi->sink_is_hdmi && is_color_space_conversion(hdmi)) ++ /* Enable color space conversion if needed */ ++ if (is_color_space_conversion(hdmi)) + hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, + HDMI_MC_FLOWCTRL); + else +-- +2.13.3 + diff --git a/patches.renesas/0228-drm-bridge-dw-hdmi-Fix-the-PHY-power-down-sequence.patch b/patches.renesas/0228-drm-bridge-dw-hdmi-Fix-the-PHY-power-down-sequence.patch new file mode 100644 index 00000000000000..f880fafbdc24fe --- /dev/null +++ b/patches.renesas/0228-drm-bridge-dw-hdmi-Fix-the-PHY-power-down-sequence.patch @@ -0,0 +1,152 @@ +From 50fafc38c436b7d77cc2a0beba931f14f1347b7f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 6 Mar 2017 01:35:39 +0200 +Subject: [PATCH 228/286] drm: bridge: dw-hdmi: Fix the PHY power down sequence + +The PHY requires us to wait for the PHY to switch to low power mode +after deasserting TXPWRON and before asserting PDDQ in the power down +sequence, otherwise power down will fail. + +The PHY power down can be monitored though the TX_READY bit, available +through I2C in the PHY registers, or the TX_PHY_LOCK bit, available +through the HDMI TX registers. As the two are equivalent, let's pick the +easier solution of polling the TX_PHY_LOCK bit. + +The power down code is currently duplicated in multiple places. To avoid +spreading multiple calls to a TX_PHY_LOCK poll function, we have to +refactor the power down code and group it all in a single function. + +Tests showed that one poll iteration was enough for TX_PHY_LOCK to +become low, without requiring any additional delay. Retrying the read +five times with a 1ms to 2ms delay between each attempt should thus be +more than enough. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170305233539.11898-1-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit b0e583e5b6b90eed40456c394410c154a5160814) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 52 +++++++++++++++++++++++++++++++++------- + 1 file changed, 43 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index d863b3393aee..3a1cd4c7ac64 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -116,6 +116,7 @@ struct dw_hdmi_i2c { + struct dw_hdmi_phy_data { + enum dw_hdmi_phy_type type; + const char *name; ++ unsigned int gen; + bool has_svsret; + }; + +@@ -914,6 +915,40 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) + HDMI_PHY_CONF0_SELDIPIF_MASK); + } + ++static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) ++{ ++ const struct dw_hdmi_phy_data *phy = hdmi->phy; ++ unsigned int i; ++ u16 val; ++ ++ if (phy->gen == 1) { ++ dw_hdmi_phy_enable_tmds(hdmi, 0); ++ dw_hdmi_phy_enable_powerdown(hdmi, true); ++ return; ++ } ++ ++ dw_hdmi_phy_gen2_txpwron(hdmi, 0); ++ ++ /* ++ * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went ++ * to low power mode. ++ */ ++ for (i = 0; i < 5; ++i) { ++ val = hdmi_readb(hdmi, HDMI_PHY_STAT0); ++ if (!(val & HDMI_PHY_TX_PHY_LOCK)) ++ break; ++ ++ usleep_range(1000, 2000); ++ } ++ ++ if (val & HDMI_PHY_TX_PHY_LOCK) ++ dev_warn(hdmi->dev, "PHY failed to power down\n"); ++ else ++ dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); ++ ++ dw_hdmi_phy_gen2_pddq(hdmi, 1); ++} ++ + static int hdmi_phy_configure(struct dw_hdmi *hdmi) + { + u8 val, msec; +@@ -946,11 +981,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) + return -EINVAL; + } + +- /* gen2 tx power off */ +- dw_hdmi_phy_gen2_txpwron(hdmi, 0); +- +- /* gen2 pddq */ +- dw_hdmi_phy_gen2_pddq(hdmi, 1); ++ dw_hdmi_phy_power_off(hdmi); + + /* Leave low power consumption mode by asserting SVSRET. */ + if (hdmi->phy->has_svsret) +@@ -1025,8 +1056,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) + for (i = 0; i < 2; i++) { + dw_hdmi_phy_sel_data_en_pol(hdmi, 1); + dw_hdmi_phy_sel_interface_control(hdmi, 0); +- dw_hdmi_phy_enable_tmds(hdmi, 0); +- dw_hdmi_phy_enable_powerdown(hdmi, true); + + ret = hdmi_phy_configure(hdmi); + if (ret) +@@ -1256,8 +1285,7 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi) + if (!hdmi->phy_enabled) + return; + +- dw_hdmi_phy_enable_tmds(hdmi, 0); +- dw_hdmi_phy_enable_powerdown(hdmi, true); ++ dw_hdmi_phy_power_off(hdmi); + + hdmi->phy_enabled = false; + } +@@ -1827,23 +1855,29 @@ static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { + { + .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, + .name = "DWC HDMI TX PHY", ++ .gen = 1, + }, { + .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, + .name = "DWC MHL PHY + HEAC PHY", ++ .gen = 2, + .has_svsret = true, + }, { + .type = DW_HDMI_PHY_DWC_MHL_PHY, + .name = "DWC MHL PHY", ++ .gen = 2, + .has_svsret = true, + }, { + .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, + .name = "DWC HDMI 3D TX PHY + HEAC PHY", ++ .gen = 2, + }, { + .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, + .name = "DWC HDMI 3D TX PHY", ++ .gen = 2, + }, { + .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, + .name = "DWC HDMI 2.0 TX PHY", ++ .gen = 2, + .has_svsret = true, + } + }; +-- +2.13.3 + diff --git a/patches.renesas/0229-drm-bridge-dw-hdmi-Fix-the-PHY-power-up-sequence.patch b/patches.renesas/0229-drm-bridge-dw-hdmi-Fix-the-PHY-power-up-sequence.patch new file mode 100644 index 00000000000000..0f3ab2e5c10493 --- /dev/null +++ b/patches.renesas/0229-drm-bridge-dw-hdmi-Fix-the-PHY-power-up-sequence.patch @@ -0,0 +1,115 @@ +From 770344ff161f01bef753f1c91494910f13590e69 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 6 Mar 2017 01:35:57 +0200 +Subject: [PATCH 229/286] drm: bridge: dw-hdmi: Fix the PHY power up sequence + +When powering the PHY up we need to wait for the PLL to lock. This is +done by polling the TX_PHY_LOCK bit in the HDMI_PHY_STAT0 register +(interrupt-based wait could be implemented as well but is likely +overkill). The bit is asserted when the PLL locks, but the current code +incorrectly waits for the bit to be deasserted. Fix it, and while at it, +replace the udelay() with a sleep as the code never runs in +non-sleepable context. + +To be consistent with the power down implementation move the poll loop +to the power off function. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170305233557.11945-1-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 181e0ef092a4952aa523c5b9cb21394cf43bcd46) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 65 +++++++++++++++++++++++----------------- + 1 file changed, 37 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index 3a1cd4c7ac64..c25eac8ba47b 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -949,9 +949,44 @@ static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) + dw_hdmi_phy_gen2_pddq(hdmi, 1); + } + ++static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) ++{ ++ const struct dw_hdmi_phy_data *phy = hdmi->phy; ++ unsigned int i; ++ u8 val; ++ ++ if (phy->gen == 1) { ++ dw_hdmi_phy_enable_powerdown(hdmi, false); ++ ++ /* Toggle TMDS enable. */ ++ dw_hdmi_phy_enable_tmds(hdmi, 0); ++ dw_hdmi_phy_enable_tmds(hdmi, 1); ++ return 0; ++ } ++ ++ dw_hdmi_phy_gen2_txpwron(hdmi, 1); ++ dw_hdmi_phy_gen2_pddq(hdmi, 0); ++ ++ /* Wait for PHY PLL lock */ ++ for (i = 0; i < 5; ++i) { ++ val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; ++ if (val) ++ break; ++ ++ usleep_range(1000, 2000); ++ } ++ ++ if (!val) { ++ dev_err(hdmi->dev, "PHY PLL failed to lock\n"); ++ return -ETIMEDOUT; ++ } ++ ++ dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); ++ return 0; ++} ++ + static int hdmi_phy_configure(struct dw_hdmi *hdmi) + { +- u8 val, msec; + const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; +@@ -1019,33 +1054,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) + hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, + HDMI_3D_TX_PHY_CKCALCTRL); + +- dw_hdmi_phy_enable_powerdown(hdmi, false); +- +- /* toggle TMDS enable */ +- dw_hdmi_phy_enable_tmds(hdmi, 0); +- dw_hdmi_phy_enable_tmds(hdmi, 1); +- +- /* gen2 tx power on */ +- dw_hdmi_phy_gen2_txpwron(hdmi, 1); +- dw_hdmi_phy_gen2_pddq(hdmi, 0); +- +- /* Wait for PHY PLL lock */ +- msec = 5; +- do { +- val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; +- if (!val) +- break; +- +- if (msec == 0) { +- dev_err(hdmi->dev, "PHY PLL not locked\n"); +- return -ETIMEDOUT; +- } +- +- udelay(1000); +- msec--; +- } while (1); +- +- return 0; ++ return dw_hdmi_phy_power_on(hdmi); + } + + static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) +-- +2.13.3 + diff --git a/patches.renesas/0230-drm-bridge-dw-hdmi-Create-PHY-operations.patch b/patches.renesas/0230-drm-bridge-dw-hdmi-Create-PHY-operations.patch new file mode 100644 index 00000000000000..79de9bb26c456a --- /dev/null +++ b/patches.renesas/0230-drm-bridge-dw-hdmi-Create-PHY-operations.patch @@ -0,0 +1,270 @@ +From 7a486124f02c28397f4c399151d91135e3943774 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 6 Mar 2017 01:36:15 +0200 +Subject: [PATCH 230/286] drm: bridge: dw-hdmi: Create PHY operations + +The HDMI TX controller support different PHYs whose programming +interface can vary significantly, especially with vendor PHYs that are +not provided by Synopsys. To support them, create a PHY operation +structure that can be provided by the platform glue layer. The existing +PHY handling code (limited to Synopsys PHY support) is refactored into a +set of default PHY operations that are used automatically when the +platform glue doesn't provide its own operations. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170305233615.11993-1-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit f1585f6e29f5aba34e2cd6e3db9f0dd33b046809) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 95 ++++++++++++++++++++++++++++------------ + include/drm/bridge/dw_hdmi.h | 18 +++++++- + 2 files changed, 82 insertions(+), 31 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index c25eac8ba47b..cb2703862be2 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -141,8 +141,12 @@ struct dw_hdmi { + u8 edid[HDMI_EDID_LEN]; + bool cable_plugin; + +- const struct dw_hdmi_phy_data *phy; +- bool phy_enabled; ++ struct { ++ const struct dw_hdmi_phy_ops *ops; ++ const char *name; ++ void *data; ++ bool enabled; ++ } phy; + + struct drm_display_mode previous_mode; + +@@ -831,6 +835,10 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi) + HDMI_VP_CONF); + } + ++/* ----------------------------------------------------------------------------- ++ * Synopsys PHY Handling ++ */ ++ + static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, + unsigned char bit) + { +@@ -917,7 +925,7 @@ static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) + + static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) + { +- const struct dw_hdmi_phy_data *phy = hdmi->phy; ++ const struct dw_hdmi_phy_data *phy = hdmi->phy.data; + unsigned int i; + u16 val; + +@@ -951,7 +959,7 @@ static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) + + static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) + { +- const struct dw_hdmi_phy_data *phy = hdmi->phy; ++ const struct dw_hdmi_phy_data *phy = hdmi->phy.data; + unsigned int i; + u8 val; + +@@ -987,6 +995,7 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) + + static int hdmi_phy_configure(struct dw_hdmi *hdmi) + { ++ const struct dw_hdmi_phy_data *phy = hdmi->phy.data; + const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; +@@ -1019,7 +1028,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) + dw_hdmi_phy_power_off(hdmi); + + /* Leave low power consumption mode by asserting SVSRET. */ +- if (hdmi->phy->has_svsret) ++ if (phy->has_svsret) + dw_hdmi_phy_enable_svsret(hdmi, 1); + + /* PHY reset. The reset signal is active high on Gen2 PHYs. */ +@@ -1057,7 +1066,8 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) + return dw_hdmi_phy_power_on(hdmi); + } + +-static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) ++static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, ++ struct drm_display_mode *mode) + { + int i, ret; + +@@ -1071,10 +1081,31 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi) + return ret; + } + +- hdmi->phy_enabled = true; + return 0; + } + ++static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) ++{ ++ dw_hdmi_phy_power_off(hdmi); ++} ++ ++static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, ++ void *data) ++{ ++ return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? ++ connector_status_connected : connector_status_disconnected; ++} ++ ++static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { ++ .init = dw_hdmi_phy_init, ++ .disable = dw_hdmi_phy_disable, ++ .read_hpd = dw_hdmi_phy_read_hpd, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * HDMI TX Setup ++ */ ++ + static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) + { + u8 de; +@@ -1289,16 +1320,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, + hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); + } + +-static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi) +-{ +- if (!hdmi->phy_enabled) +- return; +- +- dw_hdmi_phy_power_off(hdmi); +- +- hdmi->phy_enabled = false; +-} +- + /* HDMI Initialization Step B.4 */ + static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) + { +@@ -1431,9 +1452,10 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + hdmi_av_composer(hdmi, mode); + + /* HDMI Initializateion Step B.2 */ +- ret = dw_hdmi_phy_init(hdmi); ++ ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); + if (ret) + return ret; ++ hdmi->phy.enabled = true; + + /* HDMI Initialization Step B.3 */ + dw_hdmi_enable_video_path(hdmi); +@@ -1548,7 +1570,11 @@ static void dw_hdmi_poweron(struct dw_hdmi *hdmi) + + static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) + { +- dw_hdmi_phy_disable(hdmi); ++ if (hdmi->phy.enabled) { ++ hdmi->phy.ops->disable(hdmi, hdmi->phy.data); ++ hdmi->phy.enabled = false; ++ } ++ + hdmi->bridge_is_on = false; + } + +@@ -1611,8 +1637,7 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); + +- return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? +- connector_status_connected : connector_status_disconnected; ++ return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + } + + static int dw_hdmi_connector_get_modes(struct drm_connector *connector) +@@ -1898,19 +1923,31 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) + + phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); + ++ if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { ++ /* Vendor PHYs require support from the glue layer. */ ++ if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { ++ dev_err(hdmi->dev, ++ "Vendor HDMI PHY not supported by glue layer\n"); ++ return -ENODEV; ++ } ++ ++ hdmi->phy.ops = hdmi->plat_data->phy_ops; ++ hdmi->phy.data = hdmi->plat_data->phy_data; ++ hdmi->phy.name = hdmi->plat_data->phy_name; ++ return 0; ++ } ++ ++ /* Synopsys PHYs are handled internally. */ + for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { + if (dw_hdmi_phys[i].type == phy_type) { +- hdmi->phy = &dw_hdmi_phys[i]; ++ hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; ++ hdmi->phy.name = dw_hdmi_phys[i].name; ++ hdmi->phy.data = (void *)&dw_hdmi_phys[i]; + return 0; + } + } + +- if (phy_type == DW_HDMI_PHY_VENDOR_PHY) +- dev_err(hdmi->dev, "Unsupported vendor HDMI PHY\n"); +- else +- dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", +- phy_type); +- ++ dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); + return -ENODEV; + } + +@@ -2031,7 +2068,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", + hdmi->version >> 12, hdmi->version & 0xfff, + prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", +- hdmi->phy->name); ++ hdmi->phy.name); + + initialize_hdmi_ih_mutes(hdmi); + +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index b080a171a23f..0f583ca7e66e 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -57,13 +57,27 @@ struct dw_hdmi_phy_config { + u16 vlev_ctr; /* voltage level control */ + }; + ++struct dw_hdmi_phy_ops { ++ int (*init)(struct dw_hdmi *hdmi, void *data, ++ struct drm_display_mode *mode); ++ void (*disable)(struct dw_hdmi *hdmi, void *data); ++ enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); ++}; ++ + struct dw_hdmi_plat_data { + enum dw_hdmi_devtype dev_type; ++ enum drm_mode_status (*mode_valid)(struct drm_connector *connector, ++ struct drm_display_mode *mode); ++ ++ /* Vendor PHY support */ ++ const struct dw_hdmi_phy_ops *phy_ops; ++ const char *phy_name; ++ void *phy_data; ++ ++ /* Synopsys PHY support */ + const struct dw_hdmi_mpll_config *mpll_cfg; + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_phy_config *phy_config; +- enum drm_mode_status (*mode_valid)(struct drm_connector *connector, +- struct drm_display_mode *mode); + }; + + int dw_hdmi_probe(struct platform_device *pdev, +-- +2.13.3 + diff --git a/patches.renesas/0231-drm-bridge-dw-hdmi-Add-support-for-custom-PHY-config.patch b/patches.renesas/0231-drm-bridge-dw-hdmi-Add-support-for-custom-PHY-config.patch new file mode 100644 index 00000000000000..bdd286429cb129 --- /dev/null +++ b/patches.renesas/0231-drm-bridge-dw-hdmi-Add-support-for-custom-PHY-config.patch @@ -0,0 +1,253 @@ +From 9123e67e17add93491c7cda1b235dbce1eddf423 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Fri, 3 Mar 2017 19:20:04 +0200 +Subject: [PATCH 231/286] drm: bridge: dw-hdmi: Add support for custom PHY + configuration + +The DWC HDMI TX controller interfaces with a companion PHY. While +Synopsys provides multiple standard PHYs, SoC vendors can also integrate +a custom PHY. + +Modularize PHY configuration to support vendor PHYs through platform +data. The existing PHY configuration code was originally written to +support the DWC HDMI 3D TX PHY, and seems to be compatible with the DWC +MLP PHY. The HDMI 2.0 PHY will require a separate configuration +function. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <Jose.Abreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-8-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 2ef9dfedefd60a12d2b02b1ee0a42be3506c43f2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 109 ++++++++++++++++++++++++++------------- + include/drm/bridge/dw_hdmi.h | 7 +++ + 2 files changed, 81 insertions(+), 35 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index cb2703862be2..b835d81bb471 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -118,6 +118,9 @@ struct dw_hdmi_phy_data { + const char *name; + unsigned int gen; + bool has_svsret; ++ int (*configure)(struct dw_hdmi *hdmi, ++ const struct dw_hdmi_plat_data *pdata, ++ unsigned long mpixelclock); + }; + + struct dw_hdmi { +@@ -860,8 +863,8 @@ static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) + return true; + } + +-static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, +- unsigned char addr) ++void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, ++ unsigned char addr) + { + hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); + hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); +@@ -873,6 +876,7 @@ static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, + HDMI_PHY_I2CM_OPERATION_ADDR); + hdmi_phy_wait_i2c_done(hdmi, 1000); + } ++EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); + + static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) + { +@@ -993,37 +997,67 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) + return 0; + } + +-static int hdmi_phy_configure(struct dw_hdmi *hdmi) ++/* ++ * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available ++ * information the DWC MHL PHY has the same register layout and is thus also ++ * supported by this function. ++ */ ++static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, ++ const struct dw_hdmi_plat_data *pdata, ++ unsigned long mpixelclock) + { +- const struct dw_hdmi_phy_data *phy = hdmi->phy.data; +- const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; + const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; + const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; + + /* PLL/MPLL Cfg - always match on final entry */ + for (; mpll_config->mpixelclock != ~0UL; mpll_config++) +- if (hdmi->hdmi_data.video_mode.mpixelclock <= +- mpll_config->mpixelclock) ++ if (mpixelclock <= mpll_config->mpixelclock) + break; + + for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) +- if (hdmi->hdmi_data.video_mode.mpixelclock <= +- curr_ctrl->mpixelclock) ++ if (mpixelclock <= curr_ctrl->mpixelclock) + break; + + for (; phy_config->mpixelclock != ~0UL; phy_config++) +- if (hdmi->hdmi_data.video_mode.mpixelclock <= +- phy_config->mpixelclock) ++ if (mpixelclock <= phy_config->mpixelclock) + break; + + if (mpll_config->mpixelclock == ~0UL || + curr_ctrl->mpixelclock == ~0UL || +- phy_config->mpixelclock == ~0UL) { +- dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n", +- hdmi->hdmi_data.video_mode.mpixelclock); ++ phy_config->mpixelclock == ~0UL) + return -EINVAL; +- } ++ ++ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, ++ HDMI_3D_TX_PHY_CPCE_CTRL); ++ dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, ++ HDMI_3D_TX_PHY_GMPCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], ++ HDMI_3D_TX_PHY_CURRCTRL); ++ ++ dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, ++ HDMI_3D_TX_PHY_MSM_CTRL); ++ ++ dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); ++ dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, ++ HDMI_3D_TX_PHY_CKSYMTXCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, ++ HDMI_3D_TX_PHY_VLEVCTRL); ++ ++ /* Override and disable clock termination. */ ++ dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, ++ HDMI_3D_TX_PHY_CKCALCTRL); ++ ++ return 0; ++} ++ ++static int hdmi_phy_configure(struct dw_hdmi *hdmi) ++{ ++ const struct dw_hdmi_phy_data *phy = hdmi->phy.data; ++ const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; ++ unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; ++ int ret; + + dw_hdmi_phy_power_off(hdmi); + +@@ -1042,26 +1076,16 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi) + HDMI_PHY_I2CM_SLAVE_ADDR); + hdmi_phy_test_clear(hdmi, 0); + +- hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, +- HDMI_3D_TX_PHY_CPCE_CTRL); +- hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, +- HDMI_3D_TX_PHY_GMPCTRL); +- hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], +- HDMI_3D_TX_PHY_CURRCTRL); +- +- hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); +- hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, +- HDMI_3D_TX_PHY_MSM_CTRL); +- +- hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); +- hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, +- HDMI_3D_TX_PHY_CKSYMTXCTRL); +- hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, +- HDMI_3D_TX_PHY_VLEVCTRL); +- +- /* Override and disable clock termination. */ +- hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, +- HDMI_3D_TX_PHY_CKCALCTRL); ++ /* Write to the PHY as configured by the platform */ ++ if (pdata->configure_phy) ++ ret = pdata->configure_phy(hdmi, pdata, mpixelclock); ++ else ++ ret = phy->configure(hdmi, pdata, mpixelclock); ++ if (ret) { ++ dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", ++ mpixelclock); ++ return ret; ++ } + + return dw_hdmi_phy_power_on(hdmi); + } +@@ -1895,24 +1919,31 @@ static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { + .name = "DWC MHL PHY + HEAC PHY", + .gen = 2, + .has_svsret = true, ++ .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, + }, { + .type = DW_HDMI_PHY_DWC_MHL_PHY, + .name = "DWC MHL PHY", + .gen = 2, + .has_svsret = true, ++ .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, + }, { + .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, + .name = "DWC HDMI 3D TX PHY + HEAC PHY", + .gen = 2, ++ .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, + }, { + .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, + .name = "DWC HDMI 3D TX PHY", + .gen = 2, ++ .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, + }, { + .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, + .name = "DWC HDMI 2.0 TX PHY", + .gen = 2, + .has_svsret = true, ++ }, { ++ .type = DW_HDMI_PHY_VENDOR_PHY, ++ .name = "Vendor PHY", + } + }; + +@@ -1943,6 +1974,14 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) + hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; + hdmi->phy.name = dw_hdmi_phys[i].name; + hdmi->phy.data = (void *)&dw_hdmi_phys[i]; ++ ++ if (!dw_hdmi_phys[i].configure && ++ !hdmi->plat_data->configure_phy) { ++ dev_err(hdmi->dev, "%s requires platform support\n", ++ hdmi->phy.name); ++ return -ENODEV; ++ } ++ + return 0; + } + } +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 0f583ca7e66e..dd330259a3dc 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -78,6 +78,9 @@ struct dw_hdmi_plat_data { + const struct dw_hdmi_mpll_config *mpll_cfg; + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_phy_config *phy_config; ++ int (*configure_phy)(struct dw_hdmi *hdmi, ++ const struct dw_hdmi_plat_data *pdata, ++ unsigned long mpixelclock); + }; + + int dw_hdmi_probe(struct platform_device *pdev, +@@ -91,4 +94,8 @@ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); + void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); + void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); + ++/* PHY configuration */ ++void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, ++ unsigned char addr); ++ + #endif /* __IMX_HDMI_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0232-drm-bridge-dw-hdmi-Remove-device-type-from-platform-.patch b/patches.renesas/0232-drm-bridge-dw-hdmi-Remove-device-type-from-platform-.patch new file mode 100644 index 00000000000000..0ed18e124c15af --- /dev/null +++ b/patches.renesas/0232-drm-bridge-dw-hdmi-Remove-device-type-from-platform-.patch @@ -0,0 +1,105 @@ +From d72254b17723fad00a4eaa3eca0f1e9c38e64096 Mon Sep 17 00:00:00 2001 +From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Date: Fri, 3 Mar 2017 19:20:05 +0200 +Subject: [PATCH 232/286] drm: bridge: dw-hdmi: Remove device type from + platform data + +The device type isn't used anymore now that workarounds and PHY-specific +operations are performed based on version information read at runtime. +Remove it. + +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-9-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 2e6777e8d5dd883b983c8de8797ff92bcb158f7c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 2 -- + drivers/gpu/drm/imx/dw_hdmi-imx.c | 2 -- + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 - + include/drm/bridge/dw_hdmi.h | 7 ------- + 4 files changed, 12 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index b835d81bb471..132c00685796 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -127,7 +127,6 @@ struct dw_hdmi { + struct drm_connector connector; + struct drm_bridge bridge; + +- enum dw_hdmi_devtype dev_type; + unsigned int version; + + struct platform_device *audio; +@@ -2014,7 +2013,6 @@ __dw_hdmi_probe(struct platform_device *pdev, + + hdmi->plat_data = plat_data; + hdmi->dev = dev; +- hdmi->dev_type = plat_data->dev_type; + hdmi->sample_rate = 48000; + hdmi->disabled = true; + hdmi->rxsense = true; +diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c +index f645275e6e63..f039641070ac 100644 +--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c ++++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c +@@ -175,7 +175,6 @@ static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .phy_config = imx_phy_config, +- .dev_type = IMX6Q_HDMI, + .mode_valid = imx6q_hdmi_mode_valid, + }; + +@@ -183,7 +182,6 @@ static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .phy_config = imx_phy_config, +- .dev_type = IMX6DL_HDMI, + .mode_valid = imx6dl_hdmi_mode_valid, + }; + +diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +index a6d4a0236e8f..d53827413996 100644 +--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +@@ -237,7 +237,6 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, +- .dev_type = RK3288_HDMI, + }; + + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index dd330259a3dc..545f04fae3b6 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -21,12 +21,6 @@ enum { + DW_HDMI_RES_MAX, + }; + +-enum dw_hdmi_devtype { +- IMX6Q_HDMI, +- IMX6DL_HDMI, +- RK3288_HDMI, +-}; +- + enum dw_hdmi_phy_type { + DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00, + DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2, +@@ -65,7 +59,6 @@ struct dw_hdmi_phy_ops { + }; + + struct dw_hdmi_plat_data { +- enum dw_hdmi_devtype dev_type; + enum drm_mode_status (*mode_valid)(struct drm_connector *connector, + struct drm_display_mode *mode); + +-- +2.13.3 + diff --git a/patches.renesas/0233-drm-bridge-dw-hdmi-Switch-to-regmap-for-register-acc.patch b/patches.renesas/0233-drm-bridge-dw-hdmi-Switch-to-regmap-for-register-acc.patch new file mode 100644 index 00000000000000..0f953fcd92c649 --- /dev/null +++ b/patches.renesas/0233-drm-bridge-dw-hdmi-Switch-to-regmap-for-register-acc.patch @@ -0,0 +1,229 @@ +From 1211fb5c348a9536dfe31edf9ea7a0620a2bd0c4 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Fri, 3 Mar 2017 19:20:06 +0200 +Subject: [PATCH 233/286] drm: bridge: dw-hdmi: Switch to regmap for register + access + +The Synopsys Designware HDMI TX Controller does not enforce register +access on platforms instanciating it. The current driver supports two +different types of memory-mapped flat register access, but in order to +support the Amlogic Meson SoCs integration, and provide a more generic +way to handle all sorts of register mapping, switch the register access +to use the regmap infrastructure. + +In the case of registers that are not flat memory-mapped or do not +conform to the current driver implementation, a regmap struct can be +given in the plat_data and be used at probe or bind. + +Since the AHB audio driver is only available with direct memory access, +only allow the I2S audio driver to be registered is directly +memory-mapped. + +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Tested-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Jose Abreu <Jose.Abreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-10-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 80e2f97968b537fc9c1789fce1b7f61609a5aae4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/dw-hdmi.c | 109 +++++++++++++++++++++------------------ + include/drm/bridge/dw_hdmi.h | 1 + + 2 files changed, 59 insertions(+), 51 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c +index 132c00685796..026a0dce7661 100644 +--- a/drivers/gpu/drm/bridge/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/dw-hdmi.c +@@ -19,6 +19,7 @@ + #include <linux/hdmi.h> + #include <linux/mutex.h> + #include <linux/of_device.h> ++#include <linux/regmap.h> + #include <linux/spinlock.h> + + #include <drm/drm_of.h> +@@ -171,8 +172,8 @@ struct dw_hdmi { + unsigned int audio_n; + bool audio_enable; + +- void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); +- u8 (*read)(struct dw_hdmi *hdmi, int offset); ++ unsigned int reg_shift; ++ struct regmap *regm; + }; + + #define HDMI_IH_PHY_STAT0_RX_SENSE \ +@@ -183,42 +184,23 @@ struct dw_hdmi { + (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ + HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) + +-static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) +-{ +- writel(val, hdmi->regs + (offset << 2)); +-} +- +-static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset) +-{ +- return readl(hdmi->regs + (offset << 2)); +-} +- +-static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) +-{ +- writeb(val, hdmi->regs + offset); +-} +- +-static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset) +-{ +- return readb(hdmi->regs + offset); +-} +- + static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) + { +- hdmi->write(hdmi, val, offset); ++ regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); + } + + static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) + { +- return hdmi->read(hdmi, offset); ++ unsigned int val = 0; ++ ++ regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); ++ ++ return val; + } + + static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) + { +- u8 val = hdmi_readb(hdmi, reg) & ~mask; +- +- val |= data & mask; +- hdmi_writeb(hdmi, val, reg); ++ regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); + } + + static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, +@@ -1989,6 +1971,20 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) + return -ENODEV; + } + ++static const struct regmap_config hdmi_regmap_8bit_config = { ++ .reg_bits = 32, ++ .val_bits = 8, ++ .reg_stride = 1, ++ .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, ++}; ++ ++static const struct regmap_config hdmi_regmap_32bit_config = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, ++}; ++ + static struct dw_hdmi * + __dw_hdmi_probe(struct platform_device *pdev, + const struct dw_hdmi_plat_data *plat_data) +@@ -1998,7 +1994,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + struct platform_device_info pdevinfo; + struct device_node *ddc_node; + struct dw_hdmi *hdmi; +- struct resource *iores; ++ struct resource *iores = NULL; + int irq; + int ret; + u32 val = 1; +@@ -2022,22 +2018,6 @@ __dw_hdmi_probe(struct platform_device *pdev, + mutex_init(&hdmi->audio_mutex); + spin_lock_init(&hdmi->audio_lock); + +- of_property_read_u32(np, "reg-io-width", &val); +- +- switch (val) { +- case 4: +- hdmi->write = dw_hdmi_writel; +- hdmi->read = dw_hdmi_readl; +- break; +- case 1: +- hdmi->write = dw_hdmi_writeb; +- hdmi->read = dw_hdmi_readb; +- break; +- default: +- dev_err(dev, "reg-io-width must be 1 or 4\n"); +- return ERR_PTR(-EINVAL); +- } +- + ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); + if (ddc_node) { + hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); +@@ -2051,11 +2031,38 @@ __dw_hdmi_probe(struct platform_device *pdev, + dev_dbg(hdmi->dev, "no ddc property found\n"); + } + +- iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- hdmi->regs = devm_ioremap_resource(dev, iores); +- if (IS_ERR(hdmi->regs)) { +- ret = PTR_ERR(hdmi->regs); +- goto err_res; ++ if (!plat_data->regm) { ++ const struct regmap_config *reg_config; ++ ++ of_property_read_u32(np, "reg-io-width", &val); ++ switch (val) { ++ case 4: ++ reg_config = &hdmi_regmap_32bit_config; ++ hdmi->reg_shift = 2; ++ break; ++ case 1: ++ reg_config = &hdmi_regmap_8bit_config; ++ break; ++ default: ++ dev_err(dev, "reg-io-width must be 1 or 4\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ hdmi->regs = devm_ioremap_resource(dev, iores); ++ if (IS_ERR(hdmi->regs)) { ++ ret = PTR_ERR(hdmi->regs); ++ goto err_res; ++ } ++ ++ hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); ++ if (IS_ERR(hdmi->regm)) { ++ dev_err(dev, "Failed to configure regmap\n"); ++ ret = PTR_ERR(hdmi->regm); ++ goto err_res; ++ } ++ } else { ++ hdmi->regm = plat_data->regm; + } + + hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); +@@ -2165,7 +2172,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); + config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); + +- if (config3 & HDMI_CONFIG3_AHBAUDDMA) { ++ if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { + struct dw_hdmi_audio_data audio; + + audio.phys = iores->start; +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 545f04fae3b6..bcceee8114a4 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -59,6 +59,7 @@ struct dw_hdmi_phy_ops { + }; + + struct dw_hdmi_plat_data { ++ struct regmap *regm; + enum drm_mode_status (*mode_valid)(struct drm_connector *connector, + struct drm_display_mode *mode); + +-- +2.13.3 + diff --git a/patches.renesas/0234-drm-bridge-dw-hdmi-Move-the-driver-to-a-separate-dir.patch b/patches.renesas/0234-drm-bridge-dw-hdmi-Move-the-driver-to-a-separate-dir.patch new file mode 100644 index 00000000000000..c9f773322aed38 --- /dev/null +++ b/patches.renesas/0234-drm-bridge-dw-hdmi-Move-the-driver-to-a-separate-dir.patch @@ -0,0 +1,159 @@ +From d88a2db7f7ef0a231ef5fc7b91b01f6400ce4d27 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 Mar 2017 15:48:12 +0530 +Subject: [PATCH 234/286] drm: bridge: dw-hdmi: Move the driver to a separate + directory. + +The driver is already made of 5 separate source files. Move it to a +newly created directory named synopsys where more Synopsys bridge +drivers can be added later (for the DisplayPort controller for +instance). + +Suggested-by: Jose Abreu <Jose.Abreu@synopsys.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-10-laurent.pinchart+renesas@ideasonboard.com +(cherry picked from commit 35dc8aabc8783d6322a59d774af2858e5955d2ab) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/Kconfig | 25 ++-------------------- + drivers/gpu/drm/bridge/Makefile | 4 +--- + drivers/gpu/drm/bridge/synopsys/Kconfig | 23 ++++++++++++++++++++ + drivers/gpu/drm/bridge/synopsys/Makefile | 5 +++++ + .../drm/bridge/{ => synopsys}/dw-hdmi-ahb-audio.c | 0 + .../gpu/drm/bridge/{ => synopsys}/dw-hdmi-audio.h | 0 + .../drm/bridge/{ => synopsys}/dw-hdmi-i2s-audio.c | 0 + drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi.c | 0 + drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi.h | 0 + 9 files changed, 31 insertions(+), 26 deletions(-) + create mode 100644 drivers/gpu/drm/bridge/synopsys/Kconfig + create mode 100644 drivers/gpu/drm/bridge/synopsys/Makefile + rename drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi-ahb-audio.c (100%) + rename drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi-audio.h (100%) + rename drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi-i2s-audio.c (100%) + rename drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi.c (100%) + rename drivers/gpu/drm/bridge/{ => synopsys}/dw-hdmi.h (100%) + +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index 3129f8d988fb..ae9bd851fc8b 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -24,29 +24,6 @@ config DRM_DUMB_VGA_DAC + help + Support for RGB to VGA DAC based bridges + +-config DRM_DW_HDMI +- tristate +- select DRM_KMS_HELPER +- +-config DRM_DW_HDMI_AHB_AUDIO +- tristate "Synopsis Designware AHB Audio interface" +- depends on DRM_DW_HDMI && SND +- select SND_PCM +- select SND_PCM_ELD +- select SND_PCM_IEC958 +- help +- Support the AHB Audio interface which is part of the Synopsis +- Designware HDMI block. This is used in conjunction with +- the i.MX6 HDMI driver. +- +-config DRM_DW_HDMI_I2S_AUDIO +- tristate "Synopsis Designware I2S Audio interface" +- depends on DRM_DW_HDMI +- select SND_SOC_HDMI_CODEC +- help +- Support the I2S Audio interface which is part of the Synopsis +- Designware HDMI block. +- + config DRM_NXP_PTN3460 + tristate "NXP PTN3460 DP/LVDS bridge" + depends on OF +@@ -86,4 +63,6 @@ source "drivers/gpu/drm/bridge/analogix/Kconfig" + + source "drivers/gpu/drm/bridge/adv7511/Kconfig" + ++source "drivers/gpu/drm/bridge/synopsys/Kconfig" ++ + endmenu +diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile +index 9a54f2ada2c2..4df86e927416 100644 +--- a/drivers/gpu/drm/bridge/Makefile ++++ b/drivers/gpu/drm/bridge/Makefile +@@ -2,12 +2,10 @@ ccflags-y := -Iinclude/drm + + obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o + obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o +-obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o +-obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o +-obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o + obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o + obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o + obj-$(CONFIG_DRM_SII902X) += sii902x.o + obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o + obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ + obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ ++obj-y += synopsys/ +diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig +new file mode 100644 +index 000000000000..40d2827a6d19 +--- /dev/null ++++ b/drivers/gpu/drm/bridge/synopsys/Kconfig +@@ -0,0 +1,23 @@ ++config DRM_DW_HDMI ++ tristate ++ select DRM_KMS_HELPER ++ ++config DRM_DW_HDMI_AHB_AUDIO ++ tristate "Synopsys Designware AHB Audio interface" ++ depends on DRM_DW_HDMI && SND ++ select SND_PCM ++ select SND_PCM_ELD ++ select SND_PCM_IEC958 ++ help ++ Support the AHB Audio interface which is part of the Synopsys ++ Designware HDMI block. This is used in conjunction with ++ the i.MX6 HDMI driver. ++ ++config DRM_DW_HDMI_I2S_AUDIO ++ tristate "Synopsys Designware I2S Audio interface" ++ depends on SND_SOC ++ depends on DRM_DW_HDMI ++ select SND_SOC_HDMI_CODEC ++ help ++ Support the I2S Audio interface which is part of the Synopsys ++ Designware HDMI block. +diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile +new file mode 100644 +index 000000000000..17aa7a65b57e +--- /dev/null ++++ b/drivers/gpu/drm/bridge/synopsys/Makefile +@@ -0,0 +1,5 @@ ++#ccflags-y := -Iinclude/drm ++ ++obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o ++obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o ++obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o +diff --git a/drivers/gpu/drm/bridge/dw-hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +similarity index 100% +rename from drivers/gpu/drm/bridge/dw-hdmi-ahb-audio.c +rename to drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c +diff --git a/drivers/gpu/drm/bridge/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +similarity index 100% +rename from drivers/gpu/drm/bridge/dw-hdmi-audio.h +rename to drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +diff --git a/drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +similarity index 100% +rename from drivers/gpu/drm/bridge/dw-hdmi-i2s-audio.c +rename to drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +similarity index 100% +rename from drivers/gpu/drm/bridge/dw-hdmi.c +rename to drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +similarity index 100% +rename from drivers/gpu/drm/bridge/dw-hdmi.h +rename to drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +-- +2.13.3 + diff --git a/patches.renesas/0235-drm-bridge-dw_hdmi-support-i2c-extended-read-mode.patch b/patches.renesas/0235-drm-bridge-dw_hdmi-support-i2c-extended-read-mode.patch new file mode 100644 index 00000000000000..98cd149be42995 --- /dev/null +++ b/patches.renesas/0235-drm-bridge-dw_hdmi-support-i2c-extended-read-mode.patch @@ -0,0 +1,117 @@ +From be9059ee366d592ad512e717c6126e63f355b4cc Mon Sep 17 00:00:00 2001 +From: Nickey Yang <nickey.yang@rock-chips.com> +Date: Mon, 20 Mar 2017 10:57:31 +0800 +Subject: [PATCH 235/286] drm/bridge: dw_hdmi: support i2c extended read mode + +"I2C Master Interface Extended Read Mode" implements a segment +pointer-based read operation using the Special Register configuration. + +This patch fix https://patchwork.kernel.org/patch/7098101/ mentioned +"The current implementation does not support "I2C Master Interface +Extended Read Mode" to read data addressed by non-zero segment +pointer, this means that if EDID has more than 1 extension blocks, +EDID reading operation won't succeed" + +With this patch, dw-hdmi can read EDID data with 1/2/4 blocks. + +Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> +Reviewed-by: Douglas Anderson <dianders@chromium.org> +Acked-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1489978651-16647-1-git-send-email-nickey.yang@rock-chips.com +(cherry picked from commit 94bb4dc132ed2e3a4d16649b0096c49d13670fe8) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 38 +++++++++++++++++++------------ + 1 file changed, 24 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 026a0dce7661..0d112cf6b969 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -33,6 +33,7 @@ + #include "dw-hdmi.h" + #include "dw-hdmi-audio.h" + ++#define DDC_SEGMENT_ADDR 0x30 + #define HDMI_EDID_LEN 512 + + #define RGB 0 +@@ -112,6 +113,7 @@ struct dw_hdmi_i2c { + + u8 slave_reg; + bool is_regaddr; ++ bool is_segment; + }; + + struct dw_hdmi_phy_data { +@@ -247,8 +249,12 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, + reinit_completion(&i2c->cmp); + + hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); +- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, +- HDMI_I2CM_OPERATION); ++ if (i2c->is_segment) ++ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, ++ HDMI_I2CM_OPERATION); ++ else ++ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, ++ HDMI_I2CM_OPERATION); + + stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); + if (!stat) +@@ -260,6 +266,7 @@ static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, + + *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); + } ++ i2c->is_segment = false; + + return 0; + } +@@ -309,12 +316,6 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, + dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); + + for (i = 0; i < num; i++) { +- if (msgs[i].addr != addr) { +- dev_warn(hdmi->dev, +- "unsupported transfer, changed slave address\n"); +- return -EOPNOTSUPP; +- } +- + if (msgs[i].len == 0) { + dev_dbg(hdmi->dev, + "unsupported transfer %d/%d, no data\n", +@@ -334,15 +335,24 @@ static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, + /* Set slave device register address on transfer */ + i2c->is_regaddr = false; + ++ /* Set segment pointer for I2C extended read mode operation */ ++ i2c->is_segment = false; ++ + for (i = 0; i < num; i++) { + dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", + i + 1, num, msgs[i].len, msgs[i].flags); +- +- if (msgs[i].flags & I2C_M_RD) +- ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len); +- else +- ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len); +- ++ if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { ++ i2c->is_segment = true; ++ hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); ++ hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); ++ } else { ++ if (msgs[i].flags & I2C_M_RD) ++ ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, ++ msgs[i].len); ++ else ++ ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, ++ msgs[i].len); ++ } + if (ret < 0) + break; + } +-- +2.13.3 + diff --git a/patches.renesas/0236-drm-bridge-dw-hdmi-add-HDMI-vendor-specific-infofram.patch b/patches.renesas/0236-drm-bridge-dw-hdmi-add-HDMI-vendor-specific-infofram.patch new file mode 100644 index 00000000000000..ba70b6607d33e4 --- /dev/null +++ b/patches.renesas/0236-drm-bridge-dw-hdmi-add-HDMI-vendor-specific-infofram.patch @@ -0,0 +1,109 @@ +From 638db3396ad9b503b213a372dd640394167c7828 Mon Sep 17 00:00:00 2001 +From: Nickey Yang <nickey.yang@rock-chips.com> +Date: Tue, 21 Mar 2017 15:36:17 +0800 +Subject: [PATCH 236/286] drm: bridge: dw-hdmi: add HDMI vendor specific + infoframe config + +Vendor specific infoframe is mandatory for 4K2K resolution. +Without this, the HDMI protocol compliance fails. + +Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1490081777-2232-1-git-send-email-nickey.yang@rock-chips.com +(cherry picked from commit 9aa1eca095579b8a8ea84d9bbd1fbdeff49cebd4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 53 +++++++++++++++++++++++++++++++ + drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 4 +++ + 2 files changed, 57 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 0d112cf6b969..af93f7a20697 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1240,6 +1240,58 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); + } + ++static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ struct hdmi_vendor_infoframe frame; ++ u8 buffer[10]; ++ ssize_t err; ++ ++ err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); ++ if (err < 0) ++ /* ++ * Going into that statement does not means vendor infoframe ++ * fails. It just informed us that vendor infoframe is not ++ * needed for the selected mode. Only 4k or stereoscopic 3D ++ * mode requires vendor infoframe. So just simply return. ++ */ ++ return; ++ ++ err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); ++ if (err < 0) { ++ dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", ++ err); ++ return; ++ } ++ hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, ++ HDMI_FC_DATAUTO0_VSD_MASK); ++ ++ /* Set the length of HDMI vendor specific InfoFrame payload */ ++ hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); ++ ++ /* Set 24bit IEEE Registration Identifier */ ++ hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); ++ hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); ++ hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); ++ ++ /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ ++ hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); ++ hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); ++ ++ if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) ++ hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); ++ ++ /* Packet frame interpolation */ ++ hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); ++ ++ /* Auto packets per frame and line spacing */ ++ hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); ++ ++ /* Configures the Frame Composer On RDRB mode */ ++ hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, ++ HDMI_FC_DATAUTO0_VSD_MASK); ++} ++ + static void hdmi_av_composer(struct dw_hdmi *hdmi, + const struct drm_display_mode *mode) + { +@@ -1489,6 +1541,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + + /* HDMI Initialization Step F - Configure AVI InfoFrame */ + hdmi_config_AVI(hdmi, mode); ++ hdmi_config_vendor_specific_infoframe(hdmi, mode); + } else { + dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); + } +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +index 325b0b8ae639..c59f87e1483e 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +@@ -854,6 +854,10 @@ enum { + HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, + HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, + ++/* FC_DATAUTO0 field values */ ++ HDMI_FC_DATAUTO0_VSD_MASK = 0x08, ++ HDMI_FC_DATAUTO0_VSD_OFFSET = 3, ++ + /* PHY_CONF0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, +-- +2.13.3 + diff --git a/patches.renesas/0237-drm-dw_hdmi-Don-t-rely-on-the-status-of-the-bridge-f.patch b/patches.renesas/0237-drm-dw_hdmi-Don-t-rely-on-the-status-of-the-bridge-f.patch new file mode 100644 index 00000000000000..c1355648070ca0 --- /dev/null +++ b/patches.renesas/0237-drm-dw_hdmi-Don-t-rely-on-the-status-of-the-bridge-f.patch @@ -0,0 +1,75 @@ +From 13f1a5bf4e8a7f29e3cb46f88362bf62ef77aaab Mon Sep 17 00:00:00 2001 +From: Romain Perier <romain.perier@collabora.com> +Date: Mon, 27 Mar 2017 11:45:07 +0530 +Subject: [PATCH 237/286] drm: dw_hdmi: Don't rely on the status of the bridge + for updating HPD + +Currently, the irq handler that monitors changes for HPD and RX_SENSE +relies on the status of the bridge for updating the status of the HPD. +The update is done only when the bridge is enabled. + +However, on Rockchip platforms we have found use cases where it could be +a problem. When HDMI is being used, turning off/on the screen or +unplugging/re-plugging the cable, the following simplified code path +will happen: + +- dw_hdmi_irq() will be triggered by an HPD event, as the bridge is on +hdmi->disabled is false, then the handler will update the rxsense flag +accordingly. +- dw_hdmi_update_power() will be invoked with the mode +DRM_FORCE_UNSPECIFIED and rxsense == 1, so dw_hdmi_poweroff() will be +called and the PHY will be desactivated (its pixel clocks and TMDS) + +[...] + +- dw_hdmi_bridge_disable() will be invoked, the bridge will be marked as +disabled. + +- dw_hdmi_irq() will be triggered by an HPD event, as the bridge is +currently disabled the HPD status won't be updated, so hdmi->rxsense +won't be changed. Even if the data part of the PHY is disabled, this +information coming from the HDMI Transmitter is correct and should be +saved. + +[...] + +- dw_hdmi_bridge_enable() will be invoked, the bridge will be marked as +enabled. +- dw_hdmi_update_power() will be called. When hdmi->force is equal to +DRM_FORCE_UNSPECIFIED the function will rely on hdmi->rxsense. If this +field has not been updated by the irq handler, it will be false and +DRM_FORCE_ON won't be put to hdmi->force. + +Consequently, most of the time dw_hdmi_poweron() won't be called in this +use case, TMDS won't be re-enabled the PHY won't be re-initialized, +resulting in a "Signal not found". + +This commit fixes the issue by removing the check for "!hdmi->disabled". +As already explained, even if the PHY is partially disabled, information +coming from HDMI Transmitter about HPD should be saved for a later use. + +Signed-off-by: Romain Perier <romain.perier@collabora.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: https://patchwork.freedesktop.org/patch/143602/ +(cherry picked from commit 187697a4544c20d4b77193275a7e10f85506d14d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index af93f7a20697..32f02e92e0b9 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1916,7 +1916,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + if (intr_stat & + (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { + mutex_lock(&hdmi->mutex); +- if (!hdmi->disabled && !hdmi->force) { ++ if (!hdmi->force) { + /* + * If the RX sense status indicates we're disconnected, + * clear the software rxsense status. +-- +2.13.3 + diff --git a/patches.renesas/0238-dt-bindings-display-renesas-Add-R-Car-Gen3-HDMI-TX-D.patch b/patches.renesas/0238-dt-bindings-display-renesas-Add-R-Car-Gen3-HDMI-TX-D.patch new file mode 100644 index 00000000000000..091b5a2a46f7af --- /dev/null +++ b/patches.renesas/0238-dt-bindings-display-renesas-Add-R-Car-Gen3-HDMI-TX-D.patch @@ -0,0 +1,116 @@ +From d3caa31fb90676e50b6b51163dced0d885c6552f Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 2 Dec 2016 01:02:53 +0200 +Subject: [PATCH 238/286] dt-bindings: display: renesas: Add R-Car Gen3 HDMI TX + DT bindings + +The Renesas R-Car Gen3 SoCs use a Synopsys DWC HDMI TX encoder IP. Add +corresponding device tree bindings based on the DWC HDMI TX bindings +model. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Acked-by: Rob Herring <robh@kernel.org> +(cherry picked from commit 907c1bbd513db7e9aee63b31627c325e39e7d9ba) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + .../bindings/display/bridge/renesas,dw-hdmi.txt | 75 ++++++++++++++++++++++ + MAINTAINERS | 1 + + 2 files changed, 76 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt + +diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +new file mode 100644 +index 000000000000..f6b3f36d422b +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt +@@ -0,0 +1,75 @@ ++Renesas Gen3 DWC HDMI TX Encoder ++================================ ++ ++The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP ++with a companion PHY IP. ++ ++These DT bindings follow the Synopsys DWC HDMI TX bindings defined in ++Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the ++following device-specific properties. ++ ++ ++Required properties: ++ ++- compatible : Shall contain one or more of ++ - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX ++ - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX ++ ++ When compatible with generic versions, nodes must list the SoC-specific ++ version corresponding to the platform first, followed by the ++ family-specific version. ++ ++- reg: See dw_hdmi.txt. ++- interrupts: HDMI interrupt number ++- clocks: See dw_hdmi.txt. ++- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. ++- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0 ++ corresponding to the video input of the controller and one port numbered 1 ++ corresponding to its HDMI output. Each port shall have a single endpoint. ++ ++Optional properties: ++ ++- power-domains: Shall reference the power domain that contains the DWC HDMI, ++ if any. ++ ++ ++Example: ++ ++ hdmi0: hdmi0@fead0000 { ++ compatible = "renesas,r8a7795-dw-hdmi"; ++ reg = <0 0xfead0000 0 0x10000>; ++ interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>; ++ clock-names = "iahb", "isfr"; ++ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ dw_hdmi0_in: endpoint { ++ remote-endpoint = <&du_out_hdmi0>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ rcar_dw_hdmi0_out: endpoint { ++ remote-endpoint = <&hdmi0_con>; ++ }; ++ }; ++ }; ++ }; ++ ++ hdmi0-out { ++ compatible = "hdmi-connector"; ++ label = "HDMI0 OUT"; ++ type = "a"; ++ ++ port { ++ hdmi0_con: endpoint { ++ remote-endpoint = <&rcar_dw_hdmi0_out>; ++ }; ++ }; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index f9c1c75a6af9..2e2d94be8c54 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4207,6 +4207,7 @@ S: Supported + F: drivers/gpu/drm/rcar-du/ + F: drivers/gpu/drm/shmobile/ + F: include/linux/platform_data/shmob_drm.h ++F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt + F: Documentation/devicetree/bindings/display/renesas,du.txt + + DRM DRIVER FOR QXL VIRTUAL GPU +-- +2.13.3 + diff --git a/patches.renesas/0239-drm-bridge-dw-hdmi-Extract-PHY-interrupt-setup-to-a-.patch b/patches.renesas/0239-drm-bridge-dw-hdmi-Extract-PHY-interrupt-setup-to-a-.patch new file mode 100644 index 00000000000000..a2d6db203613f4 --- /dev/null +++ b/patches.renesas/0239-drm-bridge-dw-hdmi-Extract-PHY-interrupt-setup-to-a-.patch @@ -0,0 +1,114 @@ +From 72d9cb9a6144567d362e748c753cbee6adc20255 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Tue, 4 Apr 2017 14:31:56 +0200 +Subject: [PATCH 239/286] drm: bridge: dw-hdmi: Extract PHY interrupt setup to + a function + +In preparation for adding PHY operations to handle RX SENSE and HPD, +group all the PHY interrupt setup code in a single location and extract +it to a separate function. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +[narmstrong: renamed dw_hdmi_fb_registered to dw_hdmi_setup_i2c] +Reviewed-by: Archit Taneja <architt@codeaurora.org> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> + +(cherry picked from commit a23d6265f033501529932db2d6b3f4bc138552ab) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 51 ++++++++++++++----------------- + 1 file changed, 23 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 32f02e92e0b9..ff1fae3a31a4 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1558,8 +1558,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + return 0; + } + +-/* Wait until we are registered to enable interrupts */ +-static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi) ++static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) + { + hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, + HDMI_PHY_I2CM_INT_ADDR); +@@ -1567,15 +1566,6 @@ static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi) + hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, + HDMI_PHY_I2CM_CTLINT_ADDR); +- +- /* enable cable hot plug irq */ +- hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); +- +- /* Clear Hotplug interrupts */ +- hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, +- HDMI_IH_PHY_STAT0); +- +- return 0; + } + + static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) +@@ -1693,6 +1683,26 @@ static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) + hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); + } + ++static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi) ++{ ++ /* ++ * Configure the PHY RX SENSE and HPD interrupts polarities and clear ++ * any pending interrupt. ++ */ ++ hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); ++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, ++ HDMI_IH_PHY_STAT0); ++ ++ /* Enable cable hot plug irq. */ ++ hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); ++ ++ /* Clear and unmute interrupts. */ ++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, ++ HDMI_IH_PHY_STAT0); ++ hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), ++ HDMI_IH_MUTE_PHY_STAT0); ++} ++ + static enum drm_connector_status + dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + { +@@ -2204,29 +2214,14 @@ __dw_hdmi_probe(struct platform_device *pdev, + hdmi->ddc = NULL; + } + +- /* +- * Configure registers related to HDMI interrupt +- * generation before registering IRQ. +- */ +- hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); +- +- /* Clear Hotplug interrupts */ +- hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, +- HDMI_IH_PHY_STAT0); +- + hdmi->bridge.driver_private = hdmi; + hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; + #ifdef CONFIG_OF + hdmi->bridge.of_node = pdev->dev.of_node; + #endif + +- ret = dw_hdmi_fb_registered(hdmi); +- if (ret) +- goto err_iahb; +- +- /* Unmute interrupts */ +- hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), +- HDMI_IH_MUTE_PHY_STAT0); ++ dw_hdmi_setup_i2c(hdmi); ++ dw_hdmi_phy_setup_hpd(hdmi); + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; +-- +2.13.3 + diff --git a/patches.renesas/0240-media-uapi-Add-RGB-and-YUV-bus-formats-for-Synopsys-.patch b/patches.renesas/0240-media-uapi-Add-RGB-and-YUV-bus-formats-for-Synopsys-.patch new file mode 100644 index 00000000000000..8e54646ca71318 --- /dev/null +++ b/patches.renesas/0240-media-uapi-Add-RGB-and-YUV-bus-formats-for-Synopsys-.patch @@ -0,0 +1,73 @@ +From 099e1369fcad6649a427919801b5a2de6ea20581 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Mon, 3 Apr 2017 16:42:34 +0200 +Subject: [PATCH 240/286] media: uapi: Add RGB and YUV bus formats for Synopsys + HDMI TX Controller + +In order to describe the RGB and YUV bus formats used to feed the +Synopsys DesignWare HDMI TX Controller, add missing formats to the +list of Bus Formats. + +Documentation for these formats is added in a separate patch. + +Reviewed-by: Archit Taneja <architt@codeaurora.org> +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Acked-by: Hans Verkuil <hans.verkuil@cisco.com> +Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Signed-off-by: Sean Paul <seanpaul@chromium.org> +Link: http://patchwork.freedesktop.org/patch/msgid/1491230558-10804-3-git-send-email-narmstrong@baylibre.com +(cherry picked from commit d0353118fd589c127875290017c7fdd266937bee) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/uapi/linux/media-bus-format.h | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h +index 2168759c1287..ef6fb307d2ce 100644 +--- a/include/uapi/linux/media-bus-format.h ++++ b/include/uapi/linux/media-bus-format.h +@@ -33,7 +33,7 @@ + + #define MEDIA_BUS_FMT_FIXED 0x0001 + +-/* RGB - next is 0x1018 */ ++/* RGB - next is 0x101b */ + #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 + #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 + #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 +@@ -57,8 +57,11 @@ + #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 + #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d + #define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f ++#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 ++#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 ++#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a + +-/* YUV (including grey) - next is 0x2026 */ ++/* YUV (including grey) - next is 0x202c */ + #define MEDIA_BUS_FMT_Y8_1X8 0x2001 + #define MEDIA_BUS_FMT_UV8_1X8 0x2015 + #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 +@@ -90,12 +93,18 @@ + #define MEDIA_BUS_FMT_YVYU10_1X20 0x200e + #define MEDIA_BUS_FMT_VUY8_1X24 0x2024 + #define MEDIA_BUS_FMT_YUV8_1X24 0x2025 ++#define MEDIA_BUS_FMT_UYYVYY8_0_5X24 0x2026 + #define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 + #define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 + #define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 + #define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 + #define MEDIA_BUS_FMT_YUV10_1X30 0x2016 ++#define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 + #define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 ++#define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 ++#define MEDIA_BUS_FMT_YUV12_1X36 0x2029 ++#define MEDIA_BUS_FMT_YUV16_1X48 0x202a ++#define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b + + /* Bayer - next is 0x3021 */ + #define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 +-- +2.13.3 + diff --git a/patches.renesas/0241-drm-bridge-dw-hdmi-Switch-to-V4L-bus-format-and-enco.patch b/patches.renesas/0241-drm-bridge-dw-hdmi-Switch-to-V4L-bus-format-and-enco.patch new file mode 100644 index 00000000000000..bfb3d3b109c918 --- /dev/null +++ b/patches.renesas/0241-drm-bridge-dw-hdmi-Switch-to-V4L-bus-format-and-enco.patch @@ -0,0 +1,559 @@ +From 9c43da13c21d0ba72bbaad864062d72b7d4dbef1 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Tue, 4 Apr 2017 14:31:57 +0200 +Subject: [PATCH 241/286] drm: bridge: dw-hdmi: Switch to V4L bus format and + encodings + +Switch code to use the newly introduced V4L bus formats IDs instead of custom +defines. Also use the V4L encoding defines. + +Some display pipelines can only provide non-RBG input pixels to the HDMI TX +Controller, this patch takes the pixel format from the plat_data if provided. + +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Reviewed-by: Archit Taneja <architt@codeaurora.org> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +(cherry picked from commit def23aa7e9821a3dfe3fb7b139dd0229a89fdeb0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 326 +++++++++++++++++++++--------- + include/drm/bridge/dw_hdmi.h | 63 ++++++ + 2 files changed, 294 insertions(+), 95 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index ff1fae3a31a4..16d5fff3e697 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -30,18 +30,15 @@ + #include <drm/drm_encoder_slave.h> + #include <drm/bridge/dw_hdmi.h> + ++#include <uapi/linux/media-bus-format.h> ++#include <uapi/linux/videodev2.h> ++ + #include "dw-hdmi.h" + #include "dw-hdmi-audio.h" + + #define DDC_SEGMENT_ADDR 0x30 + #define HDMI_EDID_LEN 512 + +-#define RGB 0 +-#define YCBCR444 1 +-#define YCBCR422_16BITS 2 +-#define YCBCR422_8BITS 3 +-#define XVYCC444 4 +- + enum hdmi_datamap { + RGB444_8B = 0x01, + RGB444_10B = 0x03, +@@ -95,10 +92,10 @@ struct hdmi_vmode { + }; + + struct hdmi_data_info { +- unsigned int enc_in_format; +- unsigned int enc_out_format; +- unsigned int enc_color_depth; +- unsigned int colorimetry; ++ unsigned int enc_in_bus_format; ++ unsigned int enc_out_bus_format; ++ unsigned int enc_in_encoding; ++ unsigned int enc_out_encoding; + unsigned int pix_repet_factor; + unsigned int hdcp_enable; + struct hdmi_vmode video_mode; +@@ -567,6 +564,92 @@ void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) + } + EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); + ++static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return true; ++ ++ default: ++ return false; ++ } ++} ++ ++static int hdmi_bus_fmt_color_depth(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ return 8; ++ ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ return 10; ++ ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ return 12; ++ ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ return 16; ++ ++ default: ++ return 0; ++ } ++} ++ + /* + * this submodule is responsible for the video data synchronization. + * for example, for RGB 4:4:4 input, the data map is defined as +@@ -579,37 +662,49 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) + int color_format = 0; + u8 val; + +- if (hdmi->hdmi_data.enc_in_format == RGB) { +- if (hdmi->hdmi_data.enc_color_depth == 8) +- color_format = 0x01; +- else if (hdmi->hdmi_data.enc_color_depth == 10) +- color_format = 0x03; +- else if (hdmi->hdmi_data.enc_color_depth == 12) +- color_format = 0x05; +- else if (hdmi->hdmi_data.enc_color_depth == 16) +- color_format = 0x07; +- else +- return; +- } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) { +- if (hdmi->hdmi_data.enc_color_depth == 8) +- color_format = 0x09; +- else if (hdmi->hdmi_data.enc_color_depth == 10) +- color_format = 0x0B; +- else if (hdmi->hdmi_data.enc_color_depth == 12) +- color_format = 0x0D; +- else if (hdmi->hdmi_data.enc_color_depth == 16) +- color_format = 0x0F; +- else +- return; +- } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) { +- if (hdmi->hdmi_data.enc_color_depth == 8) +- color_format = 0x16; +- else if (hdmi->hdmi_data.enc_color_depth == 10) +- color_format = 0x14; +- else if (hdmi->hdmi_data.enc_color_depth == 12) +- color_format = 0x12; +- else +- return; ++ switch (hdmi->hdmi_data.enc_in_bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ color_format = 0x01; ++ break; ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ color_format = 0x03; ++ break; ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ color_format = 0x05; ++ break; ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ color_format = 0x07; ++ break; ++ ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ color_format = 0x09; ++ break; ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ color_format = 0x0B; ++ break; ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_UYYVYY12_0_5X36: ++ color_format = 0x0D; ++ break; ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ case MEDIA_BUS_FMT_UYYVYY16_0_5X48: ++ color_format = 0x0F; ++ break; ++ ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ color_format = 0x16; ++ break; ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ color_format = 0x14; ++ break; ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ color_format = 0x12; ++ break; ++ ++ default: ++ return; + } + + val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | +@@ -632,26 +727,30 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi) + + static int is_color_space_conversion(struct dw_hdmi *hdmi) + { +- return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format; ++ return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; + } + + static int is_color_space_decimation(struct dw_hdmi *hdmi) + { +- if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS) ++ if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) + return 0; +- if (hdmi->hdmi_data.enc_in_format == RGB || +- hdmi->hdmi_data.enc_in_format == YCBCR444) ++ ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || ++ hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) + return 1; ++ + return 0; + } + + static int is_color_space_interpolation(struct dw_hdmi *hdmi) + { +- if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS) ++ if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) + return 0; +- if (hdmi->hdmi_data.enc_out_format == RGB || +- hdmi->hdmi_data.enc_out_format == YCBCR444) ++ ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || ++ hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) + return 1; ++ + return 0; + } + +@@ -662,15 +761,16 @@ static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) + u32 csc_scale = 1; + + if (is_color_space_conversion(hdmi)) { +- if (hdmi->hdmi_data.enc_out_format == RGB) { +- if (hdmi->hdmi_data.colorimetry == +- HDMI_COLORIMETRY_ITU_601) ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { ++ if (hdmi->hdmi_data.enc_out_encoding == ++ V4L2_YCBCR_ENC_601) + csc_coeff = &csc_coeff_rgb_out_eitu601; + else + csc_coeff = &csc_coeff_rgb_out_eitu709; +- } else if (hdmi->hdmi_data.enc_in_format == RGB) { +- if (hdmi->hdmi_data.colorimetry == +- HDMI_COLORIMETRY_ITU_601) ++ } else if (hdmi_bus_fmt_is_rgb( ++ hdmi->hdmi_data.enc_in_bus_format)) { ++ if (hdmi->hdmi_data.enc_out_encoding == ++ V4L2_YCBCR_ENC_601) + csc_coeff = &csc_coeff_rgb_in_eitu601; + else + csc_coeff = &csc_coeff_rgb_in_eitu709; +@@ -708,16 +808,23 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) + else if (is_color_space_decimation(hdmi)) + decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; + +- if (hdmi->hdmi_data.enc_color_depth == 8) ++ switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { ++ case 8: + color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; +- else if (hdmi->hdmi_data.enc_color_depth == 10) ++ break; ++ case 10: + color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; +- else if (hdmi->hdmi_data.enc_color_depth == 12) ++ break; ++ case 12: + color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; +- else if (hdmi->hdmi_data.enc_color_depth == 16) ++ break; ++ case 16: + color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; +- else ++ break; ++ ++ default: + return; ++ } + + /* Configure the CSC registers */ + hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); +@@ -740,32 +847,43 @@ static void hdmi_video_packetize(struct dw_hdmi *hdmi) + struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; + u8 val, vp_conf; + +- if (hdmi_data->enc_out_format == RGB || +- hdmi_data->enc_out_format == YCBCR444) { +- if (!hdmi_data->enc_color_depth) { +- output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; +- } else if (hdmi_data->enc_color_depth == 8) { ++ if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || ++ hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) { ++ switch (hdmi_bus_fmt_color_depth( ++ hdmi->hdmi_data.enc_out_bus_format)) { ++ case 8: + color_depth = 4; + output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; +- } else if (hdmi_data->enc_color_depth == 10) { ++ break; ++ case 10: + color_depth = 5; +- } else if (hdmi_data->enc_color_depth == 12) { ++ break; ++ case 12: + color_depth = 6; +- } else if (hdmi_data->enc_color_depth == 16) { ++ break; ++ case 16: + color_depth = 7; +- } else { +- return; ++ break; ++ default: ++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; + } +- } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { +- if (!hdmi_data->enc_color_depth || +- hdmi_data->enc_color_depth == 8) ++ } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { ++ switch (hdmi_bus_fmt_color_depth( ++ hdmi->hdmi_data.enc_out_bus_format)) { ++ case 0: ++ case 8: + remap_size = HDMI_VP_REMAP_YCC422_16bit; +- else if (hdmi_data->enc_color_depth == 10) ++ break; ++ case 10: + remap_size = HDMI_VP_REMAP_YCC422_20bit; +- else if (hdmi_data->enc_color_depth == 12) ++ break; ++ case 12: + remap_size = HDMI_VP_REMAP_YCC422_24bit; +- else ++ break; ++ ++ default: + return; ++ } + output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; + } else { + return; +@@ -1148,28 +1266,35 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + /* Initialise info frame from DRM mode */ + drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + +- if (hdmi->hdmi_data.enc_out_format == YCBCR444) ++ if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV444; +- else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) ++ else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) + frame.colorspace = HDMI_COLORSPACE_YUV422; + else + frame.colorspace = HDMI_COLORSPACE_RGB; + + /* Set up colorimetry */ +- if (hdmi->hdmi_data.enc_out_format == XVYCC444) { +- frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; +- if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601) +- frame.extended_colorimetry = ++ switch (hdmi->hdmi_data.enc_out_encoding) { ++ case V4L2_YCBCR_ENC_601: ++ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ else ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; +- else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/ +- frame.extended_colorimetry = ++ case V4L2_YCBCR_ENC_709: ++ if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) ++ frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; ++ else ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_709; ++ frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; +- } else if (hdmi->hdmi_data.enc_out_format != RGB) { +- frame.colorimetry = hdmi->hdmi_data.colorimetry; +- frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; +- } else { /* Carries no data */ +- frame.colorimetry = HDMI_COLORIMETRY_NONE; +- frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ break; ++ default: /* Carries no data */ ++ frame.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ frame.extended_colorimetry = ++ HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ break; + } + + frame.scan_mode = HDMI_SCAN_MODE_NONE; +@@ -1498,19 +1623,30 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + (hdmi->vic == 21) || (hdmi->vic == 22) || + (hdmi->vic == 2) || (hdmi->vic == 3) || + (hdmi->vic == 17) || (hdmi->vic == 18)) +- hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; ++ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; + else +- hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; ++ hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; + + hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; + hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; + +- /* TODO: Get input format from IPU (via FB driver interface) */ +- hdmi->hdmi_data.enc_in_format = RGB; ++ /* TOFIX: Get input format from plat data or fallback to RGB888 */ ++ if (hdmi->plat_data->input_bus_format >= 0) ++ hdmi->hdmi_data.enc_in_bus_format = ++ hdmi->plat_data->input_bus_format; ++ else ++ hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; ++ ++ /* TOFIX: Get input encoding from plat data or fallback to none */ ++ if (hdmi->plat_data->input_bus_encoding >= 0) ++ hdmi->hdmi_data.enc_in_encoding = ++ hdmi->plat_data->input_bus_encoding; ++ else ++ hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; + +- hdmi->hdmi_data.enc_out_format = RGB; ++ /* TOFIX: Default to RGB888 output format */ ++ hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + +- hdmi->hdmi_data.enc_color_depth = 8; + hdmi->hdmi_data.pix_repet_factor = 0; + hdmi->hdmi_data.hdcp_enable = 0; + hdmi->hdmi_data.video_mode.mdataenablepolarity = true; +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index bcceee8114a4..5d6b92c6c0bc 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -14,6 +14,67 @@ + + struct dw_hdmi; + ++/** ++ * DOC: Supported input formats and encodings ++ * ++ * Depending on the Hardware configuration of the Controller IP, it supports ++ * a subset of the following input formats and encodings on its internal ++ * 48bit bus. ++ * ++ * +----------------------+----------------------------------+------------------------------+ ++ * + Format Name + Format Code + Encodings + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + RGB 4:4:4 8bit + ``MEDIA_BUS_FMT_RGB888_1X24`` + ``V4L2_YCBCR_ENC_DEFAULT`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + RGB 4:4:4 10bits + ``MEDIA_BUS_FMT_RGB101010_1X30`` + ``V4L2_YCBCR_ENC_DEFAULT`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + RGB 4:4:4 12bits + ``MEDIA_BUS_FMT_RGB121212_1X36`` + ``V4L2_YCBCR_ENC_DEFAULT`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + RGB 4:4:4 16bits + ``MEDIA_BUS_FMT_RGB161616_1X48`` + ``V4L2_YCBCR_ENC_DEFAULT`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:4:4 8bit + ``MEDIA_BUS_FMT_YUV8_1X24`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV601`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:4:4 10bits + ``MEDIA_BUS_FMT_YUV10_1X30`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV601`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:4:4 12bits + ``MEDIA_BUS_FMT_YUV12_1X36`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV601`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:4:4 16bits + ``MEDIA_BUS_FMT_YUV16_1X48`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV601`` + ++ * + + + or ``V4L2_YCBCR_ENC_XV709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:2 8bit + ``MEDIA_BUS_FMT_UYVY8_1X16`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:2 10bits + ``MEDIA_BUS_FMT_UYVY10_1X20`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:2 12bits + ``MEDIA_BUS_FMT_UYVY12_1X24`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:0 8bit + ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` + ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:0 10bits + ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``+ ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:0 12bits + ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``+ ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ * + YCbCr 4:2:0 16bits + ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``+ ``V4L2_YCBCR_ENC_601`` + ++ * + + + or ``V4L2_YCBCR_ENC_709`` + ++ * +----------------------+----------------------------------+------------------------------+ ++ */ ++ + enum { + DW_HDMI_RES_8, + DW_HDMI_RES_10, +@@ -62,6 +123,8 @@ struct dw_hdmi_plat_data { + struct regmap *regm; + enum drm_mode_status (*mode_valid)(struct drm_connector *connector, + struct drm_display_mode *mode); ++ unsigned long input_bus_format; ++ unsigned long input_bus_encoding; + + /* Vendor PHY support */ + const struct dw_hdmi_phy_ops *phy_ops; +-- +2.13.3 + diff --git a/patches.renesas/0242-drm-bridge-dw-hdmi-Move-HPD-handling-to-PHY-operatio.patch b/patches.renesas/0242-drm-bridge-dw-hdmi-Move-HPD-handling-to-PHY-operatio.patch new file mode 100644 index 00000000000000..49e3a2de7674ef --- /dev/null +++ b/patches.renesas/0242-drm-bridge-dw-hdmi-Move-HPD-handling-to-PHY-operatio.patch @@ -0,0 +1,231 @@ +From 5dbc8b8c1806051cdf79dc75c6bb44f53c3076f0 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Tue, 4 Apr 2017 14:31:59 +0200 +Subject: [PATCH 242/286] drm: bridge: dw-hdmi: Move HPD handling to PHY + operations + +The HDMI TX controller support HPD and RXSENSE signaling from the PHY +via it's STAT0 PHY interface, but some vendor PHYs can manage these +signals independently from the controller, thus these STAT0 handling +should be moved to PHY specific operations and become optional. + +The existing STAT0 HPD and RXSENSE handling code is refactored into +a supplementaty set of default PHY operations that are used automatically +when the platform glue doesn't provide its own operations. + +Reviewed-by: Jose Abreu <joabreu@synopsys.com> +Reviewed-by: Archit Taneja <architt@codeaurora.org> +Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Link: http://patchwork.freedesktop.org/patch/msgid/1491309119-24220-2-git-send-email-narmstrong@baylibre.com +(cherry picked from commit 386d3299ef7298a3bc57e2ff3498ce41ac7f6184) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 135 ++++++++++++++++++------------ + include/drm/bridge/dw_hdmi.h | 5 ++ + 2 files changed, 86 insertions(+), 54 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 16d5fff3e697..84cc949eae2b 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1229,10 +1229,46 @@ static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, + connector_status_connected : connector_status_disconnected; + } + ++static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, ++ bool force, bool disabled, bool rxsense) ++{ ++ u8 old_mask = hdmi->phy_mask; ++ ++ if (force || disabled || !rxsense) ++ hdmi->phy_mask |= HDMI_PHY_RX_SENSE; ++ else ++ hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; ++ ++ if (old_mask != hdmi->phy_mask) ++ hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); ++} ++ ++static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) ++{ ++ /* ++ * Configure the PHY RX SENSE and HPD interrupts polarities and clear ++ * any pending interrupt. ++ */ ++ hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); ++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, ++ HDMI_IH_PHY_STAT0); ++ ++ /* Enable cable hot plug irq. */ ++ hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); ++ ++ /* Clear and unmute interrupts. */ ++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, ++ HDMI_IH_PHY_STAT0); ++ hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), ++ HDMI_IH_MUTE_PHY_STAT0); ++} ++ + static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { + .init = dw_hdmi_phy_init, + .disable = dw_hdmi_phy_disable, + .read_hpd = dw_hdmi_phy_read_hpd, ++ .update_hpd = dw_hdmi_phy_update_hpd, ++ .setup_hpd = dw_hdmi_phy_setup_hpd, + }; + + /* ----------------------------------------------------------------------------- +@@ -1808,35 +1844,10 @@ static void dw_hdmi_update_power(struct dw_hdmi *hdmi) + */ + static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) + { +- u8 old_mask = hdmi->phy_mask; +- +- if (hdmi->force || hdmi->disabled || !hdmi->rxsense) +- hdmi->phy_mask |= HDMI_PHY_RX_SENSE; +- else +- hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; +- +- if (old_mask != hdmi->phy_mask) +- hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); +-} +- +-static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi) +-{ +- /* +- * Configure the PHY RX SENSE and HPD interrupts polarities and clear +- * any pending interrupt. +- */ +- hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); +- hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, +- HDMI_IH_PHY_STAT0); +- +- /* Enable cable hot plug irq. */ +- hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); +- +- /* Clear and unmute interrupts. */ +- hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, +- HDMI_IH_PHY_STAT0); +- hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), +- HDMI_IH_MUTE_PHY_STAT0); ++ if (hdmi->phy.ops->update_hpd) ++ hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, ++ hdmi->force, hdmi->disabled, ++ hdmi->rxsense); + } + + static enum drm_connector_status +@@ -2028,6 +2039,41 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) + return ret; + } + ++void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) ++{ ++ mutex_lock(&hdmi->mutex); ++ ++ if (!hdmi->force) { ++ /* ++ * If the RX sense status indicates we're disconnected, ++ * clear the software rxsense status. ++ */ ++ if (!rx_sense) ++ hdmi->rxsense = false; ++ ++ /* ++ * Only set the software rxsense status when both ++ * rxsense and hpd indicates we're connected. ++ * This avoids what seems to be bad behaviour in ++ * at least iMX6S versions of the phy. ++ */ ++ if (hpd) ++ hdmi->rxsense = true; ++ ++ dw_hdmi_update_power(hdmi); ++ dw_hdmi_update_phy_mask(hdmi); ++ } ++ mutex_unlock(&hdmi->mutex); ++} ++ ++void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense) ++{ ++ struct dw_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense); ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); ++ + static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + { + struct dw_hdmi *hdmi = dev_id; +@@ -2060,30 +2106,10 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + * ask the source to re-read the EDID. + */ + if (intr_stat & +- (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { +- mutex_lock(&hdmi->mutex); +- if (!hdmi->force) { +- /* +- * If the RX sense status indicates we're disconnected, +- * clear the software rxsense status. +- */ +- if (!(phy_stat & HDMI_PHY_RX_SENSE)) +- hdmi->rxsense = false; +- +- /* +- * Only set the software rxsense status when both +- * rxsense and hpd indicates we're connected. +- * This avoids what seems to be bad behaviour in +- * at least iMX6S versions of the phy. +- */ +- if (phy_stat & HDMI_PHY_HPD) +- hdmi->rxsense = true; +- +- dw_hdmi_update_power(hdmi); +- dw_hdmi_update_phy_mask(hdmi); +- } +- mutex_unlock(&hdmi->mutex); +- } ++ (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) ++ __dw_hdmi_setup_rx_sense(hdmi, ++ phy_stat & HDMI_PHY_HPD, ++ phy_stat & HDMI_PHY_RX_SENSE); + + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + dev_dbg(hdmi->dev, "EVENT=%s\n", +@@ -2357,7 +2383,8 @@ __dw_hdmi_probe(struct platform_device *pdev, + #endif + + dw_hdmi_setup_i2c(hdmi); +- dw_hdmi_phy_setup_hpd(hdmi); ++ if (hdmi->phy.ops->setup_hpd) ++ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 5d6b92c6c0bc..ed599bea3f6c 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -117,6 +117,9 @@ struct dw_hdmi_phy_ops { + struct drm_display_mode *mode); + void (*disable)(struct dw_hdmi *hdmi, void *data); + enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data); ++ void (*update_hpd)(struct dw_hdmi *hdmi, void *data, ++ bool force, bool disabled, bool rxsense); ++ void (*setup_hpd)(struct dw_hdmi *hdmi, void *data); + }; + + struct dw_hdmi_plat_data { +@@ -147,6 +150,8 @@ void dw_hdmi_unbind(struct device *dev); + int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, + const struct dw_hdmi_plat_data *plat_data); + ++void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense); ++ + void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); + void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); + void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); +-- +2.13.3 + diff --git a/patches.renesas/0243-drm-bridge-dw-hdmi-remove-unused-hdmi_bus_fmt_is_yuv.patch b/patches.renesas/0243-drm-bridge-dw-hdmi-remove-unused-hdmi_bus_fmt_is_yuv.patch new file mode 100644 index 00000000000000..68f7ef70032318 --- /dev/null +++ b/patches.renesas/0243-drm-bridge-dw-hdmi-remove-unused-hdmi_bus_fmt_is_yuv.patch @@ -0,0 +1,46 @@ +From 49a6631e96fc1cb1c6b9f4f35d3a66cba2778977 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Wed, 5 Apr 2017 09:32:59 +0200 +Subject: [PATCH 243/286] drm: bridge: dw-hdmi: remove unused + hdmi_bus_fmt_is_yuv420 + +Remove usused yet hdmi_bus_fmt_is_yuv420 function. + +Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings") +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Link: http://patchwork.freedesktop.org/patch/msgid/1491377579-9353-1-git-send-email-narmstrong@baylibre.com +(cherry picked from commit 4c67b20c98a1a711cc010bff4927129d82a851c7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 84cc949eae2b..7dd669945b55 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -605,20 +605,6 @@ static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) + } + } + +-static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) +-{ +- switch (bus_format) { +- case MEDIA_BUS_FMT_UYYVYY8_0_5X24: +- case MEDIA_BUS_FMT_UYYVYY10_0_5X30: +- case MEDIA_BUS_FMT_UYYVYY12_0_5X36: +- case MEDIA_BUS_FMT_UYYVYY16_0_5X48: +- return true; +- +- default: +- return false; +- } +-} +- + static int hdmi_bus_fmt_color_depth(unsigned int bus_format) + { + switch (bus_format) { +-- +2.13.3 + diff --git a/patches.renesas/0244-drm-bridge-dw-hdmi-Add-a-missing-break-statement.patch b/patches.renesas/0244-drm-bridge-dw-hdmi-Add-a-missing-break-statement.patch new file mode 100644 index 00000000000000..8cb7de276787a7 --- /dev/null +++ b/patches.renesas/0244-drm-bridge-dw-hdmi-Add-a-missing-break-statement.patch @@ -0,0 +1,33 @@ +From 41f6cd91433fe935741c343b04223b6b6723f62e Mon Sep 17 00:00:00 2001 +From: Dan Carpenter <dan.carpenter@oracle.com> +Date: Thu, 6 Apr 2017 08:21:32 +0300 +Subject: [PATCH 244/286] drm: bridge: dw-hdmi: Add a missing break statement + +There was supposed to be a break before the next case statement. + +Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings") +Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> +Acked-by: Neil Armstrong <narmstrong@baylibre.com> +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Link: http://patchwork.freedesktop.org/patch/msgid/20170406052132.GA26605@mwanda +(cherry picked from commit f40d6560eba65b2a2b84805d2927fed96978669a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 7dd669945b55..5dc5a5fa44f5 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1304,6 +1304,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + frame.colorimetry = HDMI_COLORIMETRY_ITU_601; + frame.extended_colorimetry = + HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; ++ break; + case V4L2_YCBCR_ENC_709: + if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) + frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; +-- +2.13.3 + diff --git a/patches.renesas/0245-drm-bridge-dw-hdmi-fix-input-format-encoding-from-pl.patch b/patches.renesas/0245-drm-bridge-dw-hdmi-fix-input-format-encoding-from-pl.patch new file mode 100644 index 00000000000000..678be15f5fd3b2 --- /dev/null +++ b/patches.renesas/0245-drm-bridge-dw-hdmi-fix-input-format-encoding-from-pl.patch @@ -0,0 +1,60 @@ +From e2d8455e5c53f4d97284693650b87b2942a5b312 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong <narmstrong@baylibre.com> +Date: Thu, 6 Apr 2017 11:34:04 +0200 +Subject: [PATCH 245/286] drm: bridge: dw-hdmi: fix input format/encoding from + plat_data + +The plat_data->input_bus_format and plat_data->input_bus_encoding +are unsigned long and are always >=0, but the value 0 was still +considered as RGB888 for input_bus_format and default color space +for input_bus_encoding in the reworked code. + +This patch changes the if statement check for a non-zero value to +either use the default input bus_format and/or bus_encoding for a zero +value and the provided bus_format and/or bus_encoding for a +non zero value. + +Thanks to Dan Carpenter for his bug report at [1]. + +Tested on Amlogic P230 (with CSC enabled for YUV444 to RGB) and Rockchip +RK3288 ACT8846 EVB Board (no CSC involved, direct RGB passthrough). + +[1] http://lkml.kernel.org/r/20170406052120.GA26578@mwanda + +Cc: Dan Carpenter <dan.carpenter@oracle.com> +Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings") +Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> +Reviewed-by: Archit Taneja <architt@codeaurora.org> +[narmstrong@baylibre.com: reworded commit message and added Fixes tag] +Link: http://patchwork.freedesktop.org/patch/msgid/1491471244-24989-1-git-send-email-narmstrong@baylibre.com + +(cherry picked from commit e20c29aa722a90f3b8092b340362eabe488dbfc4) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 5dc5a5fa44f5..3bc856cc6daa 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1654,14 +1654,14 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; + + /* TOFIX: Get input format from plat data or fallback to RGB888 */ +- if (hdmi->plat_data->input_bus_format >= 0) ++ if (hdmi->plat_data->input_bus_format) + hdmi->hdmi_data.enc_in_bus_format = + hdmi->plat_data->input_bus_format; + else + hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; + + /* TOFIX: Get input encoding from plat data or fallback to none */ +- if (hdmi->plat_data->input_bus_encoding >= 0) ++ if (hdmi->plat_data->input_bus_encoding) + hdmi->hdmi_data.enc_in_encoding = + hdmi->plat_data->input_bus_encoding; + else +-- +2.13.3 + diff --git a/patches.renesas/0246-drm-dw-hdmi-Implement-the-mode_fixup-drm-helper.patch b/patches.renesas/0246-drm-dw-hdmi-Implement-the-mode_fixup-drm-helper.patch new file mode 100644 index 00000000000000..f981cf91efc1df --- /dev/null +++ b/patches.renesas/0246-drm-dw-hdmi-Implement-the-mode_fixup-drm-helper.patch @@ -0,0 +1,65 @@ +From 29af91364af8b7e44f5fa589a4790e8175b58c30 Mon Sep 17 00:00:00 2001 +From: Romain Perier <romain.perier@collabora.com> +Date: Fri, 7 Apr 2017 14:17:43 +0200 +Subject: [PATCH 246/286] drm: dw-hdmi: Implement the mode_fixup drm helper + +This helper is supposed to validate or reject the modeline before it +applied by the mode setting. Currently this function has been dropped, +it was previously set to a dummy function that always returned true. For +both cases, this means that userspace can ask for a bad modeline that +will be always accepted. + +On some platforms, like Rockchip, the drm dw_hdmi-rockchip variant driver +already implements the atomic_check drm helper, so mode_fixup cannot be +handled and implemented there (as drm_atomic_helper relies on either +atomic_check or mode_fixup). + +This commit implements this helper. It only checks that this mode is +correct from the connector point of view. + +Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> +Signed-off-by: Romain Perier <romain.perier@collabora.com> +Signed-off-by: Archit Taneja <architt@codeaurora.org> +Link: http://patchwork.freedesktop.org/patch/msgid/20170407121743.4142-1-romain.perier@collabora.com +(cherry picked from commit 6ce2ca580f10d8d76cc3661a0b6b88d419725c9c) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 3bc856cc6daa..4e1f54a675d8 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1947,6 +1947,20 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) + return 0; + } + ++static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, ++ const struct drm_display_mode *orig_mode, ++ struct drm_display_mode *mode) ++{ ++ struct dw_hdmi *hdmi = bridge->driver_private; ++ struct drm_connector *connector = &hdmi->connector; ++ enum drm_mode_status status; ++ ++ status = dw_hdmi_connector_mode_valid(connector, mode); ++ if (status != MODE_OK) ++ return false; ++ return true; ++} ++ + static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) +@@ -1988,6 +2002,7 @@ static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { + .enable = dw_hdmi_bridge_enable, + .disable = dw_hdmi_bridge_disable, + .mode_set = dw_hdmi_bridge_mode_set, ++ .mode_fixup = dw_hdmi_bridge_mode_fixup, + }; + + static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) +-- +2.13.3 + diff --git a/patches.renesas/0247-drm-rcar-du-Switch-to-encoder-.atomic_mode_set-helpe.patch b/patches.renesas/0247-drm-rcar-du-Switch-to-encoder-.atomic_mode_set-helpe.patch new file mode 100644 index 00000000000000..d01975ab235aca --- /dev/null +++ b/patches.renesas/0247-drm-rcar-du-Switch-to-encoder-.atomic_mode_set-helpe.patch @@ -0,0 +1,70 @@ +From 645efae95ea245f7342a4e9e0a40e39739ebc3b8 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 18 Nov 2016 15:37:37 +0200 +Subject: [PATCH 247/286] drm: rcar-du: Switch to encoder .atomic_mode_set() + helper function + +The native encoder mode set helper function for atomic drivers is +.atomic_mode_set(). Replace the legacy .mode_set() implementation. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit e79a7dfafa3adedb7653f6d14fea3376db5285e2) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 8 ++++---- + drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c | 8 ++++---- + 2 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +index ab8645c57e2d..3974d9495f37 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +@@ -83,16 +83,16 @@ static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder, + } + + static void rcar_du_encoder_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) + { + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); + +- rcar_du_crtc_route_output(encoder->crtc, renc->output); ++ rcar_du_crtc_route_output(crtc_state->crtc, renc->output); + } + + static const struct drm_encoder_helper_funcs encoder_helper_funcs = { +- .mode_set = rcar_du_encoder_mode_set, ++ .atomic_mode_set = rcar_du_encoder_mode_set, + .disable = rcar_du_encoder_disable, + .enable = rcar_du_encoder_enable, + .atomic_check = rcar_du_encoder_atomic_check, +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c +index c4c5d1abcff8..933a2547798e 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c +@@ -67,16 +67,16 @@ static int rcar_du_hdmienc_atomic_check(struct drm_encoder *encoder, + + + static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) + { + struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); + +- rcar_du_crtc_route_output(encoder->crtc, hdmienc->renc->output); ++ rcar_du_crtc_route_output(crtc_state->crtc, hdmienc->renc->output); + } + + static const struct drm_encoder_helper_funcs encoder_helper_funcs = { +- .mode_set = rcar_du_hdmienc_mode_set, ++ .atomic_mode_set = rcar_du_hdmienc_mode_set, + .disable = rcar_du_hdmienc_disable, + .enable = rcar_du_hdmienc_enable, + .atomic_check = rcar_du_hdmienc_atomic_check, +-- +2.13.3 + diff --git a/patches.renesas/0248-drm-rcar-du-Don-t-open-code-of_device_get_match_data.patch b/patches.renesas/0248-drm-rcar-du-Don-t-open-code-of_device_get_match_data.patch new file mode 100644 index 00000000000000..8031f31d561348 --- /dev/null +++ b/patches.renesas/0248-drm-rcar-du-Don-t-open-code-of_device_get_match_data.patch @@ -0,0 +1,36 @@ +From 543e75777fe98170b6b15f8da7aae0a4fcfe411d Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Sun, 16 Oct 2016 10:01:47 +0200 +Subject: [PATCH 248/286] drm: rcar-du: Don't open code + of_device_get_match_data() + +This change will also make Coverity happy by avoiding a theoretical NULL +pointer dereference; yet another reason is to use the above helper function +to tighten the code and make it more readable. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +(cherry picked from commit 9e7d80e648793d5bf263a3ec9cfb1cf29b86a6e0) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +index c05e00872778..e09e0e6194ba 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +@@ -351,7 +351,7 @@ static int rcar_du_probe(struct platform_device *pdev) + init_waitqueue_head(&rcdu->commit.wait); + + rcdu->dev = &pdev->dev; +- rcdu->info = of_match_device(rcar_du_of_table, rcdu->dev)->data; ++ rcdu->info = of_device_get_match_data(rcdu->dev); + + platform_set_drvdata(pdev, rcdu); + +-- +2.13.3 + diff --git a/patches.renesas/0249-drm-rcar-du-Handle-event-when-disabling-CRTCs.patch b/patches.renesas/0249-drm-rcar-du-Handle-event-when-disabling-CRTCs.patch new file mode 100644 index 00000000000000..232df2063add06 --- /dev/null +++ b/patches.renesas/0249-drm-rcar-du-Handle-event-when-disabling-CRTCs.patch @@ -0,0 +1,38 @@ +From 116104b12295ade36a1cd34fa1a7ef6930044aca Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 Feb 2017 13:30:35 +0200 +Subject: [PATCH 249/286] drm: rcar-du: Handle event when disabling CRTCs + +The driver currently handles vblank events only when updating planes on +a CRTC. The atomic update API however allows requesting an event when +disabling a CRTC. This currently leads to event objects being leaked in +the kernel and to events not being sent out. Fix it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 6dd47cfd03a058d08b8caffb06194aa0eb109cf1) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +index a2ec6d8796a0..3a81cc0fe299 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +@@ -488,6 +488,13 @@ static void rcar_du_crtc_disable(struct drm_crtc *crtc) + rcar_du_crtc_stop(rcrtc); + rcar_du_crtc_put(rcrtc); + ++ spin_lock_irq(&crtc->dev->event_lock); ++ if (crtc->state->event) { ++ drm_crtc_send_vblank_event(crtc, crtc->state->event); ++ crtc->state->event = NULL; ++ } ++ spin_unlock_irq(&crtc->dev->event_lock); ++ + rcrtc->outputs = 0; + } + +-- +2.13.3 + diff --git a/patches.renesas/0250-drm-rcar-du-Clear-handled-event-pointer-in-CRTC-stat.patch b/patches.renesas/0250-drm-rcar-du-Clear-handled-event-pointer-in-CRTC-stat.patch new file mode 100644 index 00000000000000..0c08583098a34c --- /dev/null +++ b/patches.renesas/0250-drm-rcar-du-Clear-handled-event-pointer-in-CRTC-stat.patch @@ -0,0 +1,44 @@ +From 499973b260751d5bc38f7b0d89f6b8b07373d525 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sun, 12 Feb 2017 02:45:11 +0200 +Subject: [PATCH 250/286] drm: rcar-du: Clear handled event pointer in CRTC + state + +The atomic commit helper requires drivers to clear the event pointer +stored in the CRTC state when the event is handled. In preparation to +using the helper, fix the driver. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 15b181a309e9c9bff8d0bc57d7da2d5f87c14186) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +index 3a81cc0fe299..75bcb5e19cca 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +@@ -501,16 +501,16 @@ static void rcar_du_crtc_disable(struct drm_crtc *crtc) + static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) + { +- struct drm_pending_vblank_event *event = crtc->state->event; + struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + struct drm_device *dev = rcrtc->crtc.dev; + unsigned long flags; + +- if (event) { ++ if (crtc->state->event) { + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + spin_lock_irqsave(&dev->event_lock, flags); +- rcrtc->event = event; ++ rcrtc->event = crtc->state->event; ++ crtc->state->event = NULL; + spin_unlock_irqrestore(&dev->event_lock, flags); + } + +-- +2.13.3 + diff --git a/patches.renesas/0251-drm-rcar-du-Use-DRM-core-s-atomic-commit-helper.patch b/patches.renesas/0251-drm-rcar-du-Use-DRM-core-s-atomic-commit-helper.patch new file mode 100644 index 00000000000000..5540bbbd29085c --- /dev/null +++ b/patches.renesas/0251-drm-rcar-du-Use-DRM-core-s-atomic-commit-helper.patch @@ -0,0 +1,156 @@ +From 086923dadd36a1aa92c5b82442fd0c0e4e3676c3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 10 Feb 2017 13:30:35 +0200 +Subject: [PATCH 251/286] drm: rcar-du: Use DRM core's atomic commit helper + +The DRM core atomic helper now supports asynchronous commits natively. +The custom rcar-du implementation isn't needed anymore, remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit a8fd12233e2348568893f1d0e251d8a4630a50af) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_kms.c | 99 ++++------------------------------- + 1 file changed, 9 insertions(+), 90 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +index b5d3f16cfa12..e775ae5e5f06 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +@@ -249,18 +249,9 @@ static int rcar_du_atomic_check(struct drm_device *dev, + return rcar_du_atomic_check_planes(dev, state); + } + +-struct rcar_du_commit { +- struct work_struct work; +- struct drm_device *dev; +- struct drm_atomic_state *state; +- u32 crtcs; +-}; +- +-static void rcar_du_atomic_complete(struct rcar_du_commit *commit) ++static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state) + { +- struct drm_device *dev = commit->dev; +- struct rcar_du_device *rcdu = dev->dev_private; +- struct drm_atomic_state *old_state = commit->state; ++ struct drm_device *dev = old_state->dev; + + /* Apply the atomic update. */ + drm_atomic_helper_commit_modeset_disables(dev, old_state); +@@ -268,98 +259,25 @@ static void rcar_du_atomic_complete(struct rcar_du_commit *commit) + drm_atomic_helper_commit_planes(dev, old_state, + DRM_PLANE_COMMIT_ACTIVE_ONLY); + ++ drm_atomic_helper_commit_hw_done(old_state); + drm_atomic_helper_wait_for_vblanks(dev, old_state); + + drm_atomic_helper_cleanup_planes(dev, old_state); +- +- drm_atomic_state_put(old_state); +- +- /* Complete the commit, wake up any waiter. */ +- spin_lock(&rcdu->commit.wait.lock); +- rcdu->commit.pending &= ~commit->crtcs; +- wake_up_all_locked(&rcdu->commit.wait); +- spin_unlock(&rcdu->commit.wait.lock); +- +- kfree(commit); +-} +- +-static void rcar_du_atomic_work(struct work_struct *work) +-{ +- struct rcar_du_commit *commit = +- container_of(work, struct rcar_du_commit, work); +- +- rcar_du_atomic_complete(commit); +-} +- +-static int rcar_du_atomic_commit(struct drm_device *dev, +- struct drm_atomic_state *state, +- bool nonblock) +-{ +- struct rcar_du_device *rcdu = dev->dev_private; +- struct rcar_du_commit *commit; +- struct drm_crtc *crtc; +- struct drm_crtc_state *crtc_state; +- unsigned int i; +- int ret; +- +- ret = drm_atomic_helper_prepare_planes(dev, state); +- if (ret) +- return ret; +- +- /* Allocate the commit object. */ +- commit = kzalloc(sizeof(*commit), GFP_KERNEL); +- if (commit == NULL) { +- ret = -ENOMEM; +- goto error; +- } +- +- INIT_WORK(&commit->work, rcar_du_atomic_work); +- commit->dev = dev; +- commit->state = state; +- +- /* Wait until all affected CRTCs have completed previous commits and +- * mark them as pending. +- */ +- for_each_crtc_in_state(state, crtc, crtc_state, i) +- commit->crtcs |= drm_crtc_mask(crtc); +- +- spin_lock(&rcdu->commit.wait.lock); +- ret = wait_event_interruptible_locked(rcdu->commit.wait, +- !(rcdu->commit.pending & commit->crtcs)); +- if (ret == 0) +- rcdu->commit.pending |= commit->crtcs; +- spin_unlock(&rcdu->commit.wait.lock); +- +- if (ret) { +- kfree(commit); +- goto error; +- } +- +- /* Swap the state, this is the point of no return. */ +- drm_atomic_helper_swap_state(state, true); +- +- drm_atomic_state_get(state); +- if (nonblock) +- schedule_work(&commit->work); +- else +- rcar_du_atomic_complete(commit); +- +- return 0; +- +-error: +- drm_atomic_helper_cleanup_planes(dev, state); +- return ret; + } + + /* ----------------------------------------------------------------------------- + * Initialization + */ + ++static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = { ++ .atomic_commit_tail = rcar_du_atomic_commit_tail, ++}; ++ + static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = { + .fb_create = rcar_du_fb_create, + .output_poll_changed = rcar_du_output_poll_changed, + .atomic_check = rcar_du_atomic_check, +- .atomic_commit = rcar_du_atomic_commit, ++ .atomic_commit = drm_atomic_helper_commit, + }; + + static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, +@@ -561,6 +479,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu) + dev->mode_config.max_width = 4095; + dev->mode_config.max_height = 2047; + dev->mode_config.funcs = &rcar_du_mode_config_funcs; ++ dev->mode_config.helper_private = &rcar_du_mode_config_helper; + + rcdu->num_crtcs = rcdu->info->num_crtcs; + +-- +2.13.3 + diff --git a/patches.renesas/0252-drm-rcar-du-Make-sure-the-VSP-is-initialized-on-plat.patch b/patches.renesas/0252-drm-rcar-du-Make-sure-the-VSP-is-initialized-on-plat.patch new file mode 100644 index 00000000000000..f182d9e91e14c4 --- /dev/null +++ b/patches.renesas/0252-drm-rcar-du-Make-sure-the-VSP-is-initialized-on-plat.patch @@ -0,0 +1,39 @@ +From d62aa80e6b7324dd2458fc3d4023a311ba894898 Mon Sep 17 00:00:00 2001 +From: Jacopo Mondi <jacopo+renesas@jmondi.org> +Date: Fri, 3 Mar 2017 13:58:56 +0100 +Subject: [PATCH 252/286] drm: rcar-du: Make sure the VSP is initialized on + platforms that need it + +On Gen3 platforms planes are managed by the external VSP compositor on +behalf of DRM/KMS. If VSP compositor support is not enabled in the DU +driver, the VSP initialization stub routine is called. Return an error +from that stub to fail explicitly, otherwise the device won't be usable +and the driver will crash. + +Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> +Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +[Clarified commit message] +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +(cherry picked from commit 3115345577d8e8c912562a1dd555787f11fcaf06) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_vsp.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h +index 510dcc9c6816..f1d0f1824528 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.h +@@ -68,7 +68,7 @@ void rcar_du_vsp_disable(struct rcar_du_crtc *crtc); + void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc); + void rcar_du_vsp_atomic_flush(struct rcar_du_crtc *crtc); + #else +-static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp) { return 0; }; ++static inline int rcar_du_vsp_init(struct rcar_du_vsp *vsp) { return -ENXIO; }; + static inline void rcar_du_vsp_enable(struct rcar_du_crtc *crtc) { }; + static inline void rcar_du_vsp_disable(struct rcar_du_crtc *crtc) { }; + static inline void rcar_du_vsp_atomic_begin(struct rcar_du_crtc *crtc) { }; +-- +2.13.3 + diff --git a/patches.renesas/0253-drm-rcar-du-Remove-wait-field-from-rcar_du_device-st.patch b/patches.renesas/0253-drm-rcar-du-Remove-wait-field-from-rcar_du_device-st.patch new file mode 100644 index 00000000000000..6982c1f582fbf2 --- /dev/null +++ b/patches.renesas/0253-drm-rcar-du-Remove-wait-field-from-rcar_du_device-st.patch @@ -0,0 +1,49 @@ +From c76ef4565cc68f106335c39ea83ddd76172052f7 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sat, 4 Mar 2017 23:49:27 +0200 +Subject: [PATCH 253/286] drm: rcar-du: Remove wait field from rcar_du_device + structure + +The field is a left-over from the switch to the atomic commit helper. +It's unused, remove it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit eff7fd6ba5e5764318e4c2bb85a11b9d3159137d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 -- + drivers/gpu/drm/rcar-du/rcar_du_drv.h | 5 ----- + 2 files changed, 7 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +index e09e0e6194ba..12af716ea57c 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +@@ -348,8 +348,6 @@ static int rcar_du_probe(struct platform_device *pdev) + if (rcdu == NULL) + return -ENOMEM; + +- init_waitqueue_head(&rcdu->commit.wait); +- + rcdu->dev = &pdev->dev; + rcdu->info = of_device_get_match_data(rcdu->dev); + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +index c843c3134498..574b3c1c21df 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +@@ -98,11 +98,6 @@ struct rcar_du_device { + unsigned int vspd1_sink; + + struct rcar_du_lvdsenc *lvds[RCAR_DU_MAX_LVDS]; +- +- struct { +- wait_queue_head_t wait; +- u32 pending; +- } commit; + }; + + static inline bool rcar_du_has(struct rcar_du_device *rcdu, +-- +2.13.3 + diff --git a/patches.renesas/0254-drm-rcar-du-Document-the-vsps-property-in-the-DT-bin.patch b/patches.renesas/0254-drm-rcar-du-Document-the-vsps-property-in-the-DT-bin.patch new file mode 100644 index 00000000000000..fcba90d638ae42 --- /dev/null +++ b/patches.renesas/0254-drm-rcar-du-Document-the-vsps-property-in-the-DT-bin.patch @@ -0,0 +1,34 @@ +From 9ab1ce0cf42a0a195275c932ddab3c0d59c89957 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 27 Mar 2017 12:51:04 +0300 +Subject: [PATCH 254/286] drm: rcar-du: Document the vsps property in the DT + bindings + +The property is used by the driver but is missing from the DT bindings. +Document it. + +Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 06711e6385a4ab4c8f4225f6cb9382eed58625a7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + Documentation/devicetree/bindings/display/renesas,du.txt | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt b/Documentation/devicetree/bindings/display/renesas,du.txt +index 1a02f099a0ff..c6cb96a4fa93 100644 +--- a/Documentation/devicetree/bindings/display/renesas,du.txt ++++ b/Documentation/devicetree/bindings/display/renesas,du.txt +@@ -36,6 +36,9 @@ Required Properties: + When supplied they must be named "dclkin.x" with "x" being the input + clock numerical index. + ++ - vsps: A list of phandles to the VSP nodes that handle the memory ++ interfaces for the DU channels. ++ + Required nodes: + + The connections to the DU output video ports are modeled using the OF graph +-- +2.13.3 + diff --git a/patches.renesas/0255-drm-panel-Constify-device-node-argument-to-of_drm_fi.patch b/patches.renesas/0255-drm-panel-Constify-device-node-argument-to-of_drm_fi.patch new file mode 100644 index 00000000000000..e381050645d822 --- /dev/null +++ b/patches.renesas/0255-drm-panel-Constify-device-node-argument-to-of_drm_fi.patch @@ -0,0 +1,49 @@ +From 0c56f4ba6b6cfb645ee9ca44bc3b172aa1c307bb Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Sat, 19 Nov 2016 05:28:05 +0200 +Subject: [PATCH 255/286] drm/panel: Constify device node argument to + of_drm_find_panel() + +The argument is never modified by the function, make it const. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Thierry Reding <treding@nvidia.com> +(cherry picked from commit 327bc443416d5aeb37e27704b2d91d2f86b8c621) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/drm_panel.c | 2 +- + include/drm/drm_panel.h | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c +index 3dfe3c886502..308d442a531b 100644 +--- a/drivers/gpu/drm/drm_panel.c ++++ b/drivers/gpu/drm/drm_panel.c +@@ -137,7 +137,7 @@ EXPORT_SYMBOL(drm_panel_detach); + * Return: A pointer to the panel registered for the specified device tree + * node or NULL if no panel matching the device tree node can be found. + */ +-struct drm_panel *of_drm_find_panel(struct device_node *np) ++struct drm_panel *of_drm_find_panel(const struct device_node *np) + { + struct drm_panel *panel; + +diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h +index 220d1e2b3db1..4b76cf2d5a7b 100644 +--- a/include/drm/drm_panel.h ++++ b/include/drm/drm_panel.h +@@ -193,9 +193,9 @@ int drm_panel_attach(struct drm_panel *panel, struct drm_connector *connector); + int drm_panel_detach(struct drm_panel *panel); + + #ifdef CONFIG_OF +-struct drm_panel *of_drm_find_panel(struct device_node *np); ++struct drm_panel *of_drm_find_panel(const struct device_node *np); + #else +-static inline struct drm_panel *of_drm_find_panel(struct device_node *np) ++static inline struct drm_panel *of_drm_find_panel(const struct device_node *np) + { + return NULL; + } +-- +2.13.3 + diff --git a/patches.renesas/0256-drm-rcar-du-Use-the-DRM-panel-API.patch b/patches.renesas/0256-drm-rcar-du-Use-the-DRM-panel-API.patch new file mode 100644 index 00000000000000..3ac9fe9d1652d6 --- /dev/null +++ b/patches.renesas/0256-drm-rcar-du-Use-the-DRM-panel-API.patch @@ -0,0 +1,234 @@ +From 574fd5f0558417ba105093380203d1777399bcb3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 18 Nov 2016 03:22:37 +0200 +Subject: [PATCH 256/286] drm: rcar-du: Use the DRM panel API + +Instead of parsing the panel device tree node manually, use the panel +API to delegate panel handling to a panel driver. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit bf7149f34241dcd6c95ea76b2b5ab4ff33f1c9b9) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/Kconfig | 1 + + drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 22 ++++++++++ + drivers/gpu/drm/rcar-du/rcar_du_encoder.h | 3 ++ + drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c | 68 +++++++++++-------------------- + 4 files changed, 50 insertions(+), 44 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig +index 4c2fd056dd6d..2bab449add76 100644 +--- a/drivers/gpu/drm/rcar-du/Kconfig ++++ b/drivers/gpu/drm/rcar-du/Kconfig +@@ -20,6 +20,7 @@ config DRM_RCAR_HDMI + config DRM_RCAR_LVDS + bool "R-Car DU LVDS Encoder Support" + depends on DRM_RCAR_DU ++ select DRM_PANEL + help + Enable support for the R-Car Display Unit embedded LVDS encoders. + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +index 3974d9495f37..31f878ad099d 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +@@ -16,6 +16,7 @@ + #include <drm/drmP.h> + #include <drm/drm_crtc.h> + #include <drm/drm_crtc_helper.h> ++#include <drm/drm_panel.h> + + #include "rcar_du_drv.h" + #include "rcar_du_encoder.h" +@@ -33,6 +34,11 @@ static void rcar_du_encoder_disable(struct drm_encoder *encoder) + { + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); + ++ if (renc->connector && renc->connector->panel) { ++ drm_panel_disable(renc->connector->panel); ++ drm_panel_unprepare(renc->connector->panel); ++ } ++ + if (renc->lvds) + rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, false); + } +@@ -43,6 +49,11 @@ static void rcar_du_encoder_enable(struct drm_encoder *encoder) + + if (renc->lvds) + rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, true); ++ ++ if (renc->connector && renc->connector->panel) { ++ drm_panel_prepare(renc->connector->panel); ++ drm_panel_enable(renc->connector->panel); ++ } + } + + static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder, +@@ -89,6 +100,17 @@ static void rcar_du_encoder_mode_set(struct drm_encoder *encoder, + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); + + rcar_du_crtc_route_output(crtc_state->crtc, renc->output); ++ ++ if (!renc->lvds) { ++ /* ++ * The DU driver creates connectors only for the outputs of the ++ * internal LVDS encoders. ++ */ ++ renc->connector = NULL; ++ return; ++ } ++ ++ renc->connector = to_rcar_connector(conn_state->connector); + } + + static const struct drm_encoder_helper_funcs encoder_helper_funcs = { +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +index 7fc10a9c34c3..269fbab15907 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +@@ -16,6 +16,7 @@ + + #include <drm/drm_crtc.h> + ++struct drm_panel; + struct rcar_du_device; + struct rcar_du_hdmienc; + struct rcar_du_lvdsenc; +@@ -31,6 +32,7 @@ enum rcar_du_encoder_type { + struct rcar_du_encoder { + struct drm_encoder base; + enum rcar_du_output output; ++ struct rcar_du_connector *connector; + struct rcar_du_hdmienc *hdmi; + struct rcar_du_lvdsenc *lvds; + }; +@@ -43,6 +45,7 @@ struct rcar_du_encoder { + struct rcar_du_connector { + struct drm_connector connector; + struct rcar_du_encoder *encoder; ++ struct drm_panel *panel; + }; + + #define to_rcar_connector(c) \ +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c +index 3bcfd161c53f..ee91481131ad 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c +@@ -15,6 +15,7 @@ + #include <drm/drm_atomic_helper.h> + #include <drm/drm_crtc.h> + #include <drm/drm_crtc_helper.h> ++#include <drm/drm_panel.h> + + #include <video/display_timing.h> + #include <video/of_display_timing.h> +@@ -25,47 +26,30 @@ + #include "rcar_du_kms.h" + #include "rcar_du_lvdscon.h" + +-struct rcar_du_lvds_connector { +- struct rcar_du_connector connector; +- +- struct { +- unsigned int width_mm; /* Panel width in mm */ +- unsigned int height_mm; /* Panel height in mm */ +- struct videomode mode; +- } panel; +-}; +- +-#define to_rcar_lvds_connector(c) \ +- container_of(c, struct rcar_du_lvds_connector, connector.connector) +- + static int rcar_du_lvds_connector_get_modes(struct drm_connector *connector) + { +- struct rcar_du_lvds_connector *lvdscon = +- to_rcar_lvds_connector(connector); +- struct drm_display_mode *mode; +- +- mode = drm_mode_create(connector->dev); +- if (mode == NULL) +- return 0; ++ struct rcar_du_connector *rcon = to_rcar_connector(connector); + +- mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; +- +- drm_display_mode_from_videomode(&lvdscon->panel.mode, mode); +- +- drm_mode_probed_add(connector, mode); +- +- return 1; ++ return drm_panel_get_modes(rcon->panel); + } + + static const struct drm_connector_helper_funcs connector_helper_funcs = { + .get_modes = rcar_du_lvds_connector_get_modes, + }; + ++static void rcar_du_lvds_connector_destroy(struct drm_connector *connector) ++{ ++ struct rcar_du_connector *rcon = to_rcar_connector(connector); ++ ++ drm_panel_detach(rcon->panel); ++ drm_connector_cleanup(connector); ++} ++ + static const struct drm_connector_funcs connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .reset = drm_atomic_helper_connector_reset, + .fill_modes = drm_helper_probe_single_connector_modes, +- .destroy = drm_connector_cleanup, ++ .destroy = rcar_du_lvds_connector_destroy, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + }; +@@ -75,27 +59,19 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu, + const struct device_node *np) + { + struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc); +- struct rcar_du_lvds_connector *lvdscon; ++ struct rcar_du_connector *rcon; + struct drm_connector *connector; +- struct display_timing timing; + int ret; + +- lvdscon = devm_kzalloc(rcdu->dev, sizeof(*lvdscon), GFP_KERNEL); +- if (lvdscon == NULL) ++ rcon = devm_kzalloc(rcdu->dev, sizeof(*rcon), GFP_KERNEL); ++ if (rcon == NULL) + return -ENOMEM; + +- ret = of_get_display_timing(np, "panel-timing", &timing); +- if (ret < 0) +- return ret; +- +- videomode_from_timing(&timing, &lvdscon->panel.mode); ++ connector = &rcon->connector; + +- of_property_read_u32(np, "width-mm", &lvdscon->panel.width_mm); +- of_property_read_u32(np, "height-mm", &lvdscon->panel.height_mm); +- +- connector = &lvdscon->connector.connector; +- connector->display_info.width_mm = lvdscon->panel.width_mm; +- connector->display_info.height_mm = lvdscon->panel.height_mm; ++ rcon->panel = of_drm_find_panel(np); ++ if (!rcon->panel) ++ return -EPROBE_DEFER; + + ret = drm_connector_init(rcdu->ddev, connector, &connector_funcs, + DRM_MODE_CONNECTOR_LVDS); +@@ -112,7 +88,11 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu, + if (ret < 0) + return ret; + +- lvdscon->connector.encoder = renc; ++ ret = drm_panel_attach(rcon->panel, connector); ++ if (ret < 0) ++ return ret; ++ ++ rcon->encoder = renc; + + return 0; + } +-- +2.13.3 + diff --git a/patches.renesas/0257-drm-Add-data-transmission-order-bus-flag.patch b/patches.renesas/0257-drm-Add-data-transmission-order-bus-flag.patch new file mode 100644 index 00000000000000..e80d83282ce9a9 --- /dev/null +++ b/patches.renesas/0257-drm-Add-data-transmission-order-bus-flag.patch @@ -0,0 +1,39 @@ +From 4418c9f47b583d0511cce3a844268a9bcce80fe2 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 18 Nov 2016 16:55:48 +0200 +Subject: [PATCH 257/286] drm: Add data transmission order bus flag + +The flags indicate whether data is transmitted LSB to MSB or MSB to LSB +on the bus. + +The exact meaning is bus-type dependent. For instance, for LVDS buses +the flags indicate whether the seven data bits transmitted in a clock +pulse are sent in normal order (MSB to LSB, slots 0 to 6) or reverse +order (LSB to MSB, slots 6 to 0). + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Reviewed-by: Thierry Reding <treding@nvidia.com> +(cherry picked from commit 5ec1a96010aa7aff19adba92a8163ef8f8c5c1ad) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + include/drm/drm_connector.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h +index 7cb10d15cfa5..2ebb54a60412 100644 +--- a/include/drm/drm_connector.h ++++ b/include/drm/drm_connector.h +@@ -159,6 +159,10 @@ struct drm_display_info { + #define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2) + /* drive data on neg. edge */ + #define DRM_BUS_FLAG_PIXDATA_NEGEDGE (1<<3) ++/* data is transmitted MSB to LSB on the bus */ ++#define DRM_BUS_FLAG_DATA_MSB_TO_LSB (1<<4) ++/* data is transmitted LSB to MSB on the bus */ ++#define DRM_BUS_FLAG_DATA_LSB_TO_MSB (1<<5) + + /** + * @bus_flags: Additional information (like pixel signal polarity) for +-- +2.13.3 + diff --git a/patches.renesas/0258-drm-rcar-du-Add-support-for-LVDS-mode-selection.patch b/patches.renesas/0258-drm-rcar-du-Add-support-for-LVDS-mode-selection.patch new file mode 100644 index 00000000000000..4adb913d5d1e41 --- /dev/null +++ b/patches.renesas/0258-drm-rcar-du-Add-support-for-LVDS-mode-selection.patch @@ -0,0 +1,143 @@ +From d6b1448ad501ad50c1d7762761a2d7c193422a51 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Mon, 3 Oct 2016 13:07:02 +0300 +Subject: [PATCH 258/286] drm: rcar-du: Add support for LVDS mode selection + +Retrieve the LVDS mode from the panel and configure the LVDS encoder +accordingly. LVDS mode selection is static as LVDS panels can't be +hot-plugged on any of the device supported by the driver. Support for +dynamic mode selection can be implemented in the future when needed. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit e947eccbeba45268bf3b5f4e30185d9bb87a293d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 27 +++++++++++++++++++++++++++ + drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 11 +++++++++-- + drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h | 13 +++++++++++++ + 3 files changed, 49 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +index 31f878ad099d..3a3c9374794e 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +@@ -98,6 +98,8 @@ static void rcar_du_encoder_mode_set(struct drm_encoder *encoder, + struct drm_connector_state *conn_state) + { + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); ++ struct drm_display_info *info = &conn_state->connector->display_info; ++ enum rcar_lvds_mode mode; + + rcar_du_crtc_route_output(crtc_state->crtc, renc->output); + +@@ -111,6 +113,31 @@ static void rcar_du_encoder_mode_set(struct drm_encoder *encoder, + } + + renc->connector = to_rcar_connector(conn_state->connector); ++ ++ if (!info->num_bus_formats || !info->bus_formats) { ++ dev_err(encoder->dev->dev, "no LVDS bus format reported\n"); ++ return; ++ } ++ ++ switch (info->bus_formats[0]) { ++ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: ++ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: ++ mode = RCAR_LVDS_MODE_JEIDA; ++ break; ++ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: ++ mode = RCAR_LVDS_MODE_VESA; ++ break; ++ default: ++ dev_err(encoder->dev->dev, ++ "unsupported LVDS bus format 0x%04x\n", ++ info->bus_formats[0]); ++ return; ++ } ++ ++ if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB) ++ mode |= RCAR_LVDS_MODE_MIRROR; ++ ++ rcar_du_lvdsenc_set_mode(renc->lvds, mode); + } + + static const struct drm_encoder_helper_funcs encoder_helper_funcs = { +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +index e3a4985f6f3f..1661f6201210 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +@@ -31,6 +31,7 @@ struct rcar_du_lvdsenc { + bool enabled; + + enum rcar_lvds_input input; ++ enum rcar_lvds_mode mode; + }; + + static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data) +@@ -61,7 +62,7 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds, + /* Select the input, hardcode mode 0, enable LVDS operation and turn + * bias circuitry on. + */ +- lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN; ++ lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN; + if (rcrtc->index == 2) + lvdcr0 |= LVDCR0_DUSEL; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); +@@ -114,7 +115,7 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, + * Turn the PLL on, set it to LVDS normal mode, wait for the startup + * delay and turn the output on. + */ +- lvdcr0 = LVDCR0_PLLON; ++ lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + + lvdcr0 |= LVDCR0_PWD; +@@ -211,6 +212,12 @@ void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds, + mode->clock = clamp(mode->clock, 25175, 148500); + } + ++void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds, ++ enum rcar_lvds_mode mode) ++{ ++ lvds->mode = mode; ++} ++ + static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds, + struct platform_device *pdev) + { +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h +index dfdba746edf4..7218ac89333e 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h +@@ -26,8 +26,17 @@ enum rcar_lvds_input { + RCAR_LVDS_INPUT_DU2, + }; + ++/* Keep in sync with the LVDCR0.LVMD hardware register values. */ ++enum rcar_lvds_mode { ++ RCAR_LVDS_MODE_JEIDA = 0, ++ RCAR_LVDS_MODE_MIRROR = 1, ++ RCAR_LVDS_MODE_VESA = 4, ++}; ++ + #if IS_ENABLED(CONFIG_DRM_RCAR_LVDS) + int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu); ++void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds, ++ enum rcar_lvds_mode mode); + int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, + struct drm_crtc *crtc, bool enable); + void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds, +@@ -37,6 +46,10 @@ static inline int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu) + { + return 0; + } ++static inline void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds, ++ enum rcar_lvds_mode mode) ++{ ++} + static inline int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, + struct drm_crtc *crtc, bool enable) + { +-- +2.13.3 + diff --git a/patches.renesas/0259-drm-rcar-du-Replace-manual-bridge-implementation-wit.patch b/patches.renesas/0259-drm-rcar-du-Replace-manual-bridge-implementation-wit.patch new file mode 100644 index 00000000000000..3aa9982ca38d7a --- /dev/null +++ b/patches.renesas/0259-drm-rcar-du-Replace-manual-bridge-implementation-wit.patch @@ -0,0 +1,536 @@ +From 5d62be51d3bb98b76f711928ab7b309ee00776be Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 7 Oct 2016 16:01:41 +0300 +Subject: [PATCH 259/286] drm: rcar-du: Replace manual bridge implementation + with DRM bridge + +The rcar-du driver contains a manual implementation of HDMI and VGA +bridges. Use DRM bridges to replace it. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 5c602531feb3db3926cdd76dda89314f0634c9e7) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/Kconfig | 6 -- + drivers/gpu/drm/rcar-du/Makefile | 5 +- + drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 104 +++++++++++++---------- + drivers/gpu/drm/rcar-du/rcar_du_encoder.h | 2 - + drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c | 134 ------------------------------ + drivers/gpu/drm/rcar-du/rcar_du_hdmienc.h | 35 -------- + drivers/gpu/drm/rcar-du/rcar_du_vgacon.c | 82 ------------------ + drivers/gpu/drm/rcar-du/rcar_du_vgacon.h | 23 ----- + 8 files changed, 60 insertions(+), 331 deletions(-) + delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c + delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_hdmienc.h + delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vgacon.c + delete mode 100644 drivers/gpu/drm/rcar-du/rcar_du_vgacon.h + +diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig +index 2bab449add76..06121eeba9e5 100644 +--- a/drivers/gpu/drm/rcar-du/Kconfig ++++ b/drivers/gpu/drm/rcar-du/Kconfig +@@ -11,12 +11,6 @@ config DRM_RCAR_DU + Choose this option if you have an R-Car chipset. + If M is selected the module will be called rcar-du-drm. + +-config DRM_RCAR_HDMI +- bool "R-Car DU HDMI Encoder Support" +- depends on DRM_RCAR_DU +- help +- Enable support for external HDMI encoders. +- + config DRM_RCAR_LVDS + bool "R-Car DU LVDS Encoder Support" + depends on DRM_RCAR_DU +diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile +index d3b44651061a..a492e6858691 100644 +--- a/drivers/gpu/drm/rcar-du/Makefile ++++ b/drivers/gpu/drm/rcar-du/Makefile +@@ -4,10 +4,7 @@ rcar-du-drm-y := rcar_du_crtc.o \ + rcar_du_group.o \ + rcar_du_kms.o \ + rcar_du_lvdscon.o \ +- rcar_du_plane.o \ +- rcar_du_vgacon.o +- +-rcar-du-drm-$(CONFIG_DRM_RCAR_HDMI) += rcar_du_hdmienc.o ++ rcar_du_plane.o + + rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +index 3a3c9374794e..92a0405c2fb2 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +@@ -20,11 +20,9 @@ + + #include "rcar_du_drv.h" + #include "rcar_du_encoder.h" +-#include "rcar_du_hdmienc.h" + #include "rcar_du_kms.h" + #include "rcar_du_lvdscon.h" + #include "rcar_du_lvdsenc.h" +-#include "rcar_du_vgacon.h" + + /* ----------------------------------------------------------------------------- + * Encoder +@@ -63,29 +61,35 @@ static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder, + struct rcar_du_encoder *renc = to_rcar_encoder(encoder); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + const struct drm_display_mode *mode = &crtc_state->mode; +- const struct drm_display_mode *panel_mode; + struct drm_connector *connector = conn_state->connector; + struct drm_device *dev = encoder->dev; + +- /* DAC encoders have currently no restriction on the mode. */ +- if (encoder->encoder_type == DRM_MODE_ENCODER_DAC) +- return 0; ++ /* ++ * Only panel-related encoder types require validation here, everything ++ * else is handled by the bridge drivers. ++ */ ++ if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { ++ const struct drm_display_mode *panel_mode; + +- if (list_empty(&connector->modes)) { +- dev_dbg(dev->dev, "encoder: empty modes list\n"); +- return -EINVAL; +- } ++ if (list_empty(&connector->modes)) { ++ dev_dbg(dev->dev, "encoder: empty modes list\n"); ++ return -EINVAL; ++ } + +- panel_mode = list_first_entry(&connector->modes, +- struct drm_display_mode, head); ++ panel_mode = list_first_entry(&connector->modes, ++ struct drm_display_mode, head); + +- /* We're not allowed to modify the resolution. */ +- if (mode->hdisplay != panel_mode->hdisplay || +- mode->vdisplay != panel_mode->vdisplay) +- return -EINVAL; ++ /* We're not allowed to modify the resolution. */ ++ if (mode->hdisplay != panel_mode->hdisplay || ++ mode->vdisplay != panel_mode->vdisplay) ++ return -EINVAL; + +- /* The flat panel mode is fixed, just copy it to the adjusted mode. */ +- drm_mode_copy(adjusted_mode, panel_mode); ++ /* ++ * The flat panel mode is fixed, just copy it to the adjusted ++ * mode. ++ */ ++ drm_mode_copy(adjusted_mode, panel_mode); ++ } + + if (renc->lvds) + rcar_du_lvdsenc_atomic_check(renc->lvds, adjusted_mode); +@@ -159,6 +163,7 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, + { + struct rcar_du_encoder *renc; + struct drm_encoder *encoder; ++ struct drm_bridge *bridge = NULL; + unsigned int encoder_type; + int ret; + +@@ -182,6 +187,15 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, + break; + } + ++ if (enc_node) { ++ /* Locate the DRM bridge from the encoder DT node. */ ++ bridge = of_drm_find_bridge(enc_node); ++ if (!bridge) { ++ ret = -EPROBE_DEFER; ++ goto done; ++ } ++ } ++ + switch (type) { + case RCAR_DU_ENCODER_VGA: + encoder_type = DRM_MODE_ENCODER_DAC; +@@ -199,35 +213,35 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, + break; + } + +- if (type == RCAR_DU_ENCODER_HDMI) { +- ret = rcar_du_hdmienc_init(rcdu, renc, enc_node); +- if (ret < 0) +- goto done; +- } else { +- ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs, +- encoder_type, NULL); +- if (ret < 0) +- goto done; +- +- drm_encoder_helper_add(encoder, &encoder_helper_funcs); +- } +- +- switch (encoder_type) { +- case DRM_MODE_ENCODER_LVDS: +- ret = rcar_du_lvds_connector_init(rcdu, renc, con_node); +- break; +- +- case DRM_MODE_ENCODER_DAC: +- ret = rcar_du_vga_connector_init(rcdu, renc); +- break; ++ ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs, ++ encoder_type, NULL); ++ if (ret < 0) ++ goto done; + +- case DRM_MODE_ENCODER_TMDS: +- /* connector managed by the bridge driver */ +- break; ++ drm_encoder_helper_add(encoder, &encoder_helper_funcs); + +- default: +- ret = -EINVAL; +- break; ++ if (bridge) { ++ /* ++ * Attach the bridge to the encoder. The bridge will create the ++ * connector. ++ */ ++ ret = drm_bridge_attach(encoder, bridge, NULL); ++ if (ret) { ++ drm_encoder_cleanup(encoder); ++ return ret; ++ } ++ } else { ++ /* There's no bridge, create the connector manually. */ ++ switch (output) { ++ case RCAR_DU_OUTPUT_LVDS0: ++ case RCAR_DU_OUTPUT_LVDS1: ++ ret = rcar_du_lvds_connector_init(rcdu, renc, con_node); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ break; ++ } + } + + done: +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +index 269fbab15907..3a6e38fe56cd 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +@@ -18,7 +18,6 @@ + + struct drm_panel; + struct rcar_du_device; +-struct rcar_du_hdmienc; + struct rcar_du_lvdsenc; + + enum rcar_du_encoder_type { +@@ -33,7 +32,6 @@ struct rcar_du_encoder { + struct drm_encoder base; + enum rcar_du_output output; + struct rcar_du_connector *connector; +- struct rcar_du_hdmienc *hdmi; + struct rcar_du_lvdsenc *lvds; + }; + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c +deleted file mode 100644 +index 933a2547798e..000000000000 +--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c ++++ /dev/null +@@ -1,134 +0,0 @@ +-/* +- * R-Car Display Unit HDMI Encoder +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * +- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#include <linux/slab.h> +- +-#include <drm/drmP.h> +-#include <drm/drm_crtc.h> +-#include <drm/drm_crtc_helper.h> +- +-#include "rcar_du_drv.h" +-#include "rcar_du_encoder.h" +-#include "rcar_du_hdmienc.h" +-#include "rcar_du_lvdsenc.h" +- +-struct rcar_du_hdmienc { +- struct rcar_du_encoder *renc; +- bool enabled; +-}; +- +-#define to_rcar_hdmienc(e) (to_rcar_encoder(e)->hdmi) +- +-static void rcar_du_hdmienc_disable(struct drm_encoder *encoder) +-{ +- struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); +- +- if (hdmienc->renc->lvds) +- rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, +- false); +- +- hdmienc->enabled = false; +-} +- +-static void rcar_du_hdmienc_enable(struct drm_encoder *encoder) +-{ +- struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); +- +- if (hdmienc->renc->lvds) +- rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, +- true); +- +- hdmienc->enabled = true; +-} +- +-static int rcar_du_hdmienc_atomic_check(struct drm_encoder *encoder, +- struct drm_crtc_state *crtc_state, +- struct drm_connector_state *conn_state) +-{ +- struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); +- struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; +- +- if (hdmienc->renc->lvds) +- rcar_du_lvdsenc_atomic_check(hdmienc->renc->lvds, +- adjusted_mode); +- +- return 0; +-} +- +- +-static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder, +- struct drm_crtc_state *crtc_state, +- struct drm_connector_state *conn_state) +-{ +- struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); +- +- rcar_du_crtc_route_output(crtc_state->crtc, hdmienc->renc->output); +-} +- +-static const struct drm_encoder_helper_funcs encoder_helper_funcs = { +- .atomic_mode_set = rcar_du_hdmienc_mode_set, +- .disable = rcar_du_hdmienc_disable, +- .enable = rcar_du_hdmienc_enable, +- .atomic_check = rcar_du_hdmienc_atomic_check, +-}; +- +-static void rcar_du_hdmienc_cleanup(struct drm_encoder *encoder) +-{ +- struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder); +- +- if (hdmienc->enabled) +- rcar_du_hdmienc_disable(encoder); +- +- drm_encoder_cleanup(encoder); +-} +- +-static const struct drm_encoder_funcs encoder_funcs = { +- .destroy = rcar_du_hdmienc_cleanup, +-}; +- +-int rcar_du_hdmienc_init(struct rcar_du_device *rcdu, +- struct rcar_du_encoder *renc, struct device_node *np) +-{ +- struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc); +- struct drm_bridge *bridge; +- struct rcar_du_hdmienc *hdmienc; +- int ret; +- +- hdmienc = devm_kzalloc(rcdu->dev, sizeof(*hdmienc), GFP_KERNEL); +- if (hdmienc == NULL) +- return -ENOMEM; +- +- /* Locate the DRM bridge from the HDMI encoder DT node. */ +- bridge = of_drm_find_bridge(np); +- if (!bridge) +- return -EPROBE_DEFER; +- +- ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs, +- DRM_MODE_ENCODER_TMDS, NULL); +- if (ret < 0) +- return ret; +- +- drm_encoder_helper_add(encoder, &encoder_helper_funcs); +- +- renc->hdmi = hdmienc; +- hdmienc->renc = renc; +- +- /* Link the bridge to the encoder. */ +- ret = drm_bridge_attach(encoder, bridge, NULL); +- if (ret) { +- drm_encoder_cleanup(encoder); +- return ret; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.h b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.h +deleted file mode 100644 +index 2ff0128ac8e1..000000000000 +--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* +- * R-Car Display Unit HDMI Encoder +- * +- * Copyright (C) 2014 Renesas Electronics Corporation +- * +- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#ifndef __RCAR_DU_HDMIENC_H__ +-#define __RCAR_DU_HDMIENC_H__ +- +-#include <linux/module.h> +- +-struct device_node; +-struct rcar_du_device; +-struct rcar_du_encoder; +- +-#if IS_ENABLED(CONFIG_DRM_RCAR_HDMI) +-int rcar_du_hdmienc_init(struct rcar_du_device *rcdu, +- struct rcar_du_encoder *renc, struct device_node *np); +-#else +-static inline int rcar_du_hdmienc_init(struct rcar_du_device *rcdu, +- struct rcar_du_encoder *renc, +- struct device_node *np) +-{ +- return -ENOSYS; +-} +-#endif +- +-#endif /* __RCAR_DU_HDMIENC_H__ */ +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c +deleted file mode 100644 +index 8d6125c1c0f9..000000000000 +--- a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * rcar_du_vgacon.c -- R-Car Display Unit VGA Connector +- * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation +- * +- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#include <drm/drmP.h> +-#include <drm/drm_atomic_helper.h> +-#include <drm/drm_crtc.h> +-#include <drm/drm_crtc_helper.h> +- +-#include "rcar_du_drv.h" +-#include "rcar_du_encoder.h" +-#include "rcar_du_kms.h" +-#include "rcar_du_vgacon.h" +- +-static int rcar_du_vga_connector_get_modes(struct drm_connector *connector) +-{ +- return 0; +-} +- +-static const struct drm_connector_helper_funcs connector_helper_funcs = { +- .get_modes = rcar_du_vga_connector_get_modes, +-}; +- +-static enum drm_connector_status +-rcar_du_vga_connector_detect(struct drm_connector *connector, bool force) +-{ +- return connector_status_connected; +-} +- +-static const struct drm_connector_funcs connector_funcs = { +- .dpms = drm_atomic_helper_connector_dpms, +- .reset = drm_atomic_helper_connector_reset, +- .detect = rcar_du_vga_connector_detect, +- .fill_modes = drm_helper_probe_single_connector_modes, +- .destroy = drm_connector_cleanup, +- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, +- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +-}; +- +-int rcar_du_vga_connector_init(struct rcar_du_device *rcdu, +- struct rcar_du_encoder *renc) +-{ +- struct drm_encoder *encoder = rcar_encoder_to_drm_encoder(renc); +- struct rcar_du_connector *rcon; +- struct drm_connector *connector; +- int ret; +- +- rcon = devm_kzalloc(rcdu->dev, sizeof(*rcon), GFP_KERNEL); +- if (rcon == NULL) +- return -ENOMEM; +- +- connector = &rcon->connector; +- connector->display_info.width_mm = 0; +- connector->display_info.height_mm = 0; +- connector->interlace_allowed = true; +- +- ret = drm_connector_init(rcdu->ddev, connector, &connector_funcs, +- DRM_MODE_CONNECTOR_VGA); +- if (ret < 0) +- return ret; +- +- drm_connector_helper_add(connector, &connector_helper_funcs); +- +- connector->dpms = DRM_MODE_DPMS_OFF; +- drm_object_property_set_value(&connector->base, +- rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF); +- +- ret = drm_mode_connector_attach_encoder(connector, encoder); +- if (ret < 0) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.h b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.h +deleted file mode 100644 +index 112f50316e01..000000000000 +--- a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-/* +- * rcar_du_vgacon.h -- R-Car Display Unit VGA Connector +- * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation +- * +- * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- */ +- +-#ifndef __RCAR_DU_VGACON_H__ +-#define __RCAR_DU_VGACON_H__ +- +-struct rcar_du_device; +-struct rcar_du_encoder; +- +-int rcar_du_vga_connector_init(struct rcar_du_device *rcdu, +- struct rcar_du_encoder *renc); +- +-#endif /* __RCAR_DU_VGACON_H__ */ +-- +2.13.3 + diff --git a/patches.renesas/0260-drm-rcar-du-Hardcode-encoders-types-to-DRM_MODE_ENCO.patch b/patches.renesas/0260-drm-rcar-du-Hardcode-encoders-types-to-DRM_MODE_ENCO.patch new file mode 100644 index 00000000000000..ffa7757d182d8a --- /dev/null +++ b/patches.renesas/0260-drm-rcar-du-Hardcode-encoders-types-to-DRM_MODE_ENCO.patch @@ -0,0 +1,306 @@ +From 39f2c083a3ceed24c8efcc277978dc66e3c71d08 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Fri, 7 Oct 2016 17:39:21 +0300 +Subject: [PATCH 260/286] drm: rcar-du: Hardcode encoders types to + DRM_MODE_ENCODER_NONE + +Unlike the connector type, the encoder type is unused by userspace. As +it is equally unused in the driver, except in a single location where +the connector type can be used instead, hardcode it to +DRM_MODE_ENCODER_NONE. This allow removing all code that tries to +determine (unsuccessfully in case a bridge is used) the encoder type. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 381ddfe478871588af95548aaecb6698009c3d6b) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 15 ------------- + drivers/gpu/drm/rcar-du/rcar_du_drv.h | 2 -- + drivers/gpu/drm/rcar-du/rcar_du_encoder.c | 30 ++++++++----------------- + drivers/gpu/drm/rcar-du/rcar_du_encoder.h | 9 -------- + drivers/gpu/drm/rcar-du/rcar_du_kms.c | 37 ++----------------------------- + 5 files changed, 11 insertions(+), 82 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +index 12af716ea57c..8ac5f5a64144 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +@@ -45,12 +45,10 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1) | BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 1, + }, + }, +@@ -69,17 +67,14 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(2) | BIT(1) | BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_LVDS, + .port = 1, + }, + [RCAR_DU_OUTPUT_LVDS1] = { + .possible_crtcs = BIT(2) | BIT(1), +- .encoder_type = DRM_MODE_ENCODER_LVDS, + .port = 2, + }, + }, +@@ -98,12 +93,10 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(1) | BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_LVDS, + .port = 1, + }, + }, +@@ -119,12 +112,10 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = { + /* R8A7792 has two RGB outputs. */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 1, + }, + }, +@@ -142,12 +133,10 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 1, + }, + }, +@@ -166,12 +155,10 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(3), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_LVDS, + .port = 3, + }, + }, +@@ -190,12 +177,10 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = { + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(2), +- .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), +- .encoder_type = DRM_MODE_ENCODER_LVDS, + .port = 2, + }, + }, +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +index 574b3c1c21df..90eb209c244e 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +@@ -38,7 +38,6 @@ struct rcar_du_lvdsenc; + /* + * struct rcar_du_output_routing - Output routing specification + * @possible_crtcs: bitmask of possible CRTCs for the output +- * @encoder_type: DRM type of the internal encoder associated with the output + * @port: device tree port number corresponding to this output route + * + * The DU has 5 possible outputs (DPAD0/1, LVDS0/1, TCON). Output routing data +@@ -47,7 +46,6 @@ struct rcar_du_lvdsenc; + */ + struct rcar_du_output_routing { + unsigned int possible_crtcs; +- unsigned int encoder_type; + unsigned int port; + }; + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +index 92a0405c2fb2..3e048dd98b64 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c +@@ -68,7 +68,7 @@ static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder, + * Only panel-related encoder types require validation here, everything + * else is handled by the bridge drivers. + */ +- if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { ++ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { + const struct drm_display_mode *panel_mode; + + if (list_empty(&connector->modes)) { +@@ -156,7 +156,6 @@ static const struct drm_encoder_funcs encoder_funcs = { + }; + + int rcar_du_encoder_init(struct rcar_du_device *rcdu, +- enum rcar_du_encoder_type type, + enum rcar_du_output output, + struct device_node *enc_node, + struct device_node *con_node) +@@ -164,7 +163,6 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, + struct rcar_du_encoder *renc; + struct drm_encoder *encoder; + struct drm_bridge *bridge = NULL; +- unsigned int encoder_type; + int ret; + + renc = devm_kzalloc(rcdu->dev, sizeof(*renc), GFP_KERNEL); +@@ -188,33 +186,23 @@ int rcar_du_encoder_init(struct rcar_du_device *rcdu, + } + + if (enc_node) { ++ dev_dbg(rcdu->dev, "initializing encoder %s for output %u\n", ++ of_node_full_name(enc_node), output); ++ + /* Locate the DRM bridge from the encoder DT node. */ + bridge = of_drm_find_bridge(enc_node); + if (!bridge) { + ret = -EPROBE_DEFER; + goto done; + } +- } +- +- switch (type) { +- case RCAR_DU_ENCODER_VGA: +- encoder_type = DRM_MODE_ENCODER_DAC; +- break; +- case RCAR_DU_ENCODER_LVDS: +- encoder_type = DRM_MODE_ENCODER_LVDS; +- break; +- case RCAR_DU_ENCODER_HDMI: +- encoder_type = DRM_MODE_ENCODER_TMDS; +- break; +- case RCAR_DU_ENCODER_NONE: +- default: +- /* No external encoder, use the internal encoder type. */ +- encoder_type = rcdu->info->routes[output].encoder_type; +- break; ++ } else { ++ dev_dbg(rcdu->dev, ++ "initializing internal encoder for output %u\n", ++ output); + } + + ret = drm_encoder_init(rcdu->ddev, encoder, &encoder_funcs, +- encoder_type, NULL); ++ DRM_MODE_ENCODER_NONE, NULL); + if (ret < 0) + goto done; + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +index 3a6e38fe56cd..b4633b64fb79 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.h +@@ -20,14 +20,6 @@ struct drm_panel; + struct rcar_du_device; + struct rcar_du_lvdsenc; + +-enum rcar_du_encoder_type { +- RCAR_DU_ENCODER_UNUSED = 0, +- RCAR_DU_ENCODER_NONE, +- RCAR_DU_ENCODER_VGA, +- RCAR_DU_ENCODER_LVDS, +- RCAR_DU_ENCODER_HDMI, +-}; +- + struct rcar_du_encoder { + struct drm_encoder base; + enum rcar_du_output output; +@@ -50,7 +42,6 @@ struct rcar_du_connector { + container_of(c, struct rcar_du_connector, connector) + + int rcar_du_encoder_init(struct rcar_du_device *rcdu, +- enum rcar_du_encoder_type type, + enum rcar_du_output output, + struct device_node *enc_node, + struct device_node *con_node); +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +index e775ae5e5f06..d845e82f4653 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +@@ -284,16 +284,6 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, + enum rcar_du_output output, + struct of_endpoint *ep) + { +- static const struct { +- const char *compatible; +- enum rcar_du_encoder_type type; +- } encoders[] = { +- { "adi,adv7123", RCAR_DU_ENCODER_VGA }, +- { "adi,adv7511w", RCAR_DU_ENCODER_HDMI }, +- { "thine,thc63lvdm83d", RCAR_DU_ENCODER_LVDS }, +- }; +- +- enum rcar_du_encoder_type enc_type = RCAR_DU_ENCODER_NONE; + struct device_node *connector = NULL; + struct device_node *encoder = NULL; + struct device_node *ep_node = NULL; +@@ -340,30 +330,7 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, + + of_node_put(entity_ep_node); + +- if (encoder) { +- /* +- * If an encoder has been found, get its type based on its +- * compatible string. +- */ +- unsigned int i; +- +- for (i = 0; i < ARRAY_SIZE(encoders); ++i) { +- if (of_device_is_compatible(encoder, +- encoders[i].compatible)) { +- enc_type = encoders[i].type; +- break; +- } +- } +- +- if (i == ARRAY_SIZE(encoders)) { +- dev_warn(rcdu->dev, +- "unknown encoder type for %s, skipping\n", +- encoder->full_name); +- of_node_put(encoder); +- of_node_put(connector); +- return -EINVAL; +- } +- } else { ++ if (!encoder) { + /* + * If no encoder has been found the entity must be the + * connector. +@@ -371,7 +338,7 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, + connector = entity; + } + +- ret = rcar_du_encoder_init(rcdu, enc_type, output, encoder, connector); ++ ret = rcar_du_encoder_init(rcdu, output, encoder, connector); + if (ret && ret != -EPROBE_DEFER) + dev_warn(rcdu->dev, + "failed to initialize encoder %s on output %u (%d), skipping\n", +-- +2.13.3 + diff --git a/patches.renesas/0261-drm-rcar-du-Add-Gen3-HDMI-encoder-support.patch b/patches.renesas/0261-drm-rcar-du-Add-Gen3-HDMI-encoder-support.patch new file mode 100644 index 00000000000000..685d664e9cedcd --- /dev/null +++ b/patches.renesas/0261-drm-rcar-du-Add-Gen3-HDMI-encoder-support.patch @@ -0,0 +1,161 @@ +From ad4201553433ad224811fef40b7a0e966f4551bd Mon Sep 17 00:00:00 2001 +From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Date: Fri, 11 Nov 2016 18:07:40 +0100 +Subject: [PATCH 261/286] drm: rcar-du: Add Gen3 HDMI encoder support + +The R-Car Gen3 SoCs include on-chip DesignWare HDMI encoders. Support +them with a platform driver to provide platform glue data to the dw-hdmi +driver. + +The driver is a complete rewrite of code coming from the Renesas BSP, +save for the values in the PHY parameters table. + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> +(cherry picked from commit 40d0fa7095d06c73c33da4fa7e381350141682f5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/Kconfig | 7 +++ + drivers/gpu/drm/rcar-du/Makefile | 1 + + drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 100 +++++++++++++++++++++++++++++++++ + 3 files changed, 108 insertions(+) + create mode 100644 drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c + +diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig +index 06121eeba9e5..8a50dab19e5c 100644 +--- a/drivers/gpu/drm/rcar-du/Kconfig ++++ b/drivers/gpu/drm/rcar-du/Kconfig +@@ -11,6 +11,13 @@ config DRM_RCAR_DU + Choose this option if you have an R-Car chipset. + If M is selected the module will be called rcar-du-drm. + ++config DRM_RCAR_DW_HDMI ++ tristate "R-Car DU Gen3 HDMI Encoder Support" ++ depends on DRM && OF ++ select DRM_DW_HDMI ++ help ++ Enable support for R-Car Gen3 internal HDMI encoder. ++ + config DRM_RCAR_LVDS + bool "R-Car DU LVDS Encoder Support" + depends on DRM_RCAR_DU +diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile +index a492e6858691..2131e722de3b 100644 +--- a/drivers/gpu/drm/rcar-du/Makefile ++++ b/drivers/gpu/drm/rcar-du/Makefile +@@ -11,3 +11,4 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_LVDS) += rcar_du_lvdsenc.o + rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o + + obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o ++obj-$(CONFIG_DRM_RCAR_DW_HDMI) += rcar_dw_hdmi.o +diff --git a/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c +new file mode 100644 +index 000000000000..7539626b8ebd +--- /dev/null ++++ b/drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c +@@ -0,0 +1,100 @@ ++/* ++ * R-Car Gen3 HDMI PHY ++ * ++ * Copyright (C) 2016 Renesas Electronics Corporation ++ * ++ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/platform_device.h> ++ ++#include <drm/bridge/dw_hdmi.h> ++ ++#define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ ++#define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ ++#define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ ++ ++struct rcar_hdmi_phy_params { ++ unsigned long mpixelclock; ++ u16 opmode_div; /* Mode of operation and PLL dividers */ ++ u16 curr_gmp; /* PLL current and Gmp (conductance) */ ++ u16 div; /* PLL dividers */ ++}; ++ ++static const struct rcar_hdmi_phy_params rcar_hdmi_phy_params[] = { ++ { 35500000, 0x0003, 0x0344, 0x0328 }, ++ { 44900000, 0x0003, 0x0285, 0x0128 }, ++ { 71000000, 0x0002, 0x1184, 0x0314 }, ++ { 90000000, 0x0002, 0x1144, 0x0114 }, ++ { 140250000, 0x0001, 0x20c4, 0x030a }, ++ { 182750000, 0x0001, 0x2084, 0x010a }, ++ { 281250000, 0x0000, 0x0084, 0x0305 }, ++ { 297000000, 0x0000, 0x0084, 0x0105 }, ++ { ~0UL, 0x0000, 0x0000, 0x0000 }, ++}; ++ ++static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, ++ const struct dw_hdmi_plat_data *pdata, ++ unsigned long mpixelclock) ++{ ++ const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; ++ ++ for (; params && params->mpixelclock != ~0UL; ++params) { ++ if (mpixelclock <= params->mpixelclock) ++ break; ++ } ++ ++ if (params->mpixelclock == ~0UL) ++ return -EINVAL; ++ ++ dw_hdmi_phy_i2c_write(hdmi, params->opmode_div, ++ RCAR_HDMI_PHY_OPMODE_PLLCFG); ++ dw_hdmi_phy_i2c_write(hdmi, params->curr_gmp, ++ RCAR_HDMI_PHY_PLLCURRGMPCTRL); ++ dw_hdmi_phy_i2c_write(hdmi, params->div, RCAR_HDMI_PHY_PLLDIVCTRL); ++ ++ return 0; ++} ++ ++static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = { ++ .configure_phy = rcar_hdmi_phy_configure, ++}; ++ ++static int rcar_dw_hdmi_probe(struct platform_device *pdev) ++{ ++ return dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data); ++} ++ ++static int rcar_dw_hdmi_remove(struct platform_device *pdev) ++{ ++ dw_hdmi_remove(pdev); ++ ++ return 0; ++} ++ ++static const struct of_device_id rcar_dw_hdmi_of_table[] = { ++ { .compatible = "renesas,rcar-gen3-hdmi" }, ++ { /* Sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, rcar_dw_hdmi_of_table); ++ ++static struct platform_driver rcar_dw_hdmi_platform_driver = { ++ .probe = rcar_dw_hdmi_probe, ++ .remove = rcar_dw_hdmi_remove, ++ .driver = { ++ .name = "rcar-dw-hdmi", ++ .of_match_table = rcar_dw_hdmi_of_table, ++ }, ++}; ++ ++module_platform_driver(rcar_dw_hdmi_platform_driver); ++ ++MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); ++MODULE_DESCRIPTION("Renesas R-Car Gen3 HDMI Encoder Driver"); ++MODULE_LICENSE("GPL"); +-- +2.13.3 + diff --git a/patches.renesas/0262-drm-rcar-du-Skip-disabled-outputs.patch b/patches.renesas/0262-drm-rcar-du-Skip-disabled-outputs.patch new file mode 100644 index 00000000000000..f0dd5e73cdac68 --- /dev/null +++ b/patches.renesas/0262-drm-rcar-du-Skip-disabled-outputs.patch @@ -0,0 +1,36 @@ +From 5b922f83b4e16ec2263289520d8a862a8b0c7af3 Mon Sep 17 00:00:00 2001 +From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +Date: Thu, 1 Dec 2016 13:07:49 +0200 +Subject: [PATCH 262/286] drm: rcar-du: Skip disabled outputs + +When a DT node connected to a DU output is disabled no bridge will ever +be instantiated for it. Skip the output in that case. + +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 4739a0d40b668ed4d60e048ee8ff03cd863e0987) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_kms.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +index d845e82f4653..b89cb152b720 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +@@ -302,6 +302,13 @@ static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu, + return -ENODEV; + } + ++ if (!of_device_is_available(entity)) { ++ dev_dbg(rcdu->dev, ++ "connected entity %s is disabled, skipping\n", ++ entity->full_name); ++ return -ENODEV; ++ } ++ + entity_ep_node = of_parse_phandle(ep->local_node, "remote-endpoint", 0); + + for_each_endpoint_of_node(entity, ep_node) { +-- +2.13.3 + diff --git a/patches.renesas/0263-drm-rcar-du-Add-DPLL-support.patch b/patches.renesas/0263-drm-rcar-du-Add-DPLL-support.patch new file mode 100644 index 00000000000000..bee21ceb26e5f9 --- /dev/null +++ b/patches.renesas/0263-drm-rcar-du-Add-DPLL-support.patch @@ -0,0 +1,197 @@ +From ffa694b7ce4a92c980e8325357901963fd3026e3 Mon Sep 17 00:00:00 2001 +From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Date: Fri, 11 Nov 2016 18:07:41 +0100 +Subject: [PATCH 263/286] drm: rcar-du: Add DPLL support + +The implementation hardcodes a workaround for the H3 ES1.x SoC +regardless of the SoC revision, as the workaround can be safely applied +on all devices in the Gen3 family without any side effect. + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit dc4aedbf7c152c092c19e980a9fa1e89d6bc215f) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 81 +++++++++++++++++++++++++++++++++- + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 1 + + drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + + drivers/gpu/drm/rcar-du/rcar_du_regs.h | 23 ++++++++++ + 4 files changed, 105 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +index 75bcb5e19cca..c903f33b2abe 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +@@ -106,9 +106,62 @@ static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc) + * Hardware Setup + */ + ++struct dpll_info { ++ unsigned int output; ++ unsigned int fdpll; ++ unsigned int n; ++ unsigned int m; ++}; ++ ++static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc, ++ struct dpll_info *dpll, ++ unsigned long input, ++ unsigned long target) ++{ ++ unsigned long best_diff = (unsigned long)-1; ++ unsigned long diff; ++ unsigned int fdpll; ++ unsigned int m; ++ unsigned int n; ++ ++ for (n = 39; n < 120; n++) { ++ for (m = 0; m < 4; m++) { ++ for (fdpll = 1; fdpll < 32; fdpll++) { ++ unsigned long output; ++ ++ /* 1/2 (FRQSEL=1) for duty rate 50% */ ++ output = input * (n + 1) / (m + 1) ++ / (fdpll + 1) / 2; ++ ++ if (output >= 400000000) ++ continue; ++ ++ diff = abs((long)output - (long)target); ++ if (best_diff > diff) { ++ best_diff = diff; ++ dpll->n = n; ++ dpll->m = m; ++ dpll->fdpll = fdpll; ++ dpll->output = output; ++ } ++ ++ if (diff == 0) ++ goto done; ++ } ++ } ++ } ++ ++done: ++ dev_dbg(rcrtc->group->dev->dev, ++ "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n", ++ dpll->output, dpll->fdpll, dpll->n, dpll->m, ++ best_diff); ++} ++ + static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) + { + const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; ++ struct rcar_du_device *rcdu = rcrtc->group->dev; + unsigned long mode_clock = mode->clock * 1000; + unsigned long clk; + u32 value; +@@ -124,12 +177,18 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) + escr = div | ESCR_DCLKSEL_CLKS; + + if (rcrtc->extclock) { ++ struct dpll_info dpll = { 0 }; + unsigned long extclk; + unsigned long extrate; + unsigned long rate; + u32 extdiv; + + extclk = clk_get_rate(rcrtc->extclock); ++ if (rcdu->info->dpll_ch & (1 << rcrtc->index)) { ++ rcar_du_dpll_divider(rcrtc, &dpll, extclk, mode_clock); ++ extclk = dpll.output; ++ } ++ + extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock); + extdiv = clamp(extdiv, 1U, 64U) - 1; + +@@ -140,7 +199,27 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) + abs((long)rate - (long)mode_clock)) { + dev_dbg(rcrtc->group->dev->dev, + "crtc%u: using external clock\n", rcrtc->index); +- escr = extdiv | ESCR_DCLKSEL_DCLKIN; ++ ++ if (rcdu->info->dpll_ch & (1 << rcrtc->index)) { ++ u32 dpllcr = DPLLCR_CODE | DPLLCR_CLKE ++ | DPLLCR_FDPLL(dpll.fdpll) ++ | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) ++ | DPLLCR_STBY; ++ ++ if (rcrtc->index == 1) ++ dpllcr |= DPLLCR_PLCS1 ++ | DPLLCR_INCS_DOTCLKIN1; ++ else ++ dpllcr |= DPLLCR_PLCS0 ++ | DPLLCR_INCS_DOTCLKIN0; ++ ++ rcar_du_group_write(rcrtc->group, DPLLCR, ++ dpllcr); ++ ++ escr = ESCR_DCLKSEL_DCLKIN | 1; ++ } else { ++ escr = ESCR_DCLKSEL_DCLKIN | extdiv; ++ } + } + } + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +index 8ac5f5a64144..da55ac11a252 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +@@ -163,6 +163,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { + }, + }, + .num_lvds = 1, ++ .dpll_ch = BIT(1) | BIT(2), + }; + + static const struct rcar_du_device_info rcar_du_r8a7796_info = { +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +index 90eb209c244e..f8cd79488ece 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +@@ -65,6 +65,7 @@ struct rcar_du_device_info { + unsigned int num_crtcs; + struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX]; + unsigned int num_lvds; ++ unsigned int dpll_ch; + }; + + #define RCAR_DU_MAX_CRTCS 4 +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h +index fedb0161e234..d5bae99d3cfe 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h +@@ -277,6 +277,29 @@ + #define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */ + #define DEFR10_DEFE10 (1 << 0) + ++#define DPLLCR 0x20044 ++#define DPLLCR_CODE (0x95 << 24) ++#define DPLLCR_PLCS1 (1 << 23) ++/* ++ * PLCS0 is bit 21, but H3 ES1.x requires bit 20 to be set as well. As bit 20 ++ * isn't implemented by other SoC in the Gen3 family it can safely be set ++ * unconditionally. ++ */ ++#define DPLLCR_PLCS0 (3 << 20) ++#define DPLLCR_CLKE (1 << 18) ++#define DPLLCR_FDPLL(n) ((n) << 12) ++#define DPLLCR_N(n) ((n) << 5) ++#define DPLLCR_M(n) ((n) << 3) ++#define DPLLCR_STBY (1 << 2) ++#define DPLLCR_INCS_DOTCLKIN0 (0 << 0) ++#define DPLLCR_INCS_DOTCLKIN1 (1 << 1) ++ ++#define DPLLC2R 0x20048 ++#define DPLLC2R_CODE (0x95 << 24) ++#define DPLLC2R_SELC (1 << 12) ++#define DPLLC2R_M(n) ((n) << 8) ++#define DPLLC2R_FDPLL(n) ((n) << 0) ++ + /* ----------------------------------------------------------------------------- + * Display Timing Generation Registers + */ +-- +2.13.3 + diff --git a/patches.renesas/0264-drm-rcar-du-Add-HDMI-outputs-to-R8A7795-device-descr.patch b/patches.renesas/0264-drm-rcar-du-Add-HDMI-outputs-to-R8A7795-device-descr.patch new file mode 100644 index 00000000000000..55ea9c166b0f9c --- /dev/null +++ b/patches.renesas/0264-drm-rcar-du-Add-HDMI-outputs-to-R8A7795-device-descr.patch @@ -0,0 +1,70 @@ +From 23f501fe5138974473d0d042758d268c9f627fe1 Mon Sep 17 00:00:00 2001 +From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Date: Fri, 11 Nov 2016 18:07:39 +0100 +Subject: [PATCH 264/286] drm: rcar-du: Add HDMI outputs to R8A7795 device + description + +Update the device description with the two available HDMI outputs. + +Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> +Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> +(cherry picked from commit 0dda563e571093f309d597cafaf7dd535496ecfb) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 4 +++- + drivers/gpu/drm/rcar-du/rcar_du_drv.c | 12 ++++++++++-- + 2 files changed, 13 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +index 6f08b7e7db06..459e5390d6e0 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h ++++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +@@ -1,7 +1,7 @@ + /* + * rcar_du_crtc.h -- R-Car Display Unit CRTCs + * +- * Copyright (C) 2013-2014 Renesas Electronics Corporation ++ * Copyright (C) 2013-2015 Renesas Electronics Corporation + * + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) + * +@@ -61,6 +61,8 @@ enum rcar_du_output { + RCAR_DU_OUTPUT_DPAD1, + RCAR_DU_OUTPUT_LVDS0, + RCAR_DU_OUTPUT_LVDS1, ++ RCAR_DU_OUTPUT_HDMI0, ++ RCAR_DU_OUTPUT_HDMI1, + RCAR_DU_OUTPUT_TCON, + RCAR_DU_OUTPUT_MAX, + }; +diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +index da55ac11a252..01981f004dc3 100644 +--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c ++++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c +@@ -150,13 +150,21 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { + | RCAR_DU_FEATURE_VSP1_SOURCE, + .num_crtcs = 4, + .routes = { +- /* R8A7795 has one RGB output, one LVDS output and two +- * (currently unsupported) HDMI outputs. ++ /* R8A7795 has one RGB output, two HDMI outputs and one ++ * LVDS output. + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(3), + .port = 0, + }, ++ [RCAR_DU_OUTPUT_HDMI0] = { ++ .possible_crtcs = BIT(1), ++ .port = 1, ++ }, ++ [RCAR_DU_OUTPUT_HDMI1] = { ++ .possible_crtcs = BIT(2), ++ .port = 2, ++ }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), + .port = 3, +-- +2.13.3 + diff --git a/patches.renesas/0265-ARM-dts-r8a7743-Add-reset-control-properties.patch b/patches.renesas/0265-ARM-dts-r8a7743-Add-reset-control-properties.patch new file mode 100644 index 00000000000000..ddc13b218bac15 --- /dev/null +++ b/patches.renesas/0265-ARM-dts-r8a7743-Add-reset-control-properties.patch @@ -0,0 +1,220 @@ +From 9b05820772244194495115b82ca92722a816f0e1 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 16 Mar 2017 15:07:25 +0100 +Subject: [PATCH 265/286] ARM: dts: r8a7743: Add reset control properties + +Add properties to describe the reset topology for on-SoC devices: + - Add the "#reset-cells" property to the CPG/MSSR device node, + - Add resets and reset-names properties to the various device nodes. + +This allows to reset SoC devices using the Reset Controller API. + +Note that all resets added match the corresponding module clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d20747b7df51178db5f5c7a03cbf17a91bdb6f0e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi +index cd908796fb3b..0ddac81742e4 100644 +--- a/arch/arm/boot/dts/r8a7743.dtsi ++++ b/arch/arm/boot/dts/r8a7743.dtsi +@@ -62,6 +62,7 @@ + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 408>; + }; + + irqc: interrupt-controller@e61c0000 { +@@ -81,6 +82,7 @@ + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 407>; + }; + + timer { +@@ -102,6 +104,7 @@ + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; ++ #reset-cells = <1>; + }; + + prr: chipid@ff000044 { +@@ -148,6 +151,7 @@ + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -180,6 +184,7 @@ + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -195,6 +200,7 @@ + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 204>; + status = "disabled"; + }; + +@@ -209,6 +215,7 @@ + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 203>; + status = "disabled"; + }; + +@@ -223,6 +230,7 @@ + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 202>; + status = "disabled"; + }; + +@@ -237,6 +245,7 @@ + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 1106>; + status = "disabled"; + }; + +@@ -251,6 +260,7 @@ + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 1107>; + status = "disabled"; + }; + +@@ -265,6 +275,7 @@ + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 1108>; + status = "disabled"; + }; + +@@ -279,6 +290,7 @@ + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 206>; + status = "disabled"; + }; + +@@ -293,6 +305,7 @@ + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 207>; + status = "disabled"; + }; + +@@ -307,6 +320,7 @@ + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 216>; + status = "disabled"; + }; + +@@ -322,6 +336,7 @@ + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 721>; + status = "disabled"; + }; + +@@ -337,6 +352,7 @@ + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 720>; + status = "disabled"; + }; + +@@ -352,6 +368,7 @@ + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 719>; + status = "disabled"; + }; + +@@ -367,6 +384,7 @@ + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 718>; + status = "disabled"; + }; + +@@ -382,6 +400,7 @@ + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 715>; + status = "disabled"; + }; + +@@ -397,6 +416,7 @@ + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 714>; + status = "disabled"; + }; + +@@ -412,6 +432,7 @@ + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 717>; + status = "disabled"; + }; + +@@ -427,6 +448,7 @@ + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 716>; + status = "disabled"; + }; + +@@ -442,6 +464,7 @@ + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 713>; + status = "disabled"; + }; + +@@ -451,6 +474,7 @@ + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; ++ resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0266-ARM-dts-r8a7745-Add-reset-control-properties.patch b/patches.renesas/0266-ARM-dts-r8a7745-Add-reset-control-properties.patch new file mode 100644 index 00000000000000..cc90456c87ebe2 --- /dev/null +++ b/patches.renesas/0266-ARM-dts-r8a7745-Add-reset-control-properties.patch @@ -0,0 +1,220 @@ +From f34147de7465b11d041aa2456aac9c2c0ebfb7fa Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Thu, 16 Mar 2017 15:07:26 +0100 +Subject: [PATCH 266/286] ARM: dts: r8a7745: Add reset control properties + +Add properties to describe the reset topology for on-SoC devices: + - Add the "#reset-cells" property to the CPG/MSSR device node, + - Add resets and reset-names properties to the various device nodes. + +This allows to reset SoC devices using the Reset Controller API. + +Note that all resets added match the corresponding module clocks. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1efab6e91e8e789f98a11d6618f0fd66f1c51f98) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7745.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi +index bca88715fada..2feb0084bb3b 100644 +--- a/arch/arm/boot/dts/r8a7745.dtsi ++++ b/arch/arm/boot/dts/r8a7745.dtsi +@@ -62,6 +62,7 @@ + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 408>; + }; + + irqc: interrupt-controller@e61c0000 { +@@ -81,6 +82,7 @@ + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 407>; + }; + + timer { +@@ -102,6 +104,7 @@ + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; ++ #reset-cells = <1>; + }; + + prr: chipid@ff000044 { +@@ -148,6 +151,7 @@ + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -180,6 +184,7 @@ + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; +@@ -195,6 +200,7 @@ + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 204>; + status = "disabled"; + }; + +@@ -209,6 +215,7 @@ + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 203>; + status = "disabled"; + }; + +@@ -223,6 +230,7 @@ + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 202>; + status = "disabled"; + }; + +@@ -237,6 +245,7 @@ + <&dmac1 0x1b>, <&dmac1 0x1c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 1106>; + status = "disabled"; + }; + +@@ -251,6 +260,7 @@ + <&dmac1 0x1f>, <&dmac1 0x20>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 1107>; + status = "disabled"; + }; + +@@ -265,6 +275,7 @@ + <&dmac1 0x23>, <&dmac1 0x24>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 1108>; + status = "disabled"; + }; + +@@ -279,6 +290,7 @@ + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 206>; + status = "disabled"; + }; + +@@ -293,6 +305,7 @@ + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 207>; + status = "disabled"; + }; + +@@ -307,6 +320,7 @@ + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 216>; + status = "disabled"; + }; + +@@ -322,6 +336,7 @@ + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 721>; + status = "disabled"; + }; + +@@ -337,6 +352,7 @@ + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 720>; + status = "disabled"; + }; + +@@ -352,6 +368,7 @@ + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 719>; + status = "disabled"; + }; + +@@ -367,6 +384,7 @@ + <&dmac1 0x2f>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 718>; + status = "disabled"; + }; + +@@ -382,6 +400,7 @@ + <&dmac1 0xfb>, <&dmac1 0xfc>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 715>; + status = "disabled"; + }; + +@@ -397,6 +416,7 @@ + <&dmac1 0xfd>, <&dmac1 0xfe>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 714>; + status = "disabled"; + }; + +@@ -412,6 +432,7 @@ + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 717>; + status = "disabled"; + }; + +@@ -427,6 +448,7 @@ + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 716>; + status = "disabled"; + }; + +@@ -442,6 +464,7 @@ + <&dmac1 0x3b>, <&dmac1 0x3c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 713>; + status = "disabled"; + }; + +@@ -451,6 +474,7 @@ + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; ++ resets = <&cpg 813>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0267-ARM-dts-r7s72100-add-power-domains-to-sdhi.patch b/patches.renesas/0267-ARM-dts-r7s72100-add-power-domains-to-sdhi.patch new file mode 100644 index 00000000000000..90bb9b8b12b97c --- /dev/null +++ b/patches.renesas/0267-ARM-dts-r7s72100-add-power-domains-to-sdhi.patch @@ -0,0 +1,39 @@ +From ccdbd481ea32162ad45febe055b36498b0380200 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Thu, 9 Feb 2017 08:38:03 -0500 +Subject: [PATCH 267/286] ARM: dts: r7s72100: add power-domains to sdhi + +Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") +Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3932197c01e4ca7d743d07728656d938f1ae93d5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 9b12d73e67dc..9fb2e510958a 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -501,6 +501,7 @@ + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; ++ power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; +@@ -516,6 +517,7 @@ + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; ++ power-domains = <&cpg_clocks>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; +-- +2.13.3 + diff --git a/patches.renesas/0268-ARM-dts-r8a7794-Add-DU1-clock-to-device-tree.patch b/patches.renesas/0268-ARM-dts-r8a7794-Add-DU1-clock-to-device-tree.patch new file mode 100644 index 00000000000000..dad73645e99601 --- /dev/null +++ b/patches.renesas/0268-ARM-dts-r8a7794-Add-DU1-clock-to-device-tree.patch @@ -0,0 +1,61 @@ +From 3f8647c4d9036e7c01c7ed719c227b343db15893 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 12:45:30 +0200 +Subject: [PATCH 268/286] ARM: dts: r8a7794: Add DU1 clock to device tree + +Add the missing module clock for the second channel of the display unit. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1764f8081f1524bf629e0744b277db751281ff56) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 8 +++++--- + include/dt-bindings/clock/r8a7794-clock.h | 1 + + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 38bf9ed8e739..f5f8d1c03ef7 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -1270,19 +1270,21 @@ + clocks = <&mp_clk>, <&hp_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, +- <&zx_clk>; ++ <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7794_CLK_EHCI R8A7794_CLK_HSUSB + R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 + R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 + R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 +- R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 ++ R8A7794_CLK_SCIF0 ++ R8A7794_CLK_DU1 R8A7794_CLK_DU0 + >; + clock-output-names = + "ehci", "hsusb", + "hscif2", "scif5", "scif4", "hscif1", "hscif0", +- "scif3", "scif2", "scif1", "scif0", "du0"; ++ "scif3", "scif2", "scif1", "scif0", ++ "du1", "du0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h +index a26776f7dedd..93e99c3ffc8d 100644 +--- a/include/dt-bindings/clock/r8a7794-clock.h ++++ b/include/dt-bindings/clock/r8a7794-clock.h +@@ -82,6 +82,7 @@ + #define R8A7794_CLK_SCIF2 19 + #define R8A7794_CLK_SCIF1 20 + #define R8A7794_CLK_SCIF0 21 ++#define R8A7794_CLK_DU1 23 + #define R8A7794_CLK_DU0 24 + + /* MSTP8 */ +-- +2.13.3 + diff --git a/patches.renesas/0269-ARM-dts-r8a7794-Correct-clock-of-DU1.patch b/patches.renesas/0269-ARM-dts-r8a7794-Correct-clock-of-DU1.patch new file mode 100644 index 00000000000000..3948a4088a2930 --- /dev/null +++ b/patches.renesas/0269-ARM-dts-r8a7794-Correct-clock-of-DU1.patch @@ -0,0 +1,34 @@ +From 947c7b557720636aa4578af4df216d2b7132b5b8 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 12:45:31 +0200 +Subject: [PATCH 269/286] ARM: dts: r8a7794: Correct clock of DU1 + +The second channel of the display unit uses a different module clock +than the first channel. + +Fixes: 46c4f13d04d729fa ("ARM: shmobile: r8a7794: Add DU node to device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 89675f36c9e17512812b9d14d9824f8ef92782c3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index f5f8d1c03ef7..2f6e94fd408c 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -925,7 +925,7 @@ + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_DU0>, +- <&mstp7_clks R8A7794_CLK_DU0>; ++ <&mstp7_clks R8A7794_CLK_DU1>; + clock-names = "du.0", "du.1"; + status = "disabled"; + +-- +2.13.3 + diff --git a/patches.renesas/0270-ARM-dts-alt-Correct-clock-of-DU1.patch b/patches.renesas/0270-ARM-dts-alt-Correct-clock-of-DU1.patch new file mode 100644 index 00000000000000..a721a802932689 --- /dev/null +++ b/patches.renesas/0270-ARM-dts-alt-Correct-clock-of-DU1.patch @@ -0,0 +1,34 @@ +From 10beaead64875c8ab8ff7e91c6f08a5a7cc654c7 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 12:45:32 +0200 +Subject: [PATCH 270/286] ARM: dts: alt: Correct clock of DU1 + +The second channel of the display unit uses a different module clock +than the first channel. + +Fixes: 876e7fb9f418fd86 ("ARM: shmobile: r8a7794: alt: Enable VGA port") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7f698bf60e3a13c991577f5360f371e2a41cf40e) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794-alt.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts +index 3fcf76b8e923..f1eea13cdf44 100644 +--- a/arch/arm/boot/dts/r8a7794-alt.dts ++++ b/arch/arm/boot/dts/r8a7794-alt.dts +@@ -168,7 +168,7 @@ + status = "okay"; + + clocks = <&mstp7_clks R8A7794_CLK_DU0>, +- <&mstp7_clks R8A7794_CLK_DU0>, ++ <&mstp7_clks R8A7794_CLK_DU1>, + <&x13_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + +-- +2.13.3 + diff --git a/patches.renesas/0271-ARM-dts-silk-Correct-clock-of-DU1.patch b/patches.renesas/0271-ARM-dts-silk-Correct-clock-of-DU1.patch new file mode 100644 index 00000000000000..bd2f103dea3c60 --- /dev/null +++ b/patches.renesas/0271-ARM-dts-silk-Correct-clock-of-DU1.patch @@ -0,0 +1,34 @@ +From f7ec308c7284327d220af81f5c3fafb23db3f3b2 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Tue, 28 Mar 2017 12:45:33 +0200 +Subject: [PATCH 271/286] ARM: dts: silk: Correct clock of DU1 + +The second channel of the display unit uses a different module clock +than the first channel. + +Fixes: 84e734f497cd48f6 ("ARM: dts: silk: add DU DT support") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 403fe77e22eb72c962c3889efc9d4fa62e454737) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794-silk.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts +index c742d80d6dca..4cb5278d104d 100644 +--- a/arch/arm/boot/dts/r8a7794-silk.dts ++++ b/arch/arm/boot/dts/r8a7794-silk.dts +@@ -424,7 +424,7 @@ + status = "okay"; + + clocks = <&mstp7_clks R8A7794_CLK_DU0>, +- <&mstp7_clks R8A7794_CLK_DU0>, ++ <&mstp7_clks R8A7794_CLK_DU1>, + <&x2_clk>, <&x3_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + +-- +2.13.3 + diff --git a/patches.renesas/0272-ARM-dts-r7s72100-fix-ethernet-clock-parent.patch b/patches.renesas/0272-ARM-dts-r7s72100-fix-ethernet-clock-parent.patch new file mode 100644 index 00000000000000..0cb39df6b0e0c1 --- /dev/null +++ b/patches.renesas/0272-ARM-dts-r7s72100-fix-ethernet-clock-parent.patch @@ -0,0 +1,34 @@ +From c1bee37fcaf3a0b95972ed5705c16f9f643d1211 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Thu, 30 Mar 2017 14:16:09 -0700 +Subject: [PATCH 272/286] ARM: dts: r7s72100: fix ethernet clock parent + +Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not +the 33MHz Peripheral 0 (P0) clock. + +Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree") +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 91a7c50cb4fabfba218549dfa84356069918bfbf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 9fb2e510958a..47ef53a4c8bf 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -121,7 +121,7 @@ + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; +- clocks = <&p0_clk>; ++ clocks = <&b_clk>; + clock-indices = <R7S72100_CLK_ETHER>; + clock-output-names = "ether"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0273-ARM-dts-r8a7790-Correct-parent-of-SSI-0-9-clocks.patch b/patches.renesas/0273-ARM-dts-r8a7790-Correct-parent-of-SSI-0-9-clocks.patch new file mode 100644 index 00000000000000..2b0c0de9849caf --- /dev/null +++ b/patches.renesas/0273-ARM-dts-r8a7790-Correct-parent-of-SSI-0-9-clocks.patch @@ -0,0 +1,39 @@ +From c5483018b947d49e2a2b94ea9557da10cf1d1894 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:45:41 +0200 +Subject: [PATCH 273/286] ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks + +The SSI-ALL gate clock is located in between the P clock and the +individual SSI[0-9] clocks, hence the former should be listed as their +parent. + +Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit d13d4e063d4a08eb1686e890e9183dde709871bf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index 534525665bb3..fe6b8c2a2d71 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1443,8 +1443,11 @@ + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, ++ <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, +-- +2.13.3 + diff --git a/patches.renesas/0274-ARM-dts-r8a7791-Correct-parent-of-SSI-0-9-clocks.patch b/patches.renesas/0274-ARM-dts-r8a7791-Correct-parent-of-SSI-0-9-clocks.patch new file mode 100644 index 00000000000000..6daed32b9752da --- /dev/null +++ b/patches.renesas/0274-ARM-dts-r8a7791-Correct-parent-of-SSI-0-9-clocks.patch @@ -0,0 +1,39 @@ +From d0d6f55d7423bc18a7bf61c23a7cf65153e25f12 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:45:42 +0200 +Subject: [PATCH 274/286] ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks + +The SSI-ALL gate clock is located in between the P clock and the +individual SSI[0-9] clocks, hence the former should be listed as their +parent. + +Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 16fe68dcab5702a024d85229ff7e98979cb701a5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 4202d474992e..234daf480122 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1447,8 +1447,11 @@ + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, ++ <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, +-- +2.13.3 + diff --git a/patches.renesas/0275-ARM-dts-r8a7793-Correct-parent-of-SSI-0-9-clocks.patch b/patches.renesas/0275-ARM-dts-r8a7793-Correct-parent-of-SSI-0-9-clocks.patch new file mode 100644 index 00000000000000..a3c47539699a98 --- /dev/null +++ b/patches.renesas/0275-ARM-dts-r8a7793-Correct-parent-of-SSI-0-9-clocks.patch @@ -0,0 +1,39 @@ +From bb124ff17ad8c8612b4c4cf8d094e898cdc6bfd2 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:45:43 +0200 +Subject: [PATCH 275/286] ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks + +The SSI-ALL gate clock is located in between the P clock and the +individual SSI[0-9] clocks, hence the former should be listed as their +parent. + +Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 1cd9028027c7a7c10b774df698c3cfafec6aa67d) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7793.dtsi | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi +index 9fcf3a9ca084..4de6041d61f9 100644 +--- a/arch/arm/boot/dts/r8a7793.dtsi ++++ b/arch/arm/boot/dts/r8a7793.dtsi +@@ -1269,8 +1269,11 @@ + compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, +- <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, ++ <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, ++ <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, + <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, +-- +2.13.3 + diff --git a/patches.renesas/0276-ARM-dts-r8a7792-Correct-Z-clock.patch b/patches.renesas/0276-ARM-dts-r8a7792-Correct-Z-clock.patch new file mode 100644 index 00000000000000..69fa7c9308578f --- /dev/null +++ b/patches.renesas/0276-ARM-dts-r8a7792-Correct-Z-clock.patch @@ -0,0 +1,79 @@ +From 6d4370067dc6d7c5887910505576db138cd53aea Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:53:08 +0200 +Subject: [PATCH 276/286] ARM: dts: r8a7792: Correct Z clock + +Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does +not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a +fixed divider. +This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. + +Hence: + - Remove the Z clock output from the cpg_clocks node, as this implied + a programmable clock, + - Add the Z clock as a fixed factor clock, + - Let the first CPU node point to the new Z clock, + - Remove the Z clock index from the bindings (this definition was used + by r8a7792.dtsi only, and was not a contract between DT and driver). + +Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 7b39e985cfc18bba43646240b10a830046382abf) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7792.dtsi | 11 +++++++++-- + include/dt-bindings/clock/r8a7792-clock.h | 1 - + 2 files changed, 9 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi +index 6c0797ebc08f..0efecb232ee5 100644 +--- a/arch/arm/boot/dts/r8a7792.dtsi ++++ b/arch/arm/boot/dts/r8a7792.dtsi +@@ -46,7 +46,7 @@ + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1000000000>; +- clocks = <&cpg_clocks R8A7792_CLK_Z>; ++ clocks = <&z_clk>; + power-domains = <&sysc R8A7792_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; +@@ -766,7 +766,7 @@ + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", +- "lb", "qspi", "z"; ++ "lb", "qspi"; + #power-domain-cells = <0>; + }; + +@@ -778,6 +778,13 @@ + clock-div = <2>; + clock-mult = <1>; + }; ++ z_clk: z { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7792_CLK_PLL0>; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ }; + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; +diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h +index 94dd16a1e6e6..5be90bc23bd7 100644 +--- a/include/dt-bindings/clock/r8a7792-clock.h ++++ b/include/dt-bindings/clock/r8a7792-clock.h +@@ -17,7 +17,6 @@ + #define R8A7792_CLK_PLL3 3 + #define R8A7792_CLK_LB 4 + #define R8A7792_CLK_QSPI 5 +-#define R8A7792_CLK_Z 6 + + /* MSTP0 */ + #define R8A7792_CLK_MSIOF0 0 +-- +2.13.3 + diff --git a/patches.renesas/0277-ARM-dts-r8a7794-Add-Z2-clock.patch b/patches.renesas/0277-ARM-dts-r8a7794-Add-Z2-clock.patch new file mode 100644 index 00000000000000..2dd32210a08ec8 --- /dev/null +++ b/patches.renesas/0277-ARM-dts-r8a7794-Add-Z2-clock.patch @@ -0,0 +1,45 @@ +From f2ba1c8d15823721be61d3d8001805c3dd78059d Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:54:14 +0200 +Subject: [PATCH 277/286] ARM: dts: r8a7794: Add Z2 clock + +Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, +and link the first CPU node to it. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 57ff9d736e05bede56fdb47599fdddb3408d4651) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7794.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi +index 2f6e94fd408c..a19b884fb258 100644 +--- a/arch/arm/boot/dts/r8a7794.dtsi ++++ b/arch/arm/boot/dts/r8a7794.dtsi +@@ -43,6 +43,7 @@ + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; ++ clocks = <&z2_clk>; + power-domains = <&sysc R8A7794_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; +@@ -1064,6 +1065,13 @@ + clock-div = <2>; + clock-mult = <1>; + }; ++ z2_clk: z2 { ++ compatible = "fixed-factor-clock"; ++ clocks = <&cpg_clocks R8A7794_CLK_PLL0>; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ }; + zg_clk: zg { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; +-- +2.13.3 + diff --git a/patches.renesas/0278-ARM-dts-koelsch-Correct-clock-frequency-of-X2-DU-clo.patch b/patches.renesas/0278-ARM-dts-koelsch-Correct-clock-frequency-of-X2-DU-clo.patch new file mode 100644 index 00000000000000..9c17196ed71bb2 --- /dev/null +++ b/patches.renesas/0278-ARM-dts-koelsch-Correct-clock-frequency-of-X2-DU-clo.patch @@ -0,0 +1,39 @@ +From 67c64333cb984de13d6dc7f1175a47eb1690a332 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 11:55:19 +0200 +Subject: [PATCH 278/286] ARM: dts: koelsch: Correct clock frequency of X2 DU + clock input +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The X2 crystal oscillator on the Koelsch development board provides a +74.25 MHz clock, not a 148.5 MHz clock. + +Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT") +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> +Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit ebf06af55c7594ed1fc18469a5cddf911c40e687) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts +index 59beb8402a36..001e6116c47c 100644 +--- a/arch/arm/boot/dts/r8a7791-koelsch.dts ++++ b/arch/arm/boot/dts/r8a7791-koelsch.dts +@@ -292,7 +292,7 @@ + x2_clk: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; +- clock-frequency = <148500000>; ++ clock-frequency = <74250000>; + }; + + x13_clk: x13-clock { +-- +2.13.3 + diff --git a/patches.renesas/0279-ARM-dts-r7s72100-add-rtc-clock-to-device-tree.patch b/patches.renesas/0279-ARM-dts-r7s72100-add-rtc-clock-to-device-tree.patch new file mode 100644 index 00000000000000..7b0f017d0033e5 --- /dev/null +++ b/patches.renesas/0279-ARM-dts-r7s72100-add-rtc-clock-to-device-tree.patch @@ -0,0 +1,54 @@ +From fc8281a2c0406283e2e7a510aed6b4626ce2a848 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:31 -0700 +Subject: [PATCH 279/286] ARM: dts: r7s72100: add rtc clock to device tree + +Add the realtime clock functional clock source. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 929ded3dd7ce91d9ef4143d673b4ace2eb9ab355) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ + include/dt-bindings/clock/r7s72100-clock.h | 3 +++ + 2 files changed, 12 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 47ef53a4c8bf..9eace892fec7 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -117,6 +117,15 @@ + clock-output-names = "ostm0", "ostm1"; + }; + ++ mstp6_clks: mstp6_clks@fcfe042c { ++ #clock-cells = <1>; ++ compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; ++ reg = <0xfcfe042c 4>; ++ clocks = <&p0_clk>; ++ clock-indices = <R7S72100_CLK_RTC>; ++ clock-output-names = "rtc"; ++ }; ++ + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; +diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h +index cd2ed5194255..bc256d31099a 100644 +--- a/include/dt-bindings/clock/r7s72100-clock.h ++++ b/include/dt-bindings/clock/r7s72100-clock.h +@@ -29,6 +29,9 @@ + #define R7S72100_CLK_OSTM0 1 + #define R7S72100_CLK_OSTM1 0 + ++/* MSTP6 */ ++#define R7S72100_CLK_RTC 0 ++ + /* MSTP7 */ + #define R7S72100_CLK_ETHER 4 + +-- +2.13.3 + diff --git a/patches.renesas/0280-ARM-dts-r7s72100-add-RTC_X-clock-inputs-to-device-tr.patch b/patches.renesas/0280-ARM-dts-r7s72100-add-RTC_X-clock-inputs-to-device-tr.patch new file mode 100644 index 00000000000000..f692b53994ba5f --- /dev/null +++ b/patches.renesas/0280-ARM-dts-r7s72100-add-RTC_X-clock-inputs-to-device-tr.patch @@ -0,0 +1,46 @@ +From cda0660d0b6a96d3cac8d2aa0980f50edde8b73e Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:32 -0700 +Subject: [PATCH 280/286] ARM: dts: r7s72100: add RTC_X clock inputs to device + tree + +Add the RTC clocks to device tree. The frequencies must be fixed values +according to the hardware manual. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit deddcb891d0d2b4f437dea9bdea4752982c4b133) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 9eace892fec7..9db46ac08ba7 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -51,6 +51,20 @@ + clock-frequency = <0>; + }; + ++ rtc_x1_clk: rtc_x1 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ /* If clk present, value must be set by board to 32678 */ ++ clock-frequency = <0>; ++ }; ++ ++ rtc_x3_clk: rtc_x3 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ /* If clk present, value must be set by board to 4000000 */ ++ clock-frequency = <0>; ++ }; ++ + /* Fixed factor clocks */ + b_clk: b { + #clock-cells = <0>; +-- +2.13.3 + diff --git a/patches.renesas/0281-ARM-dts-r7s72100-add-rtc-to-device-tree.patch b/patches.renesas/0281-ARM-dts-r7s72100-add-rtc-to-device-tree.patch new file mode 100644 index 00000000000000..32753eac174119 --- /dev/null +++ b/patches.renesas/0281-ARM-dts-r7s72100-add-rtc-to-device-tree.patch @@ -0,0 +1,42 @@ +From 5a1356592873f9ce9780f4f869038df93ebd71a9 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:33 -0700 +Subject: [PATCH 281/286] ARM: dts: r7s72100: add rtc to device tree + +Add the realtime clock device node. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 3b5e3f0455442f376f91c69147526535a0389ac3) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi +index 9db46ac08ba7..ab9ced453118 100644 +--- a/arch/arm/boot/dts/r7s72100.dtsi ++++ b/arch/arm/boot/dts/r7s72100.dtsi +@@ -563,4 +563,18 @@ + power-domains = <&cpg_clocks>; + status = "disabled"; + }; ++ ++ rtc: rtc@fcff1000 { ++ compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc"; ++ reg = <0xfcff1000 0x2e>; ++ interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING ++ GIC_SPI 277 IRQ_TYPE_EDGE_RISING ++ GIC_SPI 278 IRQ_TYPE_EDGE_RISING>; ++ interrupt-names = "alarm", "period", "carry"; ++ clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, ++ <&rtc_x3_clk>, <&extal_clk>; ++ clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; ++ power-domains = <&cpg_clocks>; ++ status = "disabled"; ++ }; + }; +-- +2.13.3 + diff --git a/patches.renesas/0282-ARM-dts-rskrza1-set-rtc_x1-clock-value.patch b/patches.renesas/0282-ARM-dts-rskrza1-set-rtc_x1-clock-value.patch new file mode 100644 index 00000000000000..7e7fde86b1d903 --- /dev/null +++ b/patches.renesas/0282-ARM-dts-rskrza1-set-rtc_x1-clock-value.patch @@ -0,0 +1,35 @@ +From e83c05de11bb23d05862dfb54807174a4f242766 Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:34 -0700 +Subject: [PATCH 282/286] ARM: dts: rskrza1: set rtc_x1 clock value + +Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to +non-zero. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit f90c36448aacde1fd41332659a12cbc9558b1137) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100-rskrza1.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts +index 02b59c5b3c53..cab5857bfb41 100644 +--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts ++++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts +@@ -43,6 +43,10 @@ + clock-frequency = <48000000>; + }; + ++&rtc_x1_clk { ++ clock-frequency = <32768>; ++}; ++ + &mtu2 { + status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0283-ARM-dts-rskrza1-add-rtc-DT-support.patch b/patches.renesas/0283-ARM-dts-rskrza1-add-rtc-DT-support.patch new file mode 100644 index 00000000000000..8fec55b4064fb8 --- /dev/null +++ b/patches.renesas/0283-ARM-dts-rskrza1-add-rtc-DT-support.patch @@ -0,0 +1,34 @@ +From 3d7c97d282bc217c0352421a8b64bd849cd5d19d Mon Sep 17 00:00:00 2001 +From: Chris Brandt <chris.brandt@renesas.com> +Date: Wed, 29 Mar 2017 10:30:35 -0700 +Subject: [PATCH 283/286] ARM: dts: rskrza1: add rtc DT support + +Enable the realtime clock. + +Signed-off-by: Chris Brandt <chris.brandt@renesas.com> +Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 931f3dc3f0d14cc7758aa2d48fc2d713f8c6ebff) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100-rskrza1.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts +index cab5857bfb41..72df20a04320 100644 +--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts ++++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts +@@ -73,6 +73,10 @@ + status = "okay"; + }; + ++&rtc { ++ status = "okay"; ++}; ++ + &scif2 { + status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0284-ARM-dts-genmai-Enable-rtc-and-rtc_x1-clock.patch b/patches.renesas/0284-ARM-dts-genmai-Enable-rtc-and-rtc_x1-clock.patch new file mode 100644 index 00000000000000..9fc6ab6c37dd2b --- /dev/null +++ b/patches.renesas/0284-ARM-dts-genmai-Enable-rtc-and-rtc_x1-clock.patch @@ -0,0 +1,45 @@ +From bc7687abec15b47fc5378930962ed6d76a2c2afe Mon Sep 17 00:00:00 2001 +From: Jacopo Mondi <jacopo+renesas@jmondi.org> +Date: Mon, 3 Apr 2017 18:03:18 +0200 +Subject: [PATCH 284/286] ARM: dts: genmai: Enable rtc and rtc_x1 clock + +Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to +non-zero and enable the realtime clock. + +Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit e533a459f07c2b7bcc60121032b3b24d0c58133a) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r7s72100-genmai.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts +index 118a8e2b86bd..52a7b586bac7 100644 +--- a/arch/arm/boot/dts/r7s72100-genmai.dts ++++ b/arch/arm/boot/dts/r7s72100-genmai.dts +@@ -44,6 +44,10 @@ + clock-frequency = <48000000>; + }; + ++&rtc_x1_clk { ++ clock-frequency = <32768>; ++}; ++ + &mtu2 { + status = "okay"; + }; +@@ -59,6 +63,10 @@ + }; + }; + ++&rtc { ++ status = "okay"; ++}; ++ + &scif2 { + status = "okay"; + }; +-- +2.13.3 + diff --git a/patches.renesas/0285-ARM-dts-r8a7790-Drop-_clk-suffix-from-external-CAN-c.patch b/patches.renesas/0285-ARM-dts-r8a7790-Drop-_clk-suffix-from-external-CAN-c.patch new file mode 100644 index 00000000000000..5978c46f6c3739 --- /dev/null +++ b/patches.renesas/0285-ARM-dts-r8a7790-Drop-_clk-suffix-from-external-CAN-c.patch @@ -0,0 +1,34 @@ +From 76e9e6cdc5519a1b16a8a03b8c36daa2b06ab1d6 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 12:08:07 +0200 +Subject: [PATCH 285/286] ARM: dts: r8a7790: Drop _clk suffix from external CAN + clock node name + +The current practice is to not add _clk suffixes to clock node names in +DT, as these names are used as the actual clock names. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit 5b476a9610910a6ac5222bee4ae83a8d41800dbd) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7790.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi +index fe6b8c2a2d71..99269aaca6fc 100644 +--- a/arch/arm/boot/dts/r8a7790.dtsi ++++ b/arch/arm/boot/dts/r8a7790.dtsi +@@ -1101,7 +1101,7 @@ + }; + + /* External CAN clock */ +- can_clk: can_clk { ++ can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ +-- +2.13.3 + diff --git a/patches.renesas/0286-ARM-dts-r8a7791-Drop-_clk-suffix-from-external-CAN-c.patch b/patches.renesas/0286-ARM-dts-r8a7791-Drop-_clk-suffix-from-external-CAN-c.patch new file mode 100644 index 00000000000000..ec8df35e4396b6 --- /dev/null +++ b/patches.renesas/0286-ARM-dts-r8a7791-Drop-_clk-suffix-from-external-CAN-c.patch @@ -0,0 +1,34 @@ +From d2fa736133ef028cd05a34cbf7d6de8a063b5ab0 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven <geert+renesas@glider.be> +Date: Mon, 3 Apr 2017 12:08:08 +0200 +Subject: [PATCH 286/286] ARM: dts: r8a7791: Drop _clk suffix from external CAN + clock node name + +The current practice is to not add _clk suffixes to clock node names in +DT, as these names are used as the actual clock names. + +Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> +Acked-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +(cherry picked from commit eb77d7260c4c25206e2a455be0dbe6443e0856b5) +Signed-off-by: Simon Horman <horms+renesas@verge.net.au> +--- + arch/arm/boot/dts/r8a7791.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi +index 234daf480122..fb405eb16c19 100644 +--- a/arch/arm/boot/dts/r8a7791.dtsi ++++ b/arch/arm/boot/dts/r8a7791.dtsi +@@ -1126,7 +1126,7 @@ + }; + + /* External CAN clock */ +- can_clk: can_clk { ++ can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ +-- +2.13.3 + @@ -576,6 +576,293 @@ patches.renesas/0253-drm-bridge-dw-hdmi-Fix-the-name-of-the-PHY-reset-mac.patch patches.renesas/0254-drm-bridge-dw-hdmi-Assert-SVSRET-before-resetting-th.patch patches.renesas/0255-drm-bridge-dw-hdmi-fix-building-without-CONFIG_OF.patch +patches.renesas/0001-clocksource-em_sti-Split-clock-prepare-and-enable-st.patch +patches.renesas/0002-clocksource-em_sti-Compute-rate-before-registration.patch +patches.renesas/0003-arm64-dts-r8a7796-Add-I2C-for-DVFS-device-node.patch +patches.renesas/0004-arm64-dts-r8a7796-salvator-x-Add-I2C-for-DVFS-device.patch +patches.renesas/0005-arm64-dts-r8a7795-Add-I2C-for-DVFS-core-to-dtsi.patch +patches.renesas/0006-arm64-dts-r8a7795-salvator-x-Enable-I2C-for-DVFS-dev.patch +patches.renesas/0007-arm64-dts-h3ulcb-Update-memory-node-to-4-GiB-map.patch +patches.renesas/0008-arm64-dts-r8a7795-Use-rgmii-txid-phy-mode-for-Ethern.patch +patches.renesas/0009-arm64-dts-r8a7795-salvator-x-Fix-EthernetAVB-PHY-tim.patch +patches.renesas/0010-arm64-dts-h3ulcb-Fix-EthernetAVB-PHY-timing.patch +patches.renesas/0011-arm64-dts-r8a7796-Use-rgmii-txid-phy-mode-for-Ethern.patch +patches.renesas/0012-arm64-dts-r8a7796-salvator-x-Fix-EthernetAVB-PHY-tim.patch +patches.renesas/0013-arm64-defconfig-Enable-SH-Mobile-I2C-controller.patch +patches.renesas/0014-ARM64-defconfig-enable-the-leds-pwm-driver-and-defau.patch +patches.renesas/0015-arm64-dts-r8a7796-dtsi-Add-all-HSCIF-nodes.patch +patches.renesas/0016-arm64-dts-r8a7796-Add-all-SCIF-nodes.patch +patches.renesas/0017-arm64-dts-r8a7796-Enable-SCIF-DMA.patch +patches.renesas/0018-arm64-dts-r8a7796-salvator-x-add-SCIF1-DEBUG1.patch +patches.renesas/0019-arm64-dts-r8a7796-Enable-HSCIF-DMA.patch +patches.renesas/0020-arm64-dts-r8a7795-Add-Cortex-A53-CPU-cores.patch +patches.renesas/0021-arm64-dts-r8a7795-Add-Cortex-A53-PMU-node.patch +patches.renesas/0022-arm64-dts-r8a7795-Upgrade-to-PSCI-v1.0-to-support-Su.patch +patches.renesas/0023-arm64-dts-r8a7796-Upgrade-to-PSCI-v1.0-to-support-Su.patch +patches.renesas/0024-arm64-dts-r8a7795-Remove-unit-addresses-and-regs-fro.patch +patches.renesas/0025-arm64-dts-r8a7796-Remove-unit-address-and-reg-from-i.patch +patches.renesas/0026-arm64-dts-r8a7795-salvator-x-Set-drive-strength-for-.patch +patches.renesas/0027-arm64-dts-r8a7795-Tidyup-Audio-DMAC-channel-for-DVC.patch +patches.renesas/0028-arm64-defconfig-enable-MVNETA.patch +patches.renesas/0029-arm64-defconfig-enable-I2C_PXA.patch +patches.renesas/0030-arm64-dts-r8a7796-Add-Cortex-A57-CPU-cores.patch +patches.renesas/0031-arm64-dts-r8a7796-Add-Cortex-A57-PMU-node.patch +patches.renesas/0032-arm64-dts-r8a7796-Add-CA53-L2-cache-controller-node.patch +patches.renesas/0033-arm64-dts-r8a7796-Add-Cortex-A53-CPU-cores.patch +patches.renesas/0034-arm64-dts-r8a7796-Add-Cortex-A53-PMU-node.patch +patches.renesas/0035-arm64-dts-h3ulcb-Drop-superfluous-status-update-for-.patch +patches.renesas/0036-arm64-dts-r8a7795-salvator-x-Drop-superfluous-status.patch +patches.renesas/0037-arm64-dts-m3ulcb-Drop-superfluous-status-update-for-.patch +patches.renesas/0038-arm64-dts-r8a7796-salvator-x-Drop-superfluous-status.patch +patches.renesas/0039-arm64-set-CONFIG_MMC_BCM2835-y-in-defconfig.patch +patches.renesas/0040-arm64-dts-r8a7795-Correct-SATA-device-size-to-2MiB.patch +patches.renesas/0041-arm64-dts-r8a7795-Add-reset-control-properties.patch +patches.renesas/0042-arm64-dts-r8a7796-Add-reset-control-properties.patch +patches.renesas/0043-arm64-defconfig-Enable-video-DRM-and-LPASS-drivers-f.patch +patches.renesas/0044-arm64-defconfig-enable-MVPP2.patch +patches.renesas/0045-clk-renesas-Add-r8a7795-ES2.0-CPG-Core-Clock-Definit.patch +patches.renesas/0046-arm64-kdump-enable-kdump-in-defconfig.patch +patches.renesas/0047-arm64-dts-r8a7795-salvator-x-Drop-_clk-suffix-from-X.patch +patches.renesas/0048-arm64-defconfig-enable-the-Safexcel-crypto-engine-as.patch +patches.renesas/0049-i2c-rcar-fix-resume-by-always-initializing-registers.patch +patches.renesas/0050-i2c-rcar-clarify-PM-handling-with-more-comments.patch +patches.renesas/0051-i2c-rcar-use-correct-length-when-unmapping-DMA.patch +patches.renesas/0052-ARM-dts-r7s72100-update-sdhi-clock-bindings.patch +patches.renesas/0053-ARM-dts-r8a7743-Fix-SCIFB0-dmas-indentation.patch +patches.renesas/0054-ARM-dts-r8a7745-Fix-SCIFB0-dmas-indentation.patch +patches.renesas/0055-ARM-dts-r8a73a4-Remove-unit-addresses-and-regs-from-.patch +patches.renesas/0056-ARM-dts-r8a7743-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0057-ARM-dts-r8a7745-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0058-ARM-dts-r8a7790-Remove-unit-addresses-and-regs-from-.patch +patches.renesas/0059-ARM-dts-r8a7791-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0060-ARM-dts-r8a7792-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0061-ARM-dts-r8a7793-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0062-ARM-dts-r8a7794-Remove-unit-address-and-reg-from-int.patch +patches.renesas/0063-ARM-dts-r8a7790-Tidyup-Audio-DMAC-channel-for-DVC.patch +patches.renesas/0064-ARM-dts-r7s72100-Add-watchdog-timer.patch +patches.renesas/0065-ARM-dts-r8a73a4-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0066-ARM-dts-r8a7790-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0067-ARM-dts-r8a7791-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0068-ARM-dts-r8a7792-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0069-ARM-dts-r8a7794-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0070-ARM-dts-r8a7791-Tidyup-Audio-DMAC-channel-for-DVC.patch +patches.renesas/0071-ARM-dts-r8a7793-Tidyup-Audio-DMAC-channel-for-DVC.patch +patches.renesas/0072-ARM-dts-r8a7793-Add-INTC-SYS-clock-to-device-tree.patch +patches.renesas/0073-ARM-dts-porter-Always-use-status-okay-to-enable-devi.patch +patches.renesas/0074-ARM-dts-bockw-Drop-superfluous-status-update-for-fre.patch +patches.renesas/0075-ARM-dts-marzen-Drop-superfluous-status-update-for-fr.patch +patches.renesas/0076-ARM-dts-lager-Drop-superfluous-status-update-for-fre.patch +patches.renesas/0077-ARM-dts-koelsch-Drop-superfluous-status-updates-for-.patch +patches.renesas/0078-ARM-dts-porter-Drop-superfluous-status-update-for-fr.patch +patches.renesas/0079-ARM-dts-gose-Drop-superfluous-status-update-for-freq.patch +patches.renesas/0080-ARM-dts-alt-Drop-superfluous-status-update-for-frequ.patch +patches.renesas/0081-ARM-dts-silk-Drop-superfluous-status-update-for-freq.patch +patches.renesas/0082-ARM-shmobile-Document-RZ-G1H-SoC-DT-binding.patch +patches.renesas/0083-ARM-shmobile-Document-RZ-G1N-SoC-DT-binding.patch +patches.renesas/0084-ARM-8660-1-shmobile-r7s72100-Enable-L2-cache.patch +patches.renesas/0085-phy-rcar-gen3-usb2-fix-implementation-for-runtime-PM.patch +patches.renesas/0086-dmaengine-rcar-dmac-enable-descriptor-mode-on-40bit.patch +patches.renesas/0087-rcar-dmac-fixup-descriptor-pointer-for-descriptor-mo.patch +patches.renesas/0088-soc-renesas-Provide-dummy-rcar_rst_read_mode_pins-fo.patch +patches.renesas/0089-ASoC-rsnd-drop-useles-self-assignments.patch +patches.renesas/0090-ASoC-rsnd-check-return-value-of-init-function.patch +patches.renesas/0091-ASoC-rcar-enable-PCM-RATE-untile-192000.patch +patches.renesas/0092-ASoC-rcar-ssi-don-t-set-SSICR.CKDV-000-with-SSIWSR.C.patch +patches.renesas/0093-ASoC-rcar-remove-rsnd_kctrl_remove.patch +patches.renesas/0094-ASoC-rcar-fixup-of_clk_add_provider-usage-for-multi-.patch +patches.renesas/0095-ASoC-rcar-call-missing-of_clk_del_provider-when-remo.patch +patches.renesas/0096-ASoC-rsnd-tidyup-src-convert_rate-reset-timing.patch +patches.renesas/0097-ASoC-rsnd-merge-rsnd_kctrl_new_m-s-e-into-rsnd_kctrl.patch +patches.renesas/0098-ASoC-rsnd-rsnd_mod_make_sure-is-not-under-DEBUG.patch +patches.renesas/0099-ASoC-rsnd-enable-clock-frequency-for-both-44.1kHz-48.patch +patches.renesas/0100-ASoC-rsnd-fix-semicolon.cocci-warnings.patch +patches.renesas/0101-ASoC-rsnd-Fix-possible-NULL-pointer-dereference.patch +patches.renesas/0102-ASoC-rsnd-don-t-use-PDTA-bit-for-24bit-on-SSI.patch +patches.renesas/0103-ASoC-rsnd-don-t-call-free_irq-on-Parent-SSI.patch +patches.renesas/0104-ASoC-rsnd-SSI-PIO-adjust-to-24bit-mode.patch +patches.renesas/0105-ASoC-rsnd-fixup-parent_clk_name-of-AUDIO_CLKOUTx.patch +patches.renesas/0106-soc-renesas-Identify-RZ-G1H.patch +patches.renesas/0107-soc-renesas-Identify-RZ-G1N.patch +patches.renesas/0108-soc-renesas-Register-SoC-device-early.patch +patches.renesas/0109-ata-sata_rcar-Handle-return-value-of-clk_prepare_ena.patch +patches.renesas/0110-clocksource-sh_cmt-Compute-rate-before-registration-.patch +patches.renesas/0111-clockevents-drivers-sh_cmt-Set-min_delta_ticks-and-m.patch +patches.renesas/0112-sh_eth-Use-platform-device-for-printing-before-regis.patch +patches.renesas/0113-sh_eth-Do-not-print-an-error-message-for-probe-defer.patch +patches.renesas/0114-mmc-sh_mmcif-Document-r7s72100-DT-bindings.patch +patches.renesas/0115-media-sh_mobile_ceu_camera-use-module_platform_drive.patch +patches.renesas/0116-mmc-tmio-ensure-end-of-DMA-and-SD-access-are-in-sync.patch +patches.renesas/0117-mmc-host-tmio-use-defines-for-CTL_STOP_INTERNAL_ACTI.patch +patches.renesas/0118-mmc-host-tmio-fix-minor-typos-in-comments.patch +patches.renesas/0119-mmc-host-tmio-don-t-BUG-on-unsupported-stop-commands.patch +patches.renesas/0120-mmc-host-tmio-fill-in-response-from-auto-cmd12.patch +patches.renesas/0121-mmc-tmio-always-unmap-DMA-before-waiting-for-interru.patch +patches.renesas/0122-mmc-tmio-always-get-number-of-taps.patch +patches.renesas/0123-rtc-sh-add-support-for-rza-series.patch +patches.renesas/0124-dt-bindings-rtc-document-the-rtc-sh-bindings.patch +patches.renesas/0125-rtc-sh-mark-PM-functions-as-unused.patch +patches.renesas/0126-serial-sh-sci-Fix-hang-in-sci_reset.patch +patches.renesas/0127-serial-sh-sci-Fix-late-enablement-of-AUTORTS.patch +patches.renesas/0128-serial-sh-sci-Fix-AUTO-RTS-in-sci_init_pins.patch +patches.renesas/0129-clocksource-sh_tmu-Compute-rate-before-registration-.patch +patches.renesas/0130-ASoC-simple-scu-card-use-defined-dev-on-probe.patch +patches.renesas/0131-ASoC-simple-scu-card-add-new-simple_priv_to_card-mac.patch +patches.renesas/0132-smsc911x-Adding-support-for-Micochip-LAN9250-Etherne.patch +patches.renesas/0133-usb-gadget-udc-renesas_usb3-add-USB-ID-signal-monito.patch +patches.renesas/0134-usb-gadget-udc-renesas_usb3-add-extcon-support.patch +patches.renesas/0135-usb-gadget-udc-renesas_usb3-add-support-for-usb-role.patch +patches.renesas/0136-usb-gadget-udc-renesas_usb3-fix-pm_runtime-functions.patch +patches.renesas/0137-usb-gadget-udc-renesas_usb3-fix-deadlock-by-spinlock.patch +patches.renesas/0138-usb-gadget-udc-renesas_usb3-Fix-PN_INT_ENA-disabling.patch +patches.renesas/0139-media-v4l-vsp1-Fix-format-info-documentation.patch +patches.renesas/0140-media-v4l-vsp1-Clean-up-file-handle-in-open-error-pa.patch +patches.renesas/0141-media-v4l-vsp1-Fix-RPF-WPF-U-V-order-in-3-planar-for.patch +patches.renesas/0142-media-v4l-vsp1-Prevent-multiple-streamon-race-commen.patch +patches.renesas/0143-media-v4l-vsp1-Remove-redundant-pipe-dl-usage-from-d.patch +patches.renesas/0144-media-v4l-vsp1-Fix-multi-line-comment-style.patch +patches.renesas/0145-media-v4l-vsp1-Disable-HSV-formats-on-Gen3-hardware.patch +patches.renesas/0146-media-v4l-vsp1-Fix-struct-vsp1_drm-documentation.patch +patches.renesas/0147-media-v4l-vsp1-Register-pipe-with-output-WPF.patch +patches.renesas/0148-media-v4l-vsp1-wpf-Implement-rotation-support.patch +patches.renesas/0149-ASoC-wm8978-Add-OF-device-ID-table.patch +patches.renesas/0150-clk-renesas-r8a7795-Add-IMR-clocks.patch +patches.renesas/0151-clk-renesas-r8a7796-Add-IMR-clocks.patch +patches.renesas/0152-clk-renesas-r8a7795-Correct-parent-clock-and-sort-or.patch +patches.renesas/0153-clk-renesas-r8a7795-Correct-name-of-watchdog-clock.patch +patches.renesas/0154-clk-renesas-r8a7796-Correct-name-of-watchdog-clock.patch +patches.renesas/0155-clk-renesas-r8a7795-Reformat-core-clock-table.patch +patches.renesas/0156-clk-renesas-r8a7796-Reformat-core-clock-table.patch +patches.renesas/0157-clk-renesas-rcar-gen3-cpg-Pass-mode-pins-to-rcar_gen.patch +patches.renesas/0158-clk-renesas-rcar-gen3-Add-workaround-for-PLL0-2-4-er.patch +patches.renesas/0159-clk-renesas-cpg-mssr-Add-support-for-fixing-up-clock.patch +patches.renesas/0160-clk-renesas-r8a7795-Add-support-for-R-Car-H3-ES2.0.patch +patches.renesas/0161-clk-renesas-rcar-gen3-cpg-Add-support-for-RCLK-on-R-.patch +patches.renesas/0162-pinctrl-sh-pfc-r8a7795-Fix-hscif2_clk_b-and-hscif4_c.patch +patches.renesas/0163-pinctrl-sh-pfc-r8a7795-Restore-sort-order.patch +patches.renesas/0164-pinctrl-sh-pfc-Update-info-pointer-after-SoC-specifi.patch +patches.renesas/0165-pinctrl-sh-pfc-r8a7795-Add-support-for-R-Car-H3-ES2..patch +patches.renesas/0166-pinctrl-sh-pfc-r8a7795-Add-SCIF-support.patch +patches.renesas/0167-pinctrl-sh-pfc-r8a7795-Add-SCIF_CLK-support.patch +patches.renesas/0168-pinctrl-sh-pfc-r8a7791-Add-missing-HSCIF1-pinmux-dat.patch +patches.renesas/0169-pinctrl-sh-pfc-r8a7791-Add-missing-DVC_MUTE-signal.patch +patches.renesas/0170-pinctrl-sh-pfc-r8a7791-Fix-SCIF2-pinmux-data.patch +patches.renesas/0171-pinctrl-sh-pfc-r8a7791-Fix-IPSR-comment-typos.patch +patches.renesas/0172-pinctrl-sh-pfc-r8a7794-Swap-ATA-signals.patch +patches.renesas/0173-net-phy-micrel-Restore-led_mode-and-clk_sel-on-resum.patch +patches.renesas/0174-soc-renesas-rcar-sysc-Add-support-for-fixing-up-powe.patch +patches.renesas/0175-soc-renesas-rcar-sysc-Add-support-for-R-Car-H3-ES2.0.patch +patches.renesas/0176-usb-xhci-plat-Enable-async-suspend-resume.patch +patches.renesas/0177-usb-xhci-clear-EINT-bit-in-status-correctly.patch +patches.renesas/0178-usb-xhci-Add-helper-function-xhci_set_power_on.patch +patches.renesas/0179-usb-xhci-Add-helper-function-xhci_disable_slot.patch +patches.renesas/0180-usb-xhci-Expose-xhci_start-function.patch +patches.renesas/0181-usb-xhci-Add-port-test-modes-support-for-usb2.patch +patches.renesas/0182-usb-host-xhci-extract-xhci_slot_state_string.patch +patches.renesas/0183-usb-host-xhci-add-Slot-and-EP-Context-tracers.patch +patches.renesas/0184-usb-host-xhci-fix-up-Control-Transfer-TRB-decoder.patch +patches.renesas/0185-xhci-add-slot-and-endpoint-numbers-to-debug-messages.patch +patches.renesas/0186-xhci-Do-not-halt-the-host-until-both-HCD-have-discon.patch +patches.renesas/0187-xhci-Rework-how-we-handle-unresponsive-or-hoptlug-re.patch +patches.renesas/0188-usb-xhci-add-xhci_log_ring-trace-events.patch +patches.renesas/0189-usb-xhci-remove-xhci_dbg_ep_rings.patch +patches.renesas/0190-usb-xhci-make-several-functions-static.patch +patches.renesas/0191-usb-xhci-remove-error-messages-for-failed-memory-all.patch +patches.renesas/0192-usb-xhci-remove-enq_updates-and-deq_updates-from-rin.patch +patches.renesas/0193-usb-xhci-remove-ring-debugging-code.patch +patches.renesas/0194-usb-xhci-remove-xhci_debug_trb.patch +patches.renesas/0195-usb-xhci-remove-xhci_dbg_ctx.patch +patches.renesas/0196-usb-xhci-fix-link-trb-decoding.patch +patches.renesas/0197-usb-xhci-refine-xhci_decode_trb.patch +patches.renesas/0198-usb-xhci-bInterval-quirk-for-TI-TUSB73x0.patch +patches.renesas/0199-xhci-use-correct-flags-for-spin_lock_irqrestore-when.patch +patches.renesas/0200-usb-host-plat-Enable-xHCI-plat-runtime-PM.patch +patches.renesas/0201-usb-host-xhci-plat-enable-clk-in-resume-timing.patch +patches.renesas/0202-usb-host-xhci-plat-add-resume_quirk.patch +patches.renesas/0203-usb-host-xhci-plat-set-resume_quirk-for-R-Car-contro.patch +patches.renesas/0204-usb-host-xhci-using-correct-specification-chapter-re.patch +patches.renesas/0205-usb-host-xhci-delete-sp_dma_buffers-for-scratchpad.patch +patches.renesas/0206-usb-host-xhci-remove-ifdef-around-PM-functions.patch +patches.renesas/0207-media-v4l-Add-metadata-buffer-type-and-format.patch +patches.renesas/0208-media-v4l-vsp1-Add-histogram-support.patch +patches.renesas/0209-media-v4l-vsp1-Support-histogram-generators-in-pipel.patch +patches.renesas/0210-media-v4l-vsp1-Fix-HGO-and-HGT-routing-register-addr.patch +patches.renesas/0211-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-1.patch +patches.renesas/0212-media-v4l-vsp1-Add-HGO-support.patch +patches.renesas/0213-media-v4l-Define-a-pixel-format-for-the-R-Car-VSP1-2.patch +patches.renesas/0214-media-v4l-vsp1-Add-HGT-support.patch +patches.renesas/0215-media-videodev.h-add-V4L2_CTRL_FLAG_MODIFY_LAYOUT.patch +patches.renesas/0216-media-vsp1-set-V4L2_CTRL_FLAG_MODIFY_LAYOUT-for-hist.patch +patches.renesas/0217-media-pixfmt-meta-vsp1-hgo.rst-remove-spurious.patch +patches.renesas/0218-USB-host-xhci-use-max-port-define.patch +patches.renesas/0219-usb-xhci-trace-URB-before-giving-it-back-instead-of-.patch +patches.renesas/0220-usb-host-xhci-ring-don-t-need-to-clear-interrupt-pen.patch +patches.renesas/0221-USB-xhci-fix-lock-inversion-problem.patch +patches.renesas/0222-xhci-Fix-command-ring-stop-regression-in-4.11.patch +patches.renesas/0223-dt-bindings-net-sms911x-Add-missing-optional-VDD-reg.patch +patches.renesas/0224-net-phy-micrel-configure-intterupts-after-autoneg-wo.patch +patches.renesas/0225-drm-bridge-dw-hdmi-Remove-unused-functions.patch +patches.renesas/0226-drm-bridge-dw-hdmi-Move-CSC-configuration-out-of-PHY.patch +patches.renesas/0227-drm-bridge-dw-hdmi-Enable-CSC-even-for-DVI.patch +patches.renesas/0228-drm-bridge-dw-hdmi-Fix-the-PHY-power-down-sequence.patch +patches.renesas/0229-drm-bridge-dw-hdmi-Fix-the-PHY-power-up-sequence.patch +patches.renesas/0230-drm-bridge-dw-hdmi-Create-PHY-operations.patch +patches.renesas/0231-drm-bridge-dw-hdmi-Add-support-for-custom-PHY-config.patch +patches.renesas/0232-drm-bridge-dw-hdmi-Remove-device-type-from-platform-.patch +patches.renesas/0233-drm-bridge-dw-hdmi-Switch-to-regmap-for-register-acc.patch +patches.renesas/0234-drm-bridge-dw-hdmi-Move-the-driver-to-a-separate-dir.patch +patches.renesas/0235-drm-bridge-dw_hdmi-support-i2c-extended-read-mode.patch +patches.renesas/0236-drm-bridge-dw-hdmi-add-HDMI-vendor-specific-infofram.patch +patches.renesas/0237-drm-dw_hdmi-Don-t-rely-on-the-status-of-the-bridge-f.patch +patches.renesas/0238-dt-bindings-display-renesas-Add-R-Car-Gen3-HDMI-TX-D.patch +patches.renesas/0239-drm-bridge-dw-hdmi-Extract-PHY-interrupt-setup-to-a-.patch +patches.renesas/0240-media-uapi-Add-RGB-and-YUV-bus-formats-for-Synopsys-.patch +patches.renesas/0241-drm-bridge-dw-hdmi-Switch-to-V4L-bus-format-and-enco.patch +patches.renesas/0242-drm-bridge-dw-hdmi-Move-HPD-handling-to-PHY-operatio.patch +patches.renesas/0243-drm-bridge-dw-hdmi-remove-unused-hdmi_bus_fmt_is_yuv.patch +patches.renesas/0244-drm-bridge-dw-hdmi-Add-a-missing-break-statement.patch +patches.renesas/0245-drm-bridge-dw-hdmi-fix-input-format-encoding-from-pl.patch +patches.renesas/0246-drm-dw-hdmi-Implement-the-mode_fixup-drm-helper.patch +patches.renesas/0247-drm-rcar-du-Switch-to-encoder-.atomic_mode_set-helpe.patch +patches.renesas/0248-drm-rcar-du-Don-t-open-code-of_device_get_match_data.patch +patches.renesas/0249-drm-rcar-du-Handle-event-when-disabling-CRTCs.patch +patches.renesas/0250-drm-rcar-du-Clear-handled-event-pointer-in-CRTC-stat.patch +patches.renesas/0251-drm-rcar-du-Use-DRM-core-s-atomic-commit-helper.patch +patches.renesas/0252-drm-rcar-du-Make-sure-the-VSP-is-initialized-on-plat.patch +patches.renesas/0253-drm-rcar-du-Remove-wait-field-from-rcar_du_device-st.patch +patches.renesas/0254-drm-rcar-du-Document-the-vsps-property-in-the-DT-bin.patch +patches.renesas/0255-drm-panel-Constify-device-node-argument-to-of_drm_fi.patch +patches.renesas/0256-drm-rcar-du-Use-the-DRM-panel-API.patch +patches.renesas/0257-drm-Add-data-transmission-order-bus-flag.patch +patches.renesas/0258-drm-rcar-du-Add-support-for-LVDS-mode-selection.patch +patches.renesas/0259-drm-rcar-du-Replace-manual-bridge-implementation-wit.patch +patches.renesas/0260-drm-rcar-du-Hardcode-encoders-types-to-DRM_MODE_ENCO.patch +patches.renesas/0261-drm-rcar-du-Add-Gen3-HDMI-encoder-support.patch +patches.renesas/0262-drm-rcar-du-Skip-disabled-outputs.patch +patches.renesas/0263-drm-rcar-du-Add-DPLL-support.patch +patches.renesas/0264-drm-rcar-du-Add-HDMI-outputs-to-R8A7795-device-descr.patch +patches.renesas/0265-ARM-dts-r8a7743-Add-reset-control-properties.patch +patches.renesas/0266-ARM-dts-r8a7745-Add-reset-control-properties.patch +patches.renesas/0267-ARM-dts-r7s72100-add-power-domains-to-sdhi.patch +patches.renesas/0268-ARM-dts-r8a7794-Add-DU1-clock-to-device-tree.patch +patches.renesas/0269-ARM-dts-r8a7794-Correct-clock-of-DU1.patch +patches.renesas/0270-ARM-dts-alt-Correct-clock-of-DU1.patch +patches.renesas/0271-ARM-dts-silk-Correct-clock-of-DU1.patch +patches.renesas/0272-ARM-dts-r7s72100-fix-ethernet-clock-parent.patch +patches.renesas/0273-ARM-dts-r8a7790-Correct-parent-of-SSI-0-9-clocks.patch +patches.renesas/0274-ARM-dts-r8a7791-Correct-parent-of-SSI-0-9-clocks.patch +patches.renesas/0275-ARM-dts-r8a7793-Correct-parent-of-SSI-0-9-clocks.patch +patches.renesas/0276-ARM-dts-r8a7792-Correct-Z-clock.patch +patches.renesas/0277-ARM-dts-r8a7794-Add-Z2-clock.patch +patches.renesas/0278-ARM-dts-koelsch-Correct-clock-frequency-of-X2-DU-clo.patch +patches.renesas/0279-ARM-dts-r7s72100-add-rtc-clock-to-device-tree.patch +patches.renesas/0280-ARM-dts-r7s72100-add-RTC_X-clock-inputs-to-device-tr.patch +patches.renesas/0281-ARM-dts-r7s72100-add-rtc-to-device-tree.patch +patches.renesas/0282-ARM-dts-rskrza1-set-rtc_x1-clock-value.patch +patches.renesas/0283-ARM-dts-rskrza1-add-rtc-DT-support.patch +patches.renesas/0284-ARM-dts-genmai-Enable-rtc-and-rtc_x1-clock.patch +patches.renesas/0285-ARM-dts-r8a7790-Drop-_clk-suffix-from-external-CAN-c.patch +patches.renesas/0286-ARM-dts-r8a7791-Drop-_clk-suffix-from-external-CAN-c.patch + ############################################################################# # Misc patches |