2.6.32-stable patches

added patches:
	arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch
	arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch

3 files changed, 117 insertions, 0 deletions

diff --git a/queue-2.6.32/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch b/queue-2.6.32/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch
new file mode 100644
index 0000000..84a4fec
--- /dev/null
+++ b/queue-2.6.32/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch
@@ -0,0 +1,58 @@
+From b46c0f74657d1fe1c1b0c1452631cc38a9e6987f Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Tue, 7 Feb 2012 19:42:07 +0100
+Subject: ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR
+
+From: Stephen Boyd <sboyd@codeaurora.org>
+
+commit b46c0f74657d1fe1c1b0c1452631cc38a9e6987f upstream.
+
+armv7's flush_cache_all() flushes caches via set/way. To
+determine the cache attributes (line size, number of sets,
+etc.) the assembly first writes the CSSELR register to select a
+cache level and then reads the CCSIDR register. The CSSELR register
+is banked per-cpu and is used to determine which cache level CCSIDR
+reads. If the task is migrated between when the CSSELR is written and
+the CCSIDR is read the CCSIDR value may be for an unexpected cache
+level (for example L1 instead of L2) and incorrect cache flushing
+could occur.
+
+Disable interrupts across the write and read so that the correct
+cache attributes are read and used for the cache flushing
+routine. We disable interrupts instead of disabling preemption
+because the critical section is only 3 instructions and we want
+to call v7_dcache_flush_all from __v7_setup which doesn't have a
+full kernel stack with a struct thread_info.
+
+This fixes a problem we see in scm_call() when flush_cache_all()
+is called from preemptible context and sometimes the L2 cache is
+not properly flushed out.
+
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Catalin Marinas <catalin.marinas@arm.com>
+Reviewed-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mm/cache-v7.S |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm/mm/cache-v7.S
++++ b/arch/arm/mm/cache-v7.S
+@@ -39,9 +39,15 @@ loop1:
+ 	and	r1, r1, #7			@ mask of the bits for current cache only
+ 	cmp	r1, #2				@ see what cache we have at this level
+ 	blt	skip				@ skip if no cache, or just i-cache
++#ifdef CONFIG_PREEMPT
++	save_and_disable_irqs r9		@ make cssr&csidr read atomic
++#endif
+ 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+ 	isb					@ isb to sych the new cssr&csidr
+ 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
++#ifdef CONFIG_PREEMPT
++	restore_irqs_notrace r9
++#endif
+ 	and	r2, r1, #7			@ extract the length of the cache lines
+ 	add	r2, r2, #4			@ add 4 (line length offset)
+ 	ldr	r4, =0x3ff
diff --git a/queue-2.6.32/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch b/queue-2.6.32/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch
new file mode 100644
index 0000000..765010d
--- /dev/null
+++ b/queue-2.6.32/arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch
@@ -0,0 +1,57 @@
+From 8e43a905dd574f54c5715d978318290ceafbe275 Mon Sep 17 00:00:00 2001
+From: Rabin Vincent <rabin@rab.in>
+Date: Wed, 15 Feb 2012 16:01:42 +0100
+Subject: ARM: 7325/1: fix v7 boot with lockdep enabled
+
+From: Rabin Vincent <rabin@rab.in>
+
+commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream.
+
+Bootup with lockdep enabled has been broken on v7 since b46c0f74657d
+("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").
+
+This is because v7_setup (which is called very early during boot) calls
+v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
+ends up attempting to call into lockdep C code (trace_hardirqs_off())
+when we are in no position to execute it (no stack, MMU off).
+
+Fix this by using a notrace variant of save_and_disable_irqs.  The code
+already uses the notrace variant of restore_irqs.
+
+Reviewed-by: Nicolas Pitre <nico@linaro.org>
+Acked-by: Stephen Boyd <sboyd@codeaurora.org>
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Rabin Vincent <rabin@rab.in>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/include/asm/assembler.h |    5 +++++
+ arch/arm/mm/cache-v7.S           |    2 +-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/include/asm/assembler.h
++++ b/arch/arm/include/asm/assembler.h
+@@ -133,6 +133,11 @@
+ 	disable_irq
+ 	.endm
+ 
++	.macro	save_and_disable_irqs_notrace, oldcpsr
++	mrs	\oldcpsr, cpsr
++	disable_irq_notrace
++	.endm
++
+ /*
+  * Restore interrupt state previously stored in a register.  We don't
+  * guarantee that this will preserve the flags.
+--- a/arch/arm/mm/cache-v7.S
++++ b/arch/arm/mm/cache-v7.S
+@@ -40,7 +40,7 @@ loop1:
+ 	cmp	r1, #2				@ see what cache we have at this level
+ 	blt	skip				@ skip if no cache, or just i-cache
+ #ifdef CONFIG_PREEMPT
+-	save_and_disable_irqs r9		@ make cssr&csidr read atomic
++	save_and_disable_irqs_notrace r9	@ make cssr&csidr read atomic
+ #endif
+ 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+ 	isb					@ isb to sych the new cssr&csidr
diff --git a/queue-2.6.32/series b/queue-2.6.32/series
index 26686e6..ca45e9c 100644
--- a/queue-2.6.32/series
+++ b/queue-2.6.32/series
@@ -15,3 +15,5 @@ crypto-sha512-use-standard-ror64.patch
 drm-radeon-kms-fix-msi-re-arm-on-rv370.patch
 ecryptfs-read-on-a-directory-should-return-eisdir-if-not-supported.patch
 scsi-3w-9xxx-fix-bug-in-sgl-loading.patch
+arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch
+arm-7325-1-fix-v7-boot-with-lockdep-enabled.patch