aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMarc Schink <dev@zapb.de>2020-07-08 15:36:29 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2020-07-26 20:11:28 +0100
commitcf902f7034efd8c9db248b631420838679e9a1ed (patch)
tree90cba66add57591bdb61c31b50bb1512897fb607
parentc1a3f2ce6ba820be302e5f64914a87329afd4a9b (diff)
downloadopenocd-jz4730-cf902f7034efd8c9db248b631420838679e9a1ed.tar.gz
tcl/target: Add initial GigaDevice GD32VF103 support
There is no flash bank support at the moment. Change-Id: I52a2bde39425d94d9333cda002e5df0a1ef63c08 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5755 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-rw-r--r--tcl/target/gd32vf103.cfg26
1 files changed, 26 insertions, 0 deletions
diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg
new file mode 100644
index 000000000..0f4dcf375
--- /dev/null
+++ b/tcl/target/gd32vf103.cfg
@@ -0,0 +1,26 @@
+#
+# GigaDevice GD32VF103 target
+#
+# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
+#
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME gd32vf103
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x800
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0