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authorEric Ruei <e-ruei1@ti.com>2019-03-19 15:59:08 -0400
committerTero Kristo <t-kristo@ti.com>2019-04-01 18:20:12 +0300
commit6755452b7703dcca11c0671d0c94fdb843b55032 (patch)
treefd825e47670d4532ed4694ad0da7a06373868f2e
parente8f16253e48bcaef1e530eb259356df07e53baa8 (diff)
downloadlinux-5.1-rc1-ti-clk.tar.gz
clk: ti: am43xx: drop idlest polling from gfx clkctrl clock5.1-rc1-ti-clk
The GFX modules on AM43xx SoCs have a hardreset line and are controlled by a GFX reset line. Any clkctrl enable/disable operations cannot be checked for module enabled/disabled status independent of the reset operation, and this causes some unwanted timeouts in the kernel and unbalanced states for the GFX clocks. These details should be handled by the driver integration code itself. Add the CLKF_NO_IDLEST flag to the GFX clkctrl clock so that these module status checks are skipped. Signed-off-by: Eric Ruei <e-ruei1@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
-rw-r--r--drivers/clk/ti/clk-43xx-compat.c2
-rw-r--r--drivers/clk/ti/clk-43xx.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c
index 5130398433921..ac8117d371a34 100644
--- a/drivers/clk/ti/clk-43xx-compat.c
+++ b/drivers/clk/ti/clk-43xx-compat.c
@@ -65,7 +65,7 @@ static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
};
static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
- { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
{ 0 },
};
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 2782d91838ac4..9882a9b07950c 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -73,7 +73,7 @@ static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
};
static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
- { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
{ 0 },
};