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| author | James Clark <james.clark@arm.com> | 2022-02-03 11:53:35 +0000 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2022-03-11 10:07:37 +0000 |
| commit | d05bbad0130ff86b802e5cd6acbb6cac23b841b8 (patch) | |
| tree | ec14327672d651073f1185aca7ff50623a15081e | |
| parent | 27caf7e473ef4b9d94a4a7d00e27ce6b24ad1b28 (diff) | |
| download | iio-d05bbad0130ff86b802e5cd6acbb6cac23b841b8.tar.gz | |
coresight: no-op refactor to make INSTP0 check more idiomatic
The spec says this:
P0 tracing support field. The permitted values are:
0b00 Tracing of load and store instructions as P0 elements is not
supported.
0b11 Tracing of load and store instructions as P0 elements is
supported, so TRCCONFIGR.INSTP0 is supported.
All other values are reserved.
The value we are looking for is 0b11 so simplify this. The double read
and && was a bit obfuscated.
Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Clark <james.clark@arm.com>
Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@arm.com
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bf18128cf5ded..e2eebd8652416 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,7 +1091,7 @@ static void etm4_init_arch_data(void *info) etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */ - if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) + if (BMVAL(etmidr0, 1, 2) == 0b11) drvdata->instrp0 = true; else drvdata->instrp0 = false; |