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author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2019-02-25 11:48:38 +0900 |
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committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2019-03-22 20:50:11 +0900 |
commit | 46a818b22337d13555f4500d006eaccaacfcc4ba (patch) | |
tree | eff19e6865e9122d5b9e8177d8c3b053fab1972e | |
parent | 59fcadc987f6bac8f70e330294c6df6dce156c0b (diff) | |
download | renesas-bsp-46a818b22337d13555f4500d006eaccaacfcc4ba.tar.gz |
clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate return value
cpg_sd_clock_round_rate() may return an unsupported clock rate for the
requested clock rate. Therefore, when cpg_sd_clock_set_rate() sets the
clock rate acquired by cpg_sd_clock_round_rate(), an error may occur.
This is not conform the clk API design.
This patch fixes that by making sure cpg_sd_clock_calc_div() considers
only the division values defined in cpg_sd_div_table[].
With this fix, the cpg_sd_clock_round_rate() always return a support
clock rate.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 1655691eb0a69b..d45437dcf5527c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -2,6 +2,7 @@ * R-Car Gen3 Clock Pulse Generator * * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2019 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * @@ -530,8 +531,6 @@ struct sd_clock { const struct sd_div_table *div_table; struct cpg_simple_notifier csn; unsigned int div_num; - unsigned int div_min; - unsigned int div_max; unsigned int cur_div_idx; }; @@ -606,14 +605,20 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock, unsigned long rate, unsigned long parent_rate) { - unsigned int div; - - if (!rate) - rate = 1; + unsigned long calc_rate, best_rate = 0, diff, diff_min = ULONG_MAX; + unsigned int i; - div = DIV_ROUND_CLOSEST(parent_rate, rate); + for (i = 0; i < clock->div_num; i++) { + calc_rate = DIV_ROUND_CLOSEST(parent_rate, + clock->div_table[i].div); + diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate; + if (diff <= diff_min) { + best_rate = calc_rate; + diff_min = diff; + } + } - return clamp_t(unsigned int, div, clock->div_min, clock->div_max); + return DIV_ROUND_CLOSEST(parent_rate, best_rate); } static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, @@ -696,13 +701,6 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, clock->cur_div_idx = i; - clock->div_max = clock->div_table[0].div; - clock->div_min = clock->div_max; - for (i = 1; i < clock->div_num; i++) { - clock->div_max = max(clock->div_max, clock->div_table[i].div); - clock->div_min = min(clock->div_min, clock->div_table[i].div); - } - clk = clk_register(NULL, &clock->hw); if (IS_ERR(clk)) goto free_clock; |