diff options
| author | Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> | 2019-05-22 09:54:53 +0700 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2019-07-11 21:17:12 +0900 |
| commit | 0879b952e2d32b44af82362bb5433b018cec60de (patch) | |
| tree | aae082a6bb185b384f342e21aa478eae4ab40d1a | |
| parent | 45ba0548f01974501c695238a664ee9e555cf2bf (diff) | |
| download | renesas-bsp-0879b952e2d32b44af82362bb5433b018cec60de.tar.gz | |
phy: rcar-gen3-usb2: Correct VBUS behavior at over-current
When VBCTRL.OCCLREN is set, VBCTRL.VBOUT and ADPCTRL.DRVVBUS
are automatically cleared when an over-current occurs.
On OTG channels, clearing these bits will turn off VBUS
so device will appear to be disconnected on the bus.
Clearing VBCTRL.OCCLREN will resolve this issue by retaining VBUS status.
USB port is able to be recovered automatically and the device can be
connected again.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
| -rw-r--r-- | drivers/phy/renesas/phy-rcar-gen3-usb2.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index b4e5c7e144ca8..0d03c5d63afdb 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -1,7 +1,7 @@ /* * Renesas R-Car Gen3 for USB2.0 PHY driver * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2019 Renesas Electronics Corporation * * This is based on the phy-rcar-gen2 driver: * Copyright (C) 2014 Renesas Solutions Corp. @@ -67,6 +67,7 @@ USB2_OBINT_IDDIGCHG) /* VBCTRL */ +#define USB2_VBCTRL_OCCLREN BIT(16) #define USB2_VBCTRL_DRVVBUSSEL BIT(8) /* LINECTRL1 */ @@ -312,11 +313,15 @@ static int rcar_gen3_phy_usb2_init(struct phy *p) { struct rcar_gen3_chan *channel = phy_get_drvdata(p); void __iomem *usb2_base = channel->base; + u32 val; /* Initialize USB2 part */ writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE); writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET); writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET); + val = readl(usb2_base + USB2_VBCTRL); + val &= ~USB2_VBCTRL_OCCLREN; + writel(val, usb2_base + USB2_VBCTRL); /* Initialize otg part */ if (channel->has_otg_pins) |