pci patches

3 files changed, 843 insertions, 1 deletions

diff --git a/pci/kconfigurable-resources-arch-dependent-changes.patch b/pci/kconfigurable-resources-arch-dependent-changes.patch
index fe68f7f93e682..ce47f102eef3d 100644
--- a/pci/kconfigurable-resources-arch-dependent-changes.patch
+++ b/pci/kconfigurable-resources-arch-dependent-changes.patch
@@ -78,7 +78,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
   */
  void pcibios_align_resource(void *data, struct resource *res,
 -			    u64 size, u64 align)
-+			    resource_sz_t size, resource_size_t align)
++			    resource_size_t size, resource_size_t align)
  {
 -	u64 start = res->start;
 +	resource_size_t start = res->start;
diff --git a/pci/pci-64-bit-resource-drivers-mips-changes.patch b/pci/pci-64-bit-resource-drivers-mips-changes.patch
new file mode 100644
index 0000000000000..0d7c21c663afb
--- /dev/null
+++ b/pci/pci-64-bit-resource-drivers-mips-changes.patch
@@ -0,0 +1,781 @@
+From ralf@linux-mips.org Sun Jun  4 15:01:18 2006
+Date: Sun, 4 Jun 2006 23:00:54 +0100
+From: Ralf Baechle <ralf@linux-mips.org>
+To: akpm@osdl.org
+Cc: greg@kroah.com, vgoyal@in.ibm.com
+Subject: PCI: 64 bit resource drivers mips changes
+Message-ID: <20060604220054.GA17873@linux-mips.org>
+Content-Disposition: inline
+
+
+Cc: Vivek Goyal <vgoyal@in.ibm.com>
+Cc: Andrew Morton <akpm@osdl.org>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+
+---
+ arch/mips/au1000/common/pci.c               |   16 +--
+ arch/mips/cobalt/setup.c                    |   41 +++++++--
+ arch/mips/ddb5xxx/ddb5476/setup.c           |   37 ++++++--
+ arch/mips/ite-boards/generic/it8172_setup.c |   74 +++++++++++++---
+ arch/mips/jmr3927/rbhma3100/setup.c         |   59 ++++++++++---
+ arch/mips/pci/ops-it8172.c                  |   34 +++----
+ arch/mips/pci/pci-ddb5074.c                 |   16 +--
+ arch/mips/pci/pci-ddb5476.c                 |   16 +--
+ arch/mips/pci/pci-ddb5477.c                 |   32 +++----
+ arch/mips/pci/pci-jmr3927.c                 |   16 +--
+ arch/mips/pci/pci-ocelot.c                  |    8 -
+ arch/mips/pci/pci-yosemite.c                |   10 +-
+ arch/mips/philips/pnx8550/common/pci.c      |   16 +--
+ arch/mips/philips/pnx8550/common/setup.c    |   25 ++++-
+ arch/mips/sni/setup.c                       |  126 +++++++++++++++++++++++-----
+ arch/mips/tx4938/toshiba_rbtx4938/setup.c   |    5 -
+ 16 files changed, 388 insertions(+), 143 deletions(-)
+
+--- gregkh-2.6.orig/arch/mips/au1000/common/pci.c
++++ gregkh-2.6/arch/mips/au1000/common/pci.c
+@@ -40,17 +40,17 @@
+ 
+ /* TBD */
+ static struct resource pci_io_resource = {
+-	"pci IO space",
+-	(u32)PCI_IO_START,
+-	(u32)PCI_IO_END,
+-	IORESOURCE_IO
++	.start	= PCI_IO_START,
++	.end	= PCI_IO_END,
++	.name	= "PCI IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource = {
+-	"pci memory space",
+-	(u32)PCI_MEM_START,
+-	(u32)PCI_MEM_END,
+-	IORESOURCE_MEM
++	.start	= PCI_MEM_START,
++	.end	= PCI_MEM_END,
++	.name	= "PCI memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops au1x_pci_ops;
+--- gregkh-2.6.orig/arch/mips/cobalt/setup.c
++++ gregkh-2.6/arch/mips/cobalt/setup.c
+@@ -68,19 +68,46 @@ static void __init cobalt_timer_setup(st
+ extern struct pci_ops gt64111_pci_ops;
+ 
+ static struct resource cobalt_mem_resource = {
+-	"PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
++	.start	= GT64111_MEM_BASE,
++	.end	= GT64111_MEM_END,
++	.name	= "PCI memory",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ static struct resource cobalt_io_resource = {
+-	"PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
++	.start	= 0x1000,
++	.end	= 0xffff,
++	.name	= "PCI I/O",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource cobalt_io_resources[] = {
+-	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
+-	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
+-	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
+-	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
+-	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
++	{
++		.start	= 0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x60,
++		.end	= 0x6f,
++		.name	= "keyboard",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	},
+ };
+ 
+ #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
+--- gregkh-2.6.orig/arch/mips/ddb5xxx/ddb5476/setup.c
++++ gregkh-2.6/arch/mips/ddb5xxx/ddb5476/setup.c
+@@ -109,17 +109,42 @@ static struct {
+ 	struct resource dma2;
+ } ddb5476_ioport = {
+ 	{
+-	"dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
+-	"timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
+-	"rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
+-	"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
+-	"dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
++		.start	= 0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x70,
++		.end	= 0x7f,
++		.name	= "rtc",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ static struct {
+ 	struct resource nile4;
+ } ddb5476_iomem = {
+-	{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
++	{
++		.start	= DDB_BASE,
++		.end	= DDB_BASE + DDB_SIZE - 1,
++		.name	= "Nile 4",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ 
+--- gregkh-2.6.orig/arch/mips/ite-boards/generic/it8172_setup.c
++++ gregkh-2.6/arch/mips/ite-boards/generic/it8172_setup.c
+@@ -72,11 +72,29 @@ struct {
+     struct resource flash;
+     struct resource boot;
+ } it8172_resources = {
+-    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
+-    { "PCI Mem",       0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
+-    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
+-    { "Flash",         0x08000000, 0x0CFFFFFF                 },
+-    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
++	{
++		.start	= 0,				/* to be initted */
++		.end	= 0,
++		.name	= "RAM",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "PCI Mem",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x17FFFFFF
++		.name	= "PCI I/O",
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x0CFFFFFF
++		.name	= "Flash",
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF
++		.name	= "Boot ROM",
++	}
+ };
+ #else
+ struct {
+@@ -89,14 +107,44 @@ struct {
+     struct resource flash;
+     struct resource boot;
+ } it8172_resources = {
+-    { "RAM",           0,          0,          IORESOURCE_MEM }, /* to be initted */
+-    { "PCI Mem0",      0x0C000000, 0x0FFFFFFF, IORESOURCE_MEM },
+-    { "PCI Mem1",      0x10000000, 0x13FFFFFF, IORESOURCE_MEM },
+-    { "PCI I/O",       0x14000000, 0x17FFFFFF                 },
+-    { "PCI Mem2",      0x1A000000, 0x1BFFFFFF, IORESOURCE_MEM },
+-    { "PCI Mem3",      0x1C000000, 0x1FBFFFFF, IORESOURCE_MEM },
+-    { "Flash",         0x08000000, 0x0CFFFFFF                 },
+-    { "Boot ROM",      0x1FC00000, 0x1FFFFFFF                 }
++	{
++		.start	= 0,				/* to be initted */
++		.end	= 0,
++		.name	= "RAM",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x0C000000,
++		.end	= 0x0FFFFFFF,
++		.name	= "PCI Mem0",
++		.flags	= IORESOURCE_MEM
++	 }, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "PCI Mem1",
++		.flags	= IORESOURCE_MEM
++	 }, {
++		.start	= 0x14000000,
++		.end	= 0x17FFFFFF
++		.name	= "PCI I/O",
++	}, {
++		.start	= 0x1A000000,
++		.end	= 0x1BFFFFFF,
++		.name	= "PCI Mem2",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x1C000000,
++		.end	= 0x1FBFFFFF,
++		.name	= "PCI Mem3",
++		.flags	= IORESOURCE_MEM
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x0CFFFFFF
++		.name	= "Flash",
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF
++		.name	= "Boot ROM",
++	}
+ };
+ #endif
+ 
+--- gregkh-2.6.orig/arch/mips/jmr3927/rbhma3100/setup.c
++++ gregkh-2.6/arch/mips/jmr3927/rbhma3100/setup.c
+@@ -82,17 +82,54 @@ struct {
+     struct resource sio0;
+     struct resource sio1;
+ } jmr3927_resources = {
+-    { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
+-    { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
+-    { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
+-    { "IOB",           0x10000000, 0x13FFFFFF                  },
+-    { "IOC",           0x14000000, 0x14FFFFFF                  },
+-    { "PCIIO",         0x15000000, 0x15FFFFFF                  },
+-    { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
+-    { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
+-    { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
+-    { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
+-    { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
++	{
++		.start	= 0,
++		.end	= 0x01FFFFFF,
++		.name	= "RAM0",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x02000000,
++		.end	= 0x03FFFFFF,
++		.name	= "RAM1",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x08000000,
++		.end	= 0x07FFFFFF,
++		.name	= "PCIMEM",
++		.flags = IORESOURCE_MEM
++	}, {
++		.start	= 0x10000000,
++		.end	= 0x13FFFFFF,
++		.name	= "IOB"
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x14FFFFFF,
++		.name	= "IOC"
++	}, {
++		.start	= 0x15000000,
++		.end	= 0x15FFFFFF,
++		.name	= "PCIIO"
++	}, {
++		.start	= 0x1D000000,
++		.end	= 0x1D3FFFFF,
++		.name	= "JMY1394"
++	}, {
++		.start	= 0x1E000000,
++		.end	= 0x1E3FFFFF,
++		.name	= "ROM1"
++	}, {
++		.start	= 0x1FC00000,
++		.end	= 0x1FFFFFFF,
++		.name	= "ROM0"
++	}, {
++		.start	= 0xFFFEF300,
++		.end	= 0xFFFEF3FF,
++		.name	= "SIO0"
++	}, {
++		.start	= 0xFFFEF400,
++		.end	= 0xFFFEF4FF,
++		.name	= "SIO1"
++	},
+ };
+ 
+ /* don't enable - see errata */
+--- gregkh-2.6.orig/arch/mips/pci/ops-it8172.c
++++ gregkh-2.6/arch/mips/pci/ops-it8172.c
+@@ -50,30 +50,28 @@
+ static struct resource pci_mem_resource_1;
+ 
+ static struct resource pci_io_resource = {
+-	"io pci IO space",
+-	0x14018000,
+-	0x17FFFFFF,
+-	IORESOURCE_IO
++	.start	= 0x14018000,
++	.end	= 0x17FFFFFF,
++	.name	= "io pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource_0 = {
+-	"ext pci memory space 0/1",
+-	0x10101000,
+-	0x13FFFFFF,
+-	IORESOURCE_MEM,
+-	&pci_mem_resource_0,
+-	NULL,
+-	&pci_mem_resource_1
++	.start	= 0x10101000,
++	.end	= 0x13FFFFFF,
++	.name	= "ext pci memory space 0/1",
++	.flags	= IORESOURCE_MEM,
++	.parent	= &pci_mem_resource_0,
++	.sibling = NULL,
++	.child	= &pci_mem_resource_1
+ };
+ 
+ static struct resource pci_mem_resource_1 = {
+-	"ext pci memory space 2/3",
+-	0x1A000000,
+-	0x1FBFFFFF,
+-	IORESOURCE_MEM,
+-	&pci_mem_resource_0,
+-	NULL,
+-	NULL
++	.start	= 0x1A000000,
++	.end	= 0x1FBFFFFF,
++	.name	= "ext pci memory space 2/3",
++	.flags	= IORESOURCE_MEM,
++	.parent	= &pci_mem_resource_0
+ };
+ 
+ extern struct pci_ops it8172_pci_ops;
+--- gregkh-2.6.orig/arch/mips/pci/pci-ddb5074.c
++++ gregkh-2.6/arch/mips/pci/pci-ddb5074.c
+@@ -8,17 +8,17 @@
+ #include <asm/ddb5xxx/ddb5xxx.h>
+ 
+ static struct resource extpci_io_resource = {
+-	"pci IO space",
+-	0x1000,			/* leave some room for ISA bus */
+-	DDB_PCI_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= 0x1000,		/* leave some room for ISA bus */
++	.end	= DDB_PCI_IO_SIZE - 1,
++	.name	= "pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource extpci_mem_resource = {
+-	"pci memory space",
+-	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
+-	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
++	.end	= DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
++	.name	= "pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops ddb5476_ext_pci_ops;
+--- gregkh-2.6.orig/arch/mips/pci/pci-ddb5476.c
++++ gregkh-2.6/arch/mips/pci/pci-ddb5476.c
+@@ -8,17 +8,17 @@
+ #include <asm/ddb5xxx/ddb5xxx.h>
+ 
+ static struct resource extpci_io_resource = {
+-	"pci IO space",
+-	0x1000,			/* leave some room for ISA bus */
+-	DDB_PCI_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= 0x1000,		/* leave some room for ISA bus */
++	.end	= DDB_PCI_IO_SIZE - 1,
++	.name	= "pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource extpci_mem_resource = {
+-	"pci memory space",
+-	DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
+-	DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI_MEM_BASE + 0x00100000,	/* leave 1 MB for RTC */
++	.end	= DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
++	.name	= "pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops ddb5476_ext_pci_ops;
+--- gregkh-2.6.orig/arch/mips/pci/pci-ddb5477.c
++++ gregkh-2.6/arch/mips/pci/pci-ddb5477.c
+@@ -22,31 +22,31 @@
+ #include <asm/ddb5xxx/ddb5xxx.h>
+ 
+ static struct resource extpci_io_resource = {
+-	"ext pci IO space",
+-	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
+-	DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000,
++	.end	= DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1,
++	.name	= "ext pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource extpci_mem_resource = {
+-	"ext pci memory space",
+-	DDB_PCI0_MEM_BASE + 0x100000,
+-	DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI0_MEM_BASE + 0x100000,
++	.end	= DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1,
++	.name	= "ext pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ static struct resource iopci_io_resource = {
+-	"io pci IO space",
+-	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
+-	DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
+-	IORESOURCE_IO
++	.start	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
++	.end	= DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1,
++	.name	= "io pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource iopci_mem_resource = {
+-	"ext pci memory space",
+-	DDB_PCI1_MEM_BASE,
+-	DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.start	= DDB_PCI1_MEM_BASE,
++	.end	= DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1,
++	.name	= "ext pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops ddb5477_ext_pci_ops;
+--- gregkh-2.6.orig/arch/mips/pci/pci-jmr3927.c
++++ gregkh-2.6/arch/mips/pci/pci-jmr3927.c
+@@ -35,17 +35,17 @@
+ #include <asm/debug.h>
+ 
+ struct resource pci_io_resource = {
+-	"IO MEM",
+-	0x1000,			/* reserve regacy I/O space */
+-	0x1000 + JMR3927_PCIIO_SIZE - 1,
+-	IORESOURCE_IO
++	.name	= "IO MEM",
++	.start	= 0x1000,			/* reserve regacy I/O space */
++	.end	= 0x1000 + JMR3927_PCIIO_SIZE - 1,
++	.flags	= IORESOURCE_IO
+ };
+ 
+ struct resource pci_mem_resource = {
+-	"PCI MEM",
+-	JMR3927_PCIMEM,
+-	JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
+-	IORESOURCE_MEM
++	.name	= "PCI MEM",
++	.start	= JMR3927_PCIMEM,
++	.end	= JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops jmr3927_pci_ops;
+--- gregkh-2.6.orig/arch/mips/pci/pci-ocelot.c
++++ gregkh-2.6/arch/mips/pci/pci-ocelot.c
+@@ -71,13 +71,13 @@ static inline void pci0WriteConfigReg(un
+ }
+ 
+ static struct resource ocelot_mem_resource = {
+-	iomem_resource.start = GT_PCI_MEM_BASE;
+-	iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
++	start	= GT_PCI_MEM_BASE;
++	end	= GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1;
+ };
+ 
+ static struct resource ocelot_io_resource = {
+-	ioport_resource.start = GT_PCI_IO_BASE;
+-	ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
++	start	= GT_PCI_IO_BASE;
++	end	= GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1;
+ };
+ 
+ static struct pci_controller ocelot_pci_controller = {
+--- gregkh-2.6.orig/arch/mips/pci/pci-yosemite.c
++++ gregkh-2.6/arch/mips/pci/pci-yosemite.c
+@@ -14,7 +14,10 @@
+ extern struct pci_ops titan_pci_ops;
+ 
+ static struct resource py_mem_resource = {
+-	"Titan PCI MEM", 0xe0000000UL, 0xe3ffffffUL, IORESOURCE_MEM
++	.start	= 0xe0000000UL,
++	.end	= 0xe3ffffffUL,
++	.name	= "Titan PCI MEM",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ /*
+@@ -26,7 +29,10 @@ static struct resource py_mem_resource =
+ #define TITAN_IO_BASE	0xe8000000UL
+ 
+ static struct resource py_io_resource = {
+-	"Titan IO MEM", 0x00001000UL, TITAN_IO_SIZE - 1, IORESOURCE_IO,
++	.start	= 0x00001000UL,
++	.end	= TITAN_IO_SIZE - 1,
++	.name	= "Titan IO MEM",
++	.flags	= IORESOURCE_IO,
+ };
+ 
+ static struct pci_controller py_controller = {
+--- gregkh-2.6.orig/arch/mips/philips/pnx8550/common/pci.c
++++ gregkh-2.6/arch/mips/philips/pnx8550/common/pci.c
+@@ -27,17 +27,17 @@
+ #include <nand.h>
+ 
+ static struct resource pci_io_resource = {
+-	"pci IO space",
+-	(u32)(PNX8550_PCIIO + 0x1000),	/* reserve regacy I/O space */
+-	(u32)(PNX8550_PCIIO + PNX8550_PCIIO_SIZE),
+-	IORESOURCE_IO
++	.start	= PNX8550_PCIIO + 0x1000,	/* reserve regacy I/O space */
++	.end	= PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
++	.name	= "pci IO space",
++	.flags	= IORESOURCE_IO
+ };
+ 
+ static struct resource pci_mem_resource = {
+-	"pci memory space",
+-	(u32)(PNX8550_PCIMEM),
+-	(u32)(PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1),
+-	IORESOURCE_MEM
++	.start	= PNX8550_PCIMEM,
++	.end	= PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
++	.name	= "pci memory space",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ extern struct pci_ops pnx8550_pci_ops;
+--- gregkh-2.6.orig/arch/mips/philips/pnx8550/common/setup.c
++++ gregkh-2.6/arch/mips/philips/pnx8550/common/setup.c
+@@ -58,10 +58,27 @@ extern void prom_printf(char *fmt, ...);
+ extern char *prom_getcmdline(void);
+ 
+ struct resource standard_io_resources[] = {
+-	{"dma1", 0x00, 0x1f, IORESOURCE_BUSY},
+-	{"timer", 0x40, 0x5f, IORESOURCE_BUSY},
+-	{"dma page reg", 0x80, 0x8f, IORESOURCE_BUSY},
+-	{"dma2", 0xc0, 0xdf, IORESOURCE_BUSY},
++	{
++		.start	= .0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	},
+ };
+ 
+ #define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
+--- gregkh-2.6.orig/arch/mips/sni/setup.c
++++ gregkh-2.6/arch/mips/sni/setup.c
+@@ -92,20 +92,51 @@ static void __init sni_display_setup(voi
+ }
+ 
+ static struct resource sni_io_resource = {
+-	"PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO,
++	.start	= 0x00001000UL,
++	.end	= 0x03bfffffUL,
++	.name	= "PCIMT IO MEM",
++	.flags	= IORESOURCE_IO,
+ };
+ 
+ static struct resource pcimt_io_resources[] = {
+-	{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
+-	{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
+-	{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
+-	{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
+-	{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
+-	{ "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY }
++	{
++		.start	= 0x00,
++		.end	= 0x1f,
++		.name	= "dma1",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x40,
++		.end	= 0x5f,
++		.name	= "timer",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x60,
++		.end	= 0x6f,
++		.name	= "keyboard",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0x80,
++		.end	= 0x8f,
++		.name	= "dma page reg",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0xc0,
++		.end	= 0xdf,
++		.name	= "dma2",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	=  0xcfc,
++		.end	= 0xcff,
++		.name	= "PCI config data",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ static struct resource sni_mem_resource = {
+-	"PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM
++	.start	= 0x10000000UL,
++	.end	= 0xffffffffUL,
++	.name	= "PCIMT PCI MEM",
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ /*
+@@ -122,19 +153,72 @@ static struct resource sni_mem_resource 
+  * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
+  */
+ static struct resource pcimt_mem_resources[] = {
+-	{ "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY },
+-	{ "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY },
+-	{ "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY },
+-	{ "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY},
+-	{ "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY },
+-	{ "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY},
+-	{ "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY},
+-	{ "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY},
+-	{ "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY},
+-	{ "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY},
+-	{ "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY},
+-	{ "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY},
+-	{ "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY}
++	{
++		.start	= 0x100a0000,
++		.end	= 0x100bffff,
++		.name	= "Video RAM area",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x100c0000,
++		.end	= 0x100fffff,
++		.name	= "ISA Reserved",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x14000000,
++		.end	= 0x17bfffff,
++		.name	= "PCI IO",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x17c00000,
++		.end	= 0x17ffffff,
++		.name	= "Cache Replacement Area",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1a000000,
++		.end	= 0x1a000003,
++		.name	= "PCI INT Acknowledge",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fc00000,
++		.end	= 0x1fc7ffff,
++		.name	= "Boot PROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fc80000,
++		.end	= 0x1fcfffff,
++		.name	= "Diag PROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fd00000,
++		.end	= 0x1fdfffff,
++		.name	= "X-Bus",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fe00000,
++		.end	= 0x1fefffff,
++		.name	= "BIOS map",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1ff00000,
++		.end	= 0x1ff7ffff,
++		.name	= "NVRAM / EEPROM",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1fff0000,
++		.end	= 0x1fffefff,
++		.name	= "ASIC PCI",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x1ffff000,
++		.end	= 0x1fffffff,
++		.name	= "MP Agent",
++		.flags	= IORESOURCE_BUSY
++	}, {
++		.start	= 0x20000000,
++		.end	= 0x9fffffff,
++		.name	= "Main Memory",
++		.flags	= IORESOURCE_BUSY
++	}
+ };
+ 
+ static void __init sni_resource_init(void)
+--- gregkh-2.6.orig/arch/mips/tx4938/toshiba_rbtx4938/setup.c
++++ gregkh-2.6/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+@@ -664,7 +664,10 @@ static struct resource rbtx4938_fpga_res
+ 
+ static char pcode_str[8];
+ static struct resource tx4938_reg_resource = {
+-	pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
++	.start	= TX4938_REG_BASE,
++	.end	= TX4938_REG_BASE + TX4938_REG_SIZE,
++	.name	= pcode_str,
++	.flags	= IORESOURCE_MEM
+ };
+ 
+ void __init tx4938_board_setup(void)
diff --git a/pci/pci-msi-k8t-neo2-fir-run-only-where-needed.patch b/pci/pci-msi-k8t-neo2-fir-run-only-where-needed.patch
new file mode 100644
index 0000000000000..984d6ad673db8
--- /dev/null
+++ b/pci/pci-msi-k8t-neo2-fir-run-only-where-needed.patch
@@ -0,0 +1,61 @@
+From akpm@osdl.org Mon Jun  5 00:13:26 2006
+Message-Id: <200606050713.k557DLt9003979@shell0.pdx.osdl.net>
+Subject: PCI: MSI-K8T-Neo2-Fir: run only where needed
+To: cw@f00f.org, greg@kroah.com, mm-commits@vger.kernel.org
+From: akpm@osdl.org
+Date: Mon, 05 Jun 2006 00:13:21 -0700
+
+From: Chris Wedgwood <cw@f00f.org>
+
+Be more selective when running the MSI-K8T-Neo2Fir soundcard PCI quirk so
+as not to run this on hardware where it's probably not needed.
+
+Signed-off-by: Chris Wedgwood <cw@f00f.org>
+Signed-off-by: Andrew Morton <akpm@osdl.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+
+---
+ drivers/pci/quirks.c |   17 ++++++++++-------
+ 1 file changed, 10 insertions(+), 7 deletions(-)
+
+--- gregkh-2.6.orig/drivers/pci/quirks.c
++++ gregkh-2.6/drivers/pci/quirks.c
+@@ -889,27 +889,30 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+  * when a PCI-Soundcard is added. The BIOS only gives Options
+  * "Disabled" and "AUTO". This Quirk Sets the corresponding
+  * Register-Value to enable the Soundcard.
++ *
++ * FIXME: Presently this quirk will run on anything that has an 8237
++ * which isn't correct, we need to check DMI tables or something in
++ * order to make sure it only runs on the MSI-K8T-Neo2Fir.  Because it
++ * runs everywhere at present we suppress the printk output in most
++ * irrelevant cases.
+  */
+ static void __init k8t_sound_hostbridge(struct pci_dev *dev)
+ {
+ 	unsigned char val;
+ 
+-	printk(KERN_INFO "PCI: Quirk-MSI-K8T Soundcard On\n");
+ 	pci_read_config_byte(dev, 0x50, &val);
+ 	if (val == 0x88 || val == 0xc8) {
++		/* Assume it's probably a MSI-K8T-Neo2Fir */
++		printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
+ 		pci_write_config_byte(dev, 0x50, val & (~0x40));
+ 
+ 		/* Verify the Change for Status output */
+ 		pci_read_config_byte(dev, 0x50, &val);
+ 		if (val & 0x40)
+-			printk(KERN_INFO "PCI: MSI-K8T soundcard still off\n");
++			printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
+ 		else
+-			printk(KERN_INFO "PCI: MSI-K8T soundcard on\n");
+-	} else {
+-		printk(KERN_INFO "PCI: Unexpected Value in PCI-Register: "
+-					"no Change!\n");
++			printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
+ 	}
+-
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
+