diff options
author | Greg Kroah-Hartman <gregkh@suse.de> | 2006-03-22 15:26:10 -0800 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2006-03-22 15:26:10 -0800 |
commit | 921b2c7212fc06e61c3c9c70c58824567ad4facb (patch) | |
tree | 5b2882f3fe8499786bfbe58f80e78756888c315f /pci | |
parent | 126e1f3979f9316caba05c0ae9aa59c7a8e97363 (diff) | |
download | patches-921b2c7212fc06e61c3c9c70c58824567ad4facb.tar.gz |
removed pci msi patches (have been resent), and refreshed stuff based on this removal
Diffstat (limited to 'pci')
-rw-r--r-- | pci/altix-msi-support.patch | 982 | ||||
-rw-r--r-- | pci/i386-pci-ordering.patch | 35 | ||||
-rw-r--r-- | pci/msi-vector-targeting-abstractions.patch | 695 | ||||
-rw-r--r-- | pci/pci-clean-up-msi.c-a-bit.patch | 40 | ||||
-rw-r--r-- | pci/pci-fix-msi-build-breakage-in-x86_64.patch | 47 | ||||
-rw-r--r-- | pci/pci-fix-problems-with-msi-x-on-ia64.patch | 16 | ||||
-rw-r--r-- | pci/pci-make-msi-quirk-inheritable-from-the-pci-bus.patch | 2 | ||||
-rw-r--r-- | pci/pci-msi-save-restore-for-suspend-resume.patch | 63 | ||||
-rw-r--r-- | pci/pci-provide-a-boot-parameter-to-disable-msi.patch | 11 | ||||
-rw-r--r-- | pci/pci-the-scheduled-removal-of-pci_legacy_proc.patch | 2 | ||||
-rw-r--r-- | pci/per-platform-ia64_-first-last-_device_vector-definitions.patch | 153 |
11 files changed, 53 insertions, 1993 deletions
diff --git a/pci/altix-msi-support.patch b/pci/altix-msi-support.patch deleted file mode 100644 index fd92f3340f3ee..0000000000000 --- a/pci/altix-msi-support.patch +++ /dev/null @@ -1,982 +0,0 @@ -From owner-linux-pci@atrey.karlin.mff.cuni.cz Thu Jan 19 11:47:09 2006 -Date: Thu, 19 Jan 2006 13:47:02 -0600 (CST) -From: Mark Maule <maule@sgi.com> -Cc: Tony Luck <tony.luck@intel.com>, gregkh@suse.de, Mark Maule <maule@sgi.com> -Message-Id: <20060119194702.12213.16524.93275@lnx-maule.americas.sgi.com> -Subject: [PATCH 3/3] altix: msi support - -MSI callouts for altix. Involves a fair amount of code reorg in sn irq.c -code as well as adding some extensions to the altix PCI provider abstaction. - -Signed-off-by: Mark Maule <maule@sgi.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> - ---- - arch/ia64/sn/kernel/io_init.c | 2 - arch/ia64/sn/kernel/irq.c | 143 +++++++++++--------- - arch/ia64/sn/pci/msi.c | 200 ++++++++++++++++++++++++++++- - arch/ia64/sn/pci/pci_dma.c | 10 - - arch/ia64/sn/pci/pcibr/pcibr_dma.c | 62 ++++++-- - arch/ia64/sn/pci/tioca_provider.c | 8 + - arch/ia64/sn/pci/tioce_provider.c | 65 ++++++--- - include/asm-ia64/sn/intr.h | 8 + - include/asm-ia64/sn/pcibr_provider.h | 5 - include/asm-ia64/sn/pcibus_provider_defs.h | 17 ++ - include/asm-ia64/sn/tiocp.h | 3 - 11 files changed, 405 insertions(+), 118 deletions(-) - ---- gregkh-2.6.orig/arch/ia64/sn/kernel/io_init.c -+++ gregkh-2.6/arch/ia64/sn/kernel/io_init.c -@@ -56,7 +56,7 @@ static int max_pcibus_number = 255; /* D - */ - - static dma_addr_t --sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size) -+sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size, int type) - { - return 0; - } ---- gregkh-2.6.orig/arch/ia64/sn/kernel/irq.c -+++ gregkh-2.6/arch/ia64/sn/kernel/irq.c -@@ -26,11 +26,11 @@ static void unregister_intr_pda(struct s - - int sn_force_interrupt_flag = 1; - extern int sn_ioif_inited; --static struct list_head **sn_irq_lh; -+struct list_head **sn_irq_lh; - static spinlock_t sn_irq_info_lock = SPIN_LOCK_UNLOCKED; /* non-IRQ lock */ - --static inline u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, -- u64 sn_irq_info, -+u64 sn_intr_alloc(nasid_t local_nasid, int local_widget, -+ struct sn_irq_info *sn_irq_info, - int req_irq, nasid_t req_nasid, - int req_slice) - { -@@ -40,12 +40,13 @@ static inline u64 sn_intr_alloc(nasid_t - - SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT, - (u64) SAL_INTR_ALLOC, (u64) local_nasid, -- (u64) local_widget, (u64) sn_irq_info, (u64) req_irq, -+ (u64) local_widget, __pa(sn_irq_info), (u64) req_irq, - (u64) req_nasid, (u64) req_slice); -+ - return ret_stuff.status; - } - --static inline void sn_intr_free(nasid_t local_nasid, int local_widget, -+void sn_intr_free(nasid_t local_nasid, int local_widget, - struct sn_irq_info *sn_irq_info) - { - struct ia64_sal_retval ret_stuff; -@@ -112,73 +113,91 @@ static void sn_end_irq(unsigned int irq) - - static void sn_irq_info_free(struct rcu_head *head); - --static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) -+struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info, -+ nasid_t nasid, int slice) - { -- struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; -- int cpuid, cpuphys; -+ int vector; -+ int cpuphys; -+ int64_t bridge; -+ int local_widget, status; -+ nasid_t local_nasid; -+ struct sn_irq_info *new_irq_info; -+ struct sn_pcibus_provider *pci_provider; - -- cpuid = first_cpu(mask); -- cpuphys = cpu_physical_id(cpuid); -+ new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); -+ if (new_irq_info == NULL) -+ return NULL; - -- list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, -- sn_irq_lh[irq], list) { -- u64 bridge; -- int local_widget, status; -- nasid_t local_nasid; -- struct sn_irq_info *new_irq_info; -- struct sn_pcibus_provider *pci_provider; -- -- new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC); -- if (new_irq_info == NULL) -- break; -- memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); -- -- bridge = (u64) new_irq_info->irq_bridge; -- if (!bridge) { -- kfree(new_irq_info); -- break; /* irq is not a device interrupt */ -- } -+ memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info)); - -- local_nasid = NASID_GET(bridge); -+ bridge = (u64) new_irq_info->irq_bridge; -+ if (!bridge) { -+ kfree(new_irq_info); -+ return NULL; /* irq is not a device interrupt */ -+ } - -- if (local_nasid & 1) -- local_widget = TIO_SWIN_WIDGETNUM(bridge); -- else -- local_widget = SWIN_WIDGETNUM(bridge); -- -- /* Free the old PROM new_irq_info structure */ -- sn_intr_free(local_nasid, local_widget, new_irq_info); -- /* Update kernels new_irq_info with new target info */ -- unregister_intr_pda(new_irq_info); -- -- /* allocate a new PROM new_irq_info struct */ -- status = sn_intr_alloc(local_nasid, local_widget, -- __pa(new_irq_info), irq, -- cpuid_to_nasid(cpuid), -- cpuid_to_slice(cpuid)); -- -- /* SAL call failed */ -- if (status) { -- kfree(new_irq_info); -- break; -- } -+ local_nasid = NASID_GET(bridge); -+ -+ if (local_nasid & 1) -+ local_widget = TIO_SWIN_WIDGETNUM(bridge); -+ else -+ local_widget = SWIN_WIDGETNUM(bridge); -+ -+ vector = sn_irq_info->irq_irq; -+ /* Free the old PROM new_irq_info structure */ -+ sn_intr_free(local_nasid, local_widget, new_irq_info); -+ /* Update kernels new_irq_info with new target info */ -+ unregister_intr_pda(new_irq_info); -+ -+ /* allocate a new PROM new_irq_info struct */ -+ status = sn_intr_alloc(local_nasid, local_widget, -+ new_irq_info, vector, -+ nasid, slice); -+ -+ /* SAL call failed */ -+ if (status) { -+ kfree(new_irq_info); -+ return NULL; -+ } -+ -+ cpuphys = nasid_slice_to_cpuid(nasid, slice); -+ new_irq_info->irq_cpuid = cpuphys; -+ register_intr_pda(new_irq_info); -+ -+ pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type]; - -- new_irq_info->irq_cpuid = cpuid; -- register_intr_pda(new_irq_info); -+ /* -+ * If this represents a line interrupt, target it. If it's -+ * an msi (irq_int_bit < 0), it's already targeted. -+ */ -+ if (new_irq_info->irq_int_bit >= 0 && -+ pci_provider && pci_provider->target_interrupt) -+ (pci_provider->target_interrupt)(new_irq_info); - -- pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type]; -- if (pci_provider && pci_provider->target_interrupt) -- (pci_provider->target_interrupt)(new_irq_info); -- -- spin_lock(&sn_irq_info_lock); -- list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); -- spin_unlock(&sn_irq_info_lock); -- call_rcu(&sn_irq_info->rcu, sn_irq_info_free); -+ spin_lock(&sn_irq_info_lock); -+ list_replace_rcu(&sn_irq_info->list, &new_irq_info->list); -+ spin_unlock(&sn_irq_info_lock); -+ call_rcu(&sn_irq_info->rcu, sn_irq_info_free); - - #ifdef CONFIG_SMP -- set_irq_affinity_info((irq & 0xff), cpuphys, 0); -+ set_irq_affinity_info((vector & 0xff), cpuphys, 0); - #endif -- } -+ -+ return new_irq_info; -+} -+ -+static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask) -+{ -+ struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; -+ nasid_t nasid; -+ int slice; -+ -+ nasid = cpuid_to_nasid(first_cpu(mask)); -+ slice = cpuid_to_slice(first_cpu(mask)); -+ -+ list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe, -+ sn_irq_lh[irq], list) -+ (void)sn_retarget_vector(sn_irq_info, nasid, slice); - } - - struct hw_interrupt_type irq_type_sn = { ---- gregkh-2.6.orig/arch/ia64/sn/pci/msi.c -+++ gregkh-2.6/arch/ia64/sn/pci/msi.c -@@ -6,13 +6,205 @@ - * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved. - */ - --#include <asm/errno.h> -+#include <linux/types.h> -+#include <linux/pci.h> -+#include <linux/cpumask.h> -+ -+#include <asm/msi.h> -+ -+#include <asm/sn/addrs.h> -+#include <asm/sn/intr.h> -+#include <asm/sn/pcibus_provider_defs.h> -+#include <asm/sn/pcidev.h> -+#include <asm/sn/nodepda.h> -+ -+struct sn_msi_info { -+ u64 pci_addr; -+ struct sn_irq_info *sn_irq_info; -+}; -+ -+static struct sn_msi_info *sn_msi_info; -+ -+static void -+sn_msi_teardown(unsigned int vector) -+{ -+ nasid_t nasid; -+ int widget; -+ struct pci_dev *pdev; -+ struct pcidev_info *sn_pdev; -+ struct sn_irq_info *sn_irq_info; -+ struct pcibus_bussoft *bussoft; -+ struct sn_pcibus_provider *provider; -+ -+ sn_irq_info = sn_msi_info[vector].sn_irq_info; -+ if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0) -+ return; -+ -+ sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; -+ pdev = sn_pdev->pdi_linux_pcidev; -+ provider = SN_PCIDEV_BUSPROVIDER(pdev); -+ -+ (*provider->dma_unmap)(pdev, -+ sn_msi_info[vector].pci_addr, -+ PCI_DMA_FROMDEVICE); -+ sn_msi_info[vector].pci_addr = 0; -+ -+ bussoft = SN_PCIDEV_BUSSOFT(pdev); -+ nasid = NASID_GET(bussoft->bs_base); -+ widget = (nasid & 1) ? -+ TIO_SWIN_WIDGETNUM(bussoft->bs_base) : -+ SWIN_WIDGETNUM(bussoft->bs_base); -+ -+ sn_intr_free(nasid, widget, sn_irq_info); -+ sn_msi_info[vector].sn_irq_info = NULL; -+ -+ return; -+} - - int --sn_msi_init(void) -+sn_msi_setup(struct pci_dev *pdev, unsigned int vector, -+ u32 *addr_hi, u32 *addr_lo, u32 *data) - { -+ int widget; -+ int status; -+ nasid_t nasid; -+ u64 bus_addr; -+ struct sn_irq_info *sn_irq_info; -+ struct pcibus_bussoft *bussoft = SN_PCIDEV_BUSSOFT(pdev); -+ struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); -+ -+ if (bussoft == NULL) -+ return -EINVAL; -+ -+ if (provider == NULL || provider->dma_map_consistent == NULL) -+ return -EINVAL; -+ -+ /* -+ * Set up the vector plumbing. Let the prom (via sn_intr_alloc) -+ * decide which cpu to direct this msi at by default. -+ */ -+ -+ nasid = NASID_GET(bussoft->bs_base); -+ widget = (nasid & 1) ? -+ TIO_SWIN_WIDGETNUM(bussoft->bs_base) : -+ SWIN_WIDGETNUM(bussoft->bs_base); -+ -+ sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL); -+ if (! sn_irq_info) -+ return -ENOMEM; -+ -+ status = sn_intr_alloc(nasid, widget, sn_irq_info, vector, -1, -1); -+ if (status) { -+ kfree(sn_irq_info); -+ return -ENOMEM; -+ } -+ -+ sn_irq_info->irq_int_bit = -1; /* mark this as an MSI irq */ -+ sn_irq_fixup(pdev, sn_irq_info); -+ -+ /* Prom probably should fill these in, but doesn't ... */ -+ sn_irq_info->irq_bridge_type = bussoft->bs_asic_type; -+ sn_irq_info->irq_bridge = (void *)bussoft->bs_base; -+ - /* -- * return error until MSI is supported on altix platforms -+ * Map the xio address into bus space - */ -- return -EINVAL; -+ bus_addr = (*provider->dma_map_consistent)(pdev, -+ sn_irq_info->irq_xtalkaddr, -+ sizeof(sn_irq_info->irq_xtalkaddr), -+ SN_DMA_MSI|SN_DMA_ADDR_XIO); -+ if (! bus_addr) { -+ sn_intr_free(nasid, widget, sn_irq_info); -+ kfree(sn_irq_info); -+ return -ENOMEM; -+ } -+ -+ sn_msi_info[vector].sn_irq_info = sn_irq_info; -+ sn_msi_info[vector].pci_addr = bus_addr; -+ -+ *addr_hi = (u32)(bus_addr >> 32); -+ *addr_lo = (u32)(bus_addr & 0x00000000ffffffff); -+ -+ /* -+ * In the SN platform, bit 16 is a "send vector" bit which -+ * must be present in order to move the vector through the system. -+ */ -+ *data = 0x100 + (unsigned int)vector; -+ -+#ifdef CONFIG_SMP -+ set_irq_affinity_info((vector & 0xff), sn_irq_info->irq_cpuid, 0); -+#endif -+ -+ return 0; -+} -+ -+static void -+sn_msi_target(unsigned int vector, unsigned int cpu, -+ u32 *addr_hi, u32 *addr_lo) -+{ -+ int slice; -+ nasid_t nasid; -+ u64 bus_addr; -+ struct pci_dev *pdev; -+ struct pcidev_info *sn_pdev; -+ struct sn_irq_info *sn_irq_info; -+ struct sn_irq_info *new_irq_info; -+ struct sn_pcibus_provider *provider; -+ -+ sn_irq_info = sn_msi_info[vector].sn_irq_info; -+ if (sn_irq_info == NULL || sn_irq_info->irq_int_bit >= 0) -+ return; -+ -+ /* -+ * Release XIO resources for the old MSI PCI address -+ */ -+ -+ sn_pdev = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; -+ pdev = sn_pdev->pdi_linux_pcidev; -+ provider = SN_PCIDEV_BUSPROVIDER(pdev); -+ -+ bus_addr = (u64)(*addr_hi) << 32 | (u64)(*addr_lo); -+ (*provider->dma_unmap)(pdev, bus_addr, PCI_DMA_FROMDEVICE); -+ sn_msi_info[vector].pci_addr = 0; -+ -+ nasid = cpuid_to_nasid(cpu); -+ slice = cpuid_to_slice(cpu); -+ -+ new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice); -+ sn_msi_info[vector].sn_irq_info = new_irq_info; -+ if (new_irq_info == NULL) -+ return; -+ -+ /* -+ * Map the xio address into bus space -+ */ -+ -+ bus_addr = (*provider->dma_map_consistent)(pdev, -+ new_irq_info->irq_xtalkaddr, -+ sizeof(new_irq_info->irq_xtalkaddr), -+ SN_DMA_MSI|SN_DMA_ADDR_XIO); -+ -+ sn_msi_info[vector].pci_addr = bus_addr; -+ *addr_hi = (u32)(bus_addr >> 32); -+ *addr_lo = (u32)(bus_addr & 0x00000000ffffffff); -+} -+ -+struct msi_ops sn_msi_ops = { -+ .setup = sn_msi_setup, -+ .teardown = sn_msi_teardown, -+#ifdef CONFIG_SMP -+ .target = sn_msi_target, -+#endif -+}; -+ -+int -+sn_msi_init(void) -+{ -+ sn_msi_info = -+ kzalloc(sizeof(struct sn_msi_info) * NR_VECTORS, GFP_KERNEL); -+ if (! sn_msi_info) -+ return -ENOMEM; -+ -+ msi_register(&sn_msi_ops); -+ return 0; - } ---- gregkh-2.6.orig/arch/ia64/sn/pci/pci_dma.c -+++ gregkh-2.6/arch/ia64/sn/pci/pci_dma.c -@@ -11,7 +11,7 @@ - - #include <linux/module.h> - #include <asm/dma.h> --#include <asm/sn/pcibr_provider.h> -+#include <asm/sn/intr.h> - #include <asm/sn/pcibus_provider_defs.h> - #include <asm/sn/pcidev.h> - #include <asm/sn/sn_sal.h> -@@ -113,7 +113,8 @@ void *sn_dma_alloc_coherent(struct devic - * resources. - */ - -- *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size); -+ *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size, -+ SN_DMA_ADDR_PHYS); - if (!*dma_handle) { - printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); - free_pages((unsigned long)cpuaddr, get_order(size)); -@@ -176,7 +177,7 @@ dma_addr_t sn_dma_map_single(struct devi - BUG_ON(dev->bus != &pci_bus_type); - - phys_addr = __pa(cpu_addr); -- dma_addr = provider->dma_map(pdev, phys_addr, size); -+ dma_addr = provider->dma_map(pdev, phys_addr, size, SN_DMA_ADDR_PHYS); - if (!dma_addr) { - printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); - return 0; -@@ -260,7 +261,8 @@ int sn_dma_map_sg(struct device *dev, st - for (i = 0; i < nhwentries; i++, sg++) { - phys_addr = SG_ENT_PHYS_ADDRESS(sg); - sg->dma_address = provider->dma_map(pdev, -- phys_addr, sg->length); -+ phys_addr, sg->length, -+ SN_DMA_ADDR_PHYS); - - if (!sg->dma_address) { - printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__); ---- gregkh-2.6.orig/arch/ia64/sn/pci/pcibr/pcibr_dma.c -+++ gregkh-2.6/arch/ia64/sn/pci/pcibr/pcibr_dma.c -@@ -41,7 +41,7 @@ extern int sn_ioif_inited; - - static dma_addr_t - pcibr_dmamap_ate32(struct pcidev_info *info, -- u64 paddr, size_t req_size, u64 flags) -+ u64 paddr, size_t req_size, u64 flags, int dma_flags) - { - - struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; -@@ -81,9 +81,12 @@ pcibr_dmamap_ate32(struct pcidev_info *i - if (IS_PCIX(pcibus_info)) - ate_flags &= ~(PCI32_ATE_PREF); - -- xio_addr = -- IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : -- PHYS_TO_TIODMA(paddr); -+ if (SN_DMA_ADDRTYPE(dma_flags == SN_DMA_ADDR_PHYS)) -+ xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : -+ PHYS_TO_TIODMA(paddr); -+ else -+ xio_addr = paddr; -+ - offset = IOPGOFF(xio_addr); - ate = ate_flags | (xio_addr - offset); - -@@ -91,6 +94,13 @@ pcibr_dmamap_ate32(struct pcidev_info *i - if (IS_PIC_SOFT(pcibus_info)) { - ate |= (pcibus_info->pbi_hub_xid << PIC_ATE_TARGETID_SHFT); - } -+ -+ /* -+ * If we're mapping for MSI, set the MSI bit in the ATE -+ */ -+ if (dma_flags & SN_DMA_MSI) -+ ate |= PCI32_ATE_MSI; -+ - ate_write(pcibus_info, ate_index, ate_count, ate); - - /* -@@ -105,20 +115,27 @@ pcibr_dmamap_ate32(struct pcidev_info *i - if (pcibus_info->pbi_devreg[internal_device] & PCIBR_DEV_SWAP_DIR) - ATE_SWAP_ON(pci_addr); - -+ - return pci_addr; - } - - static dma_addr_t - pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr, -- u64 dma_attributes) -+ u64 dma_attributes, int dma_flags) - { - struct pcibus_info *pcibus_info = (struct pcibus_info *) - ((info->pdi_host_pcidev_info)->pdi_pcibus_info); - u64 pci_addr; - - /* Translate to Crosstalk View of Physical Address */ -- pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : -- PHYS_TO_TIODMA(paddr)) | dma_attributes; -+ if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) -+ pci_addr = IS_PIC_SOFT(pcibus_info) ? -+ PHYS_TO_DMA(paddr) : -+ PHYS_TO_TIODMA(paddr) | dma_attributes; -+ else -+ pci_addr = IS_PIC_SOFT(pcibus_info) ? -+ paddr : -+ paddr | dma_attributes; - - /* Handle Bus mode */ - if (IS_PCIX(pcibus_info)) -@@ -130,7 +147,9 @@ pcibr_dmatrans_direct64(struct pcidev_in - ((u64) pcibus_info-> - pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT); - } else -- pci_addr |= TIOCP_PCI64_CMDTYPE_MEM; -+ pci_addr |= (dma_flags & SN_DMA_MSI) ? -+ TIOCP_PCI64_CMDTYPE_MSI : -+ TIOCP_PCI64_CMDTYPE_MEM; - - /* If PCI mode, func zero uses VCHAN0, every other func uses VCHAN1 */ - if (!IS_PCIX(pcibus_info) && PCI_FUNC(info->pdi_linux_pcidev->devfn)) -@@ -141,7 +160,7 @@ pcibr_dmatrans_direct64(struct pcidev_in - - static dma_addr_t - pcibr_dmatrans_direct32(struct pcidev_info * info, -- u64 paddr, size_t req_size, u64 flags) -+ u64 paddr, size_t req_size, u64 flags, int dma_flags) - { - struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info; - struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info-> -@@ -156,8 +175,14 @@ pcibr_dmatrans_direct32(struct pcidev_in - return 0; - } - -- xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : -- PHYS_TO_TIODMA(paddr); -+ if (dma_flags & SN_DMA_MSI) -+ return 0; -+ -+ if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) -+ xio_addr = IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) : -+ PHYS_TO_TIODMA(paddr); -+ else -+ xio_addr = paddr; - - xio_base = pcibus_info->pbi_dir_xbase; - offset = xio_addr - xio_base; -@@ -327,7 +352,7 @@ void sn_dma_flush(u64 addr) - */ - - dma_addr_t --pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size) -+pcibr_dma_map(struct pci_dev * hwdev, unsigned long phys_addr, size_t size, int dma_flags) - { - dma_addr_t dma_handle; - struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev); -@@ -344,11 +369,11 @@ pcibr_dma_map(struct pci_dev * hwdev, un - */ - - dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr, -- PCI64_ATTR_PREF); -+ PCI64_ATTR_PREF, dma_flags); - } else { - /* Handle 32-63 bit cards via direct mapping */ - dma_handle = pcibr_dmatrans_direct32(pcidev_info, phys_addr, -- size, 0); -+ size, 0, dma_flags); - if (!dma_handle) { - /* - * It is a 32 bit card and we cannot do direct mapping, -@@ -356,7 +381,8 @@ pcibr_dma_map(struct pci_dev * hwdev, un - */ - - dma_handle = pcibr_dmamap_ate32(pcidev_info, phys_addr, -- size, PCI32_ATE_PREF); -+ size, PCI32_ATE_PREF, -+ dma_flags); - } - } - -@@ -365,18 +391,18 @@ pcibr_dma_map(struct pci_dev * hwdev, un - - dma_addr_t - pcibr_dma_map_consistent(struct pci_dev * hwdev, unsigned long phys_addr, -- size_t size) -+ size_t size, int dma_flags) - { - dma_addr_t dma_handle; - struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(hwdev); - - if (hwdev->dev.coherent_dma_mask == ~0UL) { - dma_handle = pcibr_dmatrans_direct64(pcidev_info, phys_addr, -- PCI64_ATTR_BAR); -+ PCI64_ATTR_BAR, dma_flags); - } else { - dma_handle = (dma_addr_t) pcibr_dmamap_ate32(pcidev_info, - phys_addr, size, -- PCI32_ATE_BAR); -+ PCI32_ATE_BAR, dma_flags); - } - - return dma_handle; ---- gregkh-2.6.orig/arch/ia64/sn/pci/tioca_provider.c -+++ gregkh-2.6/arch/ia64/sn/pci/tioca_provider.c -@@ -515,11 +515,17 @@ tioca_dma_unmap(struct pci_dev *pdev, dm - * use the GART mapped mode. - */ - static u64 --tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count) -+tioca_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags) - { - u64 mapaddr; - - /* -+ * Not supported for now ... -+ */ -+ if (dma_flags & SN_DMA_MSI) -+ return 0; -+ -+ /* - * If card is 64 or 48 bit addresable, use a direct mapping. 32 - * bit direct is so restrictive w.r.t. where the memory resides that - * we don't use it even though CA has some support. ---- gregkh-2.6.orig/arch/ia64/sn/pci/tioce_provider.c -+++ gregkh-2.6/arch/ia64/sn/pci/tioce_provider.c -@@ -52,7 +52,8 @@ - (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1) - - #define ATE_VALID(ate) ((ate) & (1UL << 63)) --#define ATE_MAKE(addr, ps) (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63)) -+#define ATE_MAKE(addr, ps, msi) \ -+ (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0)) - - /* - * Flavors of ate-based mapping supported by tioce_alloc_map() -@@ -78,15 +79,17 @@ - * - * 63 - must be 1 to indicate d64 mode to CE hardware - * 62 - barrier bit ... controlled with tioce_dma_barrier() -- * 61 - 0 since this is not an MSI transaction -+ * 61 - msi bit ... specified through dma_flags - * 60:54 - reserved, MBZ - */ - static u64 --tioce_dma_d64(unsigned long ct_addr) -+tioce_dma_d64(unsigned long ct_addr, int dma_flags) - { - u64 bus_addr; - - bus_addr = ct_addr | (1UL << 63); -+ if (dma_flags & SN_DMA_MSI) -+ bus_addr |= (1UL << 61); - - return bus_addr; - } -@@ -143,7 +146,7 @@ pcidev_to_tioce(struct pci_dev *pdev, st - */ - static u64 - tioce_alloc_map(struct tioce_kernel *ce_kern, int type, int port, -- u64 ct_addr, int len) -+ u64 ct_addr, int len, int dma_flags) - { - int i; - int j; -@@ -152,6 +155,7 @@ tioce_alloc_map(struct tioce_kernel *ce_ - int entries; - int nates; - int pagesize; -+ int msi_capable, msi_wanted; - u64 *ate_shadow; - u64 *ate_reg; - u64 addr; -@@ -173,6 +177,7 @@ tioce_alloc_map(struct tioce_kernel *ce_ - ate_reg = ce_mmr->ce_ure_ate3240; - pagesize = ce_kern->ce_ate3240_pagesize; - bus_base = TIOCE_M32_MIN; -+ msi_capable = 1; - break; - case TIOCE_ATE_M40: - first = 0; -@@ -181,6 +186,7 @@ tioce_alloc_map(struct tioce_kernel *ce_ - ate_reg = ce_mmr->ce_ure_ate40; - pagesize = MB(64); - bus_base = TIOCE_M40_MIN; -+ msi_capable = 0; - break; - case TIOCE_ATE_M40S: - /* -@@ -193,11 +199,16 @@ tioce_alloc_map(struct tioce_kernel *ce_ - ate_reg = ce_mmr->ce_ure_ate3240; - pagesize = GB(16); - bus_base = TIOCE_M40S_MIN; -+ msi_capable = 0; - break; - default: - return 0; - } - -+ msi_wanted = dma_flags & SN_DMA_MSI; -+ if (msi_wanted && !msi_capable) -+ return 0; -+ - nates = ATE_NPAGES(ct_addr, len, pagesize); - if (nates > entries) - return 0; -@@ -226,7 +237,7 @@ tioce_alloc_map(struct tioce_kernel *ce_ - for (j = 0; j < nates; j++) { - u64 ate; - -- ate = ATE_MAKE(addr, pagesize); -+ ate = ATE_MAKE(addr, pagesize, msi_wanted); - ate_shadow[i + j] = ate; - writeq(ate, &ate_reg[i + j]); - addr += pagesize; -@@ -253,7 +264,7 @@ tioce_alloc_map(struct tioce_kernel *ce_ - * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info. - */ - static u64 --tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr) -+tioce_dma_d32(struct pci_dev *pdev, u64 ct_addr, int dma_flags) - { - int dma_ok; - int port; -@@ -263,6 +274,9 @@ tioce_dma_d32(struct pci_dev *pdev, u64 - u64 ct_lower; - dma_addr_t bus_addr; - -+ if (dma_flags & SN_DMA_MSI) -+ return 0; -+ - ct_upper = ct_addr & ~0x3fffffffUL; - ct_lower = ct_addr & 0x3fffffffUL; - -@@ -387,7 +401,7 @@ tioce_dma_unmap(struct pci_dev *pdev, dm - */ - static u64 - tioce_do_dma_map(struct pci_dev *pdev, u64 paddr, size_t byte_count, -- int barrier) -+ int barrier, int dma_flags) - { - unsigned long flags; - u64 ct_addr; -@@ -403,15 +417,18 @@ tioce_do_dma_map(struct pci_dev *pdev, u - if (dma_mask < 0x7fffffffUL) - return 0; - -- ct_addr = PHYS_TO_TIODMA(paddr); -+ if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) -+ ct_addr = PHYS_TO_TIODMA(paddr); -+ else -+ ct_addr = paddr; - - /* - * If the device can generate 64 bit addresses, create a D64 map. -- * Since this should never fail, bypass the rest of the checks. - */ - if (dma_mask == ~0UL) { -- mapaddr = tioce_dma_d64(ct_addr); -- goto dma_map_done; -+ mapaddr = tioce_dma_d64(ct_addr, dma_flags); -+ if (mapaddr) -+ goto dma_map_done; - } - - pcidev_to_tioce(pdev, NULL, &ce_kern, &port); -@@ -454,18 +471,22 @@ tioce_do_dma_map(struct pci_dev *pdev, u - - if (byte_count > MB(64)) { - mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, -- port, ct_addr, byte_count); -+ port, ct_addr, byte_count, -+ dma_flags); - if (!mapaddr) - mapaddr = - tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, -- ct_addr, byte_count); -+ ct_addr, byte_count, -+ dma_flags); - } else { - mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, -- ct_addr, byte_count); -+ ct_addr, byte_count, -+ dma_flags); - if (!mapaddr) - mapaddr = - tioce_alloc_map(ce_kern, TIOCE_ATE_M40S, -- port, ct_addr, byte_count); -+ port, ct_addr, byte_count, -+ dma_flags); - } - } - -@@ -473,7 +494,7 @@ tioce_do_dma_map(struct pci_dev *pdev, u - * 32-bit direct is the next mode to try - */ - if (!mapaddr && dma_mask >= 0xffffffffUL) -- mapaddr = tioce_dma_d32(pdev, ct_addr); -+ mapaddr = tioce_dma_d32(pdev, ct_addr, dma_flags); - - /* - * Last resort, try 32-bit ATE-based map. -@@ -481,12 +502,12 @@ tioce_do_dma_map(struct pci_dev *pdev, u - if (!mapaddr) - mapaddr = - tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr, -- byte_count); -+ byte_count, dma_flags); - - spin_unlock_irqrestore(&ce_kern->ce_lock, flags); - - dma_map_done: -- if (mapaddr & barrier) -+ if (mapaddr && barrier) - mapaddr = tioce_dma_barrier(mapaddr, 1); - - return mapaddr; -@@ -502,9 +523,9 @@ dma_map_done: - * in the address. - */ - static u64 --tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count) -+tioce_dma(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags) - { -- return tioce_do_dma_map(pdev, paddr, byte_count, 0); -+ return tioce_do_dma_map(pdev, paddr, byte_count, 0, dma_flags); - } - - /** -@@ -516,9 +537,9 @@ tioce_dma(struct pci_dev *pdev, u64 padd - * Simply call tioce_do_dma_map() to create a map with the barrier bit set - * in the address. - */ static u64 --tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count) -+tioce_dma_consistent(struct pci_dev *pdev, u64 paddr, size_t byte_count, int dma_flags) - { -- return tioce_do_dma_map(pdev, paddr, byte_count, 1); -+ return tioce_do_dma_map(pdev, paddr, byte_count, 1, dma_flags); - } - - /** ---- gregkh-2.6.orig/include/asm-ia64/sn/intr.h -+++ gregkh-2.6/include/asm-ia64/sn/intr.h -@@ -10,6 +10,7 @@ - #define _ASM_IA64_SN_INTR_H - - #include <linux/rcupdate.h> -+#include <asm/sn/types.h> - - #define SGI_UART_VECTOR 0xe9 - -@@ -40,6 +41,7 @@ struct sn_irq_info { - int irq_cpuid; /* kernel logical cpuid */ - int irq_irq; /* the IRQ number */ - int irq_int_bit; /* Bridge interrupt pin */ -+ /* <0 means MSI */ - u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */ - int irq_bridge_type;/* pciio asic type (pciio.h) */ - void *irq_bridge; /* bridge generating irq */ -@@ -53,6 +55,12 @@ struct sn_irq_info { - }; - - extern void sn_send_IPI_phys(int, long, int, int); -+extern u64 sn_intr_alloc(nasid_t, int, -+ struct sn_irq_info *, -+ int, nasid_t, int); -+extern void sn_intr_free(nasid_t, int, struct sn_irq_info *); -+extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int); -+extern struct list_head **sn_irq_lh; - - #define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector) - ---- gregkh-2.6.orig/include/asm-ia64/sn/pcibr_provider.h -+++ gregkh-2.6/include/asm-ia64/sn/pcibr_provider.h -@@ -55,6 +55,7 @@ - #define PCI32_ATE_V (0x1 << 0) - #define PCI32_ATE_CO (0x1 << 1) - #define PCI32_ATE_PREC (0x1 << 2) -+#define PCI32_ATE_MSI (0x1 << 2) - #define PCI32_ATE_PREF (0x1 << 3) - #define PCI32_ATE_BAR (0x1 << 4) - #define PCI32_ATE_ADDR_SHFT 12 -@@ -117,8 +118,8 @@ struct pcibus_info { - - extern int pcibr_init_provider(void); - extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *); --extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t); --extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t); -+extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type); -+extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type); - extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int); - - /* ---- gregkh-2.6.orig/include/asm-ia64/sn/pcibus_provider_defs.h -+++ gregkh-2.6/include/asm-ia64/sn/pcibus_provider_defs.h -@@ -3,7 +3,7 @@ - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * -- * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. -+ * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved. - */ - #ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H - #define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H -@@ -45,13 +45,24 @@ struct pci_controller; - */ - - struct sn_pcibus_provider { -- dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t); -- dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t); -+ dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags); -+ dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags); - void (*dma_unmap)(struct pci_dev *, dma_addr_t, int); - void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *); - void (*force_interrupt)(struct sn_irq_info *); - void (*target_interrupt)(struct sn_irq_info *); - }; - -+/* -+ * Flags used by the map interfaces -+ * bits 3:0 specifies format of passed in address -+ * bit 4 specifies that address is to be used for MSI -+ */ -+ -+#define SN_DMA_ADDRTYPE(x) ((x) & 0xf) -+#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */ -+#define SN_DMA_ADDR_XIO 2 /* address is phys memory */ -+#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */ -+ - extern struct sn_pcibus_provider *sn_pci_provider[]; - #endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */ ---- gregkh-2.6.orig/include/asm-ia64/sn/tiocp.h -+++ gregkh-2.6/include/asm-ia64/sn/tiocp.h -@@ -3,13 +3,14 @@ - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * -- * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved. -+ * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved. - */ - #ifndef _ASM_IA64_SN_PCI_TIOCP_H - #define _ASM_IA64_SN_PCI_TIOCP_H - - #define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL - #define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60) -+#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60) - - - /***************************************************************************** diff --git a/pci/i386-pci-ordering.patch b/pci/i386-pci-ordering.patch index f227c0b414be8..ffdaaeff55355 100644 --- a/pci/i386-pci-ordering.patch +++ b/pci/i386-pci-ordering.patch @@ -23,8 +23,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> arch/i386/pci/pcbios.c | 4 +--- arch/i386/pci/pci.h | 3 +++ arch/x86_64/pci/Makefile | 3 ++- - include/asm-i386/acpi.h | 9 ++++++--- - 8 files changed, 46 insertions(+), 26 deletions(-) + 7 files changed, 40 insertions(+), 23 deletions(-) --- gregkh-2.6.orig/arch/i386/pci/Makefile +++ gregkh-2.6/arch/i386/pci/Makefile @@ -185,35 +184,3 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> fixup-y += ../../i386/pci/fixup.o i386-y += ../../i386/pci/i386.o +init-y += ../../i386/pci/init.o ---- gregkh-2.6.orig/include/asm-i386/acpi.h -+++ gregkh-2.6/include/asm-i386/acpi.h -@@ -103,6 +103,12 @@ __acpi_release_global_lock (unsigned int - :"=r"(n_hi), "=r"(n_lo) \ - :"0"(n_hi), "1"(n_lo)) - -+#ifdef CONFIG_X86_IO_APIC -+extern void check_acpi_pci(void); -+#else -+static inline void check_acpi_pci(void) { } -+#endif -+ - #ifdef CONFIG_ACPI - extern int acpi_lapic; - extern int acpi_ioapic; -@@ -128,7 +134,6 @@ extern int acpi_gsi_to_irq(u32 gsi, unsi - extern int skip_ioapic_setup; - extern int acpi_skip_timer_override; - --extern void check_acpi_pci(void); - - static inline void disable_ioapic_setup(void) - { -@@ -142,8 +147,6 @@ static inline int ioapic_setup_disabled( - - #else - static inline void disable_ioapic_setup(void) { } --static inline void check_acpi_pci(void) { } -- - #endif - - static inline void acpi_noirq_set(void) { acpi_noirq = 1; } diff --git a/pci/msi-vector-targeting-abstractions.patch b/pci/msi-vector-targeting-abstractions.patch deleted file mode 100644 index 158129efa562e..0000000000000 --- a/pci/msi-vector-targeting-abstractions.patch +++ /dev/null @@ -1,695 +0,0 @@ -From owner-linux-pci@atrey.karlin.mff.cuni.cz Thu Jan 19 11:46:59 2006 -Date: Thu, 19 Jan 2006 13:46:52 -0600 (CST) -From: Mark Maule <maule@sgi.com> -Cc: Tony Luck <tony.luck@intel.com>, gregkh@suse.de, Mark Maule <maule@sgi.com> -Message-Id: <20060119194652.12213.96503.19247@lnx-maule.americas.sgi.com> -Subject: [PATCH 1/3] msi vector targeting abstractions - -Abstract portions of the MSI core for platforms that do not use standard -APIC interrupt controllers. This is implemented through a new arch-specific -msi setup routine, and a set of msi ops which can be set on a per platform -basis. - -Signed-off-by: Mark Maule <maule@sgi.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> - ---- - arch/ia64/sn/pci/Makefile | 3 - arch/ia64/sn/pci/msi.c | 18 +++++ - drivers/pci/Makefile | 2 - drivers/pci/msi-apic.c | 92 +++++++++++++++++++++++++ - drivers/pci/msi.c | 146 ++++++++++++++++++++++------------------- - drivers/pci/msi.h | 120 ++++++++++++++++----------------- - drivers/pci/pci.h | 3 - include/asm-i386/msi.h | 8 ++ - include/asm-ia64/machvec.h | 12 +++ - include/asm-ia64/machvec_sn2.h | 6 + - include/asm-ia64/msi.h | 11 +++ - include/asm-x86_64/msi.h | 8 ++ - 12 files changed, 300 insertions(+), 129 deletions(-) - ---- gregkh-2.6.orig/arch/ia64/sn/pci/Makefile -+++ gregkh-2.6/arch/ia64/sn/pci/Makefile -@@ -3,10 +3,11 @@ - # License. See the file "COPYING" in the main directory of this archive - # for more details. - # --# Copyright (C) 2000-2004 Silicon Graphics, Inc. All Rights Reserved. -+# Copyright (C) 2000-2005 Silicon Graphics, Inc. All Rights Reserved. - # - # Makefile for the sn pci general routines. - - CPPFLAGS += -I$(srctree)/arch/ia64/sn/include - - obj-y := pci_dma.o tioca_provider.o tioce_provider.o pcibr/ -+obj-$(CONFIG_PCI_MSI) += msi.o ---- /dev/null -+++ gregkh-2.6/arch/ia64/sn/pci/msi.c -@@ -0,0 +1,18 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved. -+ */ -+ -+#include <asm/errno.h> -+ -+int -+sn_msi_init(void) -+{ -+ /* -+ * return error until MSI is supported on altix platforms -+ */ -+ return -EINVAL; -+} ---- gregkh-2.6.orig/drivers/pci/Makefile -+++ gregkh-2.6/drivers/pci/Makefile -@@ -26,7 +26,7 @@ obj-$(CONFIG_PPC32) += setup-irq.o - obj-$(CONFIG_PPC64) += setup-bus.o - obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o - obj-$(CONFIG_X86_VISWS) += setup-irq.o --obj-$(CONFIG_PCI_MSI) += msi.o -+obj-$(CONFIG_PCI_MSI) += msi.o msi-apic.o - - # - # ACPI Related PCI FW Functions ---- /dev/null -+++ gregkh-2.6/drivers/pci/msi-apic.c -@@ -0,0 +1,92 @@ -+/* -+ * MSI hooks for standard x86 apic -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2005 Silicon Graphics, Inc. All Rights Reserved. -+ */ -+ -+#include <linux/pci.h> -+#include <linux/irq.h> -+ -+#include "pci.h" -+#include "msi.h" -+ -+/* Shifts for APIC-based data */ -+#define MSI_DATA_VECTOR_SHIFT 0 -+#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT) -+ -+#define MSI_DATA_DELIVERY_SHIFT 8 -+#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_SHIFT) -+#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_SHIFT) -+ -+#define MSI_DATA_LEVEL_SHIFT 14 -+#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) -+#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) -+ -+#define MSI_DATA_TRIGGER_SHIFT 15 -+#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) -+#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) -+ -+/* Shift/mask fields for APIC-based bus address */ -+#define MSI_ADDR_HEADER 0xfee00000 -+ -+#define MSI_ADDR_DESTID_MASK 0xfff0000f -+#define MSI_ADDR_DESTID_CPU(cpu) ((cpu) << MSI_TARGET_CPU_SHIFT) -+ -+#define MSI_ADDR_DESTMODE_SHIFT 2 -+#define MSI_ADDR_DESTMODE_PHYS (0 << MSI_ADDR_DESTMODE_SHIFT) -+#define MSI_ADDR_DESTMODE_LOGIC (1 << MSI_ADDR_DESTMODE_SHIFT) -+ -+#define MSI_ADDR_REDIRECTION_SHIFT 3 -+#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) -+#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) -+ -+ -+static void msi_target_apic(unsigned int vector, unsigned int dest_cpu, -+ u32 *address_hi, u32 *address_lo) -+{ -+ u32 addr = *address_lo; -+ -+ addr &= MSI_ADDR_DESTID_MASK; -+ addr |= MSI_ADDR_DESTID_CPU(cpu_physical_id(dest_cpu)); -+ -+ *address_lo = addr; -+} -+ -+static int msi_setup_apic(struct pci_dev *pdev, unsigned int vector, -+ u32 *address_hi, u32 *address_lo, u32 *data) -+{ -+ unsigned long dest_phys_id; -+ -+ dest_phys_id = cpu_physical_id(first_cpu(cpu_online_map)); -+ -+ *address_hi = 0; -+ *address_lo = MSI_ADDR_HEADER | -+ MSI_ADDR_DESTMODE_PHYS | -+ MSI_ADDR_REDIRECTION_CPU | -+ MSI_ADDR_DESTID_CPU(dest_phys_id); -+ -+ *data = MSI_DATA_TRIGGER_EDGE | -+ MSI_DATA_LEVEL_ASSERT | -+ MSI_DATA_DELIVERY_FIXED | -+ MSI_DATA_VECTOR(vector); -+ -+ return 0; -+} -+ -+static void msi_teardown_apic(unsigned int vector) -+{ -+ return; -+} -+ -+/* -+ * Generic ops used on most IA archs/platforms. Set with msi_register() -+ */ -+struct msi_ops msi_apic_ops = { -+ .setup = msi_setup_apic, -+ .teardown = msi_teardown_apic, -+ .target = msi_target_apic, -+}; ---- gregkh-2.6.orig/drivers/pci/msi.c -+++ gregkh-2.6/drivers/pci/msi.c -@@ -23,8 +23,6 @@ - #include "pci.h" - #include "msi.h" - --#define MSI_TARGET_CPU first_cpu(cpu_online_map) -- - static DEFINE_SPINLOCK(msi_lock); - static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; - static kmem_cache_t* msi_cachep; -@@ -40,6 +38,14 @@ int vector_irq[NR_VECTORS] = { [0 ... NR - u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 }; - #endif - -+static struct msi_ops *msi_ops; -+ -+int msi_register(struct msi_ops *ops) -+{ -+ msi_ops = ops; -+ return 0; -+} -+ - static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags) - { - memset(p, 0, NR_IRQS * sizeof(struct msi_desc)); -@@ -92,7 +98,7 @@ static void msi_set_mask_bit(unsigned in - static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask) - { - struct msi_desc *entry; -- struct msg_address address; -+ u32 address_hi, address_lo; - unsigned int irq = vector; - unsigned int dest_cpu = first_cpu(cpu_mask); - -@@ -108,28 +114,36 @@ static void set_msi_affinity(unsigned in - if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI))) - return; - -+ pci_read_config_dword(entry->dev, msi_upper_address_reg(pos), -+ &address_hi); - pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), -- &address.lo_address.value); -- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; -- address.lo_address.value |= (cpu_physical_id(dest_cpu) << -- MSI_TARGET_CPU_SHIFT); -- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu); -+ &address_lo); -+ -+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo); -+ -+ pci_write_config_dword(entry->dev, msi_upper_address_reg(pos), -+ address_hi); - pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), -- address.lo_address.value); -+ address_lo); - set_native_irq_info(irq, cpu_mask); - break; - } - case PCI_CAP_ID_MSIX: - { -- int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + -- PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET; -+ int offset_hi = -+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + -+ PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET; -+ int offset_lo = -+ entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + -+ PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET; -+ -+ address_hi = readl(entry->mask_base + offset_hi); -+ address_lo = readl(entry->mask_base + offset_lo); - -- address.lo_address.value = readl(entry->mask_base + offset); -- address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; -- address.lo_address.value |= (cpu_physical_id(dest_cpu) << -- MSI_TARGET_CPU_SHIFT); -- entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu); -- writel(address.lo_address.value, entry->mask_base + offset); -+ msi_ops->target(vector, dest_cpu, &address_hi, &address_lo); -+ -+ writel(address_hi, entry->mask_base + offset_hi); -+ writel(address_lo, entry->mask_base + offset_lo); - set_native_irq_info(irq, cpu_mask); - break; - } -@@ -251,30 +265,6 @@ static struct hw_interrupt_type msi_irq_ - .set_affinity = set_msi_affinity - }; - --static void msi_data_init(struct msg_data *msi_data, -- unsigned int vector) --{ -- memset(msi_data, 0, sizeof(struct msg_data)); -- msi_data->vector = (u8)vector; -- msi_data->delivery_mode = MSI_DELIVERY_MODE; -- msi_data->level = MSI_LEVEL_MODE; -- msi_data->trigger = MSI_TRIGGER_MODE; --} -- --static void msi_address_init(struct msg_address *msi_address) --{ -- unsigned int dest_id; -- unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU); -- -- memset(msi_address, 0, sizeof(struct msg_address)); -- msi_address->hi_address = (u32)0; -- dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT); -- msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE; -- msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE; -- msi_address->lo_address.u.dest_id = dest_id; -- msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT); --} -- - static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); - static int assign_msi_vector(void) - { -@@ -369,6 +359,20 @@ static int msi_init(void) - return status; - } - -+ if ((status = msi_arch_init()) < 0) { -+ pci_msi_enable = 0; -+ printk(KERN_WARNING -+ "PCI: MSI arch init failed. MSI disabled.\n"); -+ return status; -+ } -+ -+ if (! msi_ops) { -+ printk(KERN_WARNING -+ "PCI: MSI ops not registered. MSI disabled.\n"); -+ status = -EINVAL; -+ return status; -+ } -+ - if ((status = msi_cache_init()) < 0) { - pci_msi_enable = 0; - printk(KERN_WARNING "PCI: MSI cache init failed\n"); -@@ -514,9 +518,11 @@ void pci_scan_msi_device(struct pci_dev - **/ - static int msi_capability_init(struct pci_dev *dev) - { -+ int status; - struct msi_desc *entry; -- struct msg_address address; -- struct msg_data data; -+ u32 address_lo; -+ u32 address_hi; -+ u32 data; - int pos, vector; - u16 control; - -@@ -543,23 +549,27 @@ static int msi_capability_init(struct pc - entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, - is_64bit_address(control)); - } -+ /* Configure MSI capability structure */ -+ status = msi_ops->setup(dev, vector, -+ &address_hi, -+ &address_lo, -+ &data); -+ if (status < 0) { -+ dev->irq = entry->msi_attrib.default_vector; -+ kmem_cache_free(msi_cachep, entry); -+ return status; -+ } - /* Replace with MSI handler */ - irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); -- /* Configure MSI capability structure */ -- msi_address_init(&address); -- msi_data_init(&data, vector); -- entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >> -- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); -- pci_write_config_dword(dev, msi_lower_address_reg(pos), -- address.lo_address.value); -+ -+ pci_write_config_dword(dev, msi_lower_address_reg(pos), address_lo); - if (is_64bit_address(control)) { - pci_write_config_dword(dev, -- msi_upper_address_reg(pos), address.hi_address); -- pci_write_config_word(dev, -- msi_data_reg(pos, 1), *((u32*)&data)); -+ msi_upper_address_reg(pos), address_hi); -+ pci_write_config_word(dev, msi_data_reg(pos, 1), data); - } else -- pci_write_config_word(dev, -- msi_data_reg(pos, 0), *((u32*)&data)); -+ pci_write_config_word(dev, msi_data_reg(pos, 0), data); -+ - if (entry->msi_attrib.maskbit) { - unsigned int maskbits, temp; - /* All MSIs are unmasked by default, Mask them all */ -@@ -594,13 +604,15 @@ static int msix_capability_init(struct p - struct msix_entry *entries, int nvec) - { - struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; -- struct msg_address address; -- struct msg_data data; -+ u32 address_hi; -+ u32 address_lo; -+ u32 data; - int vector, pos, i, j, nr_entries, temp = 0; - u32 phys_addr, table_offset; - u16 control; - u8 bir; - void __iomem *base; -+ int status; - - pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); - /* Request & Map MSI-X table region */ -@@ -647,18 +659,20 @@ static int msix_capability_init(struct p - /* Replace with MSI-X handler */ - irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); - /* Configure MSI-X capability structure */ -- msi_address_init(&address); -- msi_data_init(&data, vector); -- entry->msi_attrib.current_cpu = -- ((address.lo_address.u.dest_id >> -- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); -- writel(address.lo_address.value, -+ status = msi_ops->setup(dev, vector, -+ &address_hi, -+ &address_lo, -+ &data); -+ if (status < 0) -+ break; -+ -+ writel(address_lo, - base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); -- writel(address.hi_address, -+ writel(address_hi, - base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); -- writel(*(u32*)&data, -+ writel(data, - base + j * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_DATA_OFFSET); - attach_msi_entry(entry, vector); -@@ -793,6 +807,8 @@ static int msi_free_vector(struct pci_de - void __iomem *base; - unsigned long flags; - -+ msi_ops->teardown(vector); -+ - spin_lock_irqsave(&msi_lock, flags); - entry = msi_desc[vector]; - if (!entry || entry->dev != dev) { ---- gregkh-2.6.orig/drivers/pci/msi.h -+++ gregkh-2.6/drivers/pci/msi.h -@@ -63,67 +63,6 @@ extern int pci_vector_resources(int last - #define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK) - #define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK) - --/* -- * MSI Defined Data Structures -- */ --#define MSI_ADDRESS_HEADER 0xfee --#define MSI_ADDRESS_HEADER_SHIFT 12 --#define MSI_ADDRESS_HEADER_MASK 0xfff000 --#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f --#define MSI_TARGET_CPU_MASK 0xff --#define MSI_DELIVERY_MODE 0 --#define MSI_LEVEL_MODE 1 /* Edge always assert */ --#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */ --#define MSI_PHYSICAL_MODE 0 --#define MSI_LOGICAL_MODE 1 --#define MSI_REDIRECTION_HINT_MODE 0 -- --struct msg_data { --#if defined(__LITTLE_ENDIAN_BITFIELD) -- __u32 vector : 8; -- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ -- __u32 reserved_1 : 3; -- __u32 level : 1; /* 0: deassert | 1: assert */ -- __u32 trigger : 1; /* 0: edge | 1: level */ -- __u32 reserved_2 : 16; --#elif defined(__BIG_ENDIAN_BITFIELD) -- __u32 reserved_2 : 16; -- __u32 trigger : 1; /* 0: edge | 1: level */ -- __u32 level : 1; /* 0: deassert | 1: assert */ -- __u32 reserved_1 : 3; -- __u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */ -- __u32 vector : 8; --#else --#error "Bitfield endianness not defined! Check your byteorder.h" --#endif --} __attribute__ ((packed)); -- --struct msg_address { -- union { -- struct { --#if defined(__LITTLE_ENDIAN_BITFIELD) -- __u32 reserved_1 : 2; -- __u32 dest_mode : 1; /*0:physic | 1:logic */ -- __u32 redirection_hint: 1; /*0: dedicated CPU -- 1: lowest priority */ -- __u32 reserved_2 : 4; -- __u32 dest_id : 24; /* Destination ID */ --#elif defined(__BIG_ENDIAN_BITFIELD) -- __u32 dest_id : 24; /* Destination ID */ -- __u32 reserved_2 : 4; -- __u32 redirection_hint: 1; /*0: dedicated CPU -- 1: lowest priority */ -- __u32 dest_mode : 1; /*0:physic | 1:logic */ -- __u32 reserved_1 : 2; --#else --#error "Bitfield endianness not defined! Check your byteorder.h" --#endif -- }u; -- __u32 value; -- }lo_address; -- __u32 hi_address; --} __attribute__ ((packed)); -- - struct msi_desc { - struct { - __u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */ -@@ -132,7 +71,7 @@ struct msi_desc { - __u8 reserved: 1; /* reserved */ - __u8 entry_nr; /* specific enabled entry */ - __u8 default_vector; /* default pre-assigned vector */ -- __u8 current_cpu; /* current destination cpu */ -+ __u8 unused; /* formerly unused destination cpu*/ - }msi_attrib; - - struct { -@@ -144,4 +83,61 @@ struct msi_desc { - struct pci_dev *dev; - }; - -+/* -+ * MSI operation vector. Used by the msi core code (drivers/pci/msi.c) -+ * to abstract platform-specific tasks relating to MSI address generation -+ * and resource management. -+ */ -+struct msi_ops { -+ /** -+ * setup - generate an MSI bus address and data for a given vector -+ * @pdev: PCI device context (in) -+ * @vector: vector allocated by the msi core (in) -+ * @addr_hi: upper 32 bits of PCI bus MSI address (out) -+ * @addr_lo: lower 32 bits of PCI bus MSI address (out) -+ * @data: MSI data payload (out) -+ * -+ * Description: The setup op is used to generate a PCI bus addres and -+ * data which the msi core will program into the card MSI capability -+ * registers. The setup routine is responsible for picking an initial -+ * cpu to target the MSI at. The setup routine is responsible for -+ * examining pdev to determine the MSI capabilities of the card and -+ * generating a suitable address/data. The setup routine is -+ * responsible for allocating and tracking any system resources it -+ * needs to route the MSI to the cpu it picks, and for associating -+ * those resources with the passed in vector. -+ * -+ * Returns 0 if the MSI address/data was successfully setup. -+ */ -+ int (*setup) (struct pci_dev *pdev, unsigned int vector, -+ u32 *addr_hi, u32 *addr_lo, u32 *data); -+ -+ /** -+ * teardown - release resources allocated by setup -+ * @vector: vector context for resources (in) -+ * -+ * Description: The teardown op is used to release any resources -+ * that were allocated in the setup routine associated with the passed -+ * in vector. -+ */ -+ void (*teardown) (unsigned int vector); -+ -+ /** -+ * target - retarget an MSI at a different cpu -+ * @vector: vector context for resources (in) -+ * @cpu: new cpu to direct vector at (in) -+ * @addr_hi: new value of PCI bus upper 32 bits (in/out) -+ * @addr_lo: new value of PCI bus lower 32 bits (in/out) -+ * -+ * Description: The target op is used to redirect an MSI vector -+ * at a different cpu. addr_hi/addr_lo coming in are the existing -+ * values that the MSI core has programmed into the card. The -+ * target code is responsible for freeing any resources (if any) -+ * associated with the old address, and generating a new PCI bus -+ * addr_hi/addr_lo that will redirect the vector at the indicated cpu. -+ */ -+ void (*target) (unsigned int vector, unsigned int cpu, -+ u32 *addr_hi, u32 *addr_lo); -+}; -+ - #endif /* MSI_H */ ---- gregkh-2.6.orig/drivers/pci/pci.h -+++ gregkh-2.6/drivers/pci/pci.h -@@ -48,10 +48,13 @@ extern int pci_msi_quirk; - #define pci_msi_quirk 0 - #endif - -+struct msi_ops; - #ifdef CONFIG_PCI_MSI - void disable_msi_mode(struct pci_dev *dev, int pos, int type); -+int msi_register(struct msi_ops *ops); - #else - static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { } -+static inline int msi_register(struct msi_ops *ops) { return 0; } - #endif - - extern int pcie_mch_quirk; ---- gregkh-2.6.orig/include/asm-i386/msi.h -+++ gregkh-2.6/include/asm-i386/msi.h -@@ -12,4 +12,12 @@ - #define LAST_DEVICE_VECTOR 232 - #define MSI_TARGET_CPU_SHIFT 12 - -+extern struct msi_ops msi_apic_ops; -+ -+static inline int msi_arch_init(void) -+{ -+ msi_register(&msi_apic_ops); -+ return 0; -+} -+ - #endif /* ASM_MSI_H */ ---- gregkh-2.6.orig/include/asm-ia64/machvec.h -+++ gregkh-2.6/include/asm-ia64/machvec.h -@@ -74,6 +74,7 @@ typedef unsigned char ia64_mv_readb_rela - typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *); - typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *); - typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *); -+typedef int ia64_mv_msi_init_t (void); - - static inline void - machvec_noop (void) -@@ -146,6 +147,7 @@ extern void machvec_tlb_migrate_finish ( - # define platform_readw_relaxed ia64_mv.readw_relaxed - # define platform_readl_relaxed ia64_mv.readl_relaxed - # define platform_readq_relaxed ia64_mv.readq_relaxed -+# define platform_msi_init ia64_mv.msi_init - # endif - - /* __attribute__((__aligned__(16))) is required to make size of the -@@ -194,6 +196,7 @@ struct ia64_machine_vector { - ia64_mv_readw_relaxed_t *readw_relaxed; - ia64_mv_readl_relaxed_t *readl_relaxed; - ia64_mv_readq_relaxed_t *readq_relaxed; -+ ia64_mv_msi_init_t *msi_init; - } __attribute__((__aligned__(16))); /* align attrib? see above comment */ - - #define MACHVEC_INIT(name) \ -@@ -238,6 +241,7 @@ struct ia64_machine_vector { - platform_readw_relaxed, \ - platform_readl_relaxed, \ - platform_readq_relaxed, \ -+ platform_msi_init, \ - } - - extern struct ia64_machine_vector ia64_mv; -@@ -386,5 +390,13 @@ extern ia64_mv_dma_supported swiotlb_dm - #ifndef platform_readq_relaxed - # define platform_readq_relaxed __ia64_readq_relaxed - #endif -+#ifndef platform_msi_init -+#ifdef CONFIG_PCI_MSI -+#include <asm/msi.h> /* pull in ia64_msi_init() */ -+# define platform_msi_init ia64_msi_init -+#else -+# define platform_msi_init NULL -+#endif /* CONFIG_PCI_MSI */ -+#endif - - #endif /* _ASM_IA64_MACHVEC_H */ ---- gregkh-2.6.orig/include/asm-ia64/machvec_sn2.h -+++ gregkh-2.6/include/asm-ia64/machvec_sn2.h -@@ -66,6 +66,7 @@ extern ia64_mv_dma_sync_single_for_devic - extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device; - extern ia64_mv_dma_mapping_error sn_dma_mapping_error; - extern ia64_mv_dma_supported sn_dma_supported; -+extern ia64_mv_msi_init_t sn_msi_init; - - /* - * This stuff has dual use! -@@ -115,6 +116,11 @@ extern ia64_mv_dma_supported sn_dma_sup - #define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device - #define platform_dma_mapping_error sn_dma_mapping_error - #define platform_dma_supported sn_dma_supported -+#ifdef CONFIG_PCI_MSI -+#define platform_msi_init sn_msi_init -+#else -+#define platform_msi_init NULL -+#endif - - #include <asm/sn/io.h> - ---- gregkh-2.6.orig/include/asm-ia64/msi.h -+++ gregkh-2.6/include/asm-ia64/msi.h -@@ -14,4 +14,15 @@ static inline void set_intr_gate (int nr - #define ack_APIC_irq ia64_eoi - #define MSI_TARGET_CPU_SHIFT 4 - -+extern struct msi_ops msi_apic_ops; -+ -+/* default ia64 msi init routine */ -+static inline int ia64_msi_init(void) -+{ -+ msi_register(&msi_apic_ops); -+ return 0; -+} -+ -+#define msi_arch_init platform_msi_init /* in asm/machvec.h */ -+ - #endif /* ASM_MSI_H */ ---- gregkh-2.6.orig/include/asm-x86_64/msi.h -+++ gregkh-2.6/include/asm-x86_64/msi.h -@@ -13,4 +13,12 @@ - #define LAST_DEVICE_VECTOR 232 - #define MSI_TARGET_CPU_SHIFT 12 - -+extern struct msi_ops msi_apic_ops; -+ -+static inline int msi_arch_init(void) -+{ -+ msi_register(&msi_apic_ops); -+ return 0; -+} -+ - #endif /* ASM_MSI_H */ diff --git a/pci/pci-clean-up-msi.c-a-bit.patch b/pci/pci-clean-up-msi.c-a-bit.patch index 34c2a4e3af7b7..8628e0fe8df26 100644 --- a/pci/pci-clean-up-msi.c-a-bit.patch +++ b/pci/pci-clean-up-msi.c-a-bit.patch @@ -21,13 +21,13 @@ Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- - drivers/pci/msi.c | 58 ++++++++++++++++++++++++++++++++++-------------------- + drivers/pci/msi.c | 55 ++++++++++++++++++++++++++++++++++-------------------- drivers/pci/pci.c | 5 +--- - 2 files changed, 39 insertions(+), 24 deletions(-) + 2 files changed, 37 insertions(+), 23 deletions(-) --- gregkh-2.6.orig/drivers/pci/msi.c +++ gregkh-2.6/drivers/pci/msi.c -@@ -109,9 +109,9 @@ static void set_msi_affinity(unsigned in +@@ -103,9 +103,9 @@ static void set_msi_affinity(unsigned in switch (entry->msi_attrib.type) { case PCI_CAP_ID_MSI: { @@ -38,8 +38,8 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + if (!pos) return; - pci_read_config_dword(entry->dev, msi_upper_address_reg(pos), -@@ -337,9 +337,9 @@ static int assign_msi_vector(void) + pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), +@@ -347,9 +347,9 @@ static int assign_msi_vector(void) static int get_new_vector(void) { @@ -51,17 +51,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> set_intr_gate(vector, interrupt[vector]); return vector; -@@ -359,7 +359,8 @@ static int msi_init(void) - return status; - } - -- if ((status = msi_arch_init()) < 0) { -+ status = msi_arch_init(); -+ if (status < 0) { - pci_msi_enable = 0; - printk(KERN_WARNING - "PCI: MSI arch init failed. MSI disabled.\n"); -@@ -373,7 +374,8 @@ static int msi_init(void) +@@ -369,7 +369,8 @@ static int msi_init(void) return status; } @@ -71,7 +61,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> pci_msi_enable = 0; printk(KERN_WARNING "PCI: MSI cache init failed\n"); return status; -@@ -534,10 +536,12 @@ static int msi_capability_init(struct pc +@@ -523,10 +524,12 @@ static int msi_capability_init(struct pc pos = pci_find_capability(dev, PCI_CAP_ID_MSI); pci_read_config_word(dev, msi_control_reg(pos), &control); /* MSI Entry Initialization */ @@ -86,7 +76,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> kmem_cache_free(msi_cachep, entry); return -EBUSY; } -@@ -637,7 +641,8 @@ static int msix_capability_init(struct p +@@ -620,7 +623,8 @@ static int msix_capability_init(struct p entry = alloc_msi_entry(); if (!entry) break; @@ -96,7 +86,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> break; j = entries[i].entry; -@@ -720,10 +725,12 @@ int pci_enable_msi(struct pci_dev* dev) +@@ -701,10 +705,12 @@ int pci_enable_msi(struct pci_dev* dev) temp = dev->irq; @@ -111,7 +101,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> return -EINVAL; pci_read_config_word(dev, msi_control_reg(pos), &control); -@@ -747,8 +754,8 @@ int pci_enable_msi(struct pci_dev* dev) +@@ -728,8 +734,8 @@ int pci_enable_msi(struct pci_dev* dev) dev->irq = temp; } /* Check whether driver already requested for MSI-X vectors */ @@ -122,7 +112,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> printk(KERN_INFO "PCI: %s: Can't enable MSI. " "Device already has MSI-X vectors assigned\n", pci_name(dev)); -@@ -774,7 +781,10 @@ void pci_disable_msi(struct pci_dev* dev +@@ -755,7 +761,10 @@ void pci_disable_msi(struct pci_dev* dev u16 control; unsigned long flags; @@ -134,7 +124,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> return; pci_read_config_word(dev, msi_control_reg(pos), &control); -@@ -945,10 +955,12 @@ int pci_enable_msix(struct pci_dev* dev, +@@ -924,10 +933,12 @@ int pci_enable_msix(struct pci_dev* dev, if (!pci_msi_enable || !dev || !entries) return -EINVAL; @@ -149,7 +139,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> return -EINVAL; pci_read_config_word(dev, msi_control_reg(pos), &control); -@@ -1027,7 +1039,11 @@ void pci_disable_msix(struct pci_dev* de +@@ -1006,7 +1017,11 @@ void pci_disable_msix(struct pci_dev* de int pos, temp; u16 control; @@ -162,7 +152,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> return; pci_read_config_word(dev, msi_control_reg(pos), &control); -@@ -1087,8 +1103,8 @@ void msi_remove_pci_irq_vectors(struct p +@@ -1066,8 +1081,8 @@ void msi_remove_pci_irq_vectors(struct p return; temp = dev->irq; /* Save IOAPIC IRQ */ @@ -173,7 +163,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> spin_lock_irqsave(&msi_lock, flags); state = msi_desc[dev->irq]->msi_attrib.state; spin_unlock_irqrestore(&msi_lock, flags); -@@ -1101,8 +1117,8 @@ void msi_remove_pci_irq_vectors(struct p +@@ -1080,8 +1095,8 @@ void msi_remove_pci_irq_vectors(struct p msi_free_vector(dev, dev->irq, 0); dev->irq = temp; /* Restore IOAPIC IRQ */ } diff --git a/pci/pci-fix-msi-build-breakage-in-x86_64.patch b/pci/pci-fix-msi-build-breakage-in-x86_64.patch deleted file mode 100644 index ea83ebec42c14..0000000000000 --- a/pci/pci-fix-msi-build-breakage-in-x86_64.patch +++ /dev/null @@ -1,47 +0,0 @@ -From akpm@osdl.org Sun Jan 22 23:29:50 2006 -Message-Id: <200601230729.k0N7TdKi012213@shell0.pdx.osdl.net> -From: Chuck Ebbert <76306.1226@compuserve.com> -Subject: PCI: fix MSI build breakage in x86_64 -To: 76306.1226@compuserve.com, gregkh@suse.de, maule@sgi.com -Date: Sun, 22 Jan 2006 23:29:23 -0800 - - -gregkh-pci-msi-vector-targeting-abstractions.patch breaks msi on x86_64: - -In file included from include/asm/msi.h:11, - from drivers/pci/msi.h:9, - from drivers/pci/msi-apic.c:15: -include/asm/smp.h:103: error: syntax error before ‘->’ token - -include/asm-x86_64/msi.h:#include <asm/mach_apic.h> - -include/asm-x86_64/mach_apic.h:#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid) - -include/asm-x86_64/smp.h:103:static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) - -drivers/pci/msi.c does not have this problem because it includes <asm/smp.h> -_before_ "msi.h" so the #define overrides the inline function. - -Ugly patch to fix this follows... at least it compiles now... - -Fix msi on x86_64, broken due to include-ordering problems. - -Signed-off-by: Chuck Ebbert <76306.1226@compuserve.com> -Cc: Mark Maule <maule@sgi.com> -Signed-off-by: Andrew Morton <akpm@osdl.org> -Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> ---- - drivers/pci/msi-apic.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- gregkh-2.6.orig/drivers/pci/msi-apic.c -+++ gregkh-2.6/drivers/pci/msi-apic.c -@@ -11,6 +11,8 @@ - #include <linux/pci.h> - #include <linux/irq.h> - -+#include <asm/smp.h> -+ - #include "pci.h" - #include "msi.h" - diff --git a/pci/pci-fix-problems-with-msi-x-on-ia64.patch b/pci/pci-fix-problems-with-msi-x-on-ia64.patch index e42d7e79db720..e6676ec178a00 100644 --- a/pci/pci-fix-problems-with-msi-x-on-ia64.patch +++ b/pci/pci-fix-problems-with-msi-x-on-ia64.patch @@ -32,9 +32,9 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- gregkh-2.6.orig/drivers/pci/msi.c +++ gregkh-2.6/drivers/pci/msi.c -@@ -805,7 +805,8 @@ static int msix_capability_init(struct p - u32 address_lo; - u32 data; +@@ -784,7 +784,8 @@ static int msix_capability_init(struct p + struct msg_address address; + struct msg_data data; int vector, pos, i, j, nr_entries, temp = 0; - u32 phys_addr, table_offset; + unsigned long phys_addr; @@ -42,7 +42,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> u16 control; u8 bir; void __iomem *base; -@@ -815,11 +816,11 @@ static int msix_capability_init(struct p +@@ -793,11 +794,11 @@ static int msix_capability_init(struct p /* Request & Map MSI-X table region */ pci_read_config_word(dev, msi_control_reg(pos), &control); nr_entries = multi_msix_capable(control); @@ -58,7 +58,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); if (base == NULL) return -ENOMEM; -@@ -1059,8 +1060,10 @@ static int msi_free_vector(struct pci_de +@@ -1033,8 +1034,10 @@ static int msi_free_vector(struct pci_de * Detect last MSI-X vector to be released. * Release the MSI-X memory-mapped table. */ @@ -70,7 +70,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> u16 control; u8 bir; -@@ -1071,9 +1074,12 @@ static int msi_free_vector(struct pci_de +@@ -1045,9 +1048,12 @@ static int msi_free_vector(struct pci_de pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); @@ -86,7 +86,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> iounmap(base); } } -@@ -1340,7 +1346,9 @@ void msi_remove_pci_irq_vectors(struct p +@@ -1314,7 +1320,9 @@ void msi_remove_pci_irq_vectors(struct p msi_free_vector(dev, vector, 0); if (warning) { /* Force to release the MSI-X memory-mapped table */ @@ -97,7 +97,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> u16 control; u8 bir; -@@ -1349,9 +1357,12 @@ void msi_remove_pci_irq_vectors(struct p +@@ -1323,9 +1331,12 @@ void msi_remove_pci_irq_vectors(struct p pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); diff --git a/pci/pci-make-msi-quirk-inheritable-from-the-pci-bus.patch b/pci/pci-make-msi-quirk-inheritable-from-the-pci-bus.patch index 54c013ce7e6d0..af6c8c28d5a6a 100644 --- a/pci/pci-make-msi-quirk-inheritable-from-the-pci-bus.patch +++ b/pci/pci-make-msi-quirk-inheritable-from-the-pci-bus.patch @@ -22,7 +22,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- gregkh-2.6.orig/drivers/pci/msi.c +++ gregkh-2.6/drivers/pci/msi.c -@@ -723,6 +723,9 @@ int pci_enable_msi(struct pci_dev* dev) +@@ -703,6 +703,9 @@ int pci_enable_msi(struct pci_dev* dev) if (dev->no_msi) return status; diff --git a/pci/pci-msi-save-restore-for-suspend-resume.patch b/pci/pci-msi-save-restore-for-suspend-resume.patch index 0bb2d18c0ba47..aec8d4575c324 100644 --- a/pci/pci-msi-save-restore-for-suspend-resume.patch +++ b/pci/pci-msi-save-restore-for-suspend-resume.patch @@ -11,15 +11,15 @@ Add MSI(X) configure space save/restore in generic PCI helper. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- - drivers/pci/msi.c | 261 +++++++++++++++++++++++++++++++++++++++++++++------- + drivers/pci/msi.c | 255 +++++++++++++++++++++++++++++++++++++++++++++------- drivers/pci/pci.c | 9 + drivers/pci/pci.h | 12 ++ include/linux/pci.h | 31 ++++++ - 4 files changed, 282 insertions(+), 31 deletions(-) + 4 files changed, 277 insertions(+), 30 deletions(-) --- gregkh-2.6.orig/drivers/pci/msi.c +++ gregkh-2.6/drivers/pci/msi.c -@@ -514,6 +514,221 @@ void pci_scan_msi_device(struct pci_dev +@@ -504,6 +504,217 @@ void pci_scan_msi_device(struct pci_dev nr_reserved_vectors++; } @@ -205,11 +205,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + pos = pci_find_capability(dev, PCI_CAP_ID_MSI); + pci_read_config_word(dev, msi_control_reg(pos), &control); + -+ /* Configure MSI capability structure */ -+ status = msi_ops->setup(dev, vector, -+ &address_hi, -+ &address_lo, -+ &data); ++ status = msi_register_init(dev, entry); + if (status < 0) + return status; + @@ -241,42 +237,25 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> /** * msi_capability_init - configure device's MSI capability structure * @dev: pointer to the pci_dev data structure of MSI device function -@@ -527,9 +742,6 @@ static int msi_capability_init(struct pc - { - int status; - struct msi_desc *entry; -- u32 address_lo; -- u32 address_hi; -- u32 data; - int pos, vector; - u16 control; - -@@ -558,11 +770,8 @@ static int msi_capability_init(struct pc - entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, - is_64bit_address(control)); +@@ -548,35 +759,8 @@ static int msi_capability_init(struct pc } -- /* Configure MSI capability structure */ -- status = msi_ops->setup(dev, vector, -- &address_hi, -- &address_lo, -- &data); -+ -+ status = msi_register_init(dev, entry); - if (status < 0) { - dev->irq = entry->msi_attrib.default_vector; - kmem_cache_free(msi_cachep, entry); -@@ -571,27 +780,6 @@ static int msi_capability_init(struct pc /* Replace with MSI handler */ irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); - -- pci_write_config_dword(dev, msi_lower_address_reg(pos), address_lo); +- /* Configure MSI capability structure */ +- msi_address_init(&address); +- msi_data_init(&data, vector); +- entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >> +- MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); +- pci_write_config_dword(dev, msi_lower_address_reg(pos), +- address.lo_address.value); - if (is_64bit_address(control)) { - pci_write_config_dword(dev, -- msi_upper_address_reg(pos), address_hi); -- pci_write_config_word(dev, msi_data_reg(pos, 1), data); +- msi_upper_address_reg(pos), address.hi_address); +- pci_write_config_word(dev, +- msi_data_reg(pos, 1), *((u32*)&data)); - } else -- pci_write_config_word(dev, msi_data_reg(pos, 0), data); -- +- pci_write_config_word(dev, +- msi_data_reg(pos, 0), *((u32*)&data)); - if (entry->msi_attrib.maskbit) { - unsigned int maskbits, temp; - /* All MSIs are unmasked by default, Mask them all */ @@ -291,9 +270,11 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> - maskbits); - } attach_msi_entry(entry, vector); ++ /* Set MSI enabled bits */ enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); -@@ -750,8 +938,19 @@ int pci_enable_msi(struct pci_dev* dev) + +@@ -730,8 +914,19 @@ int pci_enable_msi(struct pci_dev* dev) vector_irq[dev->irq] = -1; nr_released_vectors--; spin_unlock_irqrestore(&msi_lock, flags); @@ -342,8 +323,8 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- gregkh-2.6.orig/drivers/pci/pci.h +++ gregkh-2.6/drivers/pci/pci.h -@@ -57,6 +57,18 @@ static inline void disable_msi_mode(stru - static inline int msi_register(struct msi_ops *ops) { return 0; } +@@ -54,6 +54,18 @@ void disable_msi_mode(struct pci_dev *de + static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { } #endif +#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM) diff --git a/pci/pci-provide-a-boot-parameter-to-disable-msi.patch b/pci/pci-provide-a-boot-parameter-to-disable-msi.patch index 9be5f1f681792..5a3277940c9c0 100644 --- a/pci/pci-provide-a-boot-parameter-to-disable-msi.patch +++ b/pci/pci-provide-a-boot-parameter-to-disable-msi.patch @@ -60,7 +60,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> config PCI_DEBUG --- gregkh-2.6.orig/drivers/pci/msi.c +++ gregkh-2.6/drivers/pci/msi.c -@@ -984,8 +984,11 @@ void pci_disable_msi(struct pci_dev* dev +@@ -960,8 +960,11 @@ void pci_disable_msi(struct pci_dev* dev u16 control; unsigned long flags; @@ -72,7 +72,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> pos = pci_find_capability(dev, PCI_CAP_ID_MSI); if (!pos) return; -@@ -1247,6 +1250,8 @@ void pci_disable_msix(struct pci_dev* de +@@ -1221,6 +1224,8 @@ void pci_disable_msix(struct pci_dev* de int pos, temp; u16 control; @@ -81,7 +81,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> if (!dev) return; -@@ -1373,6 +1378,11 @@ void msi_remove_pci_irq_vectors(struct p +@@ -1347,6 +1352,11 @@ void msi_remove_pci_irq_vectors(struct p } } @@ -112,14 +112,13 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> } --- gregkh-2.6.orig/drivers/pci/pci.h +++ gregkh-2.6/drivers/pci/pci.h -@@ -52,9 +52,11 @@ struct msi_ops; +@@ -50,8 +50,10 @@ extern int pci_msi_quirk; + #ifdef CONFIG_PCI_MSI void disable_msi_mode(struct pci_dev *dev, int pos, int type); - int msi_register(struct msi_ops *ops); +void pci_no_msi(void); #else static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { } - static inline int msi_register(struct msi_ops *ops) { return 0; } +static inline void pci_no_msi(void) { } #endif diff --git a/pci/pci-the-scheduled-removal-of-pci_legacy_proc.patch b/pci/pci-the-scheduled-removal-of-pci_legacy_proc.patch index 2057c78878165..af8d6636509f5 100644 --- a/pci/pci-the-scheduled-removal-of-pci_legacy_proc.patch +++ b/pci/pci-the-scheduled-removal-of-pci_legacy_proc.patch @@ -20,7 +20,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- gregkh-2.6.orig/Documentation/feature-removal-schedule.txt +++ gregkh-2.6/Documentation/feature-removal-schedule.txt -@@ -151,13 +151,6 @@ Who: Ralf Baechle <ralf@linux-mips.org> +@@ -158,13 +158,6 @@ Who: Adrian Bunk <bunk@stusta.de> --------------------------- diff --git a/pci/per-platform-ia64_-first-last-_device_vector-definitions.patch b/pci/per-platform-ia64_-first-last-_device_vector-definitions.patch deleted file mode 100644 index 291d35ba08a51..0000000000000 --- a/pci/per-platform-ia64_-first-last-_device_vector-definitions.patch +++ /dev/null @@ -1,153 +0,0 @@ -From owner-linux-pci@atrey.karlin.mff.cuni.cz Thu Jan 19 11:46:59 2006 -Date: Thu, 19 Jan 2006 13:46:57 -0600 (CST) -From: Mark Maule <maule@sgi.com> -Cc: Tony Luck <tony.luck@intel.com>, gregkh@suse.de, Mark Maule <maule@sgi.com> -Message-Id: <20060119194657.12213.25378.83969@lnx-maule.americas.sgi.com> -Subject: [PATCH 2/3] per-platform IA64_{FIRST,LAST}_DEVICE_VECTOR definitions - -Abstract IA64_FIRST_DEVICE_VECTOR/IA64_LAST_DEVICE_VECTOR since SN platforms -use a subset of the IA64 range. Implement this by making the above macros -global variables which the platform can override in it setup code. - -Also add a reserve_irq_vector() routine used by SN to mark a vector's as -in-use when that weren't allocated through assign_irq_vector(). - -Signed-off-by: Mark Maule <maule@sgi.com> -Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> - ---- - arch/ia64/kernel/irq_ia64.c | 19 ++++++++++++++++++- - arch/ia64/sn/kernel/irq.c | 7 +++++++ - drivers/pci/msi.c | 7 ++++++- - include/asm-ia64/hw_irq.h | 15 +++++++++++++-- - 4 files changed, 44 insertions(+), 4 deletions(-) - ---- gregkh-2.6.orig/arch/ia64/kernel/irq_ia64.c -+++ gregkh-2.6/arch/ia64/kernel/irq_ia64.c -@@ -46,6 +46,10 @@ - - #define IRQ_DEBUG 0 - -+/* These can be overridden in platform_irq_init */ -+int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR; -+int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR; -+ - /* default base addr of IPI table */ - void __iomem *ipi_base_addr = ((void __iomem *) - (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR)); -@@ -60,7 +64,7 @@ __u8 isa_irq_to_vector_map[16] = { - }; - EXPORT_SYMBOL(isa_irq_to_vector_map); - --static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_NUM_DEVICE_VECTORS)]; -+static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_MAX_DEVICE_VECTORS)]; - - int - assign_irq_vector (int irq) -@@ -89,6 +93,19 @@ free_irq_vector (int vector) - printk(KERN_WARNING "%s: double free!\n", __FUNCTION__); - } - -+int -+reserve_irq_vector (int vector) -+{ -+ int pos; -+ -+ if (vector < IA64_FIRST_DEVICE_VECTOR || -+ vector > IA64_LAST_DEVICE_VECTOR) -+ return -EINVAL; -+ -+ pos = vector - IA64_FIRST_DEVICE_VECTOR; -+ return test_and_set_bit(pos, ia64_vector_mask); -+} -+ - #ifdef CONFIG_SMP - # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE) - #else ---- gregkh-2.6.orig/arch/ia64/sn/kernel/irq.c -+++ gregkh-2.6/arch/ia64/sn/kernel/irq.c -@@ -202,6 +202,9 @@ void sn_irq_init(void) - int i; - irq_desc_t *base_desc = irq_desc; - -+ ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; -+ ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; -+ - for (i = 0; i < NR_IRQS; i++) { - if (base_desc[i].handler == &no_irq_type) { - base_desc[i].handler = &irq_type_sn; -@@ -285,6 +288,7 @@ void sn_irq_fixup(struct pci_dev *pci_de - /* link it into the sn_irq[irq] list */ - spin_lock(&sn_irq_info_lock); - list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]); -+ reserve_irq_vector(sn_irq_info->irq_irq); - spin_unlock(&sn_irq_info_lock); - - register_intr_pda(sn_irq_info); -@@ -310,8 +314,11 @@ void sn_irq_unfixup(struct pci_dev *pci_ - spin_lock(&sn_irq_info_lock); - list_del_rcu(&sn_irq_info->list); - spin_unlock(&sn_irq_info_lock); -+ if (list_empty(sn_irq_lh[sn_irq_info->irq_irq])) -+ free_irq_vector(sn_irq_info->irq_irq); - call_rcu(&sn_irq_info->rcu, sn_irq_info_free); - pci_dev_put(pci_dev); -+ - } - - static inline void ---- gregkh-2.6.orig/drivers/pci/msi.c -+++ gregkh-2.6/drivers/pci/msi.c -@@ -35,7 +35,7 @@ static int nr_msix_devices; - - #ifndef CONFIG_X86_IO_APIC - int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; --u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 }; -+u8 irq_vector[NR_IRQ_VECTORS]; - #endif - - static struct msi_ops *msi_ops; -@@ -378,6 +378,11 @@ static int msi_init(void) - printk(KERN_WARNING "PCI: MSI cache init failed\n"); - return status; - } -+ -+#ifndef CONFIG_X86_IO_APIC -+ irq_vector[0] = FIRST_DEVICE_VECTOR; -+#endif -+ - last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); - if (last_alloc_vector < 0) { - pci_msi_enable = 0; ---- gregkh-2.6.orig/include/asm-ia64/hw_irq.h -+++ gregkh-2.6/include/asm-ia64/hw_irq.h -@@ -47,9 +47,19 @@ typedef u8 ia64_vector; - #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ - /* - * Vectors 0x20-0x2f are reserved for legacy ISA IRQs. -+ * Use vectors 0x30-0xe7 as the default device vector range for ia64. -+ * Platforms may choose to reduce this range in platform_irq_setup, but the -+ * platform range must fall within -+ * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] - */ --#define IA64_FIRST_DEVICE_VECTOR 0x30 --#define IA64_LAST_DEVICE_VECTOR 0xe7 -+extern int ia64_first_device_vector; -+extern int ia64_last_device_vector; -+ -+#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 -+#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 -+#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector -+#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector -+#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) - #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) - - #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ -@@ -83,6 +93,7 @@ extern struct hw_interrupt_type irq_type - - extern int assign_irq_vector (int irq); /* allocate a free vector */ - extern void free_irq_vector (int vector); -+extern int reserve_irq_vector (int vector); - extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); - extern void register_percpu_irq (ia64_vector vec, struct irqaction *action); - |