more patches added

2 files changed, 175 insertions, 0 deletions

diff --git a/pci/pci-fix-issues-with-extended-conf-space-when-mmconfig-disabled-because-of-e820.patch b/pci/pci-fix-issues-with-extended-conf-space-when-mmconfig-disabled-because-of-e820.patch
new file mode 100644
index 0000000000000..229ba2aa0e14a
--- /dev/null
+++ b/pci/pci-fix-issues-with-extended-conf-space-when-mmconfig-disabled-because-of-e820.patch
@@ -0,0 +1,113 @@
+From 76306.1226@compuserve.com Thu Jun 15 01:45:12 2006
+Date: Thu, 15 Jun 2006 04:41:52 -0400
+From: Chuck Ebbert <76306.1226@compuserve.com>
+Subject: PCI: fix issues with extended conf space when MMCONFIG disabled because of e820
+To: Andi Kleen <ak@suse.de>
+Cc: Brice Goglin <brice@myri.com>, Arjan van de Ven <arjan@linux.intel.com>, Greg KH <greg@kroah.com>
+Message-ID: <200606150443_MC3-1-C283-D4F7@compuserve.com>
+Content-Disposition: inline
+
+On 15 Jun 2006 03:45:10 +0200, Andi Kleen wrote:
+
+> Anyways I would say that if the BIOS can't get MCFG right then 
+> it's likely not been validated on that board and shouldn't be used.
+
+According to Petr Vandrovec:
+
+ ... "What is important (and checked) is address of MMCONFIG reported by MCFG
+ table...  Unfortunately code does not bother with printing that address :-(
+ 
+ "Another problem is that code has hardcoded that MMCONFIG area is 256MB large. 
+ Unfortunately for the code PCI specification allows any power of two between 2MB 
+ and 256MB if vendor knows that such amount of busses (from 2 to 128) will be 
+ sufficient for system.  With notebook it is quite possible that not full 8 bits 
+ are implemented for MMCONFIG bus number."
+
+
+So here is a patch.  Unfortunately my system still fails the test because
+it doesn't reserve any part of the MMCONFIG area, but this may fix others.
+
+Booted on x86_64, only compiled on i386.  x86_64 still remaps the max area
+(256MB) even though only 2MB is checked... but 2.6.16 had no check at all
+so it is still better.
+
+
+PCI: reduce size of x86 MMCONFIG reserved area check
+
+1.  Print the address of the MMCONFIG area when the test for that area
+    being reserved fails.
+
+2.  Only check if the first 2MB is reserved, as that is the minimum.
+
+Signed-off-by: Chuck Ebbert <76306.1226@compuserve.com>
+Acked-by: Arjan van de Ven <arjan@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/i386/pci/mmconfig.c   |    9 ++++++---
+ arch/x86_64/pci/mmconfig.c |   13 +++++++++----
+ 2 files changed, 15 insertions(+), 7 deletions(-)
+
+--- gregkh-2.6.orig/arch/i386/pci/mmconfig.c
++++ gregkh-2.6/arch/i386/pci/mmconfig.c
+@@ -15,7 +15,9 @@
+ #include <asm/e820.h>
+ #include "pci.h"
+ 
+-#define MMCONFIG_APER_SIZE (256*1024*1024)
++/* aperture is up to 256MB but BIOS may reserve less */
++#define MMCONFIG_APER_MIN	(2 * 1024*1024)
++#define MMCONFIG_APER_MAX	(256 * 1024*1024)
+ 
+ /* Assume systems with more busses have correct MCFG */
+ #define MAX_CHECK_BUS 16
+@@ -197,9 +199,10 @@ void __init pci_mmcfg_init(void)
+ 		return;
+ 
+ 	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
+-			pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
++			pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
+ 			E820_RESERVED)) {
+-		printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
++		printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
++				pci_mmcfg_config[0].base_address);
+ 		printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
+ 		return;
+ 	}
+--- gregkh-2.6.orig/arch/x86_64/pci/mmconfig.c
++++ gregkh-2.6/arch/x86_64/pci/mmconfig.c
+@@ -13,7 +13,10 @@
+ 
+ #include "pci.h"
+ 
+-#define MMCONFIG_APER_SIZE (256*1024*1024)
++/* aperture is up to 256MB but BIOS may reserve less */
++#define MMCONFIG_APER_MIN	(2 * 1024*1024)
++#define MMCONFIG_APER_MAX	(256 * 1024*1024)
++
+ /* Verify the first 16 busses. We assume that systems with more busses
+    get MCFG right. */
+ #define MAX_CHECK_BUS 16
+@@ -175,9 +178,10 @@ void __init pci_mmcfg_init(void)
+ 		return;
+ 
+ 	if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
+-			pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
++			pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
+ 			E820_RESERVED)) {
+-		printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
++		printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
++				pci_mmcfg_config[0].base_address);
+ 		printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
+ 		return;
+ 	}
+@@ -190,7 +194,8 @@ void __init pci_mmcfg_init(void)
+ 	}
+ 	for (i = 0; i < pci_mmcfg_config_num; ++i) {
+ 		pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
+-		pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
++		pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address,
++							 MMCONFIG_APER_MAX);
+ 		if (!pci_mmcfg_virt[i].virt) {
+ 			printk("PCI: Cannot map mmconfig aperture for segment %d\n",
+ 			       pci_mmcfg_config[i].pci_segment_group_number);
diff --git a/pci/pci-nvidia-quirk-to-make-aer-pci-e-extended-capability-visible.patch b/pci/pci-nvidia-quirk-to-make-aer-pci-e-extended-capability-visible.patch
new file mode 100644
index 0000000000000..d749d57d0de59
--- /dev/null
+++ b/pci/pci-nvidia-quirk-to-make-aer-pci-e-extended-capability-visible.patch
@@ -0,0 +1,62 @@
+From brice@myri.com Tue Jun 13 11:36:06 2006
+Message-ID: <448F057E.1040104@myri.com>
+Date: Tue, 13 Jun 2006 14:35:42 -0400
+From: Brice Goglin <brice@myri.com>
+To: Greg KH <gregkh@suse.de>
+Subject: PCI: nVidia quirk to make AER PCI-E extended capability visible
+
+The nVidia CK804 PCI-E chipset supports the AER extended capability
+but sometimes fails to link it (with some BIOS or after a warm reboot).
+It makes the AER cap invisible to pci_find_ext_capability().
+
+The patch adds a quirk to set the missing bit that controls the
+linking of the capability.
+By the way, it removes the corresponding code in the myri10ge driver.
+
+Signed-off-by: Brice Goglin <brice@myri.com>
+Signed-off-by: Loic Prylli <loic@myri.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/pci/quirks.c    |   19 +++++++++++++++++++
+ include/linux/pci_ids.h |    1 +
+ 2 files changed, 20 insertions(+)
+
+--- gregkh-2.6.orig/drivers/pci/quirks.c
++++ gregkh-2.6/drivers/pci/quirks.c
+@@ -1499,6 +1499,25 @@ static void __devinit quirk_p64h2_1k_io(
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	0x1460,		quirk_p64h2_1k_io);
+ 
++/* Under some circumstances, AER is not linked with extended capabilities.
++ * Force it to be linked by setting the corresponding control bit in the
++ * config space.
++ */
++static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
++{
++	uint8_t b;
++	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
++		if (!(b & 0x20)) {
++			pci_write_config_byte(dev, 0xf41, b | 0x20);
++			printk(KERN_INFO
++			       "PCI: Linking AER extended capability on %s\n",
++			       pci_name(dev));
++		}
++	}
++}
++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
++			quirk_nvidia_ck804_pcie_aer_ext_cap);
++
+ EXPORT_SYMBOL(pcie_mch_quirk);
+ #ifdef CONFIG_HOTPLUG
+ EXPORT_SYMBOL(pci_fixup_device);
+--- gregkh-2.6.orig/include/linux/pci_ids.h
++++ gregkh-2.6/include/linux/pci_ids.h
+@@ -1025,6 +1025,7 @@
+ #define PCI_DEVICE_ID_NVIDIA_NVENET_8		0x0056
+ #define PCI_DEVICE_ID_NVIDIA_NVENET_9		0x0057
+ #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
++#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE		0x005d
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
+ #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+ #define PCI_DEVICE_ID_NVIDIA_NVENET_2		0x0066