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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:41 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:14 -0700 |
| commit | 9b464e19669de574b7a659c97bdd5be913d63c98 (patch) | |
| tree | 591ccd7a7da6860e2c5cebfa6b010e70b0e433d5 | |
| parent | 7d51e7e2e08f6503bf76c7477edd86532845f831 (diff) | |
| download | devicetree-rebasing-9b464e19669de574b7a659c97bdd5be913d63c98.tar.gz | |
riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
The Andes hart-level interrupt controller (Andes INTC) allows AX45MP
cores to handle custom local interrupts, such as the performance
counter overflow interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222083946.3977135-6-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[ upstream commit: 95113bb705157f3518cec4ff0225a922507a0f8b ]
| -rw-r--r-- | src/riscv/renesas/r9a07g043f.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/riscv/renesas/r9a07g043f.dtsi b/src/riscv/renesas/r9a07g043f.dtsi index a92cfcfc021b4c..099f3df75b4237 100644 --- a/src/riscv/renesas/r9a07g043f.dtsi +++ b/src/riscv/renesas/r9a07g043f.dtsi @@ -39,7 +39,7 @@ cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; |