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authorEli Cohen <eli@mellanox.co.il>2008-01-14 15:53:29 +0200
committerRoland Dreier <rolandd@cisco.com>2008-01-14 13:29:05 -0800
commit063b9070bb4f9f0a9789f96dd4166eaae248bb25 (patch)
treeb697d848060429c8918cfdf7bb17ee0727a18454
parent3a89c5cb9f6a31f3f192ff5ac087e7cb3aa89fc7 (diff)
downloadlibmthca-063b9070bb4f9f0a9789f96dd4166eaae248bb25.tar.gz
Ensure an receive WQEs are in memory before linking to chain
Use a write memory barrier to ensure that a receive WQE is fully written to memory before linking it to the previous WQE. Signed-off-by: Eli Cohen <eli@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
-rw-r--r--src/qp.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/qp.c b/src/qp.c
index 2ea9dc0..3d18071 100644
--- a/src/qp.c
+++ b/src/qp.c
@@ -390,6 +390,7 @@ int mthca_tavor_post_recv(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
((struct mthca_next_seg *) prev_wqe)->nda_op =
htonl((ind << qp->rq.wqe_shift) | 1);
+ wmb();
((struct mthca_next_seg *) prev_wqe)->ee_nds =
htonl(MTHCA_NEXT_DBD | size);