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author | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2020-07-07 03:12:39 +0200 |
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committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2020-07-07 03:12:39 +0200 |
commit | d92121c266d18a11cb734bdb32825d09c5f68a64 (patch) | |
tree | 7188d0506faddfe2ce70e52b548570e6d12ea1d1 | |
parent | cc0592e1e3dadad96826cfc404cf68f3e69b500d (diff) | |
download | sparse-d92121c266d18a11cb734bdb32825d09c5f68a64.tar.gz |
riscv: add the predefines for the extensions
The RISC-V architecture has some predefined macros
to specify which extensions are supported.
So, now that these extensions are known via the '-march'
options, add the corresponding predefines.
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
-rw-r--r-- | target-riscv.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/target-riscv.c b/target-riscv.c index 9431ebc9..e7f2b03b 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -99,6 +99,25 @@ static void predefine_riscv(const struct target *self) predefine("__riscv", 1, "1"); predefine("__riscv_xlen", 1, "%d", ptr_ctype.bit_size); + if (riscv_flags & RISCV_ATOMIC) + predefine("__riscv_atomic", 1, "1"); + if (riscv_flags & RISCV_COMP) + predefine("__riscv_compressed", 1, "1"); + if (riscv_flags & RISCV_DIV) + predefine("__riscv_div", 1, "1"); + if (riscv_flags & RISCV_EMBD) + predefine("__riscv_32e", 1, "1"); + if (riscv_flags & RISCV_FPU) + predefine("__riscv_flen", 1, "%d", (riscv_flags & RISCV_DOUBLE) ? 64 : 32); + if (riscv_flags & RISCV_FDIV) + predefine("__riscv_fdiv", 1, "1"); + if (riscv_flags & RISCV_FDIV) + predefine("__riscv_fsqrt", 1, "1"); + if (riscv_flags & RISCV_MUL) + predefine("__riscv_mul", 1, "1"); + if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV)) + predefine("__riscv_muldiv", 1, "1"); + if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); } |