From d92121c266d18a11cb734bdb32825d09c5f68a64 Mon Sep 17 00:00:00 2001 From: Luc Van Oostenryck Date: Tue, 7 Jul 2020 03:12:39 +0200 Subject: riscv: add the predefines for the extensions The RISC-V architecture has some predefined macros to specify which extensions are supported. So, now that these extensions are known via the '-march' options, add the corresponding predefines. Signed-off-by: Luc Van Oostenryck --- target-riscv.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target-riscv.c b/target-riscv.c index 9431ebc9..e7f2b03b 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -99,6 +99,25 @@ static void predefine_riscv(const struct target *self) predefine("__riscv", 1, "1"); predefine("__riscv_xlen", 1, "%d", ptr_ctype.bit_size); + if (riscv_flags & RISCV_ATOMIC) + predefine("__riscv_atomic", 1, "1"); + if (riscv_flags & RISCV_COMP) + predefine("__riscv_compressed", 1, "1"); + if (riscv_flags & RISCV_DIV) + predefine("__riscv_div", 1, "1"); + if (riscv_flags & RISCV_EMBD) + predefine("__riscv_32e", 1, "1"); + if (riscv_flags & RISCV_FPU) + predefine("__riscv_flen", 1, "%d", (riscv_flags & RISCV_DOUBLE) ? 64 : 32); + if (riscv_flags & RISCV_FDIV) + predefine("__riscv_fdiv", 1, "1"); + if (riscv_flags & RISCV_FDIV) + predefine("__riscv_fsqrt", 1, "1"); + if (riscv_flags & RISCV_MUL) + predefine("__riscv_mul", 1, "1"); + if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV)) + predefine("__riscv_muldiv", 1, "1"); + if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); } -- cgit 1.2.3-korg