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| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2012-09-01 17:12:56 +0200 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2012-09-03 12:04:56 -0400 |
| commit | 9de339d1f59d0be7ddc3e86e4a4fa466bf871f83 (patch) | |
| tree | 396ead8b898edde11f93abded0bf4cc3fd41a5da | |
| parent | 0155aef19a1478d2e30efa4ef96c7fba104ed296 (diff) | |
| download | seabios-9de339d1f59d0be7ddc3e86e4a4fa466bf871f83.tar.gz | |
Add framebuffer size detection
It is possible to read out the framebuffer size via msr. The size
information is needed for VESA later.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| -rw-r--r-- | vgasrc/geodevga.c | 27 | ||||
| -rw-r--r-- | vgasrc/geodevga.h | 1 |
2 files changed, 28 insertions, 0 deletions
diff --git a/vgasrc/geodevga.c b/vgasrc/geodevga.c index ae606a7..636d55b 100644 --- a/vgasrc/geodevga.c +++ b/vgasrc/geodevga.c @@ -106,6 +106,30 @@ static int legacyio_check(void) return ret; } +static u32 framebuffer_size(void) +{ + u32 val; + union u64_u32_u msr; + + /* We use the P2D_R0 msr to read out the number of pages. + * One page has a size of 4k + * + * Bit Name Description + * 39:20 PMAX Physical Memory Address Max + * 19:0 PMIX Physical Memory Address Min + * + */ + msr = geode_msrRead(GLIU0_P2D_RO); + + u32 pmax = ((msr.hi & 0xff) << 12) | ((msr.lo & 0xfff00000) >> 20); + u32 pmin = (msr.lo & 0x000fffff); + + val = pmax - pmin; + val += 1; + + /* The page size is 4k */ + return (val << 12); +} /**************************************************************** * Init Functions @@ -140,6 +164,9 @@ static int dc_setup(void) geode_memWrite(dc_base + DC_UNLOCK, 0x0, DC_LOCK_LOCK); + u32 fb_size = framebuffer_size(); // in byte + dprintf(1, "%d KB of video memory at 0x%08x\n", fb_size / 1024, fb); + return 0; } diff --git a/vgasrc/geodevga.h b/vgasrc/geodevga.h index 7098037..14e33d6 100644 --- a/vgasrc/geodevga.h +++ b/vgasrc/geodevga.h @@ -26,6 +26,7 @@ #define MSR_GLIU0 (1 << 28) #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* LX */ #define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) /* GX2 */ +#define GLIU0_P2D_RO (MSR_GLIU0 + 0x29) #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) #define DC_SPARE 0x80000011 |