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authorDan Williams <dan.j.williams@intel.com>2022-04-28 15:10:42 -0700
committerVishal Verma <vishal.l.verma@intel.com>2022-06-15 16:28:51 -0600
commitcf0e0586bf45fd7e4ab17ce2b234bf68995daca3 (patch)
tree678ae79b146cae5c37004e11b61dfcf1d16749a3
parent2dbe3b45879ad614968a75392cb1ef9907d8648d (diff)
cxl/list: Add support for filtering by host identifiers
Accept host device names as valid filters for memdevs, ports, and endpoints. # cxl list -u -m 7 { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } # cxl list -u -m cxl_mem.6 { "memdev":"mem7", "pmem_size":"256.00 MiB (268.44 MB)", "ram_size":"256.00 MiB (268.44 MB)", "serial":"0x6", "numa_node":0, "host":"cxl_mem.6" } Link: https://lore.kernel.org/r/165118384289.1676208.4779565283924668304.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
-rw-r--r--cxl/filter.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/cxl/filter.c b/cxl/filter.c
index c6ab9eb5..66fd7420 100644
--- a/cxl/filter.c
+++ b/cxl/filter.c
@@ -73,6 +73,9 @@ struct cxl_endpoint *util_cxl_endpoint_filter(struct cxl_endpoint *endpoint,
if (strcmp(arg, cxl_endpoint_get_devname(endpoint)) == 0)
break;
+
+ if (strcmp(arg, cxl_endpoint_get_host(endpoint)) == 0)
+ break;
}
free(ident);
@@ -116,6 +119,9 @@ static struct cxl_port *__util_cxl_port_filter(struct cxl_port *port,
if (strcmp(arg, cxl_port_get_devname(port)) == 0)
break;
+
+ if (strcmp(arg, cxl_port_get_host(port)) == 0)
+ break;
}
free(ident);
@@ -303,6 +309,9 @@ struct cxl_memdev *util_cxl_memdev_filter(struct cxl_memdev *memdev,
if (strcmp(name, cxl_memdev_get_devname(memdev)) == 0)
break;
+
+ if (strcmp(name, cxl_memdev_get_host(memdev)) == 0)
+ break;
}
free(ident);