Here's the main MIPS pull request for v5.1:

- Support for the MIPSr6 MemoryMapID register & Global INValidate TLB
  (GINVT) instructions, allowing for more efficient TLB maintenance when
  running on a CPU such as the I6500 that supports these.

- Enable huge page support for MIPS64r6.

- Optimize post-DMA cache sync by removing that code entirely for kernel
  configurations in which we know it won't be needed.

- The number of pages allocated for interrupt stacks is now calculated
  correctly, where before we would wastefully allocate too much memory
  in some configurations.

- The ath79 platform migrates to devicetree.

- The bcm47xx platform sees fixes for the Buffalo WHR-G54S board.

- The ingenic/jz4740 platform gains support for appended devicetrees.

- The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see
  cleanups as do various pieces of core architecture code.
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