/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
 * Qualcomm SM7150 interconnect IDs
 *
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
 */

#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H

#define MASTER_A1NOC_CFG		0
#define MASTER_QUP_0			1
#define MASTER_TSIF			2
#define MASTER_EMMC			3
#define MASTER_SDCC_2			4
#define MASTER_SDCC_4			5
#define MASTER_UFS_MEM			6
#define A1NOC_SNOC_SLV			7
#define SLAVE_SERVICE_A1NOC		8

#define MASTER_A2NOC_CFG		0
#define MASTER_QDSS_BAM			1
#define MASTER_QUP_1			2
#define MASTER_CNOC_A2NOC		3
#define MASTER_CRYPTO_CORE_0		4
#define MASTER_IPA			5
#define MASTER_PCIE			6
#define MASTER_QDSS_ETR			7
#define MASTER_USB3			8
#define A2NOC_SNOC_SLV			9
#define SLAVE_ANOC_PCIE_GEM_NOC		10
#define SLAVE_SERVICE_A2NOC		11

#define MASTER_CAMNOC_HF0_UNCOMP	0
#define MASTER_CAMNOC_RT_UNCOMP		1
#define MASTER_CAMNOC_SF_UNCOMP		2
#define MASTER_CAMNOC_NRT_UNCOMP	3
#define SLAVE_CAMNOC_UNCOMP		4

#define MASTER_NPU			0
#define SLAVE_CDSP_GEM_NOC		1

#define MASTER_SPDM			0
#define SNOC_CNOC_MAS			1
#define MASTER_QDSS_DAP			2
#define SLAVE_A1NOC_CFG			3
#define SLAVE_A2NOC_CFG			4
#define SLAVE_AHB2PHY_NORTH		5
#define SLAVE_AHB2PHY_SOUTH		6
#define SLAVE_AHB2PHY_WEST		7
#define SLAVE_AOP			8
#define SLAVE_AOSS			9
#define SLAVE_CAMERA_CFG		10
#define SLAVE_CAMERA_NRT_THROTTLE_CFG	11
#define SLAVE_CAMERA_RT_THROTTLE_CFG	12
#define SLAVE_CLK_CTL			13
#define SLAVE_CDSP_CFG			14
#define SLAVE_RBCPR_CX_CFG		15
#define SLAVE_RBCPR_MX_CFG		16
#define SLAVE_CRYPTO_0_CFG		17
#define SLAVE_CNOC_DDRSS		18
#define SLAVE_DISPLAY_CFG		19
#define SLAVE_DISPLAY_THROTTLE_CFG	20
#define SLAVE_EMMC_CFG			21
#define SLAVE_GLM			22
#define SLAVE_GRAPHICS_3D_CFG		23
#define SLAVE_IMEM_CFG			24
#define SLAVE_IPA_CFG			25
#define SLAVE_CNOC_MNOC_CFG		26
#define SLAVE_PCIE_CFG			27
#define SLAVE_PDM			28
#define SLAVE_PIMEM_CFG			29
#define SLAVE_PRNG			30
#define SLAVE_QDSS_CFG			31
#define SLAVE_QUP_0			32
#define SLAVE_QUP_1			33
#define SLAVE_SDCC_2			34
#define SLAVE_SDCC_4			35
#define SLAVE_SNOC_CFG			36
#define SLAVE_SPDM_WRAPPER		37
#define SLAVE_TCSR			38
#define SLAVE_TLMM_NORTH		39
#define SLAVE_TLMM_SOUTH		40
#define SLAVE_TLMM_WEST			41
#define SLAVE_TSIF			42
#define SLAVE_UFS_MEM_CFG		43
#define SLAVE_USB3			44
#define SLAVE_VENUS_CFG			45
#define SLAVE_VENUS_CVP_THROTTLE_CFG	46
#define SLAVE_VENUS_THROTTLE_CFG	47
#define SLAVE_VSENSE_CTRL_CFG		48
#define SLAVE_CNOC_A2NOC		49
#define SLAVE_SERVICE_CNOC		50

#define MASTER_CNOC_DC_NOC		0
#define SLAVE_GEM_NOC_CFG		1
#define SLAVE_LLCC_CFG			2

#define MASTER_AMPSS_M0			0
#define MASTER_SYS_TCU			1
#define MASTER_GEM_NOC_CFG		2
#define MASTER_COMPUTE_NOC		3
#define MASTER_MNOC_HF_MEM_NOC		4
#define MASTER_MNOC_SF_MEM_NOC		5
#define MASTER_GEM_NOC_PCIE_SNOC	6
#define MASTER_SNOC_GC_MEM_NOC		7
#define MASTER_SNOC_SF_MEM_NOC		8
#define MASTER_GRAPHICS_3D		9
#define SLAVE_MSS_PROC_MS_MPU_CFG	10
#define SLAVE_GEM_NOC_SNOC		11
#define SLAVE_LLCC			12
#define SLAVE_SERVICE_GEM_NOC		13


#define MASTER_LLCC			0
#define SLAVE_EBI_CH0			1

#define MASTER_CNOC_MNOC_CFG		0
#define MASTER_CAMNOC_HF0		1
#define MASTER_CAMNOC_NRT		2
#define MASTER_CAMNOC_RT		3
#define MASTER_CAMNOC_SF		4
#define MASTER_MDP_PORT0		5
#define MASTER_MDP_PORT1		6
#define MASTER_ROTATOR			7
#define MASTER_VIDEO_P0			8
#define MASTER_VIDEO_P1			9
#define MASTER_VIDEO_PROC		10
#define SLAVE_MNOC_SF_MEM_NOC		11
#define SLAVE_MNOC_HF_MEM_NOC		12
#define SLAVE_SERVICE_MNOC		13

#define MASTER_SNOC_CFG			0
#define A1NOC_SNOC_MAS			1
#define A2NOC_SNOC_MAS			2
#define MASTER_GEM_NOC_SNOC		3
#define MASTER_PIMEM			4
#define MASTER_GIC			5
#define SLAVE_APPSS			6
#define SNOC_CNOC_SLV			7
#define SLAVE_SNOC_GEM_NOC_GC		8
#define SLAVE_SNOC_GEM_NOC_SF		9
#define SLAVE_OCIMEM			10
#define SLAVE_PIMEM			11
#define SLAVE_SERVICE_SNOC		12
#define SLAVE_QDSS_STM			13
#define SLAVE_TCU			14

#endif