872ee9cc0219 ("drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_state")
1103672fd6b8 ("drm/i915/mtl: Remove misleading "clock" field from C20 pll_state")
234fcb978f61 ("drm/i915/hdmi: C20 computed PLL frequencies")
f968a25381ac ("drm/i915/mtl: Dump C20 pll hw state")
929f527a7b70 ("drm/i915/mtl: C20 HW readout")
62618c7f117e ("drm/i915/mtl: C20 PLL programming")
27ac123b4544 ("drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams")
5836bc5f8d31 ("drm/i915/mtl: Add C10 phy programming for HDMI")
ea8af87ae6be ("drm/i915/mtl: Add vswing programming for C10 phys")
51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
a42e65f33c38 ("drm/i915/mtl: Create separate reg file for PICA registers")
7cb3eb334b8c ("drm/i915/mtl: Add DP rates")
57b5482bff9e ("drm/i915: Introduce intel_csc_matrix struct")