6ef83c4e19e9 ("cxl: Move QoS class to be calculated from the nearest CPU")
863027d40993 ("cxl: Split out host bridge access coordinates")
032f7b37adff ("cxl: Split out combine_coordinates() for common shared usage")
bd98cbbbf82a ("ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes")
1745a7b364df ("ACPI: HMAT: Introduce 2 levels of generic port access class")
11270e526276 ("base/node / ACPI: Enumerate node access class for 'struct access_coordinate'")
54b9460b0a28 ("ACPI: HMAT: Remove register of memory node for generic target")
cc214417f06f ("cxl: Fix sysfs export of qos_class for memdev")
00413c150682 ("cxl: Change 'struct cxl_memdev_state' *_perf_list to single 'struct cxl_dpa_perf'")
98e7ab3345e1 ("cxl: Fix device reference leak in cxl_port_perf_data_calculate()")
44cd71ef7bac ("cxl: Convert find_cxl_root() to return a 'struct cxl_root *'")
98856b2ea306 ("cxl: Introduce put_cxl_root() helper")
185c1a489f87 ("cxl: Check qos_class validity on memdev probe")
42834b17cf1f ("cxl: Export sysfs attributes for memory device QoS class")
86557b7edf77 ("cxl: Store QTG IDs and related info to the CXL memory device context")
7a4f148dd8d5 ("cxl: Compute the entire CXL path latency and bandwidth data")
14a6960b3e92 ("cxl: Add helper function that calculate performance data for downstream ports")
1037b82fccfe ("cxl: Store the access coordinates for the generic ports")
4d07a05397c8 ("cxl: Calculate and store PCI link latency for the downstream ports")
790815902ec6 ("cxl: Add support for _DSM Function for retrieving QTG ID")