a46cfc0f011c ("cxl/pmem: Introduce a find_cxl_root() helper")
5ff7316f6fea ("cxl/port: Introduce cxl_port_to_pci_bus()")
53989fad1286 ("cxl/pmem: Fix module reload vs workqueue state")
7d3eb23c4ccf ("tools/testing/cxl: Introduce a mock memory device + driver")
67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
2e52b6256b9a ("cxl/pmem: Add support for multiple nvdimm-bridge objects")
06737cd0d216 ("cxl/core: Move pmem functionality")
5161a55c069f ("cxl: Move cxl_core to new directory")
da6aafec3dca ("cxl/acpi: Add the Host Bridge base address to CXL port objects")
21083f51521f ("cxl/pmem: Register 'pmem' / cxl_nvdimm devices")
8fdcb1704f61 ("cxl/pmem: Add initial infrastructure for pmem support")
6af7139c9794 ("cxl/core: Add cxl-bus driver infrastructure")
40ba17afdfab ("cxl/acpi: Introduce cxl_decoder objects")
3b94ce7b7bc1 ("cxl/acpi: Enumerate host bridge root ports")
7d4b5ca2e2cb ("cxl/acpi: Add downstream port data to cxl_port instances")
4812be97c015 ("cxl/acpi: Introduce the root of a cxl_port topology")
08422378c4ad ("cxl/pci: Add HDM decoder capabilities")
9a016527dcb7 ("cxl/pci: Reserve individual register block regions")
30af97296f48 ("cxl/pci: Map registers based on capabilities")
f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once")