16b86e5c03c5 ("clk: renesas: rzg2l: Refactor SD mux driver")
3e8008fcf6b7 ("clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header")
97c1c4ccda76 ("clk: renesas: rzg2l: Add struct clk_hw_data")
bf51d3b2d048 ("clk: renesas: rzg2l: Trust value returned by hardware")
d2692ed490e6 ("clk: renesas: rzg2l: Lock around writes to mux register")
549f4ae2601f ("clk: renesas: rzg2l: Wait for status bit of SD mux before continuing")
897a3e34d6e7 ("clk: renesas: rzg2l: Use u32 for flag and mux_flags")
8282fe0029e0 ("clk: renesas: rzg2l: Add read only versions of the clk macros")
ceb3bfab2da4 ("clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro")
4e683604cfc1 ("clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller")
31d5ef2f565d ("clk: renesas: r9a07g044: Add M4 Clock support")
359f10c1b02d ("clk: renesas: r9a07g044: Add M3 Clock support")
300d95c5bbb4 ("clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support")
60191843db78 ("clk: renesas: r9a07g044: Add M1 clock support")
46bb3e15e8c7 ("clk: renesas: rzg2l: Add DSI divider clk support")
6cc859cae9aa ("clk: renesas: rzg2l: Add PLL5_4 clk mux support")
1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
5d33481f5475 ("clk: renesas: r9a07g043: Add WDT clock and reset entries")
6c05648b57ab ("clk: renesas: r9a07g043: Add OSTM clock and reset entries")
59086e4193f4 ("clk: renesas: r9a07g043: Add SDHI clock and reset entries")