e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup")
43cb86799ff0 ("drm: meson: venc: cvbs: fix CVBS mode matching")
61af6e22ec26 ("drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock")
ff217bc710e0 ("drm/meson: Add support for VIC alternate timings")