ab2940a72dfa ("ASoC: cs42l42: Implement 'set_bclk_ratio'")
7e178946c3e4 ("ASoC: cs42l42: Add bitclock frequency argument to cs42l42_pll_config()")
c2683ecfd185 ("ASoC: cs42l42: Use snd_soc_tdm_params_to_bclk()")
fdbd256175a1 ("ASoC: cs42l42: Set correct SRC MCLK")
06441c82f0cd ("ASoC: cs42l42: Don't reconfigure the PLL while it is running")
c76d572c1ec8 ("ASoC: cs42l42: Assume 24-bit samples are in 32-bit slots")
0c2f2ad4f16a ("ASoC: cs42l42: Fix LRCLK frame start edge")
f1040e86f83b ("ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL")
926ef1a4c245 ("ASoC: cs42l42: Fix bclk calculation for mono")
64324bac750b ("ASoC: cs42l42: Don't allow SND_SOC_DAIFMT_LEFT_J")
c26a5289e865 ("ASoC: cs42l42: Add support for set_jack calls")
b7d00776ebf7 ("ASoC: cs42l42: Wait for PLL to lock before switching to it")
882589bb707b ("ASoC: cs42l42: Only start PLL if it is needed")
0ea23660c717 ("ASoC: cs42l42: Wait at least 150us after writing SCLK_PRESENT")
2cdba9b045c7 ("ASoC: cs42l42: Use bclk from hw_params if set_sysclk was not called")
c5b8ee0879bc ("ASoC: cs42l42: Report jack and button detection")
43fc357199f9 ("ASoC: cs42l42: Set clock source for both ways of stream")
19325cfea044 ("ASoC: cs42l42: Always wait at least 3ms after reset")
15013240fcf7 ("ASoC: cs42l42: Don't enable/disable regulator at Bias Level")
2bdc4f5c6838 ("ASoC: cs42l42: Fix channel width support")