86bc22191892 ("drm/amd/display: Support crc on specific region")
8e7b6fee9b03 ("drm/amd/display: Fix crc_src is not thread safe")
afd3a359c452 ("drm/amd/display: do not use drm middle layer for debugfs")
585d450c76d1 ("drm/amd/display: Refactor to prevent crtc state access in DM IRQ handler")
5d1c59c47997 ("drm/amdgpu: Move existing pflip fields into separate struct")
4a580877bdcb ("drm/amdgpu: Get DRM dev from adev by inline-f")
1348969ab68c ("drm/amdgpu: drm_device to amdgpu_device by inline-f (v2)")
d95e8e97e2d5 ("drm/amdgpu: refine create and release logic of hive info")
aac891685da6 ("drm/amdgpu: refine message print for devices of hive")
53b3f8f40e6c ("drm/amdgpu: refine codes to avoid reentering GPU recovery")
f1403342ebdf ("drm/amdgpu: revert "fix system hang issue during GPU reset"")
72e14ebf9fc0 ("drm/amdgpu: annotate a false positive recursive locking")
a4322e1881be ("drm/amdgpu: add debugfs interface for RAP test")
f75e94d86829 ("drm/amdgpu: bypass querying ras error count registers")
94561899ddb0 ("drm/amdgpu: unlock mutex on error")
25c933b1c4fc ("drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)")
3d4e52d0cf24 ("drm/amd/display: Add debugfs for forcing stream timing sync")
c84d46707ebb ("drm/amdgpu: validate bad page threshold in ras(v3)")
81b41ff5d287 ("drm/amd/powerplay: revise the outputs layout of amdgpu_pm_info debugfs")
df9c8d1aa278 ("drm/amdgpu: fix system hang issue during GPU reset")
7dbf78051f75 ("drm/amd/powerplay: move ppfeature mask setting to smu_cmn.c")
28251d726b2b ("drm/amd/powerplay: implement smu_cmn_get_enabled_mask() for all ASICs")
b4bb3aaf04af ("drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c")
4d942ae349bb ("drm/amd/powerplay: move dpm feature support checking to smu_cmn.c")
6c339f37f1cd ("drm/amd/powerplay: unify swSMU index to asic specific index mapping")
443c7f3c3641 ("drm/amdgpu: add read amdgpu_gfxoff status in debugfs")
3cd7e415aea4 ("drm/amd/powerplay: drop unused code around thermal range setting")
1e1964b777ce ("drm/amd/powerplay: maximum the code sharing on thermal irq setting")
0540ecedcba9 ("drm/amd/powerplay: sort the call flow on temperature ranges retrieving")
2b1f12a2da04 ("drm/amd/powerplay: correct Sienna Cichlid temperature limit settings")