84c9829d16d8 ("clk: renesas: r9a07g043: Add clock and reset entries for ADC")
b67685300478 ("clk: renesas: r9a07g043: Add TSU clock and reset entry")
1cbda37757ab ("clk: renesas: r9a07g043: Add clock and reset entries for CANFD")
6c185664b3d4 ("clk: renesas: r9a07g043: Add GPIO clock and reset entries")
c8b088224c25 ("clk: renesas: Add support for RZ/G2UL SoC")
a1bcf50a99dd ("clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC")
b289cdecc7c3 ("clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3")
f0b62b0bbedc ("clk: renesas: r9a07g044: Add GPU clock and reset entries")
7ef9c45a23a9 ("clk: renesas: r9a07g044: Add mux and divider for G clock")
98ee8b2f66eb ("clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro")
33b22d9c3272 ("clk: renesas: r9a07g044: Add TSU clock and reset entry")
e7d960cd6afd ("clk: renesas: r9a07g044: Add RSPI clock and reset entries")
d6dabaf67897 ("clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV")
161450134ae9 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
dc446cba4301 ("clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros")
073da9e7c768 ("clk: renesas: r9a07g044: Add WDT clock and reset entries")
a0d2a2c6736c ("clk: renesas: r9a07g044: Add clock and reset entry for SCI1")
373bd6f48756 ("clk: renesas: r9a07g044: Add SDHI clock and reset entries")
eaff33646f4c ("clk: renesas: rzg2l: Add SDHI clk mux support")
f294a0ea9d12 ("clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller")