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| author | Peter Wang <peter.wang@mediatek.com> | 2022-06-23 11:50:47 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2022-06-27 23:17:36 -0400 |
| commit | 2bae03a6ac985fe80a7a228af3bcc2d5dbe43381 (patch) | |
| tree | f5432a979cf7a85fc6fa75cac3816d690f9a8d3d | |
| parent | 981b4ac04c2f7c24724d3b3a62c3d0c2fc9adcb7 (diff) | |
| download | linux-next-2bae03a6ac985fe80a7a228af3bcc2d5dbe43381.tar.gz | |
scsi: ufs: ufs-mediatek: Prevent host hang by setting CLK_CG early
Some UFSHCI hosts in MediaTek UFS platform need workaround to prevent host
hang issue by setting CLK_CG bit before host is enabled.
This operation shall have no side effect on those platforms which do not
support this bit.
Link: https://lore.kernel.org/r/20220623035052.18802-4-stanley.chu@mediatek.com
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| -rw-r--r-- | drivers/ufs/host/ufs-mediatek.c | 8 | ||||
| -rw-r--r-- | drivers/ufs/host/ufs-mediatek.h | 1 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index b8f2a74d2a5143..b15351c2235bf8 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -183,6 +183,14 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba, hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT; hba->ahit = 0; } + + /* + * Turn on CLK_CG early to bypass abnormal ERR_CHK signal + * to prevent host hang issue + */ + ufshcd_writel(hba, + ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, + REG_UFS_XOUFS_CTRL); } return 0; diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index 49a2137fb2519d..f5c1c643dd52a8 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -12,6 +12,7 @@ /* * Vendor specific UFSHCI Registers */ +#define REG_UFS_XOUFS_CTRL 0x140 #define REG_UFS_REFCLK_CTRL 0x144 #define REG_UFS_EXTREG 0x2100 #define REG_UFS_MPHYCTRL 0x2200 |