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| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2021-09-30 14:34:20 +1000 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2021-09-30 14:34:20 +1000 |
| commit | 9da5899ea6bbadd2d4de0f0645e470e19360d447 (patch) | |
| tree | a8ef8d46cab0eb908bcc08ab9071e5d4a00dd233 | |
| parent | 8af45a83229b9641908394d3df42fa49e5c0a6f6 (diff) | |
| parent | fcfb63148c241adad54ed99fc318167176d7254b (diff) | |
| download | devel-9da5899ea6bbadd2d4de0f0645e470e19360d447.tar.gz | |
Merge branch 'renesas-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
| -rw-r--r-- | drivers/pinctrl/renesas/core.c | 12 | ||||
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index f2ab02225837ec..ef8ef05ba93030 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -741,12 +741,12 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } #define SH_PFC_MAX_REGS 300 #define SH_PFC_MAX_ENUMS 3000 -static unsigned int sh_pfc_errors __initdata = 0; -static unsigned int sh_pfc_warnings __initdata = 0; -static u32 *sh_pfc_regs __initdata = NULL; -static u32 sh_pfc_num_regs __initdata = 0; -static u16 *sh_pfc_enums __initdata = NULL; -static u32 sh_pfc_num_enums __initdata = 0; +static unsigned int sh_pfc_errors __initdata; +static unsigned int sh_pfc_warnings __initdata; +static u32 *sh_pfc_regs __initdata; +static u32 sh_pfc_num_regs __initdata; +static u16 *sh_pfc_enums __initdata; +static u32 sh_pfc_num_enums __initdata; #define sh_pfc_err(fmt, ...) \ do { \ diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index dbf2f521bb2726..20b2af889ca96b 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -852,7 +852,7 @@ static const u32 rzg2l_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x22, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_ETH0)), |