Anyka GPL kernel dumplinux-2.6.32.9-ak

Obtained from https://github.com/onyx-intl/ak98_kernel

569 files changed, 148622 insertions, 453 deletions

diff --git a/Makefile b/Makefile
index ec932b2155b..ba7b02ea1b1 100644
--- a/Makefile
+++ b/Makefile
@@ -122,6 +122,13 @@ sub-make: FORCE
 	KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
 	$(filter-out _all sub-make,$(MAKECMDGOALS))
 
+myPATH := $(KBUILD_OUTPUT)/lib
+myFILE := "libfha.a"
+myFILE_SOURCE := "lib/libfha.a"
+$(shell if [ ! -d $(myPATH) ]; then\
+	mkdir -p $(myPATH); fi)
+$(shell cp -f $(myFILE_SOURCE) $(myPATH))
+
 # Leave processing to above invocation of make
 skip-makefile := 1
 endif # ifneq ($(KBUILD_OUTPUT),)
@@ -180,8 +187,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
 # Default value for CROSS_COMPILE is not to prefix executables
 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
 export KBUILD_BUILDHOST := $(SUBARCH)
-ARCH		?= $(SUBARCH)
-CROSS_COMPILE	?=
+ARCH		?= arm
+CROSS_COMPILE	?= arm-none-linux-gnueabi-
 
 # Architecture as present in compile.h
 UTS_MACHINE 	:= $(ARCH)
@@ -661,7 +668,7 @@ drivers-y	:= $(patsubst %/, %/built-in.o, $(drivers-y))
 net-y		:= $(patsubst %/, %/built-in.o, $(net-y))
 libs-y1		:= $(patsubst %/, %/lib.a, $(libs-y))
 libs-y2		:= $(patsubst %/, %/built-in.o, $(libs-y))
-libs-y		:= $(libs-y1) $(libs-y2)
+libs-y		:= $(libs-y1) $(libs-y2) lib/libfha.a
 
 # Build vmlinux
 # ---------------------------------------------------------------------------
@@ -1213,12 +1220,14 @@ $(clean-dirs):
 clean: archclean $(clean-dirs)
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
+	@mv -f lib/libfha.a lib/libfha.a.1
 	@find . $(RCS_FIND_IGNORE) \
 		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name 'Module.markers' -o -name '.tmp_*.o.*' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
+	@mv -f lib/libfha.a.1 lib/libfha.a
 
 # mrproper - Delete all generated files, including .config
 #
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c6004..61179e06c61 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -179,6 +179,11 @@ config OPROFILE_ARMV7
 	depends on CPU_V7 && !SMP
 	bool
 
+config OPROFILE_AK98
+    def_bool y
+    depends on CPU_ARM926T && !SMP
+    bool
+
 endif
 
 config VECTORS_BASE
@@ -702,6 +707,24 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
+config ARCH_AK98
+	bool "Anyka AK9801, AK9802, AK9803, AK9805, AK9806"
+	select GENERIC_GPIO
+	select HAVE_GPIO_LIB
+	select ARCH_HAS_CPUFREQ
+	select CPU_ARM926T
+	help
+	  Support for systems based on the Anyka ak98.
+
+config ARCH_AK88
+	bool "Anyka AK88"
+	select GENERIC_GPIO
+	select HAVE_GPIO_LIB
+	select ARCH_HAS_CPUFREQ
+	select CPU_ARM926T
+	help
+	  Support for systems based on the Anyka ak88.
+
 endchoice
 
 source "arch/arm/mach-clps711x/Kconfig"
@@ -804,6 +827,9 @@ source "arch/arm/mach-w90x900/Kconfig"
 
 source "arch/arm/mach-bcmring/Kconfig"
 
+source "arch/arm/mach-ak88/Kconfig"
+source "arch/arm/mach-ak98/Kconfig"
+
 # Definitions to make life easier
 config ARCH_ACORN
 	bool
@@ -1320,6 +1346,22 @@ config ATAGS_PROC
 	  Should the atags used to boot the kernel be exported in an "atags"
 	  file in procfs. Useful with kexec.
 
+config RAM_BASE
+	hex "RAM physical starting address"
+	depends on ARCH_AK98
+	default 0x80000000
+	help
+	  AK98xx RAM physical starting address (in hex).
+
+config VIDEO_RESERVED_MEM_SIZE
+	hex "Memory reserved for video decoding"
+	depends on ARCH_AK98	
+	default 0x1A00000
+	help
+	  AK98xx H.264 decoder requires continuous physical RAM which do NOT cross
+	  32MB boundary (Decoder IP requirement). So we have to reserve enough RAM
+	  for H.264 decoding. Default size if 0x1A00000 (26MB).
+
 endmenu
 
 menu "CPU Power Management"
@@ -1405,6 +1447,11 @@ config CPU_FREQ_S3C24XX_DEBUGFS
 	help
 	  Export status information via debugfs.
 
+config CPU_FREQ_AK98
+	bool "CPUfreq support for ANYKA AK98 CPUs"
+	depends on CPU_FREQ && ARCH_AK98
+	default y
+
 endif
 
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1a6f70e5292..4dbcd50fbf9 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -112,4 +112,36 @@ config DEBUG_S3C_UART
 	  The uncompressor code port configuration is now handled
 	  by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+config DEBUG_AK88_PORT
+	depends on DEBUG_LL && ARCH_AK88
+	bool "Kernel low-level debugging messages via AK88 UART"
+	help
+	   Say Y here if you want debug print routines to go to one of the
+	   AK8801 internal UARTs. The chosen UART must have been configured
+	   befor it is used.
+
+config DEBUG_AK88_UART
+	depends on DEBUG_AK88_PORT
+	int "AK88 UART to use for low-level debug"
+	default "0"
+	help
+	   Choice for UART for kernel low-level using AK88 UARTS.
+	   The port must have been initialised by the boot-loader before use.
+
+config DEBUG_AK98_PORT
+	depends on DEBUG_LL && ARCH_AK98
+	bool "Kernel low-level debugging messages via AK98 UART"
+	help
+	   Say Y here if you want debug print routines to go to one of the
+	   AK98XX internal UARTs. The chosen UART must have been configured
+	   befor it is used.
+
+config DEBUG_AK98_UART
+	depends on DEBUG_AK98_PORT
+	int "AK98 UART to use for low-level debug"
+	default "0"
+	help
+	   Choice for UART for kernel low-level using AK98 UARTS.
+	   The port must have been initialised by the boot-loader before use.
+
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf6676..431bba4c3ad 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -170,6 +170,8 @@ machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
 machine-$(CONFIG_ARCH_MXC91231)		:= mxc91231
+machine-$(CONFIG_ARCH_AK88)			:= ak88
+machine-$(CONFIG_ARCH_AK98)			:= ak98
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fa6fbf45cf3..219ce716663 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -9,6 +9,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/linkage.h>
+#include <asm/mach-types.h>
 
 /*
  * Debugging stuff
@@ -21,7 +22,7 @@
 
 #if defined(CONFIG_DEBUG_ICEDCC)
 
-#ifdef CONFIG_CPU_V6
+#ifdef defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
 		.macro	loadsp, rb
 		.endm
 		.macro	writeb, ch, rb
@@ -127,7 +128,30 @@ start:
 		.word	0x016f2818		@ Magic numbers to help the loader
 		.word	start			@ absolute load/run zImage address
 		.word	_edata			@ zImage end address
-1:		mov	r7, r1			@ save architecture ID
+1:
+/*
+ * Actually `machine type' MUST be provided in register r1 by boot/loader according to
+ * ARM Linux booting requirements (Documentation/arm/Booting). However, it seems
+ * that AK88xx/AK98xx nandboot or boot/loader-like program do NOT follow this standard,
+ * we have to give a fake one here.
+ *
+ * NOTE: The following code assumes that machine type is NOT greater than 0xFFFF, that could
+ *           be true for a very long time, so just keep the code.
+ */
+#ifdef CONFIG_ARCH_AK88
+		mov	r1, #(MACH_TYPE_AK88 & 0xFF)
+		orr	r1, r1, #(MACH_TYPE_AK88 & 0xFF00)
+#elif CONFIG_AK9801_ATHENA
+		mov	r1, #(MACH_TYPE_AK9801_ATHENA & 0xFF)
+		orr	r1, r1, #(MACH_TYPE_AK9801_ATHENA & 0xFF00)
+#elif CONFIG_AK9805_TV908
+		mov	r1, #(MACH_TYPE_AK9805_TV908 & 0xFF)
+		orr	r1, r1, #(MACH_TYPE_AK9805_TV908 & 0xFF00)
+#elif CONFIG_AK9805_MP5
+		mov	r1, #(MACH_TYPE_AK9805_MP5 & 0xFF)
+		orr	r1, r1, #(MACH_TYPE_AK9805_MP5 & 0xFF00)
+#endif
+		mov	r7, r1			@ save architecture ID
 		mov	r8, r2			@ save atags pointer
 
 #ifndef __ARM_ARCH_2__
@@ -620,6 +644,8 @@ proc_types:
 @		b	__arm6_mmu_cache_off
 @		b	__armv3_mmu_cache_flush
 
+#if !defined(CONFIG_CPU_V7)
+		/* This collides with some V7 IDs, preventing correct detection */
 		.word	0x00000000		@ old ARM ID
 		.word	0x0000f000
 		mov	pc, lr
@@ -628,6 +654,7 @@ proc_types:
  THUMB(		nop				)
 		mov	pc, lr
  THUMB(		nop				)
+#endif
 
 		.word	0x41007000		@ ARM7/710
 		.word	0xfff8fe00
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 17153b54613..c97ad768b42 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -33,7 +33,7 @@ static void putstr(const char *ptr);
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
-#ifdef CONFIG_CPU_V6
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
 
 static void icedcc_putc(int ch)
 {
diff --git a/arch/arm/configs/ak880x_defconfig b/arch/arm/configs/ak880x_defconfig
new file mode 100644
index 00000000000..c0755e1c874
--- /dev/null
+++ b/arch/arm/configs/ak880x_defconfig
@@ -0,0 +1,1316 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.8
+# Sun May 23 22:42:32 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+# CONFIG_CGROUP_MEM_RES_CTLR_SWAP is not set
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_USER_NS is not set
+CONFIG_PID_NS=y
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK88=y
+# CONFIG_BOARD_AK8801EPC is not set
+CONFIG_BOARD_AK8802EBOOK=y
+# CONFIG_AK88_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock2 init=linuxrc mem=56M console=ttySAK0,115200n8 debug LD_LIBRARY_PATH=/lib"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_AK88=y
+# CONFIG_MTD_NAND_DMA_MODE is not set
+# CONFIG_MTD_NAND_AK88_DEBUG is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK88=y
+# CONFIG_TOUCHSCREEN_AK88_DEBUG is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK88=y
+CONFIG_SERIAL_AK88_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=0
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_AK88=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_AK88=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK88=y
+# CONFIG_FB_AK88_DEBUG is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+CONFIG_USB_GADGET_AK88=y
+CONFIG_USB_AK88=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+# CONFIG_USB_ETH_RNDIS is not set
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK88=y
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_AK88=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK88=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set
+# CONFIG_YAFFS_DISABLE_BACKGROUND is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK88_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak88_androidrd_defconfig b/arch/arm/configs/ak88_androidrd_defconfig
new file mode 100755
index 00000000000..145258bbe06
--- /dev/null
+++ b/arch/arm/configs/ak88_androidrd_defconfig
@@ -0,0 +1,1504 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Sep 28 13:35:55 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak88"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_AK98 is not set
+CONFIG_ARCH_AK88=y
+CONFIG_BOARD_AK8801EPC=y
+# CONFIG_BOARD_AK8802EBOOK is not set
+CONFIG_AK88_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="initrd=0x33000000,160139byte init=/init mem=128M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK88=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_AK88_DEBUG is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_AK88_TRKBALL=y
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK88=y
+CONFIG_SERIAL_AK88_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK88=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_AK88=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_ANYKA_FAKE=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK88=y
+# CONFIG_FB_AK88_DEBUG is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+CONFIG_USB_GADGET_AK88=y
+CONFIG_USB_AK88=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK88=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK88=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK88_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak88_full_defconfig b/arch/arm/configs/ak88_full_defconfig
new file mode 100644
index 00000000000..9f3e08f6bb3
--- /dev/null
+++ b/arch/arm/configs/ak88_full_defconfig
@@ -0,0 +1,1508 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Wed Nov 17 17:53:04 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak88"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_AK98 is not set
+CONFIG_ARCH_AK88=y
+# CONFIG_BOARD_AK8801EPC is not set
+CONFIG_BOARD_AK8802EBOOK=y
+CONFIG_AK88_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock3 rw init=/sbin/init mem=64M console=ttySAK3,115200n8"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK88=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_AK88_DEBUG is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_AK88_TRKBALL=y
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK88=y
+CONFIG_SERIAL_AK88_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK88=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_AK88=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK88=y
+# CONFIG_FB_AK88_DEBUG is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+CONFIG_USB_GADGET_AK88=y
+CONFIG_USB_AK88=y
+# CONFIG_USB_GADGET_AK98 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_AK88 is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK88=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK88_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak88_micro_defconfig b/arch/arm/configs/ak88_micro_defconfig
new file mode 100644
index 00000000000..8246e57fd89
--- /dev/null
+++ b/arch/arm/configs/ak88_micro_defconfig
@@ -0,0 +1,715 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Thu Sep 16 17:26:38 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+# CONFIG_AIO is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+# CONFIG_BLOCK is not set
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK88=y
+# CONFIG_BOARD_AK8801EPC is not set
+CONFIG_BOARD_AK8802EBOOK=y
+# CONFIG_AK88_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=64M console=ttySAK3,115200n8"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK88=y
+CONFIG_SERIAL_AK88_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK88=y
+# CONFIG_FB_AK88_DEBUG is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK88_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak88_producer_defconfig b/arch/arm/configs/ak88_producer_defconfig
new file mode 100644
index 00000000000..57a91b5f3f3
--- /dev/null
+++ b/arch/arm/configs/ak88_producer_defconfig
@@ -0,0 +1,1340 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Wed Nov 17 16:23:21 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak88"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="~/tools/rootfs/rootfs.initramfs"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_AK98 is not set
+CONFIG_ARCH_AK88=y
+# CONFIG_BOARD_AK8801EPC is not set
+CONFIG_BOARD_AK8802EBOOK=y
+CONFIG_AK88_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock3 rw init=/sbin/init mem=64M console=ttySAK3,115200n8"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_AK88=y
+CONFIG_MTD_NAND_DMA_MODE=y
+CONFIG_MTD_DOWNLOAD_MODE=y
+# CONFIG_MTD_NAND_AK88_DEBUG is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+CONFIG_MOUSE_AK88_TRKBALL=y
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK88=y
+CONFIG_SERIAL_AK88_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK88=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_AK88=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK88=y
+# CONFIG_FB_AK88_DEBUG is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+CONFIG_USB_GADGET_AK88=y
+CONFIG_USB_AK88=y
+# CONFIG_USB_GADGET_AK98 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK88=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK88_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_android_7inch_defconfig b/arch/arm/configs/ak98_android_7inch_defconfig
new file mode 100644
index 00000000000..74503f03b36
--- /dev/null
+++ b/arch/arm/configs/ak98_android_7inch_defconfig
@@ -0,0 +1,1721 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul  5 09:37:50 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../2.1/out/target/product/ak98/root/"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+CONFIG_AK98_PM=y
+CONFIG_AK98_CPUFREQ=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AK98=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_CONSOLE_EARLYSUSPEND=y
+# CONFIG_FB_EARLYSUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+CONFIG_SENSOR_INFO=y
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_AK98_MAC=y
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK98=y
+# CONFIG_TOUCHSCREEN_AK98_DEBUG is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643 is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643_SPI is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+# CONFIG_I2C_AW9523_GPIO is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_MXC622X=y
+CONFIG_ECOMPASS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_AK98 is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+CONFIG_FREQ_POLICY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_HI253 is not set
+# CONFIG_VIDEO_AK98 is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+# CONFIG_LCD_PANEL_QD043003C0_40 is not set
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+CONFIG_LCD_PANEL_LW700AT9009=y
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_AK98_PWM=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+CONFIG_USB_ANDROID_MASS_STORAGE=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_android_defconfig b/arch/arm/configs/ak98_android_defconfig
new file mode 100644
index 00000000000..23feb5eed90
--- /dev/null
+++ b/arch/arm/configs/ak98_android_defconfig
@@ -0,0 +1,1722 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul  5 16:02:19 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../2.1/out/target/product/ak98/root/"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+CONFIG_AK98_PM=y
+CONFIG_AK98_CPUFREQ=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AK98=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_CONSOLE_EARLYSUSPEND=y
+# CONFIG_FB_EARLYSUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+CONFIG_AK_SENSOR=y
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_AK98_MAC=y
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK98=y
+# CONFIG_TOUCHSCREEN_AK98_DEBUG is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643 is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643_SPI is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+# CONFIG_I2C_AW9523_GPIO is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_MXC622X=y
+# CONFIG_SENSORS_MMC328X is not set
+CONFIG_ECOMPASS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_AK98 is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+CONFIG_FREQ_POLICY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_HI253 is not set
+# CONFIG_VIDEO_AK98 is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_QD043003C0_40=y
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_AK98_PWM=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+CONFIG_USB_ANDROID_MASS_STORAGE=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_full_defconfig b/arch/arm/configs/ak98_full_defconfig
new file mode 100644
index 00000000000..a7a59351446
--- /dev/null
+++ b/arch/arm/configs/ak98_full_defconfig
@@ -0,0 +1,1665 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul  5 16:00:26 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+CONFIG_AK98_PM=y
+CONFIG_AK98_CPUFREQ=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock0 rw init=/sbin/init mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AK98=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_WAKELOCK is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+CONFIG_AK_SENSOR=y
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_AK98_MAC=y
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK98=y
+# CONFIG_TOUCHSCREEN_AK98_DEBUG is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643 is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643_SPI is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+# CONFIG_I2C_AW9523_GPIO is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_MXC622X=y
+# CONFIG_SENSORS_MMC328X is not set
+CONFIG_ECOMPASS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_AK98 is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+CONFIG_FREQ_POLICY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_HI253 is not set
+# CONFIG_VIDEO_AK98 is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_QD043003C0_40=y
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_AK98_PWM=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_micro_defconfig b/arch/arm/configs/ak98_micro_defconfig
new file mode 100644
index 00000000000..8518a009584
--- /dev/null
+++ b/arch/arm/configs/ak98_micro_defconfig
@@ -0,0 +1,676 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Sat Jun 11 11:35:01 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="~/_rootfs/fs/rootfs/rootfs.initramfs"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+# CONFIG_BLOCK is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ak98_micro_nand_defconfig b/arch/arm/configs/ak98_micro_nand_defconfig
new file mode 100644
index 00000000000..55d35cc0606
--- /dev/null
+++ b/arch/arm/configs/ak98_micro_nand_defconfig
@@ -0,0 +1,881 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Sat Jun 11 11:35:51 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock0 rw init=/sbin/init mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ak98_mmx_defconfig b/arch/arm/configs/ak98_mmx_defconfig
new file mode 100644
index 00000000000..118b7c085d5
--- /dev/null
+++ b/arch/arm/configs/ak98_mmx_defconfig
@@ -0,0 +1,758 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul  5 09:41:02 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="/home/lzy/rootfs/athena-rootfs/rootfs.initramfs"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+# CONFIG_AK98_PWM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="console=ttySAK0 mem=256M"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+# CONFIG_SENSOR_INFO is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVMEM is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_QD043003C0_40=y
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+# CONFIG_SDIO_DEVICE_SLOT is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_mp5_android_defconfig b/arch/arm/configs/ak98_mp5_android_defconfig
new file mode 100644
index 00000000000..996daf47b51
--- /dev/null
+++ b/arch/arm/configs/ak98_mp5_android_defconfig
@@ -0,0 +1,1723 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul 19 10:48:08 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../2.1/out/target/product/ak98/root/"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+# CONFIG_AK9801_ATHENA is not set
+# CONFIG_AK9805_TV908 is not set
+CONFIG_AK9805_MP5=y
+CONFIG_AK98_PWM=y
+CONFIG_AK98_PM=y
+CONFIG_AK98_CPUFREQ=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AK98=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_CONSOLE_EARLYSUSPEND=y
+# CONFIG_FB_EARLYSUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+CONFIG_AK_SENSOR=y
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_AK98_MAC=y
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+CONFIG_KEYBOARD_AK98_KEYPAD=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK98=y
+# CONFIG_TOUCHSCREEN_AK98_DEBUG is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643 is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643_SPI is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+CONFIG_I2C_AW9523_GPIO=y
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_MXC622X=y
+# CONFIG_SENSORS_MMC328X is not set
+CONFIG_ECOMPASS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_AK98 is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+CONFIG_FREQ_POLICY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_SOC_CAMERA_HI253=y
+CONFIG_VIDEO_AK98=y
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_QD043003C0_40=y
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_AK98_PWM=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+CONFIG_USB_ANDROID_MASS_STORAGE=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_mp5_full_defconfig b/arch/arm/configs/ak98_mp5_full_defconfig
new file mode 100755
index 00000000000..0acb9ec546b
--- /dev/null
+++ b/arch/arm/configs/ak98_mp5_full_defconfig
@@ -0,0 +1,1666 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Tue Jul 19 11:01:25 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+# CONFIG_AK9801_ATHENA is not set
+# CONFIG_AK9805_TV908 is not set
+CONFIG_AK9805_MP5=y
+CONFIG_AK98_PWM=y
+CONFIG_AK98_PM=y
+CONFIG_AK98_CPUFREQ=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock0 rw init=/sbin/init mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1A00000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_AK98=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_WAKELOCK is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+CONFIG_AK_SENSOR=y
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+CONFIG_AK98_MAC=y
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+CONFIG_KEYBOARD_AK98_KEYPAD=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+CONFIG_TOUCHSCREEN_AK98=y
+# CONFIG_TOUCHSCREEN_AK98_DEBUG is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643 is not set
+# CONFIG_TOUCHSCREEN_AK98_AR7643_SPI is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+CONFIG_I2C_AW9523_GPIO=y
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_SENSORS_MXC622X=y
+# CONFIG_SENSORS_MMC328X is not set
+CONFIG_ECOMPASS=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_AK98 is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+CONFIG_FREQ_POLICY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_SOC_CAMERA_HI253=y
+CONFIG_VIDEO_AK98=y
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_QD043003C0_40=y
+# CONFIG_LCD_PANEL_AT043TN24 is not set
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_LCD_PANEL_AT070TN92 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_AK98_PWM=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+CONFIG_SPKHP_SWITCH_AUTO=y
+# CONFIG_SPKHP_SWITCH_MIXER is not set
+# CONFIG_SPKHP_SWITCH_UEVENT is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIODMA is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_AK98_VCODEC=y
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/ak98_producer_defconfig b/arch/arm/configs/ak98_producer_defconfig
new file mode 100644
index 00000000000..35edb2c4f3a
--- /dev/null
+++ b/arch/arm/configs/ak98_producer_defconfig
@@ -0,0 +1,1078 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Sat Jun 11 11:37:28 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../tools/rootfs/rootfs.initramfs"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+CONFIG_AK9801_ATHENA=y
+# CONFIG_AK9805_TV908 is not set
+# CONFIG_AK9805_MP5 is not set
+CONFIG_AK98_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8 download=1"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x0
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_UNIX is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_INET is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+CONFIG_MTD_DOWNLOAD_MODE=y
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_AK98_MAC is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_AK98_2KEY is not set
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+CONFIG_USB_GADGET_AK98_PRODUCER=y
+CONFIG_USB_AK98_PRODUCER=m
+# CONFIG_USB_GADGET_AK98 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index cc3b06ee24f..faf9ebde382 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -69,6 +69,7 @@ CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
@@ -256,6 +257,7 @@ CONFIG_NET=y
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
+CONFIG_ANDROID_PARANOID_NETWORK=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
diff --git a/arch/arm/configs/tv908_android_defconfig b/arch/arm/configs/tv908_android_defconfig
new file mode 100644
index 00000000000..5746e5ebfe5
--- /dev/null
+++ b/arch/arm/configs/tv908_android_defconfig
@@ -0,0 +1,1690 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Fri Apr  8 09:15:39 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="../2.1/out/target/product/ak98/root/"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
+# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+# CONFIG_AK9801_ATHENA is not set
+CONFIG_AK9805_TV908=y
+CONFIG_AK98_PWM=y
+# CONFIG_AK98_PM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1400000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_WAKELOCK is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_AK98_MAC is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_AK98 is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+CONFIG_TOUCHSCREEN_AK98_AR7643=y
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_GPIO is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+CONFIG_I2C_AW9523_GPIO=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_AT043TN24=y
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+CONFIG_USB_AK98_FS_HCD=y
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+CONFIG_USB_ANDROID_MASS_STORAGE=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AK98=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIODMA=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT=y
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR=0
+CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE=0
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/tv908_full_defconfig b/arch/arm/configs/tv908_full_defconfig
new file mode 100644
index 00000000000..8204af4c365
--- /dev/null
+++ b/arch/arm/configs/tv908_full_defconfig
@@ -0,0 +1,1663 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Thu Apr  7 17:43:25 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+# CONFIG_AK9801_ATHENA is not set
+CONFIG_AK9805_TV908=y
+CONFIG_AK98_PWM=y
+# CONFIG_AK98_PM is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock2 rw init=/sbin/init mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1400000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_CONSOLE_EARLYSUSPEND=y
+# CONFIG_FB_EARLYSUSPEND is not set
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_AK98=y
+CONFIG_MTD_NAND_DMA_MODE=y
+# CONFIG_MTD_DOWNLOAD_MODE is not set
+# CONFIG_MTD_NAND_TEST is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ANDROID_PMEM=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_KERNEL_DEBUGGER_CORE is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_APANIC is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_AK98_MAC is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_KEYBOARD_AK98_2KEY=y
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_AK98 is not set
+# CONFIG_TOUCHSCREEN_AK98ADC is not set
+CONFIG_TOUCHSCREEN_AK98_AR7643=y
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+CONFIG_I2C_AK98=y
+CONFIG_I2C_AW9523_GPIO=y
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_BATTERY_AK98=y
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_FB_AK98=y
+CONFIG_LCD_PANEL_AT043TN24=y
+# CONFIG_LCD_PANEL_A050VW01_V5 is not set
+# CONFIG_LCD_PANEL_LW700AT9009 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_AK98_PCM=y
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_AK98_FS_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_AK88 is not set
+# CONFIG_USB_GADGET_AK98_PRODUCER is not set
+CONFIG_USB_GADGET_AK98=y
+CONFIG_USB_AK98=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_ANDROID is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_AK98=y
+CONFIG_FOUR_DATA_LINE=y
+# CONFIG_EIGHT_DATA_LINE is not set
+CONFIG_SDIO_DEVICE_SLOT=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AK98 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+CONFIG_UIODMA=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=m
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/tv908_micro_defconfig b/arch/arm/configs/tv908_micro_defconfig
new file mode 100644
index 00000000000..bcb27b410aa
--- /dev/null
+++ b/arch/arm/configs/tv908_micro_defconfig
@@ -0,0 +1,1421 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32.9
+# Wed Mar 23 13:39:25 2011
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-ak98"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_ASHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_ARCH_AK98=y
+# CONFIG_ARCH_AK88 is not set
+# CONFIG_AK9801_ATHENA is not set
+CONFIG_AK9805_TV908=y
+CONFIG_AK98_PWM=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=256M console=ttySAK0,115200n8"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_RAM_BASE=0x80000000
+CONFIG_VIDEO_RESERVED_MEM_SIZE=0x1400000
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_AK98 is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_KEYRESET is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_AK98_2KEY is not set
+# CONFIG_KEYBOARD_AK98_KEYPAD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVMEM=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_AK98=y
+CONFIG_SERIAL_AK98_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_DCC_TTY is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_AK98 is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC_INPUT_EVDEV is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AK98 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_AK98_PCM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_AK98_FS_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_AK98 is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_SWITCH is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AK98 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_AK98_PORT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_PCBC is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 3d0cdd21b88..3e32991c04f 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -381,7 +381,7 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
  * Harvard caches are synchronised for the user space address range.
  * This is used for the ARM private sys_cacheflush system call.
  */
-#define flush_cache_user_range(vma,start,end) \
+#define flush_cache_user_range(start,end) \
 	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 
 /*
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index bbecccda76d..6674c42a1a2 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -150,7 +150,11 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
-	if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
+	long mode = regs->ARM_cpsr & MODE_MASK;
+
+	if (((mode == USR_MODE) ||
+	     ((elf_hwcap & HWCAP_26BIT) && (mode == USR26_MODE))) &&
+	    (regs->ARM_cpsr & PSR_I_BIT) == 0) {
 		regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
 		return 1;
 	}
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index b121b6053cc..9690ebed78f 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -22,7 +22,7 @@
 #if defined(CONFIG_DEBUG_ICEDCC)
 		@@ debug using ARM EmbeddedICE DCC channel
 
-#if defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
 
 		.macro	addruart, rx
 		.endm
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index d2903e3bc86..3a71fb16397 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -741,10 +741,11 @@ ENTRY(__switch_to)
 #endif
 #if defined(CONFIG_HAS_TLS_REG)
 	mcr	p15, 0, r3, c13, c0, 3		@ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
+//#elif !defined(CONFIG_TLS_REG_EMUL)
+#endif
 	mov	r4, #0xffff0fff
 	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
-#endif
+//#endif
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 38ccbe1d3b2..5bbbb363d23 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -21,6 +21,7 @@
 #include <asm/memory.h>
 #include <asm/thread_info.h>
 #include <asm/system.h>
+#include <asm/mach-types.h>
 
 #if (PHYS_OFFSET & 0x001fffff)
 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 0d96d0171c0..3b1aac1da0b 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -206,6 +206,77 @@ void machine_restart(char *cmd)
 	arm_pm_restart(reboot_mode, cmd);
 }
 
+/*
+ * dump a block of kernel memory from around the given address
+ */
+static void show_data(unsigned long addr, int nbytes, const char *name)
+{
+	int	i, j;
+	int	nlines;
+	u32	*p;
+
+	/*
+	 * don't attempt to dump non-kernel addresses or
+	 * values that are probably just small negative numbers
+	 */
+	if (addr < PAGE_OFFSET || addr > -256UL)
+		return;
+
+	printk("\n%s: %#lx:\n", name, addr);
+
+	/*
+	 * round address down to a 32 bit boundary
+	 * and always dump a multiple of 32 bytes
+	 */
+	p = (u32 *)(addr & ~(sizeof(u32) - 1));
+	nbytes += (addr & (sizeof(u32) - 1));
+	nlines = (nbytes + 31) / 32;
+
+
+	for (i = 0; i < nlines; i++) {
+		/*
+		 * just display low 16 bits of address to keep
+		 * each line of the dump < 80 characters
+		 */
+		printk("%04lx ", (unsigned long)p & 0xffff);
+		for (j = 0; j < 8; j++) {
+			u32	data;
+			if (probe_kernel_address(p, data)) {
+				printk(" ********");
+			} else {
+				printk(" %08x", data);
+			}
+			++p;
+		}
+		printk("\n");
+	}
+}
+
+static void show_extra_register_data(struct pt_regs *regs, int nbytes)
+{
+	mm_segment_t fs;
+
+	fs = get_fs();
+	set_fs(KERNEL_DS);
+	show_data(regs->ARM_pc - nbytes, nbytes * 2, "PC");
+	show_data(regs->ARM_lr - nbytes, nbytes * 2, "LR");
+	show_data(regs->ARM_sp - nbytes, nbytes * 2, "SP");
+	show_data(regs->ARM_ip - nbytes, nbytes * 2, "IP");
+	show_data(regs->ARM_fp - nbytes, nbytes * 2, "FP");
+	show_data(regs->ARM_r0 - nbytes, nbytes * 2, "R0");
+	show_data(regs->ARM_r1 - nbytes, nbytes * 2, "R1");
+	show_data(regs->ARM_r2 - nbytes, nbytes * 2, "R2");
+	show_data(regs->ARM_r3 - nbytes, nbytes * 2, "R3");
+	show_data(regs->ARM_r4 - nbytes, nbytes * 2, "R4");
+	show_data(regs->ARM_r5 - nbytes, nbytes * 2, "R5");
+	show_data(regs->ARM_r6 - nbytes, nbytes * 2, "R6");
+	show_data(regs->ARM_r7 - nbytes, nbytes * 2, "R7");
+	show_data(regs->ARM_r8 - nbytes, nbytes * 2, "R8");
+	show_data(regs->ARM_r9 - nbytes, nbytes * 2, "R9");
+	show_data(regs->ARM_r10 - nbytes, nbytes * 2, "R10");
+	set_fs(fs);
+}
+
 void __show_regs(struct pt_regs *regs)
 {
 	unsigned long flags;
@@ -264,6 +335,8 @@ void __show_regs(struct pt_regs *regs)
 		printk("Control: %08x%s\n", ctrl, buf);
 	}
 #endif
+
+	show_extra_register_data(regs, 128);
 }
 
 void show_regs(struct pt_regs * regs)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c6c57b640b6..94aa64dce4d 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
+#include <linux/ctype.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -437,6 +438,20 @@ static void __init early_mem(char **p)
 	if (**p == '@')
 		start = memparse(*p + 1, p);
 
+#ifdef CONFIG_VIDEO_RESERVED_MEM_SIZE
+	/*
+	 * Workaround for AK98xx H.264 decoder limitation which requires continous 
+	 * physical RAM which do NOT cross 32MB boundary (Decoder IP requirement).
+	 *
+	 * To avoid confusing developers, developer still pass something like
+	 * mem=REAL_RAM_SIZE in command line. But we must skip memory reserved for
+	 * H.264 decoder since they are NOT handled by normal kernel VM. They are
+	 * manipulated by pmem-like drivers.
+	 */
+	if (meminfo.nr_banks == 0) {
+		size -= CONFIG_VIDEO_RESERVED_MEM_SIZE;
+	}
+#endif
 	arm_add_memory(start, size);
 }
 __early_param("mem=", early_mem);
@@ -635,6 +650,13 @@ static int __init parse_tag_cmdline(const struct tag *tag)
 
 __tagtable(ATAG_CMDLINE, parse_tag_cmdline);
 
+#ifdef CONFIG_ARCH_AK98
+/*
+ * For AK98xx, we do NOT use TAGS to pass command line or other info
+ * to kernel. Nandboot use the same physical address as TAGS to save
+ * kernel command line.
+ */
+#else
 /*
  * Scan the tag table for this tag, and call its parse function.
  * The tag table is built by the linker from all the __tagtable
@@ -683,6 +705,7 @@ static struct init_tags {
 	{ MEM_SIZE, PHYS_OFFSET },
 	{ 0, ATAG_NONE }
 };
+#endif
 
 static void (*init_machine)(void) __initdata;
 
@@ -697,7 +720,12 @@ arch_initcall(customize_machine);
 
 void __init setup_arch(char **cmdline_p)
 {
+	int i = 0;
+#ifdef CONFIG_ARCH_AK98
+	char *p;
+#else
 	struct tag *tags = (struct tag *)&init_tags;
+#endif
 	struct machine_desc *mdesc;
 	char *from = default_command_line;
 
@@ -710,6 +738,33 @@ void __init setup_arch(char **cmdline_p)
 	if (mdesc->soft_reboot)
 		reboot_setup("s");
 
+#ifdef CONFIG_ARCH_AK98
+	/*
+	 * For AK98xx, we get kernel command line passed by nandboot program.
+	 * However, when we are NOT able to get correct command line from nandboot,
+	 * we fall back to default command line configured by kernel config.
+	 */
+	memset(boot_command_line, 0x00, COMMAND_LINE_SIZE);
+	if (mdesc->boot_params)
+		p = phys_to_virt(mdesc->boot_params);
+	else
+		p = phys_to_virt(PHYS_OFFSET + 0x100);
+	while ((i < (COMMAND_LINE_SIZE - 1)) && (*p != '\0') && isascii(*p)) {
+		boot_command_line[i++] = *p++;
+	}
+
+	/*
+	 * Just in case there are some garbage in the position where command 
+	 * line should be. (This should ONLY be possible when one use old version
+	 * burntool to burn the new kernel image.)
+	 * Once we found one character which is NOT readble, we discard
+	 * the whole string for safe.
+	 */
+	if ((i > 0) && (*p != '\0') && (!isascii(*p))) {
+		printk("Invalid command line passed by Nandboot, ignored\n");
+		i = 0;
+	}
+#else
 	if (__atags_pointer)
 		tags = phys_to_virt(__atags_pointer);
 	else if (mdesc->boot_params)
@@ -733,15 +788,21 @@ void __init setup_arch(char **cmdline_p)
 		save_atags(tags);
 		parse_tags(tags);
 	}
-
+#endif
 	init_mm.start_code = (unsigned long) _text;
 	init_mm.end_code   = (unsigned long) _etext;
 	init_mm.end_data   = (unsigned long) _edata;
 	init_mm.brk	   = (unsigned long) _end;
 
-	memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-	boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
-	parse_cmdline(cmdline_p, from);
+	if (i == 0) {
+		printk("Using default command line for kernel\n");
+		memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+		boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
+	} else {
+		printk("Using command line passed by Nandboot\n");
+	}
+
+	parse_cmdline(cmdline_p, boot_command_line);
 	paging_init(mdesc);
 	request_standard_resources(&meminfo, mdesc);
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index e7714f367eb..29a905bf747 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -517,6 +517,14 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
 
 static inline void setup_syscall_restart(struct pt_regs *regs)
 {
+	if (regs->ARM_ORIG_r0 == -ERESTARTNOHAND ||
+	    regs->ARM_ORIG_r0 == -ERESTARTSYS ||
+	    regs->ARM_ORIG_r0 == -ERESTARTNOINTR ||
+	    regs->ARM_ORIG_r0 == -ERESTART_RESTARTBLOCK) {
+		/* the syscall cannot be safely restarted, return -EINTR instead */
+		regs->ARM_r0 = -EINTR;
+		return;
+	}
 	regs->ARM_r0 = regs->ARM_ORIG_r0;
 	regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
 }
@@ -649,6 +657,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
 	 */
 	if (syscall) {
 		if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) {
+			regs->ARM_r0 = -EAGAIN; /* prevent multiple restarts */
 			if (thumb_mode(regs)) {
 				regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE;
 				regs->ARM_pc -= 2;
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index d38cdf2c827..aa876d394d2 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -238,6 +238,8 @@ static inline void do_leds(void)
 #endif
 
 #ifndef CONFIG_GENERIC_TIME
+extern unsigned long ak98_gettimeofcycle(void);
+
 void do_gettimeofday(struct timeval *tv)
 {
 	unsigned long flags;
@@ -251,6 +253,8 @@ void do_gettimeofday(struct timeval *tv)
 		usec += xtime.tv_nsec / 1000;
 	} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
 
+    usec += ak98_gettimeofcycle();
+
 	/* usec may have gone up a lot: be safe */
 	while (usec >= 1000000) {
 		usec -= 1000000;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3f361a783f4..14abab76019 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -438,7 +438,9 @@ do_cache_op(unsigned long start, unsigned long end, int flags)
 		if (end > vma->vm_end)
 			end = vma->vm_end;
 
-		flush_cache_user_range(vma, start, end);
+		up_read(&mm->mmap_sem);
+		flush_cache_user_range(start, end);
+		return;
 	}
 	up_read(&mm->mmap_sem);
 }
@@ -505,7 +507,8 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		thread->tp_value = regs->ARM_r0;
 #if defined(CONFIG_HAS_TLS_REG)
 		asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
+//#elif !defined(CONFIG_TLS_REG_EMUL)
+#endif
 		/*
 		 * User space must never try to access this directly.
 		 * Expect your app to break eventually if you do so.
@@ -513,7 +516,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 		 * (see entry-armv.S for details)
 		 */
 		*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+//#endif
 		return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index aecf87dfbae..3a8424f25e9 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -120,6 +120,12 @@ SECTIONS
 		*(.got)			/* Global offset table		*/
 	}
 
+/* plug enter_standby code into the kernel and linker here */
+
+	L2MEM(standby)
+	L2MEM(freqchange)
+	L2MEM(ddr2change)
+
 	RO_DATA(PAGE_SIZE)
 
 	_etext = .;			/* End of text and rodata section */
diff --git a/arch/arm/mach-ak88/Kconfig b/arch/arm/mach-ak88/Kconfig
new file mode 100644
index 00000000000..8f658b93117
--- /dev/null
+++ b/arch/arm/mach-ak88/Kconfig
@@ -0,0 +1,33 @@
+if ARCH_AK88
+
+choice
+	prompt "AK88 boards"
+	default ARCH_AK8802EBOOK
+
+config BOARD_AK8801EPC
+	bool "EPC board based on AK8801"
+	depends on ARCH_AK88
+	help
+	  Say Y here if you are using the EPC board based on AK8801.
+
+config BOARD_AK8802EBOOK
+	bool "EBOOK board based on AK8802"
+	depends on ARCH_AK88
+	help
+	  Say Y here if you are using the EBOOK board on AK8802.
+
+endchoice
+
+config AK88_PWM
+	bool "PWM control driver for AK88"
+	depends on ARCH_AK88
+	help
+	  Say Y here if you want support pwm control.
+
+config AK88_PM
+	bool "power management for AK88"
+	depends on PM && ARCH_AK88
+	help
+	  Say Y here if you want support power management for AK88.
+
+endif
diff --git a/arch/arm/mach-ak88/Makefile b/arch/arm/mach-ak88/Makefile
new file mode 100644
index 00000000000..cfad14584a9
--- /dev/null
+++ b/arch/arm/mach-ak88/Makefile
@@ -0,0 +1,18 @@
+obj-y				+= cpu.o irq.o time.o clock.o \
+				   l2mem.o dma.o gpio.o devices.o \
+					lib_freq.o \
+					lib_mmu.o \
+					lib_gpio.o \
+					lib_lcd.o \
+					l2.o
+			
+
+obj-$(CONFIG_AK88_PWM)	+= pwm.o
+
+# Power Management support
+
+obj-$(CONFIG_AK88_PM)		+= pm.o sleep.o
+
+# Machin support
+
+obj-y				+= boards.o
diff --git a/arch/arm/mach-ak88/Makefile.boot b/arch/arm/mach-ak88/Makefile.boot
new file mode 100644
index 00000000000..b0909e34737
--- /dev/null
+++ b/arch/arm/mach-ak88/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x30008000
+params_phys-y	:= 0x30000100
diff --git a/arch/arm/mach-ak88/boards.c b/arch/arm/mach-ak88/boards.c
new file mode 100644
index 00000000000..3af9bc7c37e
--- /dev/null
+++ b/arch/arm/mach-ak88/boards.c
@@ -0,0 +1,308 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/spi/spi.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/nand.h>
+#include <mach/ts.h>
+#include <mach/spi.h>
+#include <mach/gpio.h>
+#include <mach/reset.h>
+#include <mach/pm.h>
+
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+#include <mach/map.h>
+#include <mach/devices_ak880x.h>
+#include <mach/lib_lcd.h>
+#include <mach/ak880x_gpio.h>
+ 
+#include <linux/delay.h>
+
+#include <mach/l2.h>
+
+#include "cpu.h"
+#include "irq.h"
+#include "devices.h"
+
+  	#define DBG_UART_ID  0
+	#define LCD_TFT      0
+
+#ifdef CONFIG_BOARD_AK8801EPC 
+ 	#undef DBG_UART_ID  
+	#undef LCD_TFT      
+
+ 	#define DBG_UART_ID  0
+	#define LCD_TFT      0
+#endif
+
+#ifdef CONFIG_BOARD_AK8802EBOOK 
+ 	#undef DBG_UART_ID  
+	#undef LCD_TFT      
+
+	#define DBG_UART_ID  3
+ 	#define LCD_TFT      1
+#endif
+
+/*
+ * LCD Controller
+ */
+//#if defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+#if defined(CONFIG_FB_AK88) || defined(CONFIG_FB_AK88_DEBUG)
+static struct fb_videomode ak880x_tft_vga_modes[] = {
+	{
+ 	 .name = "HSD070IDW1-A10",
+	 .refresh = 60,
+	 .xres = 800,.yres = 480,
+	 .pixclock = 30000000,
+
+	 .left_margin = 40,.right_margin = 40,
+	 .upper_margin = 29,.lower_margin = 13,
+	 .hsync_len = 48,.vsync_len = 3,
+
+	 .sync = 0,
+	 .vmode = FB_VMODE_NONINTERLACED,
+	 },
+
+	{
+	 .name = "Q07021-701",
+	 .refresh = 60,
+	 .xres = 800,.yres = 600,
+ 	 .pixclock = 40000000,
+
+	 .left_margin = 88,.right_margin = 112,
+	 .upper_margin = 39,.lower_margin = 21,
+	 .hsync_len = 48,.vsync_len = 3,
+
+	 .sync = 0,
+	 .vmode = FB_VMODE_NONINTERLACED,
+	 },
+
+};
+
+static struct fb_monspecs ak880xfb_default_monspecs = {
+	.manufacturer = "HIT",
+	.monitor = "TX09D70VM1CCA",
+
+	.modedb = &ak880x_tft_vga_modes[LCD_TFT],
+	.modedb_len = ARRAY_SIZE(ak880x_tft_vga_modes),
+	.hfmin = 15000,
+	.hfmax = 64000,
+	.vfmin = 50,
+	.vfmax = 150,
+};
+
+static void ak880x_lcdc_power_control(int on)
+{
+
+#if 1
+	if (on)
+		//open LCD controller clock
+		AKCLR_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+	else
+		//close LCD controller clock
+		AKSET_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+	//panel power on
+	bsplcd_set_panel_power(on);	//pullup TFT_VGH_L and TFT_AVDD
+
+	//panel backlight
+	baselcd_set_panel_backlight(on);	//will clear memory after memory setting
+
+	printk("ak880x_lcdc_power_control(%d)\n", on);
+
+#endif
+
+}
+
+/* Driver datas */
+static struct anyka_lcdfb_info __initdata ak880x_lcdc_data = {
+	.lcdcon_is_backlight = true,
+	.default_bpp = 16,
+	//.default_dmacon                       = ANYKA_LCDC_DMAEN,
+	//.default_lcdcon2              = AK88_DEFAULT_LCDCON2,
+	.default_monspecs = &ak880xfb_default_monspecs,
+	.anyka_lcdfb_power_control = ak880x_lcdc_power_control,
+	.guard_time = 1,
+	//if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_RGB) {
+	.lcd_wiring_mode = ANYKA_LCDC_WIRING_RGB,	//RGB:565 mode
+};
+
+#else
+static struct anyka_lcdfb_info __initdata ak880x_lcdc_data;
+#endif				//for defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+
+//#define SIZEMTD(x) (SZ_xM)
+
+/* NAND parititon */
+/* for each block=512K */
+static struct mtd_partition ta801_nand_part[] = {
+[0] = {
+		.name = "Bootloader",
+		.size = SZ_512K,                 // 0 to 0
+		.offset = 0,
+		.mask_flags = MTD_WRITEABLE,
+       },
+[1] = {
+		.name = "SYS",
+		.size = SZ_256M , 			
+ 		.offset = MTDPART_OFS_APPEND,
+ 		},
+[2] = {  
+		.name = "DATA",
+ 		.size = SZ_256M  , 		
+   		.offset = MTDPART_OFS_APPEND,
+ 		},
+[3] = {
+		.name = "TEST",
+ 		.size = SZ_256M ,  		
+  		.offset = MTDPART_OFS_APPEND,
+		},
+[4] = {
+		.name = "GUI",              
+		.size = MTDPART_SIZ_FULL,        
+		.offset = MTDPART_OFS_APPEND,
+		}
+};
+
+static struct ak880x_nand_set ta801_nand_sets[] = {
+	[0] = {
+	       .name = "NAND",
+	       .nr_chips = 1,
+	       .nr_partitions = ARRAY_SIZE(ta801_nand_part),
+	       .partitions = ta801_nand_part,
+	       //.cmd_len = 0xF5BD1,	//0x93791
+	       .cmd_len = 0xF5AD1,
+	       //.data_len = 0xF5C5C,	//0x91517
+	       .data_len = 0x91717,
+	       }
+};
+
+static struct ak880x_platform_nand ta801_nand_info = {
+	.nr_sets = ARRAY_SIZE(ta801_nand_sets),
+	.sets = ta801_nand_sets,
+};
+
+static struct ak880x_ts_mach_info ta801_ts_info = {
+	.irq = IRQ_DGPIO_33,
+	.irqpin = AK88_DGPIO_33,
+	.sample_rate = 8000,
+	.wait_time = 5,
+};
+
+static struct ak880x_spi_info ta801_spi_info;
+
+/* platform devices */
+static struct platform_device *ta801_platform_devices[] __initdata = {
+	&ak880x_led_device,
+	&ak880x_rtc_device,
+	&ak880x_uart0_device,
+	//&ak880x_uart1_device,
+	//&ak880x_uart2_device,
+	&ak880x_uart3_device,
+	&ak880x_ts_device,
+	&ak880x_gpio_trkball_device,
+	&ak880x_kpd_device,
+	&ak880x_nand_device,
+	&ak880x_lcd_device,
+	&ak880x_snd_device,
+	&ak880x_spi0_device,
+	&ak880x_i2c_device,
+	&ak880x_mmc_device,
+	&ak880x_usb_device,
+};
+
+static void ta801_shutdown_machine(void)
+{
+	ak880x_gpio_cfgpin(AK88_DGPIO_21, AK88_GPIO_OUT_0);
+	ak880x_gpio_setpin(AK88_DGPIO_21, 0);
+}
+
+static void __init ta801_machine_init(void)
+{
+
+#ifdef CONFIG_BOARD_AK8802EBOOK
+
+	unsigned int pin;
+
+	//POWER_OFF
+	//pin name VI_DATA2/GPIO53    //pull high
+	pin = AK8802_GPIO_53;
+	AKCLR_BITS(1UL << 24, AK88_SHAREPIN_CTRL);	//set pin as gpio[58:47]
+	gpio_set_output(pin, 1);	//open,set to output and pull high
+			
+#endif
+	
+	ak880x_shutdown_machine = ta801_shutdown_machine;
+
+	ak880x_nand_device.dev.platform_data = &ta801_nand_info;
+	ak880x_ts_device.dev.platform_data = &ta801_ts_info;
+	ak880x_spi0_device.dev.platform_data = &ta801_spi_info;
+
+	printk("ta801_machine_init(),DBG_UART_ID=%d,LCD_TFT=%d\n",(int)DBG_UART_ID,(int)LCD_TFT);
+
+	#if 0
+	//* UART */
+ 	ak880x_register_uart(3,3);  
+  	ak880x_set_serial_console(DBG_UART_ID);
+	ak880x_register_uart(0,0);
+
+	ak880x_add_device_serial();
+	#endif
+
+	/* LCD Controller */
+	ak880x_add_device_lcdc(&ak880x_lcdc_data);
+
+	/* register platform devices */
+	platform_add_devices(ta801_platform_devices,
+			     ARRAY_SIZE(ta801_platform_devices));
+
+	ak880x_pm_init();
+
+	/* Initialize L2 buffer */
+	ak88_l2_init();
+}
+
+#ifdef CONFIG_BOARD_AK8801EPC
+MACHINE_START(AK88, "BOARD_AK8801EPC")
+#else
+#ifdef CONFIG_BOARD_AK8802EBOOK
+MACHINE_START(AK88, "BOARD_AK8802EBOOK")
+#endif
+#endif
+/* Maintainer: */
+	.phys_io = 0x30000000,
+	.io_pg_offst = ((0xc0000000) >> 18) & 0xfffc,
+	.boot_params = 0x30000100,
+	.init_irq = ak880x_init_irq,
+	.map_io = ak880x_map_io,
+	.init_machine = ta801_machine_init,
+	.timer = &ak880x_timer, 
+MACHINE_END
diff --git a/arch/arm/mach-ak88/clock.c b/arch/arm/mach-ak88/clock.c
new file mode 100644
index 00000000000..acecbb02d80
--- /dev/null
+++ b/arch/arm/mach-ak88/clock.c
@@ -0,0 +1,578 @@
+/*
+   linux/arch/arm/mach-ak7801/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/ak880x_addr.h>
+#include <mach/clock.h>
+
+/* clock information */
+
+static LIST_HEAD(clocks);
+
+DEFINE_MUTEX(clocks_mutex);
+
+/* enable and disable calls for use with the clk struct */
+
+static int clk_null_enable(struct clk *clk, int enable)
+{
+	return 0;
+}
+
+/* Clock API calls */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+	struct clk *p;
+	struct clk *clk = ERR_PTR(-ENOENT);
+	int idno;
+
+	if (dev == NULL || dev->bus != &platform_bus_type)
+		idno = -1;
+	else
+		idno = to_platform_device(dev)->id;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(p, &clocks, list) {
+		if (p->id == idno &&
+		    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+			clk = p;
+			break;
+		}
+	}
+
+	/* check for the case where a device was supplied, but the
+	 * clock that was being searched for is not device specific */
+
+	if (IS_ERR(clk)) {
+		list_for_each_entry(p, &clocks, list) {
+			if (p->id == -1 && strcmp(id, p->name) == 0 &&
+			    try_module_get(p->owner)) {
+				clk = p;
+				break;
+			}
+		}
+	}
+
+	mutex_unlock(&clocks_mutex);
+	return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+	module_put(clk->owner);
+}
+
+int clk_enable(struct clk *clk)
+{
+
+	if (IS_ERR(clk) || clk == NULL)
+		return -EINVAL;
+
+ 	clk_enable(clk->parent);
+
+	mutex_lock(&clocks_mutex);
+	if ((clk->usage++) == 0)
+		(clk->enable) (clk, 1);
+ 
+	mutex_unlock(&clocks_mutex);
+
+	return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+	if (IS_ERR(clk) || clk == NULL)
+		return;
+
+	mutex_lock(&clocks_mutex);
+
+	if ((--clk->usage) == 0)
+		(clk->enable) (clk, 0);
+
+	mutex_unlock(&clocks_mutex);
+	clk_disable(clk->parent);
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (IS_ERR(clk))
+		return 0;
+
+	if (clk->rate != 0)
+		return clk->rate;
+
+	if (clk->get_rate != NULL)
+		return (clk->get_rate) (clk);
+
+	if (clk->parent != NULL)
+		return clk_get_rate(clk->parent);
+
+	return clk->rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	/* We do not default just do a clk->rate = rate as
+	 * the clock may have been made this way by choice.
+	 */
+
+	WARN_ON(clk->set_rate == NULL);
+
+	if (clk->set_rate == NULL)
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+	ret = (clk->set_rate) (clk, rate);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	return clk->parent;
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+
+	if (clk->set_parent)
+		ret = (clk->set_parent) (clk, parent);
+
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+
+EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_get_rate);
+EXPORT_SYMBOL(clk_set_rate);
+EXPORT_SYMBOL(clk_get_parent);
+EXPORT_SYMBOL(clk_set_parent);
+
+/* base clocks */
+
+int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+	clk->rate = rate;
+	return 0;
+}
+
+struct clk clk_xtal_12M = {
+	.name = "xtal_12M",
+	.id = -1,
+	.usage = 0,
+	.rate = 12 * 1000 * 1000,
+	.parent = NULL,
+};
+
+struct clk clk_xtal_27M = {
+	.name = "xtal_27M",
+	.id = -1,
+	.usage = 0,
+	.rate = 27 * 1000 * 1000,
+	.parent = NULL,
+	//.enable               = xtal_27M_enable,
+};
+
+struct clk clk_xtal_32K = {
+	.name = "xtal_32K",
+	.id = -1,
+	.usage = 0,
+	.rate = 32768,
+	.parent = NULL,
+};
+
+struct clk clk_pll1 = {
+	.name = "pll1",
+	.id = -1,
+	.usage = 0,
+	.parent = NULL,
+	//.set_rate     = clk_pll1_setrate,
+	//.get_rate     = clk_pll1_getrate,
+};
+
+struct clk clk_pll2 = {
+	.name = "pll2",
+	.id = -1,
+	.usage = 0,
+	//.set_rate     = clk_pll2_setrate,
+	//.get_rate     = clk_pll2_getrate,
+};
+
+struct clk clk_asic = {
+	.name = "asic_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll1,
+};
+
+struct clk clk_cpu = {
+	.name = "cpu_clk",
+	.id = -1,
+	.usage = 0,
+	//.set_rate     = clk_cpu_setrate,
+	//.get_rate     = clk_cpu_getrate,
+};
+
+struct clk ap_clk = {
+	.name = "ap_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = NULL,
+};
+
+struct clk adc1_clk = {
+	.name = "adc1_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll1,
+};
+
+struct clk adc2_clk = {
+	.name = "adc2_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_xtal_12M,
+};
+
+struct clk dac_clk = {
+	.name = "dac_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll1,
+};
+
+
+/* cis clock */
+struct clk camif_clk = {
+	.name = "camif_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll2,
+	//.set_rate     = clk_camif_setrate,
+	//.get_rate     = clk_camif_getrate,
+};
+
+/* spi clock */
+static int spi_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON &= ~(1UL << 2);
+	else
+		rCLK_CON |= (1UL << 2);
+
+	return 0;
+}
+
+struct clk spi_clk = {
+	.name = "spi_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = spi_clk_enable,
+};
+
+/* MMC/SD clock */
+#define AK88_MMC_CLK_CTRL     (AK88_VA_MMC + 0x04)
+static int mci_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON &= ~((1UL << 2) | (1UL << 18));
+	/*
+	 * else
+	 *         rCLK_CON |= (1<<2); [> shared with SPI1/SPI2/UART2 <] 
+	 */
+	return 0;
+}
+
+#if 0
+static int mci_set_rate(struct clk *c, unsigned long rate)
+{
+	int divider, regval;
+	int src_rate = clk_get_rate(c->parent) * 1000 * 1000;
+
+	if (rate == 0)
+		return -EINVAL;
+
+	regval = __raw_readl(AK88_MMC_CLK_CTRL) & ~0xffff;
+	divider = (src_rate / rate - 2) / 2 & 0xff;
+	regval |= divider << 8 | divider;
+	__raw_writel(regval, AK88_MMC_CLK_CTRL);
+
+	return 0;
+}
+#endif
+
+static unsigned long mci_get_rate(struct clk *c)
+{
+#if 0
+	int divider, regval;
+	int src_rate = clk_get_rate(c->parent) * 1000 * 1000;
+
+	regval = __raw_readl(AK88_MMC_CLK_CTRL) & 0xffff;
+	divider = (regval & 0xff) + ((regval >> 8) & 0xff) + 2;
+
+	return src_rate / divider;
+#else
+	/* return asic clock */
+	return clk_asic.rate;
+#endif
+}
+
+struct clk mci_clk = {
+	.name = "mci_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = mci_clk_enable,
+#if 0
+	.set_rate = mci_set_rate,
+#endif
+	.get_rate = mci_get_rate,
+};
+
+/* udc */
+static int udc_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON &= ~(1UL << 5);
+	else
+		rCLK_CON |= (1UL << 5);
+	return 0;
+}
+
+struct clk udc_clk = {
+	.name = "udc_clk",
+	.id = -1,
+	.usage = 0,
+ 	.parent = &clk_pll1,
+	.enable = udc_clk_enable,
+};
+
+/* uart4 clk*/
+static int uart4_clk_enable(struct clk *clk, int enable)
+{
+	if (enable){
+		rCLK_CON &= ~(1UL << 8);
+ 	}
+	else
+		rCLK_CON |= (1UL << 8);
+
+	return 0;
+}
+
+struct clk uart4_clk = {
+	.name = "uart4_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll1,
+	.enable = uart4_clk_enable,
+};
+
+/* lcd clk */
+static int lcd_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON &= ~(1UL << 3);
+	else
+		rCLK_CON |= (1UL << 3);
+	return 0;
+}
+
+struct clk lcd_clk = {
+	.name = "lcd_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = lcd_clk_enable,
+	//.set_rate     = pclk_setrate,
+	//.get_rate     = pclk_getrate,
+};
+
+/* initialise the clock system */
+
+int ak880x_register_clock(struct clk *clk)
+{
+	clk->owner = THIS_MODULE;
+
+	if (clk->enable == NULL)
+		clk->enable = clk_null_enable;
+
+	/* add to the list of available clocks */
+	
+	mutex_lock(&clocks_mutex);
+	list_add(&clk->list, &clocks);
+	mutex_unlock(&clocks_mutex);
+	//printk("ak880x_register_clock(),clk->name=%s\n",clk->name);
+
+	return 0;
+}
+
+int ak880x_register_clocks(struct clk **clks, int nr_clks)
+{
+	int fails = 0;
+
+	for (; nr_clks > 0; nr_clks--, clks++) {
+		if (ak880x_register_clock(*clks) < 0)
+			fails++;
+	}
+
+	return fails;
+}
+
+/* initalise all the clocks */
+
+/*
+ *               4  x  M
+ *  PLL1_CLK =  -----------, M = (62 + m), N = (1 + n)
+ *                  N
+ *
+ *               PLL1_CLK
+ *  ASIC_CLK =  -----------
+ *               ASIC_DIV
+ *
+ *
+ *  CPU_CLK  =  PLL1_CLK or ASIC_CLK
+ *
+ */
+static int __init ak880x_init_clocks(void)
+{
+	union ak880x_clk_div1_reg clk_div1_reg;
+
+	printk(KERN_INFO "ANYKA AK88 Clocks, (c) 2010 ANYKA \n");
+
+	clk_div1_reg.regval = __raw_readl(AK88_VA_SYSCTRL + 0x04);
+
+	/* work out what clocks we've got */
+	/* printk("regval = 0x%lx\n", clk_div1_reg.regval); */
+
+#if	defined(CONFIG_BOARD_AK8801EPC)
+
+	#if 0
+	if (clk_div1_reg.clk_div.m > 0x20)
+		clk_pll1.rate = 4 * 62 / (clk_div1_reg.clk_div.n + 1);
+	else
+		clk_pll1.rate =
+		    4 * (clk_div1_reg.clk_div.m +
+			 62) / (clk_div1_reg.clk_div.n + 1);
+	#endif
+
+	clk_pll1.rate =
+	    4 * (clk_div1_reg.clk_div.m + 45) / (clk_div1_reg.clk_div.n + 1);
+	clk_asic.rate =
+	    clk_pll1.rate >> (clk_div1_reg.clk_div.asic_clk ? clk_div1_reg.
+			      clk_div.asic_clk : 1);
+ 	
+	clk_cpu.rate =
+	    clk_div1_reg.clk_div.cpu_clk ? clk_pll1.rate : clk_asic.rate;
+
+	printk("AK88: PLL1 %ld MHz, ASIC %ld MHz, CPU Core %ld MHz\n",
+	       clk_pll1.rate, clk_asic.rate, clk_cpu.rate);
+
+	clk_pll1.rate =clk_pll1.rate*1000*1000;
+	clk_asic.rate =clk_asic.rate*1000*1000;
+	clk_cpu.rate =clk_cpu.rate*1000*1000;
+
+#elif	defined(CONFIG_BOARD_AK8802EBOOK)
+
+	clk_pll1.rate =
+	    4 * (clk_div1_reg.clk_div.m + 45) / (clk_div1_reg.clk_div.n + 1);
+	clk_asic.rate =
+	    clk_pll1.rate >> (clk_div1_reg.clk_div.asic_clk ? clk_div1_reg.
+			      clk_div.asic_clk : 1);
+	clk_cpu.rate =
+	    clk_div1_reg.clk_div.cpu_clk ? clk_pll1.rate : clk_asic.rate;
+
+	printk("AK8802: PLL1 %ld MHz, ASIC %ld MHz, CPU Core %ld MHz\n",
+	       clk_pll1.rate, clk_asic.rate, clk_cpu.rate);
+
+	clk_pll1.rate =clk_pll1.rate*1000*1000;
+	clk_asic.rate =clk_asic.rate*1000*1000;
+	clk_cpu.rate =clk_cpu.rate*1000*1000;
+
+#else
+#error "Only support AK780X & AK88."
+#endif
+
+	/* register our clocks */
+
+	if (ak880x_register_clock(&clk_xtal_12M) < 0)
+		printk(KERN_ERR "failed to register master xtal\n");
+
+	if (ak880x_register_clock(&clk_pll1) < 0)
+		printk(KERN_ERR "failed to register master xtal\n");
+
+	if (ak880x_register_clock(&clk_asic) < 0)
+		printk(KERN_ERR "failed to register asic clk\n");
+
+	if (ak880x_register_clock(&clk_cpu) < 0)
+		printk(KERN_ERR "failed to register cpu clk\n");
+
+	if (ak880x_register_clock(&spi_clk) < 0)
+		printk(KERN_ERR "failed to register spi clk\n");
+
+	if (ak880x_register_clock(&mci_clk) < 0)
+		printk(KERN_ERR "failed to register mci clk\n");
+
+	if (ak880x_register_clock(&udc_clk) < 0)
+		printk(KERN_ERR "failed to register udc clk\n");
+
+	if (ak880x_register_clock(&uart4_clk) < 0)
+		printk(KERN_ERR "failed to register uart4 clk\n");
+
+	if (ak880x_register_clock(&lcd_clk) < 0)
+		printk(KERN_ERR "failed to register lcd clk\n");
+
+	/* FIXME:
+	 * here we disable unused clock, only leave SDRAM/DDR clock enabled.
+	 * please manual enable clock as need.
+	 */
+	__raw_writel(0x7BF7, AK88_VA_SYSCTRL + 0x0C);
+
+	//uart4_clk_enable(&uart4_clk,1);
+	clk_enable(&uart4_clk);
+
+	printk("clk control: 0x%08X\n", __raw_readl(AK88_VA_SYSCTRL + 0x0C));
+
+	return 0;
+}
+
+arch_initcall(ak880x_init_clocks);
diff --git a/arch/arm/mach-ak88/cpu.c b/arch/arm/mach-ak88/cpu.c
new file mode 100644
index 00000000000..27169240fb5
--- /dev/null
+++ b/arch/arm/mach-ak88/cpu.c
@@ -0,0 +1,45 @@
+/*
+ * init cpu freq, clock
+ *
+ * report cpu id
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#define IODESC_ENT(x) { (unsigned long)AK88_VA_##x, __phys_to_pfn(AK88_PA_##x), AK88_SZ_##x, MT_DEVICE }
+
+static struct map_desc ak880x_iodesc[] __initdata = {
+	IODESC_ENT(SYSCTRL),
+	IODESC_ENT(SUBCTRL),
+	IODESC_ENT(L2MEM),
+};
+
+void __init ak880x_map_io(void)
+{
+	unsigned long idcode = 0x0;
+
+	/* initialise the io descriptors we need for initialisation */
+	iotable_init(ak880x_iodesc, ARRAY_SIZE(ak880x_iodesc));
+
+	idcode = __raw_readl(AK88_VA_SYSCTRL + 0x00);
+
+	if (idcode == 0x33323236)
+#if	defined(CONFIG_BOARD_AK8801EPC)
+		printk("ANYKA CPU %s (id 0x%lx)\n", "AK7801", idcode);
+#elif	defined(CONFIG_BOARD_AK8802EBOOK)
+		printk("ANYKA CPU %s (id 0x%lx)\n", "AK88", idcode);
+#endif
+	else
+		panic("Unknown ANYKA CPU id: 0x%lx\n", idcode);
+}
diff --git a/arch/arm/mach-ak88/cpu.h b/arch/arm/mach-ak88/cpu.h
new file mode 100644
index 00000000000..965ed57a47a
--- /dev/null
+++ b/arch/arm/mach-ak88/cpu.h
@@ -0,0 +1,5 @@
+
+struct sys_timer;
+extern struct sys_timer ak880x_timer;
+
+void __init ak880x_map_io(void);
diff --git a/arch/arm/mach-ak88/devices.c b/arch/arm/mach-ak88/devices.c
new file mode 100644
index 00000000000..ec25c03fbf0
--- /dev/null
+++ b/arch/arm/mach-ak88/devices.c
@@ -0,0 +1,584 @@
+/* linux/arch/arm/mach-ak880x/devices.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/lib_l2.h>
+#include <mach/lib_uart.h>
+#include <mach/lib_lcd.h>
+#include <mach/devices_ak880x.h>
+#include <mach/gpio.h>
+
+struct platform_device ak880x_led_device = {
+	.name = "ak880x-led",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_led_device);
+
+struct platform_device ak880x_rtc_device = {
+	.name = "ak880x-rtc",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_rtc_device);
+
+struct platform_device ak880x_pwm0_device = {
+	.name = "ak880x-pwm",
+	.id = 0,
+};
+
+EXPORT_SYMBOL(ak880x_pwm0_device);
+
+struct platform_device ak880x_pwm1_device = {
+	.name = "ak880x-pwm",
+	.id = 1,
+};
+
+EXPORT_SYMBOL(ak880x_pwm1_device);
+
+struct platform_device ak880x_pwm2_device = {
+	.name = "ak880x-pwm",
+	.id = 2,
+};
+
+EXPORT_SYMBOL(ak880x_pwm2_device);
+
+struct platform_device ak880x_pwm3_device = {
+	.name = "ak880x-pwm",
+	.id = 3,
+};
+
+EXPORT_SYMBOL(ak880x_pwm3_device);
+
+#if 1
+struct platform_device ak880x_uart0_device = {
+	.name = "ak880x-uart",
+	.id = 0,
+};
+
+EXPORT_SYMBOL(ak880x_uart0_device);
+
+struct platform_device ak880x_uart1_device = {
+	.name = "ak880x-uart",
+	.id = 1,
+};
+
+EXPORT_SYMBOL(ak880x_uart1_device);
+
+struct platform_device ak880x_uart2_device = {
+	.name = "ak880x-uart",
+	.id = 2,
+};
+
+EXPORT_SYMBOL(ak880x_uart2_device);
+
+struct platform_device ak880x_uart3_device = {
+	.name = "ak880x-uart",
+	.id = 3,
+};
+
+EXPORT_SYMBOL(ak880x_uart3_device);
+#endif
+
+struct platform_device ak880x_ts_device = {
+	.name = "ak880x-ts",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_ts_device);
+
+static struct resource gpio_trkball_resources[] = {
+#if 0	/* NORMAL SCREEN */
+	{		/* UP IRQ */
+		.name		= "UP GPIO IRQ",
+		.start		= IRQ_GPIO_79,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* DOWN IRQ */
+		.name		= "DOWN GPIO IRQ",
+		.start		= IRQ_GPIO_77,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* LEFT IRQ */
+		.name		= "LEFT GPIO IRQ",
+		.start		= IRQ_GPIO_76,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* RIGHT IRQ */
+		.name		= "RIGHT GPIO IRQ",
+		.start		= IRQ_GPIO_78,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	},
+#else	/* ROTATE SCREEN */
+	{		/* UP IRQ */
+		.name		= "UP GPIO IRQ",
+		.start		= IRQ_GPIO_76,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* DOWN IRQ */
+		.name		= "DOWN GPIO IRQ",
+		.start		= IRQ_GPIO_78,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* LEFT IRQ */
+		.name		= "LEFT GPIO IRQ",
+		.start		= IRQ_GPIO_77,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* RIGHT IRQ */
+		.name		= "RIGHT GPIO IRQ",
+		.start		= IRQ_GPIO_79,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	},
+#endif
+};
+
+struct platform_device ak880x_gpio_trkball_device = {
+	.name		= "ak880x-trkball",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(gpio_trkball_resources),
+	.resource	= gpio_trkball_resources,
+};
+
+EXPORT_SYMBOL(ak880x_gpio_trkball_device);
+
+struct platform_device ak880x_kpd_device = {
+	.name = "ak880x-kpd",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_kpd_device);
+
+struct platform_device ak880x_sdio_device = {
+	.name = "ak880x-sdio",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_sdio_device);
+
+/* AK88 AD/DA for sound system */
+struct platform_device ak880x_snd_device = {
+	.name = "ak880x-snd",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_snd_device);
+
+/* AK88 SPI */
+static struct resource ak880x_spi0_resource[] = {
+	[0] = {
+	       .start = AK88_PA_SPI0,
+	       .end = AK88_PA_SPI0 + 0x23,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .start = IRQ_SPI1,
+	       .end = IRQ_SPI1,
+	       .flags = IORESOURCE_IRQ,
+	       }
+};
+
+struct platform_device ak880x_spi0_device = {
+	.name = "ak880x-spi",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak880x_spi0_resource),
+	.resource = ak880x_spi0_resource,
+};
+
+EXPORT_SYMBOL(ak880x_spi0_device);
+
+struct platform_device ak880x_lcd_device = {
+	.name = "ak880x-lcd",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_lcd_device);
+
+struct platform_device ak880x_osd_device = {
+	.name = "ak880x-osd",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_osd_device);
+
+struct platform_device ak880x_tvout_device = {
+	.name = "ak880x-tvout",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_tvout_device);
+
+struct platform_device ak880x_nand_device = {
+	.name = "ak880x-nand",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_nand_device);
+
+struct platform_device ak880x_i2c_device = {
+	.name = "ak880x-i2c",
+	.id = -1,
+};
+
+EXPORT_SYMBOL(ak880x_i2c_device);
+
+/* MMC/SD */
+static struct resource ak880x_mmc_resource[] = {
+	[0] = {
+		.start = 0x20020000,
+		.end = 0x20020000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC_SD,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct ak88_mci_platform_data mci_plat_data = {
+#ifdef CONFIG_BOARD_AK8801EPC
+	.gpio_cd  = AK88_GPIO_12,
+	.gpio_wp  = AK88_GPIO_19,
+#elif defined CONFIG_BOARD_AK8802EBOOK
+	.gpio_cd  = AK88_GPIO_7,
+	.gpio_wp  = AK88_GPIO_10,
+#else
+#error "board defined error"
+#endif
+};
+
+struct platform_device ak880x_mmc_device = {
+	.name = "ak88_mci",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak880x_mmc_resource),
+	.resource = ak880x_mmc_resource,
+	.dev = {
+		.platform_data = &mci_plat_data,
+	},
+};
+
+EXPORT_SYMBOL(ak880x_mmc_device);
+
+/* USB */
+static struct resource ak880x_usb_resource[] = {
+	[0] = {
+	       .start = 0x70000000,
+	       .end = 0x700007ff,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .name = "usb mcu irq",
+	       .start = IRQ_USBOTG_MCU,
+	       .flags = IORESOURCE_IRQ,
+	       },
+	[2] = {
+	       .name = "usb dma irq",
+	       .start = IRQ_USBOTG_DMA,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+struct platform_device ak880x_usb_device = {
+	.name = "ak880x_udc",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak880x_usb_resource),
+	.resource = ak880x_usb_resource,
+};
+
+EXPORT_SYMBOL(ak880x_usb_device);
+
+#if 0
+
+/* --------------------------------------------------------------------
+ *  UART
+ * --------------------------------------------------------------------*/
+
+#if defined(CONFIG_SERIAL_AK88)
+
+static struct resource uart0_resources[] = {
+	[0] = {
+		.start	= (int)AK88_UART_CFG_REG1(0) ,
+		.end	= (int)AK88_UART_CFG_REG1(0) + 0x100,
+		.flags	= (int)IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_UART0,
+		.end	= IRQ_UART0,
+		.flags	= IORESOURCE_IRQ,
+	},
+
+	[2] = {
+		.start	= (int)AK88_VA_L2BUF + 0x1000,         //buf8 ,sendbuf
+		.end	= (int)AK88_VA_L2BUF + 0x1000+0x80-1, 
+		.flags	= (int)IORESOURCE_MEM,
+	},
+	[3] = {
+		.start	= (int)AK88_VA_L2BUF + 0x1000+0x80,    //buf9 ,recvbuf
+		.end	= (int)AK88_VA_L2BUF + 0x1000+0x80+0x80-1, 
+		.flags	= (int)IORESOURCE_MEM,
+	},
+
+};
+ 
+static struct resource uart3_resources[] = {
+	[0] = {
+		.start	= (int)AK88_UART_CFG_REG1(3) ,
+		.end	= (int)AK88_UART_CFG_REG1(3) + 0x100,
+		.flags	= (int)IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_UART3,
+		.end	= IRQ_UART3,
+		.flags	= IORESOURCE_IRQ,
+	},
+ 
+	[2] = {
+		.start	= (int)AK88_VA_L2BUF + 0x1300,         //buf14,sendbuf
+		.end	= (int)AK88_VA_L2BUF + 0x1300+0x80-1,   
+		.flags	= (int)IORESOURCE_MEM,
+	},
+	[3] = {
+		.start	= (int)AK88_VA_L2BUF + 0x1300+0x80,    //buf15,recvbuf
+		.end	= (int)AK88_VA_L2BUF + 0x1300+0x80+0x80-1,   
+		.flags	= (int)IORESOURCE_MEM,
+	},
+
+};
+ 
+static struct platform_device ak880x_uart0_device_lynn = {
+	.name		= "ak880x_serial",
+ 	.id		= 0,
+ 	.resource	= uart0_resources,
+	.num_resources	= ARRAY_SIZE(uart0_resources),
+};
+
+static struct platform_device ak880x_uart3_device_lynn = {
+	.name		= "ak880x_serial",
+ 	.id		= 3,
+ 	.resource	= uart3_resources,
+	.num_resources	= ARRAY_SIZE(uart3_resources),
+};
+
+static inline void configure_uart0_pins(void)
+{
+	//at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	//at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+
+    //set sharepin
+//#define AK88_SHAREPIN_CTRL    (AK88_VA_SYS+0x0078)   //0xF0000078
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+
+//all bits default is 0, = Corresponding pin is used as GPIO
+//bit[9] : 1=corresponding are used as {URD1,UTD1}  // gpio[15:14]
+//bit[14]: 1=corresponding are used as {URD4,UTD4}  // gpio[25:24]
+
+ 	AKSET_BITS(1UL<<9,AK88_SHAREPIN_CTRL);
+
+        //open power clock
+//#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)   //0xF000000C
+//bit[15],0 = to enable L2 controller/UART1 working clock
+
+ 	AKCLR_BITS(1UL<<15,AK88_POWER_CLOCK); 
+}
+
+
+static inline void configure_uart3_pins(void)
+{
+	//at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
+	//at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
+
+    //set sharepin
+//#define AK88_SHAREPIN_CTRL    (AK88_VA_SYS+0x0078)   //0xF0000078
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+
+//all bits default is 0, = Corresponding pin is used as GPIO
+//bit[9] : 1=corresponding are used as {URD1,UTD1}  // gpio[15:14]
+//bit[14]: 1=corresponding are used as {URD4,UTD4}  // gpio[25:24]
+//bit[15]: 1=corresponding are used as {CTS4,RTS4}  // gpio[27:26]
+
+//#define AK88_SHAREPIN_CTRL2    (AK88_VA_SYS+0x0074)   //0xF0000074
+//bit[2:1] 00:reserved
+//	   01 =	Corresponding pins are used as those of UART4
+//	   10 =	Corresponding pins are used as those of SDIO interface
+//	   11:reserved
+
+	AKSET_BITS(1UL<<14,AK88_SHAREPIN_CTRL);
+	AKSET_BITS(1UL<<15,AK88_SHAREPIN_CTRL);
+	AKCLR_BITS(3UL<<1,AK88_SHAREPIN_CTRL2);
+	AKSET_BITS(1UL<<1,AK88_SHAREPIN_CTRL2);
+
+        //open power clock
+//#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)   //0xF000000C
+//bit[15],0 = to enable L2 controller/UART1 working clock
+//bit[24],0 = No instruction, 1 = To reset SDIO interface/UART4
+
+ 	AKCLR_BITS(1UL<<8,AK88_POWER_CLOCK); //
+
+}
+ 
+/* the UARTs to use */
+static struct platform_device *__initdata ak880x_uarts[AK88_MAX_UART];
+
+struct platform_device *ak880x_default_console_device;	/* the serial console device */
+
+void __init ak880x_register_uart(unsigned char id, unsigned char portnr)
+//register single serial device
+{
+	struct platform_device *pdev;
+
+        uart_clear_rx_status(portnr);
+        uart_clear_rx_timeout(portnr);
+        uart_clear_rx_buffull(portnr);
+	l2_clr_uartbuf_status((portnr*2+9));
+
+	switch (id) {
+		case 0:	/* DBGU */
+	 		pdev = &ak880x_uart0_device;
+ 
+			configure_uart0_pins();
+
+                        //uart_init(id,115200,132000000);  //132MHZ
+                        uart_init(portnr,115200,124000000);  //124MHZ
+ 
+ 			break;
+
+		case 3:	/* for ak8802 EBOOK DBGU */
+			pdev = &ak880x_uart3_device;
+ 
+			configure_uart3_pins();
+
+                        //uart_init(id,115200,3);
+                        uart_init(portnr,115200,132000000);   //132MHZ
+		        //uart_open_interrupt(portnr);
+
+			break;
+
+		default:
+			return;
+	}
+	pdev->id = portnr;		/* update to mapped ID */
+
+	if (portnr < AK88_MAX_UART)
+		ak880x_uarts[portnr] = pdev;
+ 
+}
+
+void __init ak880x_set_serial_console(unsigned char portnr)
+{
+	if (portnr < AK88_MAX_UART)
+		ak880x_default_console_device = ak880x_uarts[portnr];
+}
+
+void __init ak880x_add_device_serial(void)
+//add all registed serial device
+{
+	int i;
+
+	for (i = 0; i < AK88_MAX_UART; i++) {
+		if (ak880x_uarts[i])
+			platform_device_register(ak880x_uarts[i]);
+	}
+
+	if (!ak880x_default_console_device)
+		printk(KERN_INFO "AK88: No default serial console defined.\n");
+}
+
+#else
+void __init ak880x_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init ak880x_set_serial_console(unsigned portnr) {}
+void __init ak880x_add_device_serial(void) {}
+#endif
+
+#endif
+
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+//#if defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+#if defined(CONFIG_FB_AK88) || defined(CONFIG_FB_AK88_DEBUG)
+
+struct anyka_lcdfb_info;
+
+static u64 lcdc_dmamask = DMA_BIT_MASK(32);	//=1UL<<31, if(n==64) : ~0ULL
+static struct anyka_lcdfb_info lcdc_data;
+
+#define IRQ_DISP IRQ_DISPLAY_CTRL
+static struct resource lcdc_resources[] = {
+	[0] = {
+	       .start = (int)AK88_VA_DISP,
+	       .end = (int)AK88_VA_DISP + SZ_4K - 1,
+	       .flags = (int)IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .start = (int)IRQ_DISP,	//IRQ_DISP=1
+	       .end = (int)IRQ_DISP,
+	       .flags = (int)IORESOURCE_IRQ,
+	       },
+};
+
+static struct platform_device ak880x_lcdc_device = {
+	.name = "anyka_lcdfb",
+	.id = 0,
+	.dev = {
+		.dma_mask = &lcdc_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+		.platform_data = &lcdc_data,
+		},
+	.resource = lcdc_resources,
+	.num_resources = ARRAY_SIZE(lcdc_resources),
+};
+
+void __init ak880x_add_device_lcdc(struct anyka_lcdfb_info *data)
+{
+	if (!data)
+		return;
+ 
+	//set sharepin
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//bit[25]: 1=corresponding are used as {LCD_DATA[15:9]}  //gpio[68:62]
+//bit[26]: 1=corresponding are used as {LCD_DATA[8]}     //gpio[61]
+//bit[27]: 1=corresponding are used as {LCD_DATA[17:16]} //gpio[70:69] 
+
+	AKSET_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[15:9]
+	AKSET_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[8]
+	AKSET_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[17:16]
+
+	//open power clock
+//#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)   //0xF000000C
+//bit[15],0 = to enable L2 controller/UART1 working clock
+//bit[3], 0 = to enable display controller working clock
+
+	//open LCD controller clock
+	AKCLR_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+	set_ahb_priority();
+
+	lcdc_data = *data;
+	platform_device_register(&ak880x_lcdc_device);
+}
+#else
+void __init ak880x_add_device_lcdc(struct anyka_lcdfb_info *data)
+{
+}
+#endif
diff --git a/arch/arm/mach-ak88/devices.h b/arch/arm/mach-ak88/devices.h
new file mode 100644
index 00000000000..fa62316bc13
--- /dev/null
+++ b/arch/arm/mach-ak88/devices.h
@@ -0,0 +1,42 @@
+#ifndef _MACH_DEVICES_H
+#define _MACH_DEVICES_H
+
+extern struct platform_device ak880x_led_device;
+
+extern struct platform_device ak880x_rtc_device;
+
+extern struct platform_device ak880x_pwm0_device;
+extern struct platform_device ak880x_pwm1_device;
+extern struct platform_device ak880x_pwm2_device;
+extern struct platform_device ak880x_pwm3_device;
+
+extern struct platform_device ak880x_uart0_device;
+extern struct platform_device ak880x_uart1_device;
+extern struct platform_device ak880x_uart2_device;
+extern struct platform_device ak880x_uart3_device;
+
+extern struct platform_device ak880x_ts_device;
+
+extern struct platform_device ak880x_gpio_trkball_device;
+
+extern struct platform_device ak880x_kpd_device;
+
+extern struct platform_device ak880x_sdio_device;
+
+extern struct platform_device ak880x_snd_device;
+
+extern struct platform_device ak880x_spi0_device;
+extern struct platform_device ak880x_spi1_device;
+
+extern struct platform_device ak880x_lcd_device;
+extern struct platform_device ak880x_osd_device;
+extern struct platform_device ak880x_tvout_device;
+
+extern struct platform_device ak880x_nand_device;
+extern struct platform_device ak880x_i2c_device;
+
+extern struct platform_device ak880x_mmc_device;
+
+extern struct platform_device ak880x_usb_device;
+
+#endif
diff --git a/arch/arm/mach-ak88/dma.c b/arch/arm/mach-ak88/dma.c
new file mode 100644
index 00000000000..8b137891791
--- /dev/null
+++ b/arch/arm/mach-ak88/dma.c
@@ -0,0 +1 @@
+
diff --git a/arch/arm/mach-ak88/gpio.c b/arch/arm/mach-ak88/gpio.c
new file mode 100644
index 00000000000..19d706a9142
--- /dev/null
+++ b/arch/arm/mach-ak88/gpio.c
@@ -0,0 +1,253 @@
+/*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/gpio.h>
+
+void ak880x_sharepin_cfg1(unsigned char to, unsigned char offset)
+{
+	void __iomem *base = AK88_SHAREPIN_CON1;
+	unsigned long val = 0;
+	unsigned long flags;
+	if (offset > 31) {
+		/*print */
+		return;
+	}
+
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == to)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_sharepin_cfg1);
+
+void ak880x_sharepin_cfg2(unsigned char to, unsigned char offset)
+{
+	void __iomem *base = AK88_SHAREPIN_CON2;
+	unsigned long val = 0;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == offset) {
+		if (0 == to)
+			val &= ~1;
+		else
+			val |= 1;
+	} else {
+		val &= ~(3 << offset);
+		val |= (to << offset);
+	}
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_sharepin_cfg2);
+
+void ak880x_gpio_cfgpin(unsigned int pin, unsigned int function)
+{
+
+	void __iomem *base = AK88_GPIO_DIR_BASE(pin);
+	unsigned long val = 0;
+	unsigned long flags;
+	unsigned int offset = ((pin) & 31);
+	if (pin >= (96 + 21)) {
+		/*printk */
+		return;
+	}
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == function)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_cfgpin);
+
+unsigned int ak880x_gpio_getcfg(unsigned int pin)
+{
+	void __iomem *base = AK88_GPIO_DIR_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+	return __raw_readl(base) & (1 << offset);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_getcfg);
+
+void ak880x_gpio_setpin(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK88_GPIO_OUT_BASE(pin);
+	unsigned long val = 0;
+	unsigned long flags;
+	unsigned int offset = ((pin) & 31);
+	if (pin >= (96 + 21)) {
+		/*printk */
+		return;
+	}
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == to)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_setpin);
+
+unsigned int ak880x_gpio_getpin(unsigned int pin)
+{
+	void __iomem *base = NULL;
+	unsigned int offset = 0;
+
+#if	defined(CONFIG_CPU_AK7801)
+	/* only for ak7801, ak880x fixed */
+	if (pin > AK88_DGPIO_36)
+		pin -= 3;
+	else if ((pin >= AK88_DGPIO_34) && (pin <= AK88_DGPIO_36))
+		return 0;
+#endif
+
+	base = AK88_GPIO_IN_BASE(pin);
+	offset = ((pin) & 31);
+
+	return __raw_readl(base) & (1 << offset);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_getpin);
+
+void ak880x_gpio_pullup(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK88_PPU_PPD_BASE(pin);
+	unsigned long val = 0;
+	unsigned long flags;
+	unsigned int offset = ((pin) & 31);
+	if (pin > 128) {
+		/*printk */
+		return;
+	}
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == to)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_pullup);
+
+void ak880x_gpio_inten(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK88_GPIO_INTEN_BASE(pin);
+	unsigned long val = 0;
+	unsigned long flags;
+	unsigned int offset = ((pin) & 31);
+	if (pin > 128) {
+		/*printk */
+		return;
+	}
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == to)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_inten);
+
+void ak880x_gpio_intpol(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK88_GPIO_INTPOL_BASE(pin);
+	unsigned long val = 0;
+	unsigned long flags;
+	unsigned int offset = ((pin) & 31);
+	if (pin >= (96 + 21)) {
+		/*printk */
+		return;
+	}
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	if (0 == to)
+		val &= ~(1 << offset);
+	else
+		val |= (1 << offset);
+	__raw_writel(val, base);
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_gpio_intpol);
+
+void ak880x_ioctl(unsigned int offset, const unsigned int to)
+{
+	unsigned long val = 0;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	if (offset < 32) {
+		val = __raw_readl(AK88_IO_CON1);
+		if (0 == to)
+			val &= ~(1 << offset);
+		else
+			val |= (1 << offset);
+		__raw_writel(val, AK88_IO_CON1);
+	} else {
+		offset -= 32;
+		val = __raw_readl(AK88_IO_CON2);
+		if (0 == to)
+			val &= ~(1 << offset);
+		else
+			val |= (1 << offset);
+		__raw_writel(val, AK88_IO_CON2);
+	}
+
+	local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(ak880x_ioctl);
+
+unsigned int ak880x_gpio_to_irq(unsigned int pin)
+{
+	return (IRQ_GPIO_0 + (pin - AK88_GPIO_0));
+}
+
+EXPORT_SYMBOL(ak880x_gpio_to_irq);
+
+unsigned int ak880x_irq_to_gpio(unsigned int irq)
+{
+	return (AK88_GPIO_0 + (irq - IRQ_GPIO_0));
+}
+
+EXPORT_SYMBOL(ak880x_irq_to_gpio);
diff --git a/arch/arm/mach-ak88/include/mach/ak-sharepin.h b/arch/arm/mach-ak88/include/mach/ak-sharepin.h
new file mode 100644
index 00000000000..226ed0f55be
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/ak-sharepin.h
@@ -0,0 +1,145 @@
+#ifndef _AK88_SHRPIN_H_
+#define _AK88_SHRPIN_H_
+
+#define AK_SHRPIN_CTRL1		(AK88_VA_SYSCTRL+0x78)
+#define	AK_SHRPIN_CTRL2		(AK88_VA_SYSCTRL+0x74)
+
+/* macro for setting sharepin control register 1 */
+
+#define AK_SHRPIN_GRP0			(0)
+#define AK_SHRPIN_GRP0_GPIO		(0<<0)
+#define AK_SHRPIN_GRP0_JTAG_PCM		(1<<0)
+
+#define AK_SHRPIN_GRP1			(1)
+#define AK_SHRPIN_GRP1_GPIO		(0<<1)
+#define AK_SHRPIN_GRP1_RTCK		(1<<1)
+
+#define AK_SHRPIN_GRP2			(2)
+#define AK_SHRPIN_GRP2_GPIO		(0<<2)
+#define AK_SHRPIN_GRP2_I2S		(1<<2)
+
+#define AK_SHRPIN_GRP3			(3)
+#define AK_SHRPIN_GRP3_GPIO		(0<<3)
+#define AK_SHRPIN_GRP3_OTG		(1<<3)
+
+#define AK_SHRPIN_GRP4			(4)
+#define AK_SHRPIN_GRP4_GPIO		(0<<4)
+#define AK_SHRPIN_GRP4_PWM1		(1<<4)
+
+#define AK_SHRPIN_GRP5			(5)
+#define AK_SHRPIN_GRP5_GPIO		(0<<5)
+#define AK_SHRPIN_GRP5_PWM2		(1<<5)
+
+#define AK_SHRPIN_GRP6			(6)
+#define AK_SHRPIN_GRP6_GPIO		(0<<6)
+#define AK_SHRPIN_GRP6_PWM3		(1<<6)
+
+#define AK_SHRPIN_GRP7			(7)
+#define AK_SHRPIN_GRP7_GPIO		(0<<7)
+#define AK_SHRPIN_GRP7_PWM4		(1<<7)
+
+#define AK_SHRPIN_GRP8			(8)
+#define AK_SHRPIN_GRP8_GPIO		(0<<8)
+#define AK_SHRPIN_GRP8_I2S_MCLK		(1<<8)
+
+#define AK_SHRPIN_GRP9			(9)
+#define AK_SHRPIN_GRP9_GPIO		(0<<9)
+#define AK_SHRPIN_GRP9_UART1		(1<<9)
+
+#define AK_SHRPIN_GRP10			(10)
+#define AK_SHRPIN_GRP10_GPIO		(0<<10)
+#define AK_SHRPIN_GRP10_UART2		(1<<10)
+
+#define AK_SHRPIN_GRP11			(11)
+#define AK_SHRPIN_GRP11_GPIO		(0<<11)
+#define AK_SHRPIN_GRP11_UART2		(1<<11)
+
+#define AK_SHRPIN_GRP12			(12)
+#define AK_SHRPIN_GRP12_GPIO		(0<<12)
+#define AK_SHRPIN_GRP12_UART3		(1<<12)
+
+#define AK_SHRPIN_GRP13			(13)
+#define AK_SHRPIN_GRP13_GPIO		(0<<13)
+#define AK_SHRPIN_GRP13_UART3		(1<<13)
+
+#define AK_SHRPIN_GRP14			(14)
+#define AK_SHRPIN_GRP14_GPIO		(0<<14)
+#define AK_SHRPIN_GRP14_UART4_SDIO	(1<<14)
+
+#define AK_SHRPIN_GRP15			(15)
+#define AK_SHRPIN_GRP15_GPIO		(0<<15)
+#define AK_SHRPIN_GRP15_UART4_SDIO	(1<<15)
+
+#define AK_SHRPIN_GRP16			(16)
+#define AK_SHRPIN_GRP16_GPIO		(0<<16)
+#define AK_SHRPIN_GRP16_NFC_MDAT	(1<<16)
+
+#define AK_SHRPIN_GRP17			(17)
+#define AK_SHRPIN_GRP17_GPIO		(0<<17)
+#define AK_SHRPIN_GRP17_NFC_MDAT	(1<<17)
+
+#define AK_SHRPIN_GRP18			(18)
+#define AK_SHRPIN_GRP18_GPIO		(0<<18)
+#define AK_SHRPIN_GRP18_NFC_MDAT	(1<<18)
+
+#define AK_SHRPIN_GRP19			(19)
+#define AK_SHRPIN_GRP19_GPIO		(0<<19)
+#define AK_SHRPIN_GRP19_NFC_CE		(1<<19)
+
+#define AK_SHRPIN_GRP22			(22)
+#define AK_SHRPIN_GRP22_GPIO		(0<<22)
+#define AK_SHRPIN_GRP22_NFC_RDY		(1<<22)
+
+#define AK_SHRPIN_GRP24			(24)
+#define AK_SHRPIN_GRP24_GPIO		(0<<24)
+#define AK_SHRPIN_GRP24_VI		(1<<24)
+
+#define AK_SHRPIN_GRP25			(25)
+#define AK_SHRPIN_GRP25_GPIO		(0<<25)
+#define AK_SHRPIN_GRP25_LCD_DATA	(1<<25)
+
+#define AK_SHRPIN_GRP26			(26)
+#define AK_SHRPIN_GRP26_GPIO		(0<<26)
+#define AK_SHRPIN_GRP26_LCD_DATA	(1<<26)
+
+#define AK_SHRPIN_GRP27			(27)
+#define AK_SHRPIN_GRP27_GPIO		(0<<27)
+#define AK_SHRPIN_GRP27_LCD_DATA	(1<<27)
+
+#define AK_SHRPIN_GRP28			(28)
+#define AK_SHRPIN_GRP28_GPIO		(0<<28)
+#define AK_SHRPIN_GRP28_MPU_RST		(1<<28)
+
+#define AK_SHRPIN_GRP29			(29)
+#define AK_SHRPIN_GRP29_GPIO		(0<<29)
+#define AK_SHRPIN_GRP29_MDAT		(1<<29)
+
+#define AK_SHRPIN_GRP30			(30)
+#define AK_SHRPIN_GRP30_GPIO		(0<<30)
+#define AK_SHRPIN_GRP30_SPI1		(1<<30)
+
+#define AK_SHRPIN_GRP31			(31)
+#define AK_SHRPIN_GRP31_GPIO		(0<<31)
+#define AK_SHRPIN_GRP31_SPI2		(1<<31)
+
+#define AK_SHRPIN_RESERVED1		(20)
+#define	AK_SHPRIN_RESERVED2		(21)
+#define AK_SHRPIN_RESERVED3		(23)
+
+/* macro for setting sharepin control register 2 */
+#define AK_SHRPIN2_GRP1_MASK		(0x1<<0)
+#define AK_SHRPIN2_GRP1_PCM		(0x0<<0)
+#define AK_SHRPIN2_GRP1_JTAG		(0x1<<0)
+
+#define AK_SHRPIN2_GRP2_MASK		(0x3<<1)
+#define AK_SHRPIN2_GRP2_UART4		(0x1<<1)
+#define AK_SHRPIN2_GRP2_SDIO		(0x2<<1)
+
+#define AK_SHRPIN2_GRP3_MASK		(0x3<<3)
+#define AK_SHRPIN2_GRP3_NFC		(0x1<<3)
+#define AK_SHRPIN2_GRP3_MMC		(0x2<<3)
+
+#define AK_SHRPIN2_GRP4_MASK		(0x3<<5)
+#define	AK_SHRPIN2_GRP4_MDAT0		(0x1<<5)
+
+#endif				/* _AK88_SHRPIN_H_ */
diff --git a/arch/arm/mach-ak88/include/mach/ak880x_addr.h b/arch/arm/mach-ak88/include/mach/ak880x_addr.h
new file mode 100644
index 00000000000..036b0e7a9f7
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/ak880x_addr.h
@@ -0,0 +1,346 @@
+/*
+*   Filename:	linux/arch/arm/mach-ak880x/include/mach/ak880x_addr.h
+*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+*/
+
+#ifndef _AK88_ADDR_H_
+#define _AK88_ADDR_H_
+
+#include <mach/map.h>
+
+#define AK88_SYSCTRL_REG(x)		(AK88_VA_SYSCTRL + (x))
+#define AK88_DISPLAY_REG(x)		(AK88_VA_DISPLAY + (x))
+#define AK88_MMC_REG(x)		(AK88_VA_MMC + (x))
+#define AK88_SDIO_REG(x)		(AK88_VA_SDIO + (x))
+#define AK88_SPI1_REG(x)		(AK88_VA_SPI0 + (x))
+#define AK88_SPI2_REG(x)		(AK88_VA_SPI0 + 0x1000 + (x))
+#define AK88_UART1_REG(x)		(AK88_VA_UART	+ (x))
+#define AK88_UART2_REG(x)		(AK88_VA_UART	+ 0x1000 + (x))
+#define AK88_UART3_REG(x)		(AK88_VA_UART	+ 0x2000 + (x))
+#define AK88_UART4_REG(x)		(AK88_VA_UART	+ 0x3000 + (x))
+#define AK88_NFCTRL_REG(x)		(AK88_VA_NFCTRL + (x))
+#define AK88_ECC_REG(x)		(AK88_VA_NFCTRL + 0x1000 + (x))
+#define AK88_L2CTRL_REG(x)		(AK88_VA_L2CTRL + (x))
+#define AK88_RAMCTRL_REG(x)		(AK88_VA_RAMCTRL + (x))
+#define AK88_DACCTRL_REG(x)		(AK88_VA_DACCTRL + (x))
+#define AK88_CAMIF_REG(x)		(AK88_VA_CAMIF + (x))
+
+/* Chip ID register */
+#define rCHIP_ID	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x00))	/*Chip ID register */
+
+/* System control registers */
+#define rCLK_DIV1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x04))	/*Clock divider register 1 */
+#define rCLK_DIV2 	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x08))	/*Clock divider register 2 */
+#define rCLK_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x0C))	/*Clock control and soft rest control register */
+#define rN_CON		(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xDC))	/*N configuration register */
+#define rMULFUN_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x58))	/*Multiple function control register */
+
+#define rIRQ_MASK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x34))	/*Interrupt mask register for IRQ */
+#define rFIQ_MASK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x38))	/*Interrupt mask register for FIQ */
+#define rINT_STAT	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xCC))	/*Interrupt status register */
+#define rINT_STATEN	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x4C))	/*Interrupt Enable/status register of system control module */
+
+#define rWKUPGPIO_POL	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x3C))	/*Wake-up GPIO polarity selection */
+#define rWKUPGPIO_CLR	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x40))	/*Clear wake-up GPIO status */
+#define rWKUPGPIO_EN	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x44))	/*Enabling the wake-up function of corresponding wake-up GPIOS */
+#define rWKUPGPIO_STAT	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x48))	/*Wake-up GPIO status register, displaying current wake-up GPIO status */
+
+#define rRTCUSB_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x50))	/*RTC configuratio and USB control register */
+#define rRTC_BOOTMOD	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x54))	/*RTC read back and bootup mode register */
+
+#define rSHAREPIN_CON1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x78))	/*Shared-pin control register 1 */
+#define rSHAREPIN_CON2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x74))	/*Shared-pin control register 2 */
+#define rPPU_PPD1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x9C))	/*Programmable Pull-ups/Pull-downs register 1 */
+#define rPPU_PPD2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xA0))	/*Programmable Pull-ups/Pull-downs register 2 */
+#define rPPU_PPD3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xA4))	/*Programmable Pull-ups/Pull-downs register 3 */
+#define rPPU_PPD4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xA8))	/*Programmable Pull-ups/Pull-downs register 4 */
+
+ /*CRC*/
+#define rCRC_POLYLEN	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xAC))	/*Polynomial's length and start CRC */
+#define rCRC_COEFCON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xB0))	/*Coefficient configuration */
+#define rCRC_RESULT	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xD0))	/*CRC result */
+#define rIO_CON1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xD4))	/*IO control register 1 */
+#define rIO_CON2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xD8))	/*IO control register 2 */
+/* Analog control */
+#define rANALOG_CON1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x5C))
+#define rADC1_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x60))
+#define rADC2_CON	(*(volatile unsigned long *)(AK88_VA_SUBCTRL + 0x72000))
+#define rADC2_DAT	(*(volatile unsigned long *)(AK88_VA_SUBCTRL + 0x72004))
+#define rANALOG_CON2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x64))
+#define rTS_XVAL	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x68))
+#define rTS_YVAL	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x6C))
+#define rADC1_STAT	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x70))
+/* PWM */
+#define rPWM1_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x2C))
+#define rPWM2_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x30))
+#define	rPWM3_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xB4))
+#define rPWM4_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xB8))
+/* Timers */
+#define rTIMER1_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x18))
+#define rTIMER2_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x1C))
+#define rTIMER3_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x20))
+#define rTIMER4_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x24))
+#define rTIMER5_CON	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x28))
+#define rTIMER1_RDBACK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x100))
+#define rTIMER2_RDBACK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x104))
+#define rTIMER3_RDBACK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x108))
+#define rTIMER4_RDBACK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x10C))
+#define rTIMER5_RDBACK	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x110))
+/* GPIOS */
+#define rGPIO_DIR1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x7C))
+#define rGPIO_DIR2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x84))
+#define rGPIO_DIR3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x8C))
+#define rGPIO_DIR4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x94))
+#define rGPIO_OUT1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x80))
+#define rGPIO_OUT2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x88))
+#define rGPIO_OUT3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x90))
+#define rGPIO_OUT4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0x98))
+#define rGPIO_IN1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xBC))
+#define rGPIO_IN2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xC0))
+#define rGPIO_IN3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xC4))
+#define rGPIO_IN4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xC8))
+#define rGPIO_INT1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xE0))
+#define rGPIO_INT2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xE4))
+#define rGPIO_INT3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xE8))
+#define rGPIO_INT4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xEC))
+#define rGPIO_INTPOL1	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xF0))
+#define rGPIO_INTPOL2	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xF4))
+#define rGPIO_INTPOL3	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xF8))
+#define rGPIO_INTPOL4	(*(volatile unsigned long *)AK88_SYSCTRL_REG(0xFC))
+/* L2 controller */
+#define rL2_ADDRBUF0	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x00))	/*DMA address information buffer0~buffer15 */
+#define	rL2_ADDRBUF1	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x04))
+#define	rL2_ADDRBUF2	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x08))
+#define	rL2_ADDRBUF3	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x0C))
+#define	rL2_ADDRBUF4	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x10))
+#define	rL2_ADDRBUF5	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x14))
+#define	rL2_ADDRBUF6	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x18))
+#define	rL2_ADDRBUF7	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x1C))
+#define	rL2_ADDRBUF8	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x20))
+#define	rL2_ADDRBUF9	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x24))
+#define	rL2_ADDRBUF10	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x28))
+#define	rL2_ADDRBUF11	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x2C))
+#define	rL2_ADDRBUF12	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x30))
+#define	rL2_ADDRBUF13	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x34))
+#define	rL2_ADDRBUF14	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x38))
+#define	rL2_ADDRBUF15	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x3C))
+#define rL2_CONBUF0	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x40))	/*DMA opeeration times buufer0~buffer15 */
+#define rL2_CONBUF1	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x44))
+#define rL2_CONBUF2	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x48))
+#define rL2_CONBUF3	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x4C))
+#define rL2_CONBUF4	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x50))
+#define rL2_CONBUF5	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x54))
+#define rL2_CONBUF6	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x58))
+#define rL2_CONBUF7	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x5C))
+#define rL2_CONBUF8	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x60))
+#define rL2_CONBUF9	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x64))
+#define rL2_CONBUF10	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x68))
+#define rL2_CONBUF11	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x6C))
+#define rL2_CONBUF12	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x70))
+#define rL2_CONBUF13	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x74))
+#define rL2_CONBUF14	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x78))
+#define rL2_CONBUF15	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x7C))
+#define rL2_DMAREQ	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x80))	/*DMA request configuration */
+#define rL2_FRACDMAADDR	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x84))	/*Fraction DMA address information */
+#define rL2_CONBUF0_7	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x88))	/*Buffer0~buffer7 configuration */
+#define rL2_CONBUF8_15	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x8C))	/*CPU-controlled buffer and buffer8~buffer15 configuration */
+#define rL2_BUFASSIGN1	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x90))	/*Buffer assignment */
+#define rL2_BUFASSIGN2	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x94))	/*Buffer assignment */
+#define rL2_LDMACON	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x98))	/*Configuration of LDMA */
+#define rL2_BUFINTEN	(*(volatile unsigned long *)AK88_L2CTRL_REG(0x9C))	/*This register enables/disables the buffer interrupts */
+#define rL2_BUFSTAT1	(*(volatile unsigned long *)AK88_L2CTRL_REG(0xA0))	/*Buffer status register 1 */
+#define rL2_BUFSTAT2	(*(volatile unsigned long *)AK88_L2CTRL_REG(0xA8))	/*Buffer status register 2 */
+#define rCRC_CON	(*(volatile unsigned long *)AK88_L2CTRL_REG(0xA4))	/*CRC configuration register */
+/* RAM controller */
+#define rMEM_CON1	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x00))	/*RAM controller configuration register 1 */
+#define rMEM_CON2	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x04))	/*RAM controller configuration register 2 */
+#define rMEM_CON3	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x08))	/*RAM controller configuration register 3 */
+#define rDMA_PRI1	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x0C))	/*DMA priority configuration register 1 */
+#define rDMA_PRI2	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x10))	/*DMA priority configuration register 2 */
+#define rAHB_PRI	(*(volatile unsigned long *)AK88_RAMCTRL_REG(0x14))	/*AHB priority configuration register */
+/* Nand flash controller */
+#define rNFC_COMM1	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x100))	/*Nand flash command register 1 */
+#define rNFC_COMM2	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x104))	/*Nand flash command register 2 */
+#define rNFC_COMM3	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x108))	/*Nand flash command register 3 */
+#define rNFC_COMM4	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x10C))	/*Nand flash command register 4 */
+#define rNFC_COMM5	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x110))	/*Nand flash command register 5 */
+#define rNFC_COMM6	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x114))	/*Nand flash command register 6 */
+#define rNFC_COMM7	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x118))	/*Nand flash command register 7 */
+#define rNFC_COMM8	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x11C))	/*Nand flash command register 8 */
+#define rNFC_COMM9	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x120))	/*Nand flash command register 9 */
+#define rNFC_COMM10	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x124))	/*Nand flash command register 10 */
+#define rNFC_COMM11	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x128))	/*Nand flash command register 11 */
+#define rNFC_COMM12	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x12C))	/*Nand flash command register 12 */
+#define rNFC_COMM13	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x130))	/*Nand flash command register 13 */
+#define rNFC_COMM14	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x134))	/*Nand flash command register 14 */
+#define rNFC_COMM15	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x138))	/*Nand flash command register 15 */
+#define rNFC_COMM16	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x13C))	/*Nand flash command register 16 */
+#define rNFC_COMM17	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x140))	/*Nand flash command register 17 */
+#define rNFC_COMM18	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x144))	/*Nand flash command register 18 */
+#define rNFC_COMM19	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x148))	/*Nand flash command register 19 */
+#define rNFC_COMM20	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x14C))	/*Nand flash command register 20 */
+#define rNFC_STAT1	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x150))	/*Nand flash status register 1 */
+#define rNFC_STAT2	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x154))	/*Nand flash status register 2 */
+#define rNFC_CONSTAT	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x158))	/*Nand flash control/status register */
+#define rNFC_COMMLEN	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x15C))	/*Nand flash command length */
+#define rNFC_DATALEN	(*(volatile unsigned long *)AK88_NFCTRL_REG(0x160))	/*Nand flash data length */
+/* ECC sub-module controller */
+#define rECC_CON	(*(volatile unsigned long *)AK88_ECC_REG(0x00))	/*ECC control register */
+#define rECC_ERRPOS1	(*(volatile unsigned long *)AK88_ECC_REG(0x04))	/*Error posision register 1 */
+#define rECC_ERRPOS2	(*(volatile unsigned long *)AK88_ECC_REG(0x08))	/*Error posision register 2 */
+#define rECC_ERRPOS3	(*(volatile unsigned long *)AK88_ECC_REG(0x0C))	/*Error posision register 3 */
+#define rECC_ERRPOS4	(*(volatile unsigned long *)AK88_ECC_REG(0x10))	/*Error posision register 4 */
+#define rECC_ERRPOS5	(*(volatile unsigned long *)AK88_ECC_REG(0x14))	/*Error posision register 5 */
+#define rECC_ERRPOS6	(*(volatile unsigned long *)AK88_ECC_REG(0x18))	/*Error posision register 6 */
+#define rECC_ERRPOS7	(*(volatile unsigned long *)AK88_ECC_REG(0x1C))	/*Error posision register 7 */
+#define rECC_ERRPOS8	(*(volatile unsigned long *)AK88_ECC_REG(0x20))	/*Error posision register 8 */
+/* DAC controller */
+#define rDAC_CON	(*(volatile unsigned long *)AK88_DACCTRL_REG(0x00))	/*DAC configuration register */
+#define rIIS_CON	(*(volatile unsigned long *)AK88_DACCTRL_REG(0x04))	/*IIS configuration register */
+#define rDAC_CPUDATA	(*(volatile unsigned long *)AK88_DACCTRL_REG(0x08))	/*Data from CPU */
+/* Camera controller */
+#define rCAM_SENSORCOMM		(*(volatile unsigned long *)AK88_CAMIF_REG(0x00))	/*Image capturing command */
+#define rCAM_IMAGEINF1		(*(volatile unsigned long *)AK88_CAMIF_REG(0x04))	/*Source/destination image horizontal length */
+#define rCAM_IMAGEINF2		(*(volatile unsigned long *)AK88_CAMIF_REG(0x08))	/*Horizontal scalling information */
+#define rCAM_IMAGEINF3		(*(volatile unsigned long *)AK88_CAMIF_REG(0x0C))	/*Source/Destination image vertical length */
+#define rCAM_IMAGEINF4		(*(volatile unsigned long *)AK88_CAMIF_REG(0x10))	/*Horizontal scalling information */
+#define rCAM_ODDYADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x18))	/*DMA starting address of external RAM for Y component of odd frame */
+#define rCAM_ODDCbADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x1C))	/*DMA starting address of external RAM for Cb component of odd frame */
+#define rCAM_ODDCrADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x20))	/*DMA starting address of external RAM for Cr component of odd frame */
+#define rCAM_ODDRGBADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x24))	/*DMA starting address of external RAM for RGB/JPGE data of odd frame */
+#define rCAM_EVENYADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x28))
+#define rCAM_EVENCbADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x2C))
+#define rCAM_EVENCrADDR		(*(volatile unsigned long *)AK88_CAMIF_REG(0x30))
+#define rCAM_EVENRGBADDR	(*(volatile unsigned long *)AK88_CAMIF_REG(0x34))
+#define rCAM_SENSORCON		(*(volatile unsigned long *)AK88_CAMIF_REG(0x40))	/*Image sensor configuration */
+#define rCAM_FRAMESTAT		(*(volatile unsigned long *)AK88_CAMIF_REG(0x60))	/*Status of the current frame */
+#define rCAM_FRAMELINE		(*(volatile unsigned long *)AK88_CAMIF_REG(0x80))	/*The line number of a frame when the input data is in JPEG-compressed format */
+/* Display controller */
+#define rLCD_COMM1		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x00))	/*LCD controller command register 1 */
+#define rLCD_MPUIFCON		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x04))	/*MPU interface control */
+#define rLCD_RSTSIG		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x08))
+#define rLCD_MPURDBACK		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x0C))
+#define rLCD_RGBIFCON1		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x10))
+#define rLCD_RGBIFCON2		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x14))
+#define rLCD_RGBPGSIZE		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x18))
+#define rLCD_RGBPGOFFSET	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x1C))
+#define rLCD_OSDADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x20))
+#define rLCD_OSDOFFSET		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x24))
+#define rLCD_OSDCOLOR1		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x28))
+#define rLCD_OSDCOLOR2		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x2C))
+#define rLCD_OSDCOLOR3		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x30))
+#define rLCD_OSDCOLOR4		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x34))
+#define rLCD_OSDCOLOR5		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xD0))
+#define rLCD_OSDCOLOR6		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xD4))
+#define rLCD_OSDCOLOR7		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xD8))
+#define rLCD_OSDCOLOR8		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xDC))
+#define rLCD_OSDSIZE		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x38))
+#define rLCD_BACKCOLOR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x3C))
+#define rLCD_RGBIFCON3		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x40))
+#define rLCD_RGBIFCON4		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x44))
+#define rLCD_RGBIFCON5		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x48))
+#define rLCD_RGBIFCON6		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x4C))
+#define rLCD_RGBIFCON7		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x50))
+#define rLCD_RGBIFCON8		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x54))
+#define rLCD_RGBIFCON9		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x58))
+#define rLCD_Y1_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x5C))
+#define rLCD_Cb1_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x60))
+#define rLCD_Cr1_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x64))
+#define rLCD_YCbCr1_HINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x68))
+#define rLCD_YCbCr1_VINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x6C))
+#define rLCD_YCbCr1_SCAL	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x70))
+#define rLCD_YCbCr1_DISPINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x74))
+#define rLCD_YCbCr1_PGSIZE	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x78))
+#define rLCD_YCbCr1_PGOFFSET	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x7C))
+#define rLCD_Y2_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x80))
+#define rLCD_Cb2_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x84))
+#define rLCD_Cr2_ADDR		(*(volatile unsigned long *)AK88_DISPLAY_REG(0x88))
+#define rLCD_YCbCr2_HINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x8C))
+#define rLCD_YCbCr2_VINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x90))
+#define rLCD_YCbCr2_SCAL	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x94))
+#define rLCD_YCbCr2_DISPINFO	(*(volatile unsigned long *)AK88_DISPLAY_REG(0x98))
+#define rLCD_RGBOFFSET		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xA8))
+#define rLCD_RGBSIZE		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xAC))
+#define rLCD_DISPSIZE		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xB0))
+#define rLCD_COMM2		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xB4))
+#define rLCD_OP			(*(volatile unsigned long *)AK88_DISPLAY_REG(0xB8))
+#define rLCD_STAT		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xBC))
+#define rLCD_INTEN		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xC0))
+#define rLCD_SOFTCON		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xC8))
+#define rTV_IFCON		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xCC))
+#define rLCD_CLKCON		(*(volatile unsigned long *)AK88_DISPLAY_REG(0xE8))
+/* UART1~UART4 controllers */
+#define rUART1_CON1		(*(volatile unsigned long *)AK88_UART1_REG(0x00))
+#define rUART1_CON2		(*(volatile unsigned long *)AK88_UART1_REG(0x04))
+#define rUART1_DATACON		(*(volatile unsigned long *)AK88_UART1_REG(0x08))
+#define rUART1_TXRXBUF		(*(volatile unsigned long *)AK88_UART1_REG(0x0C))
+#define rUART2_CON1		(*(volatile unsigned long *)AK88_UART2_REG(0x00))
+#define rUART2_CON2		(*(volatile unsigned long *)AK88_UART2_REG(0x04))
+#define rUART2_DATACON		(*(volatile unsigned long *)AK88_UART2_REG(0x08))
+#define rUART2_TXRXBUF		(*(volatile unsigned long *)AK88_UART2_REG(0x0C))
+#define rUART3_CON1		(*(volatile unsigned long *)AK88_UART3_REG(0x00))
+#define rUART3_CON2		(*(volatile unsigned long *)AK88_UART3_REG(0x04))
+#define rUART3_DATACON		(*(volatile unsigned long *)AK88_UART3_REG(0x08))
+#define rUART3_TXRXBUF		(*(volatile unsigned long *)AK88_UART3_REG(0x0C))
+#define rUART4_CON1		(*(volatile unsigned long *)AK88_UART4_REG(0x00))
+#define rUART4_CON2		(*(volatile unsigned long *)AK88_UART4_REG(0x04))
+#define rUART4_DATACON		(*(volatile unsigned long *)AK88_UART4_REG(0x08))
+#define rUART4_TXRXBUF		(*(volatile unsigned long *)AK88_UART4_REG(0x0C))
+/* SPI1 SPI2 Controllers */
+#define rSPI1_CON		(*(volatile unsigned long *)AK88_SPI1_REG(0x00))
+#define rSPI1_STAT		(*(volatile unsigned long *)AK88_SPI1_REG(0x04))
+#define rSPI1_INTEN		(*(volatile unsigned long *)AK88_SPI1_REG(0x08))
+#define rSPI1_COUNT		(*(volatile unsigned long *)AK88_SPI1_REG(0x0C))
+#define rSPI1_TXBUF		(*(volatile unsigned long *)AK88_SPI1_REG(0x10))
+#define rSPI1_RXBUF		(*(volatile unsigned long *)AK88_SPI1_REG(0x14))
+#define rSPI1_OUTDATA		(*(volatile unsigned long *)AK88_SPI1_REG(0x18))
+#define rSPI1_INDATA		(*(volatile unsigned long *)AK88_SPI1_REG(0x1C))
+#define rSPI1_TIMEOUT		(*(volatile unsigned long *)AK88_SPI1_REG(0x20))
+#define rSPI2_CON		(*(volatile unsigned long *)AK88_SPI2_REG(0x00))
+#define rSPI2_STAT		(*(volatile unsigned long *)AK88_SPI2_REG(0x04))
+#define rSPI2_INTEN		(*(volatile unsigned long *)AK88_SPI2_REG(0x08))
+#define rSPI2_COUNT		(*(volatile unsigned long *)AK88_SPI2_REG(0x0C))
+#define rSPI2_TXBUF		(*(volatile unsigned long *)AK88_SPI2_REG(0x10))
+#define rSPI2_RXBUF		(*(volatile unsigned long *)AK88_SPI2_REG(0x14))
+#define rSPI2_OUTDATA		(*(volatile unsigned long *)AK88_SPI2_REG(0x18))
+#define rSPI2_INDATA		(*(volatile unsigned long *)AK88_SPI2_REG(0x1C))
+#define rSPI2_TIMEOUT		(*(volatile unsigned long *)AK88_SPI2_REG(0x20))
+/* MMC/SD controller */
+#define rSD_CLKCON		(*(volatile unsigned long *)AK88_MMC_REG(0x04))
+#define rSD_COMMARG		(*(volatile unsigned long *)AK88_MMC_REG(0x08))
+#define rSD_COMM		(*(volatile unsigned long *)AK88_MMC_REG(0x0C))
+#define rSD_COMMRESP		(*(volatile unsigned long *)AK88_MMC_REG(0x10))
+#define rSD_RESP1		(*(volatile unsigned long *)AK88_MMC_REG(0x14))
+#define rSD_RESP2		(*(volatile unsigned long *)AK88_MMC_REG(0x18))
+#define rSD_RESP3		(*(volatile unsigned long *)AK88_MMC_REG(0x1C))
+#define rSD_RESP4		(*(volatile unsigned long *)AK88_MMC_REG(0x20))
+#define rSD_DATATIMER		(*(volatile unsigned long *)AK88_MMC_REG(0x24))
+#define rSD_DATALEN		(*(volatile unsigned long *)AK88_MMC_REG(0x28))
+#define rSD_DATACON		(*(volatile unsigned long *)AK88_MMC_REG(0x2C))
+#define rSD_DATACOUNT		(*(volatile unsigned long *)AK88_MMC_REG(0x30))
+#define rSD_STAT		(*(volatile unsigned long *)AK88_MMC_REG(0x34))
+#define rSD_INTEN		(*(volatile unsigned long *)AK88_MMC_REG(0x38))
+#define rSD_DMAMOD		(*(volatile unsigned long *)AK88_MMC_REG(0x3C))
+#define rSD_CPUMOD		(*(volatile unsigned long *)AK88_MMC_REG(0x40))
+/* SDIO controller */
+#define rSDIO_CLKCON		(*(volatile unsigned long *)AK88_SDIO_REG(0x04))
+#define rSDIO_COMMARG		(*(volatile unsigned long *)AK88_SDIO_REG(0x08))
+#define rSDIO_COMM		(*(volatile unsigned long *)AK88_SDIO_REG(0x0C))
+#define rSDIO_COMMRESP		(*(volatile unsigned long *)AK88_SDIO_REG(0x10))
+#define rSDIO_RESP1		(*(volatile unsigned long *)AK88_SDIO_REG(0x14))
+#define rSDIO_RESP2		(*(volatile unsigned long *)AK88_SDIO_REG(0x18))
+#define rSDIO_RESP3		(*(volatile unsigned long *)AK88_SDIO_REG(0x1C))
+#define rSDIO_RESP4		(*(volatile unsigned long *)AK88_SDIO_REG(0x20))
+#define rSDIO_DATATIMER		(*(volatile unsigned long *)AK88_SDIO_REG(0x24))
+#define rSDIO_DATALEN		(*(volatile unsigned long *)AK88_SDIO_REG(0x28))
+#define rSDIO_DATACON		(*(volatile unsigned long *)AK88_SDIO_REG(0x2C))
+#define rSDIO_DATACOUNT		(*(volatile unsigned long *)AK88_SDIO_REG(0x30))
+#define rSDIO_STAT		(*(volatile unsigned long *)AK88_SDIO_REG(0x34))
+#define rSDIO_INTEN		(*(volatile unsigned long *)AK88_SDIO_REG(0x38))
+#define rSDIO_DMAMOD		(*(volatile unsigned long *)AK88_SDIO_REG(0x3C))
+#define rSDIO_CPUMOD		(*(volatile unsigned long *)AK88_SDIO_REG(0x40))
+#endif/*_AK88_ADDR_H_*/
diff --git a/arch/arm/mach-ak88/include/mach/ak880x_freq.h b/arch/arm/mach-ak88/include/mach/ak880x_freq.h
new file mode 100644
index 00000000000..52d2e02e56f
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/ak880x_freq.h
@@ -0,0 +1,21 @@
+#ifndef __ARCH_ARM_MACH_AK88_LIB_BASE_H__
+#define __ARCH_ARM_MACH_AK88_LIB_BASE_H__
+
+/*
+ freq,clock,gpio,sharepin
+*/
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+void ak880x_sdelay(int s_time);
+void ak880x_msdelay(int ms_time);
+void ak880x_usdelay(int us_time);
+
+unsigned long ak880x_pll1freq_get(void);
+unsigned long ak880x_cpufreq_get(void);
+unsigned long ak880x_asicfreq_get(void);
+
+unsigned long ak780x_cpufreq_get(void);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/ak880x_gpio.h b/arch/arm/mach-ak88/include/mach/ak880x_gpio.h
new file mode 100644
index 00000000000..05d822cfa12
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/ak880x_gpio.h
@@ -0,0 +1,173 @@
+#ifndef __ARCH_ARM_MACH_AK88_AK88_GPIO_H__
+#define __ARCH_ARM_MACH_AK88_AK88_GPIO_H__
+
+bool gpio_set_dir(int gpiopin /*0~31,32~64,64~95,96~127 */ ,
+		  int set /*0:out,1:in */ );
+bool gpio_set_level(int gpiopin /*0~31,32~64,64~95,96~127 */ , int set);
+bool gpio_get_level(int gpiopin /*0~31,32~64,64~95,96~127 */ );
+
+bool gpio_set_output(int gpiopin /*0~31,32~64,64~95,96~127 */ ,
+		     int level /*output level */ );
+bool gpio_get_input(int gpiopin /*0~31,32~64,64~95,96~127 */ );
+
+typedef enum {
+
+//GPIO_XXX(0)
+
+	AK8802_GPIO_00 = 0,	//00
+	AK8802_GPIO_01,		//01 
+	AK8802_GPIO_02,		//02
+	AK8802_GPIO_03,		//03
+	AK8802_GPIO_04,		//04
+	AK8802_GPIO_05,		//05
+	AK8802_GPIO_06,		//06 
+	AK8802_GPIO_07,		//07
+	AK8802_GPIO_08,		//08
+	AK8802_GPIO_09,		//09
+	AK8802_GPIO_10,		//10
+
+	AK8802_GPIO_RESV11,	//GPIO_11 //11
+	AK8802_GPIO_RESV12,	//GPIO_12 //12
+	AK8802_GPIO_13,		//13
+	AK8802_GPIO_14,		//14
+	AK8802_GPIO_15,		//15
+	AK8802_GPIO_RESV16,	//GPIO_16 //16 
+	AK8802_GPIO_RESV17,	//GPIO_17 //17
+	AK8802_GPIO_RESV18,	//GPIO_18 //18
+	AK8802_GPIO_RESV19,	//GPIO_19 //19
+	AK8802_GPIO_RESV20,	//GPIO_20 //20 
+
+	AK8802_GPIO_RESV21,	//GPIO_21 //21 
+	AK8802_GPIO_RESV22,	//GPIO_22 //22  
+	AK8802_GPIO_RESV23,	//GPIO_23 //23 
+	AK8802_GPIO_24,		//24 
+	AK8802_GPIO_25,		//25 
+	AK8802_GPIO_26,		//26 
+	AK8802_GPIO_27,		//27 
+	AK8802_GPIO_28,		//28 
+	AK8802_GPIO_29,		//29 
+	AK8802_GPIO_30,		//30 
+	AK8802_GPIO_31,		//31 
+
+//GPIO_XXX(1)
+
+	AK8802_GPIO_32,		//00
+	AK8802_GPIO_33,		//01
+	AK8802_GPIO_34,		//02
+	AK8802_GPIO_35,		//03
+	AK8802_GPIO_36,		//04
+	AK8802_GPIO_37,		//05
+	AK8802_GPIO_38,		//06
+	AK8802_GPIO_39,		//07
+	AK8802_GPIO_40,		//08
+
+	AK8802_GPIO_41,		//09
+	AK8802_GPIO_42,		//10
+	AK8802_GPIO_43,		//11 
+	AK8802_GPIO_44,		//12 
+	AK8802_GPIO_45,		//13
+	AK8802_GPIO_46,		//14
+	AK8802_GPIO_47,		//15
+	AK8802_GPIO_48,		//16
+	AK8802_GPIO_49,		//17
+	AK8802_GPIO_50,		//18
+
+	AK8802_GPIO_51,		//19
+	AK8802_GPIO_52,		//20
+	AK8802_GPIO_53,		//21
+	AK8802_GPIO_54,		//22
+	AK8802_GPIO_55,		//23
+	AK8802_GPIO_56,		//24
+	AK8802_GPIO_57,		//25
+	AK8802_GPIO_58,		//26
+	AK8802_GPIO_RESV59,	//27 
+	AK8802_GPIO_RESV60,	//28
+	AK8802_GPIO_61,		//29
+	AK8802_GPIO_62,		//30
+	AK8802_GPIO_63,		//31
+
+//GPIO_XXX(2)
+
+	AK8802_GPIO_64,		//00
+	AK8802_GPIO_65,		//01
+	AK8802_GPIO_66,		//02
+	AK8802_GPIO_67,		//03
+	AK8802_GPIO_68,		//04
+	AK8802_GPIO_69,		//05
+	AK8802_GPIO_70,		//06
+
+	AK8802_GPIO_71,		//07
+	AK8802_GPIO_RESV72,	//GPIO_72 //08
+	AK8802_GPIO_RESV73,	//GPIO_73 //09
+	AK8802_GPIO_RESV74,	//GPIO_74 //10
+	AK8802_GPIO_RESV75,	//GPIO_75 //11
+	AK8802_GPIO_76,		//12
+	AK8802_GPIO_77,		//13
+	AK8802_GPIO_78,		//14
+	AK8802_GPIO_79,		//15
+	AK8802_GPIO_RESV80,	//GPIO_80 //16 
+
+	AK8802_GPIO_RESV81,	//GPIO_81 //17
+	AK8802_GPIO_RESV82,	//GPIO_82 //18 
+	AK8802_GPIO_RESV83,	//GPIO_83 //19
+	AK8802_GPIO_DGPIO19,	//20  //84
+	AK8802_GPIO_RESV85,	//DGPIO_20 //21
+	AK8802_GPIO_RESV86,	//DGPIO_21 //22
+	AK8802_GPIO_RESV87,	//DGPIO_22 //23
+	AK8802_GPIO_RESV88,	//DGPIO_23 //24
+	AK8802_GPIO_RESV89,	//DGPIO_24 //25
+	AK8802_GPIO_RESV90,	//DGPIO_25 //26
+
+	AK8802_GPIO_RESV91,	//DGPIO_26 //27
+	AK8802_GPIO_RESV92,	//DGPIO_27 //28
+	AK8802_GPIO_DGPIO28,	//29
+	AK8802_GPIO_RESV94,	//DGPIO_29 //30
+	AK8802_GPIO_RESV95,	//DGPIO_30 //31
+
+//GPIO_XXX(3)
+
+	AK8802_GPIO_RESV96,	//DGPIO_31 //00  //96   
+	AK8802_GPIO_RESV97,	//DGPIO_32 //01
+	AK8802_GPIO_RESV98,	//DGPIO_33 //02
+	AK8802_GPIO_RESV99,	//DGPIO_34 //03
+	AK8802_GPIO_RESV100,	//DGPIO_35 //04 
+
+	AK8802_GPIO_RESV101,	//DGPIO_36 //05  //05+3*32=101
+	AK8802_GPIO_DGPIO0,	//06             //06+3*32=102
+	AK8802_GPIO_DGPIO1,	//07
+	AK8802_GPIO_DGPIO2,	//08
+	AK8802_GPIO_DGPIO3,	//09
+	AK8802_GPIO_RESV106,	//DGPIO_04 //10
+	AK8802_GPIO_RESV107,	//DGPIO_05 //11
+	AK8802_GPIO_RESV108,	//12
+	AK8802_GPIO_RESV109,	//DGPIO_07 //13
+	AK8802_GPIO_RESV110,	//DGPIO_08 //14
+
+	AK8802_GPIO_RESV111,	//DGPIO_09 //15
+	AK8802_GPIO_RESV112,	//DGPIO_10 //16
+	AK8802_GPIO_RESV113,	//DGPIO_11 //17 
+	AK8802_GPIO_RESV114,	//DGPIO_12 //18
+	AK8802_GPIO_RESV115,	//DGPIO_13 //19
+	AK8802_GPIO_RESV116,	//DGPIO_14 //20    //20+3*32=116
+	AK8802_GPIO_RESV117,	//21
+	AK8802_GPIO_RESV118,	//22
+	AK8802_GPIO_RESV119,	//23
+	AK8802_GPIO_RESV120,	//24
+
+	AK8802_GPIO_RESV121,	//25 
+
+	//AK8802_GPIO_RESV122 ,  //26 
+	//AK8802_GPIO_RESV123 ,  //27 
+	AK88_GPIO_DGPIO25,	//26
+	AK88_GPIO_DGPIO26,	//27
+
+	AK8802_GPIO_RESV124,	//28 
+	AK8802_GPIO_RESV125,	//29 
+	AK8802_GPIO_RESV126,	//30 
+	AK8802_GPIO_RESV127,	//31 
+
+	AK88_GPIO_MAX_PIN_NUM,
+
+} AK8802_GPIO_PIN;
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/clock.h b/arch/arm/mach-ak88/include/mach/clock.h
new file mode 100644
index 00000000000..dcdac8668b6
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/clock.h
@@ -0,0 +1,83 @@
+/* 
+ * linux/include/asm-arm/arch-ak880x/clock.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _ANYKA_CLK_H_
+#define _ANYKA_CLK_H_
+
+/* reset & clock control */
+#define AK_HWMMD_CODEC		0
+#define AK_CAMIF		1
+#define AK_SPI_MMC_UART1	2
+#define AK_DISPLAY_CTRL		3
+#define AK_AUDIO_PROCSESSOR	4
+#define AK_USBOTG_CTRL		5
+#define AK_H264_DECODER		6
+#define AK_USBFS_HOST_CTRL	7
+#define AK_SDIO_UART2_UART3	8
+#define AK_CLK_RESERVED0	9
+#define AK_MEMORY_CTRL		10
+#define AK_MOTION_ESTIMATION	11
+#define AK_2DGRAPHICS_ACC	12
+#define AK_NANDFLASH_CTRL	13
+#define AK_CLK_RESERVED1	14
+#define AK_L2CTRL_UART0		15
+
+union ak880x_clk_div1_reg {
+	struct {
+		unsigned long m:6;	/* 5:0  */
+		unsigned long asic_clk:3;	/* 8:6  */
+		unsigned long ap_clk:3;	/* 11:9 */
+		unsigned long pll1_en:1;	/* 12   */
+		unsigned long st:1;	/* 13   */
+		unsigned long asic_ap_en:1;	/* 14   */
+		unsigned long cpu_clk:1;	/* 15   */
+		unsigned long rtc_wakeup:1;	/* 16   */
+		unsigned long n:4;	/* 20:17 */
+		unsigned long reserved:11;	/* 31:21 */
+	} clk_div;
+	unsigned long regval;
+};
+
+struct clk {
+	struct list_head list;
+	struct module *owner;
+	struct clk *parent;
+	const char *name;
+	int id;
+	int usage;
+	unsigned long rate;
+	unsigned long ctrlbit;
+
+	int (*enable) (struct clk *, int enable);
+	int (*set_rate) (struct clk * c, unsigned long rate);
+	unsigned long (*get_rate) (struct clk * c);
+	int (*set_parent) (struct clk * c, struct clk * parent);
+};
+
+/* core clock support */
+extern struct clk clk_xtal_12M;
+extern struct clk clk_xtal_27M;
+extern struct clk clk_xtal_32K;
+extern struct clk clk_pll1;
+extern struct clk clk_pll2;
+extern struct clk clk_asic;
+extern struct clk clk_cpu;
+
+/* other clocks which may be registered by board support */
+extern struct clk ap_clk;
+extern struct clk adc1_clk;
+extern struct clk adc2_clk;
+extern struct clk dac_clk;
+extern struct clk camif_clk;
+extern struct clk lcd_clk;
+extern struct clk spi_clk;
+extern struct clk mci_clk;
+extern struct clk udc_clk;
+extern struct clk uart4_clk;
+ 
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/debug-macro.S b/arch/arm/mach-ak88/include/mach/debug-macro.S
new file mode 100644
index 00000000000..9036020b914
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/debug-macro.S
@@ -0,0 +1,108 @@
+/* linux/include/asm-arm/arch-ak880x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/map.h>
+
+	.macro	addruart,	rx
+	mrc	p15, 0, \rx, c1, c0
+
+	@ init uart for output, no need init everytime
+	@ share-pin settting
+	@tst	\rx, #1
+	@ldreq	r11, =(AK88_PA_SYSCTRL+0x78)
+	@ldrne	r11, =(AK88_VA_SYSCTRL+0x78)
+	@ldr	r12, [r11]
+	@orr	r12, r12, #(0x1<<9)
+	@str	r12, [r11]
+
+	@ uart buf setting
+	@tst     \rx, #1
+	@ldreq   r11, =(AK88_PA_L2CTRL+0x40)    @ mmu disabled
+	@ldrne   r11, =(AK88_VA_L2CTRL+0x40)    @ mmu enabled
+	@ldr     r12, [r11]
+	@orr     r12, r12, #(0x1<<11)
+	@str     r12, [r11]
+	
+	@uart config (ie: baudrate)
+	@tst     \rx, #1
+	@ldreq   r11, =(AK88_PA_UART+0x00)     @0x20026000
+	@ldrne   r11, =(AK88_VA_UART+0x00)
+	@ldr     r12, [r11]
+	@orr     r12, r12, #(0x1<<21)
+	@orr     r12, r12, #(0x3<<28)
+	@str     r12, [r11]
+	
+	@ uart tx threshold setting
+	@tst     \rx, #1
+	@ldreq   r11, =(AK88_PA_UART+0x0C)     @0x2002600C
+	@ldrne   r11, =(AK88_VA_UART+0x0C)
+	@mov     r12, #0x0
+	@str     r12, [r11]
+	.endm
+
+	.macro	senduart,	rb,	rx
+	tst	\rx, #1
+	ldreq   r11, =AK88_PA_L2CTRL		@0x2002C08C
+	ldrne	r11, =(AK88_VA_L2CTRL+0x8C)
+	ldr     r12, [r11]
+	orr     r12, r12, #0x10000
+	str     r12, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK88_PA_L2MEM+0x1000)	@0x48001000
+	ldrne	r11, =(AK88_VA_L2MEM+0x1000)
+	@ldr    r12, ='z'
+	str     \rb, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK88_PA_L2MEM+0x103C)	@0x4800103C
+	ldrne	r11, =(AK88_VA_L2MEM+0x103C)
+	mov     r12, #0x0
+	str     r12, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK88_PA_UART+0x00)	@0x20026000
+	ldrne	r11, =(AK88_VA_UART+0x00)
+	ldr     r12, [r11]
+	orr     r12, r12, #(0x1<<28)
+	str     r12, [r11]
+	
+	tst	\rx, #1
+	ldreq	r11, =(AK88_PA_UART+0x04)	@0x20026004
+	ldrne	r11, =(AK88_VA_UART+0x04)
+	ldr     r12, [r11]
+	orr     r12, r12, #(0x1<<4)
+	orr     r12, r12, #(0x1<<16)
+	str     r12, [r11]
+
+ak_loop:
+	tst	\rx, #1
+	ldreq	r11, =(AK88_PA_UART+0x04)	@0x20026004
+	ldrne	r11, =(AK88_VA_UART+0x04)
+	ldr     r12, [r11]
+	and     r12, r12, #0x80000
+	cmp     r12, #0
+	beq     ak_loop			@ FIXME
+
+	ldr     r11, =0x800
+ak_delay:
+	subs    r11, r11, #1
+	cmp     r11, #0
+	bne     ak_delay
+
+	.endm
+	
+	.macro	waituart,	rd,	rx
+	.endm
+	
+	.macro	busyuart,	rd,	rx
+	.endm
diff --git a/arch/arm/mach-ak88/include/mach/devices_ak880x.h b/arch/arm/mach-ak88/include/mach/devices_ak880x.h
new file mode 100644
index 00000000000..ebba0c70eff
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/devices_ak880x.h
@@ -0,0 +1,30 @@
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+#ifndef __ARCH_ARM_MACH_AK88_DEVICE_H__
+#define __ARCH_ARM_MACH_AK88_DEVICE_H__
+
+//include <linux/device.h>
+//include <linux/mod_devicetable.h>
+//include <linux/platform_device.h>
+
+
+struct ak88_mci_platform_data {
+	int gpio_cd;		/* card detect pin */
+	int gpio_wp;		/* write protect pin */
+};
+
+#define AK88_MAX_UART   4
+
+extern struct platform_device *ak880x_default_console_device;
+
+void __init ak880x_register_uart(unsigned char id, unsigned char portnr);
+
+void __init ak880x_set_serial_console(unsigned char portnr);
+
+void __init ak880x_add_device_serial(void);
+
+void __init ak880x_add_device_lcdc(struct anyka_lcdfb_info *data);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/dma.h b/arch/arm/mach-ak88/include/mach/dma.h
new file mode 100644
index 00000000000..e5fe7b399d9
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/dma.h
@@ -0,0 +1,40 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __AK88_DMA_H
+#define __AK88_DMA_H __FILE__
+
+//#include <linux/sysdev.h>
+#include <mach/hardware.h>
+
+#define AK88_DMA_CHANNELS  11
+
+/*
+ * This is the maximum DMA address(physical address) that can be DMAd to.
+ *
+ */
+//#define MAX_DMA_ADDRESS               0x40000000
+//#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
+
+struct ak880x_dma_channel {
+	const char *name;
+	void (*irq_handler) (int, void *);
+	void *data;
+	unsigned char dma_id;
+	unsigned char irq_bit;
+};
+
+/*
+ * 0: camera: 2
+ * 1: display: 1
+ * 2: audio processor:5
+ * 4: motion Estimation /H.264 decoder: 3&6
+ * 5: image processor/ MPEG4/H.263 codec: 4
+ * 6: l2:10
+ * 7: 2d graphics accelerator: 20
+ */
+
+#endif				/* __AK88_DMA_H */
diff --git a/arch/arm/mach-ak88/include/mach/entry-macro.S b/arch/arm/mach-ak88/include/mach/entry-macro.S
new file mode 100644
index 00000000000..43c5c824236
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/entry-macro.S
@@ -0,0 +1,172 @@
+/*
+ * include/asm-arm/arch-s3c2410/entry-macro.S
+ *
+ * Low-level IRQ helper macros for S3C2410-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+/* We have a problem that the INTOFFSET register does not always
+ * show one interrupt. Occasionally we get two interrupts through
+ * the prioritiser, and this causes the INTOFFSET register to show
+ * what looks like the logical-or of the two interrupt numbers.
+ *
+ * Thanks to Klaus, Shannon, et al for helping to debug this problem
+*/
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#define	AK88_IRQ_INTMASK		(AK88_VA_SYSCTRL + 0x34)
+#define	AK88_FIQ_INTMASK		(AK88_VA_SYSCTRL + 0x38)
+#define	AK88_INT_STATUS		(AK88_VA_SYSCTRL + 0xCC)
+
+	.macro  get_irqnr_preamble, base, tmp
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		ldr	\base, =AK88_INT_STATUS
+		ldr	\irqstat, [\base]		@ get interrupts status
+		teq	\irqstat, #0x0
+		beq	1002f
+		
+		ldr	\base, =AK88_IRQ_INTMASK	@ get interrupts mask
+		ldr	\base, [\base]
+		and	\irqstat, \irqstat, \base
+
+		tst	\irqstat, #(1<<IRQ_DISPLAY_CTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_DISPLAY_CTRL)
+		movne	\irqnr, #IRQ_DISPLAY_CTRL
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_CAMERA_IF)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_CAMERA_IF)
+		movne	\irqnr, #IRQ_CAMERA_IF
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_MOTIONESTIMATION)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MOTIONESTIMATION)
+		movne	\irqnr, #IRQ_MOTIONESTIMATION
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_IMG_MPEG4)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_IMG_MPEG4)
+		movne	\irqnr, #IRQ_IMG_MPEG4
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_AUDIO)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_AUDIO)
+		movne	\irqnr, #IRQ_AUDIO
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_H264_DECODER)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_H264_DECODER)
+		movne	\irqnr, #IRQ_H264_DECODER
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_DAC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_DAC)
+		movne	\irqnr, #IRQ_DAC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_L2MEM)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_L2MEM)
+		movne	\irqnr, #IRQ_L2MEM
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_NF_ECC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_NF_ECC)
+		movne	\irqnr, #IRQ_NF_ECC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_NF_CTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_NF_CTRL)
+		movne	\irqnr, #IRQ_NF_CTRL
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART3)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART3)
+		movne	\irqnr, #IRQ_UART3
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART2)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART2)
+		movne	\irqnr, #IRQ_UART2
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART1)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART1)
+		movne	\irqnr, #IRQ_UART1
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART0)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART0)
+		movne	\irqnr, #IRQ_UART0
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SPI2)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SPI2)
+		movne	\irqnr, #IRQ_SPI2
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SPI1)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SPI1)
+		movne	\irqnr, #IRQ_SPI1
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_2D_ACC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_2D_ACC)
+		movne	\irqnr, #IRQ_2D_ACC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SDIO)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SDIO)
+		movne	\irqnr, #IRQ_SDIO
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_MMC_SD)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MMC_SD)
+		movne	\irqnr, #IRQ_MMC_SD
+		bne	1001f
+		
+		tst	\irqstat, #(1<<IRQ_USBHOST_MCU)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBHOST_MCU)
+		movne	\irqnr, #IRQ_USBHOST_MCU
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBHOST_DMA)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBHOST_DMA)
+		movne	\irqnr, #IRQ_USBHOST_DMA
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBOTG_MCU)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBOTG_MCU)
+		movne	\irqnr, #IRQ_USBOTG_MCU
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBOTG_DMA)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBOTG_DMA)
+		movne	\irqnr, #IRQ_USBOTG_DMA
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_SYSCTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SYSCTRL)
+		movne	\irqnr, #IRQ_SYSCTRL
+		bne	1001f
+
+	1001:
+		@ got irqnr
+	1002:
+		@ exit here
+	.endm
+	
+	/* currently don't need an disable_fiq macro */
+	.macro	disable_fiq
+	.endm
+
diff --git a/arch/arm/mach-ak88/include/mach/gpio.h b/arch/arm/mach-ak88/include/mach/gpio.h
new file mode 100644
index 00000000000..b47f015c74d
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/gpio.h
@@ -0,0 +1,268 @@
+/*************************************************************************
+*   Filename: include/asm-arm/arch-ak880x/gpio.h
+*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+**************************************************************************/
+
+#ifndef _AK88_GPIO_H_
+#define _AK88_GPIO_H_ __FILE__
+
+#include <mach/hardware.h>
+
+#include "ak880x_addr.h"
+#include "io-ctl.h"
+
+#define AK88_SHARE_GPIO		0
+#define AK88_SHARE_FUNC		1
+#define AK88_GPIO_OUT_0		0
+#define AK88_GPIO_IN_0		1
+#define AK88_GPIO_PUPD_ENABLE		0
+#define AK88_GPIO_PUPD_DISABLE	1
+#define AK88_GPIO_INTDISABLE		0
+#define AK88_GPIO_INTENABLE 		1
+
+#define AK88_IO_CON1                  AK88_SYSCTRL_REG(0xD4)
+#define AK88_IO_CON2                  AK88_SYSCTRL_REG(0xD8)
+
+#define AK88_SHAREPIN_CON1		AK88_SYSCTRL_REG(0x78)
+#define AK88_SHAREPIN_CON2		AK88_SYSCTRL_REG(0x74)
+
+#define AK88_GPIO_DIR1                AK88_SYSCTRL_REG(0x7C)
+#define AK88_GPIO_DIR2                AK88_SYSCTRL_REG(0x84)
+#define AK88_GPIO_DIR3                AK88_SYSCTRL_REG(0x8C)
+#define AK88_GPIO_DIR4                AK88_SYSCTRL_REG(0x94)
+
+#define AK88_GPIO_OUT1                AK88_SYSCTRL_REG(0x80)
+#define AK88_GPIO_OUT2                AK88_SYSCTRL_REG(0x88)
+#define AK88_GPIO_OUT3                AK88_SYSCTRL_REG(0x90)
+#define AK88_GPIO_OUT4                AK88_SYSCTRL_REG(0x98)
+
+#define AK88_GPIO_IN1                 AK88_SYSCTRL_REG(0xBC)
+#define AK88_GPIO_IN2                 AK88_SYSCTRL_REG(0xC0)
+#define AK88_GPIO_IN3                 AK88_SYSCTRL_REG(0xC4)
+#define AK88_GPIO_IN4                 AK88_SYSCTRL_REG(0xC8)
+
+#define AK88_PPU_PPD1                 AK88_SYSCTRL_REG(0x9C)
+#define AK88_PPU_PPD2                 AK88_SYSCTRL_REG(0xA0)
+#define AK88_PPU_PPD3                 AK88_SYSCTRL_REG(0xA4)
+#define AK88_PPU_PPD4                 AK88_SYSCTRL_REG(0xA8)
+
+#define AK88_GPIO_INTEN1              AK88_SYSCTRL_REG(0xE0)
+#define AK88_GPIO_INTEN2              AK88_SYSCTRL_REG(0xE4)
+#define AK88_GPIO_INTEN3              AK88_SYSCTRL_REG(0xE8)
+#define AK88_GPIO_INTEN4              AK88_SYSCTRL_REG(0xEC)
+
+#define AK88_GPIO_INTPOL1             AK88_SYSCTRL_REG(0xF0)
+#define AK88_GPIO_INTPOL2             AK88_SYSCTRL_REG(0xF4)
+#define AK88_GPIO_INTPOL3             AK88_SYSCTRL_REG(0xF8)
+#define AK88_GPIO_INTPOL4             AK88_SYSCTRL_REG(0xFC)
+
+#define AK88_GPIO_DIR_BASE(pin)	( ((pin)>>5)*8 + AK88_GPIO_DIR1 )
+#define AK88_GPIO_OUT_BASE(pin)	( ((pin)>>5)*8 + AK88_GPIO_OUT1 )
+#define AK88_GPIO_IN_BASE(pin)	( ((pin)>>5)*4 + AK88_GPIO_IN1 )
+#define AK88_PPU_PPD_BASE(pin)	( ((pin)>>5)*4 + AK88_PPU_PPD1 )
+#define AK88_GPIO_INTEN_BASE(pin)	( ((pin)>>5)*4 + AK88_GPIO_INTEN1 )
+#define AK88_GPIO_INTPOL_BASE(pin)	( ((pin)>>5)*4 + AK88_GPIO_INTPOL1 )
+
+/*
+ * Share-pin con1 bits
+ * x:0 the pins are used as gpio(default except JTAG).
+ * x:1	the pins are used as function pins.
+ */
+#define AK88_GPIO_PCM_JTAG(x) 	ak880x_sharepin_cfg1(x,0)
+#define AK88_GPIO_JTAG_RTCK(x)	ak880x_sharepin_cfg1(x,1)
+#define AK88_GPIO_IIS(x)		ak880x_sharepin_cfg1(x,2)
+#define AK88_GPIO_OTG_BUS(x)		ak880x_sharepin_cfg1(x,3)
+#define AK88_GPIO_PWM1(x)		ak880x_sharepin_cfg1(x,4)
+#define AK88_GPIO_PWM2(x)		ak880x_sharepin_cfg1(x,5)
+#define AK88_GPIO_PWM3(x)		ak880x_sharepin_cfg1(x,6)
+#define AK88_GPIO_PWM4(x)		ak880x_sharepin_cfg1(x,7)
+#define AK88_GPIO_IIS_MCLK(x)		ak880x_sharepin_cfg1(x,8)
+#define AK88_GPIO_UART0(x)		ak880x_sharepin_cfg1(x,9)
+#define AK88_GPIO_UART1(x)		ak880x_sharepin_cfg1(x,10)
+#define AK88_GPIO_UART1_FLOW(x)	ak880x_sharepin_cfg1(x,11)
+#define AK88_GPIO_UART2(x)		ak880x_sharepin_cfg1(x,12)
+#define AK88_GPIO_UART2_FLOW(x)	ak880x_sharepin_cfg1(x,13)
+#define AK88_GPIO_UART3(x)		ak880x_sharepin_cfg1(x,14)
+#define AK88_GPIO_UART3_FLOW(x)	ak880x_sharepin_cfg1(x,15)
+#define AK88_GPIO_NFC_DATA0(x)	ak880x_sharepin_cfg1(x,16)
+#define AK88_GPIO_NFC_DATA1_3(x)	ak880x_sharepin_cfg1(x,17)
+#define AK88_GPIO_NFC_DATA4_7(x)	ak880x_sharepin_cfg1(x,18)
+#define AK88_GPIO_NFC_CE(x)		ak880x_sharepin_cfg1(x,19)
+#define AK88_GPIO_NFC_READY(x)	ak880x_sharepin_cfg1(x,22)
+#define AK88_GPIO_CAMARA(x)		ak880x_sharepin_cfg1(x,24)
+#define AK88_GPIO_LCD_DATA8(x)	ak880x_sharepin_cfg1(x,26)
+#define AK88_GPIO_LCD_DATA9_15(x)	ak880x_sharepin_cfg1(x,25)
+#define AK88_GPIO_LCD_DATA16_17(x)	ak880x_sharepin_cfg1(x,27)
+#define AK88_GPIO_MPU_RST(x)		ak880x_sharepin_cfg1(x,28)
+#define AK88_GPIO_MDAT2(x)		ak880x_sharepin_cfg1(x,29)
+#define AK88_GPIO_SPI1(x)		ak880x_sharepin_cfg1(x,30)
+#define AK88_GPIO_SPI2(x)		ak880x_sharepin_cfg1(x,31)
+
+/* sharepin con2 */
+#define AK88_MCI_ENABLE()		ak880x_sharepin_cfg2(2,5)
+#define AK88_MCI_DISABLE()		ak880x_sharepin_cfg2(0,5)
+
+#define AK88_NFC_ENABLE()		ak880x_sharepin_cfg2(1,3)
+#define AK88_SD_ENABLE()		ak880x_sharepin_cfg2(2,3)
+#define AK88_NFC_DISABLE()		ak880x_sharepin_cfg2(0,3)
+#define AK88_SD_DISABLE()		ak880x_sharepin_cfg2(0,3)
+
+#define AK88_UART3_ENABLE()		ak880x_sharepin_cfg2(1,1)
+#define AK88_SDIO_ENABLE()		ak880x_sharepin_cfg2(2,1)
+#define AK88_UART3_DISABLE()		ak880x_sharepin_cfg2(0,1)
+#define AK88_SDIO_DISABLE()		ak880x_sharepin_cfg2(0,1)
+
+#define AK88_JTAG_ENABLE()		ak880x_sharepin_cfg2(1,0)
+#define AK88_PCM_ENABLE()		ak880x_sharepin_cfg2(0,0)
+
+/* gpio offsets */
+#define AK88_GPIO_GROUP1		(32*0)
+#define AK88_GPIO_GROUP2		(32*1)
+#define AK88_GPIO_GROUP3		(32*2)
+#define AK88_GPIO_GROUP4		(32*3)
+
+#define AK88_GPIO_GROUP1_NO(offset)	( AK88_GPIO_GROUP1 + (offset))
+#define AK88_GPIO_GROUP2_NO(offset)	( AK88_GPIO_GROUP2 + (offset))
+#define AK88_GPIO_GROUP3_NO(offset)	( AK88_GPIO_GROUP3 + (offset))
+#define AK88_GPIO_GROUP4_NO(offset)	( AK88_GPIO_GROUP4 + (offset))
+
+#define AK88_GPIO_0		AK88_GPIO_GROUP1_NO(0)
+#define AK88_GPIO_1		AK88_GPIO_GROUP1_NO(1)
+#define AK88_GPIO_2		AK88_GPIO_GROUP1_NO(2)
+#define AK88_GPIO_3		AK88_GPIO_GROUP1_NO(3)
+#define AK88_GPIO_4		AK88_GPIO_GROUP1_NO(4)
+#define AK88_GPIO_5		AK88_GPIO_GROUP1_NO(5)
+#define AK88_GPIO_6		AK88_GPIO_GROUP1_NO(6)
+#define AK88_GPIO_7		AK88_GPIO_GROUP1_NO(7)
+#define AK88_GPIO_8		AK88_GPIO_GROUP1_NO(8)
+#define AK88_GPIO_9		AK88_GPIO_GROUP1_NO(9)
+#define AK88_GPIO_10		AK88_GPIO_GROUP1_NO(10)
+#define AK88_GPIO_11		AK88_GPIO_GROUP1_NO(11)
+#define AK88_GPIO_12		AK88_GPIO_GROUP1_NO(12)
+#define AK88_GPIO_13		AK88_GPIO_GROUP1_NO(13)
+#define AK88_GPIO_14		AK88_GPIO_GROUP1_NO(14)
+#define AK88_GPIO_15		AK88_GPIO_GROUP1_NO(15)
+#define AK88_GPIO_16		AK88_GPIO_GROUP1_NO(16)
+#define AK88_GPIO_17		AK88_GPIO_GROUP1_NO(17)
+#define AK88_GPIO_18		AK88_GPIO_GROUP1_NO(18)
+#define AK88_GPIO_19		AK88_GPIO_GROUP1_NO(19)
+#define AK88_GPIO_20		AK88_GPIO_GROUP1_NO(20)
+#define AK88_GPIO_21		AK88_GPIO_GROUP1_NO(21)
+#define AK88_GPIO_22		AK88_GPIO_GROUP1_NO(22)
+#define AK88_GPIO_23		AK88_GPIO_GROUP1_NO(23)
+#define AK88_GPIO_24		AK88_GPIO_GROUP1_NO(24)
+#define AK88_GPIO_25		AK88_GPIO_GROUP1_NO(25)
+#define AK88_GPIO_26		AK88_GPIO_GROUP1_NO(26)
+#define AK88_GPIO_27		AK88_GPIO_GROUP1_NO(27)
+#define AK88_GPIO_28		AK88_GPIO_GROUP1_NO(28)
+#define AK88_GPIO_29		AK88_GPIO_GROUP1_NO(29)
+#define AK88_GPIO_30		AK88_GPIO_GROUP1_NO(30)
+#define AK88_GPIO_31		AK88_GPIO_GROUP1_NO(31)
+
+#define AK88_GPIO_32		AK88_GPIO_GROUP2_NO(0)
+#define AK88_GPIO_33		AK88_GPIO_GROUP2_NO(1)
+#define AK88_GPIO_34		AK88_GPIO_GROUP2_NO(2)
+#define AK88_GPIO_35		AK88_GPIO_GROUP2_NO(3)
+#define AK88_GPIO_36		AK88_GPIO_GROUP2_NO(4)
+#define AK88_GPIO_37		AK88_GPIO_GROUP2_NO(5)
+#define AK88_GPIO_38		AK88_GPIO_GROUP2_NO(6)
+#define AK88_GPIO_39		AK88_GPIO_GROUP2_NO(7)
+#define AK88_GPIO_40		AK88_GPIO_GROUP2_NO(8)
+#define AK88_GPIO_41		AK88_GPIO_GROUP2_NO(9)
+#define AK88_GPIO_42		AK88_GPIO_GROUP2_NO(10)
+#define AK88_GPIO_43		AK88_GPIO_GROUP2_NO(11)
+#define AK88_GPIO_44		AK88_GPIO_GROUP2_NO(12)
+#define AK88_GPIO_45		AK88_GPIO_GROUP2_NO(13)
+#define AK88_GPIO_46		AK88_GPIO_GROUP2_NO(14)
+#define AK88_GPIO_47		AK88_GPIO_GROUP2_NO(15)
+#define AK88_GPIO_48		AK88_GPIO_GROUP2_NO(16)
+#define AK88_GPIO_49		AK88_GPIO_GROUP2_NO(17)
+#define AK88_GPIO_50		AK88_GPIO_GROUP2_NO(18)
+#define AK88_GPIO_51		AK88_GPIO_GROUP2_NO(19)
+#define AK88_GPIO_52		AK88_GPIO_GROUP2_NO(20)
+#define AK88_GPIO_53		AK88_GPIO_GROUP2_NO(21)
+#define AK88_GPIO_54		AK88_GPIO_GROUP2_NO(22)
+#define AK88_GPIO_55		AK88_GPIO_GROUP2_NO(23)
+#define AK88_GPIO_56		AK88_GPIO_GROUP2_NO(24)
+#define AK88_GPIO_57		AK88_GPIO_GROUP2_NO(25)
+#define AK88_GPIO_58		AK88_GPIO_GROUP2_NO(26)
+#define AK88_GPIO_59_RESERVED AK88_GPIO_GROUP2_NO(27)	/* Reserved */
+#define AK88_GPIO_60_RESERVED	AK88_GPIO_GROUP2_NO(28)	/* Reserved */
+#define AK88_GPIO_61		AK88_GPIO_GROUP2_NO(29)
+#define AK88_GPIO_62		AK88_GPIO_GROUP2_NO(30)
+#define AK88_GPIO_63		AK88_GPIO_GROUP2_NO(31)
+
+#define AK88_GPIO_64		AK88_GPIO_GROUP3_NO(0)
+#define AK88_GPIO_65		AK88_GPIO_GROUP3_NO(1)
+#define AK88_GPIO_66		AK88_GPIO_GROUP3_NO(2)
+#define AK88_GPIO_67		AK88_GPIO_GROUP3_NO(3)
+#define AK88_GPIO_68		AK88_GPIO_GROUP3_NO(4)
+#define AK88_GPIO_69		AK88_GPIO_GROUP3_NO(5)
+#define AK88_GPIO_70		AK88_GPIO_GROUP3_NO(6)
+#define AK88_GPIO_71		AK88_GPIO_GROUP3_NO(7)
+#define AK88_GPIO_72		AK88_GPIO_GROUP3_NO(8)
+#define AK88_GPIO_73		AK88_GPIO_GROUP3_NO(9)
+#define AK88_GPIO_74		AK88_GPIO_GROUP3_NO(10)
+#define AK88_GPIO_75		AK88_GPIO_GROUP3_NO(11)
+#define AK88_GPIO_76		AK88_GPIO_GROUP3_NO(12)
+#define AK88_GPIO_77		AK88_GPIO_GROUP3_NO(13)
+#define AK88_GPIO_78		AK88_GPIO_GROUP3_NO(14)
+#define AK88_GPIO_79		AK88_GPIO_GROUP3_NO(15)
+#define AK88_GPIO_80		AK88_GPIO_GROUP3_NO(16)
+#define AK88_GPIO_81		AK88_GPIO_GROUP3_NO(17)
+#define AK88_GPIO_82		AK88_GPIO_GROUP3_NO(18)
+#define AK88_GPIO_83		AK88_GPIO_GROUP3_NO(19)
+#define AK88_DGPIO_19		AK88_GPIO_GROUP3_NO(20)
+#define AK88_DGPIO_20		AK88_GPIO_GROUP3_NO(21)
+#define AK88_DGPIO_21		AK88_GPIO_GROUP3_NO(22)
+#define AK88_DGPIO_22		AK88_GPIO_GROUP3_NO(23)
+#define AK88_DGPIO_23		AK88_GPIO_GROUP3_NO(24)
+#define AK88_DGPIO_24		AK88_GPIO_GROUP3_NO(25)
+#define AK88_DGPIO_25		AK88_GPIO_GROUP3_NO(26)
+#define AK88_DGPIO_26		AK88_GPIO_GROUP3_NO(27)
+#define AK88_DGPIO_27		AK88_GPIO_GROUP3_NO(28)
+#define AK88_DGPIO_28		AK88_GPIO_GROUP3_NO(29)
+#define AK88_DGPIO_29		AK88_GPIO_GROUP3_NO(30)
+#define AK88_DGPIO_30		AK88_GPIO_GROUP3_NO(31)
+
+#define AK88_DGPIO_31		AK88_GPIO_GROUP4_NO(0)
+#define AK88_DGPIO_32		AK88_GPIO_GROUP4_NO(1)
+#define AK88_DGPIO_33		AK88_GPIO_GROUP4_NO(2)
+#define AK88_DGPIO_34		AK88_GPIO_GROUP4_NO(3)
+#define AK88_DGPIO_35		AK88_GPIO_GROUP4_NO(4)
+#define AK88_DGPIO_36		AK88_GPIO_GROUP4_NO(5)
+#define AK88_DGPIO_0		AK88_GPIO_GROUP4_NO(6)
+#define AK88_DGPIO_1		AK88_GPIO_GROUP4_NO(7)
+#define AK88_DGPIO_2		AK88_GPIO_GROUP4_NO(8)
+#define AK88_DGPIO_3		AK88_GPIO_GROUP4_NO(9)
+#define AK88_DGPIO_4		AK88_GPIO_GROUP4_NO(10)
+#define AK88_DGPIO_5		AK88_GPIO_GROUP4_NO(11)
+#define AK88_DGPIO_6_RESERVED	AK88_GPIO_GROUP4_NO(12)	/* Reserved */
+#define AK88_DGPIO_7		AK88_GPIO_GROUP4_NO(13)
+#define AK88_DGPIO_8		AK88_GPIO_GROUP4_NO(14)
+#define AK88_DGPIO_9		AK88_GPIO_GROUP4_NO(15)
+#define AK88_DGPIO_10		AK88_GPIO_GROUP4_NO(16)
+#define AK88_DGPIO_11		AK88_GPIO_GROUP4_NO(17)
+#define AK88_DGPIO_12		AK88_GPIO_GROUP4_NO(18)
+#define AK88_DGPIO_13		AK88_GPIO_GROUP4_NO(19)
+#define AK88_DGPIO_14		AK88_GPIO_GROUP4_NO(20)
+
+void ak880x_sharepin_cfg1(unsigned char to, unsigned char offset);
+void ak880x_sharepin_cfg2(unsigned char to, unsigned char offset);
+void ak880x_gpio_cfgpin(unsigned int pin, unsigned int function);
+unsigned int ak880x_gpio_getcfg(unsigned int pin);
+void ak880x_gpio_setpin(unsigned int pin, unsigned int to);
+unsigned int ak880x_gpio_getpin(unsigned int pin);
+void ak880x_gpio_pullup(unsigned int pin, unsigned int to);
+void ak880x_gpio_inten(unsigned int pin, unsigned int to);
+void ak880x_gpio_intpol(unsigned int pin, unsigned int to);
+void ak880x_ioctl(unsigned int offset, const unsigned int to);
+
+unsigned int ak880x_gpio_to_irq(unsigned int pin);
+unsigned int ak880x_irq_to_gpio(unsigned int irq);
+
+#endif/*_AK88_GPIO_H_*/
diff --git a/arch/arm/mach-ak88/include/mach/guireg.h b/arch/arm/mach-ak88/include/mach/guireg.h
new file mode 100644
index 00000000000..2a852a774be
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/guireg.h
@@ -0,0 +1,203 @@
+#ifndef __AK_2DACC_REG_H__
+#define __AK_2DACC_REG_H__ __FILE__
+
+#define GUI_SET_REG(reg_addr, value)	(*((volatile T_U32 *)(reg_addr))) = (value)
+#define GUI_GET_REG(reg_addr)		(*((volatile T_U32 *)(reg_addr)))
+
+/* register address define */
+#define GUI_BASE_ADDR			0x20022000	// gui register base address
+#define GUI_CMD_ADDR			(GUI_BASE_ADDR+0x04)	// Command
+#define GUI_BLTSIZE_ADDR		(GUI_BASE_ADDR+0x08)	// Bitblt
+#define GUI_POINT1_ADDR			(GUI_BASE_ADDR+0x0c)	// Point 1
+#define GUI_DSTXY_ADDR			(GUI_BASE_ADDR+0x10)	// Dest. XY
+#define GUI_POINT2_ADDR			(GUI_BASE_ADDR+0x14)	// Point 2
+#define GUI_SRCXY_ADDR			(GUI_BASE_ADDR+0x18)	// Source XY
+#define GUI_POINT3_ADDR			(GUI_BASE_ADDR+0x1c)	// Point 3
+#define GUI_COLORCMP_ADDR		(GUI_BASE_ADDR+0x20)	// Color Compare
+#define GUI_CLIPLT_ADDR			(GUI_BASE_ADDR+0x24)	// Clip Left/Top
+#define GUI_CLIPRB_ADDR			(GUI_BASE_ADDR+0x28)	// Clip Right/Bottom
+#define GUI_FCOLOR_ADDR			(GUI_BASE_ADDR+0x2c)	// Foreground Color
+#define GUI_BCOLOR_ADDR			(GUI_BASE_ADDR+0x30)	// Background Color : Useless now
+#define GUI_SRCSTRD_ADDR		(GUI_BASE_ADDR+0x34)	// Source Stride
+#define GUI_DSTSTRD_ADDR		(GUI_BASE_ADDR+0x3c)	// Dest. Stride
+#define GUI_DSTADDR_ADDR		(GUI_BASE_ADDR+0x40)	// Dest. Base Address
+#define GUI_PATN0_ADDR			(GUI_BASE_ADDR+0x58)	// Pattern Part 0
+#define GUI_PATN1_ADDR			(GUI_BASE_ADDR+0x5c)	// Pattern Part 1
+#define GUI_PATNFC_ADDR			(GUI_BASE_ADDR+0x60)	// Pattern Foreground
+#define GUI_PATNBC_ADDR			(GUI_BASE_ADDR+0x64)	// Pattern Background
+#define GUI_ARBIOBJLID_ADDR		(GUI_BASE_ADDR+0x70)	// Arbitrary Object Line Index
+#define GUI_ARBIOBJLRB_ADDR		(GUI_BASE_ADDR+0x74)	// Arbitrary Object Left/Right Boundary
+#define GUI_SRCADDR_ADDR		(GUI_BASE_ADDR+0x78)	// Source Base Address
+#define GUI_STATUS_ADDR			(GUI_BASE_ADDR+0x7c)	// Status
+
+///////////////////////////////////////////////////////////////////////////////
+
+// command register bit
+#define CMD_RASTER_OP_VALUE_BIT		0	// Raster operation, 6:0
+#define CMD_RASTER_OP_BIT		7	// 0-raster, 1-alpha
+#define CMD_TYPE_BIT			8	// Command type, 10:8
+#define CMD_MONO_SRC_BIT		14	// Monochrome source, 14
+#define CMD_MONO_PAT_BIT		15	// Monochrome pattern, 15
+#define CMD_COLOR_TRANS_EN_BIT		16	// Color transparency enable, 16
+#define CMD_DST_TRANS_POL_BIT		17	// Destination transparency polarity, 17
+#define CMD_MONO_SRC_PAT_BIT		18	// Monochrome source or pattern transparency enable, 18
+#define CMD_MONO_TRANS_POL_BIT		19	// Monochrome transparency polarity, 19
+#define CMD_SOLID_SRC_BIT		21	// Solid source color, 21
+#define CMD_CLIP_EN_BIT			24	// Clipping enable, 24
+#define CMD_SOLID_PAT_BIT		26	// Solid pattern, 26
+#define CMD_TRANS_CMP_SRC_BIT		27	// Color transparency compare source, 27
+//#define CMD_3D_BIT                    28  // 3D command
+#define CMD_MATRIX_TRI_EN_BIT		30	// Matrix Triangle Enable
+
+// BitBLT width and height parameter register bit
+#define BITBLT_WIDTH_BIT		0	// Source or destination window width, 11:0
+#define BITBLT_HEIGHT_BIT		16	// Source or destination window height, 27:16
+
+// Bresenham line draw parameter register point1 bit
+#define POINT1_X_BIT			0	// X coordination of point1, 11:0
+#define POINT1_Y_BIT			16	// Y coordination of point1, 27:16
+
+// Destination XY register bit
+#define DSTXY_X_BIT			0	// Destination X position, 11:0
+//#define DST_MONO_X_OFF_BIT            12  // Monochrome pattern horizontal offset, 15:12
+#define DSTXY_Y_BIT			16	// Destination Y position, 27:16
+//#define DST_MONO_Y_OFF_BIT            28  // Monochrome pattern horizontal offset, 31:28
+
+// Bresenham line draw parameter register point2 bit
+#define POINT2_X_BIT			0	// X coordination of point2, 11:0
+#define POINT2_Y_BIT			16	// Y coordination of point2, 27:16
+
+// Source XY register bit
+#define SRCXY_X_BIT			0	// Source X position, 11:0
+#define SRCXY_Y_BIT			16	// Source Y position, 27:16
+
+// Bresenham line draw parameter register point3 bit
+#define POINT3_X_BIT			0	// X coordination of point3, 11:0
+#define POINT3_Y_BIT			16	// Y coordination of point3, 27:16
+
+// Color compare register bit
+#define COLCMP_TRANS_COLOR_BIT		0	// Destination transparent color, 23:0
+
+// Clip Left/Top register bit
+#define CLIPLT_LEFT_X_BIT		0	// Left edge of clipping rectangle, 11:0
+#define CLIPLT_TOP_Y_BIT		16	// Top edge of clipping rectangle, 27:16
+
+// Clip Left/Top register bit
+#define CLIPRB_RIGHT_X_BIT		0	// Right edge of clipping rectangle, 11:0
+#define CLIPRB_BOTTOM_Y_BIT		16	// Bottom edge of clipping rectangle, 27:16
+
+// Source stride register bit
+#define SRCSTRD_LINE_STRIDE_BIT		0	// Source line stride, 11:0
+#define SRCSTRD_MONO_SRC_START_BIT	13	// Monochrome source starts, 15:13
+
+// Destination stride and color depth register bit
+#define DSTSTRD_LINE_STRIDE_BIT		0	// Destination line stride, 11:0
+#define DSTSTRD_ROTATE_90		14	// Enable 90 degree clockwise rotation, 15:14
+
+// Monochrome pattern register0 bit
+#define PATN0_LINE0_BIT			0	// Line 0 of monochrome pattern, 7:0
+#define PATN0_LINE1_BIT			8	// Line 1 of monochrome pattern, 15:8
+#define PATN0_LINE2_BIT			16	// Line 2 of monochrome pattern, 23:16
+#define PATN0_LINE3_BIT			24	// Line 3 of monochrome pattern, 31:24
+
+// Monochrome pattern register1 bit
+#define PATN0_LINE4_BIT			0	// Line 4 of monochrome pattern, 7:0
+#define PATN0_LINE5_BIT			8	// Line 5 of monochrome pattern, 15:8
+#define PATN0_LINE6_BIT			16	// Line 6 of monochrome pattern, 23:16
+#define PATN0_LINE7_BIT			24	// Line 7 of monochrome pattern, 31:24
+
+// Color Space conversion and scaling control bit 
+
+// start rectangle draw operation with scaling and color conversion
+#define SCALCTRL_START_BIT		0
+#define SCALCTRL_BYPASS_BIT		1	// Bypass scaler, 2
+// input format, 3:2=00-rgb888), 01-rgb565, 10-YUV420
+#define SCALCTRL_FORMAT_BIT		2
+// destination image is also a source needed in GUI operations, 4
+#define SCALCTRL_NEEDED_BIT		4
+
+// Scaling parameters, scaling ration = 8192 / ILX[8:0]
+#define SCALRATIO_HORI_DIV_BIT		0	// Horizontal scaling divider ratio, 8:0
+#define SCALRATIO_VERT_DIV_BIT		16	// Vertical scaling divider ratio, 24:16
+
+// Input image rectangle dimensions
+#define SCALSRCRECT_WIDTH_BIT		0	// Input image width in pixels, 9:0
+#define SCALSRCRECT_HEIGHT_BIT		16	// Input image width in pixels, 24:16
+
+// Output image rectangle dimensions
+#define SCALDSTRECT_WIDTH_BIT		0	// Output image width in pixels, 9:0
+#define SCALDSTRECT_HEIGHT_BIT		16	// Output image width in pixels, 24:16
+
+/////////////////////////////////////////////////////////////////////////
+
+// command register bit 7
+#define RASTER_OP           0
+#define ALPHA_OP            1
+
+// raster operation
+#define RASTER_NO_OP        0
+#define RASTER_SRCAND       1
+#define RASTER_SRCOR        2
+#define RASTER_SRCXOR       3
+#define RASTER_SRCCOPY      4
+
+// command type
+#define TYPE_SCALE_CONVT    0	// draw rectangle with scaling and color conversion capability
+#define TYPE_RECT_FILL      1
+#define TYPE_LINE_DRAW      2
+#define TYPE_TRIANGLE_FILL  3
+#define TYPE_ARBITRARY_FILL 4
+#define TYPE_RECT_COPY      5
+
+// pattern start pixel
+#define PATN_START_PIXEL(n)     (n)
+
+// pattern start line
+#define PATN_START_LINE(n)      (n)
+
+// monochrome start bit
+#define MONO_START_BIT(n)       (n)
+
+////////////////////////////////////////////////////////////////////////////////
+
+// Gradient Color Fill
+#define GUI_REFPOINT_ADDR       (GUI_BASE_ADDR+0x200)	// Reference Point
+#define GUI_REFCOLOR_ADDR       (GUI_BASE_ADDR+0x204)	// Reference Color
+#define GUI_GRADCOLOR_X_ADDR    (GUI_BASE_ADDR+0x208)	// X Gradient Color
+#define GUI_GRADCOLOR_Y_ADDR    (GUI_BASE_ADDR+0x20c)	// Y Gradient Color
+#define GUI_GRAD_RED_X_ADDR     (GUI_BASE_ADDR+0x210)	// Denominator/Nominator X for color R
+#define GUI_GRAD_RED_Y_ADDR     (GUI_BASE_ADDR+0x214)	// Denominator/Nominator Y for color R
+#define GUI_GRAD_GREEN_X_ADDR   (GUI_BASE_ADDR+0x220)	// Denominator/Nominator X for color G
+#define GUI_GRAD_GREEN_Y_ADDR   (GUI_BASE_ADDR+0x224)	// Denominator/Nominator Y for color G
+#define GUI_GRAD_BLUE_X_ADDR    (GUI_BASE_ADDR+0x230)	// Denominator/Nominator X for color B
+#define GUI_GRAD_BLUE_Y_ADDR    (GUI_BASE_ADDR+0x234)	// Denominator/Nominator Y for color B
+
+// Reference Point Bit
+#define REF_POINT_ENABLE        24
+#define REF_POINT_X0            12
+#define REF_POINT_Y0            0
+
+// Denominator/Nominator Bit
+#define GRADFILL_ABS             20
+#define GRADFILL_NOMINATOR       8
+#define GRADFILL_DENOMINATOR     0
+
+////////////////////////////////////////////////////////////////////////////////
+
+// Matrix Triangle Fill
+#define GUI_MATRIX_SRCADDR	(GUI_BASE_ADDR+0x240)
+#define GUI_MATRIX_SRCSTRD	(GUI_BASE_ADDR+0x244)
+#define GUI_MATRIX_REG1		(GUI_BASE_ADDR+0x250)	// sx, shx [31:22], [21:12]
+#define GUI_MATRIX_REG2		(GUI_BASE_ADDR+0x254)	// sy, shy [31:22], [21:12]
+#define GUI_MATRIX_REG3		(GUI_BASE_ADDR+0x258)	// w0,  w1 [31:22], [21:12]
+#define GUI_MATRIX_REGTX	(GUI_BASE_ADDR+0x260)	// tx [23:0]
+#define GUI_MATRIX_REGTY	(GUI_BASE_ADDR+0x264)	// ty [23:0]
+#define GUI_MATRIX_REGW2	(GUI_BASE_ADDR+0x268)	// w2 [23:0]
+
+// Shift Bit
+#define GUI_MATRIX_SHIFT1	22
+#define GUI_MATRIX_SHIFT2	12
+
+////////////////////////////////////////////////////////////////////////////////
+
+#endif				// __GUI_REG_H__
diff --git a/arch/arm/mach-ak88/include/mach/hardware.h b/arch/arm/mach-ak88/include/mach/hardware.h
new file mode 100644
index 00000000000..66488e52119
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/hardware.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/hardware.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+#endif				/* __ASSEMBLY__ */
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+/* machine specific hardware definitions should go after this */
+
+#endif				/* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ak88/include/mach/i2c.h b/arch/arm/mach-ak88/include/mach/i2c.h
new file mode 100644
index 00000000000..7ab481f770c
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/i2c.h
@@ -0,0 +1,24 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __AK88_IIC_H
+#define __AK88_IIC_H __FILE__
+
+/* Notes:
+ *	1) All frequencies are expressed in Hz
+ *	2) A value of zero is `do not care`
+*/
+
+struct ak880x_platform_i2c {
+	unsigned int flags;
+	unsigned int slave_addr;	/* slave address for controller */
+	unsigned long bus_freq;	/* standard bus frequency */
+	unsigned long max_freq;	/* max frequency for the bus */
+	unsigned long min_freq;	/* min frequency for the bus */
+	unsigned int sda_delay;	/* pclks (s3c2440 only) */
+};
+
+#endif				/* __AK88_IIC_H */
diff --git a/arch/arm/mach-ak88/include/mach/io-ctl.h b/arch/arm/mach-ak88/include/mach/io-ctl.h
new file mode 100644
index 00000000000..ec9bf636190
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/io-ctl.h
@@ -0,0 +1,81 @@
+#ifndef __H_AK88_IO_CONTROL__
+#define __H_AK88_IO_CONTROL__
+
+/* IO control register 1 */
+#define DS_SDIO_MCMD		0
+#define DS_SDIO_MCK		1
+
+#define IE_URD1			2
+#define IE_UTD1			3
+#define IE_CTS1			4
+#define IE_RTS1			5
+
+#define IE_URD2			6
+#define IE_UTD2			7
+#define IE_CTS2			8
+#define IE_RTS2			9
+
+#define IE_URD3			10
+#define IE_UTD3			11
+#define IE_CTS3			12
+#define IE_RTS3			13
+
+#define PE_URD1			14
+#define PE_UTD1			15
+#define PE_CTS1			16
+#define PE_RTS1			17
+
+#define PE_URD2			18
+#define PE_UTD2			19
+#define PE_CTS2			20
+#define PE_RTS2			21
+
+#define PE_URD3			22
+#define PE_UTD3			23
+#define PE_CTS3			24
+#define PE_RTS3			25
+
+#define IE_SDIO_MCK		26
+#define IE_SDIO_MCMD		27
+
+#define DS_GPIO_29		0
+#define DS_GPIO_28		1
+
+#define IE_GPIO_17		2
+#define IE_GPIO_16		3
+#define IE_GPIO_19		4
+#define IE_GPIO_18		5
+#define IE_GPIO_21		6
+#define IE_GPIO_20		7
+#define IE_GPIO_23		8
+#define IE_GPIO_22		9
+#define IE_GPIO_25		10
+#define IE_GPIO_24		11
+#define IE_GPIO_27		12
+#define IE_GPIO_26		13
+
+#define PE_GPIO_17		14
+#define PE_GPIO_16		15
+#define PE_GPIO_19		16
+#define PE_GPIO_18		17
+#define PE_GPIO_21		18
+#define PE_GPIO_20		19
+#define PE_GPIO_23		20
+#define PE_GPIO_22		21
+#define PE_GPIO_25		22
+#define PE_GPIO_24		23
+#define PE_GPIO_27		24
+#define PE_GPIO_26		25
+
+#define IE_GPIO_29		26
+#define IE_GPIO_28		27
+
+/* IO control register 2 */
+
+#define IE_DGPIO_7		(32 + 4)
+#define PE_DGPIO_7		(32 + 8)
+#define DS_DGPIO_7		(32 + 12)
+
+void ak880x_ioctl(unsigned int offset, const unsigned int to);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/io.h b/arch/arm/mach-ak88/include/mach/io.h
new file mode 100644
index 00000000000..3aedda39b2e
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/io.h
@@ -0,0 +1,71 @@
+/*
+ * linux/include/asm-arm/arch-s3c2410/io.h
+ *  from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *	     (C) 2003 Simtec Electronics
+*/
+
+//#ifndef __ASM_ARM_ARCH_IO_H
+//#define __ASM_ARM_ARCH_IO_H
+#ifndef __ARCH_ARM_MACH_AK88_IO_H
+#define __ARCH_ARM_MACH_AK88_IO_H
+
+//#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
+ * and are translated to the start of IO.  Note that all addresses are
+ * not shifted left!
+ */
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)	(x)
+
+#define __io(a)		((void __iomem *)(a))
+
+#define AK88_DUMP_REG(x) { printk("reg 0x%x=0x%x\n",(u32)AK88_##x,(u32)__raw_readl(AK88_##x)); }
+
+static inline unsigned long AKSET_BITS(unsigned long bits_result, void *reg)
+{
+	volatile unsigned long val;
+	val = __raw_readl(reg);
+
+	val |= bits_result;
+
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static inline unsigned long AKCLR_BITS(unsigned long bits_result, void *reg)
+{
+	volatile unsigned long val;
+	val = __raw_readl(reg);
+	val &= ~bits_result;
+
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static inline bool AKGET_BIT(unsigned long bit_result, void *reg)
+{
+	unsigned long val;
+
+	val = __raw_readl(reg) & bit_result;
+
+	if (val == bit_result)
+		return true;
+	else
+		return false;
+
+}
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/irqs.h b/arch/arm/mach-ak88/include/mach/irqs.h
new file mode 100644
index 00000000000..7e716712c95
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/irqs.h
@@ -0,0 +1,219 @@
+/* linux/arch/arm/mach-ak880x/include/mach/irqs.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#define AK88_IRQ(x)		(x)
+
+/* Main cpu interrupts */
+#define	IRQ_AK_RESERVED0	AK88_IRQ(0)	/* No 0 reserved */
+#define	IRQ_DISPLAY_CTRL	AK88_IRQ(1)
+#define	IRQ_CAMERA_IF		AK88_IRQ(2)
+#define	IRQ_MOTIONESTIMATION	AK88_IRQ(3)
+
+#define	IRQ_IMG_MPEG4		AK88_IRQ(4)
+#define	IRQ_AUDIO		AK88_IRQ(5)
+#define	IRQ_H264_DECODER	AK88_IRQ(6)
+#define	IRQ_AK_RESERVED1	AK88_IRQ(7)	/* No 7 reserved */
+
+#define	IRQ_DAC			AK88_IRQ(8)
+#define	IRQ_AK_RESERVED2	AK88_IRQ(9)	/* No 9 reserved */
+#define	IRQ_L2MEM		AK88_IRQ(10)
+#define	IRQ_NF_ECC		AK88_IRQ(11)
+
+#define	IRQ_NF_CTRL		AK88_IRQ(12)
+#define	IRQ_UART3		AK88_IRQ(13)
+#define	IRQ_UART2		AK88_IRQ(14)
+#define	IRQ_UART1		AK88_IRQ(15)
+
+#define	IRQ_UART0		AK88_IRQ(16)
+#define	IRQ_SPI2		AK88_IRQ(17)
+#define	IRQ_SPI1		AK88_IRQ(18)
+#define	IRQ_AK_RESERVED3	AK88_IRQ(19)	/* No 19 reserved */
+
+#define	IRQ_2D_ACC		AK88_IRQ(20)
+#define	IRQ_SDIO		AK88_IRQ(21)
+#define	IRQ_MMC_SD		AK88_IRQ(22)
+#define	IRQ_USBHOST_MCU		AK88_IRQ(23)
+
+#define	IRQ_USBHOST_DMA		AK88_IRQ(24)
+#define	IRQ_USBOTG_MCU		AK88_IRQ(25)
+#define	IRQ_USBOTG_DMA		AK88_IRQ(26)
+#define	IRQ_SYSCTRL		AK88_IRQ(27)
+
+/* System control sub irqs */
+
+#define	AK88_SYSCTRL_IRQ(x)	((x) + IRQ_SYSCTRL + 1)
+
+#define	IRQ_TOUCHPANEL		AK88_SYSCTRL_IRQ(0)
+#define	IRQ_TIMER5		AK88_SYSCTRL_IRQ(1)
+#define	IRQ_TIMER4		AK88_SYSCTRL_IRQ(2)
+#define	IRQ_TIMER3		AK88_SYSCTRL_IRQ(3)
+
+#define	IRQ_TIMER2		AK88_SYSCTRL_IRQ(4)
+#define	IRQ_TIMER1		AK88_SYSCTRL_IRQ(5)
+#define	IRQ_CLK_ADJUST		AK88_SYSCTRL_IRQ(6)
+#define	IRQ_WGPIO		AK88_SYSCTRL_IRQ(7)
+
+#define	IRQ_RTC_RDY		AK88_SYSCTRL_IRQ(8)
+#define	IRQ_RTC_ALARM		AK88_SYSCTRL_IRQ(9)
+#define	IRQ_GPIO		AK88_SYSCTRL_IRQ(10)
+
+/* 
+ * GPIO interrupts
+ */
+
+#define AK88_GPIO_IRQ(x)	((x) + IRQ_GPIO + 1)
+
+#define IRQ_GPIO_0		AK88_GPIO_IRQ(0)
+#define IRQ_GPIO_1		AK88_GPIO_IRQ(1)
+#define IRQ_GPIO_2		AK88_GPIO_IRQ(2)
+#define IRQ_GPIO_3		AK88_GPIO_IRQ(3)
+#define IRQ_GPIO_4		AK88_GPIO_IRQ(4)
+#define IRQ_GPIO_5		AK88_GPIO_IRQ(5)
+#define IRQ_GPIO_6		AK88_GPIO_IRQ(6)
+#define IRQ_GPIO_7		AK88_GPIO_IRQ(7)
+#define IRQ_GPIO_8		AK88_GPIO_IRQ(8)
+#define IRQ_GPIO_9		AK88_GPIO_IRQ(9)
+#define IRQ_GPIO_10		AK88_GPIO_IRQ(10)
+#define IRQ_GPIO_11		AK88_GPIO_IRQ(11)
+#define IRQ_GPIO_12		AK88_GPIO_IRQ(12)
+#define IRQ_GPIO_13		AK88_GPIO_IRQ(13)
+#define IRQ_GPIO_14		AK88_GPIO_IRQ(14)
+#define IRQ_GPIO_15		AK88_GPIO_IRQ(15)
+#define IRQ_GPIO_16		AK88_GPIO_IRQ(16)
+#define IRQ_GPIO_17		AK88_GPIO_IRQ(17)
+#define IRQ_GPIO_18		AK88_GPIO_IRQ(18)
+#define IRQ_GPIO_19		AK88_GPIO_IRQ(19)
+#define IRQ_GPIO_20		AK88_GPIO_IRQ(20)
+#define IRQ_GPIO_21		AK88_GPIO_IRQ(21)
+#define IRQ_GPIO_22		AK88_GPIO_IRQ(22)
+#define IRQ_GPIO_23		AK88_GPIO_IRQ(23)
+#define IRQ_GPIO_24		AK88_GPIO_IRQ(24)
+#define IRQ_GPIO_25		AK88_GPIO_IRQ(25)
+#define IRQ_GPIO_26		AK88_GPIO_IRQ(26)
+#define IRQ_GPIO_27		AK88_GPIO_IRQ(27)
+#define IRQ_GPIO_28		AK88_GPIO_IRQ(28)
+#define IRQ_GPIO_29		AK88_GPIO_IRQ(29)
+#define IRQ_GPIO_30		AK88_GPIO_IRQ(30)
+#define IRQ_GPIO_31		AK88_GPIO_IRQ(31)
+#define IRQ_GPIO_32		AK88_GPIO_IRQ(32)
+#define IRQ_GPIO_33		AK88_GPIO_IRQ(33)
+#define IRQ_GPIO_34		AK88_GPIO_IRQ(34)
+#define IRQ_GPIO_35		AK88_GPIO_IRQ(35)
+#define IRQ_GPIO_36		AK88_GPIO_IRQ(36)
+#define IRQ_GPIO_37		AK88_GPIO_IRQ(37)
+#define IRQ_GPIO_38		AK88_GPIO_IRQ(38)
+#define IRQ_GPIO_39		AK88_GPIO_IRQ(39)
+#define IRQ_GPIO_40		AK88_GPIO_IRQ(40)
+#define IRQ_GPIO_41		AK88_GPIO_IRQ(41)
+#define IRQ_GPIO_42		AK88_GPIO_IRQ(42)
+#define IRQ_GPIO_43		AK88_GPIO_IRQ(43)
+#define IRQ_GPIO_44		AK88_GPIO_IRQ(44)
+#define IRQ_GPIO_45		AK88_GPIO_IRQ(45)
+#define IRQ_GPIO_46		AK88_GPIO_IRQ(46)
+#define IRQ_GPIO_47		AK88_GPIO_IRQ(47)
+#define IRQ_GPIO_48		AK88_GPIO_IRQ(48)
+#define IRQ_GPIO_49		AK88_GPIO_IRQ(49)
+#define IRQ_GPIO_50		AK88_GPIO_IRQ(50)
+#define IRQ_GPIO_51		AK88_GPIO_IRQ(51)
+#define IRQ_GPIO_52		AK88_GPIO_IRQ(52)
+#define IRQ_GPIO_53		AK88_GPIO_IRQ(53)
+#define IRQ_GPIO_54		AK88_GPIO_IRQ(54)
+#define IRQ_GPIO_55		AK88_GPIO_IRQ(55)
+#define IRQ_GPIO_56		AK88_GPIO_IRQ(56)
+#define IRQ_GPIO_57		AK88_GPIO_IRQ(57)
+#define IRQ_GPIO_58		AK88_GPIO_IRQ(58)
+#define IRQ_GPIO_59_RESERVED	AK88_GPIO_IRQ(59)	/* reserved */
+#define IRQ_GPIO_60_RESERVED	AK88_GPIO_IRQ(60)	/* reserved */
+#define IRQ_GPIO_61		AK88_GPIO_IRQ(61)
+#define IRQ_GPIO_62		AK88_GPIO_IRQ(62)
+#define IRQ_GPIO_63		AK88_GPIO_IRQ(63)
+#define IRQ_GPIO_64		AK88_GPIO_IRQ(64)
+#define IRQ_GPIO_65		AK88_GPIO_IRQ(65)
+#define IRQ_GPIO_66		AK88_GPIO_IRQ(66)
+#define IRQ_GPIO_67		AK88_GPIO_IRQ(67)
+#define IRQ_GPIO_68		AK88_GPIO_IRQ(68)
+#define IRQ_GPIO_69		AK88_GPIO_IRQ(69)
+#define IRQ_GPIO_70		AK88_GPIO_IRQ(70)
+#define IRQ_GPIO_71		AK88_GPIO_IRQ(71)
+#define IRQ_GPIO_72		AK88_GPIO_IRQ(72)
+#define IRQ_GPIO_73		AK88_GPIO_IRQ(73)
+#define IRQ_GPIO_74		AK88_GPIO_IRQ(74)
+#define IRQ_GPIO_75		AK88_GPIO_IRQ(75)
+#define IRQ_GPIO_76		AK88_GPIO_IRQ(76)
+#define IRQ_GPIO_77		AK88_GPIO_IRQ(77)
+#define IRQ_GPIO_78		AK88_GPIO_IRQ(78)
+#define IRQ_GPIO_79		AK88_GPIO_IRQ(79)
+#define IRQ_GPIO_80		AK88_GPIO_IRQ(80)
+#define IRQ_GPIO_81		AK88_GPIO_IRQ(81)
+#define IRQ_GPIO_82		AK88_GPIO_IRQ(82)
+#define IRQ_GPIO_83		AK88_GPIO_IRQ(83)
+
+/* DGPIO */
+#define IRQ_DGPIO_19		AK88_GPIO_IRQ(84)
+#define IRQ_DGPIO_20		AK88_GPIO_IRQ(85)
+#define IRQ_DGPIO_21		AK88_GPIO_IRQ(86)
+#define IRQ_DGPIO_22		AK88_GPIO_IRQ(87)
+#define IRQ_DGPIO_23		AK88_GPIO_IRQ(88)
+#define IRQ_DGPIO_24		AK88_GPIO_IRQ(89)
+#define IRQ_DGPIO_25		AK88_GPIO_IRQ(90)
+#define IRQ_DGPIO_26		AK88_GPIO_IRQ(91)
+#define IRQ_DGPIO_27		AK88_GPIO_IRQ(92)
+#define IRQ_DGPIO_28		AK88_GPIO_IRQ(93)
+#define IRQ_DGPIO_29		AK88_GPIO_IRQ(94)
+#define IRQ_DGPIO_30		AK88_GPIO_IRQ(95)
+#define IRQ_DGPIO_31		AK88_GPIO_IRQ(96)
+#define IRQ_DGPIO_32		AK88_GPIO_IRQ(97)
+#define IRQ_DGPIO_33		AK88_GPIO_IRQ(98)
+#define IRQ_DGPIO_34		AK88_GPIO_IRQ(99)
+#define IRQ_DGPIO_35		AK88_GPIO_IRQ(100)
+#define IRQ_DGPIO_36		AK88_GPIO_IRQ(101)
+#define IRQ_DGPIO_0		AK88_GPIO_IRQ(102)
+#define IRQ_DGPIO_1		AK88_GPIO_IRQ(103)
+#define IRQ_DGPIO_2		AK88_GPIO_IRQ(104)
+#define IRQ_DGPIO_3		AK88_GPIO_IRQ(105)
+#define IRQ_DGPIO_4		AK88_GPIO_IRQ(106)
+#define IRQ_DGPIO_5		AK88_GPIO_IRQ(107)
+#define IRQ_DGPIO_6		AK88_GPIO_IRQ(108)
+#define IRQ_DGPIO_7		AK88_GPIO_IRQ(109)
+#define IRQ_DGPIO_8		AK88_GPIO_IRQ(110)
+#define IRQ_DGPIO_9		AK88_GPIO_IRQ(111)
+#define IRQ_DGPIO_10		AK88_GPIO_IRQ(112)
+#define IRQ_DGPIO_11		AK88_GPIO_IRQ(113)
+#define IRQ_DGPIO_12		AK88_GPIO_IRQ(114)
+#define IRQ_DGPIO_13		AK88_GPIO_IRQ(115)
+#define IRQ_DGPIO_14		AK88_GPIO_IRQ(116)
+
+#define AK88_L2MEM_IRQ(x)	((x) + IRQ_DGPIO_14 + 1)
+
+#define IRQ_L2_FRAC_DMA		AK88_L2MEM_IRQ(0)
+#define IRQ_L2_UART0_TX_DMA	AK88_L2MEM_IRQ(1)
+#define IRQ_L2_UART0_RX_DMA	AK88_L2MEM_IRQ(2)
+#define IRQ_L2_UART1_TX_DMA	AK88_L2MEM_IRQ(3)
+#define IRQ_L2_UART1_RX_DMA	AK88_L2MEM_IRQ(4)
+#define IRQ_L2_UART2_TX_DMA	AK88_L2MEM_IRQ(5)
+#define IRQ_L2_UART2_RX_DMA	AK88_L2MEM_IRQ(6)
+#define IRQ_L2_UART3_TX_DMA	AK88_L2MEM_IRQ(7)
+#define IRQ_L2_UART3_RX_DMA	AK88_L2MEM_IRQ(8)
+#define IRQ_L2_BUF0_DMA		AK88_L2MEM_IRQ(9)
+#define IRQ_L2_BUF1_DMA		AK88_L2MEM_IRQ(10)
+#define IRQ_L2_BUF2_DMA		AK88_L2MEM_IRQ(11)
+#define IRQ_L2_BUF3_DMA		AK88_L2MEM_IRQ(12)
+#define IRQ_L2_BUF4_DMA		AK88_L2MEM_IRQ(13)
+#define IRQ_L2_BUF5_DMA		AK88_L2MEM_IRQ(14)
+#define IRQ_L2_BUF6_DMA		AK88_L2MEM_IRQ(15)
+#define IRQ_L2_BUF7_DMA		AK88_L2MEM_IRQ(16)
+#define IRQ_L2_LDMA_VLD		AK88_L2MEM_IRQ(17)
+#define IRQ_L2_CRC_VLD		AK88_L2MEM_IRQ(18)
+
+#define AK88_LAST_IRQ	IRQ_L2_CRC_VLD
+
+#define NR_IRQS			(AK88_LAST_IRQ + 1)
+
+#endif				/* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-ak88/include/mach/l2.h b/arch/arm/mach-ak88/include/mach/l2.h
new file mode 100644
index 00000000000..ed7618a6d98
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/l2.h
@@ -0,0 +1,359 @@
+/*
+ * linux/arch/arm/mach-ak88/include/l2.h
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_L2_H
+#define __ASM_ARCH_L2_H
+
+#include <mach/ak880x_addr.h>
+#include <asm/io.h>
+
+
+#define AK88_L2_DEBUG	1
+//#undef AK88_L2_DEBUG
+
+/*
+ * AK88xx L2 Control Register List and Bit map definition
+ * TODO: Add all register bit maps and move all to map.h in the future.
+*/
+#define AK88_VA_L2_DMA_ADDR		AK88_L2CTRL_REG(0x00)
+#define AK88_VA_L2_DMA_OP_TIMES		AK88_L2CTRL_REG(0x40)
+#define AK88_VA_L2_DMA_REQ		AK88_L2CTRL_REG(0x80)
+#define AK88_VA_L2_FRAC_DMA		AK88_L2CTRL_REG(0x84)
+#define AK88_VA_L2_COMMON_BUF_CFG	AK88_L2CTRL_REG(0x88)
+#define AK88_VA_L2_UART_BUF_CFG		AK88_L2CTRL_REG(0x8C)
+#define AK88_VA_L2_BUF_ASSIGN1		AK88_L2CTRL_REG(0x90)
+#define AK88_VA_L2_BUF_ASSIGN2		AK88_L2CTRL_REG(0x94)
+#define AK88_VA_L2_INTR_ENABLE		AK88_L2CTRL_REG(0x9C)
+#define AK88_VA_L2_BUF_STAT1		AK88_L2CTRL_REG(0xA0)
+#define AK88_VA_L2_BUF_STAT2		AK88_L2CTRL_REG(0xA8)
+
+#define AK88_L2_DMA_REQ_BUF_START		24
+#define AK88_L2_DMA_REQ_BUF_REQ_MASK		(0xFFFF << 16)
+#define AK88_L2_DMA_REQ_UART_BUF_REQ_START	16
+#define AK88_L2_DMA_REQ_FRAC_DMA_LEN_START	10
+#define AK88_L2_DMA_REQ_FRAC_DMA_LEN_MASK	(0x3F << AK88_L2_DMA_REQ_FRAC_DMA_LEN_START)
+#define AK88_L2_DMA_REQ_FRAC_DMA_REQ		(1 << 9)
+#define AK88_L2_DMA_REQ_FRAC_DMA_DIR_WR		(1 << 8)
+#define AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START	1
+#define AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_MASK	(0x7F << AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START)
+#define AK88_L2_DMA_REQ_EN			(1 << 0)
+
+#define AK88_L2_FRAC_DMA_AHB_FLAG_EN		(1 << 29)
+#define AK88_L2_FRAC_DMA_LDMA_FLAG_EN		(1 << 28)
+#define AK88_L2_DMA_ADDR_MASK			(0xFFFFFFF << 0)
+#define AK88_L2_FRAC_DMA_ADDR_MASK		(0xFFFFFFF << 0)
+
+#define AK88_L2_COMMON_BUF_CFG_BUF7_CLR		(1 << 31)
+#define AK88_L2_COMMON_BUF_CFG_BUF6_CLR		(1 << 30)
+#define AK88_L2_COMMON_BUF_CFG_BUF5_CLR		(1 << 29)
+#define AK88_L2_COMMON_BUF_CFG_BUF4_CLR		(1 << 28)
+#define AK88_L2_COMMON_BUF_CFG_BUF3_CLR		(1 << 27)
+#define AK88_L2_COMMON_BUF_CFG_BUF2_CLR		(1 << 26)
+#define AK88_L2_COMMON_BUF_CFG_BUF1_CLR		(1 << 25)
+#define AK88_L2_COMMON_BUF_CFG_BUF0_CLR		(1 << 24)
+#define AK88_L2_COMMON_BUF_CFG_BUF_CLR_START	24
+#define AK88_L2_COMMON_BUF_CFG_BUF0_7_CLR_MASK	(0xFF << AK88_L2_COMMON_BUF_CFG_BUF_START)
+#define AK88_L2_COMMON_BUF_CFG_BUF_VLD_START	16
+#define AK88_L2_COMMON_BUF_CFG_BUF0_7_VLD_MASK	(0xFF << AK88_L2_COMMON_BUF_CFG_BUF_VLD_START
+#define AK88_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START	0
+#define AK88_L2_COMMON_BUF_CFG_BUF_DIR_START	8
+
+#define AK88_L2_UART_BUF_CFG_BUF_START		16
+
+#define AK88_L2_UART_BUF_CFG_UART_EN_MASK	(0xF << 28)
+#define AK88_L2_UART_BUF_CFG_UART_CLR_MASK	(0xFF << 16)
+#define AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_EN	(1 << 3)
+#define AK88_L2_UART_BUF_CFG_CPU_BUF_NUM_START	4
+#define AK88_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK	(0xF << AK88_L2_UART_BUF_CFG_CPU_BUF_NUM_START)
+#define AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_START	0
+#define AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK	(0x7 << AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_START)
+
+#define AK88_L2_DMA_INTR_ENABLE_BUF_START	9
+#define AK88_L2_DMA_INTR_ENABLE_UART_BUF_START	1
+#define AK88_L2_DMA_INTR_ENABLE_FRAC_INTR_EN	(1 << 0)
+
+/*
+ * AK88xx L2 buffer size(buffer 0 to buffer 7), all 512Bytes.
+ * NOTE: L2 buffer 8 to 15 dedicate to UART 1 to 4 &  USB 2.0 Controller, 
+ *           and the corresponding L2 buffer size could be 64, 128 and 256 Bytes.
+ * See AK88xx Programmer's Guide for details (AK8801 preferably).
+ */
+#define AK88_L2_BUFFER_SIZE	512
+
+/*
+  * AK88xx L2 DMA waiting times in loop
+  * TODO: Must be change to waiting time based on CPU frequency when frequency APIs are done.
+  */
+#define AK88_L2_MAX_DMA_WAIT_TIME	50 * 1000000UL
+
+/*
+ * AK88xx DMA size in bytes per transfer (Always 64Bytes)
+ * L2 DMA transfer follows this definition.
+ */
+#define AK88_DMA_ONE_SHOT_LEN		64
+
+/*
+ * AK88xx L2 Buffer Status Multiply Ratio(64)
+ * Buffer Status Register 1 & 2: The number of data = Bufn_sta * AK88_L2_BUF_STATUS_MULTIPLY_RATIO
+ */
+#define AK88_L2_BUF_STATUS_MULTIPLY_RATIO	64
+
+/*
+ * L2 Buffer ID Assignment:
+ * 0 - 7: L2 common buffer, could be used by different peripherals
+ * 8 - 15: Dedicate L2 buffer for UART
+ * 16 - 18: Dedicate L2 buffer for USB
+ */
+#define AK88_L2_COMMON_BUFFER_NUM	8
+#define AK88_L2_UART_BUFFER_NUM		8
+#define AK88_L2_USB_HOST_BUFFER_NUM	1
+#define AK88_L2_USB_BUFFER_NUM		2
+
+#define AK88_L2_UART_BUFFER_INDEX	AK88_L2_COMMON_BUFFER_NUM
+#define AK88_L2_USB_HOST_BUFFER_INDEX	(AK88_L2_UART_BUFFER_INDEX + AK88_L2_UART_BUFFER_NUM)
+#define AK88_L2_USB_BUFFER_INDEX	(AK88_L2_USB_HOST_BUFFER_INDEX + AK88_L2_USB_HOST_BUFFER_NUM)
+
+#define AK88_L2_COMMON_BUFFER_LEN	512
+#define AK88_L2_UART_BUFFER_LEN		128
+#define AK88_L2_USB_HOST_BUFFER_LEN	256
+#define AK88_L2_USB_BUFFER_LEN		64
+
+#define AK88_L2_COMMON_BUFFER_OFFSET	0
+#define AK88_L2_UART_BUFFER_OFFSET	(AK88_L2_COMMON_BUFFER_LEN * AK88_L2_COMMON_BUFFER_NUM)
+#define AK88_L2_USB_HOST_BUFFER_OFFSET	(AK88_L2_UART_BUFFER_OFFSET + AK88_L2_UART_BUFFER_LEN * AK88_L2_UART_BUFFER_NUM)
+#define AK88_L2_USB_BUFFER_OFFSET	(AK88_L2_USB_HOST_BUFFER_OFFSET + AK88_L2_USB_BUFFER_LEN * AK88_L2_USB_BUFFER_NUM)
+
+/*
+ * AK88xx L2 device list which may use L2 memory.
+ * The devices are defined according to L2 Buffer Assignement 1 & 2 register bit sequence.
+ */
+typedef enum {
+	ADDR_USB_BULKOUT = 0,		/* USB 2.0 HS OTG Controller: Bulkout */
+	ADDR_USB_BULKIN,		/* USB 2.0 HS OTG Controller: Bulkin */
+	ADDR_USB_ISO,			/* USB 2.0 HS OTG Controller: ISO buffer */
+	ADDR_NFC,			/* NAND Flash Controller */
+	ADDR_MMC_SD,			/* MMC/SD interface */
+	ADDR_SDIO,			/* SDIO interface */
+	ADDR_RESERVED,			/* Reserved */
+	ADDR_SPI1_RX,			/* Rx buffer of SPI1 Controller */
+	ADDR_SPI1_TX,			/* Tx buffer of SPI1 Controller */
+	ADDR_DAC,			/* DAC control module */
+	ADDR_SPI2_RX,			/* Rx buffer of SPI2 Controller */
+	ADDR_SPI2_TX,			/* Tx buffer of SPI2 Controller */
+	ADDR_PCM_RX,			/* Rx buffer of PCM Controller */
+	ADDR_PCM_TX,			/* Tx buffer of PCM Controller */
+	ADDR_ADC,			/* ADC2 and ADC3 */
+} ak88_l2_device_t;
+
+#define BUF_NULL			0xFF	/* Invalid L2 buffer ID */
+#define AK88_L2_UART_BUF_START_ID	AK88_L2_COMMON_BUFFER_NUM	/* UART used buffer ID from 8 */
+
+/*
+ * Maximum L2 DMA status value (The value in CPU-Controlled Buffer and Buffer8 ~ Buffer15 Configuration Register)
+ * The maximum DMA transfer bytes = MAX_L2_DMA_STATUS_VALUE * 64
+ */
+#define MAX_L2_DMA_STATUS_VALUE		0x8
+#define MAX_L2_BUFFER_USED_TIMES	0xFFFF
+
+/*
+ * Data transfer direction between L2 memory and external RAM
+ */
+typedef enum {
+	BUF2MEM = 0,	/* Data transfer from L2 buffer to external RAM */
+	MEM2BUF,	/* Data transfer from external RAM to L2 buffer */
+} ak88_l2_dma_transfer_direction_t;
+
+/*
+ * Callback function when L2 DMA/fraction DMA interrupt handler is done
+ */
+typedef void (*ak88_l2_callback_func_t)(void);
+
+/*
+ * L2 buffer status
+ */
+typedef enum {
+	L2_STAT_USED = 0,	/* Current L2 buffer is used by some device */
+	L2_STAT_IDLE,		/* Current L2 buffer is NOT used by some device, thus could be allocated */
+} ak88_l2_buffer_status_t;
+
+/*
+ * L2 buffer information
+ */
+typedef struct {
+	u8 id;				/* L2 buffer ID (0~17) */
+	ak88_l2_buffer_status_t usable;	/* L2 buffer status(used or idle) */
+	u16 used_time;			/* Counter on L2 buffer used times */
+} ak88_l2_buffer_info_t;
+
+/*
+ * Information on device which use L2 memory
+ */
+typedef struct {
+	ak88_l2_device_t device;	/* Device ID */
+	u8 id;				/* TODO: Remove id in the future since array index already represent buffer id */
+} ak88_l2_device_info_t;
+
+/*
+ * L2 DMA usage information (including DMA/fraction DMA/external RAM/Callback function)
+ */
+typedef struct {
+	bool dma_start;
+	bool intr_enable;
+	ak88_l2_dma_transfer_direction_t direction;
+	void *dma_addr;
+	u32  dma_op_times;
+	bool need_frac;
+	bool dma_frac_start;
+	void *dma_frac_addr;
+	u32  dma_frac_offset;
+	u32  dma_frac_data_len;
+	ak88_l2_callback_func_t callback_func;
+	wait_queue_head_t wq;
+	int dma_irq_done;
+} ak88_l2_dma_info_t;
+
+/**
+ * ak88_l2_init - Initialize linux kernel L2 memory support
+ */
+void __init ak88_l2_init(void);
+
+/**
+ * ak88_l2_alloc - Allocate a common L2 buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak88_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ */
+u8 ak88_l2_alloc(ak88_l2_device_t device);
+
+/**
+ * ak88_l2_free - Free L2 common buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak88_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ *  NOTE: Return the previous L2 buffer ID if a L2 buffer has been allocated to the device.
+ *            This means one device could get only one L2 buffer maximum.
+ */
+void ak88_l2_free(ak88_l2_device_t device);
+
+/**
+ * ak88_l2_set_dma_callback - Set callback function when L2 DMA/fraction DMA interrupt handler is done
+ *  @id:		L2 buffer ID
+ *  @func:	Callback function
+ *  Return true(Always)
+ *  
+ *  NOTE: Caller MUST guarantee that L2 buffer ID is valid. And since the callback function is called
+ *  in interrupt handler, it MUST NOT call any functions which may sleep.
+ */
+bool ak88_l2_set_dma_callback(u8 id, ak88_l2_callback_func_t func);
+
+/**
+ * ak88_l2_combuf_dma - Start data tranferring between memory and l2 common buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:			L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:		Open interrupt for this L2 buffer or not
+ */
+void ak88_l2_combuf_dma(unsigned long ram_addr, u8 id, unsigned int bytes, ak88_l2_dma_transfer_direction_t direction, bool intr_enable);
+
+/**
+ * ak88_l2_combuf_wait_dma_finish - Wait for L2 DMA finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak88_l2_combuf_dma.
+ */
+bool ak88_l2_combuf_wait_dma_finish(u8 id);
+
+/**
+ * ak88_l2_combuf_cpu - Transfer data between memory and l2 common buffer in CPU mode
+ *  @ram_addr:	External RAM address(Physical)
+ *  @id:	L2 buffer ID
+ *  @bytes:	Data transfer size
+ *  @direction:	Data transfer direction between L2 memory and external RAM
+ *
+ *  NOTE: According to XuChang, if one transfer data from Peripheral --> L2 Buffer --> RAM, 
+ *            special care need to be taken when data size is NOT multiple of 64Bytes.
+ *            Pheripheral driver must check hardware signals to confirm data has been transfer from
+ *            peripheral to L2 buffer since L2 do NOT provide some mechanism to confirm data has
+ *            been in L2 Buffer. Driver can and only can call ak88_l2_combuf_cpu() to copy data from L2
+ *            Buffer --> RAM after checking hardware signals.
+ *            As to 64Bytes * n size data, L2 could check Buffer Status Status Counter to confirm that
+ *            Data has been transfer from peripheral to L2 buffer, so no hardware signals checking needed.
+ */
+void ak88_l2_combuf_cpu(unsigned long ram_addr, u8 id, unsigned int bytes, ak88_l2_dma_transfer_direction_t direction);
+
+/**
+ * ak88_l2_get_status - Get L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+u8 ak88_l2_get_status(u8 id);
+
+/**
+ * ak88_l2_clr_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+void ak88_l2_clr_status(u8 id);
+
+/**
+ * ak88_l2_set_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ *  @status:	Status to be set (0 ~ 8)
+ */
+void ak88_l2_set_status(u8 id, u8 status);
+
+#ifdef AK88_L2_DEBUG
+#define AK88_L2_PRINT_FUNCLINES() do { printk("%s(): line: %d\n", __func__, __LINE__); } while (0)
+
+static inline void ak88_l2_dump_registers(void)
+{
+	printk("AK88xx L2 Register Dumping Begin:\n");
+
+	printk("  AK88_VA_L2_DMA_REQ(C080)        = 0x%08X, AK88_VA_L2_FRAC_DMA(C084)     = 0x%0X\n",
+		__raw_readl(AK88_VA_L2_DMA_REQ), __raw_readl(AK88_VA_L2_FRAC_DMA));
+	printk("  AK88_VA_L2_COMMON_BUF_CFG(C088) = 0x%08X, AK88_VA_L2_UART_BUF_CFG(C08C) = 0x%0X\n",
+		__raw_readl(AK88_VA_L2_COMMON_BUF_CFG), __raw_readl(AK88_VA_L2_UART_BUF_CFG));
+	printk("  AK88_VA_L2_BUF_ASSIGN1(C090)    = 0x%08X, AK88_VA_L2_INTR_ENABLE(C09C)  = 0x%0X\n",
+		__raw_readl(AK88_VA_L2_BUF_ASSIGN1), __raw_readl(AK88_VA_L2_INTR_ENABLE));
+	printk("  AK88_VA_L2_BUF_STAT1(C0A0)      = 0x%08X, AK88_VA_L2_BUF_STAT2(C0A8)    = 0x%0X\n",
+		__raw_readl(AK88_VA_L2_BUF_STAT1), __raw_readl(AK88_VA_L2_BUF_STAT2));
+
+	printk("AK88xx L2 Register Dumping End.\n");
+}
+
+static inline void ak88_l2_print_array(const char *name, unsigned char *array, int len)
+{
+	int i;
+
+	printk("%s[%d] = {\n ", name, len);
+	for (i = 0; i < len; i++) {
+		printk(" 0x%02X,", array[i]);
+		if (i % 16 == 15)
+			printk("\n ");
+	}
+	printk("};\n");
+
+}
+
+#else
+#define AK88_L2_PRINT_FUNCLINES() do { } while (0)
+
+static inline void ak88_l2_dump_registers(void)
+{
+}
+static inline void ak88_l2_print_array(const char *name, unsigned int *array, int len)
+{
+}
+#endif
+
+#endif	/* __ASM_ARCH_L2_H */
diff --git a/arch/arm/mach-ak88/include/mach/lib_l2.h b/arch/arm/mach-ak88/include/mach/lib_l2.h
new file mode 100644
index 00000000000..3618aa88509
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/lib_l2.h
@@ -0,0 +1,357 @@
+/**
+* @FILENAME: l2.h
+* @BRIEF l2 buffer driver head file
+* Copyright (C) 2007 Anyka (Guang zhou) Software Technology Co., LTD
+* @AUTHOR Pumbaa
+* @DATA 2007-09-11
+* @VERSION 1.8
+* @REF please refer to...
+*/
+
+/******************************************
+The following is an example to use mmc and sd driver APIs
+
+******************************************/
+#ifndef _ARCH_ARM_MACH_AK88_LIB_L2_H
+#define _ARCH_ARM_MACH_AK88_LIB_L2_H
+
+//#include "anyka_types.h"
+
+#define    BUF2MEM                0
+#define    MEM2BUF                1
+#define    L2_SINGLE_BUF_SIZE     512
+#define    L2_INVALIDE_BUF_ID     0xff
+
+typedef enum {
+	ADDR_USB_BULKOUT = 0,
+	ADDR_USB_BULKIN,	// 1
+	ADDR_USB_ISO,		// 2
+	ADDR_NFC,		// 3
+	ADDR_MMC_SD,		// 4
+	ADDR_SDIO,		// 5
+	ADDR_RESERVED,		// 6
+	ADDR_SPI1_RX,		// 7
+	ADDR_SPI1_TX,		// 8    
+	ADDR_DAC,		// 9
+	ADDR_SPI2_RX,		// 10            
+	ADDR_SPI2_TX		// 11
+} DEVICE_SELECT;
+
+/**
+* @BRIEF initial l2 buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_VOID:
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_Initial(T_VOID);
+void l2_init(void);
+
+/**
+* @BRIEF allocate a buffer which doesn't used by other device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 *buf_id : the pointer of the variable which storage return buffer id
+* @RETURN T_BOOL: if allocate a buffer successful, return AK_TRUE, otherwise, return AK_FALSE
+* @NOTE: to make sure buffer allocate by this function is avalid, user must check the return value
+*/
+//T_BOOL L2_AllocBuf(T_U8 *buf_id);
+unsigned char l2_alloc_buf(unsigned char *buf_id);
+
+/**
+* @BRIEF set device information
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device to be select for change it's information
+* @PARAM T_U8 buf_id0: a buffer of device used
+* @PARAM T_U8 buf_id0: anther buffer of device used
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_SetDevInfo(DEVICE_SELECT dev_slct, T_U8 buf_id, T_U8 buf_id1);
+void l2_set_devinfo(DEVICE_SELECT dev_slct, unsigned char buf_id,
+		    unsigned char buf_id1);
+
+/**
+* @BRIEF free a or two buffer(s) which used by a device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_FreeBuf(DEVICE_SELECT dev_slct);
+void l2_free_buf(DEVICE_SELECT dev_slct);
+
+/**
+* @BRIEF set a buffer as device buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_SlctBuf(DEVICE_SELECT dev_sel, T_U8 buf_id);
+void l2_slct_buf(DEVICE_SELECT dev_sel, unsigned char buf_id);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+//T_VOID L2_ComBufDMA(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_dma(unsigned int ram_addr, unsigned char buf_id,
+		   unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer fraction data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+//T_VOID L2_ComBufFracDMA(T_U32 ram_addr, T_U8 buf_id, T_U8 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_fracdma(unsigned int ram_addr, unsigned char buf_id,
+		       unsigned char buf_offset, unsigned int tran_byte,
+		       unsigned char tran_dir);
+
+/**
+* @BRIEF wait DMA transfer data between memory and common buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitComBufDMAFinish(T_U8 buf_id);
+void l2_wait_combuf_dmafinish(unsigned char buf_id);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma and fraction dma
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 512
+*/
+//T_VOID L2_ComBufTranData(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_tran_data(unsigned int ram_addr, unsigned char buf_id,
+			 unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with cpu
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: 1. from RAM to buffer 0. from buffer to RAM
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 512
+*/
+//T_VOID L2_ComBufTranData_CPU(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+			     unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+//T_VOID L2_UartBufDMA(T_U32 ram_addr, T_U8 uart_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_uartbuf_dma(unsigned int ram_addr, unsigned char uart_id,
+		    unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer fraction data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+//T_VOID L2_UartBufFracDMA(T_U32 ram_addr, T_U8 uart_id, T_U8 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_uartbuf_fracdma(unsigned int ram_addr, unsigned char uart_id,
+			unsigned char buf_offset, unsigned int tran_byte,
+			unsigned char tran_dir);
+
+/**
+* @BRIEF wait DMA transfer data between memory and uart buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 tran_dir: the transfer direction
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitUartBufDMAFinish(T_U8 uart_id, T_U8 tran_dir);
+void l2_wait_uartbuf_dmafinish(unsigned char uart_id, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma and fraction dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 128
+*/
+//T_VOID L2_UartBufTxData(T_U32 ram_addr, T_U8 uart_id, T_U32 tran_byte);
+void l2_uartbuf_tx_data(unsigned int ram_addr, unsigned char uart_id,
+			unsigned int tran_byte);
+
+/**
+* @BRIEF wait fraction DMA transfer data between memory and buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitFracDMAFinish(T_VOID);
+void l2_wait_frac_dmafinish(void);
+
+/**
+* @BRIEF transfer data between memory and l2 buffer with CPU mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U32 buf_addr: the buffer address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: if buffer is common buffer, the max value of tran_byte should be 512, if buffer is uart buffer, the
+        max value of tran_byte should be 128.
+*/
+//T_VOID L2_TranDataCPU(T_U32 ram_addr, T_U8 buf_id, T_U32 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+		      unsigned int buf_offset, unsigned int tran_byte,
+		      unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data from a buffer to another buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 dst_addr: the destination buffer address
+* @PARAM T_U32 src_addr: the source buffer address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @RETURN T_VOID: 
+* @NOTE: all the parameter must be multiple of 4 bytes
+*/
+//T_VOID L2_LocalDMA(T_U32 dst_addr, T_U32 src_addr, T_U32 tran_byte);
+void l2_localdma(unsigned int dst_addr, unsigned int src_addr,
+		 unsigned int tran_byte);
+
+/**
+* @BRIEF return a common buffer current flag 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_BOOL: if return flag is 1, it mean buffer is full, otherwise mean buffer is empty 
+* @NOTE: buffer id should be 0~7
+*/
+//T_U8 L2_ComBufFlag(T_U8 buf_id);
+unsigned char l2_combuf_flag(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly set a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_SetComBufFlag(T_U8 buf_id);
+void l2_set_combuf_flag(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly clear a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_ClrComBufFlag(T_U8 buf_id);
+void l2_clr_combuf_flag(unsigned char buf_id);
+
+//T_VOID L2_ChangeSetFlag(T_U8 buf_id, T_U8 set_status_flag);
+void l2_change_set_flag(unsigned char buf_id, unsigned char set_status_flag);
+
+/**
+* @BRIEF forcibly clear a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_ClrComBufStatus(T_U8 buf_id);
+void l2_clr_combuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly clear a uart buffer status to 0
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 8~15
+*/
+//T_VOID L2_ClrUartBufStatus(T_U8 buf_id);
+void l2_clr_uartbuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF return a common buffer current flag 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_BOOL: if return flag is 1, it mean buffer is full, oterwise mean buffer is empty 
+* @NOTE: buffer id should be 0~7
+*/
+//T_U8 L2_ComBufStatus(T_U8 buf_id);
+unsigned char l2_combuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF return a uart buffer current status 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_U8: if return status is 2, it mean buffer is full, if return 1, it mean buffer is half full, oterwise 
+                mean buffer is empty 
+* @NOTE: buffer id should be 8~15
+*/
+//T_U8 L2_UartBufStatus(T_U8 buf_id);
+unsigned char l2_uartbuf_status(unsigned char buf_id);
+
+//unsigned long AKSET_BITS(unsigned long bits_result,/* void __iomem* */void* reg);
+//unsigned long AKCLR_BITS(unsigned long bits_result,/* void __iomem* */void* reg);
+//bool AKGET_BIT(unsigned long bit_result,/* void __iomem* */void* reg);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/lib_lcd.h b/arch/arm/mach-ak88/include/mach/lib_lcd.h
new file mode 100644
index 00000000000..3195f5dc173
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/lib_lcd.h
@@ -0,0 +1,161 @@
+#ifndef __ARCH_ARM_MACH_AK88_LIB_LCD_H
+#define __ARCH_ARM_MACH_AK88_LIB_LCD_H
+
+#include <mach/map.h>
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+struct tft_lcd_timing_info {
+
+	u8 bus_width;		//24
+	u32 interlace;		//PROGRESS=1<<20   //interlace(1) or progress(0)
+	u8 hvg_pol;		//0xe              //h_sync(bit2),v_sync(bit1),gate(bit0) polarity
+	u16 rgb_bit;		//0x0888           //RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+
+	u32 clock_hz;		//30,000,000(30M)  //bit clock, clock cycle,unit HZ
+
+	u32 h_sync_hz;		//15711??          //h_sync cycle,unit HZ
+	u32 v_sync_001hz;	//5885             //v_sync cycle,unit 0.01HZ
+
+	u16 h_tot_clk;		//1058             //horizontal total cycle,unit clock
+	u16 h_disp_clk;		//800              //horizontal display cycle,unit clock
+	u16 h_front_porch_clk;	//170              //horizontal front porch,unit clock
+	u16 h_pulse_width_clk;	//48               //horizontal pulse width,unit clock
+	u16 h_back_porch_clk;	//40               //horizontal back porch,unit clock
+
+	u16 v_tot_clk;		//553              //vertical   total cycle,unit h_sync
+	u16 v_disp_clk;		//480              //vertical   display cycle,unit h_sync
+	u16 v_front_porch_clk;	//40               //vertical   front porch,unit clock
+	u16 v_pulse_width_clk;	//4                //vertical   pulse width,unit clock
+	u16 v_back_porch_clk;	//29               //vertical   back porch,unit clock
+
+	char *name;
+};
+
+//lcd panel info
+struct lcd_size {
+
+	u16 w_pixel;
+	u16 h_pixel;
+	u32 pixels;
+	u8 byte_per_pixel;
+	u32 ram_size;
+	u32 freq;
+};
+
+//display ram info
+struct display_ram {
+
+	u8 *p_rgb_base1;	//physical frame base
+	u8 *p_rgb_vrt_base1;
+	u32 rgb_len1;
+	u8 *p_rgb_base2;
+	u8 *p_rgb_vrt_base2;
+	u32 rgb_len2;
+
+	u8 *p_yuv1_base;
+	u8 *p_yuv1_vrt_base;
+	u32 yuv1_len;
+	u8 *p_yuv2_base;
+	u8 *p_yuv2_vrt_base;
+	u32 yuv2_len;
+
+	u8 *p_osd_base;
+	u8 *p_osd_vrt_base;
+	u32 osd_len;
+};
+
+//need refresh picture area
+struct picture_area {
+	u32 h_offset;
+	u32 v_offset;
+	u32 h_len;
+	u32 v_len;
+	u8 *buf;
+};
+
+typedef enum {
+	LCD_IF_MPU = 0,
+	LCD_IF_RGB,
+	LCD_IF_TVOUT
+} LCD_IF_MODE;
+
+#define AK88_LCD_CMD_REG1	      (AK88_VA_DISP + 0x00)
+#define AK88_LCD_REST_SIGNAL        (AK88_VA_DISP + 0x08)	//to send a reset signal
+#define AK88_LCD_RGB_CTRL1          (AK88_VA_DISP + 0x10)	//signal of RGB interface conf
+#define AK88_LCD_RGB_CTRL2          (AK88_VA_DISP + 0x14)	//buffer address setting and to enable virtual page func of data from RGB channel
+#define AK88_LCD_RGB_VIRPAGE_SIZE   (AK88_VA_DISP + 0x18)	//virtual page size of the data input from RGB channel
+#define AK88_LCD_RGB_VIRPAGE_OFFSET (AK88_VA_DISP + 0x1C)	//virtual page offset reg
+#define AK88_LCD_OSD_ADDR           (AK88_VA_DISP + 0x20)	//osd address
+#define AK88_LCD_BKG_COLO           (AK88_VA_DISP + 0x3C)	//background color
+#define AK88_LCD_RGB_CTRL3          (AK88_VA_DISP + 0x40)	//Horizontal/Vertical sync pulse width
+#define AK88_LCD_RGB_CTRL4          (AK88_VA_DISP + 0x44)	//Horizontal back porch width and display area width
+#define AK88_LCD_RGB_CTRL5          (AK88_VA_DISP + 0x48)	//Horizontal front porch width
+#define AK88_LCD_RGB_CTRL6          (AK88_VA_DISP + 0x4C)	//Vertical back porch width
+#define AK88_LCD_RGB_CTRL7          (AK88_VA_DISP + 0x50)	//Vertical front porch width
+#define AK88_LCD_RGB_CTRL8          (AK88_VA_DISP + 0x54)	//Vertical display area
+#define AK88_LCD_RGB_CTRL9          (AK88_VA_DISP + 0x58)	//Length of VOVSYNC signal
+#define AK88_LCD_RGB_OFFSET         (AK88_VA_DISP + 0xA8)	//Offset values of the data input from RGB channel
+#define AK88_LCD_RGB_SIZE           (AK88_VA_DISP + 0xAC)	//the size of the data input from RGB channel
+#define AK88_LCD_DISP_AREA          (AK88_VA_DISP + 0xB0)	//Display area size
+#define AK88_LCD_CMD_REG2           (AK88_VA_DISP + 0xB4)	//LCD command
+#define AK88_LCD_OPER_REG           (AK88_VA_DISP + 0xB8)	//to start the reflash func
+#define AK88_LCD_STATUS_REG         (AK88_VA_DISP + 0xBC)
+#define AK88_LCD_INT_ENAB           (AK88_VA_DISP + 0xC0)	//to enable interrupt
+//status_reg bits corespondents to int_enab_reg
+//0x2001,00bc bits corespondents to 0x2001,00c0
+
+#define AK88_LCD_SOFT_CTRL          (AK88_VA_DISP + 0xC8)	//software control
+
+#define AK88_LCD_CLOCK_CONF         (AK88_VA_DISP + 0xE8)	//LCD clock configuration
+
+#define STATUS_BUF_EMPTY_ALARM		(0x1UL << 18)
+#define STATUS_ALERT_VALID		(0x1UL << 17)
+#define STATUS_TV_REFRESH_START		(0x1UL << 10)
+#define STATUS_TV_REFRESH_OK		(0x1UL << 9)
+#define STATUS_RGB_EVEN_START		(0x1UL << 8)
+#define STATUS_RGB_EVEN_DONE		(0x1UL << 7)
+#define STATUS_RGB_ODD_START		(0x1UL << 6)
+#define STATUS_RGB_ODD_DONE		(0x1UL << 5)
+#define STATUS_RGB_REFRESH_START	(0x1UL << 4)
+#define STATUS_RGB_REFRESH_OK		(0x1UL << 3)
+#define STATUS_MPU_REFRESH_OK		(0x1UL << 2)
+#define STATUS_MPU_REFRESH_START	(0x1UL << 1)
+#define STATUS_SYS_ERROR		(0x1UL << 0)
+#define SYS_RST_CLK_CTL_OFFSET (0x000c)	//0x0800,000c
+#define SYS_RST_LCD            (1 << 19)
+#define CLOCK_DSA_DISPLAY      (1 <<3 )
+
+void set_ahb_priority(void);
+
+//extern void rgbcontroller_set_interface(LCD_IF_MODE if_mode);
+void bsplcd_set_panel_power(int en /*1=open,0=close */ );	//pullup TFT_VGH_L and TFT_AVDD
+void baselcd_set_panel_backlight(int en /*en=0:close; en=1:open */ );
+void baselcd_reset_controller(void);	//to rest power clock reg bit19
+void baselcd_reset_panel(void);	//lcd panel reset
+
+bool lcd_controller_isrefreshok(void);
+
+void lcd_controller_start_clock(void);
+void lcd_controller_stop_clock(void);
+void lcd_controller_fastdma(void);
+
+void lcd_update(void);
+void lcd_dump_reg(void);
+
+void baselcd_controller_init(int en);
+void lcd_rgb_set_interface(LCD_IF_MODE if_mode);
+bool lcd_fb_init_ram(unsigned long dma_addr, unsigned long xres,
+		     unsigned long yres);
+void lcd_rgb_set_pclk(unsigned long pll1_clk, unsigned lcd_clk);
+void lcd_fb_set_timing(struct anyka_lcdfb_info *sinfo, u32 pll1_freq);
+
+void lcd_rgb_start_refresh(void);
+void lcd_rgb_stop_refresh(void);
+void lcd_interrupt_mask(unsigned bits_result, bool disable);
+void lcd_wait_status(int mask);
+
+void display_init(void);
+bool OEMIPLInit(void);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/lib_uart.h b/arch/arm/mach-ak88/include/mach/lib_uart.h
new file mode 100644
index 00000000000..cdc7a07752e
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/lib_uart.h
@@ -0,0 +1,238 @@
+/**
+ * @file uart.h
+ * @brief UART driver header file
+ *
+ * This file provides UART APIs: UART initialization, write data to UART, read data from
+ * UART, register callback function to handle data from UART, and interrupt handler.
+ * Copyright (C) 2005 Anyka (GuangZhou) Software Technology Co., Ltd.
+ * @author ZouMai
+ * @date 2005-07-14
+ * @version 1.0
+ */
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+#ifndef __ARCH_ARM_MACH_AK88_LIB_UART_H__
+#define __ARCH_ARM_MACH_AK88_LIB_UART_H__
+
//#include "common-regs.h"
+/**
+ * @brief UART port define
+ *	define port name with port number
+ */
+typedef enum {
+	uiUART0 = 0,
+#ifdef CHIP_780X
+	uiUART1,
+	uiUART2,
+#endif
+	uiUART3,
+
+	MAX_UART_NUM		/* UART number */
+} T_UART_ID;
+
+typedef enum {
+	UART_RX_buf_full = 1,
+	UART_INT_timeout,
+	UART_R_err,
+	UART_RX_ov,
+	UART_TX_end,
+	UART_Rx_th_int_sta,
+	UART_Tx_th_int_sta,
+} UART_STATU_REG04;
+
+#define MODULE_UART uiUART0
+
+//#define uart_id2register(uart_id/*0~3*/)  (unsigned int) (AK88_UART_BASE+(unsigned int)(uart_id/*0~3*/)*0x1000)  //0x20026000
+
+static inline char ak880x_uart_get_tx_rdy(unsigned char uart_id)
+{
+	unsigned int status;
+	//status=__raw_readl(uart_id2register(uart_id)+0x04);
+
+	status = __raw_readl(AK88_UART_CFG_REG2(uart_id));
+
+	if (status & (1 << 19))
+		return 1;
+	else
+		return 0;
+}
+
+static inline char ak880x_uart_get_rx_rdy(unsigned char uart_id)
+{
+	unsigned int status;
+	//status=__raw_readl(uart_id2register(uart_id)+0x04);
+	status = __raw_readl(AK88_UART_CFG_REG2(uart_id));
+
+	if (status & (1 << 2))
+		return 1;
+	else if (status & (1 << 1))
+		return 1;
+	else
+		return 0;
+
+	//0x20026004
+	//bit[2]:timeout:1=the receiving timeout occurs.
+	//bit[1]:RX_buf_full:1=the receive buffer is full.
+}
+
+void uart_clock_ctl(unsigned char uart_id, unsigned char enable);
+void uart_pin_ctl(unsigned char uart_id);
+
+unsigned int uart_get_int_status(unsigned char uart_id, unsigned test_status);
+
+void uart_clear_tx_status(unsigned char uart_id);
+void uart_clear_rx_status(unsigned char uart_id);
+unsigned int uart_clear_rx_timeout(unsigned char uart_id);	//return timeout_count
+void uart_clear_rx_buffull(unsigned char uart_id);
+void uart_clear_rx_err(unsigned char uart_id);
+
+void uart_clear_rx_th(unsigned char uart_id);
+void uart_reen_rx_th(unsigned char uart_id);
+
+unsigned char uart_wait_tx_finish(unsigned char uart_id);
+unsigned char uart_get_tx_empty(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+unsigned char uart_wait_rx_timeout(unsigned char uart_id);
+unsigned char uart_get_rx_timeout(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+unsigned char uart_get_rx_buffull(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+
+unsigned int uart_read_timeout(unsigned char uart_id, unsigned char *chr);
+/*when timeout is occur,read all the rxfifo data,return real read number*/
+
+unsigned int uart_read_buffull(unsigned char uart_id, unsigned char *chr);
+/*when RX_buf_full is occur,read all the rxfifo data,return real read number*/
+
+/**
+ * @brief UART callback define
+ *	define UART callback type
+ */
+//typedef T_VOID (*T_fUART_CALLBACK)(T_VOID);
+typedef void (*t_fuart_callback) (void);
+
+/**
+ * @brief Initialize UART
+ *
+ * Initialize UART base on UART ID, baudrate and system clock. If user want to change
+ * baudrate or system clock is changed, user should call this function to initialize
+ * UART again.
+ * Function uart_init() must be called before call any other UART functions
+ * @author ZouMai
+ * @date 2005-07-13
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] unsigned int baud_rate: Baud rate, use UART_BAUD_9600, UART_BAUD_19200 ...
+ * @return unsigned char: Init UART OK or not
+ * @retval AK_TRUE: Successfully initialized UART. AK_FALSE: Initializing UART failed.
+ */
+
+unsigned char uart_init(unsigned char uart_id, unsigned int baud_rate,
+			unsigned int sys_clk);
+
+//unsigned char uart_enable_int(unsigned char uart_id/*0~3*/);
+
+extern void uart_close_interrupt(unsigned char uart_id /*0~3 */ );
+extern void uart_open_interrupt(unsigned char uart_id /*0~3 */ );
+
+void uart_free(unsigned char uart_id);
+
+/**
+ * @brief Write one character to UART base on UART ID
+ *
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] unsigned char chr: The character which will be written to UART
+ * @return unsigned char: Write character OK or not
+ * @retval AK_TRUE: Successfully written character to UART. AK_FALSE: Writing character to UART failed.
+ */
+
+unsigned char uart_write_chr(unsigned char uart_id, unsigned char chr);
+
+/**
+ * @brief Write string to UART base on UART ID
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param unsigned char uart_id: UART ID
+ * @param unsigned char *str: The string which will be written to UART
+ * @return unsigned int: Length of the data which have been written to UART
+ * @retval
+ */
+
+unsigned int uart_write_str(unsigned char uart_id, unsigned char *str);
+
+unsigned char uart_write_buf(unsigned char uart_id /*0~3 */ ,
+			     unsigned char *chr,
+			     unsigned int byte_nbr
+			     /*<60,last 4 bytes(0x3c/0x7c) write 0 */ );
+
+/**
+ * @brief Write string data to UART
+ *
+ * Write data to UART base on UART ID and data length
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-16
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] const unsigned char* data: Constant data to be written to UART, this data needn't be end with '\0'
+ * @param[in] unsigned int data_len: Data length
+ * @return unsigned int
+ * @retval Length of the data which have been written to UART
+ */
+unsigned int uart_write(unsigned char uart_id, const unsigned char *data,
+			unsigned int data_len);
+
+unsigned int uart_write_dma(unsigned char uart_id, const unsigned char *chr,
+			    unsigned int byte_nbr);
+
+/**
+ * @brief Read a character from UART
+ *
+ * This function will not return until get a character from UART
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[out] unsigned char *chr: character for return
+ * @return unsigned char: Got character or not
+ * @retval return AK_TRUE
+ */
+unsigned char uart_read_chr(unsigned char uart_id, unsigned char *chr);
+
+/**
+ * @brief Register a callback function to process UART received data.
+ *
+ * This function words only in the UART interrupt mode.
+ * Caution: The macro definition "__ENABLE_UARTxx_INT__" must be defined. 
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] t_fuart_callback callback_func: Callback function
+ * @return void
+ * @retval
+ */
+
+void uart_set_callback(unsigned char uart_id, t_fuart_callback callback_func);
+
+/**
+ * @brief Register a callback function to process UART received data.
+ *
+ * This function words only in the UART interrupt mode.
+ * Caution: The macro definition "__ENABLE_UARTxx_INT__" must be defined. 
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: uart_id
+ * @param[in] t_fuart_callback callback_func: Callback function
+ * @return void
+ * @retval
+ */
+unsigned char uart_read_chr_asy(unsigned char uart_id, unsigned char *chr);
+
+/*@}*/
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/map.h b/arch/arm/mach-ak88/include/mach/map.h
new file mode 100644
index 00000000000..f24389357f5
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/map.h
@@ -0,0 +1,285 @@
+/* linux/include/asm-arm/arch-s3c2410/map.h
+ *
+ * AK88 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+/* we have a bit of a tight squeeze to fit all our registers from
+ * 0xF00000000 upwards, since we use all of the nGCS space in some
+ * capacity, and also need to fit the S3C2410 registers in as well...
+ * 
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ *
+ * Note, we are trying to remove some of these from the implementation
+ * as they are only useful to certain drivers...
+ */
+#ifndef __ASSEMBLY__
+#define AK88_ADDR(x)		((void __iomem *)0xF0000000 + (x))
+#else
+#define AK88_ADDR(x)		(0xF0000000 + (x))
+#endif
+
+#define AK88_VA_OCROM		AK88_ADDR(0x00000000)
+#define AK88_PA_OCROM		(0x00000000)
+#define AK88_SZ_OCROM		2*SZ_16K	/* 32KB */
+
+#define AK88_VA_SYSCTRL	AK88_ADDR(0x00100000)
+#define AK88_PA_SYSCTRL	(0x08000000)
+#define AK88_SZ_SYSCTRL	SZ_64K	/* 64KB */
+#define AK88_VA_SYS           AK88_ADDR(0x00100000)
+#define AK88_PA_SYS	  	(0x08000000)
+ 
+#define AK88_VA_SUBCTRL	AK88_ADDR(0x00200000)
+#define AK88_PA_SUBCTRL	(0x20000000)
+#define AK88_SZ_SUBCTRL	SZ_1M
+
+#define AK88_VA_L2MEM		AK88_ADDR(0x00300000)
+#define AK88_PA_L2MEM		(0x48000000)
+#define AK88_SZ_L2MEM		SZ_1M
+#define AK88_VA_L2BUF         AK88_ADDR(0x00300000)
+#define	AK88_PA_L2BUF	        (0x48000000)
+
+#define AK88_VA_USB		AK88_ADDR(0x00400000)
+#define AK88_PA_USB		(0x70000000)
+#define AK88_SZ_USB		SZ_1M
+#define AK88_VA_USB	   	AK88_ADDR(0x00400000)
+#define AK88_PA_USB	 	(0x70000000)
+ 
+#define AK88_VA_DISPLAY	(AK88_VA_SUBCTRL + 0x10000)
+#define AK88_PA_DISPLAY	(AK88_PA_SUBCTRL + 0x10000)
+#define AK88_VA_DISP     	(AK88_VA_SUBCTRL + 0x10000)
+#define AK88_PA_DISP	  	(0x20010000)
+
+#define AK88_VA_MMC		(AK88_VA_SUBCTRL + 0x20000)
+#define AK88_PA_MMC		(AK88_PA_SUBCTRL + 0x20000)
+#define AK88_VA_DEV 	        (AK88_VA_SUBCTRL + 0x20000)
+#define AK88_PA_DEV		(0x20020000)
+ 
+#define AK88_VA_SDIO		(AK88_VA_SUBCTRL + 0x21000)
+#define AK88_PA_SDIO		(AK88_PA_SUBCTRL + 0x21000)
+
+#define AK88_VA_2DACC		(AK88_VA_SUBCTRL + 0x22000)
+#define AK88_PA_2DACC		(AK88_PA_SUBCTRL + 0x22000)
+
+#define AK88_VA_SPI0		(AK88_VA_SUBCTRL + 0x24000)
+#define AK88_PA_SPI0		(AK88_PA_SUBCTRL + 0x24000)
+
+#define AK88_VA_SPI1		(AK88_VA_SUBCTRL + 0x25000)
+#define AK88_PA_SPI1		(AK88_PA_SUBCTRL + 0x25000)
+
+#define AK88_VA_UART		(AK88_VA_SUBCTRL + 0x26000)
+#define AK88_PA_UART		(AK88_PA_SUBCTRL + 0x26000)
+
+#define AK88_VA_NFCTRL	(AK88_VA_SUBCTRL + 0x2A000)
+#define AK88_PA_NFCTRL	(AK88_PA_SUBCTRL + 0x2A000)
+
+#define AK88_VA_ECCCTRL	(AK88_VA_SUBCTRL + 0x2B000)
+#define AK88_PA_ECCCTRL	(AK88_PA_SUBCTRL + 0x2B000)
+
+#define AK88_VA_L2CTRL	(AK88_VA_SUBCTRL + 0x2C000)
+#define AK88_PA_L2CTRL	(AK88_PA_SUBCTRL + 0x2C000)
+
+#define AK88_VA_RAMCTRL	(AK88_VA_SUBCTRL + 0x2D000)
+#define AK88_PA_RAMCTRL	(AK88_PA_SUBCTRL + 0x2D000)
+
+#define AK88_VA_DACCTRL	(AK88_VA_SUBCTRL + 0x2E000)
+#define AK88_PA_DACCTRL	(AK88_PA_SUBCTRL + 0x2E000)
+
+#define AK88_VA_CAMIF		(AK88_VA_SUBCTRL + 0x30000)
+#define AK88_PA_CAMIF		(AK88_PA_SUBCTRL + 0x30000)
+#define AK88_VA_CAMER	   	(AK88_VA_SUBCTRL + 0x30000)
+#define AK88_PA_CAMER	  	(0x20030000)
+ 
+#define AK88_VA_HWMM		(AK88_VA_SUBCTRL + 0x40000)
+#define AK88_PA_HWMM		(AK88_PA_SUBCTRL + 0x40000)
+#define AK88_VA_IMAGE	        (AK88_VA_SUBCTRL + 0x40000)
+#define AK88_PA_IMAGE	  	(0x20040000)
+ 
+/* physical addresses of all the chip-select areas */
+
+#define AK88_SDRAM_PA		(0x30000000)
+
+#endif				/* __ASM_ARCH_MAP_H */
+
+///========================================================================////
+
+#ifndef __ARCH_ARM_MACH_AK88_MAP_H
+#define __ARCH_ARM_MACH_AK88_MAP_H
+
+//#include <mach/map-base.h>
+
+#if 0
+#define AK88_VA_SYS	AK88_ADDR(0x00000000)	/* System control */
+#define AK88_VA_MEM	AK88_ADDR(0x00100000)	/* L2 memory control */
+#define AK88_VA_DEV	AK88_ADDR(0x00200000)	/* device controller(s) */
+#define AK88_VA_LCD	AK88_ADDR(0x00300000)	/* system control */
+#define AK88_VA_CAMERA	AK88_ADDR(0x00400000)	/* camera control */
+#define AK88_VA_IMAGE	AK88_ADDR(0x00500000)	/* image control */
+#define AK88_VA_VIDEO	AK88_ADDR(0x00600000)	/* video control */
+#define AK88_VA_AUDIO	AK88_ADDR(0x00700000)	/* audio control */
+#endif
+
+/* This is used for the CPU specific mappings that may be needed, so that
+ * they do not need to directly used AK88_ADDR() and thus make it easier to
+ * modify the space for mapping.
+ */
+//#define AK88_ADDR_CPU(x)    AK88_ADDR(0x00700000 + (x))
+
+#define		AK_FALSE			0
+#define		AK_TRUE				1
+#define 	AK_NULL				((void*)(0))
+#define		AK_EMPTY
+
+#define write_ramb(v,p)	             (*(volatile unsigned char *)(p) = (v))
+#define write_ramw(v,p)	             (*(volatile unsigned short *)(p) = (v))
+#define write_raml(v,p)	             (*(volatile unsigned long  *)(p) = (v))
+
+#define read_ramb(p)	             (*(volatile unsigned char *)(p))
+#define read_ramw(p)	             (*(volatile unsigned short *)(p))
+#define read_raml(p)	             (*(volatile unsigned long *)(p))
+
+#define write_buf(v,p)		     (*(volatile unsigned long  *)(p) = (v))
+#define read_buf(p)		     (*(volatile unsigned long *)(p))
+
+
+/************************** IRQ ************************************/
+
+#define AK88_IRQ_IMR                (AK88_VA_SYS+0x0034)
+#define AK88_IRQ_FMR                (AK88_VA_SYS+0x0038)
+#define AK88_IRQ_STA                (AK88_VA_SYS+0x00CC)
+#define AK88_IRQ_SYS_STA_ENA        (AK88_VA_SYS+0x004C)
+
+/***************************** TIMER ********************************/
+
+#define AK88_TIMER_CON1		   (AK88_VA_SYS+0x0018)
+#define AK88_TIMER_CON2		   (AK88_VA_SYS+0x001C)
+#define AK88_TIMER_CON3		   (AK88_VA_SYS+0x0020)
+#define AK88_TIMER_CON4		   (AK88_VA_SYS+0x0024)
+#define AK88_TIMER_CON5		   (AK88_VA_SYS+0x0028)
+
+#define AK88_TIMER_RBR1		   (AK88_VA_SYS+0x0100)
+#define AK88_TIMER_RBR2		   (AK88_VA_SYS+0x0104)
+#define AK88_TIMER_RBR3		   (AK88_VA_SYS+0x0108)
+#define AK88_TIMER_RBR4		   (AK88_VA_SYS+0x010C)
+#define AK88_TIMER_RBR5		   (AK88_VA_SYS+0x0110)
+
+#define AK88_TIMER_BIT_EN	   (1<<26)
+#define AK88_TIMER_BIT_LD	   (1<<27)	//to load new count value
+#define AK88_TIMER_BIT_CLEAR	   (1<<28)
+#define AK88_TIMER_BIT_STA	   (1<<29)
+
+/************************** CLOCK/POWER ***********************************/
+#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)	//0xF000000C
+//1=disable corresponding pin power clock
+//0=enable  corresponding pin power clock
+
+//bit[15],0 = to enable L2 controller/UART1 working clock
+
+//bit[3], 0 = to enable display controller working clock
+
+/**************************** SHARE PIN CTRL**************************/
+
+#define AK88_SHAREPIN_CTRL    (AK88_VA_SYS+0x0078)	//0xF0000078
+#define AK88_PA_SHAREPIN_CTRL    (AK88_PA_SYS+0x0078)	//0xF0000078
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//all bits default is 0, = Corresponding pin is used as GPIO
+//bit[9] : 1=corresponding are used as {URD1,UTD1}  // gpio[15:14]
+//bit[14]: 1=corresponding are used as {URD4,UTD4} or {SDIO_data[1:0]} // gpio[25:24]
+
+//bit[25]: 1=corresponding are used as {LCD_DATA[15:9]}  //gpio[68:62]
+//bit[26]: 1=corresponding are used as {LCD_DATA[8]}     //gpio[61]
+//bit[27]: 1=corresponding are used as {LCD_DATA[17:16]} //gpio[70:69]
+
+#define AK88_SHAREPIN_CTRL2    (AK88_VA_SYS+0x0074)	//0xF0000074
+#define AK88_PA_SHAREPIN_CTRL2    (AK88_PA_SYS+0x0074)	//0xF0000074
+//bit[2:1] 00:reserved
+//         01 = Corresponding pins are used as those of UART4
+//         10 = Corresponding pins are used as those of UART4
+//         11:reserved
+
+/************************** GPIO ***********************************/
+#define AK88_GPIO_BASE         (AK88_VA_SYS)
+
+#define AK88_GPIO_DIR(n)       (AK88_VA_SYS+0x007C+n*8)	//n=0~3
+#define AK88_PA_GPIO_DIR(n)       (AK88_PA_SYS+0x007C+n*8)	//n=0~3
+
+//0x7C for GPIO[0] ~ GPIO[31]
+//0x84 for GPIO[32] ~ GPIO[63]
+//0x8C for GPIO[64] ~ GPIO[79], bit20:DGPIO[19],bit29:DGPIO[28]
+//0x94 for bit[9:6]: DGPIO[0]~ DGPIO[3]
+
+#define AK88_GPIO_OUT(n)         (AK88_VA_SYS+0x0080+n*8)	//n=0~3
+#define AK88_PA_GPIO_OUT(n)         (AK88_PA_SYS+0x0080+n*8)	//n=0~3
+
+//0x80
+//0x88
+//0x90
+//0x98
+
+#define AK88_GPIO_IN(n)          (AK88_VA_SYS+0x00BC+n*4)	//n=0~3
+#define AK88_PA_GPIO_IN(n)          (AK88_PA_SYS+0x00BC+n*4)	//n=0~3
+
+//0xBC
+//0xC0
+//0xC4
+//0xC8
+
+#define AK88_GPIO_INT_EN1         (AK88_VA_SYS+0x00E0+n*4)	//n=0~3
+#define AK88_PA_GPIO_INT_EN1         (AK88_VA_SYS+0x00E0+n*4)	//n=0~3
+//0xE0
+//0xE4
+//0xE8
+//0xEC
+
+#define AK88_GPIO_INT_POLA1       (AK88_VA_SYS+0x00F0+n*4)	//n=0~3
+#define AK88_PA_GPIO_INT_POLA1       (AK88_VA_SYS+0x00F0+n*4)	//n=0~3
+//0xF0
+//0xF4
+//0xF8
+//0xFC
+
+/*************************** RAM CONTROLER ***************************/
+#define AK88_AHB_PRIORITY                 (AK88_VA_DEV +0xD014)
+
+/************************** L2 CONTROLER **************************/
+
+#define	AK88_L2CTR_DMAADDR	             (AK88_VA_DEV+0xC000+0x00)
+//0x2002c000 -> 0x2002c03c for buffer 0 to 15 (32-bit for each)
+
+#define	AK88_L2CTR_DMACNT                    (AK88_VA_DEV+0xC000+0x40)
+//0x2002c040 -> 0x2002c07c for buffer 0 to 15 (32-bit for each)
+//need operating DMA times,
+//DMA controller can only transfer 64 byes at each time
+
+#define	AK88_L2CTR_DMAREQ		       (AK88_VA_DEV+0xC000+0x80)	//0x2002c080
+#define	AK88_L2CTR_DMAFRAC	               (AK88_VA_DEV+0xC000+0x84)	//0x2002c084
+#define	AK88_L2CTR_COMBUF_CFG	               (AK88_VA_DEV+0xC000+0x88)	//0x2002c088
+#define	AK88_L2CTR_UARTBUF_CFG	       (AK88_VA_DEV+0xC000+0x8C)	//0x2002c08c
+#define AK88_L2CTR_ASSIGN_REG1               (AK88_VA_DEV+0xC000+0x90)	//0x2002c090
+#define AK88_L2CTR_ASSIGN_REG2               (AK88_VA_DEV+0xC000+0x94)	//0x2002c094
+#define AK88_L2CTR_LDMA_CFG                  (AK88_VA_DEV+0xC000+0x98)	//0x2002c098
+#define AK88_L2CTR_STAT_REG1                 (AK88_VA_DEV+0xC000+0xA0)	//0x2002c0A0
+#define AK88_L2CTR_STAT_REG2                 (AK88_VA_DEV+0xC000+0xA8)	//0x2002c0A8
+
+/************************** UART *************************************/
+
+#define AK88_UART_BASE              (AK88_VA_DEV+0x6000)
+#define AK88_UART_CFG_REG1(n)       (AK88_VA_DEV+0x6000+n*0x1000)	//n=0 to 3   // 0x20026000,0x20027000,0x20028000,0x20029000
+#define AK88_UART_CFG_REG2(n)       (AK88_VA_DEV+0x6004+n*0x1000)	//n=0 to 3   // 0x20026004,0x20027004,0x20028004,0x20029004
+#define AK88_UART_DATA_CFG(n)       (AK88_VA_DEV+0x6008+n*0x1000)	//n=0 to 3   // 0x20026008,0x20027008,0x20028008,0x20029008
+#define AK88_UART_THREHOLD(n)       (AK88_VA_DEV+0x600C+n*0x1000)	//n=0 to 3   // 0x2002600C,0x2002700C,0x2002800C,0x2002900C
+#define AK88_UART_RX_DATA(n)        (AK88_VA_DEV+0x6010+n*0x1000)	//n=0 to 3   // 0x20026010,0x20027010,0x20028010,0x20029010
+
+#define UART_BOOT_SET 
+
+
+//#include <mach/ak880x_freq.h>
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/memory.h b/arch/arm/mach-ak88/include/mach/memory.h
new file mode 100644
index 00000000000..24953826f72
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/memory.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/arch-ak880x/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET		UL(0x30000000)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#define __virt_to_bus(x)	(x - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt(x)	(x - PHYS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/nand.h b/arch/arm/mach-ak88/include/mach/nand.h
new file mode 100644
index 00000000000..fe1301d2014
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/nand.h
@@ -0,0 +1,37 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* struct ak880x_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips	 = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name		 = name of set (optional)
+ * nr_map	 = map for low-layer logical to physical chip numbers (option)
+ * partitions	 = mtd partition list
+*/
+
+struct ak880x_nand_set {
+	int nr_chips;
+	int nr_partitions;
+	char *name;
+	int *nr_map;
+	struct mtd_partition *partitions;
+
+	/* timing information for controller */
+	unsigned int cmd_len;
+	unsigned int data_len;
+	unsigned char col_cycle;
+	unsigned char row_cycle;
+};
+
+struct ak880x_platform_nand {
+	int nr_sets;
+	struct ak880x_nand_set *sets;
+
+	void (*select_chip) (struct ak880x_nand_set *, int chip);
+};
diff --git a/arch/arm/mach-ak88/include/mach/pm.h b/arch/arm/mach-ak88/include/mach/pm.h
new file mode 100644
index 00000000000..bba53489ecd
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/pm.h
@@ -0,0 +1,52 @@
+
+/* ak880x_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+
+extern __init int ak880x_pm_init(void);
+
+#else
+
+static inline int ak880x_pm_init(void)
+{
+	return 0;
+}
+#endif
+
+/* configuration for the IRQ mask over sleep */
+
+/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
+
+/* per-cpu sleep functions */
+
+extern void (*pm_cpu_prep) (void);
+extern void (*pm_cpu_sleep) (void);
+
+/* Flags for PM Control */
+
+extern unsigned long ak880x_pm_flags;
+
+/* from sleep.S */
+
+extern int ak880x_cpu_save(unsigned long *saveblk);
+extern void ak880x_cpu_suspend(void);
+extern void ak880x_cpu_resume(void);
+
+extern unsigned long ak880x_sleep_save_phys;
+
+/* sleep save info */
+
+struct sleep_save {
+	void __iomem *reg;
+	unsigned long val;
+};
+
+#define SAVE_ITEM(x) \
+	{ .reg = (x) }
+
+extern void ak880x_pm_do_save(struct sleep_save *ptr, int count);
+extern void ak880x_pm_do_restore(struct sleep_save *ptr, int count);
diff --git a/arch/arm/mach-ak88/include/mach/pwm.h b/arch/arm/mach-ak88/include/mach/pwm.h
new file mode 100644
index 00000000000..2a0463e7a0e
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/pwm.h
@@ -0,0 +1,29 @@
+/*
+ */
+#ifndef _AK88_PWM_H_
+#define _AK88_PWM_H_ __FILE__
+
+#define AK88_PWM0_CTRL	(AK88_VA_SYSCTRL+0x2C)
+#define AK88_PWM1_CTRL	(AK88_VA_SYSCTRL+0x30)
+#define AK88_PWM2_CTRL	(AK88_VA_SYSCTRL+0xB4)
+#define AK88_PWM3_CTRL	(AK88_VA_SYSCTRL+0xB8)
+
+struct ak880x_pwm {
+	unsigned int id;
+	unsigned int gpio;
+	unsigned char __iomem *pwm_ctrl;
+	unsigned long high;
+	unsigned long low;
+};
+
+extern struct ak880x_pwm ak880x_pwm0;
+extern struct ak880x_pwm ak880x_pwm1;
+extern struct ak880x_pwm ak880x_pwm2;
+extern struct ak880x_pwm ak880x_pwm3;
+
+unsigned int ak880x_pwm_init(struct ak880x_pwm *pwm);
+unsigned int ak880x_pwm_set_duty_cycle(struct ak880x_pwm *pwm);
+unsigned int ak880x_pwm_get_duty_cycle(struct ak880x_pwm *pwm);
+unsigned int ak880x_pwm_deinit(struct ak880x_pwm *pwm);
+
+#endif				/* _AK88_PWM_H_ */
diff --git a/arch/arm/mach-ak88/include/mach/regs-adc.h b/arch/arm/mach-ak88/include/mach/regs-adc.h
new file mode 100644
index 00000000000..9a1802981b1
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/regs-adc.h
@@ -0,0 +1,40 @@
+#ifndef	_AK88_ADC_H_
+#define _AK88_ADC_H_ __FILE__
+
+#define AK88_ANALOG_CTRL1	(AK88_VA_SYSCTRL+0x5C)
+#define AD5_sel1		(1 << 29)
+#define BAT_ON			(1 << 28)
+#define RM_DIR			(1 << 27)
+#define PD_TS			(1 << 26)
+
+#define AK88_ADC1_CTRL	(AK88_VA_SYSCTRL+0x60)
+
+#define AK88_ANALOG_CTRL2	(AK88_VA_SYSCTRL+0x64)
+#define ADC1_en			(1 << 8)
+#define bat_en			(1 << 9)
+#define TS_en			(1 << 10)
+#define AD5_sel			(1 << 11)
+#define TS_threshold08		(0x08 << 17)
+#define TS_threshold1023	(0x3ff << 17)
+#define TS_ctrl255		(0xff << 0)
+#define TS_ctrl05		(0x05 << 0)
+
+#define AK88_ADC1_STATUS	(AK88_VA_SYSCTRL+0x70)
+#define YN_int			(1 << 23)
+#define YP_int			(1 << 22)
+#define XN_int			(1 << 21)
+#define XP_int			(1 << 20)
+
+#define AK88_CLK_DIV2		(AK88_VA_SYSCTRL+0x08)
+#define ADC1_pd			(1 << 29)
+#define ADC1_rst		(1 << 22)
+#define ADC1_CLK_en		(1 << 3)
+#define ADC1_DIV0		(0 << 0)	/* ADC CLOCK=12M/(ADC1_DIV+1) */
+#define ADC1_DIV1		(1 << 0)
+#define ADC1_DIV2		(2 << 0)
+#define ADC1_DIV3		(3 << 0)
+
+#define AK88_X_COORDINATE	(AK88_VA_SYSCTRL+0x68)
+#define AK88_Y_COORDINATE	(AK88_VA_SYSCTRL+0x6C)
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/reset.h b/arch/arm/mach-ak88/include/mach/reset.h
new file mode 100644
index 00000000000..e57c81a42d6
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/reset.h
@@ -0,0 +1,9 @@
+/* include/asm/arch/reset.h
+ *
+ */
+#ifndef _AK88_RESET_H_
+#define _AK88_RESET_H_	__FILE__
+
+extern void (*ak880x_shutdown_machine) (void);
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/spi.h b/arch/arm/mach-ak88/include/mach/spi.h
new file mode 100644
index 00000000000..1046d23b429
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/spi.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-ak880x/spi.h
+ */
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+struct ak880x_spi_info {
+	unsigned long pin_cs;
+	unsigned long board_size;
+	struct spi_board_info *board_info;
+
+	void (*set_cs) (struct ak880x_spi_info, int cs, int pol);
+};
+
+#define AK88_SPICON		(0x00)
+#define AK88_SPICON_CLKDIV	(0x7F<<8)
+#define AK88_SPICON_EN	(1<<6)
+#define AK88_SPICON_CS	(1<<5)
+#define AK88_SPICON_MS	(1<<4)
+#define AK88_SPICON_CPHA	(1<<3)
+#define AK88_SPICON_CPOL	(1<<2)
+#define AK88_SPICON_ARRM	(1<<1)
+#define AK88_SPICON_TGDM	(1<<0)
+
+#define AK88_SPISTA		(0x04)
+#define AK88_SPISTA_TIMEOUT	(1<<10)
+#define AK88_SPISTA_MPROC	(1<<9)
+#define AK88_SPISTA_TRANSF	(1<<8)
+#define AK88_SPISTA_RXOVER	(1<<7)
+#define AK88_SPISTA_RXHFULL	(1<<6)
+#define AK88_SPISTA_RXFULL	(1<<5)
+#define AK88_SPISTA_RXEMP	(1<<4)
+#define AK88_SPISTA_TXUNDER	(1<<3)
+#define AK88_SPISTA_TXHEMP	(1<<2)
+#define AK88_SPISTA_TXFULL	(1<<1)
+#define AK88_SPISTA_TXEMP	(1<<0)
+
+#define AK88_SPIINT		(0x08)
+#define AK88_SPIINT_TIMEOUT	(1<<10)
+#define AK88_SPIINT_MPROC	(1<<9)
+#define AK88_SPIINT_TRANSF	(1<<8)
+#define AK88_SPIINT_RXOVER	(1<<7)
+#define AK88_SPIINT_RXHFULL	(1<<6)
+#define AK88_SPIINT_RXFULL	(1<<5)
+#define AK88_SPIINT_RXEMP	(1<<4)
+#define AK88_SPIINT_TXUNDER	(1<<3)
+#define AK88_SPIINT_TXHEMP	(1<<2)
+#define AK88_SPIINT_TXFULL	(1<<1)
+#define AK88_SPIINT_TXEMP	(1<<0)
+
+#define AK88_SPICNT		(0x0C)
+
+#define AK88_SPIEXTX		(0x10)
+
+#define AK88_SPIEXRX		(0x14)
+
+#define AK88_SPIOUT		(0x18)
+
+#define AK88_SPIIN		(0x1C)
+
+#endif
diff --git a/arch/arm/mach-ak88/include/mach/system-reset.h b/arch/arm/mach-ak88/include/mach/system-reset.h
new file mode 100644
index 00000000000..faf0ae2df4e
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/system-reset.h
@@ -0,0 +1,42 @@
+/* arch/arm/mach-ak880x/include/mach/system-reset.h
+ * from arch/arm/mach-s3c2410/include/mach/system-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * AK88 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+//#include <mach/hardware.h>
+//#include <mach/watchdog-reset.h>
+
+extern void (*ak880x_reset_hook) (void);
+
+static inline void arch_wdt_reset(void)
+{
+	//struct clk *wdtclk;
+
+	printk("arch_reset: attempting watchdog reset\n");
+
+	/* delay to allow the serial port to show the message */
+	mdelay(50);
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	if (mode == 's') {
+		cpu_reset(0);
+	}
+
+	if (ak880x_reset_hook)
+		ak880x_reset_hook();
+
+	arch_wdt_reset();
+
+	/* we'll take a jump through zero as a poor second */
+	cpu_reset(0);
+}
diff --git a/arch/arm/mach-ak88/include/mach/system.h b/arch/arm/mach-ak88/include/mach/system.h
new file mode 100644
index 00000000000..313dd2eeb3a
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/system.h
@@ -0,0 +1,55 @@
+/* linux/include/asm-arm/arch-ak880x/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+//#include <mach/hardware.h>
+//#include <mach/io.h>
+//#include <linux/err.h>
+
+#include <asm/io.h>
+
+void (*ak880x_shutdown_machine) (void);
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	/* TODO:
+	 * 1, check power key.
+	 * 2. check charger
+	 * --------------------
+	 *    set mode to 's', and reboot system.
+	 *
+	 * 3. check rtc wakeup
+	 * --------------------
+	 *   clear wakeup status and shutdown system.
+	 */
+
+	if (mode == 'h') {	/* Power off system */
+		printk("%s: poweroff system\n", __FUNCTION__);
+
+		if (ak880x_shutdown_machine)
+			ak880x_shutdown_machine();
+
+		mdelay(1000);
+
+	} else {		/* Reset system use watchdog timer */
+
+		/* TODO: Add watchdog timer setup to reboot */
+
+		/* wait for reset to assert... */
+		mdelay(5000);
+		printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+		/* we'll take a jump through zero as a poor second */
+		cpu_reset(0);
+	}
+}
+
+//#include <mach/system-reset.h>
diff --git a/arch/arm/mach-ak88/include/mach/timex.h b/arch/arm/mach-ak88/include/mach/timex.h
new file mode 100644
index 00000000000..452cf9adb6c
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/timex.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-ak880x/include/mach/timex.h
+ *
+ * AK88 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif				/* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ak88/include/mach/ts.h b/arch/arm/mach-ak88/include/mach/ts.h
new file mode 100644
index 00000000000..2cc242ac424
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/ts.h
@@ -0,0 +1,11 @@
+#ifndef __AK88_TS_H_
+#define __AK88_TS_H_ __FILE__
+
+struct ak880x_ts_mach_info {
+	unsigned int irq;	/* use a macro convert gpio pin */
+	unsigned int irqpin;
+	unsigned int sample_rate;
+	unsigned int wait_time;
+};
+
+#endif				/* __AK88_TS_H_ */
diff --git a/arch/arm/mach-ak88/include/mach/uncompress.h b/arch/arm/mach-ak88/include/mach/uncompress.h
new file mode 100644
index 00000000000..8b76a80fe3f
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/uncompress.h
@@ -0,0 +1,286 @@
+/*
+ * linux/arch/arm/mach-ak8801/include/mach/uncompress.h
+ *
+ */
+
+#define CONFIG_AK88_LL_DEBUG_UART3
+#define BAUD_RATE  115200
+
+#define REG32(addr)             (*(volatile unsigned long*)(addr))
+
+/* L2 buffer register */
+#define L2BUF_CONF2_REG         REG32(0x2002c08c)
+
+#define UART0_TXBUF_CLR_BIT     16
+#define UART0_RXBUF_CLR_BIT     17
+#define UART1_TXBUF_CLR_BIT     18
+#define UART1_RXBUF_CLR_BIT     19
+#define UART2_TXBUF_CLR_BIT     20
+#define UART2_RXBUF_CLR_BIT     21
+#define UART3_TXBUF_CLR_BIT     22
+#define UART3_RXBUF_CLR_BIT     23
+
+/* L2 buffer address */
+#define L2BUF(addr)             (*(volatile unsigned long*)(addr))
+
+#define UART0_TXBUF_ADDR        0x48001000
+#define UART0_RXBUF_ADDR        0x48001080
+#define UART1_TXBUF_ADDR        0x48001100
+#define UART1_RXBUF_ADDR        0x48001180
+#define UART2_TXBUF_ADDR        0x48001200
+#define UART2_RXBUF_ADDR        0x48001280
+#define UART3_TXBUF_ADDR        0x48001300
+#define UART3_RXBUF_ADDR        0x48001380
+
+#define ENDDING_OFFSET1         60
+#define ENDDING_OFFSET2         124
+
+/* Shared pin control reigsters */
+#define SRDPIN_CTRL1_REG        REG32(0x08000078)
+#define SRDPIN_CTRL2_REG        REG32(0x08000074)
+
+#define SRDPIN_UART0_RXTX_BIT   9
+#define SRDPIN_UART1_RXTX_BIT   10
+#define SRDPIN_UART1_RTSCTS_BIT 11
+#define SRDPIN_UART2_RXTX_BIT   12
+#define SRDPIN_UART2_RTSCTS_BIT 13
+#define SRDPIN_UART3_RXTX_BIT   14
+#define SRDPIN_UART3_RTSCTS_BIT 15
+
+#define SRDPIN_UART3_SDIO_BIT   1
+
+/* Pin configure registers */
+#define PPU_PPD1_REG            REG32(0x0800009c)
+/* pullup control: 0 - pulldown; 1 - pullup */
+#define CTS3_PU_BIT             27
+#define RTS3_PU_BIT             26
+#define URD3_PU_BIT             25
+#define UTD3_PU_BIT             24
+#define CTS2_PU_BIT             23
+#define RTS2_PU_BIT             22
+#define URD2_PU_BIT             21
+#define UTD2_PU_BIT             20
+#define CTS1_PU_BIT             19
+#define RTS1_PU_BIT             18
+#define URD1_PU_BIT             17
+#define UTD1_PU_BIT             16
+#define URD0_PU_BIT             15
+#define UTD0_PU_BIT             14
+
+#define GPIO_CTRL1_REG          REG32(0x080000d4)
+/* pullup/pulldown enable */
+#define CTS3_PE_BIT             24
+#define RTS3_PE_BIT             25
+#define URD3_PE_BIT             22
+#define UTD3_PE_BIT             23
+#define CTS2_PE_BIT             20
+#define RTS2_PE_BIT             21
+#define URD2_PE_BIT             18
+#define UTD2_PE_BIT             19
+#define CTS1_PE_BIT             16
+#define RTS1_PE_BIT             17
+#define URD1_PE_BIT             14
+#define UTD1_PE_BIT             15
+/* input enable */
+#define CTS3_IE_BIT             12
+#define RTS3_IE_BIT             13
+#define URD3_IE_BIT             10
+#define UTD3_IE_BIT             11
+#define CTS2_IE_BIT             8
+#define RTS2_IE_BIT             9
+#define URD2_IE_BIT             6
+#define UTD2_IE_BIT             7
+#define CTS1_IE_BIT             4
+#define RTS1_IE_BIT             5
+#define URD1_IE_BIT             2
+#define UTD1_IE_BIT             3
+
+/* Clock control register */
+#define CLK_CTRL_REG            REG32(0x0800000c)
+
+#define UART0_ENABLE_BIT        15
+#define UART1_ENABLE_BIT        2
+#define UART2_ENABLE_BIT        8
+#define UART3_ENABLE_BIT        8
+
+/* Clock divider register */
+#define CLK_DIV_REG             REG32(0x08000004)
+
+/* UART registers */
+#define UART0_BASE_ADDR_PHYS	0x20026000
+#define UART1_BASE_ADDR_PHYS	0x20027000
+#define UART2_BASE_ADDR_PHYS	0x20028000
+#define UART3_BASE_ADDR_PHYS	0x20029000
+
+#define UART0_CONF1_REG		REG32(UART0_BASE_ADDR_PHYS + 0x0)
+#define UART0_CONF2_REG		REG32(UART0_BASE_ADDR_PHYS + 0x4)
+#define UART0_DATA_CONF_REG	REG32(UART0_BASE_ADDR_PHYS + 0x8)
+#define UART0_BUF_THRE_REG	REG32(UART0_BASE_ADDR_PHYS + 0xc)
+
+#define UART1_CONF1_REG		REG32(UART1_BASE_ADDR_PHYS + 0x0)
+#define UART1_CONF2_REG		REG32(UART1_BASE_ADDR_PHYS + 0x4)
+#define UART1_DATA_CONF_REG	REG32(UART1_BASE_ADDR_PHYS + 0x8)
+#define UART1_BUF_THRE_REG	REG32(UART1_BASE_ADDR_PHYS + 0xc)
+
+#define UART2_CONF1_REG		REG32(UART2_BASE_ADDR_PHYS + 0x0)
+#define UART2_CONF2_REG		REG32(UART2_BASE_ADDR_PHYS + 0x4)
+#define UART2_DATA_CONF_REG	REG32(UART2_BASE_ADDR_PHYS + 0x8)
+#define UART2_BUF_THRE_REG	REG32(UART2_BASE_ADDR_PHYS + 0xc)
+
+#define UART3_CONF1_REG		REG32(UART3_BASE_ADDR_PHYS + 0x0)
+#define UART3_CONF2_REG		REG32(UART3_BASE_ADDR_PHYS + 0x4)
+#define UART3_DATA_CONF_REG	REG32(UART3_BASE_ADDR_PHYS + 0x8)
+#define UART3_BUF_THRE_REG	REG32(UART3_BASE_ADDR_PHYS + 0xc)
+
+/* bit define of UARTx_CONF1_REG */
+#define BAUD_RATE_DIV_BIT       0
+#define CTS_SEL_BIT             18
+#define RTS_SEL_BIT             19
+#define PORT_ENABLE_BIT         21
+#define TX_STATUS_CLR_BIT       28
+#define RX_STATUS_CLR_BIT       29
+
+/* bit define of UARTx_CONF2_REG */
+#define TX_COUNT_BIT            4
+#define TX_COUNT_VALID_BIT      16
+#define TX_END_BIT              19
+#define TX_END_MASK             (1 << TX_END_BIT)
+
+
+#if defined CONFIG_AK88_LL_DEBUG_UART3
+#define UART_TXBUF_CLR_BIT      UART3_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART3_RXTX_BIT
+#define URD_PU_BIT              URD3_PU_BIT
+#define UTD_PU_BIT              UTD3_PU_BIT
+#define URD_PE_BIT              URD3_PE_BIT
+#define UTD_PE_BIT              UTD3_PE_BIT
+#define URD_IE_BIT              URD3_IE_BIT
+#define UTD_IE_BIT              UTD3_IE_BIT
+#define UART_ENABLE_BIT         UART3_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART3_TXBUF_ADDR
+#define UART_CONF1_REG          UART3_CONF1_REG
+#define UART_CONF2_REG          UART3_CONF2_REG
+#define UART_DATA_CONF_REG      UART3_DATA_CONF_REG
+#elif defined CONFIG_AK88_LL_DEBUG_UART2
+#define UART_TXBUF_CLR_BIT      UART2_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART2_RXTX_BIT
+#define URD_PU_BIT              URD2_PU_BIT
+#define UTD_PU_BIT              UTD2_PU_BIT
+#define URD_PE_BIT              URD2_PE_BIT
+#define UTD_PE_BIT              UTD2_PE_BIT
+#define URD_IE_BIT              URD2_IE_BIT
+#define UTD_IE_BIT              UTD2_IE_BIT
+#define UART_ENABLE_BIT         UART2_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART2_TXBUF_ADDR
+#define UART_CONF1_REG          UART2_CONF1_REG
+#define UART_CONF2_REG          UART2_CONF2_REG
+#define UART_DATA_CONF_REG      UART2_DATA_CONF_REG
+#elif defined CONFIG_AK88_LL_DEBUG_UART1
+#define UART_TXBUF_CLR_BIT      UART1_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART1_RXTX_BIT
+#define URD_PU_BIT              URD1_PU_BIT
+#define UTD_PU_BIT              UTD1_PU_BIT
+#define URD_PE_BIT              URD1_PE_BIT
+#define UTD_PE_BIT              UTD1_PE_BIT
+#define URD_IE_BIT              URD1_IE_BIT
+#define UTD_IE_BIT              UTD1_IE_BIT
+#define UART_ENABLE_BIT         UART1_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART1_TXBUF_ADDR
+#define UART_CONF1_REG          UART1_CONF1_REG
+#define UART_CONF2_REG          UART1_CONF2_REG
+#define UART_DATA_CONF_REG      UART1_DATA_CONF_REG
+#else  /* default use UART0 */
+#define UART_TXBUF_CLR_BIT      UART0_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART0_RXTX_BIT
+#define URD_PU_BIT              URD0_PU_BIT
+#define UTD_PU_BIT              UTD0_PU_BIT
+#define UART_ENABLE_BIT         UART0_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART0_TXBUF_ADDR
+#define UART_CONF1_REG          UART0_CONF1_REG
+#define UART_CONF2_REG          UART0_CONF2_REG
+#define UART_DATA_CONF_REG      UART0_DATA_CONF_REG
+#endif
+
+static inline void flush(void)
+{
+}
+
+static unsigned int __uidiv__(unsigned int num, unsigned int den)
+{
+	unsigned int i;
+
+	if (den == 1)
+		return num;
+
+	i = 1;
+	while (den * i < num)
+		i++;
+
+	return i-1;
+}
+
+static void uart_init(void)
+{
+	int pll1_clk, asic_clk, clk_div;
+
+	/* Enable UART port */
+	CLK_CTRL_REG &= ~(0x1 << UART_ENABLE_BIT);
+
+	/* Set shared pins to UART */
+	SRDPIN_CTRL1_REG  |= (0x1 << SRDPIN_UART_RXTX_BIT);
+#ifdef CONFIG_AK88_LL_DEBUG_UART3
+	SRDPIN_CTRL2_REG  |= (0x1 << SRDPIN_UART3_SDIO_BIT);
+#endif
+
+	/* Set pin config */
+	PPU_PPD1_REG |= (0x1 << URD_PU_BIT) | (0x1 << UTD_PU_BIT);
+#ifndef CONFIG_AK88_LL_DEBUG_UART0
+	GPIO_CTRL1_REG |= (0x1 << URD_PE_BIT) | (0x1 << UTD_PE_BIT);
+	GPIO_CTRL1_REG &= ~(0x1 << UTD_IE_BIT);
+	GPIO_CTRL1_REG |= (0x1 << URD_IE_BIT);
+#endif
+
+	/* Set baud rate */
+	pll1_clk = __uidiv__(4 * ((CLK_DIV_REG&0x3f) + 45), (((CLK_DIV_REG>>17)&0xf) + 1));
+	asic_clk = (pll1_clk >> ((CLK_DIV_REG>>6)&0x7)) * 1000 * 1000;
+	clk_div = __uidiv__(asic_clk, BAUD_RATE) - 1;
+	UART_CONF1_REG = (0x1 << TX_STATUS_CLR_BIT)
+		| (0x1 << RX_STATUS_CLR_BIT)
+		| clk_div;
+
+#ifndef CONFIG_AK88_LL_DEBUG_UART0
+	/* Disable flow control */
+	UART_CONF1_REG |= (0x1 << CTS_SEL_BIT) | (0x1 << RTS_SEL_BIT);
+#endif
+
+	/* go */
+	UART_CONF1_REG |= (0x1 << PORT_ENABLE_BIT);
+}
+
+/* print a char to uart */
+static void putc(char c)
+{
+	/* Clear uart tx buffer */
+	L2BUF_CONF2_REG   |= (0x1 << UART_TXBUF_CLR_BIT);
+	/* write char to uart buffer */
+	L2BUF(UART_TXBUF_ADDR) = (unsigned long)c;
+	L2BUF(UART_TXBUF_ADDR+ENDDING_OFFSET1) = (unsigned long)'\0';
+	/* Clear uart tx count register */
+	UART_CONF1_REG |= (0x1 << TX_STATUS_CLR_BIT);
+	/* Send buffer */
+	UART_CONF2_REG |= (1 << TX_COUNT_BIT) | (0x1 << TX_COUNT_VALID_BIT);
+
+	/* Wait for finish */
+	while((UART_CONF2_REG & TX_END_MASK) == 0) {
+	}
+}
+
+static inline void arch_decomp_setup(void)
+{
+	uart_init();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ak88/include/mach/vmalloc.h b/arch/arm/mach-ak88/include/mach/vmalloc.h
new file mode 100644
index 00000000000..68dc357caef
--- /dev/null
+++ b/arch/arm/mach-ak88/include/mach/vmalloc.h
@@ -0,0 +1,15 @@
+/* linux/arch/arm/mach-ak880x/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * ANYKA 8801 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END		(0xE0000000)
+
+#endif				/* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-ak88/irq.c b/arch/arm/mach-ak88/irq.c
new file mode 100644
index 00000000000..ff33c66eb9f
--- /dev/null
+++ b/arch/arm/mach-ak88/irq.c
@@ -0,0 +1,444 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+#include "cpu.h"
+#include "irq.h"
+
+#define AK88_CLKDIV1		(AK88_VA_SYSCTRL + 0x04)
+#define AK88_IRQ_MASK		(AK88_VA_SYSCTRL + 0x34)
+#define AK88_FIQ_MASK		(AK88_VA_SYSCTRL + 0x38)
+#define AK88_INT_STATUS	(AK88_VA_SYSCTRL + 0xCC)
+#define	AK88_SYSCTRL_INT_CTRL	(AK88_VA_SYSCTRL + 0x4C)
+
+#define AK88_GPIO_INT_CTRL0	(AK88_VA_SYSCTRL + 0xE0)
+#define AK88_GPIO_INT_CTRL1	(AK88_VA_SYSCTRL + 0xE4)
+#define AK88_GPIO_INT_CTRL2	(AK88_VA_SYSCTRL + 0xE8)
+#define AK88_GPIO_INT_CTRL3	(AK88_VA_SYSCTRL + 0xEC)
+
+#define AK88_GPIO_INPUT0	(AK88_VA_SYSCTRL + 0xBC)
+#define AK88_GPIO_INPUT1	(AK88_VA_SYSCTRL + 0xC0)
+#define AK88_GPIO_INPUT2	(AK88_VA_SYSCTRL + 0xC4)
+#define AK88_GPIO_INPUT3	(AK88_VA_SYSCTRL + 0xC8)
+
+#define AK88_GPIO_INTP0	(AK88_VA_SYSCTRL + 0xF0)
+#define AK88_GPIO_INTP1	(AK88_VA_SYSCTRL + 0xF4)
+#define AK88_GPIO_INTP2	(AK88_VA_SYSCTRL + 0xF8)
+#define AK88_GPIO_INTP3	(AK88_VA_SYSCTRL + 0xFC)
+
+#define AK88_WGPIO_POLARITY	(AK88_VA_SYSCTRL + 0x3C)
+#define AK88_WGPIO_CLEAR	(AK88_VA_SYSCTRL + 0x40)
+#define AK88_WGPIO_ENABLE	(AK88_VA_SYSCTRL + 0x44)
+#define AK88_WGPIO_STATUS	(AK88_VA_SYSCTRL + 0x48)
+
+#define AK88_L2MEM_IRQ_ENABLE	(AK88_VA_L2CTRL + 0x9C)
+
+/*
+ * Disable interrupt number "irq"
+ */
+static void ak880x_mask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	unsigned long bitval = (1UL << irq);
+
+	mask = __raw_readl(AK88_IRQ_MASK);
+
+	__raw_writel(mask & ~bitval, AK88_IRQ_MASK);
+}
+
+/*
+ * Enable interrupt number "irq"
+ */
+static void ak880x_unmask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	unsigned long bitval = (1UL << irq);
+
+	mask = __raw_readl(AK88_IRQ_MASK);
+
+	__raw_writel(mask | bitval, AK88_IRQ_MASK);
+	#if 0
+	if(irq==IRQ_UART0)
+		printk("ak880x_unmask_irq,irq=%d\n",irq);
+	if(irq==IRQ_UART3)
+		printk("ak880x_unmask_irq,irq=%d\n",irq);
+	#endif	
+
+}
+
+static struct irq_chip ak880x_irq_chip = {
+	.name = "ak7801",
+	.mask_ack = ak880x_mask_irq,
+	.mask = ak880x_mask_irq,
+	.unmask = ak880x_unmask_irq,
+};
+
+static void sysctrl_mask_irq(unsigned int irq)
+{
+	unsigned long sysctrl;
+	unsigned long bitval = ~(1 << (irq - IRQ_TOUCHPANEL));
+
+	sysctrl = __raw_readl(AK88_SYSCTRL_INT_CTRL);
+
+	__raw_writel(sysctrl & bitval, AK88_SYSCTRL_INT_CTRL);
+}
+
+static void sysctrl_unmask_irq(unsigned int irq)
+{
+	unsigned long sysctrl;
+	unsigned long bitval = (1 << (irq - IRQ_TOUCHPANEL));
+
+	sysctrl = __raw_readl(AK88_SYSCTRL_INT_CTRL);
+
+	__raw_writel(sysctrl | bitval, AK88_SYSCTRL_INT_CTRL);
+}
+
+static int sysctrl_set_wake(unsigned int irq, unsigned int on)
+{
+	unsigned long clkdiv1;
+
+	if (irq == IRQ_RTC_ALARM) {
+
+		clkdiv1 = __raw_readl(AK88_CLKDIV1);
+
+		if (on == 1)
+			clkdiv1 |= (1 << 16);
+		else
+			clkdiv1 &= ~(1 << 16);
+
+		__raw_writel(clkdiv1, AK88_CLKDIV1);
+
+		return 0;
+	}
+
+	return 0;
+}
+
+static struct irq_chip ak880x_sysctrl_chip = {
+	.name = "ak-sysctrl",
+	.mask_ack = sysctrl_mask_irq,
+	.mask = sysctrl_mask_irq,
+	.unmask = sysctrl_unmask_irq,
+	.set_wake = sysctrl_set_wake,
+};
+
+static void ak880x_sysctrl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned long regval;
+	unsigned long intpnd;
+	unsigned int offset = 0;
+
+	regval = __raw_readl(AK88_SYSCTRL_INT_CTRL);
+
+	intpnd = (regval & 0x7FF) & ((regval & 0x7FF0000) >> 16);
+
+	offset = 0;
+	for (offset = 0; intpnd && offset < 32; offset++) {
+
+		if (intpnd & (1 << offset))
+			intpnd &= ~(1 << offset);
+		else
+			continue;
+
+		irq = AK88_SYSCTRL_IRQ(offset);
+
+		desc_handle_irq(irq, irq_desc + irq);
+	}
+}
+
+static void ak880x_gpioirq_mask(unsigned int irq)
+{
+	void __iomem *gpio_ctrl = AK88_GPIO_INT_CTRL0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+	regval &= ~(1 << (irq % 32));
+
+	__raw_writel(regval, gpio_ctrl);
+}
+
+static int ak880x_gpioirq_set_type(unsigned int irq, unsigned int type)
+{
+	void __iomem *gpio_ctrl = AK88_GPIO_INTP0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+
+	if (type == IRQ_TYPE_LEVEL_HIGH)
+		regval &= ~(1 << (irq % 32));
+	else if (type == IRQ_TYPE_LEVEL_LOW)
+		regval |= (1 << (irq % 32));
+	else {
+		printk("Not support irq type\n");
+		return -1;
+	}
+
+	/* printk("0x%x, %d\n", gpio_ctrl, irq%32); */
+
+	__raw_writel(regval, gpio_ctrl);
+
+	return 0;
+}
+
+static void ak880x_gpioirq_unmask(unsigned int irq)
+{
+	void __iomem *gpio_ctrl = AK88_GPIO_INT_CTRL0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+	regval |= (1 << (irq % 32));
+
+	/* printk("0x%x, %d\n", gpio_ctrl, irq%32); */
+
+	__raw_writel(regval, gpio_ctrl);
+}
+
+static int ak880x_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+	unsigned long wgpio_enable;
+
+	wgpio_enable = __raw_readl(AK88_WGPIO_ENABLE);
+
+	if (irq >= IRQ_GPIO_5 && irq <= IRQ_GPIO_7)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_5));
+
+	else if (irq >= IRQ_GPIO_10 && irq <= IRQ_GPIO_13)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_10 + 3));
+
+	else if (irq >= IRQ_GPIO_16 && irq <= IRQ_GPIO_19)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_16 + 7));
+
+	else if (irq >= IRQ_GPIO_24 && irq <= IRQ_GPIO_27)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_24 + 11));
+
+	else if (irq >= IRQ_GPIO_72 && irq <= IRQ_GPIO_75)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_72 + 15));
+
+	else if (irq >= IRQ_DGPIO_2 && irq <= IRQ_DGPIO_5)
+		wgpio_enable |= (1 << (irq - IRQ_DGPIO_2 + 19));
+
+	else if (irq == IRQ_DGPIO_19)
+		wgpio_enable |= (1 << 23);
+
+	else if (irq >= IRQ_DGPIO_7 && irq <= IRQ_DGPIO_14)
+		wgpio_enable |= (1 << (irq - IRQ_DGPIO_7 + 24));
+	else {
+		printk("Not WGPIO IRQ: %d\n", irq);
+		return -1;
+	}
+
+	__raw_writel(wgpio_enable, AK88_WGPIO_ENABLE);
+
+	return 0;
+}
+
+static struct irq_chip ak880x_gpioirq_chip = {
+	.name = "gpio_irq",
+	.mask_ack = ak880x_gpioirq_mask,
+	.mask = ak880x_gpioirq_mask,
+	.set_type = ak880x_gpioirq_set_type,
+	.unmask = ak880x_gpioirq_unmask,
+	.set_wake = ak880x_gpio_irq_set_wake,
+};
+
+static void ak880x_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned long enabled_irq;
+	unsigned int i;
+	unsigned int off;
+
+	/* printk("Enterring %s\n", __FUNCTION__); */
+
+#if	defined(CONFIG_ARCH_AK7801)
+
+	for (i = 0; i < 3; i++) {
+		enabled_irq = __raw_readl(AK88_GPIO_INT_CTRL0 + i * 4);
+
+		while (enabled_irq) {
+			off = __ffs(enabled_irq);
+			enabled_irq &= ~(1 << off);
+			if (test_bit(off, AK88_GPIO_INTP0 + i * 4) !=
+			    test_bit(off, AK88_GPIO_INPUT0 + i * 4)) {
+				irq = IRQ_GPIO_0 + i * 32 + off;
+				desc_handle_irq(irq, irq_desc + irq);
+				/* printk("irq: grp %d, %d\n", i, off); */
+			}
+		}
+	}
+
+	/* Group 3 */
+	{
+		enabled_irq = __raw_readl(AK88_GPIO_INT_CTRL3);
+
+		while (enabled_irq) {
+
+			off = __ffs(enabled_irq);
+			enabled_irq &= ~(1 << off);
+
+			if (off < 3) {
+
+				if (test_bit(off, AK88_GPIO_INTP3) !=
+				    test_bit(off, AK88_GPIO_INPUT3)) {
+					irq = IRQ_DGPIO_31 + off;
+					desc_handle_irq(irq, irq_desc + irq);
+				}
+
+			} else if (off < 6) {
+
+				printk("Can't handle irq: %d\n",
+				       IRQ_DGPIO_31 + off);
+
+			} else {
+
+				if (test_bit(off, AK88_GPIO_INTP3) !=
+				    test_bit(off - 3, AK88_GPIO_INPUT3)) {
+					irq = IRQ_DGPIO_31 + off;
+					desc_handle_irq(irq, irq_desc + irq);
+				}
+			}
+		}
+	}
+
+#elif	defined(CONFIG_ARCH_AK88)
+	for (i = 0; i < 4; i++) {
+		enabled_irq = __raw_readl(AK88_GPIO_INT_CTRL0 + i * 4);
+
+		while (enabled_irq) {
+			off = __ffs(enabled_irq);
+			enabled_irq &= ~(1 << off);
+			if (test_bit(off, AK88_GPIO_INTP0 + i * 4) !=
+			    test_bit(off, AK88_GPIO_INPUT0 + i * 4)) {
+				irq = IRQ_GPIO_0 + i * 32 + off;
+				desc_handle_irq(irq, irq_desc + irq);
+				/* printk("irq: grp %d, %d\n", i, off); */
+			}
+		}
+	}
+#else
+#error "Unsupported CPU. please check."
+#endif
+
+	/* printk("Leaving %s\n", __FUNCTION__); */
+}
+
+static void ak880x_l2mem_irq_mask(unsigned int irq)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(AK88_L2MEM_IRQ_ENABLE);
+	regval &= ~(1 << (irq - IRQ_L2_FRAC_DMA));
+	__raw_writel(regval, AK88_L2MEM_IRQ_ENABLE);
+}
+
+static void ak880x_l2mem_irq_unmask(unsigned int irq)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(AK88_L2MEM_IRQ_ENABLE);
+	regval |= (1 << (irq - IRQ_L2_FRAC_DMA));
+	__raw_writel(regval, AK88_L2MEM_IRQ_ENABLE);
+}
+
+static struct irq_chip ak880x_l2mem_irq_chip = {
+	.name = "l2mem_irq",
+	.mask_ack = ak880x_l2mem_irq_mask,
+	.mask = ak880x_l2mem_irq_mask,
+	.unmask = ak880x_l2mem_irq_unmask,
+};
+
+static void ak880x_l2mem_irqhandler(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned long enabled_irq;
+	unsigned int off;
+
+	/* printk("Enterring %s: irq = %d\n", __FUNCTION__, irq); */
+
+	enabled_irq = __raw_readl(AK88_L2MEM_IRQ_ENABLE) & 0x7FFFF;
+
+	while (enabled_irq) {
+		off = __ffs(enabled_irq);
+		enabled_irq &= ~(1 << off);
+		irq = IRQ_L2_FRAC_DMA + off;
+		desc_handle_irq(irq, irq_desc + irq);
+	}
+}
+
+/* ak880x_init_irq
+ *
+ * Initialise AK7801 IRQ system
+ */
+
+void __init ak880x_init_irq(void)
+{
+	int i;
+
+	/* 1st, clear all interrupts */
+	__raw_readl(AK88_INT_STATUS);
+	__raw_readl(AK88_SYSCTRL_INT_CTRL);
+
+	/* 2nd, mask all interrutps */
+	__raw_writel(0x0, AK88_IRQ_MASK);
+	__raw_writel(0x0, AK88_FIQ_MASK);
+	__raw_writel(0x0, AK88_SYSCTRL_INT_CTRL);
+
+	/* mask all gpio interrupts */
+	__raw_writel(0x0, AK88_GPIO_INT_CTRL0);
+	__raw_writel(0x0, AK88_GPIO_INT_CTRL1);
+	__raw_writel(0x0, AK88_GPIO_INT_CTRL2);
+	__raw_writel(0x0, AK88_GPIO_INT_CTRL3);
+
+	/* mask all l2 interrupts */
+	__raw_writel(0x0, AK88_L2MEM_IRQ_ENABLE);
+
+	for (i = 0; i <= IRQ_SYSCTRL; i++) {
+		set_irq_chip(i, &ak880x_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_SYSCTRL, ak880x_sysctrl_handler);
+
+	for (i = IRQ_TOUCHPANEL; i <= IRQ_GPIO; i++) {
+		set_irq_chip(i, &ak880x_sysctrl_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_GPIO, ak880x_gpio_irqhandler);
+
+	for (i = IRQ_GPIO_0; i <= IRQ_DGPIO_14; i++) {
+		set_irq_chip(i, &ak880x_gpioirq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+#if 0
+	set_irq_chained_handler(IRQ_L2MEM, ak880x_l2mem_irqhandler);
+
+	for (i = IRQ_L2_FRAC_DMA; i <= IRQ_L2_CRC_VLD; i++) {
+		set_irq_chip(i, &ak880x_l2mem_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+#endif
+}
diff --git a/arch/arm/mach-ak88/irq.h b/arch/arm/mach-ak88/irq.h
new file mode 100644
index 00000000000..afa6ac6dfdb
--- /dev/null
+++ b/arch/arm/mach-ak88/irq.h
@@ -0,0 +1 @@
+void __init ak880x_init_irq(void);
diff --git a/arch/arm/mach-ak88/l2.c b/arch/arm/mach-ak88/l2.c
new file mode 100644
index 00000000000..1932517f18f
--- /dev/null
+++ b/arch/arm/mach-ak88/l2.c
@@ -0,0 +1,1058 @@
+/*
+ * linux/arch/arm/mach-ak88/l2.c
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/stddef.h>
+#include <linux/irq.h>
+ 
+#include <asm/dma.h>
+#include <asm/sizes.h>
+ 
+#include <mach/l2.h>
+
+static ak88_l2_buffer_info_t ak88_l2_buffer_info[AK88_L2_COMMON_BUFFER_NUM];
+static ak88_l2_dma_info_t ak88_l2_dma_info[AK88_L2_COMMON_BUFFER_NUM + AK88_L2_UART_BUFFER_NUM];
+static bool ak88_l2_frac_started = false;	/* L2 fraction DMA start flag */
+static ak88_l2_device_info_t ak88_l2_device_info[] = {
+	{ ADDR_USB_BULKOUT,	BUF_NULL },
+	{ ADDR_USB_BULKIN,	BUF_NULL },
+	{ ADDR_USB_ISO,		BUF_NULL },
+	{ ADDR_NFC,		BUF_NULL },
+	{ ADDR_MMC_SD,		BUF_NULL },
+	{ ADDR_SDIO,		BUF_NULL },
+	{ ADDR_RESERVED,	BUF_NULL },
+	{ ADDR_SPI1_RX,		BUF_NULL },
+	{ ADDR_SPI1_TX,		BUF_NULL },
+	{ ADDR_DAC,		BUF_NULL },
+	{ ADDR_SPI2_RX,		BUF_NULL },
+	{ ADDR_SPI2_TX,		BUF_NULL },
+	{ ADDR_PCM_RX,		BUF_NULL },
+	{ ADDR_PCM_TX,		BUF_NULL },
+	{ ADDR_ADC,		BUF_NULL },
+};
+
+static void ak88_l2_combuf_ctrl(u8 id, bool enable);
+static void ak88_l2_select_combuf(ak88_l2_device_t device, u8 id);
+static void ak88_l2_assert_combuf_id(u8 id);
+static void ak88_l2_assert_buf_id(u8 id);
+static void ak88_l2_clear_dma(u8 id);
+static void ak88_l2_frac_dma(unsigned long ram_addr, u8 id, u8 frac_offset,
+	unsigned int bytes, ak88_l2_dma_transfer_direction_t direction, bool intr_enable);
+static u32 ak88_l2_get_addr(u8 id);
+static void ak88_l2_dma(unsigned long ram_addr, u8 id, unsigned int bytes,
+		ak88_l2_dma_transfer_direction_t direction, bool intr_enable);
+static bool ak88_l2_wait_dma_finish(u8 id);
+static void ak88_l2_cpu(unsigned long ram_addr, u8 id,
+	unsigned long buf_offset, unsigned int bytes, ak88_l2_dma_transfer_direction_t direction);
+static irqreturn_t ak88_l2_interrupt_handler(int irq, void *dev_id);
+
+/**
+ * ak88_l2_assert_buf_id - Assert a L2 buffer ID is valid
+ *  @id:		L2 buffer ID
+ *
+ *  NOTE: Assert only L2 common buffer and UART buffer, USB buffer is not checked.
+ *            Since this function is called internally by other L2 API, invalid id will cause
+ *            linux kernel to oops for bug tracking.
+ */
+static void ak88_l2_assert_buf_id(u8 id)
+{
+	if (id >= AK88_L2_COMMON_BUFFER_NUM + AK88_L2_UART_BUFFER_NUM)
+		BUG();
+}
+
+/**
+ * ak88_l2_assert_combuf_id - Assert a L2 common buffer ID is valid
+ *  @id:		L2 buffer ID
+ *
+ *  NOTE: Assert only L2 common buffer, UART & USB buffer is not checked.
+ *            Since this function is called internally by other L2 API, invalid id will cause
+ *            linux kernel to oops for bug tracking.
+ */
+static void ak88_l2_assert_combuf_id(u8 id)
+{
+	if (id >= AK88_L2_COMMON_BUFFER_NUM)
+		BUG();
+}
+
+/**
+ * ak88_l2_combuf_ctrl - L2 buffer enable/disable
+ *  @id:		L2 buffer ID
+ *  @enable:	true to enable L2 buffer, false to disable L2 buffer 
+ */
+static void ak88_l2_combuf_ctrl(u8 id, bool enable)
+{
+	unsigned long regval;
+	unsigned long flags;
+
+	ak88_l2_assert_buf_id(id);
+
+	local_irq_save(flags);
+	
+	regval = __raw_readl(AK88_VA_L2_COMMON_BUF_CFG);
+	if (enable) {
+		/* Enable L2 buffer & L2 Buffer DMA */
+		regval |= (1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START)) |
+			(1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_VLD_START));
+	} else {
+		/* Disable L2 buffer & L2 Buffer DMA */
+		regval &= ~((1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START)) |
+			(1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_VLD_START)));
+	}
+	__raw_writel(regval, AK88_VA_L2_COMMON_BUF_CFG);
+
+	local_irq_restore(flags);
+
+}
+
+/**
+ * ak88_l2_select_combuf - Select a L2 buffer for given device
+ *  @device:	Device which need to assign a L2 buffer
+ *  @id:		L2 buffer ID
+ */
+static void ak88_l2_select_combuf(ak88_l2_device_t device, u8 id)
+{
+	unsigned long regid;
+	unsigned long regval;
+	unsigned long bits_offset;
+	
+	ak88_l2_assert_combuf_id(id);
+
+	if ((u8)device < 10) {
+		/*
+		 * USB Bulkout ~ DAC (Device 0 ~ 9) is controlled by Buffer Assignment Register 1
+		 */
+		regid = (unsigned long)AK88_VA_L2_BUF_ASSIGN1;
+		bits_offset = (u8)device * 3;
+	} else {
+		/*
+		 * SPI2 Rx ~ ADC (Device 10 ~ 14) is controlled by Buffer Assignment Register 2
+		 */
+		regid = (unsigned long)AK88_VA_L2_BUF_ASSIGN2;
+		bits_offset = ((u8)device - 10) * 3;
+	}
+
+	regval = __raw_readl(regid);
+	regval &= ~(0x7 << bits_offset);
+	regval |= ((id & 0x7) << bits_offset);
+	__raw_writel(regval, regid);
+
+}
+
+/**
+ * ak88_l2_clear_dma - Clear L2 buffer DMA status
+ *  @id:		L2 buffer ID which need to clear DMA status
+ */
+static void ak88_l2_clear_dma(u8 id)
+{
+	bool dmapending;
+	u8 status;
+	
+	dmapending = __raw_readl(AK88_VA_L2_DMA_REQ) & (1 << (id + AK88_L2_DMA_REQ_BUF_START));
+	status = ak88_l2_get_status(id);
+
+	if (status == 0) {
+		return ;	/* NO DMA request, so do nothing */
+	}
+
+	/*
+	 * Wait until DMA request of this L2 buffer is finished.
+	 */
+	while (dmapending) {
+		printk("ak88-l2: unfinished DMA in buf[%d].\n", id);
+		ak88_l2_clr_status(id);
+		dmapending = __raw_readl(AK88_VA_L2_DMA_REQ) & (1 << (id + AK88_L2_DMA_REQ_BUF_START));
+	}
+
+}
+
+/**
+ * ak88_l2_frac_dma - Start data tranferring between memory and l2 common buffer in fraction DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @frac_offset:	The region offset between buffer start address and transfer start address
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ *
+ *  NOTE: Data transfer size should be 1~64Bytes, frac_offset should be 0~7 (*64Bytes)
+ */
+static void ak88_l2_frac_dma(unsigned long ram_addr, u8 id, u8 frac_offset,
+	unsigned int bytes, ak88_l2_dma_transfer_direction_t direction,	bool intr_enable)
+{
+	u32 bufaddr;
+	unsigned long regval;
+	unsigned long flags;
+
+#if 0
+	printk("%s(): ram_addr=0x%08X, l2 buffer id=%d, frac_offset=%d, bytes=%d, direction=%s, intr_enable=%d.\n",
+		__func__, (unsigned int)ram_addr, id, frac_offset, bytes, (direction == BUF2MEM)?"BUF2MEM":"MEM2BUF", intr_enable);
+#endif
+
+	if (bytes == 0) {
+		printk("ak88-l2: no need to start fraction dma transfer: bytes=0.\n");
+		return ;
+	}
+
+	local_irq_save(flags);
+
+	/*
+	 * Set fraction external RAM address.
+	 */
+	regval = __raw_readl(AK88_VA_L2_FRAC_DMA);
+	regval &= ~AK88_L2_FRAC_DMA_ADDR_MASK;
+	regval |= (ram_addr & AK88_L2_FRAC_DMA_ADDR_MASK);
+	__raw_writel(regval, AK88_VA_L2_FRAC_DMA);
+
+	/* Set fraction DMA address */
+	bufaddr = (id < AK88_L2_COMMON_BUFFER_NUM) ? ((id & 0x7) << 3) | (frac_offset & 0x7) :
+		(0x40 + ((id - AK88_L2_COMMON_BUFFER_NUM) << 1)) | (frac_offset & 0x1);
+
+	/* Clear other fraction DMA request and info */
+	regval = __raw_readl(AK88_VA_L2_DMA_REQ);
+	regval &= ~(AK88_L2_DMA_REQ_FRAC_DMA_LEN_MASK | AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_MASK |
+		AK88_L2_DMA_REQ_FRAC_DMA_REQ | AK88_L2_DMA_REQ_BUF_REQ_MASK);
+
+	switch (direction) {
+	case MEM2BUF:
+		if (bytes & 0x1)
+			bytes = bytes + 1;	/* Round to even number when read data from external ram */
+		regval |= AK88_L2_DMA_REQ_FRAC_DMA_REQ | AK88_L2_DMA_REQ_FRAC_DMA_DIR_WR |
+			(bufaddr << AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START) |
+			((bytes - 1) << AK88_L2_DMA_REQ_FRAC_DMA_LEN_START);
+		__raw_writel(regval, AK88_VA_L2_DMA_REQ);
+		break;
+	case BUF2MEM:
+		regval &= ~(AK88_L2_DMA_REQ_FRAC_DMA_DIR_WR);
+		regval |= AK88_L2_DMA_REQ_FRAC_DMA_REQ |
+			(bufaddr << AK88_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START) |
+			((bytes - 1) << AK88_L2_DMA_REQ_FRAC_DMA_LEN_START);
+		__raw_writel(regval, AK88_VA_L2_DMA_REQ);
+		break;
+	default:
+		BUG();
+	}
+
+	if (intr_enable) {
+		regval = __raw_readl(AK88_VA_L2_INTR_ENABLE);
+		regval |= AK88_L2_DMA_INTR_ENABLE_FRAC_INTR_EN;
+		__raw_writel(regval, AK88_VA_L2_INTR_ENABLE);
+	}
+
+	local_irq_restore(flags);
+
+	if (intr_enable)
+		wait_event(ak88_l2_dma_info[id].wq, ak88_l2_dma_info[id].dma_irq_done);
+}
+
+/**
+ * ak88_l2_get_addr - Get L2 memory start address for given L2 buffer
+ *  @id:		L2 buffer ID
+ *  Return L2 memory start address(Logical/Virtual) (NOT physical address)
+ */
+static u32 ak88_l2_get_addr(u8 id)
+{
+	u32 bufaddr = 0;
+
+	if (id < AK88_L2_UART_BUFFER_INDEX) {	/* L2 common buffer */
+		bufaddr = (u32)AK88_VA_L2MEM + AK88_L2_COMMON_BUFFER_OFFSET +
+			id * AK88_L2_COMMON_BUFFER_LEN;
+	} else if (id < AK88_L2_USB_HOST_BUFFER_INDEX) {	/* UART L2 buffer */
+		bufaddr = (u32)AK88_VA_L2MEM + AK88_L2_UART_BUFFER_OFFSET + 
+			(id - AK88_L2_COMMON_BUFFER_NUM) * AK88_L2_UART_BUFFER_LEN;
+	} else if (id == AK88_L2_USB_HOST_BUFFER_INDEX) {	/* USB Host L2 buffer */
+		bufaddr = (u32)AK88_VA_L2MEM + AK88_L2_USB_HOST_BUFFER_OFFSET;
+	} else if (id < AK88_L2_USB_BUFFER_OFFSET) {	/* USB L2 buffer */
+		bufaddr = (u32)AK88_VA_L2MEM + AK88_L2_USB_BUFFER_OFFSET +
+			(id - AK88_L2_USB_BUFFER_INDEX) * AK88_L2_USB_BUFFER_LEN;
+	} else {
+		printk("ak88-l2: invalid buffer id %d.\n", (int)id);
+	}
+
+	return bufaddr;
+}
+
+/**
+ * ak88_l2_dma - Start data tranferring between memory and l2 buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ */
+static void ak88_l2_dma(unsigned long ram_addr, u8 id, unsigned int bytes,
+	ak88_l2_dma_transfer_direction_t direction, bool intr_enable)
+{
+	unsigned long regid;
+	unsigned long regval;
+	unsigned long flags;
+
+#if 0
+	printk("%s(): ram_addr=0x%0X, id=%d, bytes=%d, direction=%d, intr_enable=%d.\n",
+		__func__, (unsigned int)ram_addr, id, bytes, direction, intr_enable);
+#endif
+	if (bytes == 0) {
+		printk("ak88-l2: no need to start fraction dma transfer: bytes=0.\n");
+		return ;
+	}
+	
+	if (ak88_l2_dma_info[id].dma_start || ak88_l2_dma_info[id].dma_frac_start) {
+		printk("ak88-l2: unable to start dma, dma NOT finished, buf id=%d.\n", (int)id);
+		return ;
+	}
+
+	ak88_l2_dma_info[id].dma_op_times = bytes / AK88_DMA_ONE_SHOT_LEN;
+	ak88_l2_dma_info[id].dma_frac_data_len = bytes % AK88_DMA_ONE_SHOT_LEN;
+	ak88_l2_dma_info[id].dma_addr = (void *)ram_addr;
+	ak88_l2_dma_info[id].direction = direction;
+	ak88_l2_dma_info[id].intr_enable = intr_enable;
+	ak88_l2_dma_info[id].need_frac = false;
+	ak88_l2_dma_info[id].dma_irq_done = 0;
+
+	if (ak88_l2_dma_info[id].dma_frac_data_len > 0) {
+		ak88_l2_dma_info[id].need_frac = true;
+		ak88_l2_dma_info[id].dma_frac_addr = (void *)(u8 *)ak88_l2_dma_info[id].dma_addr +
+			ak88_l2_dma_info[id].dma_op_times* AK88_DMA_ONE_SHOT_LEN;
+		ak88_l2_dma_info[id].dma_frac_offset = ak88_l2_dma_info[id].dma_op_times;
+	}
+
+	if (ak88_l2_dma_info[id].dma_op_times== 0) {
+		/*
+		 * If DMA transfer size < 64, we start fraction DMA immediately.
+		 */
+		 
+		ak88_l2_dma_info[id].dma_start = false;
+		ak88_l2_dma_info[id].dma_frac_start = true;
+
+		ak88_l2_frac_dma((unsigned long)ak88_l2_dma_info[id].dma_frac_addr, id,
+			ak88_l2_dma_info[id].dma_frac_offset, ak88_l2_dma_info[id].dma_frac_data_len,
+			ak88_l2_dma_info[id].direction, intr_enable);
+		return ;
+	}
+	ak88_l2_dma_info[id].dma_start = true;
+
+	local_irq_save(flags);
+
+	/*
+	 * Set address of external RAM
+	 */
+	regval = (unsigned long)ak88_l2_dma_info[id].dma_addr & AK88_L2_DMA_ADDR_MASK;
+	regid = (unsigned long)AK88_VA_L2_DMA_ADDR + id * 4;
+	__raw_writel(regval, regid);
+
+	/*
+	 * Set DMA operation times
+	 */
+	regid = (unsigned long)AK88_VA_L2_DMA_OP_TIMES + id * 4;
+	regval = ak88_l2_dma_info[id].dma_op_times& 0xFF;
+	__raw_writew((u16)regval, regid);
+
+	/*
+	 * Set DMA direction for L2 common buffer
+	 */
+	if (id < AK88_L2_COMMON_BUFFER_NUM) {
+		regval = __raw_readl(AK88_VA_L2_COMMON_BUF_CFG);
+		if (ak88_l2_dma_info[id].direction == MEM2BUF) {
+			regval |= (1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_DIR_START));;
+		} else {
+			regval &= ~(1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_DIR_START)); 
+		}
+		__raw_writel(regval, AK88_VA_L2_COMMON_BUF_CFG);
+	}
+
+	
+	/*
+	 * Start buffer DMA request
+	 */
+	regval = __raw_readl(AK88_VA_L2_DMA_REQ);
+	regval &= ~(AK88_L2_DMA_REQ_FRAC_DMA_REQ | AK88_L2_DMA_REQ_BUF_REQ_MASK);
+	if (id < AK88_L2_COMMON_BUFFER_NUM) {
+		regval |= (1 << (id + AK88_L2_DMA_REQ_BUF_START));
+	} else {
+		regval |= (1 << ((id - AK88_L2_UART_BUF_START_ID + AK88_L2_UART_BUF_CFG_BUF_START)));
+	}
+	__raw_writel(regval, AK88_VA_L2_DMA_REQ);
+
+	
+	/*
+	 * Enable DMA interrupt now
+	 */
+	if (intr_enable) {
+		regval = __raw_readl(AK88_VA_L2_INTR_ENABLE);
+		if (id < AK88_L2_COMMON_BUFFER_NUM) {
+			regval |= 1 << (id + AK88_L2_DMA_INTR_ENABLE_BUF_START);
+		} else {
+			regval |= 1 << (id - AK88_L2_COMMON_BUFFER_NUM + AK88_L2_DMA_INTR_ENABLE_UART_BUF_START);
+		}
+		__raw_writel(regval, AK88_VA_L2_INTR_ENABLE);
+	}
+
+	local_irq_restore(flags);
+
+	if (intr_enable)
+		wait_event(ak88_l2_dma_info[id].wq, ak88_l2_dma_info[id].dma_irq_done);
+}
+
+/**
+ * ak88_l2_wait_dma_finish - Wait for L2 DMA to finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak88_l2_dma.
+ */
+static bool ak88_l2_wait_dma_finish(u8 id)
+{
+	unsigned int timeout;
+	unsigned long dmareq;
+	unsigned long dma_bit;
+	const unsigned int max_wait_time = AK88_L2_MAX_DMA_WAIT_TIME;
+
+	timeout = 0;
+	if (ak88_l2_dma_info[id].dma_start) {
+		dma_bit = (id < AK88_L2_COMMON_BUFFER_NUM) ? (1 << (id + AK88_L2_DMA_REQ_BUF_START)) :
+			(1 << (id - AK88_L2_COMMON_BUFFER_NUM + AK88_L2_DMA_REQ_UART_BUF_REQ_START));
+		do {
+			dmareq = __raw_readl(AK88_VA_L2_DMA_REQ);
+		} while((dmareq & dma_bit) && timeout++ < max_wait_time);
+
+		ak88_l2_dma_info[id].dma_start = false;
+
+		if (timeout >= max_wait_time) {
+			printk("ak88-l2: wait dma timeout, buf id=%d, status=%d.\n", id, ak88_l2_get_status(id));
+			ak88_l2_clear_dma(id);
+			__raw_writel(0x0, AK88_VA_L2_DMA_OP_TIMES + id * 4);
+			return false;
+		}
+
+		/*
+		 * If fraction DMA  is NOT need, then everything is done.
+		 */
+		if (!ak88_l2_dma_info[id].need_frac) {
+			return true;
+		}	
+
+
+		/*
+		 * Start fraction DMA here for remain bytes transfer (<64Bytes).
+		 */
+		ak88_l2_dma_info[id].dma_frac_start = true;
+		ak88_l2_frac_dma((unsigned long)ak88_l2_dma_info[id].dma_frac_addr, id,
+			ak88_l2_dma_info[id].dma_frac_offset, ak88_l2_dma_info[id].dma_frac_data_len,
+			ak88_l2_dma_info[id].direction, false);
+
+	}
+
+	/*
+	 * Fraction DMA handling starts here.
+	 */
+	if (ak88_l2_dma_info[id].dma_frac_start) {
+		timeout = 0;
+		do {
+			dmareq = __raw_readl(AK88_VA_L2_DMA_REQ);
+		} while((dmareq & AK88_L2_DMA_REQ_FRAC_DMA_REQ) && (timeout++ < max_wait_time));
+
+		ak88_l2_dma_info[id].dma_frac_start = false;
+
+		if (timeout >= max_wait_time) {
+			printk("ak88-l2:wait frac dma timeout, buf id=%d, status=%d.\n", id, ak88_l2_get_status(id));
+			return false;
+		}
+	}
+
+	return true;
+}
+
+/**
+ * ak88_l2_interrupt_handler - L2 memory interrupt handler
+ *  @irq:	IRQ number for L2 memory (Must be IRQ_L2MEM)
+ *  @dev_id:	Device specific information used by interrupt handler
+ *
+ *  NOTE: Only shared IRQ need to check @irq & @dev_id.
+ *            No need to check them here since L2 memory IRQ is NOT shared IRQ.
+ */
+static irqreturn_t ak88_l2_interrupt_handler(int irq, void *dev_id)
+{
+	unsigned long regval;
+	int i = 0;
+
+	regval = __raw_readl(AK88_VA_L2_DMA_REQ);
+
+	for (i = 0; i < AK88_L2_COMMON_BUFFER_NUM; i++) {
+		unsigned long dmapending = regval & (1 << ( i + AK88_L2_DMA_REQ_BUF_START));
+
+		if (ak88_l2_dma_info[i].dma_start && !dmapending) {
+			if (!ak88_l2_frac_started && ak88_l2_dma_info[i].need_frac) {
+				ak88_l2_dma_info[i].dma_frac_start = true;
+				ak88_l2_dma_info[i].dma_start = false;
+				ak88_l2_dma_info[i].dma_irq_done = 0;
+
+				ak88_l2_frac_dma((unsigned long)ak88_l2_dma_info[i].dma_frac_addr, i,
+					ak88_l2_dma_info[i].dma_frac_offset, ak88_l2_dma_info[i].dma_frac_data_len,
+					ak88_l2_dma_info[i].direction, true);
+
+				ak88_l2_frac_started = true;
+			} else {
+				/* DMA has finished */
+				unsigned long regval;
+
+				regval = __raw_readl(AK88_VA_L2_INTR_ENABLE);
+				regval &= ~(1 << (i + AK88_L2_DMA_INTR_ENABLE_BUF_START));
+				__raw_writel(regval, AK88_VA_L2_INTR_ENABLE);
+
+				ak88_l2_dma_info[i].dma_start = false;
+
+				if (ak88_l2_dma_info[i].callback_func != NULL)
+					ak88_l2_dma_info[i].callback_func();
+				ak88_l2_dma_info[i].dma_irq_done = 1;
+				wake_up(&ak88_l2_dma_info[i].wq);
+				
+			}
+		}
+
+		if (ak88_l2_dma_info[i].dma_frac_start) {
+			unsigned long frac_dmapending = regval & AK88_L2_DMA_REQ_FRAC_DMA_REQ;
+			if (ak88_l2_frac_started && !frac_dmapending) {
+				ak88_l2_frac_started = false;
+
+				switch (ak88_l2_dma_info[i].direction) {
+				case MEM2BUF:
+					if (ak88_l2_dma_info[i].dma_frac_data_len <= 60)
+						__raw_writel(0x0, AK88_VA_L2MEM + i * 512 + 0x1FC);
+					break;
+				case BUF2MEM:
+					if (ak88_l2_dma_info[i].dma_frac_data_len <= 512 - 4)
+						ak88_l2_clear_dma(i);
+					break;
+				default:
+					BUG();
+				}
+				ak88_l2_dma_info[i].dma_frac_start = false;
+
+				if (ak88_l2_dma_info[i].callback_func != NULL)
+					ak88_l2_dma_info[i].callback_func();
+				
+				ak88_l2_dma_info[i].dma_irq_done = 1;
+				wake_up(&ak88_l2_dma_info[i].wq);
+			}
+		}
+		
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * ak88_l2_cpu - Transfer data between memory and l2 buffer in CPU mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID
+ *  @buf_offset:	The buffer offset
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ */
+static void ak88_l2_cpu(unsigned long ram_addr, u8 id,
+	unsigned long buf_offset, unsigned int bytes, ak88_l2_dma_transfer_direction_t direction)
+{
+	int i;
+	int j;
+	unsigned long trans_no;
+	unsigned long frac_no;
+	unsigned long buf_count;
+	unsigned long buf_remain;
+	unsigned long temp_ram;
+	unsigned long temp_buf;
+	unsigned long bufaddr;
+	
+	/*
+	 * L2 buffer caller MUST guarantee L2 buffer offset is 4-byte aligned
+	 */
+	if (unlikely(buf_offset % 4))
+		BUG();
+
+	bufaddr = ak88_l2_get_addr(id);
+
+	if (bufaddr == 0) {
+		return ;
+	}
+
+	bufaddr += buf_offset;
+	trans_no = bytes / 4;
+	frac_no = bytes % 4;
+
+	buf_count = (buf_offset + bytes) / AK88_L2_BUF_STATUS_MULTIPLY_RATIO;
+	buf_remain = (buf_offset + bytes) % AK88_L2_BUF_STATUS_MULTIPLY_RATIO;
+
+	switch (direction) {
+	case MEM2BUF:
+		if (ram_addr % 4) {
+			for (i = 0; i < trans_no; i++) {
+				temp_ram = 0;
+				for (j = 0; j < 4; j++)
+					temp_ram |= ((read_ramb(ram_addr + i*4 + j))<<(j*8));
+				write_buf(temp_ram, (bufaddr + i * 4));
+			}
+			if (frac_no) {
+				temp_ram = 0;
+				for (i = 0; i < frac_no; i++)
+					temp_ram |= ((read_ramb(ram_addr + trans_no*4 + j))<<(j*8));
+				write_buf(temp_ram, (bufaddr + trans_no * 4));
+			}
+		} else {
+			for (i = 0; i < trans_no; i++)
+				write_buf(read_raml(ram_addr + i*4), (bufaddr + i*4));
+			if (frac_no)
+				write_buf(read_raml(ram_addr + trans_no*4), (bufaddr + trans_no*4));
+		}
+		
+		/*
+		 * If we do NOT write data to L2 in multiple of 64Bytes, we must write something to the 4Bytes in 64Bytes-
+		 * boundary so that CPU knows writing ends..
+		 */
+		if ((buf_remain > 0) && (buf_remain <= AK88_L2_BUF_STATUS_MULTIPLY_RATIO - 4))
+			write_buf(0, (bufaddr - buf_offset + buf_count*AK88_L2_BUF_STATUS_MULTIPLY_RATIO + AK88_L2_BUF_STATUS_MULTIPLY_RATIO - 4));
+		break;
+	case BUF2MEM:
+		if (ram_addr % 4) {
+			for (i = 0; i < trans_no; i++) {
+				temp_buf = read_buf(bufaddr + i * 4);
+				for (j = 0; j < 4; j++)
+					write_ramb((u8)((temp_buf>>j*8) & 0xFF), (ram_addr + i*4 + j));
+			}
+			if (frac_no) {
+				temp_buf = read_buf(bufaddr+trans_no*4);
+				for (j = 0; j < frac_no; j++)
+					write_ramb((u8)((temp_buf>>j*8) & 0xFF), (ram_addr + trans_no*4 + j));
+			}
+		} else {
+			for (i = 0; i < trans_no; i++)
+				write_raml(read_buf(bufaddr+i*4), (ram_addr+i*4));
+			if (frac_no) {
+				temp_buf = read_buf(bufaddr+trans_no*4);
+				temp_ram = read_raml(ram_addr+trans_no*4);
+				temp_buf &= ((1<<(frac_no*8+1))-1);
+				temp_ram &= ~((1<<(frac_no*8+1))-1);
+				temp_ram |= temp_buf;
+				write_raml(temp_ram, (ram_addr+trans_no*4));
+			}
+		}
+		
+		/*
+		 * If we do NOT read data from L2 in multiple of 64Bytes, we must read the 4Bytes in 64Bytes-
+		 * boundary so that CPU knows reading ends..
+		 */
+		if ((buf_remain > 0) && (buf_remain <= AK88_L2_BUF_STATUS_MULTIPLY_RATIO - 4))
+			temp_buf = read_buf(bufaddr-buf_offset+buf_count*AK88_L2_BUF_STATUS_MULTIPLY_RATIO+AK88_L2_BUF_STATUS_MULTIPLY_RATIO - 4);
+		break;
+	default:
+		BUG();
+	}
+
+}
+
+
+
+/**
+ * ak88_l2_init - Initialize linux kernel L2 memory support
+ */
+void __init ak88_l2_init(void)
+{
+	int i;
+	int retval;
+
+	/*
+	 * Initialize all L2 common buffer status to IDLE(could be allocated)
+	 */
+	for (i = 0; i < AK88_L2_COMMON_BUFFER_NUM; i++) {
+		ak88_l2_buffer_info[i].id = (u8)i;
+		ak88_l2_buffer_info[i].usable = L2_STAT_IDLE;
+		ak88_l2_buffer_info[i].used_time = 0;
+	}
+
+	/* L2 Memory Register initializations */
+	__raw_writel(AK88_L2_DMA_REQ_EN, AK88_VA_L2_DMA_REQ);
+	__raw_writel(AK88_L2_FRAC_DMA_AHB_FLAG_EN | AK88_L2_FRAC_DMA_LDMA_FLAG_EN, AK88_VA_L2_FRAC_DMA);
+	__raw_writel(0x0, AK88_VA_L2_COMMON_BUF_CFG);
+	__raw_writel(AK88_L2_UART_BUF_CFG_UART_EN_MASK | AK88_L2_UART_BUF_CFG_UART_CLR_MASK, AK88_VA_L2_UART_BUF_CFG);
+	__raw_writel(0x0, AK88_VA_L2_INTR_ENABLE);
+	__raw_writel(0x0, AK88_VA_L2_BUF_ASSIGN1);
+	__raw_writel(0x0, AK88_VA_L2_BUF_ASSIGN2);
+
+
+	/* L2 Memory Interrupt handler registered */
+	if ((retval = request_irq(IRQ_L2MEM, &ak88_l2_interrupt_handler, IRQF_DISABLED, "ak88-l2", NULL)) < 0)
+		printk(KERN_ERR "ak88-l2: failed to request_irq, irq number: %d, retval=%d.\n", IRQ_L2MEM, retval);
+
+	/* Initialize L2 DMA information status */
+	memset(ak88_l2_dma_info, 0, ARRAY_SIZE(ak88_l2_dma_info));
+
+	/* Initialize L2 DMA wait queue */
+	for (i = 0; i < ARRAY_SIZE(ak88_l2_dma_info); i++)
+		init_waitqueue_head(&ak88_l2_dma_info[i].wq);
+
+	/* Initialize global L2 fraction DMA start flag */
+	ak88_l2_frac_started = false;
+
+	printk("AK88xx: L2 memory support initialized\n");
+}
+
+/**
+ * ak88_l2_alloc - Allocate a common L2 buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak88_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ */
+u8 ak88_l2_alloc(ak88_l2_device_t device)
+{
+	int i;
+	u16 used_times = MAX_L2_BUFFER_USED_TIMES;
+	u8 id = BUF_NULL;
+	u8 first_id = BUF_NULL;
+	unsigned long flags;
+
+	if (unlikely(device == ADDR_RESERVED)) {
+		printk("ak88_l2: unable to allocate l2 buffer for reserved device.\n");
+		
+		return BUF_NULL;
+	}
+
+	if (unlikely(ak88_l2_device_info[(u8)device].id != BUF_NULL)) {
+		printk("ak88_l2: device %d already have a l2 buffer %d\n",
+			(int)(u8)device, (int)(u8)ak88_l2_device_info[(u8)device].id);
+		
+		return ak88_l2_device_info[(u8)device].id;
+	}
+
+	local_irq_save(flags);
+
+	for (i = 0; i < AK88_L2_COMMON_BUFFER_NUM; i++) {
+		if (ak88_l2_buffer_info[i].usable == L2_STAT_IDLE) {
+			if (first_id == BUF_NULL) {
+				first_id = ak88_l2_buffer_info[i].id;
+				used_times = ak88_l2_buffer_info[i].used_time;
+				id = first_id;
+			}
+			if (ak88_l2_buffer_info[i].used_time < used_times) {
+				used_times = ak88_l2_buffer_info[i].used_time;
+				id = ak88_l2_buffer_info[i].id;
+			}
+		}
+	}
+
+	if (unlikely(first_id == BUF_NULL)) {
+		local_irq_restore(flags);
+		printk(KERN_ERR "ak88-l2: fatal error: no more l2 buffer to allocate!\n");
+		BUG();
+		return BUF_NULL;
+	}
+
+	/*
+	 * Got a L2 buffer successfully...
+	 */
+	ak88_l2_buffer_info[id].usable = L2_STAT_USED;
+	ak88_l2_buffer_info[id].used_time++;
+	if (ak88_l2_buffer_info[id].used_time == 0) {
+		/*
+		 * In case when the new allocated L2 buffer has been used MAX_L2_BUFFER_USED_TIMES,
+		 * we just clear all L2 buffer used times as a simpfied method of balancing 8 L2 buffer usage.
+		 */
+		for (i = 0; i < AK88_L2_COMMON_BUFFER_NUM; i++)
+			ak88_l2_buffer_info[i].used_time = 0;
+	}
+
+	/* Enable L2 buffer */
+	ak88_l2_combuf_ctrl(id, true);
+
+	/* Change device info */
+	ak88_l2_device_info[device].id = id;
+
+	/* Select L2 common buffer for device */
+	ak88_l2_select_combuf(device, id);
+
+	local_irq_restore(flags);
+
+	/* Clear L2 buffer status */
+	ak88_l2_clr_status(id);
+
+	return id;
+}
+EXPORT_SYMBOL(ak88_l2_alloc);
+
+/**
+ * ak88_l2_free - Free L2 common buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak88_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ *  NOTE: Return the previous L2 buffer ID if a L2 buffer has been allocated to the device.
+ *            This means one device could get only one L2 buffer maximum.
+ */
+void ak88_l2_free(ak88_l2_device_t device)
+{
+	u8 id;
+	unsigned long regval;
+	unsigned long flags;
+
+	id = ak88_l2_device_info[(u8)device].id;
+	if (unlikely(id == BUF_NULL)) {
+		printk("ak88-l2: trying to free invalid buffer id %d\n", (int)id);
+		return ;
+	}
+
+	ak88_l2_clear_dma(id);
+
+	local_irq_save(flags);
+
+	/*
+	 * Disable DMA interrupt of this L2 buffer.
+	 */
+	regval = __raw_readl(AK88_VA_L2_INTR_ENABLE);
+	regval &= ~(1 << (id + AK88_L2_DMA_INTR_ENABLE_BUF_START));
+	__raw_writel(regval, AK88_VA_L2_INTR_ENABLE);
+
+	/* Set DMA count to 0 */
+	__raw_writel(0x0, AK88_VA_L2_DMA_OP_TIMES + id * 4);
+
+	/* Disable this L2 buffer */
+	ak88_l2_combuf_ctrl(id, false);
+
+	/* Clear DMA & DMA fraction flags */
+	if (ak88_l2_dma_info[id].dma_start || ak88_l2_dma_info[id].dma_frac_start) {
+		ak88_l2_dma_info[id].dma_start = false;
+		ak88_l2_dma_info[id].dma_frac_start = false;
+	}
+
+	ak88_l2_device_info[(u8)device].id = BUF_NULL;
+	ak88_l2_buffer_info[id].usable = L2_STAT_IDLE;
+
+	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(ak88_l2_free);
+
+/**
+ * ak88_l2_set_dma_callback - Set callback function when L2 DMA/fraction DMA interrupt handler is done
+ *  @id:	L2 buffer ID
+ *  @func:	Callback function
+ *  Return true(Always)
+ *  
+ *  NOTE: Caller MUST guarantee that L2 buffer ID is valid. And since the callback function is called
+ *  in interrupt handler, it MUST NOT call any functions which may sleep.
+ */
+bool ak88_l2_set_dma_callback(u8 id, ak88_l2_callback_func_t func)
+{
+	if (unlikely(id >= AK88_L2_COMMON_BUFFER_NUM)) {
+		printk(KERN_ERR "ak88-l2: Set dma callback, invalid buf id[%d].\n", id);
+		return false;
+	}
+
+	if (unlikely(ak88_l2_dma_info[id].dma_start || ak88_l2_dma_info[id].dma_frac_start)) {
+		printk(KERN_ERR "ak88-l2: Set dma callback, dma not finished.\n");
+		return false;
+	}
+
+	ak88_l2_dma_info[id].callback_func = func;
+
+	return true;
+}
+EXPORT_SYMBOL(ak88_l2_set_dma_callback);
+
+/**
+ * ak88_l2_combuf_dma - Start data tranferring between memory and l2 common buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ */
+void ak88_l2_combuf_dma(unsigned long ram_addr, u8 id, unsigned int bytes, ak88_l2_dma_transfer_direction_t direction, bool intr_enable)
+{
+	if (unlikely(id >= AK88_L2_COMMON_BUFFER_NUM)) {
+		printk("ak88-l2: begin common buffer dma, error buf id=[%d].\n", id);
+		return ;
+	}
+
+	ak88_l2_dma(ram_addr, id, bytes, direction, intr_enable);
+}
+EXPORT_SYMBOL(ak88_l2_combuf_dma);
+
+/**
+ * ak88_l2_combuf_wait_dma_finish - Wait for L2 DMA to finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak88_l2_combuf_dma.
+ */
+bool ak88_l2_combuf_wait_dma_finish(u8 id)
+{
+	if (unlikely(id >= AK88_L2_COMMON_BUFFER_NUM)) {
+		printk("ak88-l2: begin common buffer dma, error buf id=[%d].\n", id);
+		return false;
+	}
+	return ak88_l2_wait_dma_finish(id);
+}
+EXPORT_SYMBOL(ak88_l2_combuf_wait_dma_finish);
+
+/**
+ * ak88_l2_combuf_cpu - Transfer data between memory and l2 common buffer in CPU mode
+ *  @ram_addr:	External RAM address(Physical)
+ *  @id:	L2 buffer ID
+ *  @bytes:	Data transfer size
+ *  @direction:	Data transfer direction between L2 memory and external RAM
+ *
+ *  NOTE: According to XuChang, if one transfer data from Peripheral --> L2 Buffer --> RAM, 
+ *            special care need to be taken when data size is NOT multiple of 64Bytes.
+ *            Pheripheral driver must check hardware signals to confirm data has been transfer from
+ *            peripheral to L2 buffer since L2 do NOT provide some mechanism to confirm data has
+ *            been in L2 Buffer. Driver can and only can call ak88_l2_combuf_cpu() to copy data from L2
+ *            Buffer --> RAM after checking hardware signals.
+ *            As to 64Bytes * n size data, L2 could check Buffer Status Status Counter to confirm that
+ *            Data has been transfer from peripheral to L2 buffer, so no hardware signals checking needed.
+ */
+void ak88_l2_combuf_cpu(unsigned long ram_addr, u8 id,
+	unsigned int bytes, ak88_l2_dma_transfer_direction_t direction)
+{
+	int i;
+	int loop;
+	int remain;
+
+	if (bytes > AK88_L2_BUFFER_SIZE) {
+		printk("ak88-l2: l2_combuf_cpu buffer exceed L2 buffer size(512Bytes).\n");
+		return ;
+	}
+
+	loop = bytes / AK88_L2_BUF_STATUS_MULTIPLY_RATIO;
+	remain = bytes % AK88_L2_BUF_STATUS_MULTIPLY_RATIO;
+
+	switch (direction) {
+	case MEM2BUF:
+		for (i = 0; i < loop; i++) {
+			
+			while (ak88_l2_get_status(id) == (AK88_L2_BUFFER_SIZE / AK88_L2_BUF_STATUS_MULTIPLY_RATIO))
+				;	/* Waiting for L2 buffer to NOT full(means writable) */
+			
+			ak88_l2_cpu(ram_addr + i * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(i % 8) * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, AK88_L2_BUF_STATUS_MULTIPLY_RATIO, direction);
+		}
+		if (remain > 0) {
+			while (ak88_l2_get_status(id) > 0)
+				;	/* Waiting for L2 buffer to empty */
+
+			ak88_l2_cpu(ram_addr + loop * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(loop % 8) * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, remain, direction);
+		}
+		break;
+	case BUF2MEM:
+		for (i = 0; i < loop; i++) {
+			while (ak88_l2_get_status(id) == 0)
+				;	/* Waiting for L2 buffer to be not empty (means readable) */
+			
+			ak88_l2_cpu(ram_addr + i * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(i % 8) * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, AK88_L2_BUF_STATUS_MULTIPLY_RATIO, direction);
+			
+		}
+		if (remain > 0) {
+			ak88_l2_cpu(ram_addr + loop * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(loop % 8) * AK88_L2_BUF_STATUS_MULTIPLY_RATIO, remain, direction);
+		}
+		break;
+	default:
+		BUG();
+	}
+}
+EXPORT_SYMBOL(ak88_l2_combuf_cpu);
+
+/**
+ * ak88_l2_get_status - Get L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+u8 ak88_l2_get_status(u8 id)
+{
+	ak88_l2_assert_buf_id(id);
+
+	return (id < AK88_L2_COMMON_BUFFER_NUM) ? (__raw_readl(AK88_VA_L2_BUF_STAT1) >> (id * 4)) & 0xF :
+		(__raw_readl(AK88_VA_L2_BUF_STAT2) >> ((id - AK88_L2_UART_BUF_START_ID) << 1)) & 0x3;
+}
+EXPORT_SYMBOL(ak88_l2_get_status);
+
+/**
+ * ak88_l2_clr_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+void ak88_l2_clr_status(u8 id)
+{
+	unsigned long regval;
+	unsigned long flags;
+
+	ak88_l2_assert_buf_id(id);
+	
+	local_irq_save(flags);
+
+	if (id < AK88_L2_COMMON_BUFFER_NUM) {
+		regval = __raw_readl(AK88_VA_L2_COMMON_BUF_CFG);
+		regval |= 1 << (id + AK88_L2_COMMON_BUF_CFG_BUF_CLR_START);
+		__raw_writel(regval, AK88_VA_L2_COMMON_BUF_CFG);
+	} else {
+		regval = __raw_readl(AK88_VA_L2_UART_BUF_CFG);
+		regval |= (1 << (id - AK88_L2_UART_BUF_START_ID + AK88_L2_UART_BUF_CFG_BUF_START));
+		__raw_writel(regval, AK88_VA_L2_UART_BUF_CFG);
+	}
+
+	local_irq_restore(flags);
+
+}
+EXPORT_SYMBOL(ak88_l2_clr_status);
+
+/**
+ * ak88_l2_set_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ *  @status:	Status to be set (0 ~ 8)
+ */
+void ak88_l2_set_status(u8 id, u8 status)
+{
+	unsigned long regval;
+	unsigned long flags;
+	
+	ak88_l2_assert_buf_id(id);
+
+	if ((id >= AK88_L2_COMMON_BUFFER_NUM) || status > MAX_L2_DMA_STATUS_VALUE)
+		BUG();
+
+	local_irq_save(flags);
+
+	/*
+	 * Enable CPU-controlled buffer function and set L2 buffer `id' status
+	 * status = current number of data in the CPU controlled buffer.
+	 */
+	regval = __raw_readl(AK88_VA_L2_UART_BUF_CFG);
+	regval &= ~(AK88_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK | AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK);
+	regval |= (id << AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_START) | AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		(status << AK88_L2_UART_BUF_CFG_CPU_BUF_NUM_START);
+	__raw_writel(regval, AK88_VA_L2_UART_BUF_CFG);
+
+	/*
+	* Disable CPU-controlled buffer function
+	*/
+	regval = __raw_readl(AK88_VA_L2_UART_BUF_CFG);
+	regval &= ~(AK88_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK | AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		AK88_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK);
+	__raw_writel(regval, AK88_VA_L2_UART_BUF_CFG);
+
+	local_irq_restore(flags);
+
+}
+EXPORT_SYMBOL(ak88_l2_set_status);
diff --git a/arch/arm/mach-ak88/l2mem.c b/arch/arm/mach-ak88/l2mem.c
new file mode 100644
index 00000000000..8b137891791
--- /dev/null
+++ b/arch/arm/mach-ak88/l2mem.c
@@ -0,0 +1 @@
+
diff --git a/arch/arm/mach-ak88/lib_freq.c b/arch/arm/mach-ak88/lib_freq.c
new file mode 100644
index 00000000000..14ea3022ff1
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_freq.c
@@ -0,0 +1,110 @@
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+#include <mach/map.h>
+#include <mach/ak880x_freq.h>
+
+//************************** clock **************************//
+
+unsigned long ak880x_pll1freq_get_default(void)
+{
+	//ref to 0x08000004
+
+	int N_def = 0b00001;	// 1
+	int M_def = 0b010001;	//17
+	unsigned long M = (45 + M_def) * 1000 * 1000;
+	int N = N_def + 1;
+
+	unsigned long freq = (unsigned long)((4 * M) / N);	//(4*62/2)M=124M
+
+	//printk("ak880x_pll1freq_get_default()=%d\n",(u32)freq);
+
+	return freq;
+}
+
+unsigned long ak880x_cpufreq_get_default(void)
+{
+	//ref to 0x08000004
+
+	//bit15,   default :0:   cpu clk = asic clk
+	//bit[8:6],default :000: asic clk =pll1clk
+
+	//return ak880x_pll1freq_get_default();
+	return 124000000;	//124MHZ
+}
+
+unsigned long ak880x_pll1freq_get(void)
+{
+	//return  ak880x_pll1freq_get_default();
+	return 124000000;	//124MHZ
+}
+
+unsigned long ak880x_cpufreq_get(void)
+{
+	//return  ak880x_cpufreq_get_default();
+	return 124000000;	//124MHZ
+}
+
+unsigned long ak880x_asicfreq_get(void)
+{
+	//return ak880x_pll1freq_get_default();
+
+	return 124000000;	//124MHZ
+}
+
+unsigned long ak780x_pll1freq_get_default(void)
+{
+	//ref to 0x08000004
+
+	int N_def = 0b00001;	//1
+	int M_def = 0b00000;	//0
+	unsigned long M = (62 + M_def) * 1000 * 1000;
+	int N = N_def + 1;
+
+	unsigned long freq = (unsigned long)((4 * M) / N);	//(4*62/2)M=124M
+
+	return freq;
+}
+
+unsigned long ak780x_cpufreq_get_default(void)
+{
+	//ref to 0x08000004
+	//bit15,   default :0:   cpu clk = asic clk
+	//bit[8:6],default :000: asic clk =pll1clk/2
+
+	return ak780x_pll1freq_get_default() / 2;
+}
+
+unsigned long ak780x_cpufreq_get(void)
+{
+	return ak780x_cpufreq_get_default();
+}
+
+void ak880x_sdelay(int s_time)
+{
+	unsigned long i, count;
+	count = ak880x_cpufreq_get();	//for seconds
+	count = count / 5;	//each loop consume 5 clock period (SUB,CMP,BNE)
+	for (; s_time > 0; s_time--)
+		for (i = count; i > 0; i--) ;	//SUB,CMP,BNE
+}
+
+void ak880x_msdelay(int ms_time)
+{
+	unsigned long i, count;
+	count = ak880x_cpufreq_get() / 1000;	//for ms
+	count = count / 5;	//each loop consume 5 clock period (SUB,CMP,BNE)
+	for (; ms_time > 0; ms_time--)
+		for (i = count; i > 0; i--) ;	//SUB,CMP,BNE
+}
+
+void ak880x_usdelay(int us_time)
+{
+	unsigned long i, count;
+	count = 124 / 5;	//for us
+
+	for (; us_time > 0; us_time--)
+		for (i = count; i > 0; i--) ;	//SUB,CMP,BNE
+}
diff --git a/arch/arm/mach-ak88/lib_gpio.c b/arch/arm/mach-ak88/lib_gpio.c
new file mode 100644
index 00000000000..0c5fe4ba1c4
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_gpio.c
@@ -0,0 +1,119 @@
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+#include <mach/map.h>
+#include <mach/ak880x_gpio.h>
+#include <mach/lib_l2.h>
+
+//************************** gpio *********************************//
+
+bool gpio_set_dir(int gpiopin /*0~31,32~64,64~95,96~127 */ ,
+		  int set /*0:out,1:in */ )
+{
+	unsigned int group_index;
+	unsigned int bit_offset;
+
+	group_index = (gpiopin >> 5) & 0x3;
+
+	if (group_index > AK88_GPIO_MAX_PIN_NUM)
+		return AK_FALSE;
+
+	bit_offset = gpiopin & 0x1f;
+	if (set)		//direction is IN
+		AKSET_BITS(1 << bit_offset, AK88_GPIO_DIR(group_index));
+	else			//direction is OUT
+		AKCLR_BITS(1 << bit_offset, AK88_GPIO_DIR(group_index));
+
+	//return AK_TRUE;
+	return true;
+}
+
+bool gpio_set_level(int gpiopin /*0~31,32~64,64~95,96~127 */ , int set)
+{
+	unsigned int group_index;
+	unsigned int bit_offset;
+
+	group_index = (gpiopin >> 5) & 0x3;
+
+	if (group_index > AK88_GPIO_MAX_PIN_NUM)
+		return AK_FALSE;
+
+	bit_offset = gpiopin & 0x1f;
+	if (set)		//pull high 
+		AKSET_BITS(1 << bit_offset, AK88_GPIO_OUT(group_index));
+	else			//pull low 
+		AKCLR_BITS(1 << bit_offset, AK88_GPIO_OUT(group_index));
+
+	//return AK_TRUE;
+	return true;
+}
+
+bool gpio_get_level(int gpiopin /*0~31,32~64,64~95,96~127 */ )
+{
+	unsigned int group_index;
+	unsigned int bit_offset;
+	bool ret;
+
+	group_index = (gpiopin >> 5) & 0x3;
+
+	if (group_index > AK88_GPIO_MAX_PIN_NUM)
+		return AK_FALSE;
+
+	bit_offset = gpiopin & 0x1f;
+
+	ret = AKGET_BIT(1 << bit_offset, AK88_GPIO_IN(group_index));
+
+	return ret;
+}
+
+bool gpio_set_output(int gpiopin /*0~31,32~64,64~95,96~127 */ ,
+		     int level /*output level */ )
+{
+	unsigned int group_index;
+	unsigned int bit_offset;
+
+	group_index = (gpiopin >> 5) & 0x3;
+
+	if (group_index > AK88_GPIO_MAX_PIN_NUM)
+		return AK_FALSE;
+
+	//set dir to output
+	bit_offset = gpiopin & 0x1f;
+
+	//direction is OUT, bit=0 for output
+	AKCLR_BITS(1 << bit_offset, AK88_GPIO_DIR(group_index));
+
+	//set output level
+	if (level)		//pull high 
+		AKSET_BITS(1 << bit_offset, AK88_GPIO_OUT(group_index));
+	else			//pull low 
+		AKCLR_BITS(1 << bit_offset, AK88_GPIO_OUT(group_index));
+
+	return true;
+
+}
+
+bool gpio_get_input(int gpiopin /*0~31,32~64,64~95,96~127 */ )
+{
+	unsigned int group_index;
+	unsigned int bit_offset;
+	bool ret;
+
+	group_index = (gpiopin >> 5) & 0x3;
+
+	if (group_index > AK88_GPIO_MAX_PIN_NUM)
+		return AK_FALSE;
+
+	//set dir to input
+	bit_offset = gpiopin & 0x1f;
+
+	//direction is IN, bit=1 for output
+	AKSET_BITS(1 << bit_offset, AK88_GPIO_DIR(group_index));
+
+	//get input level
+	ret = AKGET_BIT(1 << bit_offset, AK88_GPIO_IN(group_index));
+
+	return ret;
+
+}
diff --git a/arch/arm/mach-ak88/lib_l2.c b/arch/arm/mach-ak88/lib_l2.c
new file mode 100644
index 00000000000..733b4a2e1c7
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_l2.c
@@ -0,0 +1,994 @@
+/**
+* @FILENAME: l2.c
+* @BRIEF l2 buffer driver file
+* Copyright (C) 2007 Anyka (Guang zhou) Software Technology Co., LTD
+* @AUTHOR Pumbaa
+* @DATA 2007-09-11
+* @VERSION 1.8
+* @REF please refer to...
+*/
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+#include <mach/map.h>
+#include <mach/lib_l2.h>
+
+#define IDLE_STATE            1
+#define USED_STATE            0
+
+#define BUF_NULL             0xff
+
+typedef struct {
+	unsigned char buf_id;
+	unsigned char usable;
+	unsigned int used_time;
+} L2_INFO;
+
+typedef struct {
+	DEVICE_SELECT device;
+	unsigned char buf_id;
+} DEVICE_INFO;
+
+L2_INFO L2_INFO_TABLE[] = {
+	{0, IDLE_STATE, 0},
+	{1, IDLE_STATE, 0},
+	{2, IDLE_STATE, 0},
+	{3, IDLE_STATE, 0},
+	{4, IDLE_STATE, 0},
+	{5, IDLE_STATE, 0},
+	{6, IDLE_STATE, 0},
+	{7, IDLE_STATE, 0}
+};
+
+DEVICE_INFO DEVICE_INFO_TABLE[] = {
+	{ADDR_USB_BULKOUT, BUF_NULL},
+	{ADDR_USB_BULKIN, BUF_NULL},
+	{ADDR_USB_ISO, BUF_NULL},
+	{ADDR_NFC, BUF_NULL},
+	{ADDR_MMC_SD, BUF_NULL},
+	{ADDR_SDIO, BUF_NULL},
+	{ADDR_RESERVED, BUF_NULL},
+	{ADDR_SPI1_RX, BUF_NULL},
+	{ADDR_SPI1_TX, BUF_NULL},
+	{ADDR_DAC, BUF_NULL},
+	{ADDR_SPI2_RX, BUF_NULL},
+	{ADDR_SPI2_TX, BUF_NULL}
+};
+
+/**
+* @BRIEF initial l2 buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_VOID:
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//define Fraction DMA Address Information Register 's bit map
+#define AHB_FLAG_EN          29
+#define LDMA_FLAG_EN         28
+
+//define DMA Request Register 's bit map
+#define DMA_EN               0
+
+void akl2_init(void)
+{
+	__raw_writel(1 << DMA_EN, AK88_L2CTR_DMAREQ);
+	//0x2002c080
+
+	//yi puzzle: use auto cpu-controlling of buffer status?
+	__raw_writel((1 << LDMA_FLAG_EN) | (1 << AHB_FLAG_EN),
+		     AK88_L2CTR_DMAFRAC);
+	//0x2002c084
+
+	__raw_writel(0xffff00ff, AK88_L2CTR_COMBUF_CFG);
+	//0x2002c088
+
+	__raw_writel(0xf0ff0000, AK88_L2CTR_UARTBUF_CFG);
+	//0x2002c08c
+}
+
+/**
+* @BRIEF allocate a buffer which doesn't used by other device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 *buf_id : the pointer of the variable which storage return buffer id
+* @RETURN T_BOOL: if allocate a buffer successful, return AK_TRUE, otherwise, return AK_FALSE
+* @NOTE: to make sure buffer allocate by this function is avalid, user must check the return value
+*/
+unsigned char l2_alloc_buf(unsigned char *buf_id)
+{
+	unsigned int buffer_nbr = sizeof(L2_INFO_TABLE) / sizeof(L2_INFO);
+	unsigned int used_least_count = 0;
+	unsigned int i;
+	unsigned char first_usable_id = BUF_NULL;
+	unsigned char slct_id = 0;
+
+	for (i = 0; i < buffer_nbr; i++) {
+		if (L2_INFO_TABLE[i].usable == IDLE_STATE)	//find a buffer which hasn't been used
+		{
+			if (first_usable_id == BUF_NULL)	//the first usable buf id
+			{
+				first_usable_id = L2_INFO_TABLE[i].buf_id;
+				used_least_count = L2_INFO_TABLE[i].used_time;
+				slct_id = first_usable_id;
+			}
+			if (L2_INFO_TABLE[i].used_time < used_least_count) {
+				used_least_count = L2_INFO_TABLE[i].used_time;
+				slct_id = L2_INFO_TABLE[i].buf_id;
+			}
+		}
+	}
+
+	if (first_usable_id == BUF_NULL) {
+		return AK_FALSE;	//can't find any buffer which hasn't been used
+		//return 0;
+	} else			//malloc a buffer successfully
+	{
+		L2_INFO_TABLE[slct_id].usable = USED_STATE;
+		L2_INFO_TABLE[slct_id].used_time++;
+		if (L2_INFO_TABLE[slct_id].used_time == 0) {
+			for (i = 0; i < buffer_nbr; i++)
+				L2_INFO_TABLE[i].used_time = 0;	//clear all buffer's used_time
+		}
+		*buf_id = slct_id;
+		return AK_TRUE;
+		//return 1;
+	}
+}
+
+/**
+* @BRIEF set device information
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device to be select for change it's information
+* @PARAM T_U8 buf_id0: a buffer of device used
+* @PARAM T_U8 buf_id0: anther buffer of device used
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+void l2_set_devinfo(DEVICE_SELECT dev_slct, unsigned char buf_id,
+		    unsigned char buf_id1)
+{
+	DEVICE_INFO_TABLE[(unsigned char)dev_slct].buf_id = buf_id;
+}
+
+/**
+* @BRIEF free a or two buffer(s) which used by a device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+void l2_free_buf(DEVICE_SELECT dev_slct)
+{
+	unsigned int device_nbr =
+	    sizeof(DEVICE_INFO_TABLE) / sizeof(DEVICE_INFO);
+	unsigned int i;
+	unsigned char free_id;
+
+	free_id = DEVICE_INFO_TABLE[(unsigned char)dev_slct].buf_id;
+	if (free_id != BUF_NULL) {
+		DEVICE_INFO_TABLE[(unsigned char)dev_slct].buf_id = BUF_NULL;
+		for (i = 0; i < device_nbr; i++) {
+			if (DEVICE_INFO_TABLE[i].buf_id == free_id)
+				break;
+		}
+
+		if (i == device_nbr)	//there isnot device use this buffer
+		{
+			L2_INFO_TABLE[free_id].usable = IDLE_STATE;
+		}
+	}
+}
+
+/**
+* @BRIEF set a buffer as device buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+void l2_slct_buf(DEVICE_SELECT dev_sel, unsigned char buf_id)
+{
+	volatile unsigned int reg_id;
+	volatile unsigned int base_bit;
+	volatile unsigned int reg_value;
+
+	if ((unsigned char)dev_sel > 9) {
+		reg_id = (unsigned int)AK88_L2CTR_ASSIGN_REG2;	//0x2002c094
+		base_bit = ((unsigned char)dev_sel - 10) * 3;
+	} else {
+		reg_id = (unsigned int)AK88_L2CTR_ASSIGN_REG1;	//0x2002c090
+		base_bit = (unsigned char)dev_sel *3;
+	}
+
+	reg_value = __raw_readl(reg_id);
+	reg_value &= ~(0x7 << base_bit);	//assume device select buffer 0
+	reg_value |= ((buf_id & 0x7) << base_bit);	//according buf_id to adjust selcted buf no
+	__raw_writel(reg_value, reg_id);
+}
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+void l2_combuf_dma(unsigned int ram_addr, unsigned char buf_id,
+		   unsigned int tran_byte,
+		   unsigned char tran_dir /*1:write(send),0:read(recv) */ )
+{
+	unsigned int tran_nbr;	//transfer times
+	volatile unsigned int reg_value;
+	volatile unsigned int reg_id;
+
+	tran_nbr = tran_byte >> 6;
+
+	//1).set ram_addr to ANYKA_L2_DMAADDR
+	reg_value = ram_addr & 0xfffffff;
+	reg_id = (unsigned int)AK88_L2CTR_DMAADDR + (buf_id << 2);	//0x2002c000 -> 0x2002c03c
+	//0x2002c000 -> 0x2002c03c for buffer 0 to 15 (32-bit for each)
+
+	__raw_writel(reg_value, reg_id);
+
+	//2).set dma times to ANYKA_L2_DMACNT
+	reg_value = tran_nbr & 0xff;
+	reg_id = (unsigned int)AK88_L2CTR_DMACNT + (buf_id << 2);	//0x2002c040 -> 0x2002c07c
+	//0x2002c040 -> 0x2002c07c for buffer 0 to 15 (32-bit for each)
+	//need operating DMA times,
+
+	__raw_writew((volatile unsigned short)reg_value, reg_id);
+
+	//3).sele common DMA buf number(0 to 8),and sele write/read by ANYKA_L2_COMBUF_CFG
+	reg_value = __raw_readl(AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+	//0x2002c088
+
+	if (tran_dir)		//write(send)
+		reg_value |= (1 << (8 + buf_id));
+	else
+		reg_value &= ~(1 << (8 + buf_id));
+
+	__raw_writel(reg_value, AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+
+	//4).send request dma commond by ANYKA_L2_DMAREQ
+	reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+	//0x2002c080
+
+	reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req
+	reg_value |= (1 << (24 + buf_id));
+
+	__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+}
+
+/**
+* @BRIEF transfer fraction data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+void l2_combuf_fracdma(unsigned int ram_addr, unsigned char buf_id,
+		       unsigned char buf_offset, unsigned int tran_byte,
+		       unsigned char tran_dir)
+{
+	unsigned int buf_addr;
+	volatile unsigned int reg_value;
+
+	//1).set ram_addr to ANYKA_L2_DMAFRAC
+	reg_value = __raw_readl(AK88_L2CTR_DMAFRAC);	//0x2002c084
+	reg_value &= ~0xfffffff;
+	reg_value |= (ram_addr & 0xfffffff);
+	__raw_writel(reg_value, AK88_L2CTR_DMAFRAC);	//0x2002c084
+
+	//2).set frac trans len, l2 buf_id,buf_offset in l2 buf, in 0x2002c080
+
+	buf_addr = ((buf_id & 0x7) << 3) | (buf_offset & 0x7);
+	//reg_value = inl(L2_DMA_REQ); 
+	//bit[7:1]:Frac_DMA_L2_addr, DMA buf contain 8's 512buf,and each 512buf contain 8's
+	//64subbuf. Frac_DMA_L2_addr point the buf_id of 8's of 512buf,add the sub buf_id 
+	//if 8's of 64subbuf in 512buf align
+	//bit[15:10]:Frac_DMA_len,the real remaider in 64subbuf
+
+	reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+
+	reg_value &= ~((0x7f << 1) | (0x3f << 10));
+	reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req        
+	if (tran_dir)
+		reg_value |=
+		    (1 << 9) | (1 << 8) | (buf_addr << 1) | ((tran_byte - 1) <<
+							     10);
+	else {
+		reg_value &= ~(1 << 8);
+		reg_value |=
+		    (1 << 9) | (buf_addr << 1) | ((tran_byte - 1) << 10);
+	}
+
+	__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+}
+
+/**
+* @BRIEF wait DMA transfer data between memory and common buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+void l2_wait_combuf_dmafinish(unsigned char buf_id)
+{
+
+	while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << (24 + buf_id))) ;	//0x2002c080
+
+	//0x2002c080 bit[31:24]: when this bit is set by CPU,the buf(buf_id) DMA operation
+	//                       enabled.And this bit is cleared automatically when the 
+	//                       requested DMA operation has been finished successfully.
+
+}
+
+/**
+* @BRIEF wait Fraction DMA transfer data between memory and common buffer finish 
+* @AUTHOR YiRuoxiang
+* @DATE 2008-02-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+void l2_wait_combuf_frac_dmafinish(unsigned char buf_id)
+{
+	volatile unsigned int dma_conf;
+
+
+	do {
+		dma_conf = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+	} while ((dma_conf & (1 << 9)));
+
+	//0x2002c080,bit9:Frac_DMA_rea:Fraction DMA request signal.
+	//                when this bit is set by CPU,the fraction DMA operation is enabled.
+	//                and this bit is cleared automatically when the requested DMA 
+	//                operation has been finished successfully.
+}
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma and fraction dma
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: 1. from RAM to buffer 0. from buffer to RAM
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 512
+*/
+
+extern void mmu_clean_invalidate_dcache(void);
+
+void l2_combuf_tran_data(unsigned int ram_addr, unsigned char buf_id,
+			 unsigned int tran_byte, unsigned char tran_dir)
+{
+
+	unsigned int tran_nbr = tran_byte >> 6;
+	unsigned int fraction_nbr = tran_byte % 64;
+	unsigned int buf_addr;
+	volatile unsigned int reg_value;
+	volatile unsigned int reg_id;
+
+	mmu_clean_invalidate_dcache();
+
+#if 0
+	__asm__ __volatile__("mmu_clean_invalidate_dcache: " "\n\t"
+			     "mrc p15,0,r15,c7,c14,3 "
+			     "bne mmu_clean_invalidate_dcache "
+			     "mov pc,lr ":::"cc");
+#endif
+
+	if (tran_nbr) {
+		reg_value = ram_addr & 0xfffffff;
+		reg_id = (unsigned int)AK88_L2CTR_DMAADDR + (buf_id << 2);	//0x2002c000 -> 0x2002c03c  
+		__raw_writel(reg_value, reg_id);
+
+		reg_value = tran_nbr & 0xff;
+		reg_id = (unsigned int)AK88_L2CTR_DMACNT + (buf_id << 2);	//0x2002c040 -> 0x2002c07c  
+		__raw_writew((unsigned short)reg_value, reg_id);
+
+		reg_value = __raw_readl(AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+		if (tran_dir)	//write(send)
+			reg_value |= (1 << (8 + buf_id));
+		else
+			reg_value &= ~(1 << (8 + buf_id));
+		__raw_writel(reg_value, AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+
+		reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+		reg_value &= ~((1 << 9) | (((unsigned int)0xffff) << 16));	//clear other buf req
+		reg_value |= (1 << (24 + buf_id));
+		__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+		//wait combuf dma finish
+		while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << (24 + buf_id)))	//0x2002c080
+		{
+		}
+	}
+
+	if (fraction_nbr) {
+		reg_value = __raw_readl(AK88_L2CTR_DMAFRAC);	//0x2002c084
+		reg_value &= ~0xfffffff;
+		reg_value |= ((ram_addr + (tran_nbr << 6)) & 0xfffffff);	//frac begin addr
+		__raw_writel(reg_value, AK88_L2CTR_DMAFRAC);	//0x2002c084 
+
+		buf_addr = ((buf_id & 0x7) << 3) | ((tran_nbr % 8) & 0x7);
+		//bit[7:1]:Frac_DMA_L2_addr, DMA buf contain 8's 512buf,and each 512buf contain 8's
+		//64subbuf. Frac_DMA_L2_addr point the buf_id of 8's of 512buf,add the sub buf_id 
+		//if 8's of 64subbuf in 512buf align
+		//bit[15:10]:Frac_DMA_len,the real remaider in 64subbuf
+
+		reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+
+		reg_value &= ~((0x7f << 1) | (0x3f << 10));
+		reg_value &= ~((1 << 9) | (((unsigned int)0xffff) << 16));	//clear other buf req    
+
+		if (tran_dir)
+			reg_value |=
+			    (1 << 9) | (1 << 8) | (buf_addr << 1) |
+			    ((fraction_nbr - 1) << 10);
+		else {
+			reg_value &= ~(1 << 8);
+			reg_value |=
+			    (1 << 9) | (buf_addr << 1) | ((fraction_nbr - 1) <<
+							  10);
+		}
+
+		__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+		while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << 9))	//0x2002c080 //wait dma finish
+		{
+		}
+	}
+
+	if ((tran_dir == 1) && (tran_byte % 512 != 0)
+	    && (tran_byte % 512 <= 512 - 4)) {
+		*(volatile unsigned int *)(AK88_VA_L2BUF + buf_id * 512 +
+					   0x1fc) = 0;
+	}			//0x48000000
+}
+
+void l2_combuf_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+			     unsigned int tran_byte, unsigned char tran_dir)
+{
+	volatile unsigned int align_4_len, len_remian_4, buf_addr, i, tmp,
+	    buf_status;
+	unsigned int *p_buf_int;
+	unsigned char *buf = (unsigned char *)ram_addr;
+
+	//buf_addr = L2_BUF_MEM_BASE_ADDR + (buf_id << 9);  //0x48000000 + buf_id*512
+	buf_addr = (unsigned int)AK88_VA_L2BUF + (buf_id << 9);	// 512 = (1<<9) //0x48000000 + buf_id*512
+
+	align_4_len = tran_byte & (~0x3);
+	len_remian_4 = tran_byte % 4;
+
+	if (tran_dir == MEM2BUF)	//from SDRAM to L2, write(send)
+	{
+		do {
+			buf_status = __raw_readl(AK88_L2CTR_STAT_REG1);	//0x2002c0a0
+		} while ((buf_status & (0xf << (4 * buf_id))) != 0);
+
+		if ((unsigned int)buf % 4 == 0)	// if the buf is the even then it can 4 bytes write.
+		{
+			p_buf_int = (unsigned int *)buf;
+			for (i = 0; i < align_4_len; i = i + 4) {
+				*(volatile unsigned int *)(buf_addr + i) = *(p_buf_int++);	//SDRAM to L2
+			}
+
+			if (len_remian_4 != 0) {
+				tmp = 0;
+				for (i = 0; i < len_remian_4; i++)
+					tmp =
+					    tmp +
+					    (buf[align_4_len + i] << (i * 8));
+
+				*(volatile unsigned int *)(buf_addr + align_4_len) = tmp;	//SDRAM to L2
+			}
+		} else		// if the buf is the odd then it can't 4 bytes write.
+		{
+			for (i = 0; i < align_4_len; i = i + 4) {
+				tmp = (buf[i] | (buf[i + 1] << 8) | (buf[i + 2] << 16) | (buf[i + 3] << 24));	//little endian
+				*(volatile unsigned char *)(buf_addr + i) = tmp;	//SDRAM to L2
+			}
+			tmp = 0;
+			if (len_remian_4 != 0) {
+				for (i = 0; i < len_remian_4; i++) {
+					tmp =
+					    tmp +
+					    (buf[align_4_len + i] << (i * 8));
+				}
+				*(volatile unsigned char *)(buf_addr + align_4_len) = tmp;	//SDRAM to L2
+			}
+		}
+
+		if (tran_byte <= 512 - 4)
+			*(volatile unsigned int *)(buf_addr + 0x1fc) = 0;	//end flag
+
+	} else			//from L2 to SDRAM , read/(receive)
+	{
+		if (tran_byte == 512) {
+			do {
+				buf_status = __raw_readl(AK88_L2CTR_STAT_REG1);	//0x2002c0a0
+			} while ((buf_status & (0xf << (4 * buf_id))) !=
+				 (8 << (4 * buf_id)));
+		}
+		if ((unsigned int)buf % 4 == 0)	// if the buf is the even then it can 4 bytes write.
+		{
+			p_buf_int = (unsigned int *)buf;
+			for (i = 0; i < align_4_len; i = i + 4)
+				*(p_buf_int++) = *(volatile unsigned int *)(buf_addr + i);	//L2 to SDRAM
+
+			if (len_remian_4 != 0) {
+				tmp =
+				    *(volatile unsigned int *)(buf_addr +
+							       align_4_len);
+				for (i = 0; i < len_remian_4; i++)
+					buf[align_4_len + i] = (tmp >> (8 * i)) & 0xff;	//L2 to SDRAM
+			}
+		} else		// if the buf is the odd then it can't 4 bytes write. 
+		{
+			for (i = 0; i < align_4_len; i = i + 4) {
+				tmp = *(volatile unsigned int *)(buf_addr + i);	//L2 to SDRAM 
+
+				buf[i] = (tmp & 0xff);
+				buf[i + 1] = ((tmp >> 8) & 0xff);
+				buf[i + 2] = ((tmp >> 16) & 0xff);
+				buf[i + 3] = ((tmp >> 24) & 0xff);
+			}
+
+			if (len_remian_4 != 0) {
+				tmp = *(volatile unsigned int *)(buf_addr + align_4_len);	//L2 to SDRAM  
+				for (i = 0; i < len_remian_4; i++)
+					buf[align_4_len + i] =
+					    (tmp >> (8 * i)) & 0xff;
+			}
+		}
+
+		//yi puzzle: manually set buffer status, should change to 64B in ak7801
+		if (tran_byte <= 512 - 4)	//clear flag
+			l2_clr_combuf_flag(buf_id);
+	}
+}
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+void l2_uartbuf_dma(unsigned int ram_addr, unsigned char uart_id,
+		    unsigned int tran_byte, unsigned char tran_dir)
+{
+	volatile unsigned int tran_nbr;
+	volatile unsigned int reg_value;
+	volatile unsigned int buf_id;
+	volatile unsigned int reg_id;
+
+	tran_nbr = tran_byte >> 6;
+
+	if (tran_dir)
+		buf_id = 8 + uart_id * 2;
+	else
+		buf_id = 8 + uart_id * 2 + 1;
+
+	reg_value = ram_addr & 0xfffffff;
+	reg_id = (unsigned int)AK88_L2CTR_DMAADDR + (buf_id << 2);	//0x2002c000 to 0x2002c03c
+	__raw_writel(reg_value, reg_id);
+
+	reg_value = tran_nbr & 0xff;
+	reg_id = (unsigned int)AK88_L2CTR_DMACNT + (buf_id << 2);	//0x2002c040 to 0x2002c07c
+	__raw_writew((volatile unsigned short)reg_value, reg_id);
+
+	reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+	reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req
+	reg_value |= (1 << (8 + buf_id));
+	__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+}
+
+/**
+* @BRIEF transfer fraction data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+void l2_uartbuf_fracdma(unsigned int ram_addr, unsigned char uart_id,
+			unsigned char buf_offset, unsigned int tran_byte,
+			unsigned char tran_dir)
+{
+	unsigned int buf_addr;
+	volatile unsigned int reg_value;
+	unsigned int buf_id;
+
+	if (tran_dir)
+		buf_id = 8 + uart_id * 2;
+	else
+		buf_id = 8 + uart_id * 2 + 1;
+
+	reg_value = __raw_readl(AK88_L2CTR_DMAFRAC);	//0x2002c084
+	reg_value &= ~(0x3ffffff);
+	reg_value |= (ram_addr & 0x3ffffff);
+	__raw_writel(reg_value, AK88_L2CTR_DMAFRAC);	//0x2002c084
+
+	buf_addr = (0x40 + ((buf_id - 8) << 1)) | buf_offset;	//0x40=64
+	reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+	reg_value &= ~((0x7f << 1) | (0x3f << 10));
+	reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req        
+	if (tran_dir)
+		reg_value |=
+		    (1 << 9) | (1 << 8) | (buf_addr << 1) | ((tran_byte - 1) <<
+							     10);
+	//bit[7:1]:Frac_DMA_L2_add
+	//bit[15:0](0x2002c080):Frac_DMD_len
+	else {
+		reg_value &= ~(1 << 8);
+		reg_value |=
+		    (1 << 9) | (buf_addr << 1) | ((tran_byte - 1) << 10);
+	}
+	__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+}
+
+/**
+* @BRIEF wait DMA transfer data between memory and uart buffer finish 
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 tran_dir: the transfer direction
+*/
+void l2_wait_uartbuf_dmafinish(unsigned char uart_id, unsigned char tran_dir)
+{
+	//T_U8 buf_id;
+	unsigned char buf_id;
+
+	if (tran_dir)
+		buf_id = 8 + uart_id * 2;
+	else
+		buf_id = 8 + uart_id * 2 + 1;
+
+	//while(inl(L2_DMA_REQ)&(1<<(8+buf_id)))
+	while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << (8 + buf_id)))	//0x2002c080
+	{
+	}
+}
+
+/**
+* @BRIEF wait fraction DMA transfer data between memory and buffer finish 
+*/
+void l2_wait_frac_dmafinish(void)
+{
+	while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << 9))	//0x2002c080
+	{
+	}
+}
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma and fraction dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 128
+*/
+void l2_uartbuf_tx_data(unsigned int ram_addr, unsigned char uart_id,
+			unsigned int tran_byte)
+{
+
+	unsigned int tran_nbr = tran_byte >> 6;
+	unsigned int fraction_nbr = tran_byte % 64;
+	unsigned int buf_addr;
+	volatile unsigned int reg_value;
+	volatile unsigned int reg_id;
+	unsigned int buf_id;
+
+	buf_id = 8 + uart_id * 2;
+
+	if (tran_nbr) {
+		reg_value = ram_addr & 0xfffffff;
+		//reg_id = L2_DMA_ADDR+ (buf_id<<2);    //0x2002c000 => 0x2002c03c
+		reg_id = (unsigned int)AK88_L2CTR_DMAADDR + (buf_id << 2);	//0x2002c000 => 0x2002c03c
+		__raw_writel(reg_value, reg_id);
+
+		reg_value = tran_nbr & 0xff;
+		reg_id = (unsigned int)AK88_L2CTR_DMACNT + (buf_id << 2);	//0x2002c040 => 0x2002c07c
+		__raw_writel((volatile unsigned short)reg_value, reg_id);
+
+		reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+		reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req
+		reg_value |= (1 << (8 + buf_id));
+		__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+		//wait uart dma finish
+		//while(inl(L2_DMA_REQ)&(1<<(8+buf_id)))    //wait dma finish
+		while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << (8 + buf_id)))	//0x2002c080   //wait dma finish
+		{
+		}
+	}
+	if (fraction_nbr) {
+		reg_value = __raw_readl(AK88_L2CTR_DMAFRAC);	//0x2002c084
+		reg_value &= ~(0x3ffffff);
+		reg_value |= ((ram_addr + (tran_nbr << 6)) & 0x3ffffff);
+		__raw_writel(reg_value, AK88_L2CTR_DMAFRAC);	//0x2002c084
+
+		buf_addr =
+		    (0x40 + ((buf_id - 8) << 1)) | ((tran_nbr % 2) & 0x1);
+		reg_value = __raw_readl(AK88_L2CTR_DMAREQ);	//0x2002c080
+		reg_value &= ~((0x7f << 1) | (0x3f << 10));
+		reg_value &= ~((1 << 9) | (0xffffUL << 16));	//clear other buf req        
+		reg_value |=
+		    (1 << 9) | (1 << 8) | (buf_addr << 1) | ((fraction_nbr - 1)
+							     << 10);
+		__raw_writel(reg_value, AK88_L2CTR_DMAREQ);	//0x2002c080
+
+		//wait frac dma finish
+		//while(inl(L2_DMA_REQ)&(1<<9))        //wait dma finish
+		while (__raw_readl(AK88_L2CTR_DMAREQ) & (1 << 9))	//0x2002c080   //wait dma finish
+		{
+		}
+	}
+}
+
+/**
+* @BRIEF transfer data between memory and l2 buffer with CPU mode
+* @NOTE: if buffer is common buffer, the max value of tran_byte should be 512, if buffer is uart buffer, the
+        max value of tran_byte should be 128.
+*/
+//T_VOID L2_TranDataCPU(T_U32 ram_addr, T_U8 buf_id, T_U32 buf_offset, T_U32 tran_byte, T_U8 tran_dir)
+void l2_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+		      unsigned int buf_offset, unsigned int tran_byte,
+		      unsigned char tran_dir /*1=write(send),0=read(recv) */ )
+{
+ 	unsigned int tran_nbr;
+	unsigned int frac_nbr;
+	volatile unsigned int temp_ram = 0, temp_buf = 0;
+	unsigned int i, j;
+	unsigned int buf_addr;
+
+	if (buf_id < 8)		//common buffer
+		buf_addr = (unsigned int)AK88_VA_L2BUF + (buf_id << 9);	//0x48000000 + (buf_id<<9);
+	else if (buf_id < 16)	//uart buffer
+		buf_addr =
+		    (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  +
+		    ((buf_id - 8) << 7);
+	else if (buf_id == 16)	//usb host buffer
+		buf_addr = (unsigned int)AK88_VA_L2BUF + 6144 /*12 * 512 */ ;
+	else if (buf_id <= 18)	//usb buffer
+		buf_addr =
+		    (unsigned int)AK88_VA_L2BUF + 6400 /*12 * 512 + 256 */  +
+		    ((buf_id - 17) << 6);
+	else {
+		printk("invalid buf id %d\n", buf_id);
+		return;
+	}
+
+	buf_addr += buf_offset;
+	tran_nbr = tran_byte >> 2;
+	frac_nbr = tran_byte % 4;	//frac_nbr = 1 ~ 3
+
+	if (tran_dir)		//write(send)
+	{			//memory to buffer ,write
+		if (ram_addr % 4)	//ram_addr isn't 4 bytes align
+		{
+			for (i = 0; i < tran_nbr; i++) {
+				temp_ram = 0;
+				for (j = 0; j < 4; j++)
+					temp_ram |=
+					    ((read_ramb(ram_addr + i * 4 + j))
+					     << (j * 8));
+				write_buf(temp_ram, (buf_addr + i * 4));
+			}
+			if (frac_nbr) {
+				temp_ram = 0;
+				for (j = 0; j < frac_nbr; j++)
+					temp_ram |=
+					    ((read_ramb
+					      (ram_addr + tran_nbr * 4 +
+					       j)) << (j * 8));
+				write_buf(temp_ram, (buf_addr + tran_nbr * 4));
+			}
+		} else		//4 bytes align
+		{
+			for (i = 0; i < tran_nbr; i++) {
+				write_buf(read_raml(ram_addr + i * 4),
+					  (buf_addr + i * 4));
+			}
+			if (frac_nbr) {
+				write_buf(read_raml(ram_addr + tran_nbr * 4),
+					  (buf_addr + tran_nbr * 4));
+			}
+		}
+	} else			//read(recv)
+	{
+		if (ram_addr % 4)	//not 4 byte align
+		{
+			for (i = 0; i < tran_nbr; i++) {
+				temp_buf = read_buf(buf_addr + i * 4);
+				for (j = 0; j < 4; j++) {
+					write_ramb((volatile unsigned
+						    char)((temp_buf >> j *
+							   8) & 0xff),
+						   (ram_addr + i * 4 + j));
+				}
+			}
+			if (frac_nbr) {
+				temp_buf = read_buf(buf_addr + tran_nbr * 4);
+				for (j = 0; j < frac_nbr; j++) {
+					write_ramb((unsigned
+						    char)((temp_buf >> j *
+							   8) & 0xff),
+						   (ram_addr + tran_nbr * 4 +
+						    j));
+				}
+			}
+		} else		//4 byte align
+		{
+			for (i = 0; i < tran_nbr; i++) {
+				write_raml(read_buf(buf_addr + i * 4),
+					   (ram_addr + i * 4));
+			}
+			if (frac_nbr)	//frac_nbr = 1 ~ 3
+			{
+				temp_buf = read_buf(buf_addr + tran_nbr * 4);
+				temp_ram = read_raml(ram_addr + tran_nbr * 4);
+				temp_buf &= ((1 << (frac_nbr * 8 + 1)) - 1);	//get frac_nbr valid bits(low bits)
+				temp_ram &= ~((1 << (frac_nbr * 8 + 1)) - 1);	//clear frac_nbr bits(low bits),keep original ram high bits
+				temp_ram |= temp_buf;	//merge original bits and frac_nbr bits
+				write_raml(temp_ram, (ram_addr + tran_nbr * 4));
+			}
+		}
+	}
+}
+
+/**
+* @BRIEF transfer data from a buffer to another buffer
+* @NOTE: all the parameter must be multiple of 4 bytes
+*/
+//T_VOID L2_LocalDMA(T_U32 dst_addr, T_U32 src_addr, T_U32 tran_byte)
+void l2_localdma(unsigned int dst_addr, unsigned int src_addr,
+		 unsigned int tran_byte)
+{
+	//T_U32 reg_value;
+	volatile unsigned int reg_value;
+
+	reg_value =
+	    ((src_addr & 0x1ffc) >> 2) | (((dst_addr & 0x1ffc) >> 2) << 11) |
+	    (((tran_byte >> 2) & 0xff) << 22) | (1 << 30);
+ 	__raw_writel(reg_value, AK88_L2CTR_LDMA_CFG);	// 0x2002c098
+
+ 	while (__raw_readl(AK88_L2CTR_LDMA_CFG) & (1 << 30))	// 0x2002c098
+	{
+	}
+}
+
+/**
+* @BRIEF forcibly set a common buffer flag
+* @NOTE: buffer id should be 0~7
+*/
+
+void l2_set_combuf_flag(unsigned char buf_id)
+{
+ 	volatile unsigned int reg_value;
+
+	//select the buf and set the buf full
+ 	reg_value = __raw_readl(AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+	reg_value &= (~0xff);
+	reg_value |= (buf_id | (1 << 3) | (8 << 4));
+	//outl(reg_value, L2_UARTBUF_CFG);
+	__raw_writel(reg_value, AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+ 
+	//deselect the buf
+ 	reg_value = __raw_readl(AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+	reg_value &= (~0xff);
+ 	__raw_writel(reg_value, AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+
+	//printk("L2_BUF_STATE2 = %x\n", *(volatile unsigned int*)(L2_BUF_STATE) );
+}
+
+void l2_change_set_flag(unsigned char buf_id, unsigned char set_status_flag)
+{
+ 	volatile unsigned int temp;
+
+	if (set_status_flag) {
+ 		temp = __raw_readl(AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+		temp |= buf_id | (1 << 3) | (set_status_flag << 4);
+ 		__raw_writel(temp, AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+	}
+}
+
+/**
+* @BRIEF forcibly clear a common buffer flag
+* @NOTE: buffer id should be 0~7
+*/
+void l2_clr_combuf_flag(unsigned char buf_id)	//buf_id = 0 ~ 15
+{
+	volatile unsigned int reg_value;
+
+
+	if (buf_id <= 7) {
+		reg_value = __raw_readl(AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+		reg_value |= 1 << (buf_id + 24);
+		//bit[31:24]:bufn_flag_clr
+		//bit24:buf0_flag_clr,1=To clear buf0 status flag
+		//outl(reg_value, L2_COMBUF_CFG);
+		__raw_writel(reg_value, AK88_L2CTR_COMBUF_CFG);	//0x2002c088
+	} else {
+		reg_value = __raw_readl(AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+		//reg_value |= (1<<(buf_id + 16)); ?
+		reg_value |= (1 << (buf_id + 8));
+		//bit[23:16] 
+		//bit16:U1_Tx_clr,1=To clear UART1 TX Buf status flag(buf_id=8)
+		//bit17:U1_Rx_clr,1=To clear UART1 RX Buf status flag(buf_id=9)
+
+		__raw_writel(reg_value, AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+	}
+}
+
+/**
+* @BRIEF forcibly clear a uart buffer status to 0
+* @NOTE: buffer id should be 8~15
+*/
+void l2_clr_uartbuf_status(unsigned char buf_id /*8~15 */ )
+{
+	volatile unsigned int reg_value;
+
+	reg_value = __raw_readl(AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c
+	reg_value |= (1 << (8 + buf_id));	//buf_id = 8 ~ 15
+	//bit[23:16] 
+	//bit16:U1_Tx_clr,1=To clear UART1 TX Buf status flag(buf_id=8)
+	//bit17:U1_Rx_clr,1=To clear UART1 RX Buf status flag(buf_id=9)
+	//outl(reg_value, L2_UARTBUF_CFG);
+	__raw_writel(reg_value, AK88_L2CTR_UARTBUF_CFG);	//0x2002c08c 
+}
+
+/**
+* @BRIEF return a common buffer current flag 
+* @RETURN T_BOOL: if return flag is 1, it mean buffer is full, otherwise mean buffer is empty 
+* @NOTE: buffer id should be 0~7
+*/
+unsigned char l2_combuf_flag(unsigned char buf_id)	//buf_id = 0 ~ 7
+{
+	//return (T_U8)((inl(L2_STAT_REG1)>>(buf_id<<2))&0xf);
+	return (volatile unsigned char)((__raw_readl(AK88_L2CTR_STAT_REG1) >> (buf_id << 2)) & 0xf);	//0x2002c0a0
+}
+
+/**
+* @BRIEF return a uart buffer current status 
+* @NOTE: buffer id should be 8~15
+*/
+unsigned char l2_uartbuf_status(unsigned char buf_id)	//buf_id = 8 ~ 15
+{
+	//return (T_U8)((inl(L2_STAT_REG2)>>((buf_id-8)<<1))&0x3);  //0x2002c0a8
+	return (volatile unsigned char)((__raw_readl(AK88_L2CTR_STAT_REG2) >> ((buf_id - 8) << 1)) & 0x3);	//0x2002c0A8
+}
+
+//#endif
+
diff --git a/arch/arm/mach-ak88/lib_lcd.c b/arch/arm/mach-ak88/lib_lcd.c
new file mode 100644
index 00000000000..53205fc2e14
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_lcd.c
@@ -0,0 +1,1748 @@
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/gfp.h>
+
+#include <video/anyka_lcdc.h>
+
+#include <asm/io.h>
+
+#include <mach/map.h>
+#include <mach/lib_l2.h>
+#include <mach/ak880x_gpio.h>
+#include <mach/ak880x_freq.h>
+#include <mach/lib_lcd.h>
+
+#if 1
+//static struct TFT_LCD_TIMING_INFO hsd070idw1_a10 = {
+static struct tft_lcd_timing_info hsd070idw1_a10 = {
+
+	.bus_width = 24,
+	.interlace = 1,		//1:no interlace
+	.hvg_pol = 0xe,		//h_sync(bit2),v_sync(bit1),vogate(bit0) polarity,0=positive,1=negative
+	.rgb_bit = 0x0888,	//RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+
+	.clock_hz = 30000000,	//(30M)  //bit clock, clock cycle,unit HZ
+
+	.h_sync_hz = 15711,	//??       //h_sync cycle,unit HZ
+	.v_sync_001hz = 5885,	//v_sync cycle,unit 0.01HZ
+
+	.h_tot_clk = 1058,	//horizontal total cycle,unit clock
+	.h_disp_clk = 800,	//horizontal display cycle,unit clock
+	.h_front_porch_clk = 170,	//right_margin //horizontal front porch,unit clock
+	.h_pulse_width_clk = 48,	//horizontal pulse width,unit clock
+	.h_back_porch_clk = 40,	//left_margin //horizontal back porch,unit clock
+
+	.v_tot_clk = 553,	//vertical   total cycle,unit h_sync
+	.v_disp_clk = 480,	//vertical   display cycle,unit h_sync
+	.v_front_porch_clk = 40,	//lower_margin //vertical   front porch,unit clock
+	.v_pulse_width_clk = 4,	//vertical   pulse width,unit clock
+	.v_back_porch_clk = 29,	//upper_margin//vertical   back porch,unit clock
+
+	.name = "HSD070IDW1-A00",
+
+};
+#endif
+
+static struct tft_lcd_timing_info q07021_701 = {
+
+	.bus_width = 24,
+	.interlace = 1,		//1:no interlace
+	.hvg_pol = 0xe,		//h_sync(bit2),v_sync(bit1),gate(bit0) polarity
+	.rgb_bit = 0x0888,	//RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+
+	.clock_hz = 40000000,	//(30M)  //bit clock, clock cycle,unit HZ
+
+	.h_sync_hz = 15711,	//??       //h_sync cycle,unit HZ
+	.v_sync_001hz = 5885,	//v_sync cycle,unit 0.01HZ
+
+	.h_tot_clk = 1000,	//horizontal total cycle,unit clock
+	.h_disp_clk = 800,	//horizontal display cycle,unit clock
+	.h_front_porch_clk = 112,	//horizontal front porch,unit clock
+	.h_pulse_width_clk = 48,	//horizontal pulse width,unit clock
+	.h_back_porch_clk = 88,	//horizontal back porch,unit clock
+
+	.v_tot_clk = 660,	//vertical   total cycle,unit h_sync
+	.v_disp_clk = 600,	//vertical   display cycle,unit h_sync
+	.v_front_porch_clk = 21,	//vertical   front porch,unit clock
+	.v_pulse_width_clk = 3,	//vertical   pulse width,unit clock
+	.v_back_porch_clk = 39,	//vertical   back porch,unit clock
+
+	.name = "Q07021-701",
+
+};
+
+static LCD_IF_MODE if_mode;
+
+static u32 disp_buf_size;
+
+static struct lcd_size lcd_size;
+
+static struct display_ram display_ram;
+
+static struct picture_area usr_rgb_area;
+
+void lcd_print_reg(void)
+{
+	printk("LCD_TOP_CONFIGURE 0x20010000 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0000));
+	printk("LCD_MPU_1 0x20010004 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0004));
+	printk("LCD_RGB_CONTROL 0x20010014 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0014));
+	printk("RGB_BACKGROUND 0x2001003C =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x003C));
+
+	printk("Y1_ADDR 0x2001005C =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x005C));
+	printk("U1_ADDR 0x20010060 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0060));
+	printk("V1_ADDR 0x20010064 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0064));
+
+	printk("YUV1_H_INFO 0x20010068 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0068));
+	printk("YUV1_V_INFO 0x2001006C =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x006C));
+	printk("YUV1_SCALE_INFO 0x20010070 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0070));
+	printk("YUV1_DISPLAY_INFO 0x20010074 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0074));
+	printk("YUV1_VIRTUAL_SIZE 0x20010078 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0078));
+	printk("YUV1_VIRTUAL_OFFSET 0x2001007C =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x007C));
+
+	printk("Y2_ADDR 0x20010080 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0080));
+	printk("U2_ADDR 0x20010084 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0084));
+	printk("V2_ADDR 0x20010088 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0088));
+
+	printk("YUV2_H_INFO 0x2001008C =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x008C));
+	printk("YUV2_V_INFO 0x20010090 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0090));
+	printk("YUV2_SCALE_INFO 0x20010094 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0094));
+	printk("YUV2_DISPLAY_INFO 0x20010098 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x0098));
+
+	printk("RGB_OFFSET 0x200100A8 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x00A8));
+	printk("RGB_SIZE 0x200100AC =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x00AC));
+	printk("PANEL_SIZE 0x200100B0 =0x%x\n",
+	       *(volatile unsigned int *)(AK88_VA_DISP + 0x00B0));
+
+}
+
+void set_ahb_priority(void)
+{
+	unsigned long reg;
+
+	reg = __raw_readl(AK88_AHB_PRIORITY);
+	reg &= ~0x7f;		//set all dma priority higher than ARM priority
+	__raw_writel(reg, AK88_AHB_PRIORITY);
+}
+
+//from BSP_LCD.c
+void bsplcd_set_panel_power(int en /*1=open,0=close */ )	//pullup TFT_VGH_L and TFT_AVDD
+{
+	unsigned int pin;
+
+#if 0
+	int i;
+	for (i = 0; i < 127; i++)	//debug ,set all gpio pin to output and pull high
+	{
+		if(i==AK8802_GPIO_57)
+		{
+			if (en)
+				gpio_set_output(i, 0);	//open,set to output and pull high
+ 			else
+				gpio_set_output(i, 1);	//close,set to output and pull low
+		}else
+		{
+		if (en)
+			gpio_set_output(i, 1);	//open,set to output and pull high
+			//gpio_set_output(i, 0);	//open,set to output and pull high
+		else
+			gpio_set_output(i, 0);	//close,set to output and pull low
+			//gpio_set_output(i, 1);	//close,set to output and pull low
+		}	
+	}
+#endif
+
+#ifdef CONFIG_BOARD_AK8802EBOOK	
+
+	//lcd pin name:TFT_VCC3V3 
+	//output, pull LOW
+
+	//pin=AK88_GPIO_DGPIO26; //for 7801 or 8801
+	//pin = AK8802_GPIO_RESV91;	//for 7802 or 8802
+
+	pin=	AK8802_GPIO_57;  //pull LOW
+
+	AKCLR_BITS(1UL << 24, AK88_SHAREPIN_CTRL);	//set pin as gpio[58:47]
+
+	if (en)
+		gpio_set_output(pin, 0);	//open,set to output and pull LOW
+	else
+		gpio_set_output(pin, 1);	//close,set to output and pull HIGH
+
+	//lcd pin name:TFT_AVDD
+	//pin=AK88_GPIO_DGPIO25;      //for 7801 or 8801
+	//pin = AK8802_GPIO_RESV90;	//for 7802 or 8802
+	pin = AK8802_GPIO_01;	//
+
+	AKCLR_BITS(1UL << 0, AK88_SHAREPIN_CTRL);	//set pin as gpio[3:0]
+
+ 	if (en)
+		gpio_set_output(pin, 1);	//open,set to output and pull high
+	else
+		gpio_set_output(pin, 0);	//close,set to output and pull low
+
+#else
+
+#ifdef CONFIG_BOARD_AK8801EPC	
+
+	//lcd pin name:TFT_VGH_L
+	//pin=AK88_GPIO_DGPIO26;      //for 7801 or 8801
+	pin = AK8802_GPIO_RESV91;	//for 7802 or 8802
+
+	if (en)
+		gpio_set_output(pin, 1);	//open,set to output and pull high
+ 	else
+		gpio_set_output(pin, 0);	//close,set to output and pull low
+
+	//lcd pin name:TFT_AVDD
+	//pin=AK88_GPIO_DGPIO25;  //for 7801 or 8801
+	pin = AK8802_GPIO_RESV90;   //for 7802 or 8802
+
+ 	if (en)
+		gpio_set_output(pin, 1);	//open,set to output and pull high
+	else
+		gpio_set_output(pin, 0);	//close,set to output and pull low
+
+#endif
+
+#endif
+
+}
+
+// from base_LCDController.cpp
+
+void baselcd_reset_panel(void)	//lcd panel reset
+{
+	//0x2001,0008   
+	//bit[31:1]: reserved
+	//bit[0]:rst:   0=To send a reset signal to LCD panel
+	//              1=No instruction
+
+	AKSET_BITS(1UL << 0, AK88_LCD_REST_SIGNAL);
+	ak880x_sdelay(2);
+
+	AKCLR_BITS(1UL << 0, AK88_LCD_REST_SIGNAL);
+	ak880x_sdelay(2);
+
+	AKSET_BITS(1UL << 0, AK88_LCD_REST_SIGNAL);
+	ak880x_sdelay(2);
+
+}
+
+void baselcd_set_panel_backlight(int en /*en=0:close; en=1:open */ ) {
+	unsigned int pin;
+
+#if 1				//debug for ak8802
+	//lcd pin name: LCD_BACK_LIGHT
+
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//bit[4]: 1=corresponding are used as {#PWM1]}     //gpio[9] 
+//        0=corresponding are used as {#gpio[9]}  
+	//AKSET_BITS(1UL<<4,AK88_SHAREPIN_CTRL);   //set pin as #PWM1
+	AKCLR_BITS(1UL << 4, AK88_SHAREPIN_CTRL);	//set pin as gpio[9]
+
+	pin = AK8802_GPIO_09;	//
+
+	//gpio_set_dir(pin,0);  //set output dir
+
+	if (en)			//open
+	{
+		//for(i=0;i<10;i++)
+		{
+			//gpio_set_level(pin,0); //pull low
+			gpio_set_output(pin, 0);	//set to output and pull low
+			ak880x_sdelay(1);
+			//gpio_set_level(pin,1);  //pull high
+			gpio_set_output(pin, 1);	//set to output and pull low
+			ak880x_sdelay(1);
+		}
+	} else {
+		//gpio_set_level(pin,0);
+		gpio_set_output(pin, 0);	//set to output and pull low
+	}
+#endif
+
+}
+
+void baselcd_reset_controller(void)	//to rest power clock reg bit19
+{
+	//0x0800,000c
+	//bit[19]:0=no instruction
+	//        1=to reset display controller
+
+	//reset lcd interface
+	AKSET_BITS(1 << 19, AK88_POWER_CLOCK);	//0x0800000C
+	//bit[19]: to reset display controller
+
+	ak880x_sdelay(1);
+
+	AKCLR_BITS(1 << 19, AK88_POWER_CLOCK);	//0x0800000C
+	ak880x_sdelay(1);
+
+	//open LCD controller clock
+	AKCLR_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+}
+
+void baselcd_controller_init(int en)
+{
+	//mapping 0x2001,0000 AK88_VA_DISP,has done in map_desc ak880x_iodesc[]
+	//mapping 0x0800,0000 AK88_VA_SYS,has done in map_desc ak880x_iodesc[]
+
+	baselcd_reset_controller();	//controler reset
+
+	baselcd_reset_panel();	//panel reset
+
+	//set share pin
+	//set sharepin
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//bit[25]: 1=corresponding are used as {LCD_DATA[15:9]}  //gpio[68:62]
+//bit[26]: 1=corresponding are used as {LCD_DATA[8]}     //gpio[61]
+//bit[27]: 1=corresponding are used as {LCD_DATA[17:16]} //gpio[70:69] 
+//bit[28]: 1=corresponding are used as {#MPU_RST]}       //gpio[71] 
+	if (en) {
+		AKSET_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[15:9]
+		AKSET_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[8]
+		AKSET_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[17:16]
+		AKSET_BITS(1UL << 28, AK88_SHAREPIN_CTRL);	//set pin as #MPU_RST
+	} else {
+
+		AKCLR_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as gpio[68:62]
+		AKCLR_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as gpio[61]
+		AKCLR_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as gpio[70:69]
+		AKCLR_BITS(1UL << 28, AK88_SHAREPIN_CTRL);	//set pin as gpio[71]
+
+	}
+
+	if (en)
+		//open LCD controller clock
+		AKCLR_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+	else
+		//close LCD controller clock
+		AKSET_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+	//panel power on
+	bsplcd_set_panel_power(en);	//pullup TFT_VGH_L and TFT_AVDD
+
+	//panel backlight
+	baselcd_set_panel_backlight(en);
+
+}
+
+bool lcd_controller_isrefreshok(void)
+{
+	int status = 0;
+	status = __raw_readl(AK88_LCD_STATUS_REG);
+	if(1UL<<3 & status)
+		return true;
+	else
+		return false;
+}
+
+void lcd_controller_start_clock(void)
+{
+
+	//open power clock
+//#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)   //0xF000000C
+
+//bit[3], 0 = to enable display controller working clock
+//        1 = to disable display controller working clock
+
+	//open LCD controller clock
+	AKCLR_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+}
+
+void lcd_controller_stop_clock(void)
+{
+
+	//close LCD controller clock
+	AKSET_BITS(1UL << 3, AK88_POWER_CLOCK);	//0x0800000C
+
+}
+
+void lcd_controller_fastdma(void)
+{
+	//enable for DMA
+	//0x2001,00c8
+	//bit[18]:sw_cs:        When the display controller is in RGB mode,this bit can control 
+	//                      the signal level of pin #RGB_CS just like a GPIO
+	//
+	//                      0=The signal of pin #RGB_CS is LOW
+	//                      1=The signal of pin #RGB_CS is HIGH
+	//                      
+	//bit[17]:fast_dma:     0=fast DMA function is OFF;
+	//                      1=fast DMA function is ON.
+	//Note:
+	//      The fast DMA operation can transmit Cb and Cr data consecutively.
+	//      which will shorten the DMA operation time.If programmers want to 
+	//      read back the value of this register,this bit will always be 0,even
+	//      when the fast DMA function is on.
+	//
+
+	//AKCLR_BITS(0x1UL<<18,AK88_LCD_SOFT_CTRL);  //#RGB_CS is LOW
+	AKSET_BITS(0x1UL << 18, AK88_LCD_SOFT_CTRL);	//#RGB_CS is HIGH
+
+	AKSET_BITS(0x1UL << 17, AK88_LCD_SOFT_CTRL);
+}
+
+//from ak780x_lcd.c
+
+//static void lcd_rgb_set_pclk(unsigned long asic_clk,unsigned lcd_clk)
+void lcd_rgb_set_pclk(unsigned long asic_clk, unsigned lcd_clk)
+/* 
+*  be called in void lcd_rgb_init(..)
+*  lcd_rgb_set_pclk(PLLFreq,pLcdInfo->ClockCycle_Hz);
+*  //PLLFreq=124000000; //(124M)
+*  //pLcdInfo->ClockCycle_Hz=30000000;//(30M);
+*/
+{
+
+	//0x2001,00e8
+	//bit[8]:   1=lcd_clk enable
+	//bit[7:1]: lcd_clk=pll1_clk/((x+1)*2) ; so: x=(pll1_clk/(lcd_clk*2)) -1 ;
+	//          asic_clk=pll1_clk/2; so x=asic_clk/lcd_clk -1;	
+	//bit[0]:   1=lcd_clk cfg valid
+
+	int div;
+	div = asic_clk / lcd_clk - 1;
+ 
+	printk("lcd_rgb_set_pclk(),asic_clk=0x%d,lcd_clk=0x%d,div=%d\n",
+	       (u32) asic_clk, (u32) lcd_clk, (u32) div);
+
+	//if asic_clk=124M, lcd_clk=30M
+	// then div=(124/30*2) -1 = 2-1=1
+
+	if (div < 1)
+		div = 1;
+	div &= 0x7f;
+
+	AKSET_BITS((1 << 8) | (1 << 0) | (div << 1), AK88_LCD_CLOCK_CONF);
+	div = __raw_readl(AK88_LCD_CLOCK_CONF);
+
+	printk("AK88_LCD_CLOCK_CONF=0x%x=0x%x\n", (u32) AK88_LCD_CLOCK_CONF,
+	       (u32) div);
+
+}
+
+static void lcd_rgb_set_disp_ram(unsigned long virpage_physical_base_addr)
+{
+//0x2001,0014
+//bit[28]:rgb_vir_en,0=to disable virtual page function of RGB channel
+//                   1=to enable virtual page function of RGB channel
+//bit[27:0] CFBA, Staring buffer address of current frame.
+
+	unsigned long val, tmp;
+
+	val = virpage_physical_base_addr & 0xfffffff;	//fetch bit[27:0]
+	tmp = __raw_readl(AK88_LCD_RGB_CTRL2);
+	tmp = tmp & 0xf0000000;	//fetch bit[31:28]
+	val = tmp | val;
+
+	printk("lcd_rgb_set_disp_ram,val=0x%x\n", (u32) val);
+
+	__raw_writel(val, AK88_LCD_RGB_CTRL2);
+}
+
+//static void lcd_osd_set_disp_ram(unsigned long osd_base_addr)
+void lcd_osd_set_disp_ram(unsigned long osd_base_addr)
+{
+//0x2001,0020
+//bit[31:28] reserved
+//bit[27:0] OSD ADDR, Staring address of externam RAM from which the data 
+//be sent to OSD channel
+
+	unsigned long val;
+	val = osd_base_addr & 0xfffffff;	//bit[27:0]
+
+	__raw_writel(val, AK88_LCD_OSD_ADDR);
+}
+
+static void lcd_rgb_set_virtual_page(unsigned long virpage_en,
+				     unsigned long virpage_hlen,
+				     unsigned long virpage_vlen)
+{
+//0x2001,0014
+//bit[28]:rgb_vir_en,0=to disable virtual page function of RGB channel
+//                   1=to enable virtual page function of RGB channel
+//bit[27:0] CFBA, Staring buffer address of current frame.
+
+//0x2001,0018
+//bit[31:16] rgb_virpage_hlen ,horizontal length of virtual page
+//bit[15:0]  rgb_virpage_vlen, vertical length of virtual page
+
+	//unsigned long val;
+
+	if (virpage_en)
+		AKSET_BITS(1 << 28, AK88_LCD_RGB_CTRL2);
+	else
+		AKCLR_BITS(1 << 28, AK88_LCD_RGB_CTRL2);
+
+	__raw_writel(((virpage_hlen & 0xffff) << 16) | (virpage_vlen & 0xffff),
+		     AK88_LCD_RGB_VIRPAGE_SIZE);
+}
+
+static void lcd_rgb_set_virtual_offset(unsigned long virpage_hoffset,
+				       unsigned long virpage_voffset)
+{
+//define the real display area offset compare to virtual page
+
+//0x2001,001C
+//bit[31:16] rgb_virpage_hoffset ,horizontal offset of virtual page(unit:pixel)
+//bit[15:0]  rgb_virpage_voffset, vertical offset of virtual page(unit:pixel)
+
+	//unsigned long val;
+
+	__raw_writel(((virpage_hoffset & 0xffff) << 16) |
+		     (virpage_voffset & 0xffff), AK88_LCD_RGB_VIRPAGE_OFFSET);
+}
+
+static void lcd_rgb_set_picture(unsigned long pic_hoffset,
+				unsigned long pic_voffset,
+				unsigned long pic_hsize,
+				unsigned long pic_vsize)
+// define the display area compare to real physical page
+//
+{
+//0x2001,00A8
+//bit[31:20],reservd
+//bit[19:10],H_offset, Horizontal offset value of the picture from RGB channel,(unit:pixel)
+//bit[9:0],V_offset,Vertical offset value of the picture from RGB channel,(unit:pixel)
+
+//0x2001,00AC
+//bit[31:20],reservd
+//bit[19:10],H_length, Horizontal length value of the picture from RGB channel,(unit:pixel)
+//bit[9:0],V_length,Vertical length value of the picture from RGB channel,(unit:pixel)
+
+	//unsigned long val;
+
+	__raw_writel(((pic_hoffset & 0x3ff) << 10) | (pic_voffset & 0x3ff),
+		     AK88_LCD_RGB_OFFSET);
+
+	__raw_writel(((pic_hsize & 0x3ff) << 10) | (pic_vsize & 0x3ff),
+		     AK88_LCD_RGB_SIZE);
+
+}
+
+bool lcd_init_display_ram(struct display_ram *p_disp_ram,
+			  struct lcd_size *p_lcd_size)
+{
+//disable virtual page, set picture area = real physical display area
+
+	lcd_rgb_set_disp_ram((u32) p_disp_ram->p_rgb_base1);
+
+	lcd_rgb_set_virtual_page(0, p_lcd_size->w_pixel, p_lcd_size->h_pixel);
+	//disable virtual page function
+	//virtual page size = real page size
+
+	lcd_rgb_set_virtual_offset(0, 0);
+
+	lcd_rgb_set_picture(0, 0, p_lcd_size->w_pixel, p_lcd_size->h_pixel);
+	//pictual area = real physical display area
+
+	lcd_osd_set_disp_ram((u32) p_disp_ram->p_osd_base);
+
+	lcd_controller_fastdma();
+
+	//set bg color
+	//0x2001,003c background color register
+	//bit[31:24]: reserved
+	//bit[23:0]:  back_color. default background color
+
+	__raw_writel(0x5a5a5a, AK88_LCD_BKG_COLO);
+	//__raw_writel(0xffffff,AK88_LCD_BKG_COLO);
+
+	return true;
+}
+
+bool lcd_fb_init_ram(unsigned long dma_addr, unsigned long xres,
+		     unsigned long yres)
+{
+//disable virtual page, set picture area = real physical display area
+
+	lcd_rgb_set_disp_ram((u32) dma_addr);
+
+	lcd_rgb_set_virtual_page(0, xres, yres);
+	//disable virtual page function
+	//virtual page size = real page size
+
+	lcd_rgb_set_virtual_offset(0, 0);
+
+	lcd_rgb_set_picture(0, 0, xres, yres);
+	//pictual area = real physical display area
+
+	//lcd_osd_set_disp_ram((u32)p_disp_ram->p_osd_base);
+
+	lcd_controller_fastdma();
+
+	//set bg color
+	//0x2001,003c background color register
+	//bit[31:24]: reserved
+	//bit[23:0]:  back_color. default background color
+
+	__raw_writel(0x5a5a5a, AK88_LCD_BKG_COLO);
+
+	return true;
+}
+
+static void lcd_rgb_set_timing(struct tft_lcd_timing_info *p_tft)
+{
+	u32 temp;
+	bool swap_bgr;
+	int  buswidthbit = 0;
+	
+	//setlect rgb interface
+	//0x21000000    
+	//bit[6:5]: if_mode: LCD interface mode selection
+	//              00:reserved
+	//              01=MPU interface
+	//              10=RGB interface
+	//              11=TV interface
+
+	AKCLR_BITS(0x3UL << 5, AK88_LCD_CMD_REG1);
+	AKSET_BITS(0x2UL << 5, AK88_LCD_CMD_REG1);
+
+	//0x20010010,AK88_LCD_RGB_CTRL1
+	//bit[22:21]:width_sel: 00=8bits,01=16bits,10=18bits,11=reserved
+	//bit[20]:RGB_panel_mode:0=reserved,1=non interlace
+	//bit[2]:h_pol:0=positive,1=negative,def=0(positive)
+	//bit[1]:v_pol:def=0(positive)
+	//bit[0]:g_pol RGB_VOGATE''s polarity,def=0(positive)
+	//AKSET_BITS((0x2UL<<21)|(p_tft->interlace<<20)|(p_tft->hvg_pol&0x07), AK88_LCD_RGB_CTRL1);
+	if(8 == p_tft->bus_width)
+	{
+		buswidthbit = 0x0<<21;
+	}
+	else if(16 == p_tft->bus_width)
+	{
+		buswidthbit = 0x1UL<<21;
+	}
+	else if(18 == p_tft->bus_width)
+	{
+		buswidthbit = 0x10UL<<21;
+	}
+		
+	AKSET_BITS((buswidthbit) | (p_tft->interlace << 20) |
+		   (p_tft->hvg_pol & 0x07), AK88_LCD_RGB_CTRL1);
+	//progress (1<<20)          0xe
+
+	//h_pulse_width_clk and v_pulse_width_clk
+	//0x20010040
+	AKCLR_BITS(0xfff << 12, AK88_LCD_RGB_CTRL3);
+	AKCLR_BITS(0xfff << 0, AK88_LCD_RGB_CTRL3);
+	AKSET_BITS((p_tft->h_pulse_width_clk << 12) | (p_tft->
+						       v_pulse_width_clk << 0),
+		   AK88_LCD_RGB_CTRL3);
+
+	//h_back_porch_clk and h_disp_clk
+	//0x20010044
+	AKCLR_BITS(0xfff << 12, AK88_LCD_RGB_CTRL4);
+	AKCLR_BITS(0xfff << 0, AK88_LCD_RGB_CTRL4);
+	AKSET_BITS((p_tft->h_back_porch_clk << 12) | (p_tft->h_disp_clk << 0),
+		   AK88_LCD_RGB_CTRL4);
+
+	//h_front_porch_clk and h_tot_clk
+	//0x20010048
+	AKCLR_BITS(0xfff << 13, AK88_LCD_RGB_CTRL5);
+	AKCLR_BITS(0x1fff << 0, AK88_LCD_RGB_CTRL5);
+	AKSET_BITS((p_tft->h_front_porch_clk << 13) | (p_tft->h_tot_clk << 0),
+		   AK88_LCD_RGB_CTRL5);
+	//1058
+	//v_back_porch_clk
+	//0x2001004C
+	AKCLR_BITS(0xfff << 0, AK88_LCD_RGB_CTRL6);
+	AKSET_BITS(p_tft->v_back_porch_clk << 0, AK88_LCD_RGB_CTRL6);
+
+	//v_front_porch_clk
+	//0x20010050
+	AKCLR_BITS(0xfff << 0, AK88_LCD_RGB_CTRL7);
+	AKSET_BITS(p_tft->v_front_porch_clk << 0, AK88_LCD_RGB_CTRL7);
+
+	//v_disp_clk
+	//0x20010054
+	AKCLR_BITS(0xfff << 15, AK88_LCD_RGB_CTRL8);
+	AKCLR_BITS(0xfff << 1, AK88_LCD_RGB_CTRL8);
+	AKSET_BITS(p_tft->v_disp_clk << 15, AK88_LCD_RGB_CTRL8);
+
+	//v_tot_clk
+	//0X20010058
+	AKCLR_BITS(0x1fff << 0, AK88_LCD_RGB_CTRL9);
+	AKSET_BITS(p_tft->v_tot_clk << 0, AK88_LCD_RGB_CTRL9);
+
+	//553
+	//set rgb or bgr and alr
+
+	//CMD1_ALR relate to what???
+
+	temp = __raw_readl(AK88_LCD_CMD_REG1);	//0x2001,0000    
+	temp &= ~((0xffUL << 24) | (0xffUL << 16));
+
+	//clk polarity
+	if (p_tft->hvg_pol & 0x8)	//0xe    
+		temp |= 1UL << 4;
+	else
+		temp &= ~(1UL << 4);
+
+	temp |= ((0x80 << 24) | (0xa8 << 16));
+
+	//swap_bgr=bsp_get_lcd_rbg_swap();
+	swap_bgr = true;
+	if ((p_tft->rgb_bit & (1UL << 12)) == 0)	//bit12=1:BGR
+		//if((p_tft->rgb_bit & (1UL<<12))==1) //bit12=1:RGB
+	{			//RGB
+		if (swap_bgr)
+			temp &= ~(1UL << 15);
+		else
+			temp |= 1UL << 15;
+	} else {
+		if (swap_bgr)
+			temp |= 1UL << 15;
+		else
+			temp &= ~(1UL << 15);
+	}
+
+	AKSET_BITS(temp, AK88_LCD_CMD_REG1);	//0x2001,0000
+	printk("lcd width=%d,lcd height=%d\n", p_tft->h_disp_clk,
+	       p_tft->v_disp_clk);
+
+	//set diaplay area size
+	__raw_writel(0, AK88_LCD_DISP_AREA);	//0x2001,00B0
+	AKSET_BITS((p_tft->h_disp_clk << 10) | (p_tft->v_disp_clk << 0), AK88_LCD_DISP_AREA);	//0x2001,00B0
+
+}
+
+void lcd_update(void)
+{
+	//0x2001,00c8
+	//bit[11]:sw_en:1=all the necessary infomation about next frame has been set properly
+	//              note:This bit is cleared automatically after writing 1
+	AKSET_BITS(1UL << 11, AK88_LCD_SOFT_CTRL);	//0x2001,00c8
+
+	//lcd_controller_fastdma();
+
+}
+
+void lcd_rgb_start_refresh(void)
+{
+	//int i;
+
+	lcd_controller_fastdma();
+
+	//0x2001,00c8
+	//bit[11]:sw_en:1=all the necessary infomation about next frame has been set properly
+	//              note:This bit is cleared automatically after writing 1
+	AKSET_BITS(1UL << 11, AK88_LCD_SOFT_CTRL);	//0x2001,00c8
+	AKCLR_BITS(1UL << 0, AK88_LCD_OPER_REG);	//start LCD refresh
+	AKSET_BITS(1UL << 2, AK88_LCD_OPER_REG);
+}
+
+void lcd_rgb_stop_refresh(void)
+{
+	AKSET_BITS(1UL << 0, AK88_LCD_OPER_REG);
+	mdelay(100);
+	AKSET_BITS(1UL << 0, AK88_LCD_OPER_REG);
+	mdelay(100);
+	printk("lcd stop refresh\n");
+}
+
+void lcd_wait_status(int mask) 
+{
+	int status = 0;
+	printk("+lcd_wait_status\n");
+	//mask = ~(1<<17);
+
+	//lcd_dump_reg();
+	
+	do
+	{
+		status = (int)__raw_readl(AK88_LCD_STATUS_REG);
+	}while(!(status & mask));
+	//lcd_dump_reg();
+	printk("-lcd_wait_status, status%x\n", status);
+}
+void lcd_interrupt_mask(unsigned bits_result, bool disable)
+{
+	//0x2001,00C0(LCD int enable reg) <==> 0x2001,00BC
+	//bitn : 0 = to disable correspondent interrupt
+	//       1 = to enable  correspondent interrupt
+	//       default=0
+	//
+
+	if (disable == true)	//disable=true, disable the interrupt
+		AKCLR_BITS(bits_result, AK88_LCD_INT_ENAB);
+	else
+		AKSET_BITS(bits_result, AK88_LCD_INT_ENAB);
+
+}
+
+//static irqreturn_t anyka_lcdfb_interrupt(int irq, void *dev_id)
+//static void anyka_lcdfb_interrupt_service(void)
+void anyka_lcdfb_interrupt_service(void)
+{
+	//struct fb_info *info = dev_id;
+	//struct atmel_lcdfb_info *sinfo = info->par;
+	unsigned long status;
+
+#if 0
+	status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
+	if (status & ATMEL_LCDC_UFLWI) {
+		dev_warn(info->device, "FIFO underflow %#x\n", status);
+		/* reset DMA and FIFO to avoid screen shifting */
+		schedule_work(&sinfo->task);
+	}
+	lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
+#endif
+
+	status = __raw_readl(AK88_LCD_STATUS_REG);
+
+	lcd_interrupt_mask(STATUS_SYS_ERROR, false);	//umask(enable) the interrupt
+
+	lcd_interrupt_mask(STATUS_RGB_REFRESH_START, false);	//umask(enable) the interrupt
+
+	if (status & STATUS_SYS_ERROR) {
+		//dev_warn(info->device, "LCD:SYS_ERROR %#x\n", status);
+		printk("LCD:SYS_ERROR recover now\n");
+
+		//stop first
+		//lcd_rgb_stop_refresh();
+		//refresh
+		//lcd_rgb_start_refresh();
+
+		/* reset DMA and FIFO to avoid screen shifting */
+		//schedule_work(&sinfo->task);          
+	}
+
+	if (status & STATUS_RGB_REFRESH_START) {
+		//dev_warn(info->device, "LCD:RGB_REFRESH_START %#x\n", status);
+		printk("LCD:mask interrupt of RGB_REFRESH_START now\n");
+
+		lcd_interrupt_mask(STATUS_RGB_REFRESH_START, true);	//mask(disable) the interrupt
+
+		/* reset DMA and FIFO to avoid screen shifting */
+		//schedule_work(&sinfo->task);          
+	}
+	//return IRQ_HANDLED;
+}
+
+//#define AK88_DUMP_REG(x) { printk("reg 0x%x=0x%x\n",(u32)AK88_##x,(u32)__raw_readl(AK88_##x)); }
+
+void lcd_dump_reg(void)
+{
+	//u32 cnt,temp;
+	printk("AK88_POWER_CLOCK 0x%x=0x%x\n",
+	       (unsigned int)AK88_POWER_CLOCK,
+	       (unsigned int)__raw_readl(AK88_POWER_CLOCK));
+
+	AK88_DUMP_REG(LCD_CMD_REG1);
+	AK88_DUMP_REG(LCD_REST_SIGNAL);
+	AK88_DUMP_REG(LCD_RGB_CTRL1);
+	AK88_DUMP_REG(LCD_RGB_CTRL2);
+	AK88_DUMP_REG(LCD_RGB_VIRPAGE_SIZE);
+	AK88_DUMP_REG(LCD_RGB_VIRPAGE_OFFSET);
+	AK88_DUMP_REG(LCD_OSD_ADDR);
+	AK88_DUMP_REG(LCD_BKG_COLO);
+	AK88_DUMP_REG(LCD_RGB_CTRL3);
+	AK88_DUMP_REG(LCD_RGB_CTRL4);
+	AK88_DUMP_REG(LCD_RGB_CTRL5);
+	AK88_DUMP_REG(LCD_RGB_CTRL6);
+	AK88_DUMP_REG(LCD_RGB_CTRL7);
+	AK88_DUMP_REG(LCD_RGB_CTRL8);
+	AK88_DUMP_REG(LCD_RGB_CTRL9);
+	AK88_DUMP_REG(LCD_RGB_OFFSET);
+	AK88_DUMP_REG(LCD_RGB_SIZE);
+	AK88_DUMP_REG(LCD_DISP_AREA);
+	AK88_DUMP_REG(LCD_CMD_REG2);
+	AK88_DUMP_REG(LCD_OPER_REG);
+	AK88_DUMP_REG(LCD_STATUS_REG);
+	AK88_DUMP_REG(LCD_INT_ENAB);
+	AK88_DUMP_REG(LCD_SOFT_CTRL);
+	AK88_DUMP_REG(LCD_CLOCK_CONF);
+
+	//lcd_print_reg();
+
+}
+
+void lcd_debug_status(void)
+{
+	u32 temp;
+	temp = __raw_readl(AK88_LCD_STATUS_REG);
+
+	if (temp & STATUS_BUF_EMPTY_ALARM)
+		printk("buffer empty\n");
+	if (temp & STATUS_ALERT_VALID)
+		printk("alert valid\n");
+	if (temp & STATUS_TV_REFRESH_START)
+		printk("tv refresh start\n");
+	if (temp & STATUS_TV_REFRESH_OK)
+		printk("tv refresh ok\n");
+	if (temp & STATUS_RGB_REFRESH_START)
+		printk("rgb refresh start\n");
+	if (temp & STATUS_RGB_REFRESH_OK)
+		printk("rgb refresh ok\n");
+	if (temp & STATUS_MPU_REFRESH_START)
+		printk("mpu refresh start\n");
+	if (temp & STATUS_MPU_REFRESH_OK)
+		printk("mpu refresh ok\n");
+
+	if (temp & STATUS_SYS_ERROR)
+		printk("err\n");
+
+}
+
+void lcd_debug_refreshing_loop(void)
+{
+	u32 temp;
+	u32 cnt = 0;
+
+	printk("lcd refreshing loop ...\n");
+
+	while (1) {
+
+		temp = __raw_readl(AK88_LCD_STATUS_REG);
+
+		if (temp & STATUS_BUF_EMPTY_ALARM)
+			printk("p");
+		if (temp & STATUS_ALERT_VALID)
+			printk("a");
+
+		if (temp & STATUS_TV_REFRESH_START)
+			if (temp & STATUS_TV_REFRESH_OK) {
+				cnt = 0;
+				printk("t");
+			}
+
+		if (temp & STATUS_RGB_REFRESH_START)
+			if (temp & STATUS_RGB_REFRESH_OK) {
+				cnt = 0;
+				printk("r");
+			}
+
+		if (temp & STATUS_MPU_REFRESH_START)
+			if (temp & STATUS_MPU_REFRESH_OK) {
+				cnt = 0;
+				printk("m");
+			}
+
+		if (temp & STATUS_SYS_ERROR) {
+			printk("e");
+			lcd_dump_reg();
+			while (1) ;
+		}
+
+		if (cnt > 1000000) {
+			printk("lcd refresh timeout! status =0x%x\n", temp);
+			lcd_dump_reg();
+			while (1) ;
+		}
+
+		cnt++;
+	}
+}
+
+void lcd_rgb_init(struct tft_lcd_timing_info *p_tft, u32 asic_freq)
+{
+	printk("sysreg_base=0x%x,lcdreg_base=0x%x\n", (u32) AK88_VA_SYS,
+	       (u32) AK88_VA_DISP);
+
+	lcd_rgb_set_pclk(asic_freq /*124 MHZ */ , p_tft->clock_hz /*30 MHZ */ );
+
+	//0x21000000    
+	//bit[3]:rgb_ch_en,   0=disable,1=enable
+	//bit[2]:YCbCr1_ch_en,0=disable,1=enable
+	//bit[1]:YCbCr2_ch_en,0=disable,1=enable
+	//bit[0]:OSD_ch_en,   0=disable,1=enable
+
+	//disable all channel
+
+	__raw_writel(0, AK88_LCD_CMD_REG1);
+	AKCLR_BITS(1UL << 3 | 1UL << 2 | 1UL << 1 | 1UL << 0,
+		   AK88_LCD_CMD_REG1);
+	//lcd_update();
+
+	//setlect rgb interface
+	//0x21000000    
+	//bit[6:5]: if_mode: LCD interface mode selection
+	//              00:reserved
+	//              01=MPU interface
+	//              10=RGB interface
+	//              11=TV interface
+
+	AKCLR_BITS(0x3UL << 5, AK88_LCD_CMD_REG1);
+	AKSET_BITS(0x2UL << 5, AK88_LCD_CMD_REG1);
+
+	//set timing
+	lcd_rgb_set_timing(p_tft);
+
+	lcd_controller_fastdma();
+
+	//set bg color
+	//0x2001,003c background color register
+	//bit[31:24]: reserved
+	//bit[23:0]:  back_color. default background color
+
+	__raw_writel(0x5a5a5a, AK88_LCD_BKG_COLO);
+
+}
+
+//void lcd_fb_rgb_init(struct anyka_lcdfb_info *sinfo, u32 asic_freq)
+void lcd_fb_set_timing(struct anyka_lcdfb_info *sinfo, u32 asic_freq)
+{
+
+	struct tft_lcd_timing_info tft;
+	u8 bit3, bit2, bit1, bit0;
+#if 0
+	struct tft_lcd_timing_info {
+
+		u8 bus_width;	//24
+		u32 interlace;	//PROGRESS=1<<20   //interlace(1) or progress(0)
+		u8 hvg_pol;	//0xe              //h_sync(bit2),v_sync(bit1),gate(bit0) polarity
+		u16 rgb_bit;	//0x0888           //RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+
+		u32 clock_hz;	//30,000,000(30M)  //bit clock, clock cycle,unit HZ
+
+		u32 h_sync_hz;	//15711??          //h_sync cycle,unit HZ
+		u32 v_sync_001hz;	//5885             //v_sync cycle,unit 0.01HZ
+
+		u16 h_tot_clk;	//1058             //horizontal total cycle,unit clock
+		u16 h_disp_clk;	//800              //horizontal display cycle,unit clock
+		u16 h_front_porch_clk;	//170              //horizontal front porch,unit clock
+		u16 h_pulse_width_clk;	//48               //horizontal pulse width,unit clock
+		u16 h_back_porch_clk;	//40               //horizontal back porch,unit clock
+
+		u16 v_tot_clk;	//553              //vertical   total cycle,unit h_sync
+		u16 v_disp_clk;	//480              //vertical   display cycle,unit h_sync
+		u16 v_front_porch_clk;	//40               //vertical   front porch,unit clock
+		u16 v_pulse_width_clk;	//4                //vertical   pulse width,unit clock
+		u16 v_back_porch_clk;	//29               //vertical   back porch,unit clock
+
+		char *name;
+	};
+#endif
+	tft.bus_width = 16;
+	//if(sinfo->mode->vmode == FB_VMODE_NONINTERLACED) in board_ak8802.c
+	//tft.interlace = 1<<20 ; //no interlace 
+
+//      .vmode          = FB_VMODE_NONINTERLACED,
+	tft.interlace = 1;	//no interlace 
+	if (sinfo->default_monspecs->modedb->vmode == FB_VMODE_NONINTERLACED)
+		tft.interlace = 1;	//no interlace 
+	else
+		tft.interlace = 0;	//interlace 
+	printk("lcd_fb_set_timing(),tft.interlace(1)=%d\n", tft.interlace);
+
+	//u8   hvg_pol;         //0xe      //1=positive,0=negative;
+	//pclk polarity(bit3),h_sync(bit2),v_sync(bit1),gate(bit0) polarity
+	//refer to board_ak8802.c
+
+	tft.hvg_pol = 0xe;	//default
+	bit0 = 0;		//VOGATE(den) high active
+	bit3 = 1;		//pclk high active
+	bit2 = 1;
+	bit1 = 1;
+
+	//if(sinfo->info->mode->sync & FB_SYNC_HOR_HIGH_ACT)   //oops error
+	if (sinfo->default_monspecs->modedb->sync & FB_SYNC_HOR_HIGH_ACT)	//oops error
+		bit2 = 0;
+	else
+		bit2 = 1;
+
+	//if(sinfo->info->mode->sync & FB_SYNC_HOR_HIGH_ACT)
+	if (sinfo->default_monspecs->modedb->sync & FB_SYNC_HOR_HIGH_ACT)
+		bit1 = 0;
+	else
+		bit1 = 1;
+
+	tft.hvg_pol = (bit3 << 3) | (bit2 << 2) | (bit1 << 1) | (bit0);
+
+	printk("lcd_fb_set_timing(),tft.hvg_pol(0xe)=0x%x\n", tft.hvg_pol);
+
+	//u16  rgb_bit;  //0x0888   //RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+	tft.rgb_bit = 0x0888;
+	if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_BGR) {
+		/* BGR mode */
+		tft.rgb_bit |= 1UL << 12;
+	}
+	//tft.clock_hz = PICOS2KHZ(sinfo->info->var.pixclock)*1000;
+	tft.clock_hz = sinfo->info->var.pixclock;
+
+	printk("sinfo->pixclock=%d,sinfo->pixclock=%d\n",
+	       (u32) sinfo->info->var.pixclock,
+	       (u32) sinfo->info->var.pixclock);
+
+	tft.h_sync_hz = 0;	//no use
+	tft.v_sync_001hz = 0;	//no use
+
+	tft.h_disp_clk = sinfo->info->var.xres;
+	tft.h_back_porch_clk = sinfo->info->var.left_margin;
+	tft.h_front_porch_clk = sinfo->info->var.right_margin;
+	tft.h_pulse_width_clk = sinfo->info->var.hsync_len;
+	tft.h_tot_clk =
+	    tft.h_disp_clk + tft.h_front_porch_clk + tft.h_pulse_width_clk +
+	    tft.h_back_porch_clk;
+
+//printk("tft.h_disp_clk=%d,tft.h_front_porch_clk=%d,tft.h_pulse_width_clk=%d,tft.h_back_porch_clk=%d,tft.h_tot_clk=%d\n",tft.h_disp_clk,tft.h_front_porch_clk,tft.h_pulse_width_clk,tft.h_back_porch_clk,tft.h_tot_clk);
+
+	tft.v_disp_clk = sinfo->info->var.yres;
+	tft.v_back_porch_clk = sinfo->info->var.upper_margin;
+	tft.v_front_porch_clk = sinfo->info->var.lower_margin;
+	tft.v_pulse_width_clk = sinfo->info->var.vsync_len;
+	tft.v_tot_clk =
+	    tft.v_disp_clk + tft.v_front_porch_clk + tft.v_pulse_width_clk +
+	    tft.v_back_porch_clk;
+
+	printk("tft.h_tot_clk=%d,tft.v_tot_clk=%d\n", tft.h_tot_clk,
+	       tft.v_tot_clk);
+
+	//lcd_rgb_init(&tft,asic_freq );
+
+	//lcd_rgb_set_pclk(asic_freq/*124 MHZ*/,tft.clock_hz/*30 MHZ*/);
+
+	lcd_rgb_set_timing(&tft);
+
+	//if_mode = LCD_IF_RGB;
+	//lcd_rgb_set_interface(if_mode);
+
+	//lcd_rgb_start_refresh();
+
+}
+
+//from ak780x_LCD_RGBController.cpp
+
+void rgbcontroller_set_interface(LCD_IF_MODE if_mode,
+				 struct tft_lcd_timing_info *p_tft_info)
+{
+	//u16 *pd;
+	//u32 i;
+
+	if (if_mode == LCD_IF_RGB) {
+
+		//lcd_rgb_init(&hsd070idw1_a10,ak880x_asicfreq_get());
+
+		lcd_rgb_init(p_tft_info, ak880x_asicfreq_get());	//debug
+		mdelay(100);
+
+#if 1				//debug
+
+		//set share pin
+		//set sharepin
+//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//bit[25]: 1=corresponding are used as {LCD_DATA[15:9]}  //gpio[68:62]
+//bit[26]: 1=corresponding are used as {LCD_DATA[8]}     //gpio[61]
+//bit[27]: 1=corresponding are used as {LCD_DATA[17:16]} //gpio[70:69] 
+//bit[28]: 1=corresponding are used as {MPU_RST]}        //gpio[71] 
+
+		AKSET_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[15:9]
+		AKSET_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[8]
+		AKSET_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[17:16]
+		AKSET_BITS(1UL << 28, AK88_SHAREPIN_CTRL);	//set pin as #MPU_RST
+		mdelay(100);
+
+		//reset lcm
+		//baselcd_reset_panel();
+
+		//lcd_select_channel
+		//0x21000000
+		//bit[3]:rgb_ch_en,   0=disable,1=enable
+		//bit[2]:YCbCr1_ch_en,0=disable,1=enable
+		//bit[1]:YCbCr2_ch_en,0=disable,1=enable
+		//bit[0]:OSD_ch_en,   0=disable,1=enable
+
+		//disable all channel
+		AKCLR_BITS(1UL << 3 | 1UL << 2 | 1UL << 1 | 1UL << 0,
+			   AK88_LCD_CMD_REG1);
+		//lcd_update();
+		mdelay(100);
+
+		//select the rgb channel
+		AKSET_BITS(1UL << 3, AK88_LCD_CMD_REG1);
+		//lcd_update();
+		mdelay(100);
+
+		//setlect rgb interface
+		//0x21000000    
+		//bit[6:5]: if_mode: LCD interface mode selection
+		//              00:reserved
+		//              01=MPU interface
+		//              10=RGB interface
+		//              11=TV interface
+
+		AKCLR_BITS(0x3UL << 5, AK88_LCD_CMD_REG1);
+		AKSET_BITS(0x2UL << 5, AK88_LCD_CMD_REG1);
+
+		mdelay(100);
+		//lcd_rgb_start_refresh();
+
+		lcd_dump_reg();
+
+		//panel power on
+		bsplcd_set_panel_power(1);	//pullup TFT_VGH_L and TFT_AVDD
+
+		//before enable back light,at least wait one frame output
+		//sleep(10);
+		baselcd_set_panel_backlight(1);
+#endif
+
+	}
+
+}
+
+//void lcd_rgb_set_interface(LCD_IF_MODE if_mode,struct tft_lcd_timing_info *p_tft_info)
+void lcd_rgb_set_interface(LCD_IF_MODE if_mode)
+{
+	//u16 *pd;
+	//u32 i;
+
+	if (if_mode == LCD_IF_RGB) {
+
+		AKSET_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[15:9]
+		AKSET_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[8]
+		AKSET_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[17:16]
+		AKSET_BITS(1UL << 28, AK88_SHAREPIN_CTRL);	//set pin as MPU_RST
+		//mdelay(100);
+
+		//lcd_select_channel
+		//0x21000000
+		//bit[3]:rgb_ch_en,   0=disable,1=enable
+		//bit[2]:YCbCr1_ch_en,0=disable,1=enable
+		//bit[1]:YCbCr2_ch_en,0=disable,1=enable
+		//bit[0]:OSD_ch_en,   0=disable,1=enable
+
+		//disable all channel
+		AKCLR_BITS(1UL << 3 | 1UL << 2 | 1UL << 1 | 1UL << 0,
+			   AK88_LCD_CMD_REG1);
+		//mdelay(100);
+		//lcd_update();
+
+		//select the rgb channel
+		AKSET_BITS(1UL << 3, AK88_LCD_CMD_REG1);
+		//mdelay(100);
+		//lcd_update();
+
+		//setlect rgb interface
+		//0x21000000    
+		//bit[6:5]: if_mode: LCD interface mode selection
+		//              00:reserved
+		//              01=MPU interface
+		//              10=RGB interface
+		//              11=TV interface
+
+		AKCLR_BITS(0x3UL << 5, AK88_LCD_CMD_REG1);
+
+		AKSET_BITS(0x2UL << 5, AK88_LCD_CMD_REG1);
+
+		lcd_controller_fastdma();
+
+		mdelay(100);
+
+	}
+
+}
+
+void rgbcontroller_copy_usrdata_to_rgb(u32 h_offset, u32 v_offset, u32 h_len,
+				       u32 v_len, u8 * buf)
+{
+	u8 *pd, *ps;
+	u32 dy;
+
+	ps = buf;
+	pd = display_ram.p_rgb_vrt_base1 + (v_offset * lcd_size.w_pixel +
+					    h_offset) * 2;
+
+	//copy one line by one line
+	for (dy = 0; dy < v_len; dy++) {
+		memcpy(pd, ps, h_len * 2);	//copy one line
+		pd += lcd_size.w_pixel * 2;
+		ps += h_len * 2;
+	}
+
+}
+
+void rgbcontroller_start_dma(void)
+{
+	rgbcontroller_copy_usrdata_to_rgb(usr_rgb_area.h_offset,
+					  usr_rgb_area.v_offset,
+					  usr_rgb_area.h_len,
+					  usr_rgb_area.v_len, usr_rgb_area.buf);
+}
+
+void display_init(void)
+{
+	//attach_controller()
+	//new ANYKA_LCD_RGB_CONTROLLER()::LCD_CONTROLLER()
+	//
+	struct tft_lcd_timing_info tft_info;
+	u32 asic_freq, smem_len, begin, addr;
+	int i, j, split;
+
+	asic_freq = ak880x_asicfreq_get();
+	tft_info = hsd070idw1_a10;
+	//tft_info=q07021_701;
+
+	lcd_size.w_pixel = tft_info.h_disp_clk;	//800
+	lcd_size.h_pixel = tft_info.v_disp_clk;	//480
+	lcd_size.pixels = lcd_size.w_pixel * lcd_size.h_pixel;
+	lcd_size.byte_per_pixel = 2;
+	lcd_size.ram_size = lcd_size.pixels * lcd_size.byte_per_pixel;	//=800*480*2
+	lcd_size.freq = tft_info.v_sync_001hz * 100;	//?? 5885*100 
+
+	if_mode = LCD_IF_RGB;
+
+	//baselcd_reset_controller();  //to rest power clock reg bit19
+	//lcd_rgb_set_interface(if_mode);
+
+	memset(&display_ram, 0, sizeof(struct display_ram));
+
+	display_ram.rgb_len1 = lcd_size.ram_size;
+
+	display_ram.yuv1_len = 640 * 480 * 3 / 2;
+
+	display_ram.osd_len = (32 * 32) / 2;	//defined in cursor.h
+
+	disp_buf_size =
+	    display_ram.rgb_len1 + display_ram.rgb_len2 + display_ram.yuv1_len +
+	    display_ram.osd_len * 2;
+
+	//display_ram.p_rgb_base1 = (u8*) AK88_PA_DISPRAM_RGB ;
+	//display_ram.p_rgb_vrt_base1 = (u8*) AK88_VA_DISPRAM_RGB ;
+
+	smem_len = lcd_size.w_pixel * lcd_size.h_pixel * 2;
+
+	display_ram.p_rgb_vrt_base1 = dma_alloc_writecombine(NULL, smem_len,
+							     (dma_addr_t *) &
+							     (display_ram.
+							      p_rgb_base1),
+							     GFP_KERNEL);
+
+	//display_ram.p_rgb_vrt_base1 = dma_alloc_writecombine(NULL, smem_len,
+	//                              (dma_addr_t *)&dma_addr, GFP_KERNEL);
+
+	//display_ram.p_rgb_base1 =dma_addr;
+
+	display_ram.p_yuv1_base =
+	    display_ram.p_rgb_base1 + display_ram.rgb_len1;
+	display_ram.p_yuv1_vrt_base =
+	    display_ram.p_rgb_vrt_base1 + display_ram.rgb_len1;
+
+	display_ram.p_osd_base =
+	    display_ram.p_rgb_base1 + display_ram.rgb_len1 +
+	    display_ram.yuv1_len;
+	display_ram.p_osd_vrt_base =
+	    display_ram.p_rgb_vrt_base1 + display_ram.rgb_len1 +
+	    display_ram.yuv1_len;
+
+	//lcd_init_display_ram(&display_ram,&lcd_size);
+
+	set_ahb_priority();
+
+	baselcd_controller_init(1);
+
+	lcd_rgb_set_pclk(asic_freq /*124 MHZ */ ,
+			 tft_info.clock_hz /*30 MHZ */ );
+
+	lcd_rgb_set_timing(&tft_info);
+
+	lcd_init_display_ram(&display_ram, &lcd_size);
+
+	lcd_rgb_set_interface(if_mode);
+
+	//baselcd_reset_panel();
+
+	lcd_rgb_start_refresh();
+
+	baselcd_set_panel_backlight(1);
+
+	printk("display_init()\n");
+
+	//mdelay(1000);
+	//for(i=0;i<2;i++)
+	//      lcd_dump_reg();
+
+	memset(display_ram.p_rgb_vrt_base1, 0x00, (lcd_size.ram_size >> 1));
+	//mdelay(1000); 
+	memset(display_ram.p_rgb_vrt_base1 + (lcd_size.ram_size >> 1), 0xff,
+	       (lcd_size.ram_size >> 1));
+
+	addr = (u32) display_ram.p_rgb_vrt_base1;
+
+	split = 8;
+	for (j = 0; j < split; j++) {
+		for (i = 0; i < smem_len / split; i++) {
+			begin = j * (smem_len / split);
+			if (j % 2 == 0)
+				*((char *)(begin + addr + i)) = 0x00;
+			else
+				*((char *)(begin + addr + i)) = 0xff;
+		}
+	}
+
+}
+
+//SYMBOL_EXPORT(display_init);
+
+//#define DEBUG_LCD_1
+#undef DEBUG_LCD_1
+#ifdef DEBUG_LCD_1
+
+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))
+#define IPL_LCD_WIDTH 800
+#define IPL_LCD_HEIGHT 480
+#define IPL_LCD_INTERFACE_TYPE_RGB 1
+#define IPL_LCD_INTERFACE_TYPE_MPU 0
+typedef long DWORD;
+typedef char BYTE;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned long UINT32;
+
+volatile char *pSysCtrlReg = AK88_VA_SYS;
+volatile char *pLcmCtrlReg = AK88_VA_DISP;
+
+#include "AK_lcd.h"
+
+const T_LCD_TIMING_INFO SUPPORT_LCD_TABLE_IPL[] = {
+	//Bus,Interlace, HVG_Pol,RGB_BIT, Clock,      HCycle,VCycle, Thlen,  Thf,Thp,Thb,Tvlen,      Tvf,Tvp,Tvb,pName
+//    {18,       AK_FALSE,  0x6,    0,      9000000,   366,       320,     22,      4,       20,       492,      480,    4,        4,      4,       "LS035B7UX01"},    
+//       {24,       AK_FALSE,  0x6,    0,      6410000,    280,       240,     10,      20,      10,       326,      320,    2,        2,      2,       "PT035TN01"},
+
+	{18, PROGRESS, 0x6, 0x1888, 9000000, 19560, 5994, 366, 320, 22, 4, 20,
+	 492, 480, 4, 4, 4, "LS035B7UX01"},
+	{18, PROGRESS, 0x6, 0x1888, 9000000, 19560, 5994, 254, 240, 2, 10, 2,
+	 365, 400, 3, 39, 3, "R61509"},
+	{18, PROGRESS, 0x6, 0x1888, 9000000, 19560, 5994, 254, 240, 2, 10, 2,
+	 365, 320, 3, 39, 3, "HX8347"},
+	{24, PROGRESS, 0x6, 0x1888, 9000000, 17140, 5994, 525, 480, 2, 41, 2,
+	 286, 272, 2, 10, 2, "AT043TN134"},
+	{24, PROGRESS, 0x6, 0x1888, 6410256, 15711, 5884, 408, 320, 20, 30, 38,
+	 267, 240, 1, 3, 23, "PT035TN01"},
+	{24, PROGRESS, 0xe, 0x0888, 30000000, 15711, 5884, 1058, 800, 170, 48,
+	 40, 553, 480, 40, 4, 29, "HSD070IDW1-A00"},
+
+	//{18,        PROGRESS, 0xe, 0x1888, 9000000, 17140, 5994, 525, 480, 2, 41, 2, 286, 272, 2, 10, 2, "LQ043T3DX04"},
+	//{24,        PROGRESS, 0x6,    0x1888,  10000000, 19560, 5994, 280, 240, 10, 20, 10, 326, 320, 2, 2, 2, "SSD1289"},
+
+};
+
+void Del_1us(void)
+{
+	volatile unsigned int i, j;
+	for (i = 0; i < 6000; i++) {
+		for (j = 0; j < 2; j++) ;
+	}
+
+}
+
+void DelayX1ms(volatile unsigned int m)
+{
+	volatile unsigned int i;
+	for (i = 0; i < m; i++)
+		Del_1us();
+}
+
+#define SYS_RST_CLK_CTL_OFFSET (0x000c)	//0x0800,000c
+#define SYS_RST_LCD            (1 << 19)
+#define CLOCK_DSA_DISPLAY      (1 <<3 )
+
+void IPL_LCDCInitRGB(DWORD DispBuf, DWORD picWidth, DWORD picHeight,
+		     DWORD picHStart, DWORD picVStart)
+{
+	DWORD temp;
+	DWORD dwASICFreq;
+	int width, height;
+	int startX, startY;
+	const T_LCD_TIMING_INFO *pLcdInfo;
+	//IOCTL_SHAREPIN  pinInfo = {0};
+
+#define IPL_DEBUG 0
+
+	if (DispBuf == (DWORD) NULL) {
+		//OALMSG( IPL_DEBUG, (TEXT("IplInit_Display_error\r\n")) );
+		printk("IplInit_Display_error\r\n");
+		return;
+	}
+	//pLcdInfo = &SUPPORT_LCD_TABLE_IPL[ ID_2_INDEX(LCD_ID) ];
+	pLcdInfo = &SUPPORT_LCD_TABLE_IPL[5];	//HSD070IDW1-A00
+	if (picWidth > pLcdInfo->Thd_PClk) {
+		width = pLcdInfo->Thd_PClk;
+	} else {
+		width = picWidth;
+	}
+
+	if (picHeight > pLcdInfo->Tvd_HCLK) {
+		height = pLcdInfo->Tvd_HCLK;
+	} else {
+		height = picHeight;
+	}
+
+	startY = (pLcdInfo->Tvd_HCLK - height) >> 1;
+	startX = (pLcdInfo->Thd_PClk - width) >> 1;
+	//OALMSG(IPL_DEBUG, (TEXT("width %d, height %d, startX %d, startY %d\r\n"), width, height, startX, startY));
+	printk("width %d, height %d, startX %d, startY %d\r\n", width, height,
+	       startX, startY);
+
+	// get ASIC frequency
+	//dwASICFreq = OALHalGetASICFreq();
+	dwASICFreq = ak880x_asicfreq_get();
+	//EdbgOutputDebugString("ASIC freq: %d sizeof = %d\n", dwASICFreq,IPL_LCD_HEIGHT*IPL_LCD_WIDTH*2);
+	printk("ASIC freq: %d sizeof = %d\n", (int)dwASICFreq,
+	       IPL_LCD_HEIGHT * IPL_LCD_WIDTH * 2);
+
+	// --- set and en pclk divider
+	//temp = dwASICFreq / pLcdInfo->ClockCycle_Hz;
+	temp = 124 / 30;
+	temp -= 1;
+	REG32(pLcmCtrlReg + LCD_CLOCK_CONFIG_OFFSET) =
+	    CLOCK_CONFIG_PCLK_EN | CLOCK_CONFIG_PCLK_CFG_VALID |
+	    ((temp << CLOCK_CONFIG_PCLK_DIV_OFFSET) &
+	     CLOCK_CONFIG_PCLK_DIV_MASK);
+
+	// --- set sharePin(MPU_RST and LCD_DATA[17:8]
+	//pinInfo.pinGrp = eSHARE_GPIO_DISPLAY;
+	//KernelIoControl(IOCTL_HAL_LOCKSET_GPIO_SHAREPIN, &pinInfo, sizeof(IOCTL_SHAREPIN), NULL, 0, NULL);
+
+	//#define AK88_SHAREPIN_CTRL    (ANYKA_PA_SYS+0x0078)   //0x08000078
+	AKSET_BITS(1UL << 25, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[15:9]
+	AKSET_BITS(1UL << 26, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[8]
+	AKSET_BITS(1UL << 27, AK88_SHAREPIN_CTRL);	//set pin as LCD_DATA[17:16]
+	AKSET_BITS(1UL << 28, AK88_SHAREPIN_CTRL);	//set pin as #MPU_RST
+
+	// --- set RGB mode
+	temp = REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET));
+	temp &= ~CMD1_IF_MODE_MASK;
+	temp |= CMD1_IF_RGB;
+	REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET)) = temp;
+
+	//--- set timing
+
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL1_REG_OFFSET)) =
+	    RGB_CTRL1_WIDTH_18 | (pLcdInfo->Interlace) | (pLcdInfo->
+							  HVG_POL &
+							  RGB_CTRL1_HVG_POL_MASK);
+	//thp and tvp
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL3_REG_OFFSET)) =
+	    (pLcdInfo->Thp_PClk << RGB_CTL3_THPW_PCLK_OFFSET) | (pLcdInfo->
+								 Tvp_PClk <<
+								 RGB_CTL3_TVPW_OFFSET);
+	//thb and thd
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL4_REG_OFFSET)) =
+	    (pLcdInfo->Thb_PClk << RGB_CTL4_THB_PCLK_OFFSET) | (pLcdInfo->
+								Thd_PClk <<
+								RGB_CTL4_THD_PCLK_OFFSET);
+
+	//thf and thlen
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL5_REG_OFFSET)) =
+	    (pLcdInfo->Thf_PClk << RGB_CTL5_THF_PCLK_OFFSET) | (pLcdInfo->
+								Thlen_PClk <<
+								RGB_CTL5_THLEN_PCLK_OFFSET);
+	//tvb
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL6_REG_OFFSET)) =
+	    (pLcdInfo->Tvb_PClk << RGB_CTL6_TVB_OFFSET);
+	//tvf
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL7_REG_OFFSET)) =
+	    (pLcdInfo->Tvf_PClk << RGB_CTL7_TVF_OFFSET);
+	//tvd
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL8_REG_OFFSET)) =
+	    (pLcdInfo->Tvd_HCLK << RGB_CTL8_TVD_OFFSET);
+	//tvlen
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL9_REG_OFFSET)) =
+	    (pLcdInfo->Tvlen_HCLK << RGB_CTL9_TVLEN_OFFSET);
+
+	//set rgb or bgr and alr
+	temp = REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET));
+	temp &= ~(CMD1_ALR_EMPTY_MASK | CMD1_ALR_FULL_MASK);
+	//Pclk polarity
+	if (pLcdInfo->HVG_POL & 0x8)
+		temp |= 1 << 4;
+	else
+		temp &= ~(1 << 4);
+	temp |=
+	    ((EMPTY_ALARM_BYTES << CMD1_ALR_EMPTY_OFFSET) |
+	     (FULL_ALARM_BYTES << CMD1_ALR_FULL_OFFSET));
+	if ((pLcdInfo->RGB_BIT & (0x1 << 12)) == 0)
+		temp |= CMD1_SEQ_BGR;
+	else
+		temp &= ~CMD1_SEQ_BGR;
+
+	REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET)) = temp;
+
+	//set display area size(NOTE: width is at hight bits)
+	REG32((DWORD *) (pLcmCtrlReg + LCD_GINFO_REG_OFFSET)) =
+	    (pLcdInfo->Tvd_HCLK << GINFO_VER_OFFSET) | (pLcdInfo->
+							Thd_PClk <<
+							GINFO_HOR_OFFSET);
+
+	// --- set starting buffer address of RGB channel
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL2_REG_OFFSET)) &=
+	    ~RGB_CTRL1_CFBA_MASK;
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_CTRL2_REG_OFFSET)) =
+	    (DispBuf) & RGB_CTRL1_CFBA_MASK;
+
+	// --- RGB virtual page
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_VIRT_LEN_REG_OFFSET)) =
+	    (pLcdInfo->Thd_PClk << RGB_VIRT_LEN_H_PXL_OFFSET) | (pLcdInfo->
+								 Tvd_HCLK <<
+								 RGB_VIRT_LEN_V_PXL_OFFSET);
+
+	// --- RGB channel offset
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_OFFSET_REG_OFFSET)) = 0;
+
+	// --- RGB channel width/height(NOTE: width is at hight bits)
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_SIZE_REG_OFFSET)) =
+	    (pLcdInfo->Thd_PClk << RGB_SIZE_H_OFFSET) | (pLcdInfo->Tvd_HCLK);
+
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_VIRT_OFFSET_REG_OFFSET)) = 0;
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RGB_OFFSET_REG_OFFSET)) = 0;
+
+	// --- enable RGB channel
+	temp = REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET));
+	temp |= CMD1_RGB_CH_EN;
+	REG32((DWORD *) (pLcmCtrlReg + LCD_CMD1_REG_OFFSET)) = temp;
+
+	//reset
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RESET_SIGNAL_REG_OFFSET)) =
+	    RESET_SIGNAL;
+	DelayX1ms(10);
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RESET_SIGNAL_REG_OFFSET)) = 0;
+	DelayX1ms(10);
+	REG32((DWORD *) (pLcmCtrlReg + LCD_RESET_SIGNAL_REG_OFFSET)) =
+	    RESET_SIGNAL;
+	DelayX1ms(20);
+
+	//Set_LCDCmd((volatile BYTE *)pSysCtrlReg, 0);   //change
+	bsplcd_set_panel_power(0);	//DGPIO26,DGPIO25
+	baselcd_set_panel_backlight(0);	//GPIO9
+	DelayX1ms(200);
+	//Set_LCDCmd((volatile BYTE *)pSysCtrlReg, 1);
+	bsplcd_set_panel_power(1);
+	baselcd_set_panel_backlight(1);
+
+	DelayX1ms(200);
+
+	// --- update software configuratioin
+	REG32((DWORD *) (pLcmCtrlReg + LCD_SOFTWARE_CTRL_REG_OFFSET)) |=
+	    SOFTWARE_CTRL_SW_EN;
+
+	// --- start refresh
+	REG32((DWORD *) (pLcmCtrlReg + LCD_OPERATE_REG_OFFSET)) &=
+	    ~OPERATE_SYS_STOP;
+	REG32((DWORD *) (pLcmCtrlReg + LCD_OPERATE_REG_OFFSET)) |=
+	    OPERATE_RGB_GO;
+}
+
+void IPL_LCDCInit(DWORD DispBuf, int picWidth, int picHeight, int picHStart,
+		  int picVStart)
+{
+	// --- reset lcd interface
+	REG32((DWORD *) (pSysCtrlReg + SYS_RST_CLK_CTL_OFFSET)) |= SYS_RST_LCD;
+	REG32((DWORD *) (pSysCtrlReg + SYS_RST_CLK_CTL_OFFSET)) &= ~SYS_RST_LCD;
+	// --- open LCD controller clock
+	REG32(pSysCtrlReg + SYS_RST_CLK_CTL_OFFSET) &= ~CLOCK_DSA_DISPLAY;
+
+	// REG32(AK88_AHB_PRIORITY) &= ~0x7f;    //set dma priority higher than ARM priority
+
+#if IPL_LCD_INTERFACE_TYPE_MPU
+	IPL_LCDCInitMPU(DispBuf, picWidth, picHeight, picHStart, picVStart);
+#elif IPL_LCD_INTERFACE_TYPE_RGB
+	IPL_LCDCInitRGB(DispBuf, picWidth, picHeight, picHStart, picVStart);
+#endif
+
+}
+
+bool OEMIPLInit(void)
+{
+
+	DWORD DisplayPhysicalBuffer = AK88_PA_DISPRAM_RGB;
+	DWORD DisplayVirtualBuffer = AK88_VA_DISPRAM_RGB;
+
+	unsigned int i, j, split, begin;
+	DWORD addr, vir_addr, smem_len;
+
+	//REG32(AK88_AHB_PRIORITY) &=~0x7f;    //set dma priority higher than ARM priority
+	set_ahb_priority();
+
+	smem_len = IPL_LCD_WIDTH * IPL_LCD_HEIGHT * 2;
+
+	DisplayVirtualBuffer = dma_alloc_writecombine(NULL, smem_len,
+						      (dma_addr_t *) &
+						      DisplayPhysicalBuffer,
+						      GFP_KERNEL);
+
+	printk
+	    ("DisplayPhysicalBuffer=0x%x,DisplayVirtualBuffer=0x%x,smem_len=%d\n",
+	     (u32) DisplayPhysicalBuffer, (u32) DisplayVirtualBuffer,
+	     (int)smem_len);
+
+	printk("Bat is larger than 3.45V!\r\n");
+
+	//REG32(0xf020d014) &=~0x7f;    //AHB priority
+
+	IPL_LCDCInit(DisplayPhysicalBuffer, IPL_LCD_WIDTH, IPL_LCD_HEIGHT, 0,
+		     0);
+	//LocalBacklightInit();
+
+	baselcd_set_panel_backlight(1);
+
+	//addr=DisplayPhysicalBuffer;
+	addr = DisplayVirtualBuffer;
+
+	memset((void *)(addr), 0x00, (smem_len >> 1));
+	memset((void *)(addr + (smem_len >> 1)), 0xff, (smem_len >> 1));
+
+	split = 8;
+	for (j = 0; j < split; j++) {
+		for (i = 0; i < smem_len / split; i++) {
+			begin = j * (smem_len / split);
+			if (j % 2 == 0)
+				*((char *)(begin + addr + i)) = 0x00;
+			else
+				*((char *)(begin + addr + i)) = 0xff;
+		}
+	}
+
+#if 0
+	for (i = 0; i < smem_len / 4; i++)
+		*((char *)(addr + i)) = 0x00;
+	for (i = 0; i < smem_len / 4; i++)
+		*((char *)(addr + (smem_len / 4) + i)) = 0xff;
+	for (i = 0; i < smem_len / 4; i++)
+		*((char *)(addr + (smem_len / 2) + i)) = 0x00;
+	for (i = 0; i < smem_len / 4; i++)
+		*((char *)(addr + (smem_len / 2) + (smem_len / 4) + i)) = 0xff;
+#endif
+
+	DelayX1ms(1000);
+
+	lcd_dump_reg();
+	mdelay(100);
+	lcd_dump_reg();
+
+	printk("----OEMIPLInit\r\n");
+	return true;
+
+}
+
+#endif
diff --git a/arch/arm/mach-ak88/lib_mmu.S b/arch/arm/mach-ak88/lib_mmu.S
new file mode 100644
index 00000000000..f460508d8da
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_mmu.S
@@ -0,0 +1,15 @@
+ @void mmu_clean_flash_dcache
+            .global mmu_clean_flash_dcache
+	mmu_clean_flash_dcache:
+             mrc p15,0,r15,c7,c10,3
+             bne mmu_clean_flash_dcache
+             mov pc,lr
+
+ 
+   @void mmu_clean_invalidate_dcache
+            .global mmu_clean_invalidate_dcache
+	mmu_clean_invalidate_dcache:
+             mrc p15,0,r15,c7,c14,3
+             bne mmu_clean_invalidate_dcache
+             mov pc,lr
+
diff --git a/arch/arm/mach-ak88/lib_uart.c b/arch/arm/mach-ak88/lib_uart.c
new file mode 100644
index 00000000000..9c96fcd2238
--- /dev/null
+++ b/arch/arm/mach-ak88/lib_uart.c
@@ -0,0 +1,1903 @@
+/**
+ * @file uart.c
+ * @brief UART driver, define UARTs APIs.
+ * This file provides UART APIs: UART initialization, write data to UART, read data from
+ * UART, register callback function to handle data from UART, and interrupt handler.
+ * Copyright (C) 2004 Anyka (GuangZhou) Software Technology Co., Ltd.
+ * @author ZouMai
+ * @date 2004-09-16
+ * @version 1.0
+ * @ref AK8802 technical manual.
+ */
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#include <asm/io.h>
+#include <mach/map.h>
+#include <mach/lib_uart.h>
+#include <mach/lib_l2.h>
+
+#define UART_RX_FIFO_SIZE       (32)	//1//128 bytes
+
+typedef void (*t_fuart_hisr_handler) (void);
+
+typedef struct {
+	unsigned int baudrate;
+	unsigned char b_interrupt;
+	unsigned char b_open;
+
+	unsigned char b_use_dma;
+	t_fuart_callback callback_func;
+	unsigned char *dma_tx_buffer;
+	unsigned int dma_tx_buffer_length;
+	unsigned char *dma_rx_buffer[2];
+	unsigned char dma_rx_buffer_shift;
+	unsigned char *p_dma_tx_buffer;
+	unsigned int n_trans_count;
+	unsigned int n_trans_complete_count;
+	unsigned char *p_receive_pool;
+	unsigned int n_receive_pool_length;
+	unsigned int n_receive_pool_head;
+	unsigned int n_receive_pool_tail;
+	unsigned int rxfifo_offset;	//4bytes in unit, it refer to the buffer in l2 memory,for example 0x48001000~0x4800180
+
+	unsigned int timeout_delay_us;
+
+} T_UART;
+
+static volatile T_UART m_uart[MAX_UART_NUM] = { {0} };
+
+#define	TX_STATUS		1
+#define	RX_STATUS		0
+
+/*
+ * @brief: Get Uart's base register address
+ */
+//#define  uart_id2register(uart_id) 
+//    (UART0_BASE_ADDR+(T_U32)(uart_id)*0x1000)
+
+#define uart_id2register(uart_id/*0~3*/)  (unsigned int) (AK88_UART_BASE+(unsigned int)(uart_id/*0~3*/)*0x1000)	//0x20026000
+
+//static void uart2_flowcontrol_init(void);
+unsigned char uart0_interrupt_handler(void);
+unsigned char uart1_interrupt_handler(void);
+//static unsigned char uart2_interrupt_handler(void);
+//static unsigned char uart3_interrupt_handler(void);
+static void uart_handler(unsigned char uart_id);
+static void uart_storedata(unsigned char uart_id, unsigned char *data,
+			   unsigned int datalen);
+static unsigned int uart_read_fifo(unsigned char uart_id, unsigned char *chr,
+				   unsigned int count);
+
+void uart_clock_ctl(unsigned char uart_id, unsigned char enable)
+{
+	volatile unsigned int value;
+
+	value = __raw_readl(AK88_POWER_CLOCK);   //0x0800,000c
+
+	switch (uart_id) {
+	default:
+	case uiUART0:
+		if (enable) 	//VME_SetSleepModeConfig(CLOCK_UART0_ENABLE);    //bit15
+			value &=~(1UL<<15);		
+		else		//VME_SetSleepModeConfig(~CLOCK_UART0_ENABLE);
+			value |=(1UL<<15);
+		break;
+#ifdef CHIP_780X
+	case uiUART1:
+		if (enable) ;	//VME_SetSleepModeConfig(CLOCK_UART1_ENABLE);
+		else;		//VME_SetSleepModeConfig(~CLOCK_UART1_ENABLE);
+		break;
+	case uiUART2:
+		if (enable) ;	//VME_SetSleepModeConfig(CLOCK_UART2_ENABLE);
+		else;		//VME_SetSleepModeConfig(~CLOCK_UART2_ENABLE);
+		break;
+#endif
+	case uiUART3:
+		if (enable) 	//VME_SetSleepModeConfig(CLOCK_UART3_ENABLE);   //bit8
+			value &=~(1UL<<8);
+		else		//VME_SetSleepModeConfig(~CLOCK_UART3_ENABLE);
+			value |=(1UL<<8);
+		break;
+ 	}
+
+	__raw_writel(value, AK88_POWER_CLOCK);	//share pin
+
+}
+
+void uart_pin_ctl(unsigned char uart_id)
+{
+
+	volatile unsigned int value,value1;
+
+	value = __raw_readl(AK88_VA_SYS + 0x78);
+
+	value1 = __raw_readl(AK88_VA_SYS + 0x74);
+
+	/* set share pin to UARTn, and disable pull-up */
+	switch (uart_id) {
+	case uiUART0:
+		//gpio_pin_group_cfg(ePIN_AS_UART1);
+		value |= (1UL << 9);
+		break;
+#ifdef CHIP_780X
+	case uiUART1:
+		//gpio_pin_group_cfg(ePIN_AS_UART2);
+		value |= (1UL << 10);
+		break;
+	case uiUART2:
+		//gpio_pin_group_cfg(ePIN_AS_UART3);
+		value |= (1UL << 12);
+		break;
+#endif
+	case uiUART3:
+		//gpio_pin_group_cfg(ePIN_AS_UART4);
+		value |= (1UL << 14);
+		value |= (1UL << 15);
+		value1 &=~(3UL<<1);
+		value1 |=(1UL<<1);
+		__raw_writel(value1, (AK88_VA_SYS + 0x74));	//share pin
+		break;
+	default:
+		break;
+		value |= (1UL << 9);
+		break;
+		//printk("uart_pin_ctl():unknown uart id %d!!\n", uart_id);
+	}
+
+	__raw_writel(value, (AK88_VA_SYS + 0x78));	//share pin
+
+	value = __raw_readl(AK88_VA_DEV + 0xc084);
+	value |= (3UL << 28);
+	__raw_writel(value, (AK88_VA_DEV + 0xc084));	//dma pin
+
+}
+
+/**
+* @BRIEF Clear transmit or receive status of uart controller
+* @AUTHOR Pumbaa
+* @DATE 2007-08-04
+* @PARAM UART_Select uart_id : uart id
+* @PARAM T_U8 txrx_status : TX_STATUS: clear transmit status; RX_STATUS: clear receive status
+* @RETURN T_VOID: 
+* @NOTE: ...
+*/
+void uart_clear_tx_status(unsigned char uart_id)
+{
+	unsigned int base_addr;
+	volatile unsigned int reg_value;
+
+	base_addr = (unsigned int)uart_id2register(uart_id);
+	reg_value = __raw_readl(base_addr + 0x00);
+
+	reg_value |= (1UL << 28);
+	__raw_writel(reg_value, (base_addr + 0x00));
+}
+
+void uart_clear_rx_status(unsigned char uart_id)
+{
+	unsigned int base_addr;
+	volatile unsigned int reg_value;
+
+	base_addr = (unsigned int)uart_id2register(uart_id);
+	reg_value = __raw_readl(base_addr + 0x00);
+	reg_value |= (1UL << 29);
+	__raw_writel(reg_value, (base_addr + 0x00));
+}
+
+/**
+* @BRIEF clear time out status
+* @AUTHOR Pumbaa
+* @DATE 2007-08-04
+* @PARAM UART_Select uart_id : uart id
+* @RETURN T_VOID: 
+* @NOTE: ...
+*/
+//static T_VOID ClearTimeout(T_UART_ID uart_id)
+unsigned int uart_clear_rx_timeout(unsigned char uart_id)
+{
+	volatile unsigned int reg_value;
+	unsigned int base_addr;
+
+	base_addr = uart_id2register(uart_id);	//0x20026004
+	reg_value = __raw_readl(base_addr + 0x04);
+	reg_value |= (1UL << 2);	//clear timeout int status
+	//reg_value &= ~(1<<3); ?
+	reg_value |= (1UL << 3);	//clear R_err int status
+	//outl(reg_value, (base_addr+0x04));
+	__raw_writel(reg_value, (base_addr + 0x04));
+
+	reg_value = ((__raw_readl(base_addr + 0x08)) >> 23) & 0x03;
+
+	return reg_value;
+
+}
+
+void uart_clear_rx_err(unsigned char uart_id)
+{
+	volatile unsigned int reg_value;
+	unsigned int base_addr;
+
+	base_addr = uart_id2register(uart_id);	//0x20026004
+	reg_value = __raw_readl(base_addr + 0x04);
+	reg_value |= (1UL << 3);	//clear R_err int status
+	__raw_writel(reg_value, (base_addr + 0x04));
+
+	return;
+
+}
+
+void uart_clear_rx_buffull(unsigned char uart_id)
+{
+	volatile unsigned int reg_value;
+	unsigned int base_addr;
+
+	base_addr = uart_id2register(uart_id);	//0x20026000
+	//bit[1]:RX_buf_full, 1=The receiving buffer is full.
+	//                Notes:This bit is cleared by being written with 1.
+	reg_value = __raw_readl(base_addr + 0x04);	//0x20026004
+	reg_value |= (1UL << 1);
+	//reg_value &= ~(1<<3);?
+	reg_value |= (1UL << 3);
+	//outl(reg_value, (base_addr+0x04));
+	__raw_writel(reg_value, (base_addr + 0x04));
+
+}
+
+void uart_clear_rx_th(unsigned char uart_id)
+{
+	volatile unsigned int reg;
+	unsigned int base_addr;
+	//0x2002600c,TX/RX Threshold Register
+	//bit[5]:Rx_th_clr,1=To clear Rx_th interrupt,and prevent the threshold counting.
+
+	//0x20026004,UARTn Configuration Reg2 
+	//bit[30]:Rx_th_int_sta,1=A RX_th interrupt is generated
+	//Note:
+	//  2.The receive buffer threshold value is set by bits[4:0] of 0x2002600C.
+	//  3.This bit is cleared by being written with 1 or when Rx_th_clr,bit[5]
+	//    of 0x2002600C is '1'
+
+	base_addr = uart_id2register(uart_id);	//0x20026000
+
+	reg = __raw_readl(base_addr + 0x0c);
+	reg |= (1UL << 5);
+	__raw_writel(reg, base_addr + 0x0c);
+	//reg &= ~(1<<5);
+	//__raw_writel(reg,base_addr+0x0c);
+
+	reg = __raw_readl(base_addr + 0x04);
+	reg |= (1UL << 30);
+	__raw_writel(reg, base_addr + 0x04);
+
+	//reg=__raw_readl(base_addr+0x0c);
+	//reg &= ~(1<<5);
+	//__raw_writel(reg,base_addr+0x0c);
+
+	return;
+
+}
+
+void uart_reen_rx_th(unsigned char uart_id)
+{
+	volatile unsigned int reg;
+	unsigned int base_addr;
+
+	base_addr = uart_id2register(uart_id);	//0x20026000
+
+	reg = __raw_readl(base_addr + 0x0c);
+	reg &= ~(1UL << 5);
+	__raw_writel(reg, base_addr + 0x0c);
+}
+
+#define	UART_TX_END_STA				    (1UL<<19)
+#define	UART_RX_TIMEOUT				    (1UL<<2)
+
+unsigned char uart_wait_tx_finish(unsigned char uart_id)
+{
+	volatile unsigned int baseAddress, status;
+
+	baseAddress = uart_id2register(uart_id);
+
+	while (1) {
+		status = __raw_readl(baseAddress + 0x04);
+		//0x20026004
+		//bit[19]:TX_end: 1=all the data in TX buffer has been sent
+		if (status & UART_TX_END_STA)
+			break;
+	}
+
+	return 1;
+}
+
+unsigned char uart_get_tx_empty(unsigned char uart_id)
+{
+/* if tx send empty,return 1   
+  
+  yes:return 1;
+  no :return 0;
+
+*/
+	volatile unsigned int base_address, status;
+
+	base_address = uart_id2register(uart_id);
+	status = __raw_readl(base_address + 0x04);
+
+	if (status & UART_TX_END_STA)
+		return 1;	//yes ,tx empty,send finish
+	else
+		return 0;
+
+}
+
+//#define ak880x_uart_get_tx_rdy(uart_id)    ((__raw_readl(uart_id2register(uart_id)+0x04)) & (1<<19))? 1:0
+
+unsigned char uart_wait_rx_timeout(unsigned char uart_id)
+{
+	volatile unsigned int base_address, status;
+
+	base_address = uart_id2register(uart_id);
+
+	while (1) {
+		status = __raw_readl(base_address + 0x04);
+		//0x20026004
+		//bit[2]:timeout,1=the receiving timeout occurs.
+		if (status & UART_RX_TIMEOUT)
+			break;
+	}
+
+	return 1;
+}
+
+unsigned char uart_get_rx_timeout(unsigned char uart_id)
+/*yes:return 1;
+  no :return 0;
+*/
+{
+	volatile unsigned int base_address, status;
+
+	base_address = uart_id2register(uart_id);
+	status = __raw_readl(base_address + 0x04);
+
+	if (status & (1UL << 2))
+		return 1;	//yes,timeout occur
+	else
+		return 0;
+
+	//while(!(__raw_readl(baseAddress+0x04)&(1<<2)))            //0x20026004        
+	//{} 
+	//bit2(0x20026004):timeout,1=the receiving timeout occurs.
+	//Note:
+	//   1.Please refer to bit[23] of 0x20026000 for the definition of timeout function
+	//   2.When this bit is set to 1,programmers should begin to process the data in received buffer
+	//   3.This bit is cleared by being written with 1.
+	//
+	//UART module can only process 4-byte data in a data transfer operation.
+	//if no more data is received when the waiting time(32 bit cycles) is out ,an interrupt is generated(if enabled)
+	//and the data left is transmitted to L2 memory.
+	//
+}
+
+unsigned char uart_get_rx_buffull(unsigned char uart_id)
+/*yes:return 1;
+  no :return 0;
+*/
+{
+	volatile unsigned int base_address, status;
+
+	base_address = uart_id2register(uart_id);
+	status = __raw_readl(base_address + 0x04);
+
+	if (status & (1UL << 1))
+		return 1;	//yes,the receive buffer is full.
+	else
+		return 0;
+}
+
+//#define ak880x_uart_get_rx_rdy(uart_id)    ((__raw_readl(uart_id2register(uart_id)+0x04))&(1<<2))? 1:0
+
+unsigned char uart_init(unsigned char uart_id /*0~3 */ , unsigned int baud_rate,
+			unsigned int sys_clk)
+{
+	unsigned int base_address;
+	unsigned int reg_baud;
+
+	if (uart_id > MAX_UART_NUM)
+		return AK_FALSE;
+
+	base_address = uart_id2register(uart_id);
+
+	//set sharepin
+	if (uart_id == 0)
+		AKSET_BITS(1UL << 9, AK88_SHAREPIN_CTRL);
+	else if (uart_id == 3) {
+		AKSET_BITS(1UL << 15, AK88_SHAREPIN_CTRL);
+		AKSET_BITS(1UL << 14, AK88_SHAREPIN_CTRL);
+		AKCLR_BITS(3UL << 1, AK88_SHAREPIN_CTRL2);
+		AKSET_BITS(1UL << 1, AK88_SHAREPIN_CTRL2);
+	}
+	//else return AK_FALSE;
+
+	printk("uart_init(%d)/AK88_POWER_CLOCK=0x%x\n",uart_id,AK88_POWER_CLOCK);
+
+	//open power clock
+	if (uart_id == 0)
+		AKCLR_BITS(1UL << 15, AK88_POWER_CLOCK);
+	else if (uart_id == 3) 		//AKCLR_BITS(1UL<<24,AK88_POWER_CLOCK); // ?
+	{
+		AKCLR_BITS(1UL << 8, AK88_POWER_CLOCK);
+		AKCLR_BITS(1UL << 24, AK88_POWER_CLOCK);  //to reset UART4
+ 	}
+	else ;
+
+	printk("uart_init(%d)/AK88_POWER_CLOCK=0x%x\n",uart_id,AK88_POWER_CLOCK);
+ 
+	//set dma flag
+	AKSET_BITS(0x3UL << 28, AK88_VA_DEV + 0xc084);
+	//(*(volatile u32*)0x2002c084) |=  0x3UL<<28 ;
+	//0x2002c084, ldma_flag_en|Ahb_flag_en
+
+	//open flowcontrol
+	/* should reverse CTS */
+	//if (uart_id != 0)  //open flowcontrol
+	//{
+		//reg_value |= (1UL << 18) | (1UL << 19);
+		//AKSET_BITS(1UL<<18,AK88_UART_CFG_REG1(uart_id) );
+		//AKSET_BITS(1UL<<19,AK88_UART_CFG_REG1(uart_id) );
+	//}
+
+	//mask all interrupts
+	__raw_writel(0, AK88_UART_CFG_REG2(uart_id));	//mask all interrupt
+
+	reg_baud = sys_clk/baud_rate - 1;
+
+	//printk("sys_clk=%d,baud_rate=%d,reg_baud=0x%x\n",sys_clk,baud_rate,reg_baud);
+
+	reg_baud |=(1UL<<29)|(1UL<<28)|(1UL<<21); //clear_tx_stat|clear_tx_stat|uart_enable
+ 
+	printk("uart_id=%d,sys_clk=%d,baud_rate=%d,reg_baud=0x%x\n",uart_id,sys_clk,baud_rate,reg_baud);
+
+	//__raw_writel(reg_baud, AK88_UART_CFG_REG1(uart_id));
+
+	
+	//open flowcontrol
+	/* should reverse CTS */
+	if (uart_id != 0)  //open flowcontrol
+	{
+		//reg_value |= (1UL << 18) | (1UL << 19);
+		AKSET_BITS(1UL<<18,AK88_UART_CFG_REG1(uart_id) );
+		AKSET_BITS(1UL<<19,AK88_UART_CFG_REG1(uart_id) );
+	}
+ 
+	//set baud_rate
+	//baud=0x30200433; //ak880x,default freq=124000000
+	//baud=0x30200219; //ak780x,default freq=62000000
+
+	return AK_TRUE;
+}
+
+ 
+#if 0
+unsigned char uart_enable_int(unsigned char uart_id /*0~3 */ )
+{
+	unsigned int br_value;
+	unsigned int reg_value;
+	unsigned int base_address;
+
+	base_address = uart_id2register(uart_id);
+
+	reg_value = __raw_readl(base_address + 0x04);	//20026004
+
+	//reg_value |=1<<29;  //TX_th_int
+	reg_value |= 1 << 27;	//TX_end_int
+	//reg_value |=1<<25;  //RX_buff_full_int
+	//reg_value |=1<<23;  //R_err_int
+	reg_value |= 1 << 22;	//timeout_int
+
+	__raw_writel(reg_value, base_address + 0x04);
+
+	return 0;
+}
+#endif
+
+//T_BOOL uart_init(T_UART_ID uart_id, T_U32 baud_rate, T_U32 sys_clk)
+unsigned char uart_init_old(unsigned char uart_id /*0~3 */ ,
+			    unsigned int baud_rate, unsigned int sys_clk)
+{
+	volatile unsigned int br_value;
+	volatile unsigned int reg_value;
+	unsigned int baseAddress;
+
+	if (uart_id > MAX_UART_NUM)
+		return AK_FALSE;
+
+	baseAddress = uart_id2register(uart_id);
+
+#if 1				//temprary close
+	/* clock control */
+	uart_clock_ctl(uart_id, AK_TRUE);
+
+	/* share pin and pull-up control */
+	uart_pin_ctl(uart_id);
+
+	/* set baudrate */
+	br_value = sys_clk / baud_rate - 1;
+	reg_value = br_value & 0xffff;
+
+	if (sys_clk % baud_rate)
+		reg_value |= (1 << 22);
+	/*bit22:(0x20026000)DIV_ADJ,1=to enable baud rate adjustment function */
+#endif
+
+#if 1
+	/* bit21: enable uartn interface 
+	   bit23: enable timeout
+	   bit28,29: clear status
+	 */
+	reg_value |= (1 << 20) | (1 << 21) | (1 << 28) | (1 << 29);
+	//if (uart_id == uiUART0)
+	reg_value |= (1 << 23);	//enable timeout
+
+	//disable rx threshold
+	//reg_value &= ~(1<<28);
+
+	/* should reverse CTS */
+	if (uart_id != uiUART0)
+		reg_value |= (1 << 18) | (1 << 19);
+
+	//HAL_WRITE_UINT32(baseAddress+UART_CFG_REG1, reg_value);
+	//HAL_WRITE_UINT32(baseAddress+UART_CFG_REG2, 0);//mask all interrupt
+	__raw_writel(reg_value, AK88_UART_CFG_REG1(uart_id));
+	__raw_writel(0, AK88_UART_CFG_REG2(uart_id));	//mask all interrupt
+
+#endif
+	if (m_uart[uart_id].b_open == AK_FALSE) {
+		m_uart[uart_id].callback_func = AK_NULL;
+	}
+	m_uart[uart_id].baudrate = baud_rate;
+	m_uart[uart_id].b_open = AK_TRUE;
+
+	m_uart[uart_id].b_use_dma = AK_FALSE;
+	m_uart[uart_id].p_dma_tx_buffer = AK_NULL;
+	m_uart[uart_id].dma_rx_buffer[0] = AK_NULL;
+	m_uart[uart_id].dma_rx_buffer[1] = AK_NULL;
+	m_uart[uart_id].dma_rx_buffer_shift = 0;
+	m_uart[uart_id].dma_tx_buffer = AK_NULL;
+	m_uart[uart_id].dma_tx_buffer_length = 0;
+
+	m_uart[uart_id].n_trans_count = 0;
+	m_uart[uart_id].n_trans_complete_count = 0;
+
+	m_uart[uart_id].p_receive_pool = AK_NULL;
+	m_uart[uart_id].n_receive_pool_length = 0;
+	m_uart[uart_id].n_receive_pool_head = 0;
+	m_uart[uart_id].n_receive_pool_tail = 0;
+	m_uart[uart_id].rxfifo_offset = 0;
+
+	baud_rate = (0 == baud_rate) ? 115200 : baud_rate;
+#ifdef CHIP_780X
+
+	if (uiUART2 == uart_id) {
+		// count each cycle used us number
+		m_uart[uart_id].timeout_delay_us = 1000000 * 64 / baud_rate;
+	} else {
+		// count each cycle used us number
+		m_uart[uart_id].timeout_delay_us = 560;
+	}
+#endif
+	return AK_TRUE;
+}
+
+//T_BOOL uart_set_DMA_mode(T_UART_ID uart_id, T_U8 *DMATXBuffer, T_U32 DMATXBufferLength, T_U8 *DMARXBuffer, T_U32 DMARXBufferLength)
+unsigned char uart_set_dma_mode(unsigned char uart_id /*0~3 */ ,
+				unsigned char *dma_tx_buffer,
+				unsigned int dma_tx_buffer_length,
+				unsigned char *dma_rx_buffer,
+				unsigned int dma_rx_buffer_length)
+{
+
+	if (uart_id > MAX_UART_NUM)
+		return AK_FALSE;
+/*
+    if(dma_tx_buffer == AK_NULL || dma_rx_buffer == AK_NULL)
+        return AK_FALSE;
+
+    baseAddress = uart_id2register( uart_id );
+
+    m_uart[uart_id].b_use_dma = AK_TRUE;
+
+    m_uart[uart_id].dma_tx_buffer = dma_tx_buffer;
+    m_uart[uart_id].dma_tx_buffer_length = dma_tx_buffer_length;
+
+    m_uart[uart_id].dma_rx_buffer[0] = dma_rx_buffer;
+    m_uart[uart_id].dma_rx_buffer[1] = dma_rx_buffer + dma_rx_buffer_length / 2;
+
+    return AK_TRUE;
+*/
+	//to be implemented
+	return AK_FALSE;
+}
+
+//T_VOID uart_on_change( T_U32 sys_clk )
+void uart_on_change(unsigned int sys_clk)
+{
+
+	unsigned char i;
+	volatile unsigned int baseAddress, br_value, reg_value;
+
+	for (i = uiUART0; i < MAX_UART_NUM; i++) {
+		if (m_uart[i].b_open) {
+			baseAddress = uart_id2register(i);
+
+			br_value = sys_clk / m_uart[i].baudrate - 1;
+
+			reg_value = __raw_readl(baseAddress + 0x00);
+
+			reg_value &= ~(0xffff);
+			reg_value &= ~(1UL << 22);
+			//bit22(0x20026000):DIV_ADJ,1=to enable baud rate adjustment function
+			//                 Notes:
+			//                  1.When baud rate adjustment function is enabled,the bit cycle of data frame will be extended one more
+			//                    ASIC CLK cycle than that configured.
+			//                  2.This function is used to reduce the tolerance caused by the inaccurate ratio of frequency dividing.
+			reg_value |= (br_value & 0xffff);
+			if (sys_clk % m_uart[i].baudrate)
+				reg_value |= (1UL << 22);
+
+			__raw_writel(reg_value, baseAddress + 0x00);
+		}
+	}
+}
+
+extern unsigned char b_test;
+
+//#define       UART_TX_END_STA                             (1<<19)
+/* this function for byte_nbr<64 ,64 is the dma transfer unit */
+unsigned char uart_write_buf(unsigned char uart_id /*0~3 */ ,
+			     unsigned char *chr,
+			     unsigned int byte_nbr
+			     /*<60,last 4 bytes(0x3c/0x7c) write 0 */ )
+{
+	unsigned int baseAddress;
+	//unsigned int status;
+	volatile unsigned int reg_value;
+	unsigned char buf_id = 8 + (uart_id << 1);
+	unsigned int buf_addr;
+	//unsigned int buf_addr, i,cnt=0;
+	//unsigned int value1,value2;
+	//unsigned int count = 0;
+
+	//if(m_uart[ uart_id ].b_open == AK_FALSE)   return AK_FALSE;
+
+	if (byte_nbr >= 64)
+		return AK_FALSE;
+
+	baseAddress = uart_id2register(uart_id);
+	//buf_addr = L2_BUF_MEM_BASE_ADDR + 4096/*8 * 512*/ + ((buf_id-8)<<7);  //0x48000000+0x1000
+	buf_addr = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//<<7 = *128
+
+	l2_clr_uartbuf_status(buf_id /*8~15 */ );
+
+	uart_clear_tx_status(uart_id);
+
+	l2_tran_data_cpu((unsigned int)chr, buf_id, 0, byte_nbr,
+			 1 /*write(send) */ );
+
+	//value1 = ReadBuf(buf_addr+SET_FLAG_OFFSET0); //forbiden to read
+	write_buf(0, buf_addr + 0x3c);
+
+	reg_value = __raw_readl(baseAddress + 0x04);	//0x20026004
+	reg_value &= 0x3fe00000;
+	reg_value |= (byte_nbr << 4) | (1UL << 16);
+	__raw_writel(reg_value, baseAddress + 0x04);
+
+	uart_wait_tx_finish(uart_id);
+
+	return AK_TRUE;
+}
+
+#define	UART_RXFIFO_FULL_STA			(1<<1)
+#define	REG_04_MSK_BIT				(0x3fe00000)
+/*this function for byte_nbr >= 64 bytes, 64 is the dma transfer unit*/
+unsigned int uart_write_cpu(unsigned char uart_id /*0~3 */ ,
+			    const unsigned char *chr,
+			    unsigned int byte_nbr /*>=60 */ )
+{
+	volatile unsigned int reg_value;
+	//unsigned int status;
+	unsigned int base_addr;
+	unsigned int set_flag_addr;
+	unsigned int tran_64_nbr;
+	unsigned int frac_nbr;
+	unsigned int buf_addr;
+	//unsigned int i,j;
+	unsigned int i;
+	unsigned char buf_id;
+	unsigned int ram_addr = (unsigned int)chr;
+
+	base_addr = uart_id2register(uart_id);
+	buf_id = 8 + uart_id * 2;
+
+	l2_clr_uartbuf_status(buf_id);
+	uart_clear_tx_status(uart_id);
+
+	tran_64_nbr = byte_nbr >> 6;
+	frac_nbr = byte_nbr % 64;
+
+	buf_addr = (unsigned int)AK88_VA_L2BUF + 0x1000 + (uart_id << 8);	// <<8 = *256
+
+	if (tran_64_nbr % 2 == 0) {
+		set_flag_addr = buf_addr + 0x3c;
+	} else {
+		set_flag_addr = buf_addr + 0x7c;
+	}
+
+	if (tran_64_nbr || frac_nbr) {
+		reg_value = __raw_readl(base_addr + 0x04);
+		if (reg_value & UART_RXFIFO_FULL_STA) {
+			//printk("F4!\n");
+			while (1) ;
+		}
+		reg_value &= REG_04_MSK_BIT;
+
+		reg_value |= (((tran_64_nbr << 6) + frac_nbr) << 4) | (1 << 16);	//data length
+
+		__raw_writel(reg_value, base_addr + 0x04);
+	}
+	for (i = 0; i < tran_64_nbr; i++) {
+		while (l2_uartbuf_status(buf_id) == 2) {	/*if return is 2, it mean buffer is full, 
+								   if return 1, it mean buffer is half full,
+								   otherwise mean buffer is empty */
+		}
+		if (i % 2 == 0)	//even 64'sbuf
+			l2_tran_data_cpu(ram_addr + (i << 6), buf_id, 0, 64,
+					 1 /*write(send) */ );
+		else		//odd 64'sbuf
+			l2_tran_data_cpu(ram_addr + (i << 6), buf_id, 64, 64,
+					 1 /*write(send) */ );
+	}
+	if (frac_nbr) {
+		while (l2_uartbuf_status(buf_id) == 2) {	/*if return is 2, it mean buffer is full */
+		}
+		if (tran_64_nbr % 2 == 0)	//even
+			l2_tran_data_cpu(ram_addr + (tran_64_nbr << 6), buf_id,
+					 0, frac_nbr, 1);
+		else		//odd
+			l2_tran_data_cpu(ram_addr + (tran_64_nbr << 6), buf_id,
+					 64, frac_nbr, 1);
+
+		if (frac_nbr <= 60)
+			write_buf(0, set_flag_addr);
+	}
+	//putch('Q');
+
+	//while (1 && bTest)
+
+	uart_wait_tx_finish(uart_id);
+
+	//putch('P');
+
+	return byte_nbr;
+}
+
+unsigned int uart_write_dma(unsigned char uart_id, const unsigned char *chr,
+			    unsigned int byte_nbr)
+{
+	volatile unsigned int reg_value;
+	//unsigned int status;
+	unsigned int base_addr;
+	unsigned int set_flag_addr;
+	unsigned int tran_2k_nbr;
+	unsigned int tran_64_nbr;
+	unsigned int frac_nbr;
+	unsigned int i;
+	unsigned char buf_id;
+	unsigned char buf_offset;
+	unsigned int ram_addr = (unsigned int)chr;
+	//MMU_InvalidateDCache();
+
+	base_addr = uart_id2register(uart_id);
+	buf_id = 8 + uart_id * 2;
+	tran_2k_nbr = byte_nbr >> 11;
+	tran_64_nbr = (byte_nbr - (tran_2k_nbr << 11)) >> 6;	//tran_64_nbr: remainder of 2048
+	frac_nbr = byte_nbr % 64;	//frac_nbr: remainder of 64
+	if (tran_64_nbr % 2 == 0) {
+		set_flag_addr = (unsigned int)AK88_VA_L2BUF + 0x1000 + (uart_id << 8) + 0x3c;	//0x48000000
+		buf_offset = 0;
+	} else {
+		set_flag_addr =
+		    (unsigned int)AK88_VA_L2BUF + 0x1000 + (uart_id << 8) +
+		    0x7c;
+		buf_offset = 1;
+	}
+
+	l2_clr_uartbuf_status(buf_id);
+	uart_clear_tx_status(uart_id);
+
+	for (i = 0; i < tran_2k_nbr; i++) {
+		reg_value = __raw_readl(base_addr + 0x04);
+		reg_value &= REG_04_MSK_BIT;
+		reg_value |= (2048 << 4) | (1 << 16);
+		__raw_writel(reg_value, base_addr + 0x04);
+
+		l2_uartbuf_dma(ram_addr + (i << 11), uart_id, 2048, 1);
+		l2_wait_uartbuf_dmafinish(uart_id, 1);
+	}
+	if (tran_64_nbr || frac_nbr) {
+		reg_value = __raw_readl(base_addr + 0x04);
+		reg_value &= REG_04_MSK_BIT;
+		reg_value |= (((tran_64_nbr << 6) + frac_nbr) << 4) | (1 << 16);
+		__raw_writel(reg_value, base_addr + 0x04);
+	}
+	if (tran_64_nbr) {
+		l2_uartbuf_dma(ram_addr + (tran_2k_nbr << 11), uart_id,
+			       (tran_64_nbr << 6), 1);
+		l2_wait_uartbuf_dmafinish(uart_id, 1);
+	}
+	if (frac_nbr) {
+		while (l2_uartbuf_status(buf_id) == 2) {	/*if return is 2, it mean buffer is full */
+		}
+		l2_uartbuf_fracdma(ram_addr + (tran_2k_nbr << 11) +
+				   (tran_64_nbr << 6), uart_id, buf_offset,
+				   frac_nbr, 1);
+		l2_wait_frac_dmafinish();
+
+		if (frac_nbr <= 60)
+			write_buf(0, set_flag_addr);
+	}
+
+	uart_wait_tx_finish(uart_id);
+
+	return byte_nbr;
+}
+
+/**
+ * @brief Write one character to UART base on UART ID
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param T_UART_ID uart_id: UART ID
+ * @param T_U8 chr: The character which will be written to UART
+ * @return T_BOOL: Write character OK or not
+ * @retval AK_TRUE: Successfully written character to UART.
+ * @retval AK_FALSE: Writing character to UART failed.
+ */
+unsigned char uart_write_chr(unsigned char uart_id, unsigned char chr)
+{
+	return uart_write_buf(uart_id, &chr, 1);
+}
+
+/**
+ * @brief Write string to UART base on UART ID
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param T_UART_ID uart_id: UART ID
+ * @param T_U8 *str: The string which will be written to UART
+ * @return T_U32: Length of the data which have been written to UART
+ * @retval
+ */
+unsigned int uart_write_str(unsigned char uart_id, unsigned char *str)
+{
+	unsigned int written_num = 0;
+
+	//if(m_uart[ uart_id ].b_open == AK_FALSE)    return 0;
+
+	/*if(m_uart[uart_id].bUseDMA)
+	   {
+	   akprintf(C3, M_DRVSYS, "Use DMA Mode\n");
+	   return AK_FALSE;
+	   } */
+
+	while (*str != '\0') {
+		uart_write_chr(uart_id, *str);
+		written_num++;
+		str++;
+	}
+
+	return written_num;
+}
+
+/**
+ * @brief Write string data to UART
+ * Write data to UART base on UART ID and data length
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-16
+ * @param T_UART_ID uart_id: UART ID
+ * @param const T_pDATA data: Constant data to be written to UART, this data needn't be end with '\0'
+ * @param T_U32 data_len: Data length
+ * @return T_U32: Length of the data which have been written to UART
+ * @retval
+ */
+unsigned int uart_write(unsigned char uart_id, const unsigned char *data,
+			unsigned int data_len)
+{
+	unsigned int written_num = 0;
+
+	if (m_uart[uart_id].b_open == AK_FALSE)
+		return 0;
+
+#ifdef CHIP_780X
+
+	if (uiUART2 != uart_id)	//for UART3
+	{
+		while (data_len > 0) {
+			if (data_len < write_cnt)
+				write_cnt = data_len;
+
+			//uart_write_buf(uart_id, (T_U8*)data, write_cnt);
+			uart_write_buf(uart_id, (unsigned char *)data,
+				       write_cnt);
+
+			data_len -= write_cnt;
+			data += write_cnt;
+			written_num += write_cnt;
+		}
+	} else			//dma write
+#endif
+	{
+		if (data_len > 0) {
+			written_num = uart_write_dma(uart_id, data, data_len);
+			//written_num = uart_write_cpu(uart_id, data, data_len);
+		}
+	}
+
+	return written_num;
+}
+
+unsigned int uart_read(unsigned char uart_id, unsigned char *data,
+		       unsigned int datalen)
+{
+	unsigned int i = 0;
+
+	if (m_uart[uart_id].b_interrupt == AK_TRUE) {
+		if (m_uart[uart_id].n_receive_pool_length != 0)	//has datapool
+		{
+			for (i = 0; i < datalen; i++) {
+				if (m_uart[uart_id].n_receive_pool_tail !=
+				    m_uart[uart_id].n_receive_pool_head) {
+					data[i] =
+					    m_uart[uart_id].
+					    p_receive_pool[m_uart[uart_id].
+							   n_receive_pool_head++];
+					m_uart[uart_id].n_receive_pool_head &=
+					    (m_uart[uart_id].
+					     n_receive_pool_length - 1);
+				} else
+					break;
+			}
+		}
+	} else {
+		unsigned int len1_3 = datalen & 3;	// len1_3 = 1~3
+		unsigned int len4;	//len4 is 4's multiple
+
+		len4 = datalen - len1_3;
+		if (len4)	//read 4byte align
+		{
+			i += uart_read_fifo(uart_id, data, len4);
+			data += i;
+		}
+		if (len1_3)	//read less than 4byte
+		{
+			while (i < datalen) {
+				uart_read_chr(uart_id, data);
+				i++;
+				data++;
+			}
+		}
+	}
+
+	return i;
+}
+
+/**
+ * @brief Read a character from UART
+ * This function will not return until get a character from UART
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param T_UART_ID uart_id: UART ID
+ * @param T_U8 *chr: character for return
+ * @return T_BOOL: Got character or not
+ * @retval
+ */
+unsigned char uart_read_chr(unsigned char uart_id, unsigned char *chr)
+{
+/* only read one char
+ * 
+ */
+	unsigned char buf_id = 9 + (uart_id << 1);
+	volatile unsigned int reg_value;
+	unsigned int baseAddress, bufferAddress;
+	volatile unsigned int nbr_to_read, timeout_count;
+	unsigned char *p_buffer;
+
+	if (uart_id > MAX_UART_NUM)
+		return AK_FALSE;
+
+	baseAddress = uart_id2register(uart_id);
+
+	uart_wait_rx_timeout(uart_id);
+
+	reg_value = __raw_readl(baseAddress + 0x04);
+	reg_value |= (1UL << 2);	//clear the timeout bit
+	__raw_writel(reg_value, baseAddress + 0x04);
+
+	nbr_to_read = (__raw_readl(baseAddress + 0x08) >> 13) & 0x1f;	//0x20026008
+	//bit[17:13]:RX_adr 
+	timeout_count = (__raw_readl(baseAddress + 0x08) >> 23) & 0x3;
+	//bit[24:23]:byt_left
+
+	bufferAddress = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001000
+	//p_buffer = (T_U8*)(bufferAddress + (m_uart[uart_id].rxfifo_offset<<2));
+	p_buffer =
+	    (unsigned char *)(bufferAddress +
+			      (m_uart[uart_id].rxfifo_offset << 2));
+	*chr = *p_buffer;
+
+	//m_uart[uart_id].rxfifo_offset = (m_uart[uart_id].rxfifo_offset+1) % UART_RX_FIFO_SIZE;
+
+	//return AK_TRUE;
+	return *chr;
+}
+
+/**
+ * @brief Read a character from UART asynchronously.
+ * If no data, this function will also return directly.
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param T_UART_ID uart_id: UART ID
+ * @param T_U8 *chr: character for return
+ * @return T_BOOL: Got character or not
+ * @retval
+ */
+static unsigned int uart_read_fifo(unsigned char uart_id, unsigned char *chr,
+				   unsigned int count)
+{
+	unsigned char buf_id = 9 + (uart_id << 1);
+	//unsigned int reg_value;
+	unsigned int baseAddress;
+	volatile unsigned int nbr_to_read = 0, timeout_count = 0, read_cnt =
+	    0, tmp_cnt = 0;
+	unsigned int bufferAddress, rxfifo_offset = 0;
+	unsigned char *p_buffer;
+
+	/* the read count must be multiple of 4 */
+	if (count & 0x3) {
+		printk("the count must be multiple of 4 !!\n");
+		return 0;
+	}
+
+	/*
+	   read_cnt is byte(8bit) unit
+	   rxfifo_offset is lword(32bit) unit
+	   nbr_to_read is lword(32bit) unit
+	 */
+
+	baseAddress = uart_id2register(uart_id);
+
+	bufferAddress = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001080
+
+	nbr_to_read = (__raw_readl(baseAddress + 0x08) >> 13) & 0x1f;
+	//bit[17:13]:Rx_adr
+	//nbr_to_read is lword(32bit) unit
+
+	/* check fifo empty or not */
+	if (nbr_to_read != m_uart[uart_id].rxfifo_offset) {
+		/* we suppose to get timeout data at the end */
+
+		rxfifo_offset = m_uart[uart_id].rxfifo_offset;
+
+		/* check timeout status. if timeout, get timeout count */
+
+		//to see if reach the last lwond in fifo
+		if ((__raw_readl(baseAddress + 0x04) & (1UL << 2)) &&	//0x20026004 
+		    ((rxfifo_offset + 1) % UART_RX_FIFO_SIZE == nbr_to_read))
+			/*
+			   'if ( (rxfifo_offset+1)%UART_RX_FIFO_SIZE == nbr_to_read ) '
+			   means it is the last lword left in fifo,need clear timeout flag
+			 */
+		{
+			uart_clear_rx_timeout(uart_id);
+
+			timeout_count = (__raw_readl(baseAddress + 0x08) >> 23) & 0x3;	//0x20026008
+			//bit[24:23](0x20026008):byt_left:The number of data left when receiving timeout occurs
+			//timeout_count = 0 ~ 3 ;
+			//
+
+			read_cnt += timeout_count;
+			rxfifo_offset = (rxfifo_offset + 1) % UART_RX_FIFO_SIZE;
+
+		}
+		/* data is still left in fifo, count it */
+		if (nbr_to_read != rxfifo_offset) {
+			// read_cnt*=4; read_cnt is byte(8bit) unit
+			// rxfifo_offset is lword(32bit) unit
+			// nbr_to_read is lword(32bit) unit
+			if (nbr_to_read > rxfifo_offset) {
+				read_cnt += (nbr_to_read - rxfifo_offset) << 2;	//read_cnt*=4
+			} else {
+				read_cnt +=
+				    (UART_RX_FIFO_SIZE - rxfifo_offset) << 2;
+				read_cnt += nbr_to_read << 2;
+			}
+		}
+	}
+
+	if (read_cnt > 0) {
+		if (read_cnt > count)
+			read_cnt = count;
+
+		p_buffer =
+		    (unsigned char *)(bufferAddress +
+				      (m_uart[uart_id].rxfifo_offset << 2));
+
+		//UART_RX_FIFO_SIZE<<2 = 128
+		if ((read_cnt + (m_uart[uart_id].rxfifo_offset << 2)) <=
+		    (UART_RX_FIFO_SIZE << 2)) {
+			memcpy(chr, p_buffer, read_cnt);
+		} else {
+			tmp_cnt =
+			    (UART_RX_FIFO_SIZE -
+			     m_uart[uart_id].rxfifo_offset) << 2;
+			memcpy(chr, p_buffer, tmp_cnt);
+			p_buffer = (unsigned char *)bufferAddress;
+			memcpy(chr + tmp_cnt, p_buffer, read_cnt - tmp_cnt);
+		}
+
+		//L2_TranDataCPU((T_U32)chr, buf_id, m_uart[uart_id].rxfifo_offset<<2, 
+		//                          read_cnt, BUF2MEM);
+
+		if (read_cnt & 0x3) {
+			m_uart[uart_id].rxfifo_offset =
+			    (m_uart[uart_id].rxfifo_offset + read_cnt / 4 +
+			     1) % UART_RX_FIFO_SIZE;
+		} else {
+			m_uart[uart_id].rxfifo_offset =
+			    (m_uart[uart_id].rxfifo_offset +
+			     read_cnt / 4) % UART_RX_FIFO_SIZE;
+		}
+	}
+
+	//if (read_cnt || nbr_to_read || rxfifo_offset|| timeout_count)
+	//akprintf(C3, M_DRVSYS, "[%d,%d,%d,%d]", read_cnt, nbr_to_read, rxfifo_offset, timeout_count);
+	return read_cnt;
+}
+
+unsigned int uart_read_timeout(unsigned char uart_id, unsigned char *chr)
+/* when timeout occur ,read all the data in fifo from 0(0x48001080),return the real read number
+*/
+{
+	unsigned char buf_id = 9 + (uart_id << 1);
+	unsigned int base_address;
+	volatile unsigned int nbr_to_read = 0, timeout_count = 0, read_cnt = 0;
+	unsigned int buffer_address;
+	unsigned char *p_buffer;
+	volatile unsigned char timeout_flag = 0;
+
+	/*
+	   read_cnt is byte(8bit) unit
+	   rxfifo_offset is lword(32bit) unit
+	   nbr_to_read is lword(32bit) unit
+	 */
+
+	base_address = uart_id2register(uart_id);
+
+	buffer_address = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001080
+
+	timeout_flag = uart_get_rx_timeout(uart_id);
+	if (!timeout_flag)
+		return 0;
+
+	nbr_to_read = (__raw_readl(base_address + 0x08) >> 13) & 0x1f;
+	//bit[17:13]:Rx_adr
+	//nbr_to_read is lword(32bit) unit
+
+	timeout_count = (__raw_readl(base_address + 0x08) >> 23) & 0x3;	//0x20026008
+	//bit[24:23](0x20026008):byt_left:The number of data left when receiving timeout occurs
+	//timeout_count = 0 ~ 3 ;
+	//
+
+	if (nbr_to_read != 0)
+		read_cnt += (nbr_to_read - 0) << 2;	//read_cnt*=4
+
+	read_cnt += timeout_count;
+
+	if (read_cnt > 0) {
+
+		//pbuffer = (T_U8*)(bufferAddress + (m_uart[uart_id].rxfifo_offset<<2));
+		p_buffer = (unsigned char *)(buffer_address + 0);
+
+		memcpy(chr, p_buffer, read_cnt);
+
+	}
+
+	uart_clear_rx_timeout(uart_id);
+
+	return read_cnt;
+}
+
+unsigned int uart_read_buffull(unsigned char uart_id, unsigned char *chr)
+/* when RX_buf_full occur ,read all the data in fifo from 0(0x48001080),return the real read number
+*/
+{
+	unsigned char buf_id = 9 + (uart_id << 1);
+	unsigned int base_address;
+	//unsigned int nbr_to_read=0,timeout_count=0, read_cnt=0;
+	volatile unsigned int nbr_to_read = 0, read_cnt = 0;
+	unsigned int buffer_address;
+	unsigned char *p_buffer;
+	volatile unsigned char buffull_flag = 0;
+
+	/*
+	   read_cnt is byte(8bit) unit
+	   rxfifo_offset is lword(32bit) unit
+	   nbr_to_read is lword(32bit) unit
+	 */
+
+	base_address = uart_id2register(uart_id);
+
+	buffer_address = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001080
+
+	buffull_flag = uart_get_rx_buffull(uart_id);
+	if (!buffull_flag)
+		return 0;
+
+	nbr_to_read = (__raw_readl(base_address + 0x08) >> 13) & 0x1f;
+	//bit[17:13]:Rx_adr
+	//nbr_to_read is lword(32bit) unit
+
+	if (nbr_to_read != 0)
+		read_cnt += (nbr_to_read - 0) << 2;	//read_cnt*=4
+
+	if (read_cnt > 0) {
+
+		//pbuffer = (T_U8*)(bufferAddress + (m_uart[uart_id].rxfifo_offset<<2));
+		p_buffer = (unsigned char *)(buffer_address + 0);
+
+		memcpy(chr, p_buffer, read_cnt);
+
+	}
+
+	uart_clear_rx_buffull(uart_id);
+
+	return read_cnt;
+}
+
+void uart_set_datapool(unsigned char uart_id, unsigned char *pool,
+		       unsigned int poollength)
+{
+	unsigned int i = 0;
+
+	if (pool == AK_NULL || poollength == 0) {
+		//printk("pool can't be null\n");
+		return;
+	}
+	//m_uart[uart_id].pReceivePool = pool;
+	//m_uart[uart_id].nReceivePoolLength = poollength;
+	m_uart[uart_id].p_receive_pool = pool;
+	m_uart[uart_id].n_receive_pool_length = poollength;
+
+	while (1) {
+		if ((m_uart[uart_id].
+		     n_receive_pool_length & (0x80000000 >> i)) != 0) {
+			m_uart[uart_id].n_receive_pool_length =
+			    m_uart[uart_id].
+			    n_receive_pool_length & (0x80000000 >> i);
+			break;
+		}
+
+		i++;
+	}
+}
+
+/**
+ * @brief Register a callback function to process UART received data.
+ * This function words only in the UART interrupt mode.
+ * Caution: The macro definition "__ENABLE_UARTxx_INT__" must be defined. 
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param T_UART_ID uart_id: UART ID
+ * @param T_fUART_CALLBACK callback_func: Callback function
+ * @return T_VOID
+ * @retval
+ */
+void uart_set_callback(unsigned char uart_id, t_fuart_callback callback_func)
+{
+	unsigned int baseAddress;
+	volatile unsigned int value;
+
+	//akprintf(C3, M_DRVSYS, "+++++++++++uart_set_callback %d++++++++++++++++++\n", uart_id);
+
+	baseAddress = uart_id2register(uart_id);	//0x20026000
+
+	/* disable uart interrupt callback */
+	if (callback_func == AK_NULL) {
+		m_uart[uart_id].b_interrupt = AK_FALSE;
+		m_uart[uart_id].rxfifo_offset = 0;
+		__raw_writel(0, baseAddress + 0x04);	//mask all interrupt //0x20026004
+		uart_clear_rx_status(uart_id);
+		l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+		return;
+	}
+
+	m_uart[uart_id].callback_func = callback_func;
+	m_uart[uart_id].b_interrupt = AK_TRUE;
+
+	/* set threshold to 4bytes */
+	value = __raw_readl(baseAddress + 0x0c);	//0x2002600c
+
+	value &= ~0x1f;
+#ifdef CHIP_780X
+	if (uiUART2 == uart_id)
+		value |= 0xf;	// (cfg+1)*4
+	else
+#endif
+		value |= 0x0;
+	__raw_writel(value, baseAddress + 0x0c);
+
+	uart_clear_rx_status(uart_id);
+	l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+
+	/* clear count */
+	value = __raw_readl(baseAddress + 0x0c);	//0x2002600c
+	//bit5(0x2002600c):Rx_th_clr:1=to clear Rx_th interrupt,and prevent the threshold counting
+	//                 Note:Please refer to bit[28] of UART_CFG_REG2(n)(0x20026004) for the definition of RX_th interrupt
+	value |= (1UL << 5);
+	__raw_writel(value, baseAddress + 0x0c);
+	value &= ~(1UL << 5);
+	__raw_writel(value, baseAddress + 0x0c);
+
+	/* enable timeout, r_err, rx buffer full and rx_th interrupt */
+	value = __raw_readl(baseAddress + 0x04);
+	value |= (1UL << 22) | (1UL << 23) | (1UL << 26) | (1UL << 28);
+	//0x20026004
+	//bit[22]:timeout_int:1=to enable timeout interrupt
+	//        Note:Please refer to bit[23] of UART_CFG_REG1(n)(0x20026000) for the definition of timeout function
+	//bit[23]:R_err_int:1=to enable R_err interrupt
+	//        Note:When an error occurs in the received data,an interrupt is generated ,
+	//        this kind of interrupt is called R_err interrupt               
+	//bit[26]:RX_buf_full_int:1=to enable RX_buf_full interrupt
+	//bit[28]:RX_th_int:1=to enable RX_th interrupt
+	//        Note:1.Programmers may set a threshold of the receive buffer.When the number of received data
+	//        is equal to the threshold value,an interrupt is generated.This kind of interrupt is called 
+	//        RX_th interrupt
+	//        2.The receive buffer threshold value is set by bits[4:0] of UART_THREHOLD(n)(0x2002600c)
+
+	__raw_writel(value, baseAddress + 0x04);
+
+	return;
+}
+
+void uart_close_interrupt(unsigned char uart_id)
+{
+	unsigned int base_address;
+	//volatile unsigned int  value;
+
+	base_address = uart_id2register(uart_id);	//0x20026000
+
+	__raw_writel(0, base_address + 0x04);	//mask all interrupt //0x20026004
+	uart_clear_rx_status(uart_id);
+	uart_clear_rx_th(uart_id);
+	l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+
+	uart_clear_tx_status(uart_id);
+	uart_clear_rx_status(uart_id);
+	uart_clear_rx_timeout(uart_id);
+	uart_clear_rx_buffull(uart_id);
+	__raw_writel(0, base_address + 0x04);	//mask all interrupt //0x20026004
+
+	printk("dbg:end:uart_close_interrupt(%d)\n", uart_id);
+	return;
+}
+
+void uart_open_interrupt(unsigned char uart_id)
+{
+	unsigned int base_address;
+	volatile unsigned int value;
+
+	printk("uart_open_interrupt(),uart_id=%d\n",uart_id);
+
+	base_address = uart_id2register(uart_id);	//0x20026000
+
+	value = __raw_readl(AK88_VA_SYS + 0x78);
+	if (uart_id == 0)
+		value |= (1UL << 9);
+	else if (uart_id == 3)
+		value |= (1UL << 14);
+	__raw_writel(value, (AK88_VA_SYS + 0x78));	//share pin
+
+	value = __raw_readl(AK88_VA_DEV + 0xc084);
+	value |= (3UL << 28);
+	__raw_writel(value, (AK88_VA_DEV + 0xc084));	//dma pin
+
+	__raw_writel(0, base_address + 0x04);	//mask all interrupt //0x20026004
+
+	uart_clear_rx_status(uart_id);
+	uart_clear_rx_th(uart_id);
+	l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+
+	__raw_writel(0, base_address + 0x04);	//mask all interrupt //0x20026004
+
+#if 0
+	/* disable uart interrupt callback */
+	if (callback_func == AK_NULL) {
+		m_uart[uart_id].b_interrupt = AK_FALSE;
+		m_uart[uart_id].rxfifo_offset = 0;
+		__raw_writel(0, baseAddress + 0x04);	//mask all interrupt //0x20026004
+		uart_clear_rx_status(uart_id);
+		l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+		return;
+	}
+#endif
+
+	//m_uart[uart_id].callback_func = callback_func;
+	//m_uart[uart_id].b_interrupt  = AK_TRUE;
+
+	/* set threshold to 4bytes */
+	value = __raw_readl(base_address + 0x0c);	//0x2002600c
+
+	value &= ~0x1f;
+#ifdef CHIP_780X
+	if (uiUART2 == uart_id)
+		value |= 0xf;	// (cfg+1)*4
+	else
+#endif
+		value |= 0x0;
+	__raw_writel(value, base_address + 0x0c);
+
+	value = __raw_readl(AK88_UART_CFG_REG1(uart_id));
+	//value |= ((1UL<<23)|(1UL<<21));   //timeout_en,EN
+	value |= 1UL << 21;	//uart interface EN
+
+	__raw_writel(0, (AK88_UART_THREHOLD(uart_id)));
+
+	//uart_clear_rx_status(uart_id);
+	//uart_clear_rx_timeout(uart_id);
+	uart_clear_rx_buffull(uart_id);
+	l2_clr_uartbuf_status((unsigned char)uart_id * 2 + 9);
+
+	uart_clear_rx_th(uart_id);
+#if 0
+	///* clear interrupt count */
+	value = __raw_readl(base_address + 0x0c);	//0x2002600c
+	//bit5(0x2002600c):Rx_th_clr:1=to clear Rx_th interrupt,and prevent the threshold counting
+	//                 Note:Please refer to bit[28] of UART_CFG_REG2(n)(0x20026004) for the definition of RX_th interrupt
+	value |= (1 << 5);
+	__raw_writel(value, base_address + 0x0c);
+	value &= ~(1 << 5);
+	__raw_writel(value, base_address + 0x0c);
+#endif
+
+	__raw_writel(0, (AK88_UART_THREHOLD(uart_id)));	//threshold count=1;
+
+	/* enable timeout, r_err, rx buffer full and rx_th interrupt */
+	value = __raw_readl(base_address + 0x04);
+	//value |= (1UL<<22)|(1UL<<23)|(1UL<<26)|(1UL<<28);  //timeout_int|R_err_int|RX_buf_full_int|RX_th_int
+	value |= 1UL << 28;	//RX_th_int 
+	//value |=1UL<<22;
+	//value |= 1UL<<27;
+	//0x20026004
+	//bit[22]:timeout_int:1=to enable timeout interrupt
+	//        Note:Please refer to bit[23] of UART_CFG_REG1(n)(0x20026000) for the definition of timeout function
+	//bit[23]:R_err_int:1=to enable R_err interrupt
+	//        Note:When an error occurs in the received data,an interrupt is generated ,
+	//        this kind of interrupt is called R_err interrupt               
+	//bit[26]:RX_buf_full_int:1=to enable RX_buf_full interrupt
+	//bit[28]:RX_th_int:1=to enable RX_th interrupt
+	//        Note:1.Programmers may set a threshold of the receive buffer.When the number of received data
+	//        is equal to the threshold value,an interrupt is generated.This kind of interrupt is called 
+	//        RX_th interrupt
+	//        2.The receive buffer threshold value is set by bits[4:0] of UART_THREHOLD(n)(0x2002600c)
+
+	__raw_writel(value, base_address + 0x04);
+
+	uart_reen_rx_th(uart_id);
+
+	printk("dbg:end:uart_open_interrupt(%d)\n", uart_id);
+	return;
+}
+
+static void uart_storedata(unsigned char uart_id, unsigned char *data,
+			   unsigned int datalen)
+{
+	if (m_uart[uart_id].p_receive_pool != AK_NULL) {
+		if (m_uart[uart_id].n_receive_pool_tail + datalen >
+		    m_uart[uart_id].n_receive_pool_length) {
+			unsigned int cpylen =
+			    m_uart[uart_id].n_receive_pool_length -
+			    m_uart[uart_id].n_receive_pool_tail;
+
+			memcpy(&m_uart[uart_id].
+			       p_receive_pool[m_uart[uart_id].
+					      n_receive_pool_tail], data,
+			       cpylen);
+			memcpy(&m_uart[uart_id].p_receive_pool[0],
+			       data + cpylen, datalen - cpylen);
+			m_uart[uart_id].n_receive_pool_tail = datalen - cpylen;
+		} else {
+			memcpy(&m_uart[uart_id].
+			       p_receive_pool[m_uart[uart_id].
+					      n_receive_pool_tail], data,
+			       datalen);
+		}
+
+		m_uart[uart_id].n_receive_pool_tail &=
+		    (m_uart[uart_id].n_receive_pool_length - 1);
+	}
+}
+
+void uart_timeout_handler(unsigned char uart_id)
+{
+
+	unsigned char buf_id = 9 + (uart_id << 1);
+	volatile unsigned int rxcount = 0, nbr_to_read, timeout_count = 0;
+	unsigned int baseAddress, status;
+	unsigned int bufferAddress;
+	unsigned char *p_buffer;
+	//unsigned int i,value;
+	volatile unsigned int value;
+	//unsigned int delay_clk;
+
+	if (m_uart[uart_id].b_open == AK_FALSE)
+		return;
+
+	if (m_uart[uart_id].b_interrupt == AK_FALSE)
+		return;
+
+	bufferAddress = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001000
+	baseAddress = uart_id2register(uart_id);
+
+	value = __raw_readl(baseAddress + 0x00);	//0x20026000,enable timeout function
+	value |= (1UL << 23);
+	__raw_writel(value, baseAddress + 0x00);
+	//us_delay(m_uart[ uart_id ].timeout_delay_us);
+	value = __raw_readl(baseAddress + 0x00);	//0x20026000, disable timeout function
+	value &= ~(1UL << 23);
+	__raw_writel(value, baseAddress + 0x00);
+
+	status = __raw_readl(baseAddress + 0x04);
+	if (status & (1UL << 2)) {
+		uart_clear_rx_timeout(uart_id);
+		value = __raw_readl(baseAddress + 0x08);	//0x20026008
+		//timeout_count = (value>>23)&0x03;
+		//0x200260i08
+		//bit[24:23]:byt_left: the number of data left when receiving timeout occurs
+		//      Note:Please refer to bit[23] of UART_CFG_REG(n)(0x20026000) for the 
+		//           definition of timeout function
+		timeout_count = (value >> 23) & 0x03;
+		//if (uart_id == uiUART2)     
+		//  printk("<%d>", timeout_count);
+	} else
+		return;
+
+	nbr_to_read = (__raw_readl(baseAddress + 0x08) >> 13) & 0x1f;	//0x20026008
+	//bit[17:13](0x20026008):RX_adr
+
+	//printk("<%d>", nbr_to_read);   
+
+	p_buffer =
+	    (unsigned char *)(bufferAddress +
+			      (m_uart[uart_id].rxfifo_offset << 2));
+
+	//REG32(L2_FRAC_ADDR) |= (1<<29); //enable ahb effect
+	if (nbr_to_read > m_uart[uart_id].rxfifo_offset) {
+		rxcount = (nbr_to_read - m_uart[uart_id].rxfifo_offset) << 2;
+		if (timeout_count)
+			rxcount = rxcount - 4 + timeout_count;
+		//uart_storedata(uart_id, pbuffer, rxcount);
+		uart_storedata(uart_id, p_buffer, rxcount);
+	} else {
+		rxcount =
+		    (UART_RX_FIFO_SIZE - m_uart[uart_id].rxfifo_offset) << 2;
+		if (timeout_count && nbr_to_read == 0)
+			rxcount = rxcount - 4 + timeout_count;
+		uart_storedata(uart_id, p_buffer, rxcount);
+		if (nbr_to_read > 0) {
+			p_buffer = (unsigned char *)bufferAddress;
+			rxcount = (nbr_to_read) << 2;
+			if (timeout_count)
+				rxcount = rxcount - 4 + timeout_count;
+			uart_storedata(uart_id, p_buffer, rxcount);
+		}
+	}
+	//REG32(L2_FRAC_ADDR) &= ~(1<<29); //disable ahb effect
+
+	m_uart[uart_id].rxfifo_offset = nbr_to_read % UART_RX_FIFO_SIZE;
+
+	if (m_uart[uart_id].b_interrupt == AK_TRUE) {
+		if (rxcount != 0) {
+			if (m_uart[uart_id].callback_func != AK_NULL)
+				m_uart[uart_id].callback_func();
+		}
+	}
+}
+
+unsigned int uart_get_int_status(unsigned char uart_id, unsigned test_status)
+{
+	volatile unsigned int base_address, status;
+
+	base_address = uart_id2register(uart_id);	//0x20026000
+
+	status = __raw_readl(base_address + 0x04);
+	switch (test_status) {
+	case UART_RX_buf_full:
+		return (status & (1UL << 1));
+		break;
+	case UART_INT_timeout:
+		return (status & (1UL << 2));
+		break;
+	case UART_R_err:
+		return (status & (1UL << 3));
+		break;
+	case UART_RX_ov:
+		return (status & (1UL << 18));
+		break;
+	case UART_TX_end:
+		return (status & (1UL << 19));
+		break;
+	case UART_Rx_th_int_sta:
+		return (status & (1UL << 30));
+		break;
+	case UART_Tx_th_int_sta:
+		return (status & (1UL << 31));
+		break;
+	default:
+		break;
+	}
+
+	return status;
+}
+
+/**
+ * @brief UART interrupt handler
+ * If chip detect that UART0 received data, this function will be called.
+ * This function will get UART data from UART Receive Data Hold Register, and call
+ * UART callback function to process the data if it is available.
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-16
+ * @param T_VOID
+ * @return T_VOID
+ * @retval
+ */
+//static T_VOID uart_handler(T_UART_ID uart_id)
+static void uart_handler(unsigned char uart_id)
+{
+	unsigned char buf_id = 9 + (uart_id << 1);
+	volatile unsigned int rxcount = 0, nbr_to_read, timeout_count = 0;
+	volatile unsigned int baseAddress;
+	volatile unsigned int bufferAddress, value, i;
+	unsigned char *p_buffer;
+
+	bufferAddress = (unsigned int)AK88_VA_L2BUF + 4096 /*8 * 512 */  + ((buf_id - 8) << 7);	//0x48001000
+
+	baseAddress = uart_id2register(uart_id);	//0x20026000
+
+#if 0
+	status = __raw_readl(baseAddress + 0x04);
+	if (status & (1 << 3)) {
+		//putch('#');
+		reg = __raw_readl(baseAddress + 0x04);
+		reg &= 0x3fe00000;
+		reg |= (1 << 3);	//clear R_err
+		__raw_writel(reg, baseAddress + 0x04);
+	}
+#endif
+	uart_clear_rx_err(uart_id);
+
+#if 0
+	//rx threshold interrupt
+	if (status & (1 << 30)) {
+
+		//clear rx th status
+		value = __raw_readl(baseAddress + 0x04);
+		value |= (1 << 30);
+		__raw_writel(value, baseAddress + 0x04);
+		//uart_clear_rx_int();
+	}
+#endif
+	uart_clear_rx_th(uart_id);
+
+	nbr_to_read = (__raw_readl(baseAddress + 0x08) >> 13) & 0x1f;
+
+	//timeout interrupt
+#if 0
+	if (status & (1 << 2)) {
+		timeout_count = uart_clear_rx_timeout(uart_id);
+
+		timeout_count = (__raw_readl(baseAddress + 0x08) >> 23) & 0x3;
+		//printk("<%d>", timeout_count);
+	}
+#endif
+	timeout_count = uart_clear_rx_timeout(uart_id);
+
+	p_buffer =
+	    (unsigned char *)(bufferAddress +
+			      (m_uart[uart_id].rxfifo_offset << 2));
+
+	if (nbr_to_read > m_uart[uart_id].rxfifo_offset) {
+		rxcount = (nbr_to_read - m_uart[uart_id].rxfifo_offset) << 2;
+		if (timeout_count)
+			rxcount = rxcount - 4 + timeout_count;
+		uart_storedata(uart_id, p_buffer, rxcount);
+	} else {
+		rxcount =
+		    (UART_RX_FIFO_SIZE - m_uart[uart_id].rxfifo_offset) << 2;
+		if (timeout_count && nbr_to_read == 0)
+			rxcount = rxcount - 4 + timeout_count;
+		for (i = 0; i < (rxcount >> 2); i++) {
+			value = *(unsigned int *)(p_buffer + (i << 2));
+			uart_storedata(uart_id, (unsigned char *)&value, 4);
+		}
+		if (nbr_to_read > 0) {
+			p_buffer = (unsigned char *)bufferAddress;
+			rxcount = (nbr_to_read) << 2;
+			if (timeout_count)
+				rxcount = rxcount - 4 + timeout_count;
+			uart_storedata(uart_id, p_buffer, rxcount);
+			/*for (i=0; i<(rxcount>>2); i++)
+			   {
+			   value = *(T_U32*)(pbuffer + (i<<2));
+			   uart_storedata(uart_id, (T_U8*)&value, 4);    
+			   } */
+		}
+	}
+
+	//if (uiUART0 != uart_id)
+	//akprintf(C3, M_DRVSYS, "[%d, %d, %d, %d]", m_uart[uart_id].rxfifo_offset, nbr_to_read, timeout_count, rxcount);
+
+	m_uart[uart_id].rxfifo_offset = nbr_to_read % UART_RX_FIFO_SIZE;
+
+	if (rxcount != 0) {
+		if (m_uart[uart_id].callback_func != AK_NULL)
+			m_uart[uart_id].callback_func();
+	}
+
+	return;
+}
+
+unsigned char uart0_interrupt_handler(void)
+{
+	uart_handler(uiUART0);
+	return AK_TRUE;
+}
+
+#ifdef CHIP_780X
+unsigned char uart1_interrupt_handler(void)
+{
+	uart_handler(uiUART1);
+	return AK_TRUE;
+}
+
+static unsigned char uart2_interrupt_handler(void)
+{
+	uart_handler(uiUART2);
+	return AK_TRUE;
+}
+#endif
+
+#if 0
+static unsigned char uart3_interrupt_handler(void)
+{
+	uart_handler(uiUART3);
+	return AK_TRUE;
+}
+#endif
+
+/**
+ * @brief Close UART
+ * Function uart_init() must be called before call this function
+ * @author Junhua Zhao
+ * @date 2005-05-18
+ * @param T_UART_ID uart_id: UART ID
+ * @return T_VOID
+ * @retval
+ */
+void uart_free(unsigned char uart_id)
+{
+	unsigned int baseAddress;
+
+	baseAddress = uart_id2register(uart_id);
+
+	/* disable uart interrupt */
+	__raw_writel(0, baseAddress + 0x04);	//mask all interrupt
+
+	m_uart[uart_id].b_open = AK_FALSE;
+
+	uart_clock_ctl(uart_id, AK_FALSE);
+
+}
+
+unsigned char uart_isrxfifoempty(unsigned char uart_id)
+{
+	return AK_TRUE;
+}
+
+unsigned char uart_istxfifoempty(unsigned char uart_id)
+{
+	return AK_TRUE;
+}
+
+unsigned char uart_setflowcontrol(unsigned char uart_id, unsigned char enable)
+{
+	unsigned int baseAddress = 0;
+	volatile unsigned int value;
+
+	if (uart_id == uiUART0)
+		return AK_FALSE;
+
+	baseAddress = uart_id2register(uart_id);
+
+	if (AK_TRUE == enable) {
+		value = __raw_readl(baseAddress + 0x00);
+		//0x20026000
+		//bit[19]:RTS_sel:( RTS:Request to Send (DCE -> DTE)
+		//                0=to output the RTS signal directly
+		//                1=to output the RTS signal inversely.
+		//
+		//bit[18]:CTS_sel:(CTS:Clear to Send (DCE -> DTE)
+		//
+		//bit[17]:URD_sel:(URD: URDx pin, UART Receive pin,UART receive serial data via the URDx pin)
+		//bit[16]:UTD_sel:(UTD: UTDx pin, UART Transmit pin,UART transmit serial data via the UTDx pin)
+		//
+		//
+		value |= (1UL << 19) | (1UL << 18);
+		__raw_writel(value, baseAddress + 0x00);
+	} else {
+		//REG32(baseAddress+UART_CFG_REG1) &= ~(1<<19);
+		//REG32(baseAddress+UART_CFG_REG1) &= ~(1<<18);
+		value = __raw_readl(baseAddress + 0x00);
+		value &= ~(1UL << 19);
+		value &= ~(1UL << 18);
+		__raw_writel(value, baseAddress + 0x00);
+	}
+
+	return AK_TRUE;
+}
+
+#if 0
+static int uart_timer_id = -1;
+
+static void timer_uart_cb(int timer_id, unsigned int delay)
+{
+	if (uart_timer_id == timer_id) {
+		//uart_timeout_handler(uiUART0);
+#ifdef CHIP_780X
+		uart_timeout_handler(uiUART1);
+		uart_timeout_handler(uiUART2);
+#endif
+		uart_timeout_handler(uiUART3);
+	}
+}
+#endif
+
+void uart_set_baudrate(unsigned char uart_id, unsigned int baud_rate,
+		       unsigned int sys_clk)
+{
+	volatile unsigned int br_value;
+	volatile unsigned int reg_value;
+	unsigned int baseAddress;
+
+	if (uart_id > MAX_UART_NUM)
+		return;
+
+	baseAddress = uart_id2register(uart_id);
+
+	reg_value = __raw_readl(baseAddress + 0x00);
+	reg_value &= 0xffff0000;
+
+	/* set baudrate */
+	br_value = sys_clk / baud_rate - 1;
+	reg_value |= (br_value & 0xffff);
+
+	if (sys_clk % baud_rate)
+		reg_value |= (1UL << 22);
+
+	__raw_writel(reg_value, baseAddress + 0x00);
+
+}
diff --git a/arch/arm/mach-ak88/pm.c b/arch/arm/mach-ak88/pm.c
new file mode 100644
index 00000000000..c0d194eb970
--- /dev/null
+++ b/arch/arm/mach-ak88/pm.c
@@ -0,0 +1,233 @@
+/* linux/arch/arm/mach-ak7801/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/crc32.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/mach/time.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/ak7801_addr.h>
+#include <asm/arch/pm.h>
+
+const unsigned char suspend_code[] = {
+	0xb4, 0x10, 0x9f, 0xe5, 0xb4, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0,
+	    0xa0, 0xe1,
+	0, 0, 0xa0, 0xe1, 0xa8, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0, 0xa0,
+	    0xe1,
+	0, 0, 0xa0, 0xe1, 0x94, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0, 0xa0,
+	    0xe1,
+	0, 0, 0xa0, 0xe1, 0x8c, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0, 0xa0,
+	    0xe1,
+	0, 0, 0xa0, 0xe1, 0, 0, 0xa0, 0xe1, 0, 0, 0xa0, 0xe1, 0x78, 0, 0x9f,
+	    0xe5,
+	0, 0x10, 0x90, 0xe5, 0x40, 0x1b, 0x81, 0xe3, 0x80, 0x1d, 0x81, 0xe3, 0,
+	    0x10, 0x80, 0xe5,
+	0, 0, 0xa0, 0xe3, 0x1, 0, 0x80, 0xe2, 0x80, 0x7, 0x50, 0xe3, 0xfc, 0xff,
+	    0xff, 0x1a,
+	0x44, 0x10, 0x9f, 0xe5, 0x44, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0,
+	    0xa0, 0xe1,
+	0, 0, 0xa0, 0xe1, 0x44, 0, 0x9f, 0xe5, 0, 0, 0x81, 0xe5, 0, 0, 0xa0,
+	    0xe1,
+	0, 0, 0xa0, 0xe1, 0, 0, 0xa0, 0xe1, 0, 0, 0xa0, 0xe1, 0, 0x10, 0xa0,
+	    0xe3,
+	0x17, 0x1f, 0x8, 0xee, 0x17, 0x1f, 0x7, 0xee, 0x48, 0x14, 0xa0, 0xe3,
+	    0xf0, 0x20, 0x91, 0xe5,
+	0x2, 0xf0, 0xa0, 0xe1, 0, 0, 0xa0, 0xe1, 0xfe, 0xff, 0xff, 0xea, 0,
+	    0xd0, 0x2, 0x20,
+	0, 0, 0x17, 0xc0, 0, 0x4, 0x12, 0xc0, 0, 0, 0x11, 0x80, 0x4, 0, 0, 0x8,
+	0, 0, 0x11, 0xe0, 0xe0,
+};
+
+extern void ak7801_cpu_sleep(void);
+extern unsigned long cdma_sleep;
+
+#if 0
+static ak7801_pm_debug_init(void)
+{
+}
+#else
+#define ak7801_pm_debug_init() do { } while(0)
+#endif
+
+static void turn_kpd_led(int on)
+{
+	ak7801_gpio_cfgpin(AK7801_DGPIO_36, AK7801_GPIO_OUT);
+	ak7801_gpio_pullup(AK7801_DGPIO_36, 1);
+
+	if (on == 1)
+		ak7801_gpio_setpin(AK7801_DGPIO_36, 1);
+	else
+		ak7801_gpio_setpin(AK7801_DGPIO_36, 0);
+}
+
+static void ak7801_set_wgpio(unsigned int wgpio_mask)
+{
+	unsigned long wgpio;
+
+	wgpio = __raw_readl(AK7801_VA_SYSCTRL + 0x40);
+	__raw_writel(wgpio | wgpio_mask, AK7801_VA_SYSCTRL + 0x40);
+
+	wgpio = __raw_readl(AK7801_VA_SYSCTRL + 0x40);
+	__raw_writel(wgpio & ~wgpio_mask, AK7801_VA_SYSCTRL + 0x40);
+
+	wgpio = __raw_readl(AK7801_VA_SYSCTRL + 0x44);
+	__raw_writel(wgpio | wgpio_mask, AK7801_VA_SYSCTRL + 0x44);
+}
+
+static int ak7801_pm_enter(suspend_state_t state)
+{
+	unsigned long regs_save[16];
+	unsigned long wgpio_status;
+	unsigned long sharepin_cfg1;
+	unsigned long tmp;
+
+	int offset = 0;
+	int i = 0;
+
+	/* turn off backlight */
+	turn_kpd_led(0);
+
+	/* store the physical address of the register recovery block */
+	ak7801_sleep_save_phys = virt_to_phys(regs_save);
+
+	/* ensure the debug is initialised (if enabled) */
+	ak7801_pm_debug_init();
+
+	flush_cache_all();
+
+	AK7801_GPIO_UART1_FLOW(0);
+	ak7801_gpio_pullup(AK7801_GPIO_18, 1);
+	ak7801_gpio_setpin(AK7801_GPIO_18, 1);
+	ak7801_gpio_cfgpin(AK7801_GPIO_18, AK7801_GPIO_OUT);
+	rIO_CON1 &= ~(1 << 17);
+
+	AK7801_GPIO_UART3_FLOW(0);
+	ak7801_gpio_pullup(AK7801_GPIO_26, 1);
+	ak7801_gpio_setpin(AK7801_GPIO_26, 1);
+	ak7801_gpio_cfgpin(AK7801_GPIO_26, AK7801_GPIO_OUT);
+
+	if (cdma_sleep == 0) {
+		ak7801_gpio_cfgpin(AK7801_GPIO_28, AK7801_GPIO_OUT);
+		ak7801_gpio_setpin(AK7801_GPIO_28, 0);
+		ak7801_gpio_pullup(AK7801_GPIO_28, 0);
+		ak7801_gpio_cfgpin(AK7801_GPIO_29, AK7801_GPIO_OUT);
+		ak7801_gpio_setpin(AK7801_GPIO_29, 0);
+		ak7801_gpio_pullup(AK7801_GPIO_29, 0);
+		ak7801_gpio_cfgpin(AK7801_GPIO_11, AK7801_GPIO_IN);
+		ak7801_gpio_pullup(AK7801_GPIO_11, 0);
+		ak7801_gpio_cfgpin(AK7801_GPIO_27, AK7801_GPIO_IN);
+		ak7801_gpio_pullup(AK7801_GPIO_27, 0);
+		ak7801_gpio_cfgpin(AK7801_GPIO_26, AK7801_GPIO_IN);
+		ak7801_gpio_pullup(AK7801_GPIO_26, 0);
+		rIO_CON1 |= (0x1 << 25 | 0x1 << 24);
+	} else
+		rIO_CON1 &= ~(1 << 25 | 1 << 24);
+
+	ak7801_set_wgpio(1 << 1 | 1 << 5 | 1 << 4 | 1 << 21);
+
+	tmp = __raw_readl(AK7801_VA_SYSCTRL + 0x3C);
+	tmp |= 1 << 1;
+	if (ak7801_gpio_getpin(AK7801_GPIO_11))
+		tmp |= 1 << 4;
+	else
+		tmp &= ~(1 << 4);
+	if (ak7801_gpio_getpin(AK7801_GPIO_12))
+		tmp |= 1 << 5;
+	else
+		tmp &= ~(1 << 5);
+	__raw_writel(tmp, AK7801_VA_SYSCTRL + 0x3C);
+
+	tmp = __raw_readl(AK7801_VA_SYSCTRL + 0xF0);
+	__raw_writel(tmp | 1 << 6, AK7801_VA_SYSCTRL + 0xF0);
+	tmp = __raw_readl(AK7801_VA_SYSCTRL + 0xE0);
+	__raw_writel(tmp | 1 << 6, AK7801_VA_SYSCTRL + 0xE0);
+
+	/* configure gpio for power save */
+	sharepin_cfg1 = __raw_readl(AK7801_SHAREPIN_CON1);
+	__raw_writel(1 << 30, AK7801_SHAREPIN_CON1);
+
+	rL2_FRACDMAADDR &= ~(1 << 29);
+
+	for (i = 0; i < sizeof(suspend_code) / sizeof(char); i += 4) {
+		__raw_writel(suspend_code[i] | (suspend_code[i + 1] << 8) |
+			     (suspend_code[i + 2] << 16) | (suspend_code[i + 3]
+							    << 24),
+			     AK7801_VA_L2MEM + i);
+	}
+
+	__raw_writel(virt_to_phys(ak7801_cpu_resume), AK7801_VA_L2MEM + 0xF0);
+
+	if (ak7801_cpu_save(regs_save) == 0) {
+		flush_cache_all();
+		ak7801_cpu_sleep();
+	}
+
+	cpu_init();
+
+	rL2_FRACDMAADDR |= (1 << 29);
+
+	ak7801_pm_debug_init();
+
+	__raw_writel(sharepin_cfg1, AK7801_SHAREPIN_CON1);
+
+	/* check which irq wakeup system */
+	/* 1. read wakeup GPIO status register, and go to wakeup sub-program */
+	wgpio_status = __raw_readl(AK7801_VA_SYSCTRL + 0x48);
+
+	while (wgpio_status) {
+		offset = __ffs(wgpio_status);
+		wgpio_status &= ~(1 << offset);
+	}
+
+	return 0;
+}
+
+static struct platform_suspend_ops ak7801_pm_ops = {
+	.valid = suspend_valid_only_mem,
+	.begin = NULL,
+	.prepare = NULL,
+	.enter = ak7801_pm_enter,
+	.finish = NULL,
+	.end = NULL,
+};
+
+/* ak7801_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+
+int __init ak7801_pm_init(void)
+{
+	printk("AK88 Power Management, (c) 2010 ANYKA\n");
+	suspend_set_ops(&ak7801_pm_ops);
+
+
+	return 0;
+}
diff --git a/arch/arm/mach-ak88/pwm.c b/arch/arm/mach-ak88/pwm.c
new file mode 100644
index 00000000000..7d4588ea5b6
--- /dev/null
+++ b/arch/arm/mach-ak88/pwm.c
@@ -0,0 +1,90 @@
+/* 
+ * AK88 PWM controler driver 
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/gpio.h>
+#include <mach/pwm.h>
+
+struct ak880x_pwm ak880x_pwm0 = {
+	.id = 0,
+	.gpio = AK88_GPIO_9,
+	.pwm_ctrl = AK88_PWM0_CTRL,
+};
+
+struct ak880x_pwm ak880x_pwm1 = {
+	.id = 1,
+	.gpio = AK88_GPIO_10,
+	.pwm_ctrl = AK88_PWM1_CTRL,
+};
+
+struct ak880x_pwm ak880x_pwm2 = {
+	.id = 2,
+	.gpio = AK88_GPIO_11,
+	.pwm_ctrl = AK88_PWM2_CTRL,
+};
+
+struct ak880x_pwm ak880x_pwm3 = {
+	.id = 3,
+	.gpio = AK88_GPIO_12,
+	.pwm_ctrl = AK88_PWM3_CTRL,
+};
+
+unsigned int ak880x_pwm_init(struct ak880x_pwm *pwm)
+{
+	__raw_writel(0xFFFF0000, pwm->pwm_ctrl);
+
+	/* init gpio for pwm */
+	ak880x_sharepin_cfg1(1, pwm->id + 4);
+
+	/* disable pullup */
+	ak880x_gpio_pullup(pwm->gpio, 1);
+
+	return 0;
+}
+
+EXPORT_SYMBOL(ak880x_pwm_init);
+
+unsigned int ak880x_pwm_set_duty_cycle(struct ak880x_pwm *pwm)
+{
+	__raw_writel(pwm->high << 16 | pwm->low, pwm->pwm_ctrl);
+	return 0;
+}
+
+EXPORT_SYMBOL(ak880x_pwm_set_duty_cycle);
+
+unsigned int ak880x_pwm_get_duty_cycle(struct ak880x_pwm *pwm)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(pwm->pwm_ctrl);
+
+	pwm->high = regval >> 16;
+	pwm->low = regval & 0xFFFF;
+
+	return 0;
+}
+
+EXPORT_SYMBOL(ak880x_pwm_get_duty_cycle);
+
+unsigned int ak880x_pwm_deinit(struct ak880x_pwm *pwm)
+{
+	/* deinit gpio for pwm */
+	ak880x_sharepin_cfg1(0, pwm->id + 4);
+
+	/* FIXME: enable pullup */
+	ak880x_gpio_pullup(pwm->gpio, 0);
+
+	return 0;
+}
+
+EXPORT_SYMBOL(ak880x_pwm_deinit);
diff --git a/arch/arm/mach-ak88/sleep.S b/arch/arm/mach-ak88/sleep.S
new file mode 100644
index 00000000000..a6ea2c79ce9
--- /dev/null
+++ b/arch/arm/mach-ak88/sleep.S
@@ -0,0 +1,96 @@
+/*
+ * linux/arch/arm/mach-ak7801/sleep.S 
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/hardware.h>
+#include <asm/arch/map.h>
+
+@@	Turn On kpd led with mmu on (TA801 DGPIO36)
+@	ldr	r0, =(AK7801_VA_SYSCTRL+0x98)
+@	ldr	r1, [r0]
+@	orr	r1, r1, #(1<<5)
+@	str	r1, [r0]
+@@
+
+@@	Turn On kpd led with mmu off
+@	mov	r0, #0x08000000
+@	ldr	r1, [r0, #0x98]
+@	orr	r1, r1, #(1<<5)
+@	str	r1, [r0, #0x98]
+
+
+	/* Put AK7801 into stanby mode */
+
+ENTRY(ak7801_cpu_save)
+	stmfd   sp!, { r4 - r12, lr }
+
+	@@ store co-processor registers
+
+        mrc     p15, 0, r4, c13, c0, 0  @ PID
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 0   @ translation table base address
+        mrc     p15, 0, r7, c1, c0, 0   @ control register
+
+        stmia   r0, { r4 - r13 }
+
+        mov     r0, #0
+        ldmfd   sp, { r4 - r12, pc }
+
+        @@ return to the caller, after having the MMU
+        @@ turned on, this restores the last bits from the
+        @@ stack
+resume_with_mmu:
+        mov     r0, #1
+        ldmfd   sp!, { r4 - r12, pc }
+
+        .ltorg
+
+
+ENTRY(ak7801_cpu_sleep)
+
+	mov     r0, #0
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
+
+	@@ Turn off MMU
+	mrc     p15, 0, r0, c1, c0, 0 
+        bic     r0, r0, #0x0004                 @ Disable D cache
+        bic     r0, r0, #0x0001                 @ Disable MMU
+        bic     r0, r0, #0x0100                 @ Disable MMU S-bit
+        mcr     p15, 0, r0, c1, c0, 0           @ The above three brought in effect
+	nop
+
+	@@ Jump To L2 mem
+
+	mov	pc, #0x48000000
+	
+	nop
+
+	.align 5
+
+        .data
+	
+        .global ak7801_sleep_save_phys
+ak7801_sleep_save_phys:
+        .word   0
+
+ENTRY(ak7801_cpu_resume)
+
+	mov     r1, #0
+        mcr     p15, 0, r1, c8, c7, 0           @@ invalidate I & D TLBs
+        mcr     p15, 0, r1, c7, c7, 0           @@ invalidate I & D caches
+
+	ldr     r0, ak7801_sleep_save_phys     @ address of restore block
+        ldmia   r0, { r4 - r13 }
+
+	mcr     p15, 0, r4, c13, c0, 0          @ PID
+        mcr     p15, 0, r5, c3, c0, 0           @ Domain ID
+        mcr     p15, 0, r6, c2, c0, 0           @ translation table base
+	
+	ldr     r2, =resume_with_mmu
+        mcr     p15, 0, r7, c1, c0, 0           @ turn on MMU, etc
+        nop                                     @ second-to-last before mmu
+        mov     pc, r2                          @ go back to virtual address
+
+	.ltorg
diff --git a/arch/arm/mach-ak88/time.c b/arch/arm/mach-ak88/time.c
new file mode 100644
index 00000000000..ed4f68508f5
--- /dev/null
+++ b/arch/arm/mach-ak88/time.c
@@ -0,0 +1,158 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#if 0
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#endif
+#include <asm/mach/time.h>
+
+#include <mach/map.h>
+
+#define	AK88_TIMER1_CTRL	(AK88_VA_SYSCTRL+0x18)
+#define	AK88_TIMER2_CTRL	(AK88_VA_SYSCTRL+0x1C)
+
+#define AK88_SYSCTRL_IRQ_CTRL	(AK88_VA_SYSCTRL+0x4C)
+#define	AK88_IRQ_MASK		(AK88_VA_SYSCTRL+0x34)
+
+#define TIMER_ENABLE		(1<<26)
+#define TIMER_LOAD_NEWCNT	(1<<27)
+#define TIMER_INT_CLR		(1<<28)
+#define TIMER_INT_STA		(1<<29)
+#define TIMER_CNT		(12000000/HZ)
+#define TIMER_CNT_MASK		(0x3F<<26)
+
+static unsigned long timer_startval;
+
+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
+{
+	return (ticks * 1000 / 12000000);
+}
+
+/*
+ * Returns microsecond  since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ *
+ * FIXME: this need be checked 
+ */
+static unsigned long ak880x_gettimeoffset(void)
+{
+	unsigned long tval;
+	unsigned long tdone;
+	unsigned long tcnt;
+
+	/* work out how many ticks have gone since last timer interrupt */
+
+	tval = __raw_readl(AK88_TIMER1_CTRL);
+
+	tcnt = tval & ~TIMER_CNT_MASK;
+
+	tdone = timer_startval - tcnt;
+
+	if (tval & TIMER_INT_STA) {	/* Timer1 has generated interrupt, and not clear */
+
+		/* Reread timer counter */
+		tval = __raw_readl(AK88_TIMER1_CTRL);
+		tcnt = tval & ~TIMER_CNT_MASK;
+
+		tdone = timer_startval - tcnt;
+
+		if (tcnt != 0)
+			tdone += timer_startval;
+	}
+
+	return timer_ticks_to_usec(tdone);
+}
+
+static void ak880x_timer_setup(unsigned long timecnt)
+{
+	unsigned long tctrl;
+
+	/* setting timer1 ctrl */
+#if 0
+	__raw_writel(TIMER_INT_CLR, AK88_TIMER1_CTRL);
+	__raw_writel(timecnt & ~TIMER_CNT_MASK, AK88_TIMER1_CTRL);
+
+	tctrl = __raw_readl(AK88_TIMER1_CTRL);
+	tctrl |= (TIMER_LOAD_NEWCNT | TIMER_ENABLE);
+	__raw_writel(tctrl, AK88_TIMER1_CTRL);
+#else				/* reload */
+	*(volatile unsigned int *)(AK88_TIMER1_CTRL) |=
+	    TIMER_INT_CLR | TIMER_ENABLE;
+#endif
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t ak880x_timer_interrupt(int irq, void *dev_id)
+{
+	/* printk("%s\n", __FUNCTION__); */
+
+	if (__raw_readl(AK88_TIMER1_CTRL) & TIMER_INT_STA) {
+
+		timer_tick();
+
+		ak880x_timer_setup(timer_startval);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ak880x_timer_irq = {
+	.name = "timer tick",
+	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler = ak880x_timer_interrupt,
+};
+
+static void __init ak880x_timer_init(void)
+{
+#if 0
+	timer_startval = TIMER_CNT;
+
+	/* setting timer1 ctrl */
+	ak880x_timer_setup(timer_startval);
+#else
+	unsigned long tctrl;
+	unsigned long timecnt = TIMER_CNT;
+	__raw_writel(TIMER_INT_CLR, AK88_TIMER1_CTRL);
+	__raw_writel(timecnt & ~TIMER_CNT_MASK, AK88_TIMER1_CTRL);
+
+	tctrl = __raw_readl(AK88_TIMER1_CTRL);
+	tctrl |= (TIMER_LOAD_NEWCNT | TIMER_ENABLE);
+	__raw_writel(tctrl, AK88_TIMER1_CTRL);
+#endif
+
+	/* setup irq handler for IRQ_TIMER */
+	setup_irq(IRQ_TIMER1, &ak880x_timer_irq);
+}
+
+struct sys_timer ak880x_timer = {
+	.init = ak880x_timer_init,
+	.offset = ak880x_gettimeoffset,
+//      .resume         = ak880x_timer_setup
+};
diff --git a/arch/arm/mach-ak98/Kconfig b/arch/arm/mach-ak98/Kconfig
new file mode 100644
index 00000000000..96357bb1445
--- /dev/null
+++ b/arch/arm/mach-ak98/Kconfig
@@ -0,0 +1,45 @@
+if ARCH_AK98
+
+choice
+	prompt "AK98XX boards"
+	default AK9801_ATHENA
+
+config AK9801_ATHENA
+	bool "ATHENA based on AK9801"
+	depends on ARCH_AK98
+	help
+	  Say Y here if you are using the ATHENA board based on AK9801.
+
+config AK9805_TV908
+	bool "TV908 based on AK9805"
+	depends on ARCH_AK98
+	help
+	  Say Y here if you are using the TV908 board on AK9805.
+
+config AK9805_MP5
+	bool "Smart MP5 based on AK9805"
+	depends on ARCH_AK98
+	help
+	  Say Y here if you are using the MP5 board on AK9805.
+
+endchoice
+
+config AK98_PWM
+	bool "PWM control driver for AK98"
+	depends on ARCH_AK98
+	help
+	  Say Y here if you want support pwm control.
+
+config AK98_PM
+	bool "AK98 CPU Power Management support"
+	depends on PM && ARCH_AK98
+	help
+	  Say Y here if you want support power management for AK98.
+
+config AK98_CPUFREQ
+	bool "AK98 CPU Frequency scaling support"
+	depends on CPU_FREQ && ARCH_AK98
+	help
+	  Say Y here, CPU Frequency scaling support for AK98 SoC CPUs.
+
+endif
diff --git a/arch/arm/mach-ak98/Makefile b/arch/arm/mach-ak98/Makefile
new file mode 100644
index 00000000000..a2b5e8d80fc
--- /dev/null
+++ b/arch/arm/mach-ak98/Makefile
@@ -0,0 +1,19 @@
+obj-y				+= cpu.o irq.o time.o clock.o \
+				   l2mem.o dma.o ak98-gpio.o gpio.o \
+				   devices.o reg.o dev_reset.o\
+				   l2.o l2cache.o rtc.o l2_exebuf.o \
+				   adc1.o 
+			
+
+obj-$(CONFIG_AK98_PWM)	+= pwm.o
+
+# Power Management support
+
+obj-$(CONFIG_AK98_PM)		+= pm.o 
+obj-$(CONFIG_AK98_CPUFREQ)	+= cpufreq.o ddr2change.o
+
+# Machin support
+obj-$(CONFIG_AK9801_ATHENA)	+= mach-athena.o
+obj-$(CONFIG_AK9805_TV908)	+= mach-tv908.o
+obj-$(CONFIG_AK9805_MP5)	+= mach-mp5.o
+
diff --git a/arch/arm/mach-ak98/Makefile.boot b/arch/arm/mach-ak98/Makefile.boot
new file mode 100644
index 00000000000..f2e0fa5ecbb
--- /dev/null
+++ b/arch/arm/mach-ak98/Makefile.boot
@@ -0,0 +1,11 @@
+ifdef CONFIG_VIDEO_RESERVED_MEM_SIZE
+   __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
+	   			$$[$(CONFIG_RAM_BASE) + $(CONFIG_VIDEO_RESERVED_MEM_SIZE) + 0x8000]')
+__PARAMS_PHYS	:= $(shell /bin/bash -c 'printf "0x%08x" \
+	   			$$[$(CONFIG_RAM_BASE) + $(CONFIG_VIDEO_RESERVED_MEM_SIZE) + 0x100]')
+   zreladdr-y	:= $(__ZRELADDR)
+params_phys-y	:= $(__PARAMS_PHYS)
+else
+   zreladdr-y	:= 0x80008000
+params_phys-y	:= 0x80000100
+endif
diff --git a/arch/arm/mach-ak98/adc1.c b/arch/arm/mach-ak98/adc1.c
new file mode 100644
index 00000000000..a394be1d68f
--- /dev/null
+++ b/arch/arm/mach-ak98/adc1.c
@@ -0,0 +1,196 @@
+

+#include <mach/adc1.h>

+#include <linux/delay.h>

+#include <mach/regs-adc.h>

+#include <mach/gpio.h>

+#include <linux/spinlock.h>

+#include <linux/semaphore.h>

+

+

+#undef PDEBUG           /* undef it, just in case */

+#ifdef ADC1_DEBUG

+# ifdef __KERNEL__

+/* This one if debugging is on, and kernel space */

+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)

+# else

+/* This one for user space */

+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)

+# endif

+#else

+# define PDEBUG(fmt, args...) /* not debugging: nothing */

+#endif

+

+

+//static struct semaphore adc1_sem;

+

+static void set_ADC1(unsigned int sample_rate, unsigned int wait_time)

+{

+	unsigned int bitcycle, hold_time;

+		

+	unsigned long ADC1_clk = ADC_MAIN_CLK / (ADC1_DIV + 1);

+	//clear first

+	REG32(AK98_CLK_DIV2) &= ~(0xf << 0);

+	//set clock

+	REG32(AK98_CLK_DIV2) |= (ADC1_clk & 0xf);	

+

+	//set bitcycle

+	/* because ADC1 is 5 channel multiplex, so SampleRate * 5 */

+	bitcycle	= (ADC1_clk * MHZ) / (sample_rate*5);	

+	REG32(AK98_ADC1_CTRL) &= ~(0xffff << 0);

+	REG32(AK98_ADC1_CTRL) |= (1000 & 0xffff); 

+

+	//set hold time

+	hold_time = bitcycle - 1;

+	REG32(AK98_ADC1_CTRL) &= ~(0xffff << 16);

+	REG32(AK98_ADC1_CTRL) |= (hold_time << 16);

+

+	wait_time = bitcycle - 20;

+	//set wait time

+	REG32(AK98_WTPF_CTRL) &= ~(0xffff << 0);

+	REG32(AK98_WTPF_CTRL) |= (wait_time << 0);

+	

+}

+

+static void select_AD5(void)

+{		

+	//select AD5

+	//AD0-AD4 are enable

+	REG32(AK98_ANALOG_CTRL2) &= ~(1 << 11);

+}

+

+static void reset_ADC1(void)

+{

+	//reset ADC1

+	REG32(AK98_CLK_DIV2) &= ~(1 << 22);

+	mdelay(2);

+	REG32(AK98_CLK_DIV2) |= (1 << 22);

+}

+

+static void enable_ADC1_clk(void)

+{

+	//Enable ADC1 clk

+	REG32(AK98_CLK_DIV2) |= (1 << 30);

+}

+

+static void enable_ADC1(void)

+{

+	//Enable ADC1

+	REG32(AK98_ANALOG_CTRL2) |= (1 << 8);

+}

+static void enable_ts(void)

+{	

+	//Enable Ts function

+	REG32(AK98_ANALOG_CTRL1) &= ~(1 << 1);

+	//Enable TS

+	REG32(AK98_ANALOG_CTRL2) |= (1 << 10);

+}

+

+/*

+	flg: 0  to sample the XP and YP channel only

+	flg: 1 to sample YP, XN, YN Xp

+*/

+static void select_ts_mode(int flg)

+{

+	if (flg)

+	{

+		REG32( AK98_PENDOWN_CTRL_REG_WRITE) = (REG32(AK98_PENDOWN_CTRL) |= (1 << 4));

+	}

+	else

+	{

+		REG32( AK98_PENDOWN_CTRL_REG_WRITE) = (REG32(AK98_PENDOWN_CTRL) &= (~(1 << 4)));

+	}	

+}

+

+static void 	set_pd_len(u32 penLen)

+{

+	//pen down filter counter length

+	REG32(AK98_WTPF_CTRL) |= ((penLen & 0xffff) << 16);

+}

+

+static void set_threshold(u32 threshold)

+{

+	//set ts threshold

+	//An interrupt will be generated when the change of XP/YP/XN/YN is large than the threshold

+	REG32(AK98_ANALOG_CTRL2) &= ~(0x3ff << 17);

+	REG32(AK98_ANALOG_CTRL2) |= (threshold << 17);

+}

+

+//to enable battery monitor

+void ak98_enable_bat_mon(void)

+{

+	//Enable ADC1

+	REG32(AK98_ANALOG_CTRL2) |= (1 << 9);

+}

+

+void ak98_disable_bat_mon(void)

+{

+	REG32(AK98_ANALOG_CTRL2) &= ~(1 << 9);

+}

+/*

+	1 to on

+	0 to off

+*/

+void 	ak98_power_ts(int op)

+{

+	//power down ts

+	if (op == POWER_ON)

+		REG32(AK98_ANALOG_CTRL1) &= ~(1 << 0);

+	else if ( op == POWER_OFF )

+		REG32(AK98_ANALOG_CTRL1) |= (1 << 0);

+	else

+		PDEBUG("Wrong power operation...\n");

+}

+

+void ak98_init_ADC1(unsigned int SampleRate, unsigned int WaitTime)

+{

+	static int init_flg = 0;

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+	

+	if (++init_flg == 1)

+	{		

+		ak98_power_ADC1(POWER_ON);

+		reset_ADC1();

+		

+		set_ADC1(SampleRate, WaitTime);

+		select_AD5();	

+		set_pd_len(PENDOWNLEN);

+		set_threshold(THRESHOLD);

+		

+		select_ts_mode(0);	

+		enable_ADC1_clk();	

+		

+		mdelay(5);

+		enable_ADC1();

+		enable_ts();

+		

+		ak98_power_ADC1(POWER_OFF);

+		ak98_power_ts(POWER_OFF);	

+	}

+}

+

+void ak98_power_ADC1(int op)

+{	

+	//power up ADC1

+	static int cnt = 0;

+	

+	if (op == POWER_ON)

+	{		

+		while (cnt !=0 );

+		REG32(AK98_CLK_DIV2) &= ~(1 << 29);

+		cnt = 1;

+	}

+	else if (op == POWER_OFF)

+	{

+		REG32(AK98_CLK_DIV2) |= (1 << 29);

+		cnt=0;

+	}

+

+	else 

+		PDEBUG("wrong power operation...\n");

+}

+

+

+long ak98_read_voltage(void)

+{

+	return ((REG32(AK98_ADC1_STATUS)>>10) & 0x3ff); 

+}
\ No newline at end of file
diff --git a/arch/arm/mach-ak98/ak98-gpio.c b/arch/arm/mach-ak98/ak98-gpio.c
new file mode 100755
index 00000000000..d60ce56a722
--- /dev/null
+++ b/arch/arm/mach-ak98/ak98-gpio.c
@@ -0,0 +1,1146 @@
+/*
+ *  arch/arm/mach-ak98/gpio.c
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/gpio.h>
+#include <mach/ak98-gpio.h>
+
+
+
+#if 1
+//share pin config fore module in AK980x
+struct gpio_sharepin_cfg share_cfg_module[] = {
+    //  func_module       share_config         reg1_bit_mask           reg1_bit_value                reg2_bit_mask       reg2_bit_value
+    {ePIN_AS_PCM,      SHARE_CFGBOTH,	(1<<0),				(1<<0),                 (1<<0),         (0<<0)},
+    {ePIN_AS_JTAG,     SHARE_CFGBOTH,	(1<<0),				(1<<0),                 (1<<0),			(1<<0)},
+	{ePIN_AS_RTCK,	   SHARE_CFG1,		(1<<1),				(1<<1),                 0,				0},
+	{ePIN_AS_I2S,      SHARE_CFG1,		((1<<2)|(1<<8)), 	((1<<2)|(1<<8)),		0,				0},
+	{ePIN_AS_USB_OTG,  SHARE_CFG1,		(1<<3),				(1<<3),                 0,				0},
+	{ePIN_AS_PWM1,     SHARE_CFG1,		(1<<4),				(1<<4),                 0,				0},
+    {ePIN_AS_PWM2,     SHARE_CFG1,		(1<<5),				(1<<5),                 0,				0},
+    {ePIN_AS_PWM3,     SHARE_CFG1,		(1<<6),				(1<<6),                 0,				0},
+    {ePIN_AS_PWM4,     SHARE_CFG1,		(1<<7),				(1<<7),                 0,				0},
+    {ePIN_AS_UART1,    SHARE_CFG1,		(1<<9),				(1<<9),                 0,				0},
+    {ePIN_AS_UART2,    SHARE_CFG1,		(3<<10),			(3<<10),                0,				0},
+    {ePIN_AS_UART3,    SHARE_CFG1,		(3<<12),			(3<<12),                0,				0},
+    {ePIN_AS_UART4,    SHARE_CFGBOTH,	(3<<14),			(3<<14),                (3<<1),			(1<<1)}, 
+    {ePIN_AS_NFC,      SHARE_CFGBOTH,	((0xF<<16)|(1<<22)), ((0xF<<16)|(1<<22)),	(3<<3),			(1<<3)},
+    {ePIN_AS_NFC_EXT,  SHARE_CFG2,		0,					0,                      (1<<7),			(1<<7)},
+    {ePIN_AS_CAMERA,   SHARE_CFG1,		(1<<24),			(1<<24),                0,				0},
+    {ePIN_AS_LCD,      SHARE_CFG1,		(0xF<<25),			(0xF<<25),              0,				0},
+    {ePIN_AS_LCD_EXT,  SHARE_CFG2,		0,					0,                      (1<<8),			(1<<8)},
+    {ePIN_AS_SDMMC1,   SHARE_CFGBOTH,	(7<<16),			(7<<16),                (3<<3),			(2<<3)},
+    {ePIN_AS_SDMMC2,   SHARE_CFGBOTH,	(1<<29),			(1<<29),                (3<<5),			(2<<5)},
+    {ePIN_AS_SDIO,     SHARE_CFGBOTH,	(3<<14),			(3<<14),                (3<<1),			(2<<1)},
+    {ePIN_AS_SPI1,     SHARE_CFG1,		(1<<30),			(1<<30),                0,				0},
+    {ePIN_AS_SPI2,     SHARE_CFG1,		(1<<31),			(1<<31),                0,				0},
+    {ePIN_AS_MAC,      SHARE_CFG2,		0,					0,                      (1<<11)|(1<<7),	(1<<11)|(0<<7)},
+    {ePIN_AS_CLK12MO,  SHARE_CFG2,		0,					0,                      (1<<18),		(1<<18)},
+    {ePIN_AS_CLK32KO,  SHARE_CFG2,		0,					0,                      (1<<19),		(1<<19)},
+    {ePIN_AS_I2C,      SHARE_CFG2,		0,					0,                      (1<<21),		(1<<21)},
+                                                                                                            
+    {ePIN_AS_DUMMY,    EXIT_CFG,		0,					0,                      0,				0}
+};
+
+
+//this used to clr in gpio chare pin cfg1
+T_SHARE_CFG_GPIO share_cfg_gpio[] = {
+    //start         end             bit
+    {0,             3,              0},
+    {4,             4,              1},
+    {5,             7,              2},
+    {8,             8,              3},
+    {9,             9,              4},
+    {10,            10,             5},
+    {11,            11,             6},
+    {12,            12,             7},
+    {13,            13,             8},
+    {18,            19,             11},
+    {22,            23,             13},
+    {24,            25,             14},
+    {26,            27,             15},
+    {30,            30,             16},
+    {31,            33,             17},
+    {34,            37,             18},
+    {38,            38,             19},
+    {41,            41,             22},
+    {47,            58,             24},
+    {62,            68,             25},
+    {61,            61,             26},
+    {69,            70,             27},
+    {71,            71,             28},
+    {72,            75,             29},
+    {76,            79,             30},
+    {80,            83,             31},
+};
+
+//this used to clr in gpio chare pin cfg2
+T_SHARE_CFG_GPIO share_cfg_gpio2[] = {
+    //start       	    end                    bit
+    {84,            89,             8},
+    {90,            90,             9},
+    {91,            91,             10},
+};
+
+//this used to set in gpio chare pin cfg2
+T_SHARE_CFG_GPIO share_cfg_gpio3[] = {
+    //start             end                   bit
+    {14,            14,             12},
+    {15,            15,             13},
+    {16,            16,             14},
+    {17,            17,             15},
+    {20,            20,             16},
+    {21,            21,             17},
+};
+
+
+#define INVALID_WK_BIT 0xff
+struct t_gpio_wakeup_cfg gpio_wakeup_cfg[] = {
+		//gpio_start        gpio_end      start_bit
+		{AK98_GPIO_5,  AK98_GPIO_7,  0 },
+		{AK98_GPIO_10, AK98_GPIO_13, 3 },
+		{AK98_GPIO_16, AK98_GPIO_19, 7 },
+		{AK98_GPIO_24, AK98_GPIO_27, 11},
+		{AK98_GPIO_72, AK98_GPIO_75, 15},
+		{AK98_GPIO_104,AK98_GPIO_107,19},
+		{AK98_GPIO_84, AK98_GPIO_84, 23},
+		{AK98_GPIO_109,AK98_GPIO_116,24},
+};
+
+/*
+    this table contains all the GPIOs whose attribute can be set, the io attribute is one 
+    of {IE, PE, SL, DS, PS}, one gpio may support only one or several attributes setting,  
+    an element of row 2~5 indicates whether this    attibute setting is aupported by this gpio, 
+    if supported, this element tells us how can we set register.
+
+    the value is encoded as:
+        bit[0:7]: register addr shift, base addr is CHIP_CONF_BASE_ADDR
+        bit[8:15]: start bit
+
+    take value 0x3d4 for example:
+    the lower 8-bit is 0xd4, that is the shift, then the address of the register we will configure
+    is CHIP_CONF_BASE_ADDR+0xd4
+
+    bit[8:15] of 0x3d4 is 3, that means we shoulde configure the bit[3] of register 
+    "CHIP_CONF_BASE_ADDR+0xd4"
+*/
+static const unsigned long gpio_io_set_table_9801[][PIN_ATTE_LINE] = { 
+    //pin no.   IE              PE                  SL                      DS                      PS
+    {16,	0x3d4,      0xfd4,      ATTR_FIXED_1,     ATTR_FIXED_0,     0x109c},
+    {17,	0x2d4,      0xed4,      ATTR_FIXED_1,     ATTR_FIXED_0,     0x119c},
+    {18,	0x5d4,      0x11d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x129c},
+    {19,	0x4d4,      0x10d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x139c},
+    {20,	0x7d4,      0x13d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x149c},
+    {21,	0x6d4,      0x12d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x159c},
+    {22,	0x9d4,      0x15d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x169c},
+    {23,	0x8d4,      0x14d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x179c},               
+    {24,	0xbd4,      0x17d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x189c},
+    {25,	0xad4,      0x16d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x199c},
+    {26,	0xdd4,      0x19d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x1a9c},
+    {27,	0xcd4,      0x18d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x1b9c},
+    {28,	0x1bd4,     0x1c9c,     ATTR_FIXED_1,     0x1d4,			ATTR_FIXED_1},
+    {29,	0x1ad4,     0x1d9c,     ATTR_FIXED_1,     0x0d4,			ATTR_FIXED_1},
+                
+    {109,	0x4d8,      0x8d8,      ATTR_FIXED_1,     0xcd8,			0xda8},
+    {END_FLAG,   0,		0,          0,					0,				0}
+};
+static const unsigned long gpio_io_set_table_9805[][PIN_ATTE_LINE] = { 
+    //pin no.   IE              PE                  SL                      DS                      PS
+    {16,	0x3d4,      0xfd4,      ATTR_FIXED_1,     ATTR_FIXED_0,     0x109c},
+    {17,	0x2d4,      0xed4,      ATTR_FIXED_1,     ATTR_FIXED_0,     0x119c},
+    {18,	0x5d4,      0x11d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x129c},
+    {19,	0x4d4,      0x10d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x139c},
+    {24,	0xbd4,      0x17d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x189c},
+    {25,	0xad4,      0x16d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x199c},
+    {26,	0xdd4,      0x19d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x1a9c},
+    {27,	0xcd4,      0x18d4,     ATTR_FIXED_1,     ATTR_FIXED_0,     0x1b9c},
+    {28,	0x1bd4,     0x1c9c,     ATTR_FIXED_1,     0x1d4,			ATTR_FIXED_1},
+    {29,	0x1ad4,     0x1d9c,     ATTR_FIXED_1,     0x0d4,			ATTR_FIXED_1},
+    {END_FLAG,   0,		0,          0,					0,				0}
+};
+
+
+/*
+    this table contains all the GPIOs attribute: each GPIO is represented by 2-bit,
+    which equals to:   
+    			00-pullup
+                   01-pulldown
+                   10-pullup/pulldown
+                   11-undefined
+*/
+const unsigned long gpio_pull_attribute_table_9801[][2] = {  
+    {0x04455501, /*gpio[0:15]*/          0x00aaaaaa}, /*gpio[16:31]*/             //reg1
+    {0x54000000, /*gpio[32:47]*/         0x57d55555}, /*gpio[48:63]*/             //reg2
+    {0x55005555, /*gpio[64:79]*/         0xf5555555}, /*gpio[80:95]*/             //reg3   
+    {0x4b55f557, /*gpio[96:111]*/        0xfffffc01}  /*gpio[112:116]*/           //reg4 
+};
+const unsigned long gpio_pull_attribute_table_9805[][2] = {  
+    {0x07c55501, /*gpio[0:15]*/          0x00aaffaa}, /*gpio[16:31]*/             //reg1
+    {0x54000000, /*gpio[32:47]*/         0x57d55555}, /*gpio[48:63]*/             //reg2
+    {0x55005555, /*gpio[64:79]*/         0xf55555ff}, /*gpio[80:95]*/             //reg3   
+    {0xfff5ffff, /*gpio[96:111]*/        0xffffff3f}  /*gpio[112:116]*/           //reg4 
+};
+
+
+unsigned int ak9801_invalid_gpio[] = {
+	AK98_GPIO_59, AK98_GPIO_60, AK98_GPIO_94, 
+	AK98_GPIO_95, AK98_GPIO_96, AK98_GPIO_108
+};
+
+unsigned int ak9805_invalid_gpio[] = {
+	AK98_GPIO_11, AK98_GPIO_12, AK98_GPIO_20, AK98_GPIO_21, AK98_GPIO_22,
+	AK98_GPIO_23, AK98_GPIO_59, AK98_GPIO_60, AK98_GPIO_80, AK98_GPIO_81,
+	AK98_GPIO_82, AK98_GPIO_83, AK98_GPIO_90, AK98_GPIO_91, AK98_GPIO_94,
+	AK98_GPIO_95, AK98_GPIO_96, AK98_GPIO_97, AK98_GPIO_98, AK98_GPIO_99,
+	AK98_GPIO_100, AK98_GPIO_101, AK98_GPIO_106, AK98_GPIO_107, AK98_GPIO_108,
+	AK98_GPIO_109, AK98_GPIO_110, AK98_GPIO_111, AK98_GPIO_112, AK98_GPIO_113,
+	AK98_GPIO_114, AK98_GPIO_116
+};
+
+
+ static unsigned char gpio_assert_legal(unsigned long pin);
+
+
+static inline unsigned int round_mcgpio(unsigned int pin)
+{
+	if (pin >= AK98_MCGPIO_0 && pin <= AK98_MCGPIO_19)
+		return pin - AK98_MCGPIO_0;
+	return pin;
+}
+static unsigned char get_bit_by_pin_wk(unsigned char pin)
+{
+	int i, n;
+	n = ARRAY_SIZE(gpio_wakeup_cfg);
+
+	for (i=0; i<n; i++)
+	{
+		if (pin >= gpio_wakeup_cfg[i].gpio_start && pin <= gpio_wakeup_cfg[i].gpio_end)
+			return gpio_wakeup_cfg[i].start_bit + (pin - gpio_wakeup_cfg[i].gpio_start);
+	}
+
+	return INVALID_WK_BIT;
+}
+
+
+void ak98_gpio_wakeup_pol(unsigned int pin, unsigned char pol)
+{
+	unsigned char bit = get_bit_by_pin_wk(pin);
+	unsigned int val;
+
+	if (bit == INVALID_WK_BIT)
+	{
+		panic("this pin %u doesn't support wakeup function\n", pin);
+		return;
+	}
+
+	
+	val = REG32(AK98_WGPIO_POLARITY);
+	//when the specific bit is set to 0, the wake-up GPIO is rising triggered
+	//when the specific bit is set to 1, the wake-up GPIO is falling triggered
+	val &= ~(1 << bit);
+	val |= (pol << bit);
+	
+	REG32(AK98_WGPIO_POLARITY) = val;
+		
+}
+EXPORT_SYMBOL(ak98_gpio_wakeup_pol);
+
+int ak98_gpio_wakeup(unsigned int pin, unsigned char enable)
+{
+	unsigned char bit = get_bit_by_pin_wk(pin);
+	unsigned int val;
+
+
+	if (bit == INVALID_WK_BIT)
+	{
+		panic("this pin %d doesn't support wakeup function\n", pin);
+		return -1;
+	}
+	//clear wake gpio status
+	val = REG32(AK98_WGPIO_CLEAR);
+	val |= (1 << bit);
+	REG32(AK98_WGPIO_CLEAR) = val;
+	val &= ~(1 << bit);
+	REG32(AK98_WGPIO_CLEAR) = val;
+
+	
+	val = REG32(AK98_WGPIO_ENABLE);
+	if (enable == AK98_WAKEUP_ENABLE)
+	{
+		val |= (1 << bit);
+	}
+	else if (enable == AK98_WAKEUP_DISABLE)
+	{
+		val &= ~(1 << bit);
+	}
+	else
+		panic("wrong enable value in ak98_gpio_wakeup\n");
+	REG32(AK98_WGPIO_ENABLE) = val;
+	
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_wakeup);
+
+/*
+ * @brief set gpio pin group as specified module used
+ * @param[in] PinCfg enum data. the specified module
+ */
+void ak98_group_config(T_GPIO_SHAREPIN_CFG mod_name)
+{
+    unsigned long i, flags, val = 0;
+	
+    if(ePIN_AS_GPIO == mod_name)
+    {
+        //set all pin as gpio except uart0
+        local_irq_save(flags);
+		__raw_writel(0x100, AK98_SHAREPIN_CON1);		
+		__raw_writel(0x1, AK98_SHAREPIN_CON2);
+		local_irq_restore(flags);
+        return;
+    }
+
+#ifdef CONFIG_AK9805
+	//canot set the following group in ak9805
+	if( ePIN_AS_PWM3 == mod_name || ePIN_AS_PWM4 == mod_name ||
+		ePIN_AS_UART3 == mod_name || ePIN_AS_SPI2 == mod_name || 
+		ePIN_AS_MAC == mod_name )
+	{
+		panic("Can't set pin configuration: %d in chip Ak9805\n", mod_name);
+		return;
+	}
+#endif
+
+    for(i = 0; ; i++)
+    {
+        if(ePIN_AS_DUMMY == share_cfg_module[i].func_module)
+            break;
+
+        if(mod_name == share_cfg_module[i].func_module)
+        {	
+        	//set pull attribute for module
+            g_ak98_setgroup_attribute(mod_name);
+			
+			local_irq_save(flags);
+            switch(share_cfg_module[i].share_config) {
+            	case SHARE_CFG1: //set share pin cfg reg1
+					val = __raw_readl(AK98_SHAREPIN_CON1);
+					val &= ~(share_cfg_module[i].reg1_bit_mask);
+					val |= (share_cfg_module[i].reg1_bit_value);
+					__raw_writel(val, AK98_SHAREPIN_CON1);
+					break;
+					
+				case SHARE_CFG2: //set share pin cfg reg2
+					val = __raw_readl(AK98_SHAREPIN_CON2);
+					val &= ~(share_cfg_module[i].reg2_bit_mask);
+					val |= (share_cfg_module[i].reg2_bit_value);
+					__raw_writel(val, AK98_SHAREPIN_CON2);
+					break;
+					
+				case SHARE_CFGBOTH: 
+					val = __raw_readl(AK98_SHAREPIN_CON1);
+					val &= ~(share_cfg_module[i].reg1_bit_mask);
+					val |= (share_cfg_module[i].reg1_bit_value);
+					__raw_writel(val, AK98_SHAREPIN_CON1);
+					
+					val = __raw_readl(AK98_SHAREPIN_CON2);
+					val &= ~(share_cfg_module[i].reg2_bit_mask);
+					val |= (share_cfg_module[i].reg2_bit_value);
+					__raw_writel(val, AK98_SHAREPIN_CON2);
+					break;
+				default:
+					break;
+            }
+			local_irq_restore(flags);
+            return ;
+        }
+    }
+	return ;
+}
+EXPORT_SYMBOL(ak98_group_config);
+#endif
+
+
+
+
+void ak98_sharepin_cfg1(unsigned char to, unsigned char offset, T_SHARE_CONFG conf)
+{
+	void __iomem *base = AK_NULL;
+	unsigned long flags;
+	
+	if (offset > 31) {
+		printk("Error, configuration sharepin1 offset larger\n");
+		return;
+	}
+	
+	switch(conf) {
+		case SHARE_CONFG1:
+			base = AK98_SHAREPIN_CON1;
+			break;		
+		case SHARE_CONFG2:
+			base = AK98_SHAREPIN_CON2;
+			break;
+		default:
+			break;
+	}
+	
+	local_irq_save(flags);
+	if (0 == to)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return;
+}
+EXPORT_SYMBOL(ak98_sharepin_cfg1);
+
+void ak98_sharepin_cfg2(unsigned long mask, unsigned long value, unsigned char offset)
+{
+	void __iomem *base = AK98_SHAREPIN_CON2;
+	unsigned long flags, val = 0;
+
+	if (offset > 21) {
+		printk("Error, configuration sharepin2 offset larger\n");
+		return;
+	}
+
+	local_irq_save(flags);
+	val = __raw_readl(base);
+	val &= ~(mask << offset);
+	val |= (value << offset);
+	__raw_writel(val, base);
+	local_irq_restore(flags);
+	return;
+}
+EXPORT_SYMBOL(ak98_sharepin_cfg2);
+
+
+ unsigned char gpio_assert_legal(unsigned long pin)
+{
+	int i, len;
+	unsigned int *gpio_legal;
+#ifdef CONFIG_AK9801
+	len = sizeof(ak9801_invalid_gpio)/sizeof(ak9801_invalid_gpio[0]);
+	gpio_legal = ak9801_invalid_gpio;
+#endif
+#ifdef CONFIG_AK9805
+	len = sizeof(ak9805_invalid_gpio)/sizeof(ak9805_invalid_gpio[0]);
+	gpio_legal = ak9805_invalid_gpio;
+#endif
+
+	for(i = 0; i < len; i++) {
+		if(gpio_legal[i] == pin)
+			return AK_FALSE;	
+	}
+	return AK_TRUE;
+}
+ unsigned long gpio_pin_check(unsigned long pin)
+{   
+    unsigned long i = 0;
+    const unsigned long (*gpio_io_set_table)[PIN_ATTE_LINE] = AK_NULL;
+
+#ifdef CONFIG_AK9801
+	gpio_io_set_table = gpio_io_set_table_9801;
+#endif
+#ifdef CONFIG_AK9805
+	gpio_io_set_table = gpio_io_set_table_9805;    
+#endif
+
+    while(1)
+	{
+        if ((gpio_io_set_table[i][0] == pin) || (gpio_io_set_table[i][0] == END_FLAG))
+            break;  
+        i++;
+    }
+
+    if (gpio_io_set_table[i][0] != END_FLAG)
+        return i;
+    else
+        return INVALID_GPIO;
+}
+
+
+/**
+ * @brief set gpio share pin as gpio 
+ * @param pin [in]  gpio pin ID
+ */
+int g_ak98_setpin_as_gpio(unsigned int pin)
+{
+    unsigned long i, bit = 0;
+	unsigned long flags;
+
+    //check param
+    if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %u configuration!\n", pin);
+		return -1;
+	}
+
+    if(28 == pin || 29 == pin)
+		REG32(AK98_SHAREPIN_CON2) &= ~(0x3 << 1);
+	
+    //loop to find the correct bits to clr in share ping cfg1
+    for(i = 0; i < ARRAY_SIZE(share_cfg_gpio); i++){
+        if((pin >= share_cfg_gpio[i].gpio_start) && (pin <= share_cfg_gpio[i].gpio_end))
+        {
+        	local_irq_save(flags);
+            bit = share_cfg_gpio[i].bit;
+			REG32(AK98_SHAREPIN_CON1) &= ~(1 << bit);
+			local_irq_restore(flags);
+            return 0;
+        }
+    }
+
+    //loop to find the correct bits to clr in share ping cfg2
+    for(i = 0; i < ARRAY_SIZE(share_cfg_gpio2); i++){
+        if((pin >= share_cfg_gpio2[i].gpio_start) && (pin <= share_cfg_gpio2[i].gpio_end))
+        {
+        	local_irq_save(flags);
+            bit = share_cfg_gpio2[i].bit;
+			REG32(AK98_SHAREPIN_CON2) &= ~(1 << bit);
+			local_irq_restore(flags);
+            return 0;
+        }
+    }
+    
+    //loop to find the correct bits to set in share ping cfg2
+    for(i = 0; i < ARRAY_SIZE(share_cfg_gpio3); i++){
+        if((pin >= share_cfg_gpio3[i].gpio_start) && (pin <= share_cfg_gpio3[i].gpio_end))
+        {
+       		local_irq_save(flags);
+            bit = share_cfg_gpio3[i].bit;
+			REG32(AK98_SHAREPIN_CON2) |= (1 << bit);
+			local_irq_restore(flags);
+            return 0;
+        }
+    }
+    return 0;
+}
+
+ int mc_ak98_setpin_as_mcgpio(unsigned int pin)
+{
+	unsigned int val;
+	unsigned long flags;
+
+   	local_irq_save(flags);
+	val= REG32(AK98_SHAREPIN_CON2);
+
+	if (pin < AK98_MCGPIO_0 || pin > AK98_MCGPIO_19)
+	{
+		panic("Error! Invalid mcgpio %u configuration.\n", pin);
+		return -1;
+	}
+	
+	if (AK98_MCGPIO_18 == pin)
+		val &= ~(1 << 18);
+	else if (AK98_MCGPIO_19 == pin)
+		val &= ~(1 << 19);
+	else
+	{
+		val &= ~(1 << 11);	
+		val &= ~(1 << 7);
+	}
+
+	REG32(AK98_SHAREPIN_CON2) = val;
+
+	local_irq_restore(flags);	
+	
+    return 0;
+}
+
+
+
+/*
+    attr: to set what kind of attribute of pin
+    enable: to enable or disable this pin attribute,1:enable 0:disable
+
+    the gpio pin attribure set is mainly for two kinds of pins: one is general GPIOs, the 
+    other is RAM bus(data & addr), for general GPIO, param pin in this function is the 
+    GPIO number, for RAM bus, param "pin" should be set as MADD_A or MDAT_A
+
+    NOTE: the following four functions:ak98_setpin_attribute, ak98_gpio_pullup,
+            ak98_gpio_pulldown, gpio_set_pin_share, you'd better not check the 
+            returned value, because it doesn't matter to give a wrong param to a
+            specific pin
+*/
+ void g_ak98_setpin_attribute(unsigned int pin, 
+	T_GPIO_PIN_ATTR attr, unsigned char enable)
+{
+	void __iomem *base = AK98_VA_SYSCTRL;
+	void __iomem *reg_addr;
+    unsigned long flags, i, reg_bit;
+    const unsigned long (*gpio_set_table)[PIN_ATTE_LINE] = AK_NULL;
+
+    if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %u configuration!\n", pin);
+		return;
+	}
+
+#ifdef CONFIG_AK9801
+	gpio_set_table = gpio_io_set_table_9801;
+#endif
+#ifdef CONFIG_AK9805
+	gpio_set_table = gpio_io_set_table_9805;    
+#endif
+
+    if ((i = gpio_pin_check(pin)) == INVALID_GPIO){
+		/* printk; couldn't preempt */
+        return;
+    }
+
+    if (gpio_set_table[i][attr] == GPIO_ATTR_UNSUPPORTED) {
+		/* printk; couldn't preempt */
+        return;		
+    }
+    else if ((gpio_set_table[i][attr] == ATTR_FIXED_1) || 
+                (gpio_set_table[i][attr] == ATTR_FIXED_0))
+    {
+    	/* printk; couldn't preempt */
+        return;
+    }
+
+    /*
+        if we want to set this attribute, we should get two things:
+        1. which register should be configured
+        2. which bit of this register should be configured
+
+        following, we decode corresponding items in gpio_io_set_table to 
+        get the above two things
+    */
+    
+    reg_addr = base + (unsigned char)(gpio_set_table[i][attr] & 0xff);
+    reg_bit = (gpio_set_table[i][attr] >> 8) & 0xff;
+	
+	local_irq_save(flags);
+    if (enable)
+		REG32(reg_addr) |= (1 << reg_bit);
+    else
+		REG32(reg_addr) &= ~(1 << reg_bit);
+	local_irq_restore(flags);
+    return ; 
+}
+
+/*
+    enable: 1:enable pullup 0:disable pullup function
+	  if the pin is attached pullup and pulldown resistor, then writing 1 to enable
+        pullup, 0 to enable pulldown, if you want to disable pullup/pulldown, then 
+        disable the PE parameter
+*/
+ int g_ak98_gpio_pullup(unsigned int pin, unsigned char enable)
+{
+	void __iomem *base = AK98_PPU_PPD_BASE(pin);
+    unsigned long index, reg_data, shift, rs;
+    T_GPIO_TYPE reg_bit;
+    const unsigned long (*gpio_pull_attribute_table)[2] = AK_NULL;
+	unsigned long flags, offset;
+
+   if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %u configuration!\n", pin);
+		return -1;
+	}
+#ifdef CONFIG_AK9801
+	gpio_pull_attribute_table = gpio_pull_attribute_table_9801;
+#endif
+#ifdef CONFIG_AK9805
+	gpio_pull_attribute_table = gpio_pull_attribute_table_9805;
+#endif
+
+    index = pin / 32;
+    offset = pin % 32;
+    if (offset < 16)
+        shift = 0;
+    else
+        shift = 1;  
+    
+    //get pin pullup/pulldown attribute
+    reg_data = gpio_pull_attribute_table[index][shift];
+    if (shift)
+        rs = (offset - 16) * 2;
+    else
+        rs = offset * 2;
+    reg_bit = (reg_data >> rs) & 0x3;   
+
+    if ((reg_bit == PULLDOWN) || (reg_bit == UNDEFINED)) {
+		/* printk; couldn't preempt */
+        return 0;
+    }
+        
+    //if this pin setting needs IO controller be set
+    if (gpio_pin_check(pin) != INVALID_GPIO)
+    {       
+        g_ak98_setpin_attribute(pin, GPIO_ATTR_PE, AK_TRUE);
+    }
+
+	local_irq_save(flags);
+    //enable/disable pullup
+    if (enable)
+    {       
+        //if the pin is attached pullup/pulldown registor, else pullup register 	
+        if (reg_bit == PULLUPDOWN)
+			REG32(base) |= (1 << offset);
+        else
+			REG32(base) &= ~(1 << offset);
+    }
+    else 
+    {
+        //first disable PE attribute
+        g_ak98_setpin_attribute(pin, GPIO_ATTR_PE, AK_FALSE);
+
+        //if this pin is attached pullup resistor only, disable it
+        if (reg_bit != PULLUPDOWN) 
+			REG32(base) |= (1 << offset);
+    }
+	local_irq_restore(flags);
+    return 0; 
+}
+
+
+//1.enable pulldown 0.disable pulldown
+ int g_ak98_gpio_pulldown(unsigned int pin, unsigned char enable)
+{
+	void __iomem *base = AK98_PPU_PPD_BASE(pin);
+    unsigned long index, reg_data, shift, rs;
+    T_GPIO_TYPE reg_bit;
+    const unsigned long (*gpio_pull_attribute_table)[2] = AK_NULL;	
+	unsigned long flags, offset;
+	
+    if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %u configuration!\n", pin);
+		return -1;
+	}
+	
+#ifdef CONFIG_AK9801
+	gpio_pull_attribute_table = gpio_pull_attribute_table_9801;
+#endif
+#ifdef CONFIG_AK9805
+	gpio_pull_attribute_table = gpio_pull_attribute_table_9805;
+#endif
+
+    index = pin / 32;
+    offset = pin % 32;
+    if (offset < 16)
+        shift = 0;
+    else
+        shift = 1;  
+    
+    //get pin attribute
+    reg_data = gpio_pull_attribute_table[index][shift];
+    if (shift)
+        rs = (offset - 16) * 2;
+    else
+        rs = offset * 2;
+    reg_bit = (reg_data >> rs) & 0x3;
+
+    if ((reg_bit == PULLUP) || (reg_bit == UNDEFINED)) {
+		/* printk; couldn't preempt */
+        return -1;
+    }
+
+    //if this pin setting needs IO controller be set
+    if (gpio_pin_check(pin) != INVALID_GPIO)
+    {       
+        g_ak98_setpin_attribute(pin, GPIO_ATTR_PE, AK_TRUE);
+    }
+
+    //enable/disable pulldown
+    local_irq_save(flags);
+    if (enable)    
+		REG32(base) &= ~(1 << offset);
+	else {
+        //same as pullup configuration
+        g_ak98_setpin_attribute(pin, GPIO_ATTR_PE, AK_FALSE);
+        
+        if (reg_bit != PULLUPDOWN) 
+			REG32(base) |= (1 << offset);
+    }
+	local_irq_restore(flags);
+    return 0; 
+}
+
+
+ void g_ak98_setgroup_attribute(T_GPIO_SHAREPIN_CFG mod_name)
+{
+    unsigned long pin, start_pin = 0, end_pin = 0;
+    
+    switch (mod_name) {
+        case ePIN_AS_NFC:
+        case ePIN_AS_SDMMC1:
+            start_pin = 30, end_pin = 37;
+            //set databus of Nand, MMCSD 
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {         
+                g_ak98_gpio_pullup(pin, AK_TRUE);
+                g_ak98_setpin_attribute(pin, GPIO_ATTR_IE, AK_TRUE);
+            }
+            break;		
+		case ePIN_AS_SPI1:
+            start_pin = 76, end_pin = 79;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pullup(pin, AK_TRUE);
+            }
+            break;
+        case ePIN_AS_SPI2:
+            start_pin = 80, end_pin = 83;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pullup(pin, AK_TRUE);
+            }
+            break;
+			
+        case ePIN_AS_SDIO:
+            start_pin = 24, end_pin = 29;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                //enable SDIO dataline pullup
+                g_ak98_gpio_pullup(pin, AK_TRUE);   
+
+                //enable SDIO dataline IE attribute
+                g_ak98_setpin_attribute(pin, GPIO_ATTR_IE, AK_TRUE);
+            }
+            break;
+            
+        case ePIN_AS_I2S:
+            //20090806 need to confirm!!!
+            start_pin = 5, end_pin = 7;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pulldown(pin, AK_FALSE);   
+            }
+            g_ak98_gpio_pulldown(AK98_GPIO_13, AK_FALSE); //gpio13 share with I2S_MCLK
+            break;
+            
+        case ePIN_AS_UART1: 
+            start_pin = 14, end_pin = 15;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pullup(pin, AK_FALSE);
+            }
+            break;
+            
+        case ePIN_AS_UART4: 
+            start_pin = 24, end_pin = 27; //end_pin = 27 ,caolianming           
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pullup(pin, AK_TRUE);    
+                if ((pin == 25) || (pin == 27))         
+                    g_ak98_setpin_attribute(pin, GPIO_ATTR_IE, AK_TRUE);                 
+            }   
+            break;
+			
+		case ePIN_AS_I2C:
+            start_pin = 92, end_pin = 93;
+            for (pin = start_pin; pin <= end_pin; pin++)
+            {
+                g_ak98_gpio_pulldown(pin, AK_FALSE);
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+
+
+/* 
+ * configuration gpio pin
+ * 1: corresponding port is input mode
+ * 0: corresponding port is output mode
+ */
+int g_ak98_gpio_cfgpin(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK98_GPIO_DIR_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+	unsigned long flags;
+
+	
+ 	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %d configuration!\n", pin);
+		return -1;
+	}
+
+	local_irq_save(flags);
+	if (0 == to) {  //output mode
+		REG32(base) &= ~(1 << offset);
+		
+		//pin90 and pin91 sepecial, cause chip driver has problem.
+		if(pin == 90)
+			REG32(AK98_SHAREPIN_CON2) &= ~(1 << 9);
+		else if (pin == 91)
+			REG32(AK98_SHAREPIN_CON2) &= ~(1 << 10);
+	} else {   //input mode
+		if(gpio_pin_check(pin) != INVALID_GPIO){
+            g_ak98_setpin_attribute(pin, GPIO_ATTR_IE, AK_TRUE);
+        }
+		REG32(base) |= (1 << offset);
+		
+		if(pin == 90)
+			REG32(AK98_SHAREPIN_CON2) |= (1 << 9);
+		else if (pin == 91) 
+			REG32(AK98_SHAREPIN_CON2) |= (1 << 10);	
+	}
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+/* 
+ * configuration gpio pin
+ * 1: corresponding port is input mode
+ * 0: corresponding port is output mode
+ */
+int mc_ak98_mcgpio_cfgpin(unsigned int pin, unsigned int to)
+{
+	void __iomem *base;
+	unsigned int offset;
+	unsigned long flags;
+	
+	pin = round_mcgpio(pin);
+	base = AK98_MCGPIO_DIR_BASE(pin);
+	offset = ((pin) & 31);
+
+	if (pin > MCGPIO_UPLIMIT) {
+		panic("Error, Invalid mcgpio %d configuration!\n", pin);
+		return -1;
+	}
+	
+	local_irq_save(flags);
+	if (0 == to)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+
+
+
+/* hold the real-time output value from GPIO[x] */ 
+int g_ak98_gpio_setpin(unsigned int pin, unsigned int to)
+{
+	void __iomem *base = AK98_GPIO_OUT_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+	unsigned long flags;
+
+		
+	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, Invalid gpio %d configuration!\n", pin);
+		return -1;
+	}
+
+	local_irq_save(flags);
+	if (0 == to)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+int mc_ak98_mcgpio_setpin(unsigned int pin, unsigned int to)
+{
+	void __iomem *base;
+	unsigned int offset;
+	unsigned long flags;
+
+	pin = round_mcgpio(pin);
+	base = AK98_MCGPIO_OUT_BASE(pin);
+	offset = ((pin) & 31);
+	
+	if (pin > MCGPIO_UPLIMIT) {
+		panic("error, invalid mcgpio %d configuration!\n", pin);
+		return -1;
+	}
+	
+	local_irq_save(flags);
+	if (0 == to)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+/* hold the real-time input value of GPIO[x] */ 
+ int g_ak98_gpio_getpin(unsigned int pin)
+{
+	void __iomem *base = AK98_GPIO_IN_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+
+	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, read invalid gpio %d status!\n", pin);
+		return -1;
+	}
+	return ((__raw_readl(base) & (1 << offset)) == (1 << offset));
+}
+
+int mc_ak98_mcgpio_getpin(unsigned int pin)
+{
+	void __iomem *base;
+	unsigned int offset;
+	
+	pin = round_mcgpio(pin);
+	base = AK98_MCGPIO_IN_BASE(pin);
+	offset = ((pin) & 31);
+
+	
+	if(pin > MCGPIO_UPLIMIT) {
+		panic("Error, read invalid mcgpio %d status!\n", pin);
+		return -1;
+	}
+	return ((__raw_readl(base) & (1 << offset)) == (1 << offset));
+}
+
+
+/* 0: enable pull down, 1: disable pull down */
+int mc_ak98_mcgpio_pulldown(unsigned int pin, unsigned char enable)
+{
+	void __iomem *base;
+	unsigned int offset;
+	unsigned long flags;
+
+	pin = round_mcgpio(pin);
+	base = AK98_MCGPIO_PPU_PPD_BASE(pin);	
+	offset = ((pin) & 31);
+	
+	if(pin > MCGPIO_UPLIMIT) {
+		panic("Error, invalid mcgpio %d!\n", pin);
+		return -1;
+	}
+	
+	local_irq_save(flags);
+	if (0 == enable)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+/* 
+ * enalbe/disable the interrupt function of GPIO[X]
+ * 1: interrupt function of corresponding port is enable
+ * 0: interrupt function of corresponding port is disable
+ */
+int g_ak98_gpio_inten(unsigned int pin, unsigned int enable)
+{
+	void __iomem *base = AK98_GPIO_INTEN_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+	unsigned long flags;
+
+	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, invalid gpio %d!\n", pin);
+		return -1;
+	}
+	
+	local_irq_save(flags);
+	if (0 == enable)
+		REG32(base) &= ~(1 << offset);
+	else
+		REG32(base) |= (1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+/*
+ * interrupt polarity selection
+ * 1: the input interrupt polarity of GPIO[X] is active high
+ * 0: the input interrupt polarity of GPIO[X] is active low
+ */
+int g_ak98_gpio_intpol(unsigned int pin, unsigned int level)
+{
+	void __iomem *base = AK98_GPIO_INTPOL_BASE(pin);
+	unsigned int offset = ((pin) & 31);
+	unsigned long flags;
+
+	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, invalid gpio %d!\n", pin);
+		return -1;
+	}
+	
+	local_irq_save(flags);
+	if (0 == level)
+		REG32(base) |= (1 << offset);
+	else
+		REG32(base) &= ~(1 << offset);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+ int g_ak98_gpio_to_irq(unsigned int pin)
+{
+	if(!gpio_assert_legal(pin) || (pin > GPIO_UPLIMIT)) {
+		panic("Error, invalid gpio %d!\n", pin);
+		return -1;
+	}
+	return (IRQ_GPIO_0 + (pin - AK98_GPIO_0));
+}
+
+
+ int g_ak98_irq_to_gpio(unsigned int irq)
+{
+	return (AK98_GPIO_0 + (irq - IRQ_GPIO_0));
+}
+
+
+#if 0
+static const char *ak98_gpio_list[AK98_GPIO_MAX];
+
+int ak98_gpio_request(unsigned long gpio, const char *label)
+{
+	if (gpio > GPIO_UPLIMIT)
+		return -EINVAL;
+	
+	if (ak98_gpio_list[gpio])
+		return -EBUSY;
+	
+	if (label)
+		ak98_gpio_list[gpio] = label;
+	else
+		ak98_gpio_list[gpio] = "busy";
+	
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_request);
+
+void ak98_gpio_free(unsigned long gpio)
+{
+	BUG_ON(!ak98_gpio_list[gpio]);
+	
+	ak98_gpio_list[gpio] = NULL;
+}
+EXPORT_SYMBOL(ak98_gpio_free);
+
+#else
+
+int ak98_gpio_request(unsigned long gpio, const char *label)
+{
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_request);
+
+void ak98_gpio_free(unsigned long gpio)
+{
+}
+EXPORT_SYMBOL(ak98_gpio_free);
+
+#endif
+
diff --git a/arch/arm/mach-ak98/clock.c b/arch/arm/mach-ak98/clock.c
new file mode 100644
index 00000000000..894761cd761
--- /dev/null
+++ b/arch/arm/mach-ak98/clock.c
@@ -0,0 +1,778 @@
+/*
+ * linux/arch/arm/mach-ak98/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/ak880x_addr.h>
+#include <mach/clock.h>
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#include <mach/regs-comm.h>
+
+
+/* clock information */
+
+static LIST_HEAD(clocks);
+
+DEFINE_MUTEX(clocks_mutex);
+
+/* enable and disable calls for use with the clk struct */
+
+static int clk_null_enable(struct clk *clk, int enable)
+{
+	return 0;
+}
+
+/* Clock API calls */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+	struct clk *p;
+	struct clk *clk = ERR_PTR(-ENOENT);
+	int idno;
+
+	if (dev == NULL || dev->bus != &platform_bus_type)
+		idno = -1;
+	else
+		idno = to_platform_device(dev)->id;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(p, &clocks, list) {
+		if (p->id == idno &&
+		    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
+			clk = p;
+			break;
+		}
+	}
+
+	/* check for the case where a device was supplied, but the
+	 * clock that was being searched for is not device specific */
+
+	if (IS_ERR(clk)) {
+		list_for_each_entry(p, &clocks, list) {
+			if (p->id == -1 && strcmp(id, p->name) == 0 &&
+			    try_module_get(p->owner)) {
+				clk = p;
+				break;
+			}
+		}
+	}
+
+	mutex_unlock(&clocks_mutex);
+	return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+	module_put(clk->owner);
+}
+
+int clk_enable(struct clk *clk)
+{
+
+	if (IS_ERR(clk) || clk == NULL)
+		return -EINVAL;
+
+ 	clk_enable(clk->parent);
+
+	mutex_lock(&clocks_mutex);
+	if ((clk->usage++) == 0)
+		(clk->enable) (clk, 1);
+ 
+	mutex_unlock(&clocks_mutex);
+
+	return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+	if (IS_ERR(clk) || clk == NULL)
+		return;
+
+	mutex_lock(&clocks_mutex);
+
+	if ((--clk->usage) == 0)
+		(clk->enable) (clk, 0);
+
+	mutex_unlock(&clocks_mutex);
+	clk_disable(clk->parent);
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (IS_ERR(clk))
+		return 0;
+
+	if (clk->rate != 0)
+		return clk->rate;
+
+	if (clk->get_rate != NULL)
+		return (clk->get_rate) (clk);
+
+	if (clk->parent != NULL)
+		return clk_get_rate(clk->parent);
+
+	return clk->rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	/* We do not default just do a clk->rate = rate as
+	 * the clock may have been made this way by choice.
+	 */
+
+	WARN_ON(clk->set_rate == NULL);
+
+	if (clk->set_rate == NULL)
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+	ret = (clk->set_rate) (clk, rate);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	return clk->parent;
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int ret = 0;
+
+	if (IS_ERR(clk))
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+
+	if (clk->set_parent)
+		ret = (clk->set_parent) (clk, parent);
+
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+
+EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_get_rate);
+EXPORT_SYMBOL(clk_set_rate);
+EXPORT_SYMBOL(clk_get_parent);
+EXPORT_SYMBOL(clk_set_parent);
+
+/* base clocks */
+
+int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+	clk->rate = rate;
+	return 0;
+}
+
+struct clk clk_xtal_12M = {
+	.name = "xtal_12M",
+	.id = -1,
+	.usage = 0,
+	.rate = 12 * MHz,
+	.parent = NULL,
+};
+
+struct clk clk_xtal_25M = {
+	.name = "xtal_25M",
+	.id = -1,
+	.usage = 0,
+	.rate = 25 * MHz,
+	.parent = NULL,
+};
+
+struct clk clk_xtal_27M = {
+	.name = "xtal_27M",
+	.id = -1,
+	.usage = 0,
+	.rate = 27 * MHz,
+	.parent = NULL,
+};
+
+struct clk clk_xtal_32K = {
+	.name = "xtal_32K",
+	.id = -1,
+	.usage = 0,
+	.rate = 32768,
+	.parent = NULL,
+};
+
+struct clk clk_pll = {
+	.name = "pll",
+	.id = -1,
+	.usage = 0,
+	.parent = NULL,
+	//.set_rate     = clk_pll_setrate,
+	//.get_rate     = clk_pll_getrate,
+};
+
+static int spll_clk_enable(struct clk *clk, int enable)
+{
+	if (enable) {
+		rMULFUN_CON1 &= ~(1UL << 30);
+		rMULFUN_CON1 &= ~(1UL << 31);
+		printk(KERN_DEBUG "CAMIF: pll2_clk_enable!\n");
+		
+	} else {
+		rMULFUN_CON1 |= (1UL << 30);
+		rMULFUN_CON1 |= (1UL << 31);
+		printk(KERN_DEBUG "CAMIF: pll2_clk_disable!\n");
+	}
+	
+	return 0;
+}
+
+struct clk clk_spll = {
+	.name = "spll",
+	.id = -1,
+	.usage = 0,
+	.parent = NULL,
+	.enable = spll_clk_enable,
+	//.set_rate     = clk_pll_setrate,
+	//.get_rate     = clk_pll_getrate,
+};
+
+
+struct clk clk_asic = {
+	.name = "asic_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll,
+};
+
+struct clk clk_cpu = {
+	.name = "cpu_clk",
+	.id = -1,
+	.usage = 0,
+	//.set_rate     = clk_cpu_setrate,
+	//.get_rate     = clk_cpu_getrate,
+};
+
+struct clk ap_clk = {
+	.name = "ap_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = NULL,
+};
+
+struct clk adc1_clk = {
+	.name = "adc1_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll,
+};
+
+struct clk adc2_clk = {
+	.name = "adc2_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_xtal_12M,
+};
+
+struct clk dac_clk = {
+	.name = "dac_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll,
+};
+
+/* camif clock */
+static int camif_clk_enable(struct clk *clk, int enable)
+{
+	if (enable) {
+		rCLK_CON1 &= ~(1UL << 8);
+		printk(KERN_DEBUG "CAMIF: camif_clk_enable!\n");
+	} else {
+		rCLK_CON1 |= (1UL << 8);
+		printk(KERN_DEBUG "CAMIF: camif_clk_disable!\n");
+	}	
+	
+	return 0;
+}
+
+/* cis clock */
+struct clk camif_clk = {
+	.name = "camif_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_spll,
+	.enable = camif_clk_enable,
+	//.set_rate     = clk_camif_setrate,
+	//.get_rate     = clk_camif_getrate,
+};
+
+
+/* i2c clock */
+static int i2c_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON2 &= ~(1UL << 5);
+	else
+		rCLK_CON2 |= (1UL << 5);
+	return 0;
+}
+
+struct clk i2c_clk = {
+	.name	= "i2c_clk",
+	.id		= -1,
+	.usage	= 0,
+	.parent = &clk_asic,
+	.enable = i2c_clk_enable,
+};
+
+/* mac clock */
+static int mac_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON2 &= ~(1UL << 14);
+	else
+		rCLK_CON2 |= (1UL << 14);
+
+	return 0;
+}
+
+struct clk mac_clk = {
+	.name	= "mac_clk",
+	.id		= -1,
+	.usage	= 0,
+	.parent = &clk_asic,
+	.enable = mac_clk_enable,
+};
+
+/* spi1 clock */
+static int spi1_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON1 &= ~(1 << 13);
+	else
+		rCLK_CON1 |= (1 << 13);
+
+	return 0;
+}
+
+struct clk spi1_clk = {
+	.name = "spi1_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = spi1_clk_enable,
+};
+
+/* spi2 clock */
+static int spi2_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON2 &= ~(1 << 7);
+	else
+		rCLK_CON2 |= (1 << 7);
+
+	return 0;
+}
+
+struct clk spi2_clk = {
+	.name = "spi2_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = spi2_clk_enable,
+};
+
+
+/* MMC/SD clock */
+static int mci_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON2 &= ~(1UL << 2);
+	else 
+		rCLK_CON2 |= (1UL << 2);
+	
+	return 0;
+}
+
+static unsigned long mci_get_rate(struct clk *c)
+{
+	/* return asic clock */
+	return clk_asic.rate;
+}
+
+struct clk mci_clk = {
+	.name = "mci_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = mci_clk_enable,
+	.get_rate = mci_get_rate,
+};
+
+/* MMC/SD clock */
+static int sdio_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON2 &= ~(1UL << 3);
+	else 
+		rCLK_CON2 |= (1UL << 3);
+	
+	return 0;
+}
+
+static unsigned long sdio_get_rate(struct clk *c)
+{
+	/* return asic clock */
+	return clk_asic.rate;
+}
+
+struct clk sdio_clk = {
+	.name = "sdio_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = sdio_clk_enable,
+	.get_rate = sdio_get_rate,
+};
+
+
+/* udc */
+static int udc_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON1 &= ~(1UL << 15);
+	else
+		rCLK_CON1 |= (1UL << 15);
+	return 0;
+}
+
+struct clk udc_clk = {
+	.name = "udc_clk",
+	.id = -1,
+	.usage = 0,
+ 	.parent = &clk_pll,
+	.enable = udc_clk_enable,
+};
+
+/* uart0 clk*/
+static int uart0_clk_enable(struct clk *clk, int enable)
+{
+	if (enable){
+		rCLK_CON1 &= ~(1UL << 12);
+ 	}
+	else
+		rCLK_CON1 |= (1UL << 12);
+
+	return 0;
+}
+
+struct clk uart0_clk = {
+	.name = "uart0_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_pll,
+	.enable = uart0_clk_enable,
+};
+
+/* lcd clk */
+static int lcd_clk_enable(struct clk *clk, int enable)
+{
+	if (enable)
+		rCLK_CON1 &= ~(1UL << 11);
+	else
+		rCLK_CON1 |= (1UL << 11);
+	return 0;
+}
+
+struct clk lcd_clk = {
+	.name = "lcd_clk",
+	.id = -1,
+	.usage = 0,
+	.parent = &clk_asic,
+	.enable = lcd_clk_enable,
+	//.set_rate     = pclk_setrate,
+	//.get_rate     = pclk_getrate,
+};
+
+
+/* initialise the clock system */
+
+int ak98_register_clock(struct clk *clk)
+{
+	clk->owner = THIS_MODULE;
+
+	if (clk->enable == NULL)
+		clk->enable = clk_null_enable;
+
+	/* add to the list of available clocks */
+	
+	mutex_lock(&clocks_mutex);
+	list_add(&clk->list, &clocks);
+	mutex_unlock(&clocks_mutex);
+	//printk("ak98_register_clock(),clk->name=%s\n",clk->name);
+
+	return 0;
+}
+
+int ak98_register_clocks(struct clk **clks, int nr_clks)
+{
+	int fails = 0;
+
+	for (; nr_clks > 0; nr_clks--, clks++) {
+		if (ak98_register_clock(*clks) < 0)
+			fails++;
+	}
+
+	return fails;
+}
+
+bool ak98_cpu_is_3x_mode(void)
+{
+	return ak98_get_cpu_mode() == CPU_MODE_CPU3X;
+}
+EXPORT_SYMBOL(ak98_cpu_is_3x_mode);
+
+bool ak98_cpu_is_2x_mode(void)
+{
+	if (ak98_cpu_is_3x_mode())
+		return false;
+
+	return __raw_readl(AK98_VA_SYSCTRL + 0x0004) & AK98_CLK_DIV_1_CPU2X;
+}
+EXPORT_SYMBOL(ak98_cpu_is_2x_mode);
+
+
+bool ak98_cpu_is_special_mode(void)
+{
+	if (ak98_cpu_is_3x_mode())
+		return false;
+
+	return __raw_readl(AK98_VA_SYSCTRL + 0x0004) & AK98_CLK_DIV_1_SPECIAL;
+}
+EXPORT_SYMBOL(ak98_cpu_is_special_mode);
+
+bool ak98_cpu_is_low_clock_mode(void)
+{
+	if (ak98_cpu_is_3x_mode())
+		return false;
+
+	return __raw_readl(AK98_VA_SYSCTRL + 0x0004) & AK98_CLK_DIV_1_LOW;
+}
+EXPORT_SYMBOL(ak98_cpu_is_low_clock_mode);
+
+bool ak98_cpu_is_normal_mode(void)
+{
+	return ak98_get_cpu_mode() == CPU_MODE_NORMAL;
+}
+EXPORT_SYMBOL(ak98_cpu_is_normal_mode);
+
+ak98_cpu_mode_t ak98_get_cpu_mode(void)
+{
+	unsigned long clk_div_1 = __raw_readl(AK98_VA_SYSCTRL + 0x0004);
+
+	if (clk_div_1 & AK98_CLK_DIV_1_CPU3X)
+		return CPU_MODE_CPU3X;
+	else if (clk_div_1 & AK98_CLK_DIV_1_LOW)
+		return CPU_MODE_LOW;
+	else if (clk_div_1 & AK98_CLK_DIV_1_SPECIAL)
+		return CPU_MODE_SPECIAL;
+
+	return CPU_MODE_NORMAL;
+}
+EXPORT_SYMBOL(ak98_get_cpu_mode);
+
+unsigned long ak98_get_pll_clk(void)
+{
+	unsigned long clk = 0UL;
+	unsigned long clk_div_1 = __raw_readl(AK98_VA_SYSCTRL + 0x0004);
+	unsigned long pll_sel = clk_div_1 & 0x3F;
+
+	clk = AK98_MIN_PLL_CLK + pll_sel * 4 * MHz;
+	
+	return clk;
+}
+EXPORT_SYMBOL(ak98_get_pll_clk);
+
+
+unsigned long ak98_get_clk168m_clk(void)
+{
+	unsigned long clk = 0UL;
+	unsigned long clk_div_1 = __raw_readl(AK98_VA_SYSCTRL + 0x0004);
+	unsigned long clk168_div = (clk_div_1 >> 17) & 0xF;
+
+	clk = ak98_get_pll_clk() / (clk168_div + 1);
+	
+	return clk;
+}
+EXPORT_SYMBOL(ak98_get_clk168m_clk);
+
+
+unsigned long ak98_get_asic_clk(void)
+{
+	unsigned long clk = 0UL;
+	unsigned long clk_div_1 = __raw_readl(AK98_VA_SYSCTRL + 0x0004);
+	unsigned long asic_div = (clk_div_1 >> 6) & 0x7;
+
+	if (asic_div == 0)
+		asic_div = 1;
+
+	if (ak98_cpu_is_3x_mode())
+		clk = ak98_get_clk168m_clk() / 3;
+	else if (ak98_cpu_is_special_mode() && !ak98_cpu_is_low_clock_mode())
+		clk = ak98_get_clk168m_clk() * 2 / 5;
+	else
+		clk = ak98_get_clk168m_clk() >> asic_div;
+	
+	return clk;
+}
+EXPORT_SYMBOL(ak98_get_asic_clk);
+
+unsigned long ak98_get_mem_clk(void)
+{
+	unsigned long clk = 0UL;
+	unsigned long clk_div_1 = __raw_readl(AK98_VA_SYSCTRL + 0x0004);
+	unsigned long mem_div = (clk_div_1 >> 9) & 0x7;
+
+	if (mem_div == 0)
+		mem_div = 1;
+	
+	if (ak98_cpu_is_3x_mode())
+		clk = ak98_get_clk168m_clk() / 3;
+	else
+		clk = ak98_get_clk168m_clk() >> mem_div;
+
+	
+	return clk;
+}
+EXPORT_SYMBOL(ak98_get_mem_clk);
+
+
+unsigned long ak98_get_cpu_clk(void)
+{
+	if (ak98_cpu_is_3x_mode() || ak98_cpu_is_2x_mode())
+		return ak98_get_clk168m_clk();
+	else if (ak98_cpu_is_low_clock_mode())
+		return ak98_get_asic_clk();
+	else return ak98_get_mem_clk();
+}
+EXPORT_SYMBOL(ak98_get_cpu_clk);
+
+
+/* initalise all the clocks */
+
+static int __init ak98_init_clocks(void)
+{
+	printk(KERN_INFO "ANYKA AK98 Clocks, (c) 2010 ANYKA \n");
+
+#if defined(CONFIG_AK9801_ATHENA) || defined(CONFIG_AK9805_TV908)
+
+	/*
+	* We assume that AK98xx EBOOK and AK98xx EPC board use the same clock settings.
+	* May need to be changed in the future.
+	*/
+ 	clk_default_setrate(&clk_pll, ak98_get_pll_clk());
+	clk_default_setrate(&clk_asic, ak98_get_asic_clk());
+	clk_default_setrate(&clk_cpu, ak98_get_cpu_clk());
+
+	printk("AK98: PLL %ld MHz, ASIC %ld MHz, CPU Core %ld MHz,"
+		"MEM %ld MHz\n", clk_pll.rate / MHz, clk_asic.rate / MHz, 
+			clk_cpu.rate / MHz, ak98_get_mem_clk() / MHz);
+#endif
+
+	/* register our clocks */
+
+	if (ak98_register_clock(&clk_xtal_12M) < 0)
+		printk(KERN_ERR "failed to register 12M xtal\n");
+
+	if (ak98_register_clock(&clk_xtal_25M) < 0)
+		printk(KERN_ERR "failed to register 25M xtal\n");
+
+	if (ak98_register_clock(&clk_xtal_27M) < 0)
+		printk(KERN_ERR "failed to register 27M xtal\n");
+
+	if (ak98_register_clock(&clk_xtal_32K) < 0)
+		printk(KERN_ERR "failed to register 32K xtal\n");
+
+	if (ak98_register_clock(&clk_pll) < 0)
+		printk(KERN_ERR "failed to register pll\n");
+
+	if (ak98_register_clock(&clk_asic) < 0)
+		printk(KERN_ERR "failed to register asic clk\n");
+
+	if (ak98_register_clock(&clk_cpu) < 0)
+		printk(KERN_ERR "failed to register cpu clk\n");
+
+	if (ak98_register_clock(&spi1_clk) < 0)
+		printk(KERN_ERR "failed to register spi clk\n");
+
+	if (ak98_register_clock(&spi2_clk) < 0)
+		printk(KERN_ERR "failed to register spi clk\n");
+
+	if (ak98_register_clock(&mci_clk) < 0)
+		printk(KERN_ERR "failed to register mci clk\n");
+
+	if (ak98_register_clock(&sdio_clk) < 0)
+		printk(KERN_ERR "failed to register sdio clk\n");
+
+	if (ak98_register_clock(&udc_clk) < 0)
+		printk(KERN_ERR "failed to register udc clk\n");
+
+	if (ak98_register_clock(&uart0_clk) < 0)
+		printk(KERN_ERR "failed to register uart0 clk\n");
+
+	if (ak98_register_clock(&lcd_clk) < 0)
+		printk(KERN_ERR "failed to register lcd clk\n");
+
+	if (ak98_register_clock(&i2c_clk) < 0)
+		printk(KERN_ERR "failed to register i2c clk\n");
+
+	if (ak98_register_clock(&mac_clk) < 0)
+		printk(KERN_ERR "failed to register mac clk\n");
+
+	if (ak98_register_clock(&camif_clk) < 0)
+		printk(KERN_ERR "failed to register camif clk\n");
+
+
+	/*
+	 * Enable L2/RAM clock by default, Disable all other clocks.
+	 */
+	__raw_writel(0xFBF7, AK98_VA_SYSCTRL + 0x0C);
+
+	clk_enable(&uart0_clk);
+
+	printk("clk control: 0x%08X\n", __raw_readl(AK98_VA_SYSCTRL + 0x0C));
+
+	return 0;
+}
+
+arch_initcall(ak98_init_clocks);
+
diff --git a/arch/arm/mach-ak98/cpu.c b/arch/arm/mach-ak98/cpu.c
new file mode 100644
index 00000000000..65e66694aa6
--- /dev/null
+++ b/arch/arm/mach-ak98/cpu.c
@@ -0,0 +1,56 @@
+/*
+ * init cpu freq, clock
+ *
+ * report cpu id
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/l2cache.h>
+#include <asm/io.h>
+
+#define IODESC_ENT(x) { (unsigned long)AK98_VA_##x, __phys_to_pfn(AK98_PA_##x), AK98_SZ_##x, MT_DEVICE }
+
+static struct map_desc ak98_iodesc[] __initdata = {
+	IODESC_ENT(SYSCTRL),
+	IODESC_ENT(SUBCTRL),
+	IODESC_ENT(L2MEM),
+	IODESC_ENT(USB),
+};
+
+void __init ak98_map_io(void)
+{
+	unsigned long idcode = 0x0;
+
+	/* initialise the io descriptors we need for initialisation */
+	iotable_init(ak98_iodesc, ARRAY_SIZE(ak98_iodesc));
+
+	idcode = __raw_readl(AK98_VA_SYSCTRL + 0x00);
+
+	if (idcode == 0x20090C00) {
+#if defined(CONFIG_AK9801_ATHENA)
+		printk("ANYKA CPU %s (id 0x%lx)\n", "AK9801", idcode);
+#elif defined(CONFIG_AK9805_TV908)
+		printk("ANYKA CPU %s (id 0x%lx)\n", "AK9805", idcode);
+#elif defined(CONFIG_AK9805_MP5)
+		printk("ANYKA CPU %s (id 0x%lx)\n", "AK9805", idcode);
+#else
+#error AK98xx Board NOT supported
+#endif
+	}
+	else
+		panic("Unknown ANYKA CPU id: 0x%lx\n", idcode);
+
+	ak98_l2cache_init();
+	ak98_l2cache_invalidate();
+}
+
diff --git a/arch/arm/mach-ak98/cpu.h b/arch/arm/mach-ak98/cpu.h
new file mode 100644
index 00000000000..3b02d1224b6
--- /dev/null
+++ b/arch/arm/mach-ak98/cpu.h
@@ -0,0 +1,5 @@
+
+struct sys_timer;
+extern struct sys_timer ak98_timer;
+
+void __init ak98_map_io(void);
diff --git a/arch/arm/mach-ak98/cpufreq.c b/arch/arm/mach-ak98/cpufreq.c
new file mode 100755
index 00000000000..3fb30a034ee
--- /dev/null
+++ b/arch/arm/mach-ak98/cpufreq.c
@@ -0,0 +1,657 @@
+/* arch/arm/mach-ak98/cpufreq.c
+ *
+ * AK98 CPUfreq Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/anyka_cpufreq.h>
+#include <linux/dma-mapping.h>
+#include <linux/freezer.h>
+#include <linux/syscalls.h>
+
+#include <mach/cpufreq.h>
+#include <mach/clock.h>
+
+#define SIZE_1K 0x00000400      /* 1K */
+extern atomic_t suspend_flags;
+
+static struct cpufreq_freqs freqs;
+static T_OPERATION_MODE current_mode;
+static int previous_mode_flag;
+static int cpufreq_in_ddr2 = 1;
+static unsigned int clkdiv = 1000000;
+
+#if 1
+struct cpufreq_mode_clkdiv cpufreq_divs[] = {
+	//mode_name  pll_sel  clk168_div  cpu_div  mem_div  asic_div  low_clock is_3x  (cpu,mem,asic[MHz])
+	{LOW_MODE_CLOCK_0, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_1, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_2, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_3, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_4, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_5, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_6, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */
+	{LOW_MODE_CLOCK_7, 	0x37,	0,	0,	2,	4,	1,	0}, /* (100,200,100) */ 
+	
+	{NORMAL_MODE_CLOCK_0, 0x37,	 0,	0,	2,	4,	0,	0}, /* (200,200,100) */
+	{NORMAL_MODE_CLOCK_1, 0x37,	 0,	0,	2,	4,	0,	0}, /* (200,200,100) */
+	{NORMAL_MODE_CLOCK_2, 0x37,  0,	0,	2,	4, 	0,	0}, /* (200,200,100) */
+	{NORMAL_MODE_CLOCK_3, 0x37,  0,	0,	2,	4,	0,	0}, /* (200,200,100) */
+	{NORMAL_MODE_CLOCK_4, 0x37,  0,	0,	2,	4, 	0,	0}, /* (200,200,100) */
+	{NORMAL_MODE_CLOCK_5, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{NORMAL_MODE_CLOCK_6, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{NORMAL_MODE_CLOCK_7, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */    
+
+	{VIDEO_MODE_CLOCK_0, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_1, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_2, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_3, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_4, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_5, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_6, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+	{VIDEO_MODE_CLOCK_7, 0x37,  0,	1,	2,	4, 	0,	0}, /* (400,200,100) */
+};
+#else
+struct cpufreq_mode_clkdiv cpufreq_divs[] = {
+    //mode_name  pll_sel  clk168_div  cpu_div  mem_div  asic_div  low_clock is_3x  (cpu,mem,asic[MHz])
+    {LOW_MODE_CLOCK_0,  0x14,   0,  0,  2,  4,  1,  0}, /* (65,130,65) */
+    {LOW_MODE_CLOCK_1,  0x14,   0,  0,  2,  4,  1,  0}, /* (65,130,65) */
+    {LOW_MODE_CLOCK_2,  0x14,   0,  0,  2,  4,  0,  0}, /* (130,130,65) */
+    {LOW_MODE_CLOCK_3,  0x14,   0,	0,  2,  4,  0,  0}, /* (130,130,65) */
+    {LOW_MODE_CLOCK_4,  0x14,   0,  0,  2,  2,  0,  0}, /* (130,130,130) */
+    {LOW_MODE_CLOCK_5,  0x14,   0,  0,  2,  2,  0,  0}, /* (130,130,130) */
+    {LOW_MODE_CLOCK_6,  0x14,   0,  1,  2,  2,  0,  0}, /* (260,130,130) */
+    {LOW_MODE_CLOCK_7,  0x14,   0,  1,  2,  2,  0,  0}, /* (260,130,130) */
+
+    {NORMAL_MODE_CLOCK_0, 0x37,  0, 0,  2,  4,  0,  0}, /* (200,200,100) */
+    {NORMAL_MODE_CLOCK_1, 0x37,  0, 0,  2,  4,  0,  0}, /* (200,200,100) */
+    {NORMAL_MODE_CLOCK_2, 0x37,  0, 0,  2,  4,  0,  0}, /* (200,200,100) */
+    {NORMAL_MODE_CLOCK_3, 0x37,  0, 0,  2,  4,  0,  0}, /* (200,200,100) */
+    {NORMAL_MODE_CLOCK_4, 0x37,  0, 0,  2,  4,  0,  0}, /* (200,200,100) */
+    {NORMAL_MODE_CLOCK_5, 0x37,  0, 1,  2,  4,  0,  0}, /* (400,200,100) */
+    {NORMAL_MODE_CLOCK_6, 0x37,  0, 1,  2,  4,  0,  0}, /* (400,200,100) */
+    {NORMAL_MODE_CLOCK_7, 0x37,  0, 1,  2,  4,  0,  0}, /* (400,200,100) */
+
+    {VIDEO_MODE_CLOCK_0, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_1, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_2, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_3, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_4, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_5, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_6, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+    {VIDEO_MODE_CLOCK_7, 0x36,  0,  1,  0,  0,  0,  1}, /* (396,132,132) */
+};
+#endif
+
+static T_OPERATION_MODE prev_suspend_mode;
+#define SUSPEND_NORMAL_MODE		NORMAL_MODE_CLOCK_2
+
+#define CPU_FREQ_CHANGING(ratio) do {\
+	/* change cpu frequence, and first close 2x mode then open 2x mode */\
+    REG32(CLOCK_DIV_REG) = ratio & (~(1 << 15));\
+    udelay(10);\
+	REG32(CLOCK_DIV_REG) |= (ratio & (1 << 15));\
+} while(0)
+
+static int get_cpufreq_mode_clkdiv(T_OPERATION_MODE mode, struct cpufreq_mode_clkdiv *clkdiv)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(cpufreq_divs); i++) {
+		if (cpufreq_divs[i].mode_name == mode) {
+			*clkdiv = cpufreq_divs[i];
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static unsigned int calcue_power(unsigned int num)
+{
+    unsigned int i;
+
+    if(num < 0)
+        return -1;
+    if((num == 2)||(num == 0))
+        return 0;
+
+    for(i = 0; num % 2 == 0; i++){
+        num /= 2;
+    }
+    if(num > 2)
+        return -1;
+
+    return i;
+}
+
+static void config_clock_parameter(struct cpufreq_mode_clkdiv *cpufreq,
+	unsigned long *ratio)
+{
+	unsigned long clk_ratio = *ratio;
+	unsigned int memdiv, asicdiv;
+
+	memdiv = calcue_power(cpufreq->mem_div);
+	if( memdiv < 0)
+		printk("Error, calcue mem_div.");
+	asicdiv = calcue_power(cpufreq->asic_div);
+	if( asicdiv < 0)
+		printk("Error, calcue asic_div.");
+	
+	clk_ratio &= ~((1 << 28)|(1 << 22)|(0xF << 17)|(1 << 15)|(0x7 << 9)|(0x7 << 6)|(0x3F << 0));
+
+	clk_ratio |= (cpufreq->is_3x << 28);		//is 3x ?
+	clk_ratio |= (cpufreq->clk168_div << 17);	//clk168 div
+	clk_ratio |= (cpufreq->cpu_div << 15);		//cpu clk = mem clk or cpu clk = asic clk
+	clk_ratio |= (cpufreq->low_clock << 22);	//cpu clk = asic clk
+	clk_ratio |= (memdiv << 9)|(asicdiv << 6);	//mem div and asic div
+	clk_ratio |= (cpufreq->pll_sel << 0);		//pll_sel
+	
+	*ratio = clk_ratio;
+}
+
+/*
+ *  *function: enter L2 modify register parameters of clock for change sys clcok
+ *   */
+void L2_LINK(freqchange) L2FUNC_NAME(freqchange)(unsigned long param1,
+	unsigned long param2,unsigned long param3,unsigned long param4)
+{
+	DISABLE_CACHE_MMU();
+	DDR2_ENTER_POWERDOWN();
+	// after send enter self - refresh, delay stable clock at least more than 1 tck
+	PM_DELAY(0x200);
+
+	//disable ram clock
+	REG32(PHY_CLOCK_CTRL_REG) |= (1<<10);
+
+	// other mode change to normal mode
+	//cpu clock from other mode to normal
+	REG32(PHY_CLOCK_DIV_REG) &= ~((1 << 28)|(1 << 22));
+	PM_DELAY(0x100);
+
+	//set clock div and check pll[12]
+	REG32(PHY_CLOCK_DIV_REG) = param1 &(~(1<<15)); // close cpu2x
+	while (REG32(PHY_CLOCK_DIV_REG) & PLL_CHANGE_ENA);
+
+	REG32(PHY_CLOCK_DIV_REG) |= (param1&(1<<15)); // open cpu2x
+
+	//enable ram clock
+	REG32(PHY_CLOCK_CTRL_REG) &= ~(1<<10);
+	// new clock stable at least more than 1tck,here is ignore because follow has few instruction.
+
+	// softreset ddr2 memory controller
+	REG32(0x0800000c) |= (0x1 << 26);
+	REG32(0x0800000c) &= ~(0x1 << 26);
+
+	// re-init ram controller
+	REG32(0x2000e05c) = 0x00000200; // bypass DCC
+	REG32(0x2000e078) = 0x40020100; // initial sstl = 00(12ma), tsel = 10(150ohm)
+	REG32(0x2000e000) = 0x00004e90; // 32 bit bus width
+
+    // exit precharge power-down mode before delay at least 1 tck
+    PM_DELAY(10);
+    DDR2_EXIT_POWERDOWN();
+
+    // load mr, reset dll and delay for 200 tck, and set odt high
+    REG32(PHY_RAM_CPU_CMD) = 0x02800532;
+    // send nop, delay for 200 tck for dll reset,
+    REG32(PHY_RAM_CPU_CMD) = 0x02f00000;
+    PM_DELAY(0x100);
+
+    // load mr, clean reset dll and remain odt low in ddr2 memory
+    REG32(PHY_RAM_CPU_CMD) = 0x0a800432;
+
+    // open auto-referesh
+    // default as mclk = 120mhz for calc tck=8.3ns, trefi=7.7us
+    REG32(0x2000e00c) = (0x39f<<1)|0x1;
+
+    //enable dll and wate for dll stable in ram controller
+    REG32(0x2000e020) = 0x00000003;
+    while (!(REG32(0x2000e020) & (1 << 2)));
+
+    //calibration sart and wait for finish
+    REG32(0x2000e024) = ((param2>>0x7)<<10)|0x1;
+    while (!(REG32(0x2000e024) & (1 << 1)));
+
+    ENABLE_CACHE_MMU();
+}
+
+/*
+ *function: change pll clock, include mem clock,asic clock and cpu clock.
+ */
+static void cpufreq_change_clocks(struct cpufreq_mode_clkdiv *cpufreq)
+{
+    unsigned long ratio;
+    void *addr;
+    unsigned long phy_addr;
+	
+    addr = kzalloc(512, GFP_KERNEL | GFP_ATOMIC);
+    if (addr == NULL)
+        return ;
+    phy_addr = virt_to_phys(addr);
+	
+    ratio = REG32(CLOCK_DIV_REG);
+    config_clock_parameter(cpufreq, &ratio);
+    ratio |= (PLL_CHANGE_ENA);
+	
+    SPECIFIC_L2BUF_EXEC(freqchange, ratio, phy_addr,0,0);
+	
+    kfree(addr);
+}
+
+/*
+ *function: according to needed new clocks and determine branch of cpufreq
+ * @cpufreq: structure include mode name and clock div
+ * note: the mode enter L2 cpufreq
+ */
+static int l2_cpu_freq_change(struct cpufreq_mode_clkdiv *cpufreq)
+{
+	int error;
+	
+	error = usermodehelper_disable();
+	if (error)
+		goto Finish;
+
+	// freeze process and kernel task.
+	error = cpufreq_freeze_processes();
+	if (error)
+		goto freeze;
+	
+	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+	cpufreq_change_clocks(cpufreq);
+	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+	
+freeze:
+	thaw_processes();
+Finish:
+	usermodehelper_enable();
+	return error;
+}
+
+
+/*
+ *function: according to needed new clocks and determine branch of cpufreq
+ * @cpufreq: structure include mode name and clock div
+ * note: the mode cpufreq in ddr2
+ */
+static void ddr2_cpu_freq_change(struct cpufreq_mode_clkdiv *cpufreq)
+{
+    unsigned long ratio,tmp;
+	
+    cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	// check if cpu clock from other mode to normal and cutover to normal
+	if((freqs.old_cpufreq.low_clock == 1) && (cpufreq->low_clock == 0)) {
+		REG32(CLOCK_DIV_REG) &= ~((1 << 28)|(1 << 22));
+		//tmp = REG32(CPU_CHIP_ID);
+		udelay(100);
+	}
+	
+    ratio = REG32(CLOCK_DIV_REG);
+    config_clock_parameter(cpufreq, &ratio);
+	if (freqs.old_cpufreq.asic_clk != freqs.new_cpufreq.asic_clk)
+		ratio |= CLOCK_ASIC_MEM_ENA;
+
+	//change cpu frequence
+    CPU_FREQ_CHANGING(ratio);
+
+    cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+}
+
+static void cpu_freq_change(struct cpufreq_mode_clkdiv *cpufreq)
+{
+	if (freqs.old_cpufreq.pll_sel == freqs.new_cpufreq.pll_sel) {
+		ddr2_cpu_freq_change(cpufreq);
+		cpufreq_in_ddr2 = 1;
+	} else {
+		l2_cpu_freq_change(cpufreq);
+		cpufreq_in_ddr2 = 0;
+	}
+}
+
+/*
+ * change from low mode to normal mode for suspend (low mode --> normal mode)
+ */
+void cpu_freq_suspend_check(void)
+{
+	struct cpufreq_mode_clkdiv cpufreq;
+	unsigned long ratio;
+	
+	if (freqs.old_cpufreq.low_clock == 1) {
+
+		// save low mode before suspend change normal
+		prev_suspend_mode = current_mode;
+		
+		if(!get_cpufreq_mode_clkdiv(SUSPEND_NORMAL_MODE, &cpufreq)){
+
+			if (cpufreq_in_ddr2) {
+				// first change to normal mode when other mode change to normal mode
+				REG32(CLOCK_DIV_REG) &= ~((1 << 28)|(1 << 22));
+				udelay(100);
+				
+				ratio = REG32(CLOCK_DIV_REG);
+				config_clock_parameter(&cpufreq, &ratio);
+
+				// change cpu frequence
+				CPU_FREQ_CHANGING(ratio);
+			} else {
+				cpufreq_change_clocks(&cpufreq);
+			}
+		}
+	}
+}
+EXPORT_SYMBOL(cpu_freq_suspend_check);
+
+/*
+ * restore low mode after resume (normal mode --> low mode)
+ */
+void cpu_freq_resume_check(void)
+{
+	struct cpufreq_mode_clkdiv cpufreq;
+	unsigned long ratio;
+
+	if (freqs.old_cpufreq.low_clock == 1) {
+		if(!get_cpufreq_mode_clkdiv(prev_suspend_mode, &cpufreq)){
+			if (cpufreq_in_ddr2) {
+				ratio = REG32(CLOCK_DIV_REG);
+				config_clock_parameter(&cpufreq, &ratio);
+
+				//change cpu frequence
+				CPU_FREQ_CHANGING(ratio);
+			} else {
+				cpufreq_change_clocks(&cpufreq);
+			}
+		}
+	}
+}
+EXPORT_SYMBOL(cpu_freq_resume_check);
+
+static void info_clock_value(void)
+{
+	printk("Cpufreq: system clocks(unit:MHz)[cpu,mem,asic] from (%d,%d,%d) to (%d,%d,%d)\n",
+		freqs.old_cpufreq.cpu_clk/clkdiv, freqs.old_cpufreq.mem_clk/clkdiv,
+		freqs.old_cpufreq.asic_clk/clkdiv, freqs.new_cpufreq.cpu_clk/clkdiv, 
+		freqs.new_cpufreq.mem_clk/clkdiv, freqs.new_cpufreq.asic_clk/clkdiv);
+}
+
+static int clock_need_changing(void)
+{
+	if((freqs.new_cpufreq.cpu_clk == freqs.old_cpufreq.cpu_clk)&&
+	  (freqs.new_cpufreq.mem_clk == freqs.old_cpufreq.mem_clk)&&
+	  (freqs.new_cpufreq.asic_clk == freqs.old_cpufreq.asic_clk))
+		return 0;
+	else
+		return 1;
+}
+
+static unsigned int get_asic_clk(struct cpufreq_mode_clkdiv *cpufreq)
+{
+    unsigned int asicclk;
+
+    if(cpufreq->is_3x)
+        asicclk = ((PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1))/3;
+    else
+        asicclk = ((PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1))/cpufreq->asic_div;
+
+    return asicclk;
+}
+
+static unsigned int get_mem_clk(struct cpufreq_mode_clkdiv *cpufreq)
+{
+	unsigned int memclk;
+	
+    if(cpufreq->is_3x)
+        memclk = ((PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1))/3;
+    else
+        memclk = ((PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1))/cpufreq->mem_div;
+
+    return memclk;
+}
+
+static unsigned int get_cpu_clk(struct cpufreq_mode_clkdiv *cpufreq)
+{
+    unsigned int cpuclk;
+
+    if(cpufreq->is_3x) {
+        cpuclk = (PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1);
+    } else {
+        if(cpufreq->cpu_div) {
+            cpuclk = (PLL_CLK_MIN+(cpufreq->pll_sel*4))/(cpufreq->clk168_div+1);
+        } else {
+            if(cpufreq->low_clock)
+                cpuclk = get_asic_clk(cpufreq);
+            else
+                cpuclk = get_mem_clk(cpufreq);
+        }
+    }
+	
+    return cpuclk;
+}
+
+static void update_current_clock(void)
+{
+    freqs.old_cpufreq.cpu_clk = freqs.new_cpufreq.cpu_clk;
+    freqs.old_cpufreq.mem_clk = freqs.new_cpufreq.mem_clk;
+    freqs.old_cpufreq.asic_clk = freqs.new_cpufreq.asic_clk;
+	freqs.old = freqs.new;
+    freqs.old_cpufreq.pll_sel = freqs.new_cpufreq.pll_sel;
+	freqs.old_cpufreq.low_clock = freqs.new_cpufreq.low_clock;
+}
+
+static void get_newmode_clock(struct cpufreq_mode_clkdiv *cpufreq)
+{	
+	freqs.new_cpufreq.cpu_clk = get_cpu_clk(cpufreq)*clkdiv;
+	freqs.new_cpufreq.mem_clk = get_mem_clk(cpufreq)*clkdiv;
+	freqs.new_cpufreq.asic_clk = get_asic_clk(cpufreq)*clkdiv;
+	freqs.new = freqs.new_cpufreq.cpu_clk;	
+	freqs.new_cpufreq.pll_sel = cpufreq->pll_sel;
+	freqs.new_cpufreq.low_clock = cpufreq->low_clock;
+}
+
+void update_pre_mode(void)
+{
+	// assign to save old mode
+	previous_mode_flag = freqs.old_cpufreq.low_clock;
+}
+
+unsigned int get_pll_sel(T_OPERATION_MODE state)
+{
+    int i, len;
+
+    len = ARRAY_SIZE(cpufreq_divs);
+    for (i = 0; i < len; i++) {
+        if (state == cpufreq_divs[i].mode_name)
+            break;
+    }
+    if (likely(i < len))
+        return cpufreq_divs[i].pll_sel;
+
+    return -1;
+}
+EXPORT_SYMBOL(get_pll_sel);
+
+int previous_mode_is_low_mode(void)
+{
+	return previous_mode_flag;
+}
+EXPORT_SYMBOL(previous_mode_is_low_mode);
+
+int current_mode_is_low_mode(void)
+{
+	return freqs.old_cpufreq.low_clock;
+}
+EXPORT_SYMBOL(current_mode_is_low_mode);
+
+/*
+ *function: get system boot's mode
+ */
+T_OPERATION_MODE get_current_mode(void)
+{
+	return current_mode;
+}
+EXPORT_SYMBOL(get_current_mode);
+
+/* function: enter change cpufreq
+ * @state: requested mode name
+ * return:
+ * 	-1: if system init mode is not surpport.
+ * 	  0: if cpufreq change successful.
+ */
+int request_cpufreq_enter(T_OPERATION_MODE state)
+{
+	int i, len;
+
+	// check if request suspending, prevent cpufreq when suspending
+	if (atomic_read(&suspend_flags))
+		return 0;
+
+	if (state == current_mode) {
+		//printk("requset new mode equal to current mode.\n");
+		return 0;
+	}
+
+	len = ARRAY_SIZE(cpufreq_divs);
+	for (i = 0; i < len; i++) {
+		if (state == cpufreq_divs[i].mode_name)
+			break;
+	}
+	if (likely(i < len)) {
+		get_newmode_clock(&cpufreq_divs[i]);
+		update_pre_mode();
+		
+		if (!clock_need_changing()) {
+			//printk("Cpufreq: new mode clocks equal to old mode clocks, exit changing.\n");
+			return 0;
+		}
+		cpu_freq_change(&cpufreq_divs[i]);
+	} else {
+		printk("requset new mode is not surpport.\n");
+		return -1;
+	}
+	
+	info_clock_value();
+	update_current_clock();
+	current_mode = state;
+
+	return 0;
+}
+EXPORT_SYMBOL(request_cpufreq_enter);
+
+/*
+ * function: get system boot's mode
+ */
+static int get_init_mode(void)
+{
+    int i;
+    unsigned int pllclk, clk168, cpuclk, memclk, asicclk;
+    unsigned int pllsel, clk168div, cpudiv, memdiv, asicdiv, lowclock;
+
+    pllclk = ak98_get_pll_clk()/clkdiv;
+    clk168 = ak98_get_clk168m_clk()/clkdiv;
+    cpuclk = freqs.old_cpufreq.cpu_clk/clkdiv;
+    memclk = freqs.old_cpufreq.mem_clk/clkdiv;
+    asicclk = freqs.old_cpufreq.asic_clk/clkdiv;
+    pllsel = ((pllclk - PLL_CLK_MIN)/4) & 0x3f;
+
+    if(pllclk == clk168)
+        clk168div = 0;
+    else
+        clk168div = pllclk/clk168;
+	
+	//system is 3x mode
+    if((cpuclk / memclk == 3)&&(cpuclk / asicclk == 3)&&
+       (cpuclk % memclk == 0)&&(cpuclk % asicclk == 0)) {
+        for(i = 0; i < ARRAY_SIZE(cpufreq_divs); i++) {
+            if((cpufreq_divs[i].is_3x == 1) &&
+              (cpufreq_divs[i].clk168_div == clk168div) &&
+              (cpufreq_divs[i].pll_sel == pllsel)){
+
+                current_mode = cpufreq_divs[i].mode_name;
+				freqs.old_cpufreq.low_clock = cpufreq_divs[i].low_clock;
+                return 0;
+            }
+        }
+        return -1;
+    }
+
+	//system is normal mode
+	if(cpuclk == clk168) {
+		lowclock = 0;
+		cpudiv = 1;
+	} else if(cpuclk == memclk) {
+		lowclock = 0;
+		cpudiv = 0;
+	} else if(cpuclk == asicclk) {
+		lowclock = 1;
+		cpudiv = 0;
+	}
+	memdiv = clk168/memclk;
+	asicdiv = clk168/asicclk;
+
+	for(i = 0;	i < ARRAY_SIZE(cpufreq_divs); i++){
+		if((cpufreq_divs[i].cpu_div == cpudiv)	&&
+		  (cpufreq_divs[i].low_clock == lowclock)&&
+		  (cpufreq_divs[i].mem_div == memdiv)	&&
+		  (cpufreq_divs[i].asic_div == asicdiv) &&
+		  (cpufreq_divs[i].pll_sel == pllsel)	&&
+		  (cpufreq_divs[i].clk168_div == clk168div)){
+
+			current_mode = cpufreq_divs[i].mode_name;
+			freqs.old_cpufreq.low_clock = cpufreq_divs[i].low_clock;
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static void cpufreq_operation_init(void)
+{
+    int i, error;
+    unsigned int tmp;
+
+    freqs.old_cpufreq.cpu_clk = ak98_get_cpu_clk();
+    freqs.old_cpufreq.mem_clk = ak98_get_mem_clk();
+    freqs.old_cpufreq.asic_clk = ak98_get_asic_clk();
+    freqs.old = freqs.old_cpufreq.cpu_clk;
+
+    freqs.flags = 0;
+
+    tmp = cpufreq_divs[0].pll_sel;
+    for(i = 1; i < ARRAY_SIZE(cpufreq_divs); i++){
+        if(cpufreq_divs[i].pll_sel > tmp)
+            tmp = cpufreq_divs[i].pll_sel;
+    }
+    freqs.old_cpufreq.pll_sel = tmp;
+	
+	error = get_init_mode();
+	if(error < 0)
+		current_mode = error;
+
+    return;
+}
+
+/* ak98_cpufreq_init
+ *
+ * Attach the cpu frequence  scaling functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+int __init ak98_cpufreq_init(void)
+{
+	printk("AK98 cpu frequence change support, (c) 2011 ANYAK\n");
+	cpufreq_operation_init();
+
+	return 0;
+}
+module_init(ak98_cpufreq_init);
+
diff --git a/arch/arm/mach-ak98/ddr2change.c b/arch/arm/mach-ak98/ddr2change.c
new file mode 100755
index 00000000000..e472b147d7d
--- /dev/null
+++ b/arch/arm/mach-ak98/ddr2change.c
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/mach-ak98/ddr2change.c
+ */
+ 
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+
+#include <mach/l2_exebuf.h>
+
+/*
+ * function: initialization ram register for ddr2 in L2
+ */
+void L2_LINK(ddr2change) L2FUNC_NAME(ddr2change)(unsigned long param1,
+	unsigned long param2,unsigned long param3,unsigned long param4)
+{
+    DISABLE_CACHE_MMU();
+    DDR2_ENTER_SELFREFRESH();
+    PM_DELAY(0x300);
+
+    //disable ram clock
+    REG32(PHY_CLOCK_CTRL_REG) |= (1<<10);
+
+    REG32(PHY_RAM_CFG_REG2) = param1; 
+    REG32(PHY_RAM_CFG_REG3) = param2; 
+	PM_DELAY(0x2000);
+
+    //enable ram clock
+    REG32(PHY_CLOCK_CTRL_REG) &= ~(1<<10);
+
+    DDR2_EXIT_SELFREFRESH();
+    PM_DELAY(0x2000);
+	LED_PHY_ON;
+    ENABLE_CACHE_MMU();
+}
+
+/*
+ *function: configuration ram register
+ *@mem_clk: mem clock for ddr2
+ */
+void sdram_on_change(unsigned int mem_clk)
+{
+	/* unit in ns
+	* refer to sdram spec.
+	*/
+	#define tRRD	40	//ative to active time, min is 10ns
+	#define tRAS	112  //acive to precharge time, min is 45
+	#define tRCD	25	//actvie to read/write delay, min is 18
+	#define tRP 	25	//precharge to next actvie/refresh time, min is 18
+	#define tRFC	256 //refresh to active/refresh command time
+	#define tWR 	25	//data in to precharge time
+	#define tWTR	25	 //data in to read command delay
+	#define tRTW	75	//read to write command delay
+
+    unsigned long cycle, value1, value2, auto_refresh;
+    unsigned char  t_ras=15, t_rcd=7, t_rp=7, t_rfc=15, t_rrd=3;   //in clk cycle
+    unsigned char  t_wr=7, t_wtr=3, t_rtw=3;
+
+    return; //not implemented now
+    
+    cycle = 1000/(mem_clk/1000000);
+  
+    t_rrd = tRAS / cycle + 1; if (t_rrd > 7) t_rrd = 7;
+    t_ras = tRAS / cycle + 1; if (t_ras > 31) t_ras = 31;
+    t_rcd = tRCD / cycle + 1; if (t_rcd > 15) t_rcd = 15;
+    t_rp  = tRP / cycle + 1; if (t_rp > 15) t_rp = 15;
+    t_rfc = tRFC / cycle + 1; if (t_rfc > 255) t_rfc = 255;
+
+    t_wr  = tWR / cycle + 1; if (t_wr > 15) t_wr = 15;
+    t_rtw = tRTW / cycle + 1; if (t_rtw > 15) t_rtw = 15;
+    t_wtr = tWTR / cycle + 1; if (t_wtr > 15) t_wtr = 15;
+
+    //update sdram AC charateristics
+    value1 = REG32(RAM_CFG_REG2);
+
+    value1 &= ~(0x7<<21); //clear rrd !!!
+    value1 |= t_rrd<<21;    
+
+    value1 &= ~(0x1f<<16); //clear ras
+    value1 |= t_ras<<16;
+
+    value1 &= ~(0xf<<12); //clear rp !!!
+    value1 |= t_rp<<12;
+    
+    value1 &= ~(0xf<<8); //clear rcd
+    value1 |= t_rcd<<8;
+
+    value1 &= ~(0xff<<0); //clear rfc
+    value1 |= t_rfc<<0;
+
+    //config reg2
+    value2 = REG32(RAM_CFG_REG3);
+    value2 &= ~(0xf<<12);
+    value2 |= t_rtw<<12;//tRTW
+    value2 &= ~(0xf<<0);
+    value2 |= t_wr<<0;//tWR
+
+	//copy the code that set pll value to L2(0x48000000), then move pc to L2
+	SPECIFIC_L2BUF_EXEC(ddr2change, value1, value2, 0, 0);
+
+
+	//ddr2 reset
+
+
+	//ram controller
+
+}
+
+
diff --git a/arch/arm/mach-ak98/dev_reset.c b/arch/arm/mach-ak98/dev_reset.c
new file mode 100644
index 00000000000..5d224f756c6
--- /dev/null
+++ b/arch/arm/mach-ak98/dev_reset.c
@@ -0,0 +1,95 @@
+/*
+ * dev_reset.c - device reset routines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <mach/dev_reset.h>
+#include <mach/map.h>
+
+static DEFINE_SPINLOCK(sys_reset_ctrl_lock);
+
+/* The device reset control register */
+static unsigned long reset_reg[] = {
+	/* RESET_CTRL_1 */ 		(unsigned long)AK98_VA_SYSCTRL + 0x000c,	/* ->0x0800000c */ 
+	/* RESET_CTRL_2 */ 		(unsigned long)AK98_VA_SYSCTRL + 0x0010,	/* ->0x08000010 */
+};
+
+static struct device_reset_ctrl reset_ctrl[] = {
+	/* Device */				/* Register index */	/* bit */	/* delay */
+	/* DEV_USB_OTG			*/		{RESET_CTRL_1,			31, 		0},
+	/* DEV_NAND 			*/		{RESET_CTRL_1,			30, 		0},
+	/* DEV_SPI1 			*/		{RESET_CTRL_1,			29, 		0},
+	/* DEV_UART1			*/		{RESET_CTRL_1,			28, 		0},
+	/* DEV_LCD,				*/		{RESET_CTRL_1,			27, 		0},
+	/* DEV_RAM,				*/		{RESET_CTRL_1,			26, 		0},
+	/* DEV_CAMERA,			*/		{RESET_CTRL_1,			24, 		0},
+	/* DEV_H264,			*/		{RESET_CTRL_1,			23, 		0},
+	/* DEV_ROTATION,		*/		{RESET_CTRL_1,			21, 		0},
+	/* DEV_L2FIFO,			*/		{RESET_CTRL_1,			19, 		0},
+	/* DEV_PCM,				*/		{RESET_CTRL_1,			18, 		0},
+	/* DEV_DAC,				*/		{RESET_CTRL_1,			17, 		0},
+	/* DEV_ADC2,			*/		{RESET_CTRL_1,			16, 		0},
+	/* DEV_VIDEO,			*/		{RESET_CTRL_2,			31, 		0},
+	/* DEV_MAC,				*/		{RESET_CTRL_2,			30, 		0},
+	/* DEV_RMVB,			*/		{RESET_CTRL_2,			29, 		0},
+	/* DEV_HUFFMAN,			*/		{RESET_CTRL_2,			28, 		0},
+	/* DEV_MOTION_ESTIMATION*/		{RESET_CTRL_2,			27, 		0},
+	/* DEV_H263_MPEG4,		*/		{RESET_CTRL_2,			26, 		0},
+	/* DEV_JPEG,			*/		{RESET_CTRL_2,			25, 		0},
+	/* DEV_MPEG2_ASP,		*/		{RESET_CTRL_2,			24, 		0},
+	/* DEV_SPI2,			*/		{RESET_CTRL_2,			23, 		0},
+	/* DEV_UART4,			*/		{RESET_CTRL_2,			22, 		0},
+	/* DEV_UART3_I2C,		*/		{RESET_CTRL_2,			21, 		0},
+	/* DEV_UART2,			*/		{RESET_CTRL_2,			20, 		0},
+	/* DEV_SDIO,			*/		{RESET_CTRL_2,			19, 		0},
+	/* DEV_MMC_SD,			*/		{RESET_CTRL_2,			18, 		0},
+	/* DEV_USB_FS,			*/		{RESET_CTRL_2,			17, 		0},
+	/* DEV_2D,				*/		{RESET_CTRL_2,			16, 		0},
+};
+
+
+/*
+ * @brief:	AK98XX device controller reset routine
+ * @author:	Zhongjunchao
+ * @date:	2011-07-13
+ * @param:	[in]dev_no the device selected to be reset, refrence dev_reset.h
+ * @note:	This routine is created in order to solve the problem of concurrency 
+ * 			and crace onditions of device driver operate Clock Control and 
+ * 			Soft Reset Control Register
+ * @note:	This routine depends on that corresponding registers are mapped, 
+ * 			currently this is done in ak98_map_io(), so be careful about 
+ * 			ak98_map_io() changes.
+ * @sample:	device_controller_reset(DEV_NAND)
+ *
+ */
+void device_controller_reset(int dev_no)
+{
+	unsigned long flags;
+	unsigned long val;
+	unsigned long reg_addr;
+	struct device_reset_ctrl *reset_device;
+
+	BUG_ON(dev_no < 0 || dev_no >= DEV_MAX);
+
+	spin_lock_irqsave(&sys_reset_ctrl_lock, flags);
+
+	reset_device = reset_ctrl + dev_no;
+	reg_addr = reset_reg[reset_device->regdix];
+
+	val = __raw_readl(reg_addr);
+	val |= (1 << reset_device->ctrlbit);
+	__raw_writel(val, reg_addr);
+	udelay(reset_device->delay);
+	val &= ~(1 << reset_device->ctrlbit);
+	__raw_writel(val, reg_addr);
+
+	spin_unlock_irqrestore(&sys_reset_ctrl_lock, flags);
+}
+EXPORT_SYMBOL(device_controller_reset);
diff --git a/arch/arm/mach-ak98/devices.c b/arch/arm/mach-ak98/devices.c
new file mode 100644
index 00000000000..cee40f7f3ad
--- /dev/null
+++ b/arch/arm/mach-ak98/devices.c
@@ -0,0 +1,719 @@
+/* linux/arch/arm/mach-ak98/devices.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <mach/ts.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <mach/lib_l2.h>
+#include <mach/lib_lcd.h>
+#include <mach/devices_ak880x.h>
+#include <mach/gpio.h>
+#include <mach/mac.h>
+#include <mach/i2c.h>
+
+#include <linux/uio_driver.h>
+#include <linux/android_pmem.h>
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#include <mach/regs-comm.h>
+#include <linux/usb/android_composite.h>
+#include <linux/ctype.h>
+
+struct platform_device ak98_freq_policy_device = {
+	.name = "freq_policy",
+		.id = -1,
+};
+EXPORT_SYMBOL(ak98_freq_policy_device);
+
+
+struct platform_device ak98_led_device = {
+	.name = "ak98-led",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_led_device);
+
+struct platform_device ak98_rtc_device = {
+	.name = "ak98-rtc",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_rtc_device);
+
+struct platform_device ak98adc_ts_device = {
+	.name = "ak98adc-ts",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98adc_ts_device);
+
+struct platform_device ak98pwm_backlight_device = {
+	.name = "ak98pwm-backlight",
+		.id = -1,
+};
+EXPORT_SYMBOL(ak98pwm_backlight_device);
+
+struct platform_device ak98_pwm0_device = {
+	.name = "ak98-pwm",
+	.id = 0,
+};
+EXPORT_SYMBOL(ak98_pwm0_device);
+
+struct platform_device ak98_pwm1_device = {
+	.name = "ak98-pwm",
+	.id = 1,
+};
+EXPORT_SYMBOL(ak98_pwm1_device);
+
+struct platform_device ak98_pwm2_device = {
+	.name = "ak98-pwm",
+	.id = 2,
+};
+EXPORT_SYMBOL(ak98_pwm2_device);
+
+struct platform_device ak98_pwm3_device = {
+	.name = "ak98-pwm",
+	.id = 3,
+};
+EXPORT_SYMBOL(ak98_pwm3_device);
+
+struct platform_device ak98_uart0_device = {
+	.name = "ak98-uart",
+	.id = 0,
+};
+EXPORT_SYMBOL(ak98_uart0_device);
+
+struct platform_device ak98_uart1_device = {
+	.name = "ak98-uart",
+	.id = 1,
+};
+EXPORT_SYMBOL(ak98_uart1_device);
+
+struct platform_device ak98_uart2_device = {
+	.name = "ak98-uart",
+	.id = 2,
+};
+EXPORT_SYMBOL(ak98_uart2_device);
+
+struct platform_device ak98_uart3_device = {
+	.name = "ak98-uart",
+	.id = 3,
+};
+EXPORT_SYMBOL(ak98_uart3_device);
+
+/* battery_power supply */
+struct platform_device ak98_battery_power = {
+	.name = "fake_battery",
+	.id   = -1,
+};
+EXPORT_SYMBOL(ak98_battery_power);
+
+static struct resource gpio_trkball_resources[] = {
+#if 0	/* NORMAL SCREEN */
+	{		/* UP IRQ */
+		.name		= "UP GPIO IRQ",
+		.start		= IRQ_GPIO_79,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* DOWN IRQ */
+		.name		= "DOWN GPIO IRQ",
+		.start		= IRQ_GPIO_77,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* LEFT IRQ */
+		.name		= "LEFT GPIO IRQ",
+		.start		= IRQ_GPIO_76,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* RIGHT IRQ */
+		.name		= "RIGHT GPIO IRQ",
+		.start		= IRQ_GPIO_78,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	},
+#else	/* ROTATE SCREEN */
+	{		/* UP IRQ */
+		.name		= "UP GPIO IRQ",
+		.start		= IRQ_GPIO_76,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* DOWN IRQ */
+		.name		= "DOWN GPIO IRQ",
+		.start		= IRQ_GPIO_78,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* LEFT IRQ */
+		.name		= "LEFT GPIO IRQ",
+		.start		= IRQ_GPIO_77,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	}, {		/* RIGHT IRQ */
+		.name		= "RIGHT GPIO IRQ",
+		.start		= IRQ_GPIO_79,
+		.flags		= IORESOURCE_IRQ | IRQ_TYPE_LEVEL_HIGH,
+	},
+#endif
+};
+
+struct platform_device ak98_gpio_trkball_device = {
+	.name		= "ak98-trkball",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(gpio_trkball_resources),
+	.resource	= gpio_trkball_resources,
+};
+EXPORT_SYMBOL(ak98_gpio_trkball_device);
+
+struct platform_device ak98_kpd_device = {
+	.name = "ak98-kpd",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_kpd_device);
+
+/* AK88 AD/DA for sound system */
+struct platform_device ak98_snd_device = {
+	.name = "ak98-snd",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_snd_device);
+
+/* AK88 SPI */
+static struct resource ak98_spi1_resource[] = {
+	[0] = {
+	       .start = AK98_PA_SPI1,
+	       .end = AK98_PA_SPI1 + 0x24,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .start = IRQ_SPI1,
+	       .end = IRQ_SPI1,
+	       .flags = IORESOURCE_IRQ,
+	       }
+};
+
+struct platform_device ak98_spi1_device = {
+	.name = "ak98-spi",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_spi1_resource),
+	.resource = ak98_spi1_resource,
+};
+EXPORT_SYMBOL(ak98_spi1_device);
+
+static struct resource ak98mmx_resources[] = {
+	{
+		.name   = "system-ctrl",
+		.start	= 0x08000000,
+		.end	= 0x08000017,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "video-base",
+		.start	= 0x20000000,
+		.end	= 0x20000693,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "h264-decoder",
+		.start	= 0x20001000,
+		.end	= 0x20001cff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "h264-Q_MATRIX",
+		.start	= 0x20002800,
+		.end	= 0x20002bbf,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "h264-dmx",
+		.start	= 0x20004000,
+		.end	= 0x2000400f,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "mpeg4-decoder",
+		.start	= 0x20040000,
+		.end	= 0x200401ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "mpeg4-decoder2",
+		.start	= 0x20040200,
+		.end	= 0x200402ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "mpeg4-decoder3",
+		.start	= 0x20040300,
+		.end	= 0x200403ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "xvid-decoder",
+		.start	= 0x20040800,
+		.end	= 0x200408ff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "h263-encoder",
+		.start	= 0x20048000,
+		.end	= 0x20048023,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "rv-decoder",
+		.start	= 0x20070000,
+		.end	= 0x20070053,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "rv-decoder2",
+		.start	= 0x20072000,
+		.end	= 0x2007202f,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "rv-filter",
+		.start	= 0x20078000,
+		.end	= 0x20078021,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name   = "mpeg2/asp-decoder",
+		.start	= 0x20071000,
+		.end	= 0x20071063,
+		.flags	= IORESOURCE_MEM,
+	}
+};
+
+static struct uio_info akmmx_uioinfo = {
+	.name    = "ak98-vcodec",
+	.version = "0.1.0",
+#ifdef CONFIG_UIODMA
+	.use_dma = true,
+#endif
+	.irq     = UIO_IRQ_CUSTOM,
+};
+
+struct platform_device ak98_mmx_device = {
+	.name		= "uio_ak98_vcodec",
+	.id		= -1,
+	.dev		= {
+		.platform_data = &akmmx_uioinfo,
+	},
+	.num_resources	= ARRAY_SIZE(ak98mmx_resources),
+	.resource	= ak98mmx_resources,
+};
+EXPORT_SYMBOL(ak98_mmx_device);
+
+static struct android_pmem_platform_data akmmx_pmeminfo = {
+	.name    = "ak98_mmx_pmem",
+#if 0
+	.start   = 0x8E600000,		/* the last 26M */
+#else
+	.start   = CONFIG_RAM_BASE,	/* the first 26M */
+#endif
+	.size    = CONFIG_VIDEO_RESERVED_MEM_SIZE,
+	.no_allocator = 1,
+	.cached  = 1,
+	.buffered = 1,
+};
+
+struct platform_device ak98_mmx_pmem = {
+	.name           = "android_pmem",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &akmmx_pmeminfo,
+	}
+};
+
+EXPORT_SYMBOL(ak98_mmx_pmem);
+
+#define IRQ_DISP IRQ_DISPLAY_CTRL
+static struct resource ak98fb_resources[] = {
+	[0] = {
+		.start	= 0x2000d000,
+		.end	= 0x2000d123,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_DISP,
+		.end	= IRQ_DISP,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+static u64 fb_dma_mask = DMA_BIT_MASK(32);
+struct platform_device ak98_lcd_device = {
+	.name		= "ak98-lcd",
+	.id		= -1,
+	.dev		= {
+		.dma_mask	= &fb_dma_mask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+	.num_resources	= ARRAY_SIZE(ak98fb_resources),
+	.resource	= ak98fb_resources,
+};
+EXPORT_SYMBOL(ak98_lcd_device);
+
+struct platform_device ak98_osd_device = {
+	.name = "ak98-osd",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_osd_device);
+
+struct platform_device ak98_tvout_device = {
+	.name = "ak98-tvout",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_tvout_device);
+
+struct platform_device ak98_nand_device = {
+	.name = "ak98-nand",
+	.id = -1,
+};
+EXPORT_SYMBOL(ak98_nand_device);
+
+/* I2C */
+struct gpio_info i2c_gpios[] = {
+		{
+			.pin 		= AK98_GPIO_92,
+			.pulldown 	= -1,
+			.pullup 	= -1,
+			.dir		= AK98_GPIO_DIR_OUTPUT,
+			.value 		= AK98_GPIO_HIGH,
+			.int_pol	= -1,
+		},
+		{
+			.pin 		= AK98_GPIO_93,
+			.pulldown 	= -1,
+			.pullup 	= -1,
+			.dir		= AK98_GPIO_DIR_OUTPUT,
+			.value 		= AK98_GPIO_HIGH,
+			.int_pol	= -1,
+
+		},
+};
+
+static struct ak98_platform_i2c ak98_default_i2c_data = {
+	.flags		= 0,
+	.bus_num	= 0,
+	.slave_addr	= 0x10,
+	.frequency	= 100*1000,
+	.sda_delay	= 100,
+	.gpios		= i2c_gpios,
+	.npins		= ARRAY_SIZE(i2c_gpios),
+};
+
+static struct resource ak98_i2c_resource[] = {
+	[0] = {
+		.start = AK98_PA_I2C,
+		.end   = AK98_PA_I2C + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_I2C,
+		.end   = IRQ_I2C,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ak98_i2c_device = {
+	.name	= "ak98-i2c",
+	.id		= -1,
+	.dev	= {
+		.platform_data = &ak98_default_i2c_data,
+	},
+	.num_resources	= ARRAY_SIZE(ak98_i2c_resource),
+	.resource		= ak98_i2c_resource,
+};
+EXPORT_SYMBOL(ak98_i2c_device);
+
+/* USB */
+static struct resource ak98_usb_resource[] = {
+	[0] = {
+	       .start = 0x70000000,
+	       .end = 0x700007ff,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .name = "usb mcu irq",
+	       .start = IRQ_USBOTG_MCU,
+	       .flags = IORESOURCE_IRQ,
+	       },
+	[2] = {
+	       .name = "usb dma irq",
+	       .start = IRQ_USBOTG_DMA,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+struct platform_device ak98_usb_device = {
+	.name = "ak98_udc",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_usb_resource),
+	.resource = ak98_usb_resource,
+};
+EXPORT_SYMBOL(ak98_usb_device);
+
+/* USB FS HCD .*/
+static struct resource ak98_usb_fs_hcd_resource[] = {
+	[0] = {
+	       .start = 0x70008000,
+	       .end = 0x70008fff,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .name = "usb mcu irq",
+	       .start = IRQ_USBHOST_MCU,
+	       .flags = IORESOURCE_IRQ,
+	       },
+	[2] = {
+	       .name = "usb dma irq",
+	       .start = IRQ_USBHOST_DMA,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+struct platform_device ak98_usb_fs_hcd_device = {
+	.name = "ak98-fs-hcd",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_usb_fs_hcd_resource),
+	.resource = ak98_usb_fs_hcd_resource,
+};
+EXPORT_SYMBOL(ak98_usb_fs_hcd_device);
+
+/* MAC */
+static struct resource ak98_mac_resource[] = {
+	[0] = {
+	       .start = 0x60000000,
+	       .end = 0x60001fff,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .name = "mac irq",
+	       .start = IRQ_MAC,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+static struct ak98_mac_data ak98_mac = {
+	.dev_addr = {0x00, 0x1a, 0xa0, 0x3a, 0x6c, 0xff},
+};
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+// convert a capital character to int
+#define CTOI(c) (isdigit(c) ? (c - '0') : (c - 'A' + 10))
+			
+int __init ak98_mac_boot_setup(char *str)
+{
+	char mac_addr[MAC_ADDR_STRING_LEN + 1];
+	int i;
+
+	if (strlen(str) != MAC_ADDR_STRING_LEN)
+		goto out;
+	
+	strcpy(mac_addr, str);
+	for (i = 0; i < MAC_ADDR_STRING_LEN; i++) {
+		if ((i % 3 != 2)) {
+			mac_addr[i] = toupper(mac_addr[i]);
+			if (!(isdigit(mac_addr[i]) || (mac_addr[i] <= 'F' && mac_addr[i] >= 'A')))
+				goto out;
+		}
+		else if (mac_addr[i] != ':')
+			goto out;
+	}
+	
+	for (i  = 0; i < MAC_ADDR_LEN; i++)
+		ak98_mac.dev_addr[i] = CTOI(mac_addr[i * 3]) * 16 + CTOI(mac_addr[i * 3 + 1]);
+
+	return 0;
+
+out:
+	printk("input MAC address ERROR, use the default mac address!\n");
+
+	return 0;
+}
+
+__setup("mac_addr=", ak98_mac_boot_setup);
+#endif
+
+struct platform_device ak98_mac_device = {
+	.name = "ak98_mac",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_mac_resource),
+	.resource = ak98_mac_resource,
+	.dev        = {
+		.platform_data = &ak98_mac,
+	}
+};
+EXPORT_SYMBOL(ak98_mac_device);
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+
+//#if defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+#if defined(CONFIG_FB_AK88) || defined(CONFIG_FB_AK88_DEBUG)
+
+struct anyka_lcdfb_info;
+
+static u64 lcdc_dmamask = DMA_BIT_MASK(32);	//=1UL<<31, if(n==64) : ~0ULL
+static struct anyka_lcdfb_info lcdc_data;
+
+#define IRQ_DISP IRQ_DISPLAY_CTRL
+static struct resource lcdc_resources[] = {
+	[0] = {
+	       .start = (int)AK98_VA_DISP,
+	       .end = (int)AK98_VA_DISP + SZ_4K - 1,
+	       .flags = (int)IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .start = (int)IRQ_DISP,	//IRQ_DISP=1
+	       .end = (int)IRQ_DISP,
+	       .flags = (int)IORESOURCE_IRQ,
+	       },
+};
+
+static struct platform_device ak98_lcdc_device = {
+	.name = "anyka_lcdfb",
+	.id = 0,
+	.dev = {
+		.dma_mask = &lcdc_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+		.platform_data = &lcdc_data,
+		},
+	.resource = lcdc_resources,
+	.num_resources = ARRAY_SIZE(lcdc_resources),
+};
+
+void __init ak98_add_device_lcdc(struct anyka_lcdfb_info *data)
+{
+	if (!data)
+		return;
+ 
+	//set sharepin
+//#define rSHAREPIN_CON1    (ANYKA_PA_SYS+0x0078)   //0x08000078
+//bit[25]: 1=corresponding are used as {LCD_DATA[15:9]}  //gpio[68:62]
+//bit[26]: 1=corresponding are used as {LCD_DATA[8]}     //gpio[61]
+//bit[27]: 1=corresponding are used as {LCD_DATA[17:16]} //gpio[70:69] 
+
+	AKSET_BITS(1UL << 25, rSHAREPIN_CON1);	//set pin as LCD_DATA[15:9]
+	AKSET_BITS(1UL << 26, rSHAREPIN_CON1);	//set pin as LCD_DATA[8]
+	AKSET_BITS(1UL << 27, rSHAREPIN_CON1);	//set pin as LCD_DATA[17:16]
+
+	//open power clock
+//#define rCLK_CON1    (AK98_VA_SYS+0x000C)   //0xF000000C
+//bit[15],0 = to enable L2 controller/UART1 working clock
+//bit[3], 0 = to enable display controller working clock
+
+	//open LCD controller clock
+	AKCLR_BITS(1UL << 3, rCLK_CON1);	//0x0800000C
+
+	set_ahb_priority();
+
+	lcdc_data = *data;
+	platform_device_register(&ak98_lcdc_device);
+}
+#else
+void __init ak98_add_device_lcdc(struct anyka_lcdfb_info *data)
+{
+}
+#endif
+
+//char *funs[] = {"adb", "usb_mass_storage"};
+char *funs1[] = {"usb_mass_storage"};
+char *funs2[] = {"usb_mass_storage", "adb"};
+
+struct android_usb_product ak98_android_usb_product[] = {
+	[0] = {
+		.product_id = 0x0C02,
+		.num_functions = 1,
+		.functions = funs1,
+	},
+	[1] = {
+		.product_id = 0x0D02,
+		.num_functions = 2,
+		.functions = funs2,
+	},
+};
+
+struct android_usb_platform_data ak98_usb_platform_data = {
+	.vendor_id = 0x18D1,
+	.product_id = 0x0D02,
+	.version = 0x1,
+
+	.product_name = "Android",
+	.manufacturer_name = "ANYKA",
+	.serial_number = "0123456789ABCDEF",
+
+	.num_products = ARRAY_SIZE(ak98_android_usb_product),
+	.products = ak98_android_usb_product,
+
+	.num_functions = 2,
+	.functions = funs2,
+};
+
+struct platform_device ak98_android_usb = {
+	.name = "android_usb",
+	.id = 0,
+	.dev = {
+			.platform_data = &ak98_usb_platform_data,
+	}
+};
+EXPORT_SYMBOL(ak98_android_usb);
+
+struct usb_mass_storage_platform_data ak98_usb_mass_storage = {
+	.vendor = "ANYKA",
+	.product = "Mass Storage",
+	.release = 0x01,
+
+	.nluns = 1,
+};
+
+struct platform_device ak98_android_usb_mass_storage = {
+	.name = "usb_mass_storage",
+	.id = 0,
+	.dev = {
+			.platform_data = &ak98_usb_mass_storage,
+	}
+};
+EXPORT_SYMBOL(ak98_android_usb_mass_storage);
+
+/* Camera interface resource */
+static struct resource ak98_camera_resource[] = {
+	[0] = {
+	       .start = 0x2000c000,
+	       .end = 0x2000c084,
+	       .flags = IORESOURCE_MEM,
+	       },
+	[1] = {
+	       .name = "camera if irq",
+	       .start = IRQ_CAMERA_IF,
+	       .flags = IORESOURCE_IRQ,
+	       },
+};
+
+/* camera interface */
+struct platform_device ak98_camera_interface = {
+	.name = "ak98_camera",
+	.id   = 98,
+	.num_resources	= ARRAY_SIZE(ak98_camera_resource),	
+	.resource = ak98_camera_resource,
+};
+EXPORT_SYMBOL(ak98_camera_interface);
+
+
diff --git a/arch/arm/mach-ak98/dma.c b/arch/arm/mach-ak98/dma.c
new file mode 100644
index 00000000000..8b137891791
--- /dev/null
+++ b/arch/arm/mach-ak98/dma.c
@@ -0,0 +1 @@
+
diff --git a/arch/arm/mach-ak98/gpio.c b/arch/arm/mach-ak98/gpio.c
new file mode 100644
index 00000000000..92cb7557a7f
--- /dev/null
+++ b/arch/arm/mach-ak98/gpio.c
@@ -0,0 +1,231 @@
+/*
+ *  arch/arm/mach-ak98/gpio.c
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <mach/ak98-gpio.h>
+#include <linux/i2c/aw9523.h>
+
+
+static struct gpio_callbacks_info ak98_gpio_callbacks[] =
+{
+		{
+			.pin_start 		= AK98_GPIO_0,
+			.pin_end 		= AK98_GPIO_116,
+			.setpin_as_gpio	= g_ak98_setpin_as_gpio,
+			.gpio_pullup	= g_ak98_gpio_pullup,
+			.gpio_pulldown	= g_ak98_gpio_pulldown,
+			.gpio_dircfg	= g_ak98_gpio_cfgpin,
+			.gpio_intcfg	= g_ak98_gpio_inten,
+			.gpio_set_intpol= g_ak98_gpio_intpol,
+			.gpio_setpin	= g_ak98_gpio_setpin,
+			.gpio_getpin	= g_ak98_gpio_getpin,
+			.gpio_to_irq	= g_ak98_gpio_to_irq,
+			.irq_to_gpio	= g_ak98_irq_to_gpio,			
+		},
+		{
+			.pin_start 		= AK98_MCGPIO_0,
+			.pin_end 		= AK98_MCGPIO_19,
+			.setpin_as_gpio	= mc_ak98_setpin_as_mcgpio,
+			.gpio_pullup	= NULL,			
+			.gpio_pulldown	= mc_ak98_mcgpio_pulldown,
+			.gpio_dircfg	= mc_ak98_mcgpio_cfgpin,
+			.gpio_intcfg	= NULL,
+			.gpio_set_intpol= NULL,
+			.gpio_setpin	= mc_ak98_mcgpio_setpin,
+			.gpio_getpin	= mc_ak98_mcgpio_getpin,
+			.gpio_to_irq	= NULL,
+			.irq_to_gpio	= NULL,			
+		},
+	#ifdef CONFIG_I2C_AW9523_GPIO
+		{
+			.pin_start 		= AW9523_GPIO_P00,
+			.pin_end 		= AW9523_GPIO_P17,
+			.setpin_as_gpio	= NULL,
+			.gpio_pullup	= NULL,
+			.gpio_pulldown	= NULL,
+			.gpio_dircfg	= aw9523_gpio_dircfg,
+			.gpio_intcfg	= aw9523_gpio_intcfg,
+			.gpio_set_intpol= NULL,
+			.gpio_setpin	= aw9523_gpio_setpin,
+			.gpio_getpin	= aw9523_gpio_getpin,
+			.gpio_to_irq	= aw9523_gpio_to_irq,
+			.irq_to_gpio	= aw9523_irq_to_gpio,			
+		},
+	#endif
+};
+
+#define CALLBACKS_TBL ak98_gpio_callbacks
+#define GET_GPIO_CALLBACKS(pfun, pin, name)\
+	do{\
+	int _i_name;\
+	pfun=NULL;\
+	for (_i_name=0; _i_name<ARRAY_SIZE(CALLBACKS_TBL); _i_name++)\
+	if (pin>= CALLBACKS_TBL[_i_name].pin_start && pin <= CALLBACKS_TBL[_i_name].pin_end)\
+	{ pfun = CALLBACKS_TBL[_i_name].name; break;}\
+	}while(0);
+										
+
+
+int ak98_setpin_as_gpio (unsigned int pin)
+{
+	int (*pfunc)(unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, setpin_as_gpio);
+	if (pfunc)
+		return pfunc(pin);
+	return 0;
+}
+EXPORT_SYMBOL(ak98_setpin_as_gpio);
+
+
+int ak98_gpio_pullup(unsigned int pin, unsigned char enable)
+{
+	int (*pfunc)(unsigned int, unsigned char);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_pullup);
+	if (pfunc)
+		return pfunc(pin, enable);	
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_pullup);
+
+int ak98_gpio_pulldown(unsigned int pin, unsigned char enable)
+{
+	int (*pfunc)(unsigned int, unsigned char);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_pulldown);
+	if (pfunc)
+		return pfunc(pin, enable);	
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_pulldown);
+
+/*  direction configuration  */
+int ak98_gpio_dircfg(unsigned int pin, unsigned int direction)
+{
+	int (*pfunc)(unsigned int, unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_dircfg);
+	if (pfunc)
+		return pfunc(pin, direction);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_dircfg);
+int ak98_gpio_cfgpin(unsigned int pin, unsigned int to)
+{
+		return ak98_gpio_dircfg(pin, to);
+}
+EXPORT_SYMBOL(ak98_gpio_cfgpin);
+
+
+/* interrupt configuration */
+int ak98_gpio_intcfg(unsigned int pin, unsigned int enable)
+{
+	int (*pfunc)(unsigned int, unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_intcfg);
+	if (pfunc)
+		return pfunc(pin, enable);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_intcfg);
+int ak98_gpio_inten(unsigned int pin, unsigned int enable)
+{
+	return ak98_gpio_intcfg(pin, enable);
+}
+EXPORT_SYMBOL(ak98_gpio_inten);
+
+
+
+/*  interrupt polarity configuration */
+int ak98_gpio_set_intpol(unsigned int pin, unsigned int level)
+{
+	int (*pfunc)(unsigned int, unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_set_intpol);
+	if (pfunc)
+		return pfunc(pin, level);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_set_intpol);
+int ak98_gpio_intpol(unsigned int pin, unsigned int level)
+{
+	return ak98_gpio_set_intpol(pin, level);
+}
+EXPORT_SYMBOL(ak98_gpio_intpol);	
+
+
+int ak98_gpio_setpin(unsigned int pin, unsigned int to)
+{
+	int (*pfunc)(unsigned int, unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_setpin);
+	if (pfunc)
+		return pfunc(pin, to);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_setpin);
+
+ int ak98_gpio_getpin(unsigned int pin)
+{	
+	 int (*pfunc)(unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_getpin);
+	if (pfunc)
+		return pfunc(pin);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_getpin);
+
+
+
+ int ak98_gpio_to_irq(unsigned int pin)
+{
+	int (*pfunc)(unsigned int);
+	GET_GPIO_CALLBACKS(pfunc, pin, gpio_to_irq);
+	if (pfunc)
+		return pfunc(pin);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_gpio_to_irq);
+
+ int ak98_irq_to_gpio(unsigned int irq)
+{
+	if ( irq >= IRQ_GPIO_0 && irq<= IRQ_GPIO_116)
+		return AK98_GPIO_0 + (irq-IRQ_GPIO_0);
+	else if (irq >= IRQ_AW9523_P00 && irq <= IRQ_AW9523_P17)
+		return AW9523_GPIO_P00 + (irq-IRQ_AW9523_P00);
+	else
+		panic("wrong irq number %u passed to ak98_irq_to_gpio.\n", irq);
+
+	return -1;
+}
+EXPORT_SYMBOL(ak98_irq_to_gpio);
+
+
+void ak98_gpio_set(const struct gpio_info *info)
+{
+	if ( ! (info->pin >= AK98_GPIO_MIN && info->pin <= AK98_GPIO_MAX ))
+		return ;
+	
+	ak98_setpin_as_gpio(info->pin);
+	if (info->dir == AK98_GPIO_DIR_OUTPUT || info->dir == AK98_GPIO_DIR_INPUT)
+		ak98_gpio_dircfg(info->pin, info->dir);
+	if (info->pullup == AK98_PULLUP_ENABLE || info->pullup == AK98_PULLUP_DISABLE)
+		ak98_gpio_pullup(info->pin, info->pullup);
+	if (info->pulldown == AK98_PULLDOWN_ENABLE || info->pulldown == AK98_PULLDOWN_DISABLE)
+		ak98_gpio_pulldown(info->pin, info->pulldown);
+	if (info->value == AK98_GPIO_HIGH || info->value == AK98_GPIO_LOW)
+		ak98_gpio_setpin(info->pin, info->value);
+	if (info->int_pol == AK98_GPIO_INT_LOWLEVEL || info->int_pol == AK98_GPIO_INT_HIGHLEVEL)
+		ak98_gpio_set_intpol(info->pin, info->int_pol);
+}
+EXPORT_SYMBOL(ak98_gpio_set);
+
diff --git a/arch/arm/mach-ak98/include/mach/adc1.h b/arch/arm/mach-ak98/include/mach/adc1.h
new file mode 100644
index 00000000000..e7739e9ba27
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/adc1.h
@@ -0,0 +1,32 @@
+#ifndef _AK98_ADC1_H_

+#define _AK98_ADC1_H_

+

+/*

+	ADC1 common module

+	2011-04-12

+

+ */

+/***** Definitions of macros **********************************/

+#define ADC_MAIN_CLK		12 	/* 12MHz */

+#define ADC1_DIV		 	11

+#define MHZ					1000000

+#define THRESHOLD			100

+

+#define PENDOWN				1

+#define PENUP				0

+#define PENDOWNLEN			0x1f

+

+#define POWER_ON			1

+#define POWER_OFF			0

+/***********************************************************/

+#undef REG32

+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))

+

+void ak98_init_ADC1(unsigned int SampleRate, unsigned int WaitTime);

+void ak98_power_ADC1(int op);

+void ak98_power_ts(int op);

+void ak98_enable_bat_mon(void);

+void ak98_disable_bat_mon(void);

+long ak98_read_voltage(void);

+

+#endif
\ No newline at end of file
diff --git a/arch/arm/mach-ak98/include/mach/ak-sharepin.h b/arch/arm/mach-ak98/include/mach/ak-sharepin.h
new file mode 100644
index 00000000000..2be0545e83b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak-sharepin.h
@@ -0,0 +1,145 @@
+#ifndef _AK88_SHRPIN_H_
+#define _AK88_SHRPIN_H_
+
+#define AK_SHRPIN_CTRL1		(AK98_VA_SYSCTRL+0x78)
+#define	AK_SHRPIN_CTRL2		(AK98_VA_SYSCTRL+0x74)
+
+/* macro for setting sharepin control register 1 */
+
+#define AK_SHRPIN_GRP0			(0)
+#define AK_SHRPIN_GRP0_GPIO		(0<<0)
+#define AK_SHRPIN_GRP0_JTAG_PCM		(1<<0)
+
+#define AK_SHRPIN_GRP1			(1)
+#define AK_SHRPIN_GRP1_GPIO		(0<<1)
+#define AK_SHRPIN_GRP1_RTCK		(1<<1)
+
+#define AK_SHRPIN_GRP2			(2)
+#define AK_SHRPIN_GRP2_GPIO		(0<<2)
+#define AK_SHRPIN_GRP2_I2S		(1<<2)
+
+#define AK_SHRPIN_GRP3			(3)
+#define AK_SHRPIN_GRP3_GPIO		(0<<3)
+#define AK_SHRPIN_GRP3_OTG		(1<<3)
+
+#define AK_SHRPIN_GRP4			(4)
+#define AK_SHRPIN_GRP4_GPIO		(0<<4)
+#define AK_SHRPIN_GRP4_PWM1		(1<<4)
+
+#define AK_SHRPIN_GRP5			(5)
+#define AK_SHRPIN_GRP5_GPIO		(0<<5)
+#define AK_SHRPIN_GRP5_PWM2		(1<<5)
+
+#define AK_SHRPIN_GRP6			(6)
+#define AK_SHRPIN_GRP6_GPIO		(0<<6)
+#define AK_SHRPIN_GRP6_PWM3		(1<<6)
+
+#define AK_SHRPIN_GRP7			(7)
+#define AK_SHRPIN_GRP7_GPIO		(0<<7)
+#define AK_SHRPIN_GRP7_PWM4		(1<<7)
+
+#define AK_SHRPIN_GRP8			(8)
+#define AK_SHRPIN_GRP8_GPIO		(0<<8)
+#define AK_SHRPIN_GRP8_I2S_MCLK		(1<<8)
+
+#define AK_SHRPIN_GRP9			(9)
+#define AK_SHRPIN_GRP9_GPIO		(0<<9)
+#define AK_SHRPIN_GRP9_UART1		(1<<9)
+
+#define AK_SHRPIN_GRP10			(10)
+#define AK_SHRPIN_GRP10_GPIO		(0<<10)
+#define AK_SHRPIN_GRP10_UART2		(1<<10)
+
+#define AK_SHRPIN_GRP11			(11)
+#define AK_SHRPIN_GRP11_GPIO		(0<<11)
+#define AK_SHRPIN_GRP11_UART2		(1<<11)
+
+#define AK_SHRPIN_GRP12			(12)
+#define AK_SHRPIN_GRP12_GPIO		(0<<12)
+#define AK_SHRPIN_GRP12_UART3		(1<<12)
+
+#define AK_SHRPIN_GRP13			(13)
+#define AK_SHRPIN_GRP13_GPIO		(0<<13)
+#define AK_SHRPIN_GRP13_UART3		(1<<13)
+
+#define AK_SHRPIN_GRP14			(14)
+#define AK_SHRPIN_GRP14_GPIO		(0<<14)
+#define AK_SHRPIN_GRP14_UART4_SDIO	(1<<14)
+
+#define AK_SHRPIN_GRP15			(15)
+#define AK_SHRPIN_GRP15_GPIO		(0<<15)
+#define AK_SHRPIN_GRP15_UART4_SDIO	(1<<15)
+
+#define AK_SHRPIN_GRP16			(16)
+#define AK_SHRPIN_GRP16_GPIO		(0<<16)
+#define AK_SHRPIN_GRP16_NFC_MDAT	(1<<16)
+
+#define AK_SHRPIN_GRP17			(17)
+#define AK_SHRPIN_GRP17_GPIO		(0<<17)
+#define AK_SHRPIN_GRP17_NFC_MDAT	(1<<17)
+
+#define AK_SHRPIN_GRP18			(18)
+#define AK_SHRPIN_GRP18_GPIO		(0<<18)
+#define AK_SHRPIN_GRP18_NFC_MDAT	(1<<18)
+
+#define AK_SHRPIN_GRP19			(19)
+#define AK_SHRPIN_GRP19_GPIO		(0<<19)
+#define AK_SHRPIN_GRP19_NFC_CE		(1<<19)
+
+#define AK_SHRPIN_GRP22			(22)
+#define AK_SHRPIN_GRP22_GPIO		(0<<22)
+#define AK_SHRPIN_GRP22_NFC_RDY		(1<<22)
+
+#define AK_SHRPIN_GRP24			(24)
+#define AK_SHRPIN_GRP24_GPIO		(0<<24)
+#define AK_SHRPIN_GRP24_VI		(1<<24)
+
+#define AK_SHRPIN_GRP25			(25)
+#define AK_SHRPIN_GRP25_GPIO		(0<<25)
+#define AK_SHRPIN_GRP25_LCD_DATA	(1<<25)
+
+#define AK_SHRPIN_GRP26			(26)
+#define AK_SHRPIN_GRP26_GPIO		(0<<26)
+#define AK_SHRPIN_GRP26_LCD_DATA	(1<<26)
+
+#define AK_SHRPIN_GRP27			(27)
+#define AK_SHRPIN_GRP27_GPIO		(0<<27)
+#define AK_SHRPIN_GRP27_LCD_DATA	(1<<27)
+
+#define AK_SHRPIN_GRP28			(28)
+#define AK_SHRPIN_GRP28_GPIO		(0<<28)
+#define AK_SHRPIN_GRP28_MPU_RST		(1<<28)
+
+#define AK_SHRPIN_GRP29			(29)
+#define AK_SHRPIN_GRP29_GPIO		(0<<29)
+#define AK_SHRPIN_GRP29_MDAT		(1<<29)
+
+#define AK_SHRPIN_GRP30			(30)
+#define AK_SHRPIN_GRP30_GPIO		(0<<30)
+#define AK_SHRPIN_GRP30_SPI1		(1<<30)
+
+#define AK_SHRPIN_GRP31			(31)
+#define AK_SHRPIN_GRP31_GPIO		(0<<31)
+#define AK_SHRPIN_GRP31_SPI2		(1<<31)
+
+#define AK_SHRPIN_RESERVED1		(20)
+#define	AK_SHPRIN_RESERVED2		(21)
+#define AK_SHRPIN_RESERVED3		(23)
+
+/* macro for setting sharepin control register 2 */
+#define AK_SHRPIN2_GRP1_MASK		(0x1<<0)
+#define AK_SHRPIN2_GRP1_PCM		(0x0<<0)
+#define AK_SHRPIN2_GRP1_JTAG		(0x1<<0)
+
+#define AK_SHRPIN2_GRP2_MASK		(0x3<<1)
+#define AK_SHRPIN2_GRP2_UART4		(0x1<<1)
+#define AK_SHRPIN2_GRP2_SDIO		(0x2<<1)
+
+#define AK_SHRPIN2_GRP3_MASK		(0x3<<3)
+#define AK_SHRPIN2_GRP3_NFC		(0x1<<3)
+#define AK_SHRPIN2_GRP3_MMC		(0x2<<3)
+
+#define AK_SHRPIN2_GRP4_MASK		(0x3<<5)
+#define	AK_SHRPIN2_GRP4_MDAT0		(0x1<<5)
+
+#endif				/* _AK88_SHRPIN_H_ */
diff --git a/arch/arm/mach-ak98/include/mach/ak880x_addr.h b/arch/arm/mach-ak98/include/mach/ak880x_addr.h
new file mode 100644
index 00000000000..97d89bce0a3
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak880x_addr.h
@@ -0,0 +1,189 @@
+/*
+*   Filename:	linux/arch/arm/mach-ak880x/include/mach/ak880x_addr.h
+*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+*/
+
+#ifndef _AK98_ADDR_H_
+#define _AK98_ADDR_H_
+
+#include <mach/map.h>
+
+#define AK98_DISPLAY_REG(x)		(AK98_VA_DISPLAY + (x))
+#define AK98_MMC_REG(x)		(AK98_VA_MMC + (x))
+#define AK98_SDIO_REG(x)		(AK98_VA_SDIO + (x))
+#define AK98_SPI1_REG(x)		(AK98_VA_SPI0 + (x))
+#define AK98_SPI2_REG(x)		(AK98_VA_SPI0 + 0x1000 + (x))
+#define AK98_NFCTRL_REG(x)		(AK98_VA_NFCTRL + (x))
+#define AK98_ECC_REG(x)		(AK98_VA_NFCTRL + 0x1000 + (x))
+#define AK98_DACCTRL_REG(x)		(AK98_VA_DACCTRL + (x))
+#define AK98_CAMIF_REG(x)		(AK98_VA_CAMIF + (x))
+
+
+/* Nand flash controller */
+#define rNFC_COMM1	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x100))	/*Nand flash command register 1 */
+#define rNFC_COMM2	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x104))	/*Nand flash command register 2 */
+#define rNFC_COMM3	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x108))	/*Nand flash command register 3 */
+#define rNFC_COMM4	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x10C))	/*Nand flash command register 4 */
+#define rNFC_COMM5	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x110))	/*Nand flash command register 5 */
+#define rNFC_COMM6	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x114))	/*Nand flash command register 6 */
+#define rNFC_COMM7	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x118))	/*Nand flash command register 7 */
+#define rNFC_COMM8	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x11C))	/*Nand flash command register 8 */
+#define rNFC_COMM9	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x120))	/*Nand flash command register 9 */
+#define rNFC_COMM10	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x124))	/*Nand flash command register 10 */
+#define rNFC_COMM11	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x128))	/*Nand flash command register 11 */
+#define rNFC_COMM12	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x12C))	/*Nand flash command register 12 */
+#define rNFC_COMM13	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x130))	/*Nand flash command register 13 */
+#define rNFC_COMM14	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x134))	/*Nand flash command register 14 */
+#define rNFC_COMM15	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x138))	/*Nand flash command register 15 */
+#define rNFC_COMM16	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x13C))	/*Nand flash command register 16 */
+#define rNFC_COMM17	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x140))	/*Nand flash command register 17 */
+#define rNFC_COMM18	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x144))	/*Nand flash command register 18 */
+#define rNFC_COMM19	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x148))	/*Nand flash command register 19 */
+#define rNFC_COMM20	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x14C))	/*Nand flash command register 20 */
+#define rNFC_STAT1	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x150))	/*Nand flash status register 1 */
+#define rNFC_STAT2	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x154))	/*Nand flash status register 2 */
+#define rNFC_CONSTAT	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x158))	/*Nand flash control/status register */
+#define rNFC_COMMLEN	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x15C))	/*Nand flash command length */
+#define rNFC_DATALEN	(*(volatile unsigned long *)AK98_NFCTRL_REG(0x160))	/*Nand flash data length */
+/* ECC sub-module controller */
+#define rECC_CON	(*(volatile unsigned long *)AK98_ECC_REG(0x00))	/*ECC control register */
+#define rECC_ERRPOS1	(*(volatile unsigned long *)AK98_ECC_REG(0x04))	/*Error posision register 1 */
+#define rECC_ERRPOS2	(*(volatile unsigned long *)AK98_ECC_REG(0x08))	/*Error posision register 2 */
+#define rECC_ERRPOS3	(*(volatile unsigned long *)AK98_ECC_REG(0x0C))	/*Error posision register 3 */
+#define rECC_ERRPOS4	(*(volatile unsigned long *)AK98_ECC_REG(0x10))	/*Error posision register 4 */
+#define rECC_ERRPOS5	(*(volatile unsigned long *)AK98_ECC_REG(0x14))	/*Error posision register 5 */
+#define rECC_ERRPOS6	(*(volatile unsigned long *)AK98_ECC_REG(0x18))	/*Error posision register 6 */
+#define rECC_ERRPOS7	(*(volatile unsigned long *)AK98_ECC_REG(0x1C))	/*Error posision register 7 */
+#define rECC_ERRPOS8	(*(volatile unsigned long *)AK98_ECC_REG(0x20))	/*Error posision register 8 */
+
+
+#define rIIS_CON	(*(volatile unsigned long *)AK98_DACCTRL_REG(0x04))	/*IIS configuration register */
+/* Camera controller */
+#define rCAM_SENSORCOMM		(*(volatile unsigned long *)AK98_CAMIF_REG(0x00))	/*Image capturing command */
+#define rCAM_IMAGEINF1		(*(volatile unsigned long *)AK98_CAMIF_REG(0x04))	/*Source/destination image horizontal length */
+#define rCAM_IMAGEINF2		(*(volatile unsigned long *)AK98_CAMIF_REG(0x08))	/*Horizontal scalling information */
+#define rCAM_IMAGEINF3		(*(volatile unsigned long *)AK98_CAMIF_REG(0x0C))	/*Source/Destination image vertical length */
+#define rCAM_IMAGEINF4		(*(volatile unsigned long *)AK98_CAMIF_REG(0x10))	/*Horizontal scalling information */
+#define rCAM_ODDYADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x18))	/*DMA starting address of external RAM for Y component of odd frame */
+#define rCAM_ODDCbADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x1C))	/*DMA starting address of external RAM for Cb component of odd frame */
+#define rCAM_ODDCrADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x20))	/*DMA starting address of external RAM for Cr component of odd frame */
+#define rCAM_ODDRGBADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x24))	/*DMA starting address of external RAM for RGB/JPGE data of odd frame */
+#define rCAM_EVENYADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x28))
+#define rCAM_EVENCbADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x2C))
+#define rCAM_EVENCrADDR		(*(volatile unsigned long *)AK98_CAMIF_REG(0x30))
+#define rCAM_EVENRGBADDR	(*(volatile unsigned long *)AK98_CAMIF_REG(0x34))
+#define rCAM_SENSORCON		(*(volatile unsigned long *)AK98_CAMIF_REG(0x40))	/*Image sensor configuration */
+#define rCAM_FRAMESTAT		(*(volatile unsigned long *)AK98_CAMIF_REG(0x60))	/*Status of the current frame */
+#define rCAM_FRAMELINE		(*(volatile unsigned long *)AK98_CAMIF_REG(0x80))	/*The line number of a frame when the input data is in JPEG-compressed format */
+/* Display controller */
+#define rLCD_COMM1		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x00))	/*LCD controller command register 1 */
+#define rLCD_MPUIFCON		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x04))	/*MPU interface control */
+#define rLCD_RSTSIG		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x08))
+#define rLCD_MPURDBACK		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x0C))
+#define rLCD_RGBIFCON1		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x10))
+#define rLCD_RGBIFCON2		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x14))
+#define rLCD_RGBPGSIZE		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x18))
+#define rLCD_RGBPGOFFSET	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x1C))
+#define rLCD_OSDADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x20))
+#define rLCD_OSDOFFSET		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x24))
+#define rLCD_OSDCOLOR1		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x28))
+#define rLCD_OSDCOLOR2		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x2C))
+#define rLCD_OSDCOLOR3		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x30))
+#define rLCD_OSDCOLOR4		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x34))
+#define rLCD_OSDCOLOR5		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xD0))
+#define rLCD_OSDCOLOR6		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xD4))
+#define rLCD_OSDCOLOR7		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xD8))
+#define rLCD_OSDCOLOR8		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xDC))
+#define rLCD_OSDSIZE		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x38))
+#define rLCD_BACKCOLOR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x3C))
+#define rLCD_RGBIFCON3		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x40))
+#define rLCD_RGBIFCON4		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x44))
+#define rLCD_RGBIFCON5		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x48))
+#define rLCD_RGBIFCON6		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x4C))
+#define rLCD_RGBIFCON7		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x50))
+#define rLCD_RGBIFCON8		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x54))
+#define rLCD_RGBIFCON9		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x58))
+#define rLCD_Y1_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x5C))
+#define rLCD_Cb1_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x60))
+#define rLCD_Cr1_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x64))
+#define rLCD_YCbCr1_HINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x68))
+#define rLCD_YCbCr1_VINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x6C))
+#define rLCD_YCbCr1_SCAL	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x70))
+#define rLCD_YCbCr1_DISPINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x74))
+#define rLCD_YCbCr1_PGSIZE	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x78))
+#define rLCD_YCbCr1_PGOFFSET	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x7C))
+#define rLCD_Y2_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x80))
+#define rLCD_Cb2_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x84))
+#define rLCD_Cr2_ADDR		(*(volatile unsigned long *)AK98_DISPLAY_REG(0x88))
+#define rLCD_YCbCr2_HINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x8C))
+#define rLCD_YCbCr2_VINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x90))
+#define rLCD_YCbCr2_SCAL	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x94))
+#define rLCD_YCbCr2_DISPINFO	(*(volatile unsigned long *)AK98_DISPLAY_REG(0x98))
+#define rLCD_RGBOFFSET		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xA8))
+#define rLCD_RGBSIZE		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xAC))
+#define rLCD_DISPSIZE		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xB0))
+#define rLCD_COMM2		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xB4))
+#define rLCD_OP			(*(volatile unsigned long *)AK98_DISPLAY_REG(0xB8))
+#define rLCD_STAT		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xBC))
+#define rLCD_INTEN		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xC0))
+#define rLCD_SOFTCON		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xC8))
+#define rTV_IFCON		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xCC))
+#define rLCD_CLKCON		(*(volatile unsigned long *)AK98_DISPLAY_REG(0xE8))
+/* SPI1 SPI2 Controllers */
+#define rSPI1_CON		(*(volatile unsigned long *)AK98_SPI1_REG(0x00))
+#define rSPI1_STAT		(*(volatile unsigned long *)AK98_SPI1_REG(0x04))
+#define rSPI1_INTEN		(*(volatile unsigned long *)AK98_SPI1_REG(0x08))
+#define rSPI1_COUNT		(*(volatile unsigned long *)AK98_SPI1_REG(0x0C))
+#define rSPI1_TXBUF		(*(volatile unsigned long *)AK98_SPI1_REG(0x10))
+#define rSPI1_RXBUF		(*(volatile unsigned long *)AK98_SPI1_REG(0x14))
+#define rSPI1_OUTDATA		(*(volatile unsigned long *)AK98_SPI1_REG(0x18))
+#define rSPI1_INDATA		(*(volatile unsigned long *)AK98_SPI1_REG(0x1C))
+#define rSPI1_TIMEOUT		(*(volatile unsigned long *)AK98_SPI1_REG(0x20))
+#define rSPI2_CON		(*(volatile unsigned long *)AK98_SPI2_REG(0x00))
+#define rSPI2_STAT		(*(volatile unsigned long *)AK98_SPI2_REG(0x04))
+#define rSPI2_INTEN		(*(volatile unsigned long *)AK98_SPI2_REG(0x08))
+#define rSPI2_COUNT		(*(volatile unsigned long *)AK98_SPI2_REG(0x0C))
+#define rSPI2_TXBUF		(*(volatile unsigned long *)AK98_SPI2_REG(0x10))
+#define rSPI2_RXBUF		(*(volatile unsigned long *)AK98_SPI2_REG(0x14))
+#define rSPI2_OUTDATA		(*(volatile unsigned long *)AK98_SPI2_REG(0x18))
+#define rSPI2_INDATA		(*(volatile unsigned long *)AK98_SPI2_REG(0x1C))
+#define rSPI2_TIMEOUT		(*(volatile unsigned long *)AK98_SPI2_REG(0x20))
+/* MMC/SD controller */
+#define rSD_CLKCON		(*(volatile unsigned long *)AK98_MMC_REG(0x04))
+#define rSD_COMMARG		(*(volatile unsigned long *)AK98_MMC_REG(0x08))
+#define rSD_COMM		(*(volatile unsigned long *)AK98_MMC_REG(0x0C))
+#define rSD_COMMRESP		(*(volatile unsigned long *)AK98_MMC_REG(0x10))
+#define rSD_RESP1		(*(volatile unsigned long *)AK98_MMC_REG(0x14))
+#define rSD_RESP2		(*(volatile unsigned long *)AK98_MMC_REG(0x18))
+#define rSD_RESP3		(*(volatile unsigned long *)AK98_MMC_REG(0x1C))
+#define rSD_RESP4		(*(volatile unsigned long *)AK98_MMC_REG(0x20))
+#define rSD_DATATIMER		(*(volatile unsigned long *)AK98_MMC_REG(0x24))
+#define rSD_DATALEN		(*(volatile unsigned long *)AK98_MMC_REG(0x28))
+#define rSD_DATACON		(*(volatile unsigned long *)AK98_MMC_REG(0x2C))
+#define rSD_DATACOUNT		(*(volatile unsigned long *)AK98_MMC_REG(0x30))
+#define rSD_STAT		(*(volatile unsigned long *)AK98_MMC_REG(0x34))
+#define rSD_INTEN		(*(volatile unsigned long *)AK98_MMC_REG(0x38))
+#define rSD_DMAMOD		(*(volatile unsigned long *)AK98_MMC_REG(0x3C))
+#define rSD_CPUMOD		(*(volatile unsigned long *)AK98_MMC_REG(0x40))
+/* SDIO controller */
+#define rSDIO_CLKCON		(*(volatile unsigned long *)AK98_SDIO_REG(0x04))
+#define rSDIO_COMMARG		(*(volatile unsigned long *)AK98_SDIO_REG(0x08))
+#define rSDIO_COMM		(*(volatile unsigned long *)AK98_SDIO_REG(0x0C))
+#define rSDIO_COMMRESP		(*(volatile unsigned long *)AK98_SDIO_REG(0x10))
+#define rSDIO_RESP1		(*(volatile unsigned long *)AK98_SDIO_REG(0x14))
+#define rSDIO_RESP2		(*(volatile unsigned long *)AK98_SDIO_REG(0x18))
+#define rSDIO_RESP3		(*(volatile unsigned long *)AK98_SDIO_REG(0x1C))
+#define rSDIO_RESP4		(*(volatile unsigned long *)AK98_SDIO_REG(0x20))
+#define rSDIO_DATATIMER		(*(volatile unsigned long *)AK98_SDIO_REG(0x24))
+#define rSDIO_DATALEN		(*(volatile unsigned long *)AK98_SDIO_REG(0x28))
+#define rSDIO_DATACON		(*(volatile unsigned long *)AK98_SDIO_REG(0x2C))
+#define rSDIO_DATACOUNT		(*(volatile unsigned long *)AK98_SDIO_REG(0x30))
+#define rSDIO_STAT		(*(volatile unsigned long *)AK98_SDIO_REG(0x34))
+#define rSDIO_INTEN		(*(volatile unsigned long *)AK98_SDIO_REG(0x38))
+#define rSDIO_DMAMOD		(*(volatile unsigned long *)AK98_SDIO_REG(0x3C))
+#define rSDIO_CPUMOD		(*(volatile unsigned long *)AK98_SDIO_REG(0x40))
+#endif/*_AK98_ADDR_H_*/
diff --git a/arch/arm/mach-ak98/include/mach/ak880x_freq.h b/arch/arm/mach-ak98/include/mach/ak880x_freq.h
new file mode 100644
index 00000000000..52d2e02e56f
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak880x_freq.h
@@ -0,0 +1,21 @@
+#ifndef __ARCH_ARM_MACH_AK88_LIB_BASE_H__
+#define __ARCH_ARM_MACH_AK88_LIB_BASE_H__
+
+/*
+ freq,clock,gpio,sharepin
+*/
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+void ak880x_sdelay(int s_time);
+void ak880x_msdelay(int ms_time);
+void ak880x_usdelay(int us_time);
+
+unsigned long ak880x_pll1freq_get(void);
+unsigned long ak880x_cpufreq_get(void);
+unsigned long ak880x_asicfreq_get(void);
+
+unsigned long ak780x_cpufreq_get(void);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/ak98-gpio.h b/arch/arm/mach-ak98/include/mach/ak98-gpio.h
new file mode 100755
index 00000000000..01d914ea5f1
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak98-gpio.h
@@ -0,0 +1,182 @@
+/*************************************************************************
+*   Filename: arch/arm/mach-ak98/include/mach/gpio.h
+*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+**************************************************************************/
+
+#ifndef _ATHENA_GPIO_H_
+#define _ATHENA_GPIO_H_ 
+
+#include "map.h"
+#include <linux/gpio.h>
+#include <mach/gpio.h>
+
+#ifdef CONFIG_AK9801_ATHENA
+	#define CONFIG_AK9801
+#endif
+
+#ifdef CONFIG_AK9805_TV908
+	#define CONFIG_AK9805
+#endif
+
+#ifdef CONFIG_AK9805_MP5
+	#define CONFIG_AK9805
+#endif
+
+
+
+#define GPIO_UPLIMIT			116
+#define MCGPIO_UPLIMIT			19
+
+
+
+#define	GPIO_PIN_MODE_GPIO		0
+#define	GPIO_PIN_MODE_INT		1
+
+
+#define	ATTR_FIXED_1			1
+#define	ATTR_FIXED_0			0
+#define	PIN_ATTE_LINE			6
+
+#define GPIO_ATTR_UNSUPPORTED   0xffff
+#define END_FLAG                0xff
+#define INVALID_GPIO			0xfe
+
+
+
+/******************  access gpio register addr **********************/
+#define AK98_GPIO_DIR1			(AK98_VA_SYSCTRL + 0x007C)
+#define AK98_GPIO_DIR2			(AK98_VA_SYSCTRL + 0x0084)
+#define AK98_GPIO_DIR3			(AK98_VA_SYSCTRL + 0x008C)
+#define AK98_GPIO_DIR4			(AK98_VA_SYSCTRL + 0x0094)
+#define AK98_GPIO_DIR5			(AK98_VA_SYSCTRL + 0x011C)
+
+#define AK98_GPIO_OUT1			(AK98_VA_SYSCTRL + 0x0080)  
+#define AK98_GPIO_OUT2			(AK98_VA_SYSCTRL + 0x0088) 
+#define AK98_GPIO_OUT3			(AK98_VA_SYSCTRL + 0x0090)  
+#define AK98_GPIO_OUT4			(AK98_VA_SYSCTRL + 0x0098)
+#define AK98_GPIO_OUT5			(AK98_VA_SYSCTRL + 0x0118)
+
+#define AK98_GPIO_IN1         	(AK98_VA_SYSCTRL + 0x00BC) 
+#define AK98_GPIO_IN2         	(AK98_VA_SYSCTRL + 0x00C0) 
+#define AK98_GPIO_IN3         	(AK98_VA_SYSCTRL + 0x00C4)  
+#define AK98_GPIO_IN4        	(AK98_VA_SYSCTRL + 0x00C8)
+#define AK98_GPIO_IN5       	(AK98_VA_SYSCTRL + 0x0124)
+
+#define AK98_GPIO_INTEN1        (AK98_VA_SYSCTRL + 0x00E0) 
+#define AK98_GPIO_INTEN2        (AK98_VA_SYSCTRL + 0x00E4) 
+#define AK98_GPIO_INTEN3        (AK98_VA_SYSCTRL + 0x00E8) 
+#define AK98_GPIO_INTEN4        (AK98_VA_SYSCTRL + 0x00EC) 
+
+#define AK98_GPIO_INTPOL1      	(AK98_VA_SYSCTRL + 0x00F0)
+#define AK98_GPIO_INTPOL2      	(AK98_VA_SYSCTRL + 0x00F4) 
+#define AK98_GPIO_INTPOL3      	(AK98_VA_SYSCTRL + 0x00F8) 
+#define AK98_GPIO_INTPOL4      	(AK98_VA_SYSCTRL + 0x00FC) 
+
+#define AK98_PPU_PPD1           (AK98_VA_SYSCTRL + 0x009C)
+#define AK98_PPU_PPD2           (AK98_VA_SYSCTRL + 0x00A0)
+#define AK98_PPU_PPD3           (AK98_VA_SYSCTRL + 0x00A4)
+#define AK98_PPU_PPD4           (AK98_VA_SYSCTRL + 0x00A8)
+#define AK98_MCGPIO_PPU_PPD		(AK98_VA_SYSCTRL + 0x0120)
+
+#define AK98_IO_CON1            (AK98_VA_SYSCTRL + 0x00D4)
+#define AK98_IO_CON2            (AK98_VA_SYSCTRL + 0x00D8)
+
+#define AK98_SHAREPIN_CON1		(AK98_VA_SYSCTRL + 0x0078)
+#define AK98_SHAREPIN_CON2		(AK98_VA_SYSCTRL + 0x0074)
+
+#define AK98_WGPIO_POLARITY		(AK98_VA_SYSCTRL + 0x3C)
+#define AK98_WGPIO_CLEAR		(AK98_VA_SYSCTRL + 0x40)
+#define AK98_WGPIO_ENABLE		(AK98_VA_SYSCTRL + 0x44)
+#define AK98_WGPIO_STATUS		(AK98_VA_SYSCTRL + 0x48)
+
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#define AK98_GPIO_DIR_BASE(pin)		(((pin)>>5)*8 + AK98_GPIO_DIR1 )
+#define AK98_GPIO_OUT_BASE(pin)		(((pin)>>5)*8 + AK98_GPIO_OUT1 )
+#define AK98_GPIO_IN_BASE(pin)		(((pin)>>5)*4 + AK98_GPIO_IN1 )
+#define AK98_GPIO_INTEN_BASE(pin)	(((pin)>>5)*4 + AK98_GPIO_INTEN1 )
+#define AK98_GPIO_INTPOL_BASE(pin)	(((pin)>>5)*4 + AK98_GPIO_INTPOL1 )
+#define AK98_PPU_PPD_BASE(pin)		(((pin)>>5)*4 + AK98_PPU_PPD1 )
+/* MCGPIO group */
+#define AK98_MCGPIO_DIR_BASE(pin)	(((pin)>>5)*4 + AK98_GPIO_DIR5)
+#define AK98_MCGPIO_OUT_BASE(pin)	(((pin)>>5)*4 + AK98_GPIO_OUT5)
+#define AK98_MCGPIO_IN_BASE(pin)	(((pin)>>5)*4 + AK98_GPIO_IN5)
+#define AK98_MCGPIO_PPU_PPD_BASE(pin)	(((pin)>>5)*4 + AK98_MCGPIO_PPU_PPD)
+
+
+
+
+struct gpio_sharepin_cfg {
+    T_GPIO_SHAREPIN_CFG func_module;
+	T_SHARE_CFG share_config;
+    unsigned long reg1_bit_mask;
+    unsigned long reg1_bit_value;
+    unsigned long reg2_bit_mask;
+    unsigned long reg2_bit_value;
+};
+
+typedef enum {
+	 PULLUP = 0,
+	 PULLDOWN,
+	 PULLUPDOWN,
+	 UNDEFINED
+ } T_GPIO_TYPE ;
+
+typedef enum {
+    GPIO_ATTR_IE = 1,   ///<input enable
+    GPIO_ATTR_PE,       ///<pullup/pulldown enable
+    GPIO_ATTR_SL,       ///<slew rate
+    GPIO_ATTR_DS,       ///<drive strength
+    GPIO_ATTR_PS        ///<pullup/pulldown selection
+}T_GPIO_PIN_ATTR;
+
+struct sharepin_group {
+    unsigned char gpio_start;
+    unsigned char gpio_end;
+    unsigned char bit;
+};
+
+typedef struct {
+    unsigned char gpio_start;
+    unsigned char gpio_end;
+    unsigned char bit;
+}
+T_SHARE_CFG_GPIO;
+
+struct t_gpio_wakeup_cfg {
+	unsigned char gpio_start;
+	unsigned char gpio_end;
+	unsigned char start_bit;
+};
+
+
+int g_ak98_setpin_as_gpio(unsigned int pin);
+void g_ak98_setpin_attribute(unsigned int pin, 
+	T_GPIO_PIN_ATTR attr, unsigned char enable);
+int g_ak98_gpio_pullup(unsigned int pin, unsigned char enable);
+int g_ak98_gpio_pulldown(unsigned int pin, unsigned char enable);
+
+void g_ak98_setgroup_attribute(T_GPIO_SHAREPIN_CFG mod_name);
+int g_ak98_gpio_cfgpin(unsigned int pin, unsigned int to);
+int g_ak98_gpio_setpin(unsigned int pin, unsigned int to);
+ int g_ak98_gpio_getpin(unsigned int pin);
+int g_ak98_gpio_inten(unsigned int pin, unsigned int enable);
+
+int g_ak98_gpio_intpol(unsigned int pin, unsigned int level);
+  int g_ak98_gpio_to_irq(unsigned int pin);
+  int g_ak98_irq_to_gpio(unsigned int irq);
+
+
+ int mc_ak98_setpin_as_mcgpio(unsigned int pin);
+ int mc_ak98_mcgpio_cfgpin(unsigned int pin, unsigned int to);
+ int mc_ak98_mcgpio_setpin(unsigned int pin, unsigned int to);
+  int mc_ak98_mcgpio_getpin(unsigned int pin);
+ int mc_ak98_mcgpio_pulldown(unsigned int pin, unsigned char enable);
+
+
+#endif /*_AK98_GPIO_H_*/
+
diff --git a/arch/arm/mach-ak98/include/mach/ak98_hal.h b/arch/arm/mach-ak98/include/mach/ak98_hal.h
new file mode 100644
index 00000000000..b9db5bfd358
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak98_hal.h
@@ -0,0 +1,162 @@
+#ifndef AK98_HAL_H
+#define AK98_HAL_H
+
+#include <mach/gpio.h>
+#include <linux/delay.h>
+
+typedef struct {
+    void    *pAddress0800;   // @field Start of 0x08000000 - mapped
+    void    *pAddress2002E;   // @field Start of 0x2002E000 - mapped
+    void    *pAddress2002D;   //@field Start of 0x2002D000 - mapped
+}REG_ADDR, *PREG_ADDR;
+
+//pAddress0800   0x08000000-0x080000FF
+#define CLK_DIV_REG2                  0x0008
+#define CLOCK_CTRL_REG1               0x000C
+#define MULTIPLE_FUN_CTRL_REG1        0x0058
+#define ANALOG_CTRL_REG3              0x005C
+#define ANALOG_CTRL_REG4              0x0064
+#define ANALOG_CTRL_REG1_WRITE        0x012C
+#define ANALOG_CTRL_REG2_WRITE        0x0130
+#define ANALOG_CTRL_REG1_READ         0x0130
+#define ANALOG_CTRL_REG2_READ         0x0134
+
+//pAddress2002E  0x2002E000-0x2002E00F
+#define DAC_CONFIG_REG                0x0000
+#define I2S_CONFIG_REG                0x0004
+#define CPU_DATA_REG                  0x0008
+
+//pAddress2002D 0x2002D000-0x2002D00F
+#define ADC2MODE_CFG_REG              0x0000
+#define WORD_LENGTH_MASK (0XF << 8)
+#define I2S_EN           (1 << 4)
+#define CH_POLARITY_SEL  (1 << 3)
+#define HOST_RD_INT_EN   (1 << 2)
+#define ADC2MODE_L2_EN   (1 << 1)
+#define ADC2_CTRL_EN     (1 <<0)
+
+//CLK_DIV_REG2(0x08000008)
+#define DAC_GATE        (1 << 26)
+#define ADC2_GATE       (1 << 25)
+#define DAC_RST         (1 << 24)
+#define ADC2_RST        (1 << 23)
+#define DAC_CLK_EN      (1 << 21)
+#define MASK_CLKDIV2_DAC_DIV     (0xFF << 13)
+#define CLKDIV2_DAC_DIV(val)     (((val)&0xFF) << 13)
+#define ADC2_CLK_EN      (1 << 12)
+#define MASK_CLKDIV2_ADC2_DIV    (0xFF << 4)
+#define CLKDIV2_ADC2_DIV(val)    (((val)&0xFF) << 4)
+#define ADC2_DIV         4
+
+
+//CLOCK_CTRL_REG1(0x0800000C)
+#define DAC_SOFT_RST      (1 << 17)
+#define ADC2Ctrl_SOFT_RST (1 << 16)
+#define L2_CLK_CTRL_EN   (1 << 3)
+#define PCM_CLK_CTRL_EN  (1 << 2)
+#define DAC_CLK_CTRL_EN  (1 << 1)
+#define ADC2_CLK_CTRL_EN (1 << 0)
+
+//MULTIPLE_FUN_CTRL_REG1(0x08000058)
+#define IN_DAAD_EN      (1 << 23) //ENABLE INTERNAL DAC ADC via i2s
+
+//ANALOG_CTRL_REG3(0x0800005C)
+#define PD_DAOUTL       (1 << 11)
+#define PD_DAOUTR       (1 << 10)
+#define MICIN_BYPASS    (1 << 9)
+#define LINEIN_BYPASS   (1 << 8)
+
+//ANALOG_CTRL_REG4(0x08000064)
+#define ANALOG_CTRL4_OSR_MASK       (0x7 << 14)
+#define ANALOG_CTRL4_OSR(value)     (((value)&0x7) << 14)
+#define DAC_EN                      (1 << 13)
+#define ADC_OSR                     12
+
+//ANALOG_CTRL_REG1(read(0x08000130)/write(0x0800012c))
+#define MUXDA_R        (1 << 31)
+#define MUXDA_L        (1 << 30)
+#define PD_MICP        (1 << 22)
+#define PD_MICN        (1 << 21)
+#define PD2_HP         (1 << 20)
+#define PD1_HP         (1 << 19)
+#define PRE_EN1        (1 << 18)
+#define PRE_EN2        (1 << 17)
+#define TRIMP_HP       (1 << 16)
+#define TRIMN_HP       (1 << 15)
+#define PD_OP          (1 << 11)
+#define PD_CK          (1 << 10)
+#define PTM_D_CHG_EN   (1 << 5)
+#define VREF_CHG_FAST  (1 << 4)
+#define PD_VCM3        (1 << 3)
+#define PL_VCM2        (1 << 2)  //pull down to ground.
+#define PD_VCM2        (1 << 1)  // power off 
+#define PD_REF         (1 << 0)
+
+//ANALOG_CTRL_REG2(read(0x08000134)/write(0x08000130))
+#define PD_ADC2          (1 << 0)
+#define PD_ADC3          (1 << 1)
+
+//DAC_CONFIG_REG(0x2002E000)
+#define ARM_INT        (1 << 3)  //ARM interrupt enable
+#define MUTE           (1 << 2)  // repeat to sent the Last data to DAC
+#define FORMAT         (1 << 4)    //  1 is used memeory saving format.
+#define L2_EN          (1 << 1)
+#define DAC_CTRL_EN    (1 << 0)
+
+//I2S_CONFIG_REG(0x2002E004)
+#define LR_CLK          (1 << 6)
+#define POLARITY_SEL    (1 << 5)  
+#define I2S_CONFIG_WORDLENGTH_MASK              (0x1F << 0)
+
+/////////////HP_IN  ADC23_IN
+#define SOURCE_DAC           (0b001)
+#define SOURCE_LINEIN        (0b010)
+#define SOURCE_MIC           (0b100)
+#define SIGNAL_SRC_MUTE      0
+#define SIGNAL_SRC_MAX       (SOURCE_DAC|SOURCE_LINEIN|SOURCE_MIC)
+
+
+#define HEADPHONE_GAIN_MIN    0
+#define HEADPHONE_GAIN_MAX    8
+#define LINEIN_GAIN_MIN       0
+#define LINEIN_GAIN_MAX       15
+#define MIC_GAIN_MIN          0
+#define MIC_GAIN_MAX          7
+
+struct ak98pcm_platform_data
+{
+	struct gpio_info hpdet_gpio;
+	struct gpio_info spk_down_gpio;
+	struct gpio_info hpmute_gpio;
+	int hp_on_value;
+	int hpdet_irq;
+	int bIsHPmuteUsed;
+	int hp_mute_enable_value;
+	int bIsMetalfixed;
+};
+
+void AK98_DAC_Open(void);
+void AK98_DAC_Close(void);
+void AK98_DAC_Set_SampleRate(unsigned long samplerate);
+void AK98_DAC_Set_Channels(unsigned long chnl);
+void AK98_Poweron_HP(bool bOn);
+void AK98_Set_HPGain(unsigned long gain);
+void AK98_Set_HP_In(unsigned long signal);
+void AK98_ADC23_Open(void);
+void AK98_ADC23_Close(void);
+void AK98_ADC23_Set_SampleRate(unsigned long samplerate);
+void AK98_Set_MicGain(unsigned long gain);
+void AK98_Set_ADC23_In(unsigned long signal);
+void AK98_ADC23_Set_Channels(unsigned long chnl);
+void AK98_Set_LineinGain(unsigned long gain);
+void AK98_Linein_PowerOn(bool bOn);
+void AK98_Mic_PowerOn(bool bOn);
+void AK98_DAC_Bypass(bool bTrue);
+void AK98_MicIn_Bypass(bool bTrue);
+void AK98_LineIn_Bypass(bool bTrue);
+void AK98_Set_Bypass(unsigned long signal);
+void AK98_Poweron_VCM_REF(bool bOn);
+void AK98_Set_SrcPower(int src,int addr,int *CurSrc);
+void AK98_Poweron_Speaker(unsigned int pin, bool bOn);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/ak98_mci.h b/arch/arm/mach-ak98/include/mach/ak98_mci.h
new file mode 100755
index 00000000000..8aac5a2f048
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak98_mci.h
@@ -0,0 +1,200 @@
+/*
+ *  linux/drivers/mmc/host/ak98_mci.h - AK98 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define AK98MCICLOCK		0x004
+#define MMC_CLK_DIVL(x)		((x) & 0xff)
+#define MMC_CLK_DIVH(x)		(((x) & 0xff) << 8)
+#define MCI_CLK_ENABLE		(1 << 16)
+#define MCI_CLK_PWRSAVE		(1 << 17)
+#define MCI_FAIL_TRIGGER	(1 << 19)
+#define MCI_ENABLE		(1 << 20)
+
+#define AK98MCIARGUMENT		0x008
+#define AK98MCICOMMAND		0x00c
+#define MCI_CPSM_ENABLE		(1 << 0)
+#define MCI_CPSM_CMD(x)		(((x) & 0x3f) << 1)
+#define MCI_CPSM_RESPONSE	(1 << 7)
+#define MCI_CPSM_LONGRSP	(1 << 8)
+#define MCI_CPSM_PENDING	(1 << 9)
+#define MCI_CPSM_RSPCRC_NOCHK	(1 << 10)
+#define MCI_CPSM_WITHDATA	(1 << 11)
+
+#define AK98MCIRESPCMD		0x010
+#define AK98MCIRESPONSE0	0x014
+#define AK98MCIRESPONSE1	0x018
+#define AK98MCIRESPONSE2	0x01c
+#define AK98MCIRESPONSE3	0x020
+#define AK98MCIDATATIMER	0x024
+#define AK98MCIDATALENGTH	0x028
+#define AK98MCIDATACTRL		0x02c
+#define MCI_DPSM_ENABLE		(1 << 0)
+#define MCI_DPSM_DIRECTION	(1 << 1)
+#define MCI_DPSM_STREAM		(1 << 2)
+#define MCI_DPSM_BUSMODE(x)	(((x) & 0x3) << 3)
+#define MCI_DPSM_BLOCKSIZE(x)	(((x) & 0xfff) << 16)
+
+#define AK98MCIDATACNT		0x030
+#define AK98MCISTATUS		0x034
+#define MCI_RESPCRCFAIL		(1 << 0)
+#define MCI_DATACRCFAIL		(1 << 1)
+#define MCI_RESPTIMEOUT		(1 << 2)
+#define MCI_DATATIMEOUT		(1 << 3)
+#define MCI_RESPEND		(1 << 4)
+#define MCI_CMDSENT		(1 << 5)
+#define MCI_DATAEND		(1 << 6)
+#define MCI_DATABLOCKEND	(1 << 7)
+#define MCI_STARTBIT_ERR	(1 << 8)
+#define MCI_CMDACTIVE		(1 << 9)
+#define MCI_TXACTIVE		(1 << 10)
+#define MCI_RXACTIVE		(1 << 11)
+#define MCI_FIFOFULL		(1 << 12)
+#define MCI_FIFOEMPTY		(1 << 13)
+#define MCI_FIFOHALFFULL	(1 << 14)
+#define MCI_FIFOHALFEMPTY	(1 << 15)
+#define MCI_DATATRANS_FINISH	(1 << 16)
+#define MCI_SDIOINT		(1 << 17)
+
+#define AK98MCIMASK		0x038
+#define MCI_RESPCRCFAILMASK	(1 << 0)
+#define MCI_DATACRCFAILMASK	(1 << 1)
+#define MCI_RESPTIMEOUTMASK	(1 << 2)
+#define MCI_DATATIMEOUTMASK	(1 << 3)
+#define MCI_RESPENDMASK		(1 << 4)
+#define MCI_CMDSENTMASK		(1 << 5)
+#define MCI_DATAENDMASK		(1 << 6)
+#define MCI_DATABLOCKENDMASK	(1 << 7)
+#define MCI_STARTBIT_ERRMASK	(1 << 8)
+#define MCI_CMDACTIVEMASK	(1 << 9)
+#define MCI_TXACTIVEMASK	(1 << 10)
+#define MCI_RXACTIVEMASK	(1 << 11)
+#define MCI_FIFOFULLMASK	(1 << 12)
+#define MCI_FIFOEMPTYMASK	(1 << 13)
+#define MCI_FIFOHALFFULLMASK	(1 << 14)
+#define MCI_FIFOHALFEMPTYMASK	(1 << 15)
+#define MCI_DATATRANS_FINISHMASK	(1 << 16)
+#define MCI_SDIOINTMASK		(1 << 17)
+
+#define AK98MCIDMACTRL		0x03c
+#define MCI_DMA_BUFEN		(1 << 0)
+#define MCI_DMA_ADDR(x)		(((x) & 0x7fff) << 1)
+#define MCI_DMA_EN		(1 << 16)
+#define MCI_DMA_SIZE(x)		(((x) & 0x7fff) << 17)
+
+#define AK98MCIFIFO		0x040
+
+#define MCI_CMDIRQMASKS \
+	(MCI_CMDSENTMASK|MCI_RESPENDMASK|		\
+	 MCI_RESPCRCFAILMASK|MCI_RESPTIMEOUTMASK)
+
+#define MCI_DATAIRQMASKS \
+	(MCI_DATAEND|MCI_DATABLOCKENDMASK|		\
+	 MCI_DATACRCFAILMASK|MCI_DATATIMEOUTMASK|	\
+	 MCI_STARTBIT_ERRMASK)
+
+/*
+ * The size of the FIFO in bytes.
+ */
+#define MCI_FIFOSIZE	4
+#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
+
+#define NR_SG		16
+
+#define L2BASE		0x2002c000
+#define L2FIFO_DMACONF	0x80
+#define L2FIFO_CONF1	0x88
+#define L2FIFO_ASSIGN1	0x90
+#define L2FIFO_INTEN	0x9c
+
+#define L2FIFOBASE	0x48000000
+#define L2ADDR(n)	(L2FIFOBASE + 512 * (n))
+#define MCI_L2FIFO_NUM	2	/* #6 l2fifo */
+#define MCI_L2FIFO_SIZE	512
+
+#define L2DMA_MAX_SIZE	(64*255)
+
+struct ak98_mci_platform_data {
+	int gpio_cd;		/* card detect pin */
+	int gpio_wp;		/* write protect pin */
+};
+
+struct clk;
+
+struct ak98_mci_host {
+	void __iomem		*base;
+	struct mmc_request	*mrq;
+	struct mmc_command	*cmd;
+	struct mmc_data		*data;
+	struct mmc_host		*mmc;
+	struct clk		*clk;
+	int			gpio_cd;
+	int			gpio_wp;
+	int			irq_mci;
+	int			irq_cd;
+	int			irq_cd_type;
+
+	unsigned int		data_xfered;
+
+	spinlock_t		lock;
+
+#if 0
+	unsigned int		mclk;
+	unsigned int		cclk;
+	u32			pwr;
+#else
+	unsigned char		bus_mode;
+	unsigned char		bus_width;
+	unsigned long		bus_clkrate;
+	unsigned long		asic_clkrate;
+	unsigned char		power_mode;
+#endif
+	struct ak98_mci_platform_data *plat;
+
+#if 0
+	u8			hw_designer;
+	u8			hw_revision:4;
+#endif
+
+#if 0
+	struct timer_list	timer;
+	unsigned int		oldstat;
+#endif
+
+	unsigned int		sg_len;
+
+	/* pio stuff */
+	struct scatterlist	*sg_ptr;
+	unsigned int		sg_off;
+	unsigned int		size;
+
+#if 0
+	struct regulator	*vcc;
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+		struct notifier_block	freq_transition;
+		struct semaphore freq_lock;
+		
+#endif
+
+
+	struct timer_list	detect_timer;
+
+	void __iomem		*l2base;
+	void __iomem		*l2fifo;
+};
+
+void ak98_mci_init_sg(struct ak98_mci_host *host, struct mmc_data *data);
+
+int ak98_mci_next_sg(struct ak98_mci_host *host);
+
+char *ak98_mci_kmap_atomic(struct ak98_mci_host *host, unsigned long *flags);
+
+void ak98_mci_kunmap_atomic(struct ak98_mci_host *host, void *buffer, unsigned long *flags);
+
diff --git a/arch/arm/mach-ak98/include/mach/ak98_sdio.h b/arch/arm/mach-ak98/include/mach/ak98_sdio.h
new file mode 100755
index 00000000000..fc7fec1cc12
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak98_sdio.h
@@ -0,0 +1,20 @@
+
+/*
+ *  linux/drivers/mmc/host/ak98_mci.h - AK98 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __AK98_SDIO_H__
+#define __AK98_SDIO_H__
+
+#include "ak98_mci.h"
+
+#define AK98SDIOINTRCTR		0x000
+#define SDIO_INTR_CTR_ENABLE	(1 << 8)
+#define SDIO_INTR_ENABLE	(1 << 17)
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/ak_sensor.h b/arch/arm/mach-ak98/include/mach/ak_sensor.h
new file mode 100755
index 00000000000..2ab1c253f5b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ak_sensor.h
@@ -0,0 +1,23 @@
+#ifndef _AK98_SENSOR_H_
+#define _AK98_SENSOR_H_
+
+#define SENSOR_ACCELEROMETER	"1"
+#define SENSOR_MAGNETIC_FIELD	"2"
+#define SENSOR_ORIENTATION		"3"
+
+struct sensor_t {
+	char *name;
+	char *vendor;
+	char *type;
+	char *maxRange;		/* maxRange/10 */
+	char *resolution;	/* resolution/10000 */
+	char *power;		/* power/1000 A */
+	char *dir;
+	int exist;
+};
+
+struct sensor_platform_data {
+	struct sensor_t *sensors;
+};
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/bat.h b/arch/arm/mach-ak98/include/mach/bat.h
new file mode 100755
index 00000000000..54fbcb8560e
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/bat.h
@@ -0,0 +1,71 @@
+#ifndef __AK98_BAT_H_
+#define __AK98_BAT_H_ __FILE__
+
+#include <mach/gpio.h>
+#include <mach/adc1.h>
+
+struct bat_gpio{
+
+	int active;					/* active value */
+	int irq;						/* use for ac in or out irq */
+	struct gpio_info pindata;		/* battery gpios info */
+
+};
+
+struct bat_info{
+	int charge_full_pin;	/* use for juge if battery charge full */ 									  
+	int voltage_sample;		/* read how many voltge sample */	
+	int power_down_level;	/* if (capacity<=power_down_level), power down */
+	int max_voltage;		/* max battery voltage  */
+    int min_voltage;		/* min battery voltage  */
+    int full_capacity;
+    int charge_max_time;
+};
+
+struct bat_ad4{
+	unsigned int sample_rate;		/* the same as touch screen */
+	unsigned int wait_time;			/* the same as touch screen */
+	int up_resistance;				/* read ad4 voltage resistance */
+	int dw_resistance;
+	int voltage_correct;			/* correct voltage from adc1-4*/
+	int adc_avdd;					/* adc avdd */
+	int adc_poweroff;				/* poweroff adc value */
+};
+
+struct bat_charge_bight{
+	int *capacity;
+	int *time;
+	int	length;
+	int points;
+};
+
+struct bat_discharge_bight{
+	int *capacity;
+	int *voltage;
+	int length;
+	int points;
+};
+
+struct bat_charge_cv_bight{
+	int *capacity;
+	int *voltage;
+	int length;
+	int points;
+};
+
+struct ak98_bat_mach_info {
+
+	void (* gpio_init) (const struct gpio_info *);
+	struct bat_gpio usb_gpio;
+	struct bat_gpio ac_gpio;
+	struct bat_gpio state_gpio;
+	struct bat_info bat_mach_info;
+	struct bat_ad4  bat_adc;
+	struct bat_charge_bight charge;
+	struct bat_charge_cv_bight charge_cv;
+	struct bat_discharge_bight discharge;
+};
+
+#endif				/* __AK98_BAT_H_ */
+
+
diff --git a/arch/arm/mach-ak98/include/mach/clock.h b/arch/arm/mach-ak98/include/mach/clock.h
new file mode 100644
index 00000000000..b1dd7ec4b25
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/clock.h
@@ -0,0 +1,99 @@
+/* 
+ * linux/include/asm-arm/arch-ak98/clock.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _ANYKA_CLK_H_
+#define _ANYKA_CLK_H_
+
+/* reset & clock control */
+#define AK_HWMMD_CODEC		0
+#define AK_CAMIF		1
+#define AK_SPI_MMC_UART1	2
+#define AK_DISPLAY_CTRL		3
+#define AK_AUDIO_PROCSESSOR	4
+#define AK_USBOTG_CTRL		5
+#define AK_H264_DECODER		6
+#define AK_USBFS_HOST_CTRL	7
+#define AK_SDIO_UART2_UART3	8
+#define AK_CLK_RESERVED0	9
+#define AK_MEMORY_CTRL		10
+#define AK_MOTION_ESTIMATION	11
+#define AK_2DGRAPHICS_ACC	12
+#define AK_NANDFLASH_CTRL	13
+#define AK_CLK_RESERVED1	14
+#define AK_L2CTRL_UART0		15
+
+struct clk {
+	struct list_head list;
+	struct module *owner;
+	struct clk *parent;
+	const char *name;
+	int id;
+	int usage;
+	unsigned long rate;
+	unsigned long ctrlbit;
+
+	int (*enable) (struct clk *, int enable);
+	int (*set_rate) (struct clk * c, unsigned long rate);
+	unsigned long (*get_rate) (struct clk * c);
+	int (*set_parent) (struct clk * c, struct clk * parent);
+};
+
+/* core clock support */
+extern struct clk clk_xtal_12M;
+extern struct clk clk_xtal_25M;
+extern struct clk clk_xtal_27M;
+extern struct clk clk_xtal_32K;
+extern struct clk clk_pll;
+extern struct clk clk_spll;
+extern struct clk clk_asic;
+extern struct clk clk_mem;
+extern struct clk clk_cpu;
+
+/* other clocks which may be registered by board support */
+extern struct clk ap_clk;
+extern struct clk adc1_clk;
+extern struct clk adc2_clk;
+extern struct clk dac_clk;
+extern struct clk camif_clk;
+extern struct clk lcd_clk;
+extern struct clk spi_clk;
+extern struct clk mci_clk;
+extern struct clk udc_clk;
+extern struct clk uart4_clk;
+extern struct clk i2c_clk;
+
+typedef enum {
+	CPU_MODE_NORMAL,
+	CPU_MODE_CPU3X,
+	CPU_MODE_SPECIAL,
+	CPU_MODE_LOW,
+} ak98_cpu_mode_t;
+
+#define AK98_CLK_DIV_1_CPU3X	(1 << 28)
+#define AK98_CLK_DIV_1_LOW	(1 << 22)
+#define AK98_CLK_DIV_1_SPECIAL	(1 << 21)
+#define AK98_CLK_DIV_1_CPU2X	(1 << 15)
+
+
+#define MHz	1000000UL
+#define AK98_MIN_PLL_CLK	(180 * MHz)
+
+bool ak98_cpu_is_3x_mode(void);
+bool ak98_cpu_is_2x_mode(void);
+bool ak98_cpu_is_special_mode(void);
+bool ak98_cpu_is_low_clock_mode(void);
+bool ak98_cpu_is_normal_mode(void);
+ak98_cpu_mode_t ak98_get_cpu_mode(void);
+unsigned long ak98_get_asic_clk(void);
+unsigned long ak98_get_mem_clk(void);
+unsigned long ak98_get_cpu_clk(void);
+ak98_cpu_mode_t ak98_get_cpu_mode(void);
+unsigned long ak98_get_pll_clk(void);
+unsigned long ak98_get_clk168m_clk(void);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/cpufreq.h b/arch/arm/mach-ak98/include/mach/cpufreq.h
new file mode 100755
index 00000000000..d951d8afb47
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/cpufreq.h
@@ -0,0 +1,31 @@
+#ifndef __CPUFREQ_H__

+#define __CPUFREQ_H__

+

+#include <linux/cpufreq.h>

+#include <mach/l2_exebuf.h>

+

+#define MEM_CLK_DIV     0x7

+#define ASIC_CLK_DIV    0x7

+

+#define PLL_CLK_MIN     180

+#define PLL_CLK_MAX     (PLL_CLK_MIN + 4*(0x3F))

+

+//#define CPUFREQ_DEBUG

+

+/* clock divider register */

+#define PLL_CHANGE_ENA          (1 << 12)

+#define CLOCK_ASIC_MEM_ENA      (1 << 14)

+

+struct cpufreq_mode_clkdiv {

+    T_OPERATION_MODE mode_name;

+    unsigned int pll_sel;

+    unsigned int clk168_div;

+    unsigned int cpu_div;

+    unsigned int mem_div;

+    unsigned int asic_div;

+    unsigned int low_clock;

+    unsigned int is_3x;

+};

+

+

+#endif	/* __CPUFREQ_H__ */

diff --git a/arch/arm/mach-ak98/include/mach/debug-macro.S b/arch/arm/mach-ak98/include/mach/debug-macro.S
new file mode 100644
index 00000000000..a5edc1a262b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/debug-macro.S
@@ -0,0 +1,108 @@
+/* linux/include/asm-arm/arch-ak98/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <mach/map.h>
+
+	.macro	addruart,	rx
+	mrc	p15, 0, \rx, c1, c0
+
+	@ init uart for output, no need init everytime
+	@ share-pin settting
+	@tst	\rx, #1
+	@ldreq	r11, =(AK98_PA_SYSCTRL+0x78)
+	@ldrne	r11, =(AK98_VA_SYSCTRL+0x78)
+	@ldr	r12, [r11]
+	@orr	r12, r12, #(0x1<<9)
+	@str	r12, [r11]
+
+	@ uart buf setting
+	@tst     \rx, #1
+	@ldreq   r11, =(AK98_PA_L2CTRL+0x40)    @ mmu disabled
+	@ldrne   r11, =(AK98_VA_L2CTRL+0x40)    @ mmu enabled
+	@ldr     r12, [r11]
+	@orr     r12, r12, #(0x1<<11)
+	@str     r12, [r11]
+	
+	@uart config (ie: baudrate)
+	@tst     \rx, #1
+	@ldreq   r11, =(AK98_PA_UART+0x00)     @0x20026000
+	@ldrne   r11, =(AK98_VA_UART+0x00)
+	@ldr     r12, [r11]
+	@orr     r12, r12, #(0x1<<21)
+	@orr     r12, r12, #(0x3<<28)
+	@str     r12, [r11]
+	
+	@ uart tx threshold setting
+	@tst     \rx, #1
+	@ldreq   r11, =(AK98_PA_UART+0x0C)     @0x2002600C
+	@ldrne   r11, =(AK98_VA_UART+0x0C)
+	@mov     r12, #0x0
+	@str     r12, [r11]
+	.endm
+
+	.macro	senduart,	rb,	rx
+	tst	\rx, #1
+	ldreq   r11, =AK98_PA_L2CTRL		@0x2002C08C
+	ldrne	r11, =(AK98_VA_L2CTRL+0x8C)
+	ldr     r12, [r11]
+	orr     r12, r12, #0x10000
+	str     r12, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK98_PA_L2MEM+0x1000)	@0x48001000
+	ldrne	r11, =(AK98_VA_L2MEM+0x1000)
+	@ldr    r12, ='z'
+	str     \rb, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK98_PA_L2MEM+0x103C)	@0x4800103C
+	ldrne	r11, =(AK98_VA_L2MEM+0x103C)
+	mov     r12, #0x0
+	str     r12, [r11]
+
+	tst	\rx, #1
+	ldreq	r11, =(AK98_PA_UART+0x00)	@0x20026000
+	ldrne	r11, =(AK98_VA_UART+0x00)
+	ldr     r12, [r11]
+	orr     r12, r12, #(0x1<<28)
+	str     r12, [r11]
+	
+	tst	\rx, #1
+	ldreq	r11, =(AK98_PA_UART+0x04)	@0x20026004
+	ldrne	r11, =(AK98_VA_UART+0x04)
+	ldr     r12, [r11]
+	orr     r12, r12, #(0x1<<4)
+	orr     r12, r12, #(0x1<<16)
+	str     r12, [r11]
+
+ak_loop:
+	tst	\rx, #1
+	ldreq	r11, =(AK98_PA_UART+0x04)	@0x20026004
+	ldrne	r11, =(AK98_VA_UART+0x04)
+	ldr     r12, [r11]
+	and     r12, r12, #0x80000
+	cmp     r12, #0
+	beq     ak_loop			@ FIXME
+
+	ldr     r11, =0x800
+ak_delay:
+	subs    r11, r11, #1
+	cmp     r11, #0
+	bne     ak_delay
+
+	.endm
+	
+	.macro	waituart,	rd,	rx
+	.endm
+	
+	.macro	busyuart,	rd,	rx
+	.endm
diff --git a/arch/arm/mach-ak98/include/mach/dev_reset.h b/arch/arm/mach-ak98/include/mach/dev_reset.h
new file mode 100644
index 00000000000..0cdefc8d441
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/dev_reset.h
@@ -0,0 +1,70 @@
+/*
+ * dev_reset.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DEV_RESET_H
+#define __DEV_RESET_H
+
+/**
+ * This is the register index of array reset_reg make sure dev_reset.c 
+ * reset_ctrl struct mach to it
+ */
+#define RESET_CTRL_1	0
+#define RESET_CTRL_2	1
+
+/**
+ * struct device_reset_ctrl - define the reset control info of device
+ * @dev_no:		the number of device to be reset
+ * @regdix:		the index of reset control register
+ * @ctrlbit:	the control bit of the corresponding register	
+ * @delay:		the delay time after reset device(us)
+ */
+struct device_reset_ctrl {
+	unsigned long regdix;
+	unsigned long ctrlbit;
+	unsigned long delay;
+};
+
+/**
+ * This is the struct device_reset_ctrl`s regdix, make sure correct to dev_reset.c
+ * define of reset_ctrl
+ */
+#define	DEV_USB_OTG				0
+#define	DEV_NAND				1
+#define	DEV_SPI1				2
+#define	DEV_UART1				3
+#define DEV_LCD					4
+#define DEV_RAM					5
+#define DEV_CAMERA				6
+#define DEV_H264				7
+#define DEV_ROTATION			8
+#define DEV_L2FIFO				9
+#define DEV_PCM					10
+#define DEV_DAC					11
+#define DEV_ADC2				12
+#define DEV_VIDEO				13
+#define DEV_MAC					14
+#define DEV_RMVB				15
+#define DEV_HUFFMAN				16
+#define DEV_MOTION_ESTIMATION	17
+#define DEV_H263_MPEG4			18
+#define DEV_JPEG				19
+#define DEV_MPEG2_ASP			20
+#define DEV_SPI2				21
+#define DEV_UART4				22
+#define DEV_UART3_I2C			23
+#define DEV_UART2				24
+#define DEV_SDIO				25
+#define DEV_MMC_SD				26
+#define DEV_USB_FS				27
+#define DEV_2D					28
+#define DEV_MAX					29
+
+void device_controller_reset(int dev_no);
+
+#endif	/* __DEV_RESET_H */
diff --git a/arch/arm/mach-ak98/include/mach/devices.h b/arch/arm/mach-ak98/include/mach/devices.h
new file mode 100755
index 00000000000..33aa4820fd0
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/devices.h
@@ -0,0 +1,62 @@
+#ifndef _MACH_DEVICES_H
+#define _MACH_DEVICES_H
+
+
+extern struct platform_device ak98_led_device;
+
+extern struct platform_device ak98_rtc_device;
+
+extern struct platform_device ak98_pwm0_device;
+extern struct platform_device ak98_pwm1_device;
+extern struct platform_device ak98_pwm2_device;
+extern struct platform_device ak98_pwm3_device;
+
+extern struct platform_device ak98pwm_backlight_device;
+
+extern struct platform_device ak98_uart0_device;
+extern struct platform_device ak98_uart1_device;
+extern struct platform_device ak98_uart2_device;
+extern struct platform_device ak98_uart3_device;
+
+extern struct platform_device ak98_battery_power;
+extern struct platform_device ak98_freq_policy_device;
+
+extern struct platform_device ak98_ts_device;
+extern struct platform_device ak98adc_ts_device;
+
+extern struct platform_device ak98_gpio_trkball_device;
+extern struct platform_device ak98_kpd_device;
+
+extern struct platform_device ak98_sdio_device;
+
+extern struct platform_device ak98_snd_device;
+
+extern struct platform_device ak98_spi1_device;
+extern struct platform_device ak98_spi2_device;
+
+extern struct platform_device ak98_lcd_device;
+extern struct platform_device ak98_osd_device;
+extern struct platform_device ak98_tvout_device;
+
+extern struct platform_device ak98_mmx_device;
+extern struct platform_device ak98_mmx_pmem;
+
+extern struct platform_device ak98_nand_device;
+extern struct platform_device ak98_i2c_device;
+
+extern struct platform_device ak98_mmc_device;
+
+extern struct platform_device ak98_usb_device;
+
+extern struct platform_device ak98_mac_device;
+
+extern struct platform_device ak98_usb_fs_hcd_device;
+
+extern struct platform_device ak98_android_usb;
+extern struct platform_device ak98_android_usb_mass_storage;
+
+extern struct platform_device sensor_info_device;
+
+extern struct platform_device ak98_camera_interface;
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/devices_ak880x.h b/arch/arm/mach-ak98/include/mach/devices_ak880x.h
new file mode 100644
index 00000000000..c1f60d5a523
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/devices_ak880x.h
@@ -0,0 +1,24 @@
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+#ifndef __ARCH_ARM_MACH_AK88_DEVICE_H__
+#define __ARCH_ARM_MACH_AK88_DEVICE_H__
+
+//include <linux/device.h>
+//include <linux/mod_devicetable.h>
+//include <linux/platform_device.h>
+
+#define AK98_MAX_UART   4
+
+extern struct platform_device *ak98_default_console_device;
+
+void __init ak98_register_uart(unsigned char id, unsigned char portnr);
+
+void __init ak98_set_serial_console(unsigned char portnr);
+
+void __init ak98_add_device_serial(void);
+
+void __init ak98_add_device_lcdc(struct anyka_lcdfb_info *data);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/dma.h b/arch/arm/mach-ak98/include/mach/dma.h
new file mode 100644
index 00000000000..6431ae52568
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/dma.h
@@ -0,0 +1,40 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __AK88_DMA_H
+#define __AK88_DMA_H __FILE__
+
+//#include <linux/sysdev.h>
+#include <mach/hardware.h>
+
+#define AK98_DMA_CHANNELS  11
+
+/*
+ * This is the maximum DMA address(physical address) that can be DMAd to.
+ *
+ */
+//#define MAX_DMA_ADDRESS               0x40000000
+//#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
+
+struct ak880x_dma_channel {
+	const char *name;
+	void (*irq_handler) (int, void *);
+	void *data;
+	unsigned char dma_id;
+	unsigned char irq_bit;
+};
+
+/*
+ * 0: camera: 2
+ * 1: display: 1
+ * 2: audio processor:5
+ * 4: motion Estimation /H.264 decoder: 3&6
+ * 5: image processor/ MPEG4/H.263 codec: 4
+ * 6: l2:10
+ * 7: 2d graphics accelerator: 20
+ */
+
+#endif				/* __AK88_DMA_H */
diff --git a/arch/arm/mach-ak98/include/mach/entry-macro.S b/arch/arm/mach-ak98/include/mach/entry-macro.S
new file mode 100644
index 00000000000..2a84a881c14
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/entry-macro.S
@@ -0,0 +1,199 @@
+/*
+ * include/asm-arm/arch-ak98/entry-macro.S
+ *
+ * Low-level IRQ helper macros for AK98-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#define	AK98_IRQ_INTMASK		(AK98_VA_SYSCTRL + 0x34)
+#define	AK98_FIQ_INTMASK		(AK98_VA_SYSCTRL + 0x38)
+#define	AK98_INT_STATUS			(AK98_VA_SYSCTRL + 0xCC)
+
+	.macro  get_irqnr_preamble, base, tmp
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		ldr	\base, =AK98_INT_STATUS
+		ldr	\irqstat, [\base]		@ get interrupts status
+		teq	\irqstat, #0x0
+		beq	1002f
+		
+		ldr	\base, =AK98_IRQ_INTMASK	@ get interrupts mask
+		ldr	\base, [\base]
+		and	\irqstat, \irqstat, \base
+
+		tst	\irqstat, #(1<<IRQ_H264_DECODER)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_H264_DECODER)
+		movne	\irqnr, #IRQ_H264_DECODER
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_DISPLAY_CTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_DISPLAY_CTRL)
+		movne	\irqnr, #IRQ_DISPLAY_CTRL
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_CAMERA_IF)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_CAMERA_IF)
+		movne	\irqnr, #IRQ_CAMERA_IF
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_MOTIONESTIMATION)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MOTIONESTIMATION)
+		movne	\irqnr, #IRQ_MOTIONESTIMATION
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_JPEG)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_JPEG)
+		movne	\irqnr, #IRQ_JPEG
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_MAC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MAC)
+		movne	\irqnr, #IRQ_MAC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_ROTATION)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_ROTATION)
+		movne	\irqnr, #IRQ_ROTATION
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_DAC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_DAC)
+		movne	\irqnr, #IRQ_DAC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SIGDELTA_ADC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SIGDELTA_ADC)
+		movne	\irqnr, #IRQ_SIGDELTA_ADC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_L2MEM)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_L2MEM)
+		movne	\irqnr, #IRQ_L2MEM
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_NF_ECC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_NF_ECC)
+		movne	\irqnr, #IRQ_NF_ECC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_NF_CTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_NF_CTRL)
+		movne	\irqnr, #IRQ_NF_CTRL
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART3)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART3)
+		movne	\irqnr, #IRQ_UART3
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART2)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART2)
+		movne	\irqnr, #IRQ_UART2
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART1)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART1)
+		movne	\irqnr, #IRQ_UART1
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_UART0)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_UART0)
+		movne	\irqnr, #IRQ_UART0
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SPI2)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SPI2)
+		movne	\irqnr, #IRQ_SPI2
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SPI1)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SPI1)
+		movne	\irqnr, #IRQ_SPI1
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_I2C)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_I2C)
+		movne	\irqnr, #IRQ_I2C
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_2D_ACC)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_2D_ACC)
+		movne	\irqnr, #IRQ_2D_ACC
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_SDIO)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SDIO)
+		movne	\irqnr, #IRQ_SDIO
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_MMC_SD)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MMC_SD)
+		movne	\irqnr, #IRQ_MMC_SD
+		bne	1001f
+		
+		tst	\irqstat, #(1<<IRQ_USBHOST_MCU)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBHOST_MCU)
+		movne	\irqnr, #IRQ_USBHOST_MCU
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBHOST_DMA)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBHOST_DMA)
+		movne	\irqnr, #IRQ_USBHOST_DMA
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBOTG_MCU)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBOTG_MCU)
+		movne	\irqnr, #IRQ_USBOTG_MCU
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_USBOTG_DMA)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_USBOTG_DMA)
+		movne	\irqnr, #IRQ_USBOTG_DMA
+		bne	1001f
+	
+		tst	\irqstat, #(1<<IRQ_SYSCTRL)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_SYSCTRL)
+		movne	\irqnr, #IRQ_SYSCTRL
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_RMVB)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_RMVB)
+		movne	\irqnr, #IRQ_RMVB
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_MPEG2)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_MPEG2)
+		movne	\irqnr, #IRQ_MPEG2
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_HUFFMAN)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_HUFFMAN)
+		movne	\irqnr, #IRQ_HUFFMAN
+		bne	1001f
+
+		tst	\irqstat, #(1<<IRQ_PCM)
+		bicne	\irqstat, \irqstat, #(1<<IRQ_PCM)
+		movne	\irqnr, #IRQ_PCM
+		bne	1001f
+
+	1001:
+		@ got irqnr
+	1002:
+		@ exit here
+	.endm
+	
+	/* currently don't need an disable_fiq macro */
+	.macro	disable_fiq
+	.endm
+
diff --git a/arch/arm/mach-ak98/include/mach/gpio.h b/arch/arm/mach-ak98/include/mach/gpio.h
new file mode 100644
index 00000000000..fd389efc1b5
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/gpio.h
@@ -0,0 +1,375 @@
+/*************************************************************************
+*   Filename: arch/arm/mach-ak98/include/mach/gpio.h
+*
+*   This program is free software; you can redistribute it and/or modify
+*   it under the terms of the GNU General Public License as published by
+*   the Free Software Foundation; either version 2 of the License, or
+*   (at your option) any later version.
+**************************************************************************/
+
+#ifndef _AK98_GPIO_H_
+#define _AK98_GPIO_H_ 
+
+#include "map.h"
+#include <linux/gpio.h>
+
+
+#define	AK98_SHARE_GPIO			0
+#define	AK98_SHARE_FUNC			1
+
+#define AK98_WAKEUP_ENABLE		1
+#define AK98_WAKEUP_DISABLE		0
+#define AK98_FALLING_TRIGGERED   1
+#define AK98_RISING_TRIGGERED	 0
+
+#define	AK98_GPIO_DIR_OUTPUT	0
+#define	AK98_GPIO_DIR_INPUT		1
+
+#define	AK98_PULLUP_DISABLE		0
+#define	AK98_PULLUP_ENABLE		1
+#define	AK98_PULLDOWN_DISABLE	0
+#define	AK98_PULLDOWN_ENABLE	1
+
+
+#define	AK98_GPIO_INT_DISABLE	0
+#define	AK98_GPIO_INT_ENABLE	1
+
+#define	AK98_GPIO_LOW			0
+#define	AK98_GPIO_HIGH			1
+#define	AK98_GPIO_OUT_LOW			0
+#define	AK98_GPIO_OUT_HIGH			1
+
+
+#define	AK98_GPIO_INT_LOWLEVEL	0
+#define	AK98_GPIO_INT_HIGHLEVEL	1
+
+#define AK_FALSE		0
+#define AK_TRUE			1
+#undef AK_NULL
+#define AK_NULL			((void *)(0))
+#define AK_EMPTY
+
+
+
+#define AK98_GPIO_UART1_FLOW(x)		ak98_sharepin_cfg1(x,11,SHARE_CONFG1)
+#define AK98_GPIO_UART2_FLOW(x)		ak98_sharepin_cfg1(x,13,SHARE_CONFG1)
+#define AK98_GPIO_UART3_FLOW(x)		ak98_sharepin_cfg1(x,15,SHARE_CONFG1)
+
+
+/**************** gpio offsets ************************/
+#define AK98_GPIO_GROUP1		(32*0)
+#define AK98_GPIO_GROUP2		(32*1)
+#define AK98_GPIO_GROUP3		(32*2)
+#define AK98_GPIO_GROUP4		(32*3)
+#define AK98_GPIO_GROUP5		(32*4)
+#define AK98_GPIO_GROUP6		(32*5)
+
+
+#define AK98_GPIO_GROUP1_NO(offset)		( AK98_GPIO_GROUP1 + (offset))
+#define AK98_GPIO_GROUP2_NO(offset)		( AK98_GPIO_GROUP2 + (offset))
+#define AK98_GPIO_GROUP3_NO(offset)		( AK98_GPIO_GROUP3 + (offset))
+#define AK98_GPIO_GROUP4_NO(offset)		( AK98_GPIO_GROUP4 + (offset))
+#define AK98_GPIO_GROUP5_NO(offset)		( AK98_GPIO_GROUP5 + (offset))
+#define AK98_GPIO_GROUP6_NO(offset)		( AK98_GPIO_GROUP6 + (offset))
+
+
+		
+#define AK98_GPIO_0			AK98_GPIO_GROUP1_NO(0)
+#define AK98_GPIO_MIN		AK98_GPIO_0
+
+#define AK98_GPIO_1			AK98_GPIO_GROUP1_NO(1)
+#define AK98_GPIO_2			AK98_GPIO_GROUP1_NO(2)
+#define AK98_GPIO_3			AK98_GPIO_GROUP1_NO(3)
+#define AK98_GPIO_4			AK98_GPIO_GROUP1_NO(4)
+#define AK98_GPIO_5			AK98_GPIO_GROUP1_NO(5)
+#define AK98_GPIO_6			AK98_GPIO_GROUP1_NO(6)
+#define AK98_GPIO_7			AK98_GPIO_GROUP1_NO(7)
+#define AK98_GPIO_8			AK98_GPIO_GROUP1_NO(8)
+#define AK98_GPIO_9			AK98_GPIO_GROUP1_NO(9)
+#define AK98_GPIO_10		AK98_GPIO_GROUP1_NO(10)
+#define AK98_GPIO_11		AK98_GPIO_GROUP1_NO(11)
+#define AK98_GPIO_12		AK98_GPIO_GROUP1_NO(12)
+#define AK98_GPIO_13		AK98_GPIO_GROUP1_NO(13)
+#define AK98_GPIO_14		AK98_GPIO_GROUP1_NO(14)
+#define AK98_GPIO_15		AK98_GPIO_GROUP1_NO(15)
+#define AK98_GPIO_16		AK98_GPIO_GROUP1_NO(16)
+#define AK98_GPIO_17		AK98_GPIO_GROUP1_NO(17)
+#define AK98_GPIO_18		AK98_GPIO_GROUP1_NO(18)
+#define AK98_GPIO_19		AK98_GPIO_GROUP1_NO(19)
+#define AK98_GPIO_20		AK98_GPIO_GROUP1_NO(20)
+#define AK98_GPIO_21		AK98_GPIO_GROUP1_NO(21)
+#define AK98_GPIO_22		AK98_GPIO_GROUP1_NO(22)
+#define AK98_GPIO_23		AK98_GPIO_GROUP1_NO(23)
+#define AK98_GPIO_24		AK98_GPIO_GROUP1_NO(24)
+#define AK98_GPIO_25		AK98_GPIO_GROUP1_NO(25)
+#define AK98_GPIO_26		AK98_GPIO_GROUP1_NO(26)
+#define AK98_GPIO_27		AK98_GPIO_GROUP1_NO(27)
+#define AK98_GPIO_28		AK98_GPIO_GROUP1_NO(28)
+#define AK98_GPIO_29		AK98_GPIO_GROUP1_NO(29)
+#define AK98_GPIO_30		AK98_GPIO_GROUP1_NO(30)
+#define AK98_GPIO_31		AK98_GPIO_GROUP1_NO(31)
+
+#define AK98_GPIO_32		AK98_GPIO_GROUP2_NO(0)
+#define AK98_GPIO_33		AK98_GPIO_GROUP2_NO(1)
+#define AK98_GPIO_34		AK98_GPIO_GROUP2_NO(2)
+#define AK98_GPIO_35		AK98_GPIO_GROUP2_NO(3)
+#define AK98_GPIO_36		AK98_GPIO_GROUP2_NO(4)
+#define AK98_GPIO_37		AK98_GPIO_GROUP2_NO(5)
+#define AK98_GPIO_38		AK98_GPIO_GROUP2_NO(6)
+#define AK98_GPIO_39		AK98_GPIO_GROUP2_NO(7)
+#define AK98_GPIO_40		AK98_GPIO_GROUP2_NO(8)
+#define AK98_GPIO_41		AK98_GPIO_GROUP2_NO(9)
+#define AK98_GPIO_42		AK98_GPIO_GROUP2_NO(10)
+#define AK98_GPIO_43		AK98_GPIO_GROUP2_NO(11)
+#define AK98_GPIO_44		AK98_GPIO_GROUP2_NO(12)
+#define AK98_GPIO_45		AK98_GPIO_GROUP2_NO(13)
+#define AK98_GPIO_46		AK98_GPIO_GROUP2_NO(14)
+#define AK98_GPIO_47		AK98_GPIO_GROUP2_NO(15)
+#define AK98_GPIO_48		AK98_GPIO_GROUP2_NO(16)
+#define AK98_GPIO_49		AK98_GPIO_GROUP2_NO(17)
+#define AK98_GPIO_50		AK98_GPIO_GROUP2_NO(18)
+#define AK98_GPIO_51		AK98_GPIO_GROUP2_NO(19)
+#define AK98_GPIO_52		AK98_GPIO_GROUP2_NO(20)
+#define AK98_GPIO_53		AK98_GPIO_GROUP2_NO(21)
+#define AK98_GPIO_54		AK98_GPIO_GROUP2_NO(22)
+#define AK98_GPIO_55		AK98_GPIO_GROUP2_NO(23)
+#define AK98_GPIO_56		AK98_GPIO_GROUP2_NO(24)
+#define AK98_GPIO_57		AK98_GPIO_GROUP2_NO(25)
+#define AK98_GPIO_58		AK98_GPIO_GROUP2_NO(26)
+#define AK98_GPIO_59 		AK98_GPIO_GROUP2_NO(27)	/* Reserved */
+#define AK98_GPIO_60		AK98_GPIO_GROUP2_NO(28)	/* Reserved */
+#define AK98_GPIO_61		AK98_GPIO_GROUP2_NO(29)
+#define AK98_GPIO_62		AK98_GPIO_GROUP2_NO(30)
+#define AK98_GPIO_63		AK98_GPIO_GROUP2_NO(31)
+
+#define AK98_GPIO_64		AK98_GPIO_GROUP3_NO(0)
+#define AK98_GPIO_65		AK98_GPIO_GROUP3_NO(1)
+#define AK98_GPIO_66		AK98_GPIO_GROUP3_NO(2)
+#define AK98_GPIO_67		AK98_GPIO_GROUP3_NO(3)
+#define AK98_GPIO_68		AK98_GPIO_GROUP3_NO(4)
+#define AK98_GPIO_69		AK98_GPIO_GROUP3_NO(5)
+#define AK98_GPIO_70		AK98_GPIO_GROUP3_NO(6)
+#define AK98_GPIO_71		AK98_GPIO_GROUP3_NO(7)
+#define AK98_GPIO_72		AK98_GPIO_GROUP3_NO(8)
+#define AK98_GPIO_73		AK98_GPIO_GROUP3_NO(9)
+#define AK98_GPIO_74		AK98_GPIO_GROUP3_NO(10)
+#define AK98_GPIO_75		AK98_GPIO_GROUP3_NO(11)
+#define AK98_GPIO_76		AK98_GPIO_GROUP3_NO(12)
+#define AK98_GPIO_77		AK98_GPIO_GROUP3_NO(13)
+#define AK98_GPIO_78		AK98_GPIO_GROUP3_NO(14)
+#define AK98_GPIO_79		AK98_GPIO_GROUP3_NO(15)
+#define AK98_GPIO_80		AK98_GPIO_GROUP3_NO(16)
+#define AK98_GPIO_81		AK98_GPIO_GROUP3_NO(17)
+#define AK98_GPIO_82		AK98_GPIO_GROUP3_NO(18)
+#define AK98_GPIO_83		AK98_GPIO_GROUP3_NO(19)
+#define AK98_GPIO_84		AK98_GPIO_GROUP3_NO(20)
+#define AK98_GPIO_85		AK98_GPIO_GROUP3_NO(21)
+#define AK98_GPIO_86		AK98_GPIO_GROUP3_NO(22)
+#define AK98_GPIO_87		AK98_GPIO_GROUP3_NO(23)
+#define AK98_GPIO_88		AK98_GPIO_GROUP3_NO(24)
+#define AK98_GPIO_89		AK98_GPIO_GROUP3_NO(25)
+#define AK98_GPIO_90		AK98_GPIO_GROUP3_NO(26)
+#define AK98_GPIO_91		AK98_GPIO_GROUP3_NO(27)
+#define AK98_GPIO_92		AK98_GPIO_GROUP3_NO(28)
+#define AK98_GPIO_93		AK98_GPIO_GROUP3_NO(29)
+#define AK98_GPIO_94		AK98_GPIO_GROUP3_NO(30) /* Reserved */
+#define AK98_GPIO_95		AK98_GPIO_GROUP3_NO(31) /* Reserved */
+
+
+#define AK98_GPIO_96		AK98_GPIO_GROUP4_NO(0) /* Reserved */
+#define AK98_GPIO_97		AK98_GPIO_GROUP4_NO(1)
+#define AK98_GPIO_98		AK98_GPIO_GROUP4_NO(2)
+#define AK98_GPIO_99		AK98_GPIO_GROUP4_NO(3)
+#define AK98_GPIO_100		AK98_GPIO_GROUP4_NO(4)
+#define AK98_GPIO_101		AK98_GPIO_GROUP4_NO(5)
+#define AK98_GPIO_102		AK98_GPIO_GROUP4_NO(6)
+#define AK98_GPIO_103		AK98_GPIO_GROUP4_NO(7)
+#define AK98_GPIO_104		AK98_GPIO_GROUP4_NO(8)
+#define AK98_GPIO_105		AK98_GPIO_GROUP4_NO(9)
+#define AK98_GPIO_106		AK98_GPIO_GROUP4_NO(10)
+#define AK98_GPIO_107		AK98_GPIO_GROUP4_NO(11)
+#define AK98_GPIO_108		AK98_GPIO_GROUP4_NO(12)	/* Reserved */
+#define AK98_GPIO_109		AK98_GPIO_GROUP4_NO(13)
+#define AK98_GPIO_110		AK98_GPIO_GROUP4_NO(14)
+#define AK98_GPIO_111		AK98_GPIO_GROUP4_NO(15)
+#define AK98_GPIO_112		AK98_GPIO_GROUP4_NO(16)
+#define AK98_GPIO_113		AK98_GPIO_GROUP4_NO(17)
+#define AK98_GPIO_114		AK98_GPIO_GROUP4_NO(18)
+#define AK98_GPIO_115		AK98_GPIO_GROUP4_NO(19)
+#define AK98_GPIO_116		AK98_GPIO_GROUP4_NO(20)
+#define AK98_MCGPIO_0		AK98_GPIO_GROUP5_NO(0)
+#define AK98_MCGPIO_1		AK98_GPIO_GROUP5_NO(1)
+#define AK98_MCGPIO_2		AK98_GPIO_GROUP5_NO(2)
+#define AK98_MCGPIO_3		AK98_GPIO_GROUP5_NO(3)
+#define AK98_MCGPIO_4		AK98_GPIO_GROUP5_NO(4)
+#define AK98_MCGPIO_5		AK98_GPIO_GROUP5_NO(5)
+#define AK98_MCGPIO_6		AK98_GPIO_GROUP5_NO(6)
+#define AK98_MCGPIO_7		AK98_GPIO_GROUP5_NO(7)
+#define AK98_MCGPIO_8		AK98_GPIO_GROUP5_NO(8)
+#define AK98_MCGPIO_9		AK98_GPIO_GROUP5_NO(9)
+#define AK98_MCGPIO_10		AK98_GPIO_GROUP5_NO(10)
+#define AK98_MCGPIO_11		AK98_GPIO_GROUP5_NO(11)
+#define AK98_MCGPIO_12		AK98_GPIO_GROUP5_NO(12)
+#define AK98_MCGPIO_13		AK98_GPIO_GROUP5_NO(13)
+#define AK98_MCGPIO_14		AK98_GPIO_GROUP5_NO(14)
+#define AK98_MCGPIO_15		AK98_GPIO_GROUP5_NO(15)
+#define AK98_MCGPIO_16		AK98_GPIO_GROUP5_NO(16)
+#define AK98_MCGPIO_17		AK98_GPIO_GROUP5_NO(17)
+#define AK98_MCGPIO_18		AK98_GPIO_GROUP5_NO(18)
+#define AK98_MCGPIO_19		AK98_GPIO_GROUP5_NO(19)
+
+/* AW9523 expander GPIO pins */
+#define AW9523_GPIO_P00		AK98_GPIO_GROUP6_NO(0)
+#define AW9523_GPIO_P01		AK98_GPIO_GROUP6_NO(1)
+#define AW9523_GPIO_P02		AK98_GPIO_GROUP6_NO(2)
+#define AW9523_GPIO_P03		AK98_GPIO_GROUP6_NO(3)
+#define AW9523_GPIO_P04		AK98_GPIO_GROUP6_NO(4)
+#define AW9523_GPIO_P05		AK98_GPIO_GROUP6_NO(5)
+#define AW9523_GPIO_P06		AK98_GPIO_GROUP6_NO(6)
+#define AW9523_GPIO_P07		AK98_GPIO_GROUP6_NO(7)
+#define AW9523_GPIO_P10		AK98_GPIO_GROUP6_NO(8)
+#define AW9523_GPIO_P11		AK98_GPIO_GROUP6_NO(9)
+#define AW9523_GPIO_P12		AK98_GPIO_GROUP6_NO(10)
+#define AW9523_GPIO_P13		AK98_GPIO_GROUP6_NO(11)
+#define AW9523_GPIO_P14		AK98_GPIO_GROUP6_NO(12)
+#define AW9523_GPIO_P15		AK98_GPIO_GROUP6_NO(13)
+#define AW9523_GPIO_P16		AK98_GPIO_GROUP6_NO(14)
+#define AW9523_GPIO_P17		AK98_GPIO_GROUP6_NO(15)
+
+#define AK98_GPIO_MAX		AW9523_GPIO_P17
+
+#undef REG32
+#define REG32(_reg)	(*(volatile unsigned long *)(_reg))
+
+#undef REG16 
+#define REG16(_reg)	(*(volatile unsigned short *)(_reg))
+
+
+typedef enum {
+	 ePIN_AS_GPIO = 0,			 // All pin as gpio
+	 ePIN_AS_PCM,				 // share pin as PCM
+	 ePIN_AS_JTAG,				 // share pin as JTAG
+	 ePIN_AS_RTCK, 		   	  	 // share pin as watch dog
+	 ePIN_AS_I2S,				 // share pin as I2S
+	 ePIN_AS_USB_OTG,			 // share pin as USB OTG
+	 ePIN_AS_PWM1,				 // share pin as PWM1
+	 ePIN_AS_PWM2,				 // share pin as PWM2
+	 ePIN_AS_PWM3,				 // share pin as PWM3
+	 ePIN_AS_PWM4,				 // share pin as PWM4
+	 ePIN_AS_UART1, 			 // share pin as UART1
+	 ePIN_AS_UART2, 			 // share pin as UART2
+	 ePIN_AS_UART3, 			 // share pin as UART3
+	 ePIN_AS_UART4, 			 // share pin as UART4
+	 ePIN_AS_NFC, 		 		 // share pin as NFC
+	 ePIN_AS_NFC_EXT, 	 		 // share pin as NFC extend data line
+	 ePIN_AS_CAMERA,			 // share pin as CAMERA
+	 ePIN_AS_LCD,				 // share pin as LCD
+	 ePIN_AS_LCD_EXT,			 // share pin as LCD Extend dataline
+	 ePIN_AS_SDMMC1,			 // share pin as MDAT1, 8 lines
+	 ePIN_AS_SDMMC2,			 // share pin as MDAT2, 4lines
+	 ePIN_AS_SDIO,				 // share pin as SDIO
+	 ePIN_AS_SPI1,				 // share pin as SPI1
+	 ePIN_AS_SPI2,				 // share pin as SPI2
+	 ePIN_AS_MAC,				 // share pin as Ethernet MAC
+	 ePIN_AS_I2C,				 // share pin as I2C
+	 ePIN_AS_RAM,				 // share pin as RAM Controller
+	 ePIN_AS_HOSTUSB, 			 // share pin as USB Host 
+	 ePIN_AS_CLK12MO,
+	 ePIN_AS_CLK32KO,
+ 
+	 ePIN_AS_DUMMY
+ } T_GPIO_SHAREPIN_CFG ;
+
+typedef enum {
+	SHARE_CONFG1 = 0,
+	SHARE_CONFG2
+} T_SHARE_CONFG;
+
+typedef enum  {
+	SHARE_CFG1 = 0,   ///share config1
+	SHARE_CFG2,       //share config2
+	SHARE_CFGBOTH,    //share config1 and share config2 as used
+	EXIT_CFG		  
+}T_SHARE_CFG;
+
+struct gpio_callbacks_info 
+{
+	unsigned int pin_start;
+	unsigned int pin_end;
+
+	int (*setpin_as_gpio) (unsigned int pin);
+	int (*gpio_pullup)(unsigned int pin, unsigned char enable);
+	int (*gpio_pulldown)(unsigned int pin, unsigned char enable);
+
+	int (*gpio_dircfg)(unsigned int pin, unsigned int to);	
+	
+	int (*gpio_intcfg)(unsigned int pin, unsigned int enable);
+	int (*gpio_set_intpol)(unsigned int pin, unsigned int level);
+
+	int (*gpio_setpin)(unsigned int pin, unsigned int to);
+	int (*gpio_getpin)(unsigned int pin);
+
+	int (*gpio_to_irq)(unsigned int pin);
+	int (*irq_to_gpio)(unsigned int irq);
+
+};
+
+struct gpio_info
+{
+	int pin;
+	char pulldown;
+	char pullup;
+	char value;
+	char dir;
+	char int_pol;
+	
+};
+
+void ak98_gpio_set(const struct gpio_info *info);
+
+/* set gpio's wake up polarity*/
+
+void ak98_gpio_wakeup_pol(unsigned int pin, unsigned char pol);
+/* enable/disable gpio wake up function*/
+int ak98_gpio_wakeup(unsigned int pin, unsigned char enable);
+
+void ak98_sharepin_cfg1(unsigned char to, unsigned char offset, T_SHARE_CONFG conf);
+void ak98_sharepin_cfg2(unsigned long mask, unsigned long value, unsigned char offset);
+
+
+int ak98_gpio_pullup(unsigned int pin, unsigned char enable);
+int ak98_gpio_pulldown(unsigned int pin, unsigned char enable);
+int ak98_setpin_as_gpio (unsigned int pin);
+void ak98_group_config(T_GPIO_SHAREPIN_CFG mod_name);
+
+
+
+
+/* new version of ak98_gpio_cfgpin */
+int ak98_gpio_dircfg(unsigned int pin, unsigned int to);
+
+int ak98_gpio_setpin(unsigned int pin, unsigned int to);
+int ak98_gpio_getpin(unsigned int pin);
+
+/* new version of  ak98_gpio_inten*/
+int ak98_gpio_intcfg(unsigned int pin, unsigned int enable);
+/* new version of  ak98_gpio_intpol*/
+int ak98_gpio_set_intpol(unsigned int pin, unsigned int level);
+
+
+int ak98_gpio_to_irq(unsigned int pin);
+int ak98_irq_to_gpio(unsigned int irq);
+
+
+
+/*  to support backward compatibility*/
+int ak98_gpio_cfgpin(unsigned int pin, unsigned int to);
+int ak98_gpio_inten(unsigned int pin, unsigned int enable);
+int ak98_gpio_intpol(unsigned int pin, unsigned int level);
+
+extern int ak98_gpio_request(unsigned long gpio, const char *label);
+extern void ak98_gpio_free(unsigned long gpio);
+
+
+#endif /*_AK98_GPIO_H_*/
+
diff --git a/arch/arm/mach-ak98/include/mach/gpio_keys.h b/arch/arm/mach-ak98/include/mach/gpio_keys.h
new file mode 100755
index 00000000000..77ccd6ef676
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/gpio_keys.h
@@ -0,0 +1,27 @@
+#ifndef _AK98_GPIO_KEYS_H
+#define _AK98_GPIO_KEYS_H
+
+struct ak98_gpio_keys_button {
+	/* Configuration parameters */
+	int code;		/* input event code (KEY_*, SW_*) */
+	int gpio;
+	int active_low;
+	char *desc;
+	int type;		/* input event type (EV_KEY, EV_SW) */
+	int wakeup;		/* configure the button as a wake-up source */
+	int debounce_interval;	/* debounce ticks interval in msecs */
+
+	char pulldown;  //pulldown function flag
+	char pullup;    //pullup function flag
+	char dir;       //direction  input/output
+	char int_pol;   //interrupt polarity	
+};
+
+struct ak98_gpio_keys_platform_data {
+	struct ak98_gpio_keys_button *buttons;
+	int nbuttons;
+	unsigned int rep:1;		/* enable input subsystem auto repeat */
+};
+
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/guireg.h b/arch/arm/mach-ak98/include/mach/guireg.h
new file mode 100644
index 00000000000..2a852a774be
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/guireg.h
@@ -0,0 +1,203 @@
+#ifndef __AK_2DACC_REG_H__
+#define __AK_2DACC_REG_H__ __FILE__
+
+#define GUI_SET_REG(reg_addr, value)	(*((volatile T_U32 *)(reg_addr))) = (value)
+#define GUI_GET_REG(reg_addr)		(*((volatile T_U32 *)(reg_addr)))
+
+/* register address define */
+#define GUI_BASE_ADDR			0x20022000	// gui register base address
+#define GUI_CMD_ADDR			(GUI_BASE_ADDR+0x04)	// Command
+#define GUI_BLTSIZE_ADDR		(GUI_BASE_ADDR+0x08)	// Bitblt
+#define GUI_POINT1_ADDR			(GUI_BASE_ADDR+0x0c)	// Point 1
+#define GUI_DSTXY_ADDR			(GUI_BASE_ADDR+0x10)	// Dest. XY
+#define GUI_POINT2_ADDR			(GUI_BASE_ADDR+0x14)	// Point 2
+#define GUI_SRCXY_ADDR			(GUI_BASE_ADDR+0x18)	// Source XY
+#define GUI_POINT3_ADDR			(GUI_BASE_ADDR+0x1c)	// Point 3
+#define GUI_COLORCMP_ADDR		(GUI_BASE_ADDR+0x20)	// Color Compare
+#define GUI_CLIPLT_ADDR			(GUI_BASE_ADDR+0x24)	// Clip Left/Top
+#define GUI_CLIPRB_ADDR			(GUI_BASE_ADDR+0x28)	// Clip Right/Bottom
+#define GUI_FCOLOR_ADDR			(GUI_BASE_ADDR+0x2c)	// Foreground Color
+#define GUI_BCOLOR_ADDR			(GUI_BASE_ADDR+0x30)	// Background Color : Useless now
+#define GUI_SRCSTRD_ADDR		(GUI_BASE_ADDR+0x34)	// Source Stride
+#define GUI_DSTSTRD_ADDR		(GUI_BASE_ADDR+0x3c)	// Dest. Stride
+#define GUI_DSTADDR_ADDR		(GUI_BASE_ADDR+0x40)	// Dest. Base Address
+#define GUI_PATN0_ADDR			(GUI_BASE_ADDR+0x58)	// Pattern Part 0
+#define GUI_PATN1_ADDR			(GUI_BASE_ADDR+0x5c)	// Pattern Part 1
+#define GUI_PATNFC_ADDR			(GUI_BASE_ADDR+0x60)	// Pattern Foreground
+#define GUI_PATNBC_ADDR			(GUI_BASE_ADDR+0x64)	// Pattern Background
+#define GUI_ARBIOBJLID_ADDR		(GUI_BASE_ADDR+0x70)	// Arbitrary Object Line Index
+#define GUI_ARBIOBJLRB_ADDR		(GUI_BASE_ADDR+0x74)	// Arbitrary Object Left/Right Boundary
+#define GUI_SRCADDR_ADDR		(GUI_BASE_ADDR+0x78)	// Source Base Address
+#define GUI_STATUS_ADDR			(GUI_BASE_ADDR+0x7c)	// Status
+
+///////////////////////////////////////////////////////////////////////////////
+
+// command register bit
+#define CMD_RASTER_OP_VALUE_BIT		0	// Raster operation, 6:0
+#define CMD_RASTER_OP_BIT		7	// 0-raster, 1-alpha
+#define CMD_TYPE_BIT			8	// Command type, 10:8
+#define CMD_MONO_SRC_BIT		14	// Monochrome source, 14
+#define CMD_MONO_PAT_BIT		15	// Monochrome pattern, 15
+#define CMD_COLOR_TRANS_EN_BIT		16	// Color transparency enable, 16
+#define CMD_DST_TRANS_POL_BIT		17	// Destination transparency polarity, 17
+#define CMD_MONO_SRC_PAT_BIT		18	// Monochrome source or pattern transparency enable, 18
+#define CMD_MONO_TRANS_POL_BIT		19	// Monochrome transparency polarity, 19
+#define CMD_SOLID_SRC_BIT		21	// Solid source color, 21
+#define CMD_CLIP_EN_BIT			24	// Clipping enable, 24
+#define CMD_SOLID_PAT_BIT		26	// Solid pattern, 26
+#define CMD_TRANS_CMP_SRC_BIT		27	// Color transparency compare source, 27
+//#define CMD_3D_BIT                    28  // 3D command
+#define CMD_MATRIX_TRI_EN_BIT		30	// Matrix Triangle Enable
+
+// BitBLT width and height parameter register bit
+#define BITBLT_WIDTH_BIT		0	// Source or destination window width, 11:0
+#define BITBLT_HEIGHT_BIT		16	// Source or destination window height, 27:16
+
+// Bresenham line draw parameter register point1 bit
+#define POINT1_X_BIT			0	// X coordination of point1, 11:0
+#define POINT1_Y_BIT			16	// Y coordination of point1, 27:16
+
+// Destination XY register bit
+#define DSTXY_X_BIT			0	// Destination X position, 11:0
+//#define DST_MONO_X_OFF_BIT            12  // Monochrome pattern horizontal offset, 15:12
+#define DSTXY_Y_BIT			16	// Destination Y position, 27:16
+//#define DST_MONO_Y_OFF_BIT            28  // Monochrome pattern horizontal offset, 31:28
+
+// Bresenham line draw parameter register point2 bit
+#define POINT2_X_BIT			0	// X coordination of point2, 11:0
+#define POINT2_Y_BIT			16	// Y coordination of point2, 27:16
+
+// Source XY register bit
+#define SRCXY_X_BIT			0	// Source X position, 11:0
+#define SRCXY_Y_BIT			16	// Source Y position, 27:16
+
+// Bresenham line draw parameter register point3 bit
+#define POINT3_X_BIT			0	// X coordination of point3, 11:0
+#define POINT3_Y_BIT			16	// Y coordination of point3, 27:16
+
+// Color compare register bit
+#define COLCMP_TRANS_COLOR_BIT		0	// Destination transparent color, 23:0
+
+// Clip Left/Top register bit
+#define CLIPLT_LEFT_X_BIT		0	// Left edge of clipping rectangle, 11:0
+#define CLIPLT_TOP_Y_BIT		16	// Top edge of clipping rectangle, 27:16
+
+// Clip Left/Top register bit
+#define CLIPRB_RIGHT_X_BIT		0	// Right edge of clipping rectangle, 11:0
+#define CLIPRB_BOTTOM_Y_BIT		16	// Bottom edge of clipping rectangle, 27:16
+
+// Source stride register bit
+#define SRCSTRD_LINE_STRIDE_BIT		0	// Source line stride, 11:0
+#define SRCSTRD_MONO_SRC_START_BIT	13	// Monochrome source starts, 15:13
+
+// Destination stride and color depth register bit
+#define DSTSTRD_LINE_STRIDE_BIT		0	// Destination line stride, 11:0
+#define DSTSTRD_ROTATE_90		14	// Enable 90 degree clockwise rotation, 15:14
+
+// Monochrome pattern register0 bit
+#define PATN0_LINE0_BIT			0	// Line 0 of monochrome pattern, 7:0
+#define PATN0_LINE1_BIT			8	// Line 1 of monochrome pattern, 15:8
+#define PATN0_LINE2_BIT			16	// Line 2 of monochrome pattern, 23:16
+#define PATN0_LINE3_BIT			24	// Line 3 of monochrome pattern, 31:24
+
+// Monochrome pattern register1 bit
+#define PATN0_LINE4_BIT			0	// Line 4 of monochrome pattern, 7:0
+#define PATN0_LINE5_BIT			8	// Line 5 of monochrome pattern, 15:8
+#define PATN0_LINE6_BIT			16	// Line 6 of monochrome pattern, 23:16
+#define PATN0_LINE7_BIT			24	// Line 7 of monochrome pattern, 31:24
+
+// Color Space conversion and scaling control bit 
+
+// start rectangle draw operation with scaling and color conversion
+#define SCALCTRL_START_BIT		0
+#define SCALCTRL_BYPASS_BIT		1	// Bypass scaler, 2
+// input format, 3:2=00-rgb888), 01-rgb565, 10-YUV420
+#define SCALCTRL_FORMAT_BIT		2
+// destination image is also a source needed in GUI operations, 4
+#define SCALCTRL_NEEDED_BIT		4
+
+// Scaling parameters, scaling ration = 8192 / ILX[8:0]
+#define SCALRATIO_HORI_DIV_BIT		0	// Horizontal scaling divider ratio, 8:0
+#define SCALRATIO_VERT_DIV_BIT		16	// Vertical scaling divider ratio, 24:16
+
+// Input image rectangle dimensions
+#define SCALSRCRECT_WIDTH_BIT		0	// Input image width in pixels, 9:0
+#define SCALSRCRECT_HEIGHT_BIT		16	// Input image width in pixels, 24:16
+
+// Output image rectangle dimensions
+#define SCALDSTRECT_WIDTH_BIT		0	// Output image width in pixels, 9:0
+#define SCALDSTRECT_HEIGHT_BIT		16	// Output image width in pixels, 24:16
+
+/////////////////////////////////////////////////////////////////////////
+
+// command register bit 7
+#define RASTER_OP           0
+#define ALPHA_OP            1
+
+// raster operation
+#define RASTER_NO_OP        0
+#define RASTER_SRCAND       1
+#define RASTER_SRCOR        2
+#define RASTER_SRCXOR       3
+#define RASTER_SRCCOPY      4
+
+// command type
+#define TYPE_SCALE_CONVT    0	// draw rectangle with scaling and color conversion capability
+#define TYPE_RECT_FILL      1
+#define TYPE_LINE_DRAW      2
+#define TYPE_TRIANGLE_FILL  3
+#define TYPE_ARBITRARY_FILL 4
+#define TYPE_RECT_COPY      5
+
+// pattern start pixel
+#define PATN_START_PIXEL(n)     (n)
+
+// pattern start line
+#define PATN_START_LINE(n)      (n)
+
+// monochrome start bit
+#define MONO_START_BIT(n)       (n)
+
+////////////////////////////////////////////////////////////////////////////////
+
+// Gradient Color Fill
+#define GUI_REFPOINT_ADDR       (GUI_BASE_ADDR+0x200)	// Reference Point
+#define GUI_REFCOLOR_ADDR       (GUI_BASE_ADDR+0x204)	// Reference Color
+#define GUI_GRADCOLOR_X_ADDR    (GUI_BASE_ADDR+0x208)	// X Gradient Color
+#define GUI_GRADCOLOR_Y_ADDR    (GUI_BASE_ADDR+0x20c)	// Y Gradient Color
+#define GUI_GRAD_RED_X_ADDR     (GUI_BASE_ADDR+0x210)	// Denominator/Nominator X for color R
+#define GUI_GRAD_RED_Y_ADDR     (GUI_BASE_ADDR+0x214)	// Denominator/Nominator Y for color R
+#define GUI_GRAD_GREEN_X_ADDR   (GUI_BASE_ADDR+0x220)	// Denominator/Nominator X for color G
+#define GUI_GRAD_GREEN_Y_ADDR   (GUI_BASE_ADDR+0x224)	// Denominator/Nominator Y for color G
+#define GUI_GRAD_BLUE_X_ADDR    (GUI_BASE_ADDR+0x230)	// Denominator/Nominator X for color B
+#define GUI_GRAD_BLUE_Y_ADDR    (GUI_BASE_ADDR+0x234)	// Denominator/Nominator Y for color B
+
+// Reference Point Bit
+#define REF_POINT_ENABLE        24
+#define REF_POINT_X0            12
+#define REF_POINT_Y0            0
+
+// Denominator/Nominator Bit
+#define GRADFILL_ABS             20
+#define GRADFILL_NOMINATOR       8
+#define GRADFILL_DENOMINATOR     0
+
+////////////////////////////////////////////////////////////////////////////////
+
+// Matrix Triangle Fill
+#define GUI_MATRIX_SRCADDR	(GUI_BASE_ADDR+0x240)
+#define GUI_MATRIX_SRCSTRD	(GUI_BASE_ADDR+0x244)
+#define GUI_MATRIX_REG1		(GUI_BASE_ADDR+0x250)	// sx, shx [31:22], [21:12]
+#define GUI_MATRIX_REG2		(GUI_BASE_ADDR+0x254)	// sy, shy [31:22], [21:12]
+#define GUI_MATRIX_REG3		(GUI_BASE_ADDR+0x258)	// w0,  w1 [31:22], [21:12]
+#define GUI_MATRIX_REGTX	(GUI_BASE_ADDR+0x260)	// tx [23:0]
+#define GUI_MATRIX_REGTY	(GUI_BASE_ADDR+0x264)	// ty [23:0]
+#define GUI_MATRIX_REGW2	(GUI_BASE_ADDR+0x268)	// w2 [23:0]
+
+// Shift Bit
+#define GUI_MATRIX_SHIFT1	22
+#define GUI_MATRIX_SHIFT2	12
+
+////////////////////////////////////////////////////////////////////////////////
+
+#endif				// __GUI_REG_H__
diff --git a/arch/arm/mach-ak98/include/mach/hardware.h b/arch/arm/mach-ak98/include/mach/hardware.h
new file mode 100644
index 00000000000..66488e52119
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/hardware.h
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/hardware.h
+ *
+ * Copyright (c) 2003 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+#endif				/* __ASSEMBLY__ */
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+/* machine specific hardware definitions should go after this */
+
+#endif				/* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ak98/include/mach/i2c.h b/arch/arm/mach-ak98/include/mach/i2c.h
new file mode 100644
index 00000000000..dc019e6462b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/i2c.h
@@ -0,0 +1,60 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __AK98_IIC_H
+#define __AK98_IIC_H __FILE__
+
+#include <mach/map.h>
+#include <mach/gpio.h>
+
+
+
+#define I2C_CLKPIN		(92)
+#define I2C_DATPIN		(93)
+#define I2C_INTPIN		(24)
+
+#define AK98_I2C_NACKEN		(1 << 17)
+#define AK98_I2C_NOSTOP		(1 << 16)
+#define AK98_I2C_ACKEN		(1 << 15)
+#define AK98_I2C_START		(1 << 14)
+#define AK98_I2C_TXRXSEL	(1 << 13)
+#define AK98_I2C_TRX_BYTE	(9)
+#define AK98_I2C_CLR_DELAY	(0x3 << 7)
+#define AK98_I2C_SDA_DELAY	(0x2 << 7)
+#define AK98_I2C_TXDIV_512	(1 << 6)
+#define AK98_I2C_INTEN		(1 << 5)
+
+#define INT_PEND_FLAG		(1 << 4)
+#define AK98_TX_CLK_DIV		(0xf)
+
+#define	AK98_I2C_CMD_EN			(1 << 18)
+#define AK98_I2C_START_BIT		(1 << 17)
+
+#define AK98_I2C_READ		1
+#define AK98_I2C_WRITE		0
+	
+#define AK98_I2C_CTRL		REG_VA_ADDR(AK98_VA_I2C, 0x00)
+#define AK98_I2C_CMD1		REG_VA_ADDR(AK98_VA_I2C, 0x10)
+#define AK98_I2C_CMD2		REG_VA_ADDR(AK98_VA_I2C, 0x14)
+#define AK98_I2C_CMD3		REG_VA_ADDR(AK98_VA_I2C, 0x18)
+#define AK98_I2C_CMD4		REG_VA_ADDR(AK98_VA_I2C, 0x1C)
+#define AK98_I2C_DATA0		REG_VA_ADDR(AK98_VA_I2C, 0x20)
+#define AK98_I2C_DATA1		REG_VA_ADDR(AK98_VA_I2C, 0x24)
+#define AK98_I2C_DATA2		REG_VA_ADDR(AK98_VA_I2C, 0x28)
+#define AK98_I2C_DATA3		REG_VA_ADDR(AK98_VA_I2C, 0x2C)
+
+
+struct ak98_platform_i2c {
+	int		bus_num;
+	unsigned int	flags;
+	unsigned int	slave_addr;
+	unsigned long	frequency;
+	unsigned int	sda_delay;
+	struct gpio_info *gpios;
+	int npins;
+};
+
+#endif	/* __AK98_IIC_H */
diff --git a/arch/arm/mach-ak98/include/mach/io-ctl.h b/arch/arm/mach-ak98/include/mach/io-ctl.h
new file mode 100644
index 00000000000..251b91309e5
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/io-ctl.h
@@ -0,0 +1,81 @@
+#ifndef __H_AK98_IO_CONTROL__
+#define __H_AK98_IO_CONTROL__
+
+/* IO control register 1 */
+#define DS_SDIO_MCMD		0
+#define DS_SDIO_MCK		1
+
+#define IE_URD1			2
+#define IE_UTD1			3
+#define IE_CTS1			4
+#define IE_RTS1			5
+
+#define IE_URD2			6
+#define IE_UTD2			7
+#define IE_CTS2			8
+#define IE_RTS2			9
+
+#define IE_URD3			10
+#define IE_UTD3			11
+#define IE_CTS3			12
+#define IE_RTS3			13
+
+#define PE_URD1			14
+#define PE_UTD1			15
+#define PE_CTS1			16
+#define PE_RTS1			17
+
+#define PE_URD2			18
+#define PE_UTD2			19
+#define PE_CTS2			20
+#define PE_RTS2			21
+
+#define PE_URD3			22
+#define PE_UTD3			23
+#define PE_CTS3			24
+#define PE_RTS3			25
+
+#define IE_SDIO_MCK		26
+#define IE_SDIO_MCMD		27
+
+#define DS_GPIO_29		0
+#define DS_GPIO_28		1
+
+#define IE_GPIO_17		2
+#define IE_GPIO_16		3
+#define IE_GPIO_19		4
+#define IE_GPIO_18		5
+#define IE_GPIO_21		6
+#define IE_GPIO_20		7
+#define IE_GPIO_23		8
+#define IE_GPIO_22		9
+#define IE_GPIO_25		10
+#define IE_GPIO_24		11
+#define IE_GPIO_27		12
+#define IE_GPIO_26		13
+
+#define PE_GPIO_17		14
+#define PE_GPIO_16		15
+#define PE_GPIO_19		16
+#define PE_GPIO_18		17
+#define PE_GPIO_21		18
+#define PE_GPIO_20		19
+#define PE_GPIO_23		20
+#define PE_GPIO_22		21
+#define PE_GPIO_25		22
+#define PE_GPIO_24		23
+#define PE_GPIO_27		24
+#define PE_GPIO_26		25
+
+#define IE_GPIO_29		26
+#define IE_GPIO_28		27
+
+/* IO control register 2 */
+
+#define IE_DGPIO_7		(32 + 4)
+#define PE_DGPIO_7		(32 + 8)
+#define DS_DGPIO_7		(32 + 12)
+
+void ak880x_ioctl(unsigned int offset, const unsigned int to);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/io.h b/arch/arm/mach-ak98/include/mach/io.h
new file mode 100644
index 00000000000..7a5373cc23f
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/io.h
@@ -0,0 +1,71 @@
+/*
+ * linux/include/asm-arm/arch-s3c2410/io.h
+ *  from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *	     (C) 2003 Simtec Electronics
+*/
+
+//#ifndef __ASM_ARM_ARCH_IO_H
+//#define __ASM_ARM_ARCH_IO_H
+#ifndef __ARCH_ARM_MACH_AK98_IO_H
+#define __ARCH_ARM_MACH_AK98_IO_H
+
+//#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
+ * and are translated to the start of IO.  Note that all addresses are
+ * not shifted left!
+ */
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)	(x)
+
+#define __io(a)		((void __iomem *)(a))
+
+#define AK98_DUMP_REG(x) { printk("reg 0x%x=0x%x\n",(u32)AK98_##x,(u32)__raw_readl(AK98_##x)); }
+
+static inline unsigned long AKSET_BITS(unsigned long bits_result, void *reg)
+{
+	volatile unsigned long val;
+	val = __raw_readl(reg);
+
+	val |= bits_result;
+
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static inline unsigned long AKCLR_BITS(unsigned long bits_result, void *reg)
+{
+	volatile unsigned long val;
+	val = __raw_readl(reg);
+	val &= ~bits_result;
+
+	__raw_writel(val, reg);
+
+	return 0;
+}
+
+static inline bool AKGET_BIT(unsigned long bit_result, void *reg)
+{
+	unsigned long val;
+
+	val = __raw_readl(reg) & bit_result;
+
+	if (val == bit_result)
+		return true;
+	else
+		return false;
+
+}
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/irqs.h b/arch/arm/mach-ak98/include/mach/irqs.h
new file mode 100644
index 00000000000..1c857950fbc
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/irqs.h
@@ -0,0 +1,262 @@
+/* linux/arch/arm/mach-ak98/include/mach/irqs.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#define AK98_IRQ(x)		(x)
+
+/*
+ *Main CPU Interrupts
+ */
+
+#define	IRQ_H264_DECODER	AK98_IRQ(0)
+#define	IRQ_DISPLAY_CTRL	AK98_IRQ(1)
+#define	IRQ_CAMERA_IF		AK98_IRQ(2)
+#define	IRQ_MOTIONESTIMATION	AK98_IRQ(3)
+
+#define	IRQ_JPEG		AK98_IRQ(4)
+#define	IRQ_MAC			AK98_IRQ(5)
+#define	IRQ_AK_RESERVED0	AK98_IRQ(6)	/* NO. 6 Reserved */
+#define	IRQ_ROTATION		AK98_IRQ(7)
+
+#define	IRQ_DAC			AK98_IRQ(8)
+#define	IRQ_SIGDELTA_ADC	AK98_IRQ(9)
+#define	IRQ_L2MEM		AK98_IRQ(10)
+#define	IRQ_NF_ECC		AK98_IRQ(11)
+
+#define	IRQ_NF_CTRL		AK98_IRQ(12)
+#define	IRQ_UART3		AK98_IRQ(13)	/* NOTE: UART3~0 == UART4~1 in datasheet */
+#define	IRQ_UART2		AK98_IRQ(14)
+#define	IRQ_UART1		AK98_IRQ(15)
+
+#define	IRQ_UART0		AK98_IRQ(16)
+#define	IRQ_SPI2		AK98_IRQ(17)
+#define	IRQ_SPI1		AK98_IRQ(18)
+#define	IRQ_I2C			AK98_IRQ(19)
+
+#define	IRQ_2D_ACC		AK98_IRQ(20)
+#define	IRQ_SDIO		AK98_IRQ(21)
+#define	IRQ_MMC_SD		AK98_IRQ(22)
+#define	IRQ_USBHOST_MCU		AK98_IRQ(23)
+
+#define	IRQ_USBHOST_DMA		AK98_IRQ(24)
+#define	IRQ_USBOTG_MCU		AK98_IRQ(25)
+#define	IRQ_USBOTG_DMA		AK98_IRQ(26)
+#define	IRQ_SYSCTRL		AK98_IRQ(27)
+
+#define IRQ_RMVB		AK98_IRQ(28)
+#define IRQ_MPEG2		AK98_IRQ(29)
+#define IRQ_HUFFMAN		AK98_IRQ(30)
+#define IRQ_PCM			AK98_IRQ(31)
+
+/*
+ * System Control Module Sub-IRQs
+ */
+#define IRQ_SYSCTRL_SUB_START	(IRQ_PCM + 1)
+#define	AK98_SYSCTRL_IRQ(x)	((x) + IRQ_SYSCTRL_SUB_START)
+
+#define	IRQ_TOUCHPANEL		AK98_SYSCTRL_IRQ(0)
+#define	IRQ_TIMER5		AK98_SYSCTRL_IRQ(1)
+#define	IRQ_TIMER4		AK98_SYSCTRL_IRQ(2)
+#define	IRQ_TIMER3		AK98_SYSCTRL_IRQ(3)
+
+#define	IRQ_TIMER2		AK98_SYSCTRL_IRQ(4)
+#define	IRQ_TIMER1		AK98_SYSCTRL_IRQ(5)
+#define	IRQ_CLK_ADJUST		AK98_SYSCTRL_IRQ(6)
+#define	IRQ_WGPIO		AK98_SYSCTRL_IRQ(7)
+
+#define	IRQ_RTC_RDY		AK98_SYSCTRL_IRQ(8)
+#define	IRQ_RTC_ALARM		AK98_SYSCTRL_IRQ(9)
+#define	IRQ_GPIO		AK98_SYSCTRL_IRQ(10)
+#define IRQ_RTC_TIMER		AK98_SYSCTRL_IRQ(11)
+
+#define IRQ_PEN_DOWN_FILTER	AK98_SYSCTRL_IRQ(12)
+/* System Control Module Sub-IRQs 13~15 are reserved */
+
+/* 
+ * GPIO IRQs
+ */
+#define IRQ_GPIO_SUB_START	(IRQ_PEN_DOWN_FILTER + 1)
+#define AK98_GPIO_IRQ(x)	((x) + IRQ_GPIO_SUB_START)
+
+#define IRQ_GPIO_0		AK98_GPIO_IRQ(0)
+#define IRQ_GPIO_1		AK98_GPIO_IRQ(1)
+#define IRQ_GPIO_2		AK98_GPIO_IRQ(2)
+#define IRQ_GPIO_3		AK98_GPIO_IRQ(3)
+#define IRQ_GPIO_4		AK98_GPIO_IRQ(4)
+#define IRQ_GPIO_5		AK98_GPIO_IRQ(5)
+#define IRQ_GPIO_6		AK98_GPIO_IRQ(6)
+#define IRQ_GPIO_7		AK98_GPIO_IRQ(7)
+#define IRQ_GPIO_8		AK98_GPIO_IRQ(8)
+#define IRQ_GPIO_9		AK98_GPIO_IRQ(9)
+#define IRQ_GPIO_10		AK98_GPIO_IRQ(10)
+#define IRQ_GPIO_11		AK98_GPIO_IRQ(11)
+#define IRQ_GPIO_12		AK98_GPIO_IRQ(12)
+#define IRQ_GPIO_13		AK98_GPIO_IRQ(13)
+#define IRQ_GPIO_14		AK98_GPIO_IRQ(14)
+#define IRQ_GPIO_15		AK98_GPIO_IRQ(15)
+#define IRQ_GPIO_16		AK98_GPIO_IRQ(16)
+#define IRQ_GPIO_17		AK98_GPIO_IRQ(17)
+#define IRQ_GPIO_18		AK98_GPIO_IRQ(18)
+#define IRQ_GPIO_19		AK98_GPIO_IRQ(19)
+#define IRQ_GPIO_20		AK98_GPIO_IRQ(20)
+#define IRQ_GPIO_21		AK98_GPIO_IRQ(21)
+#define IRQ_GPIO_22		AK98_GPIO_IRQ(22)
+#define IRQ_GPIO_23		AK98_GPIO_IRQ(23)
+#define IRQ_GPIO_24		AK98_GPIO_IRQ(24)
+#define IRQ_GPIO_25		AK98_GPIO_IRQ(25)
+#define IRQ_GPIO_26		AK98_GPIO_IRQ(26)
+#define IRQ_GPIO_27		AK98_GPIO_IRQ(27)
+#define IRQ_GPIO_28		AK98_GPIO_IRQ(28)
+#define IRQ_GPIO_29		AK98_GPIO_IRQ(29)
+#define IRQ_GPIO_30		AK98_GPIO_IRQ(30)
+#define IRQ_GPIO_31		AK98_GPIO_IRQ(31)
+
+#define IRQ_GPIO_32		AK98_GPIO_IRQ(32)
+#define IRQ_GPIO_33		AK98_GPIO_IRQ(33)
+#define IRQ_GPIO_34		AK98_GPIO_IRQ(34)
+#define IRQ_GPIO_35		AK98_GPIO_IRQ(35)
+#define IRQ_GPIO_36		AK98_GPIO_IRQ(36)
+#define IRQ_GPIO_37		AK98_GPIO_IRQ(37)
+#define IRQ_GPIO_38		AK98_GPIO_IRQ(38)
+#define IRQ_GPIO_39		AK98_GPIO_IRQ(39)
+#define IRQ_GPIO_40		AK98_GPIO_IRQ(40)
+#define IRQ_GPIO_41		AK98_GPIO_IRQ(41)
+#define IRQ_GPIO_42		AK98_GPIO_IRQ(42)
+#define IRQ_GPIO_43		AK98_GPIO_IRQ(43)
+#define IRQ_GPIO_44		AK98_GPIO_IRQ(44)
+#define IRQ_GPIO_45		AK98_GPIO_IRQ(45)
+#define IRQ_GPIO_46		AK98_GPIO_IRQ(46)
+#define IRQ_GPIO_47		AK98_GPIO_IRQ(47)
+#define IRQ_GPIO_48		AK98_GPIO_IRQ(48)
+#define IRQ_GPIO_49		AK98_GPIO_IRQ(49)
+#define IRQ_GPIO_50		AK98_GPIO_IRQ(50)
+#define IRQ_GPIO_51		AK98_GPIO_IRQ(51)
+#define IRQ_GPIO_52		AK98_GPIO_IRQ(52)
+#define IRQ_GPIO_53		AK98_GPIO_IRQ(53)
+#define IRQ_GPIO_54		AK98_GPIO_IRQ(54)
+#define IRQ_GPIO_55		AK98_GPIO_IRQ(55)
+#define IRQ_GPIO_56		AK98_GPIO_IRQ(56)
+#define IRQ_GPIO_57		AK98_GPIO_IRQ(57)
+#define IRQ_GPIO_58		AK98_GPIO_IRQ(58)
+#define IRQ_GPIO_59_RESERVED	AK98_GPIO_IRQ(59)	/* reserved */
+#define IRQ_GPIO_60_RESERVED	AK98_GPIO_IRQ(60)	/* reserved */
+#define IRQ_GPIO_61		AK98_GPIO_IRQ(61)
+#define IRQ_GPIO_62		AK98_GPIO_IRQ(62)
+#define IRQ_GPIO_63		AK98_GPIO_IRQ(63)
+
+#define IRQ_GPIO_64		AK98_GPIO_IRQ(64)
+#define IRQ_GPIO_65		AK98_GPIO_IRQ(65)
+#define IRQ_GPIO_66		AK98_GPIO_IRQ(66)
+#define IRQ_GPIO_67		AK98_GPIO_IRQ(67)
+#define IRQ_GPIO_68		AK98_GPIO_IRQ(68)
+#define IRQ_GPIO_69		AK98_GPIO_IRQ(69)
+#define IRQ_GPIO_70		AK98_GPIO_IRQ(70)
+#define IRQ_GPIO_71		AK98_GPIO_IRQ(71)
+#define IRQ_GPIO_72		AK98_GPIO_IRQ(72)
+#define IRQ_GPIO_73		AK98_GPIO_IRQ(73)
+#define IRQ_GPIO_74		AK98_GPIO_IRQ(74)
+#define IRQ_GPIO_75		AK98_GPIO_IRQ(75)
+#define IRQ_GPIO_76		AK98_GPIO_IRQ(76)
+#define IRQ_GPIO_77		AK98_GPIO_IRQ(77)
+#define IRQ_GPIO_78		AK98_GPIO_IRQ(78)
+#define IRQ_GPIO_79		AK98_GPIO_IRQ(79)
+#define IRQ_GPIO_80		AK98_GPIO_IRQ(80)
+#define IRQ_GPIO_81		AK98_GPIO_IRQ(81)
+#define IRQ_GPIO_82		AK98_GPIO_IRQ(82)
+#define IRQ_GPIO_83		AK98_GPIO_IRQ(83)
+#define IRQ_GPIO_84		AK98_GPIO_IRQ(84)
+#define IRQ_GPIO_85		AK98_GPIO_IRQ(85)
+#define IRQ_GPIO_86		AK98_GPIO_IRQ(86)
+#define IRQ_GPIO_87		AK98_GPIO_IRQ(87)
+#define IRQ_GPIO_88		AK98_GPIO_IRQ(88)
+#define IRQ_GPIO_89		AK98_GPIO_IRQ(89)
+#define IRQ_GPIO_90		AK98_GPIO_IRQ(90)
+#define IRQ_GPIO_91		AK98_GPIO_IRQ(91)
+#define IRQ_GPIO_92		AK98_GPIO_IRQ(92)
+#define IRQ_GPIO_93		AK98_GPIO_IRQ(93)
+#define IRQ_GPIO_94_RESERVED	AK98_GPIO_IRQ(94)	/* reserved */
+#define IRQ_GPIO_95_RESERVED	AK98_GPIO_IRQ(95)	/* reserved */
+
+#define IRQ_GPIO_96_RESERVED	AK98_GPIO_IRQ(96)
+#define IRQ_GPIO_97		AK98_GPIO_IRQ(97)
+#define IRQ_GPIO_98		AK98_GPIO_IRQ(98)
+#define IRQ_GPIO_99		AK98_GPIO_IRQ(99)
+#define IRQ_GPIO_100		AK98_GPIO_IRQ(100)
+#define IRQ_GPIO_101		AK98_GPIO_IRQ(101)
+#define IRQ_GPIO_102		AK98_GPIO_IRQ(102)
+#define IRQ_GPIO_103		AK98_GPIO_IRQ(103)
+#define IRQ_GPIO_104		AK98_GPIO_IRQ(104)
+#define IRQ_GPIO_105		AK98_GPIO_IRQ(105)
+#define IRQ_GPIO_106		AK98_GPIO_IRQ(106)
+#define IRQ_GPIO_107		AK98_GPIO_IRQ(107)
+#define IRQ_GPIO_108_RESERVED	AK98_GPIO_IRQ(108)	/* reserved */
+#define IRQ_GPIO_109		AK98_GPIO_IRQ(109)
+#define IRQ_GPIO_110		AK98_GPIO_IRQ(110)
+#define IRQ_GPIO_111		AK98_GPIO_IRQ(111)
+#define IRQ_GPIO_112		AK98_GPIO_IRQ(112)
+#define IRQ_GPIO_113		AK98_GPIO_IRQ(113)
+#define IRQ_GPIO_114		AK98_GPIO_IRQ(114)
+#define IRQ_GPIO_115		AK98_GPIO_IRQ(115)
+#define IRQ_GPIO_116		AK98_GPIO_IRQ(116)
+
+/* NO IRQ for MCGPIOs */
+
+/*
+ * L2 Memory Sub-IRQs
+ */
+#define AK98_L2MEM_SUB_START	(IRQ_GPIO_116 + 1)
+#define AK98_L2MEM_IRQ(x)	((x) + AK98_L2MEM_SUB_START)
+
+#define IRQ_L2_FRAC_DMA		AK98_L2MEM_IRQ(0)
+#define IRQ_L2_UART0_TX_DMA	AK98_L2MEM_IRQ(1)
+#define IRQ_L2_UART0_RX_DMA	AK98_L2MEM_IRQ(2)
+#define IRQ_L2_UART1_TX_DMA	AK98_L2MEM_IRQ(3)
+#define IRQ_L2_UART1_RX_DMA	AK98_L2MEM_IRQ(4)
+#define IRQ_L2_UART2_TX_DMA	AK98_L2MEM_IRQ(5)
+#define IRQ_L2_UART2_RX_DMA	AK98_L2MEM_IRQ(6)
+#define IRQ_L2_UART3_TX_DMA	AK98_L2MEM_IRQ(7)
+#define IRQ_L2_UART3_RX_DMA	AK98_L2MEM_IRQ(8)
+#define IRQ_L2_BUF0_DMA		AK98_L2MEM_IRQ(9)
+#define IRQ_L2_BUF1_DMA		AK98_L2MEM_IRQ(10)
+#define IRQ_L2_BUF2_DMA		AK98_L2MEM_IRQ(11)
+#define IRQ_L2_BUF3_DMA		AK98_L2MEM_IRQ(12)
+#define IRQ_L2_BUF4_DMA		AK98_L2MEM_IRQ(13)
+#define IRQ_L2_BUF5_DMA		AK98_L2MEM_IRQ(14)
+#define IRQ_L2_BUF6_DMA		AK98_L2MEM_IRQ(15)
+#define IRQ_L2_BUF7_DMA		AK98_L2MEM_IRQ(16)
+#define IRQ_L2_LDMA_VLD		AK98_L2MEM_IRQ(17)
+#define IRQ_L2_CRC_VLD		AK98_L2MEM_IRQ(18)
+#define IRQ_L2_SMALL_LOOP	AK98_L2MEM_IRQ(19)
+
+/*
+ * AW9523 Extension chip Sub-IRQs
+ */
+#define AK98_AW9523_IRQ_START  (IRQ_L2_SMALL_LOOP + 1)
+#define AK98_AW9523_IRQ(x)  ((x) + AK98_AW9523_IRQ_START)
+
+#define IRQ_AW9523_P00 		AK98_AW9523_IRQ(0)
+#define IRQ_AW9523_P01		AK98_AW9523_IRQ(1)
+#define IRQ_AW9523_P02		AK98_AW9523_IRQ(2)
+#define IRQ_AW9523_P03		AK98_AW9523_IRQ(3)
+#define IRQ_AW9523_P04		AK98_AW9523_IRQ(4)
+#define IRQ_AW9523_P05		AK98_AW9523_IRQ(5)
+#define IRQ_AW9523_P06		AK98_AW9523_IRQ(6)
+#define IRQ_AW9523_P07		AK98_AW9523_IRQ(7)
+#define IRQ_AW9523_P10		AK98_AW9523_IRQ(8)
+#define IRQ_AW9523_P11		AK98_AW9523_IRQ(9)
+#define IRQ_AW9523_P12		AK98_AW9523_IRQ(10)
+#define IRQ_AW9523_P13		AK98_AW9523_IRQ(11)
+#define IRQ_AW9523_P14		AK98_AW9523_IRQ(12)
+#define IRQ_AW9523_P15		AK98_AW9523_IRQ(13)
+#define IRQ_AW9523_P16		AK98_AW9523_IRQ(14)
+#define IRQ_AW9523_P17		AK98_AW9523_IRQ(15)
+
+#define NR_IRQS			(IRQ_AW9523_P17 + 1)
+
+#endif	/* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ak98/include/mach/l2.h b/arch/arm/mach-ak98/include/mach/l2.h
new file mode 100644
index 00000000000..1d7dd079d7c
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/l2.h
@@ -0,0 +1,356 @@
+/*
+ * linux/arch/arm/mach-ak98/include/mach/l2.h
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_L2_H
+#define __ASM_ARCH_L2_H
+
+#include <mach/ak880x_addr.h>
+#include <asm/io.h>
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#include <mach/regs-l2.h>
+
+
+#define AK98_L2_DEBUG	1
+//#undef AK98_L2_DEBUG
+
+/*
+ * AK98xx L2 Control Register List and Bit map definition
+ * TODO: Add all register bit maps and move all to map.h in the future.
+*/
+#define vL2DMA_ADDRBUF0			REG_VA_ADDR(AK98_VA_L2CTRL, 0x00)
+#define vL2DMA_CONBUF0			REG_VA_ADDR(AK98_VA_L2CTRL, 0x40)
+#define vL2DMA_CONBUF0			REG_VA_ADDR(AK98_VA_L2CTRL, 0x40)
+
+#define AK98_L2_DMA_REQ_BUF_START		24
+#define AK98_L2_DMA_REQ_BUF_REQ_MASK		(0xFFFF << 16)
+#define AK98_L2_DMA_REQ_UART_BUF_REQ_START	16
+#define AK98_L2_DMA_REQ_FRAC_DMA_LEN_START	10
+#define AK98_L2_DMA_REQ_FRAC_DMA_LEN_MASK	(0x3F << AK98_L2_DMA_REQ_FRAC_DMA_LEN_START)
+#define AK98_L2_DMA_REQ_FRAC_DMA_REQ		(1 << 9)
+#define AK98_L2_DMA_REQ_FRAC_DMA_DIR_WR		(1 << 8)
+#define AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START	1
+#define AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_MASK	(0x7F << AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START)
+#define AK98_L2_DMA_REQ_EN			(1 << 0)
+
+#define AK98_L2_FRAC_DMA_AHB_FLAG_EN		(1 << 29)
+#define AK98_L2_FRAC_DMA_LDMA_FLAG_EN		(1 << 28)
+
+#define AK98_L2_FRAC_DMA_LOW_ADDR_MASK		(0xFFFFFFF << 0)
+
+#define AK98_L2_COMMON_BUF_CFG_BUF7_CLR		(1 << 31)
+#define AK98_L2_COMMON_BUF_CFG_BUF6_CLR		(1 << 30)
+#define AK98_L2_COMMON_BUF_CFG_BUF5_CLR		(1 << 29)
+#define AK98_L2_COMMON_BUF_CFG_BUF4_CLR		(1 << 28)
+#define AK98_L2_COMMON_BUF_CFG_BUF3_CLR		(1 << 27)
+#define AK98_L2_COMMON_BUF_CFG_BUF2_CLR		(1 << 26)
+#define AK98_L2_COMMON_BUF_CFG_BUF1_CLR		(1 << 25)
+#define AK98_L2_COMMON_BUF_CFG_BUF0_CLR		(1 << 24)
+#define AK98_L2_COMMON_BUF_CFG_BUF_CLR_START	24
+#define AK98_L2_COMMON_BUF_CFG_BUF0_7_CLR_MASK	(0xFF << AK98_L2_COMMON_BUF_CFG_BUF_START)
+#define AK98_L2_COMMON_BUF_CFG_BUF_VLD_START	16
+#define AK98_L2_COMMON_BUF_CFG_BUF0_7_VLD_MASK	(0xFF << AK98_L2_COMMON_BUF_CFG_BUF_VLD_START
+#define AK98_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START	0
+#define AK98_L2_COMMON_BUF_CFG_BUF_DIR_START	8
+
+#define AK98_L2_UART_BUF_CFG_BUF_START		16
+
+#define AK98_L2_UART_BUF_CFG_UART_EN_MASK	(0xF << 28)
+#define AK98_L2_UART_BUF_CFG_UART_CLR_MASK	(0xFF << 16)
+#define AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_EN	(1 << 3)
+#define AK98_L2_UART_BUF_CFG_CPU_BUF_NUM_START	4
+#define AK98_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK	(0xF << AK98_L2_UART_BUF_CFG_CPU_BUF_NUM_START)
+#define AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_START	0
+#define AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK	(0x7 << AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_START)
+
+#define AK98_L2_DMA_INTR_ENABLE_BUF_START	9
+#define AK98_L2_DMA_INTR_ENABLE_UART_BUF_START	1
+#define AK98_L2_DMA_INTR_ENABLE_FRAC_INTR_EN	(1 << 0)
+
+/*
+ * AK98xx L2 buffer size(buffer 0 to buffer 7), all 512Bytes.
+ * NOTE: L2 buffer 8 to 15 dedicate to UART 1 to 4 &  USB 2.0 Controller, 
+ *           and the corresponding L2 buffer size could be 64, 128 and 256 Bytes.
+ * See AK98xx Programmer's Guide for details (AK9801 preferably).
+ */
+#define AK98_L2_BUFFER_SIZE	512
+
+/*
+  * AK98xx L2 DMA waiting times in loop
+  * TODO: Must be change to waiting time based on CPU frequency when frequency APIs are done.
+  */
+#define AK98_L2_MAX_DMA_WAIT_TIME	50 * 1000000UL
+
+/*
+ * AK98xx DMA size in bytes per transfer (Always 64Bytes)
+ * L2 DMA transfer follows this definition.
+ */
+#define AK98_DMA_ONE_SHOT_LEN		64
+
+/*
+ * AK98xx L2 Buffer Status Multiply Ratio(64)
+ * Buffer Status Register 1 & 2: The number of data = Bufn_sta * AK98_L2_BUF_STATUS_MULTIPLY_RATIO
+ */
+#define AK98_L2_BUF_STATUS_MULTIPLY_RATIO	64
+
+/*
+ * L2 Buffer ID Assignment:
+ * 0 - 7: L2 common buffer, could be used by different peripherals
+ * 8 - 15: Dedicate L2 buffer for UART
+ * 16 - 18: Dedicate L2 buffer for USB
+ */
+#define AK98_L2_COMMON_BUFFER_NUM	8
+#define AK98_L2_UART_BUFFER_NUM		8
+#define AK98_L2_USB_HOST_BUFFER_NUM	1
+#define AK98_L2_USB_BUFFER_NUM		2
+
+#define AK98_L2_UART_BUFFER_INDEX	AK98_L2_COMMON_BUFFER_NUM
+#define AK98_L2_USB_HOST_BUFFER_INDEX	(AK98_L2_UART_BUFFER_INDEX + AK98_L2_UART_BUFFER_NUM)
+#define AK98_L2_USB_BUFFER_INDEX	(AK98_L2_USB_HOST_BUFFER_INDEX + AK98_L2_USB_HOST_BUFFER_NUM)
+
+#define AK98_L2_COMMON_BUFFER_LEN	512
+#define AK98_L2_UART_BUFFER_LEN		128
+#define AK98_L2_USB_HOST_BUFFER_LEN	256
+#define AK98_L2_USB_BUFFER_LEN		64
+
+#define AK98_L2_COMMON_BUFFER_OFFSET	0
+#define AK98_L2_UART_BUFFER_OFFSET	(AK98_L2_COMMON_BUFFER_LEN * AK98_L2_COMMON_BUFFER_NUM)
+#define AK98_L2_USB_HOST_BUFFER_OFFSET	(AK98_L2_UART_BUFFER_OFFSET + AK98_L2_UART_BUFFER_LEN * AK98_L2_UART_BUFFER_NUM)
+#define AK98_L2_USB_BUFFER_OFFSET	(AK98_L2_USB_HOST_BUFFER_OFFSET + AK98_L2_USB_BUFFER_LEN * AK98_L2_USB_BUFFER_NUM)
+
+/*
+ * AK98xx L2 device list which may use L2 memory.
+ * The devices are defined according to L2 Buffer Assignement 1 & 2 register bit sequence.
+ */
+typedef enum {
+	ADDR_USB_EP2	= 0,		/* USB 2.0 HS OTG Controller: Endpoint 2 */
+	ADDR_USB_EP3,			/* USB 2.0 HS OTG Controller: Endpoint 3 */
+	ADDR_USB_EP4,			/* USB 2.0 HS OTG Controller: Endpoint 4 */
+	ADDR_NFC,			/* NAND Flash Controller */
+	ADDR_MMC_SD,			/* MMC/SD interface */
+	ADDR_SDIO,			/* SDIO interface */
+	ADDR_RESERVED,			/* Reserved */
+	ADDR_SPI1_RX,			/* Rx buffer of SPI1 Controller */
+	ADDR_SPI1_TX,			/* Tx buffer of SPI1 Controller */
+	ADDR_DAC,			/* DAC control module */
+	ADDR_SPI2_RX,			/* Rx buffer of SPI2 Controller */
+	ADDR_SPI2_TX,			/* Tx buffer of SPI2 Controller */
+	ADDR_PCM_RX,			/* Rx buffer of PCM Controller */
+	ADDR_PCM_TX,			/* Tx buffer of PCM Controller */
+	ADDR_ADC,			/* ADC2 and ADC3 */
+	ADDR_USB_EP5,			/* USB 2.0 HS OTG Controller: Endpoint 5 */
+	ADDR_USB_EP6,			/* USB 2.0 HS OTG Controller: Endpoint 6 */
+} ak98_l2_device_t;
+
+#define BUF_NULL			0xFF	/* Invalid L2 buffer ID */
+#define AK98_L2_UART_BUF_START_ID	AK98_L2_COMMON_BUFFER_NUM	/* UART used buffer ID from 8 */
+
+/*
+ * Maximum L2 DMA status value (The value in CPU-Controlled Buffer and Buffer8 ~ Buffer15 Configuration Register)
+ * The maximum DMA transfer bytes = MAX_L2_DMA_STATUS_VALUE * 64
+ */
+#define MAX_L2_DMA_STATUS_VALUE		0x8
+#define MAX_L2_BUFFER_USED_TIMES	0xFFFF
+
+/*
+ * Data transfer direction between L2 memory and external RAM
+ */
+typedef enum {
+	BUF2MEM = 0,	/* Data transfer from L2 buffer to external RAM */
+	MEM2BUF,	/* Data transfer from external RAM to L2 buffer */
+} ak98_l2_dma_transfer_direction_t;
+
+/*
+ * Callback function when L2 DMA/fraction DMA interrupt handler is done
+ */
+typedef void (*ak98_l2_callback_func_t)(unsigned long data);
+
+/*
+ * L2 buffer status
+ */
+typedef enum {
+	L2_STAT_USED = 0,	/* Current L2 buffer is used by some device */
+	L2_STAT_IDLE,		/* Current L2 buffer is NOT used by some device, thus could be allocated */
+} ak98_l2_buffer_status_t;
+
+/*
+ * L2 buffer information
+ */
+typedef struct {
+	u8 id;				/* L2 buffer ID (0~17) */
+	ak98_l2_buffer_status_t usable;	/* L2 buffer status(used or idle) */
+	u16 used_time;			/* Counter on L2 buffer used times */
+} ak98_l2_buffer_info_t;
+
+/*
+ * Information on device which use L2 memory
+ */
+typedef struct {
+	ak98_l2_device_t device;	/* Device ID */
+	u8 id;				/* TODO: Remove id in the future since array index already represent buffer id */
+} ak98_l2_device_info_t;
+
+/*
+ * L2 DMA usage information (including DMA/fraction DMA/external RAM/Callback function)
+ */
+typedef struct {
+	bool dma_start;
+	bool intr_enable;
+	ak98_l2_dma_transfer_direction_t direction;
+	void *dma_addr;
+	u32  dma_op_times;
+	bool need_frac;
+	bool dma_frac_start;
+	void *dma_frac_addr;
+	u32  dma_frac_offset;
+	u32  dma_frac_data_len;
+	ak98_l2_callback_func_t callback_func;
+	unsigned long data;
+} ak98_l2_dma_info_t;
+
+/**
+ * ak98_l2_init - Initialize linux kernel L2 memory support
+ */
+void __init ak98_l2_init(void);
+
+/**
+ * ak98_l2_alloc - Allocate a common L2 buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak98_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ */
+u8 ak98_l2_alloc(ak98_l2_device_t device);
+
+/**
+ * ak98_l2_free - Free L2 common buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak98_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ *  NOTE: Return the previous L2 buffer ID if a L2 buffer has been allocated to the device.
+ *            This means one device could get only one L2 buffer maximum.
+ */
+void ak98_l2_free(ak98_l2_device_t device);
+
+/**
+ * ak98_l2_set_dma_callback - Set callback function when L2 DMA/fraction DMA interrupt handler is done
+ *  @id:		L2 buffer ID
+ *  @func:	Callback function
+ *  @data:	Arguments used by callback function
+ *  Return true(Always)
+ *  
+ *  NOTE: Caller MUST guarantee that L2 buffer ID is valid. And since the callback function is called
+ *  in interrupt handler, it MUST NOT call any functions which may sleep.
+ */
+bool ak98_l2_set_dma_callback(u8 id, ak98_l2_callback_func_t func, unsigned long data);
+
+/**
+ * ak98_l2_combuf_dma - Start data tranferring between memory and l2 common buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:			L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:		Open interrupt for this L2 buffer or not
+ */
+void ak98_l2_combuf_dma(unsigned long ram_addr, u8 id, unsigned int bytes, ak98_l2_dma_transfer_direction_t direction, bool intr_enable);
+
+/**
+ * ak98_l2_combuf_wait_dma_finish - Wait for L2 DMA finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak98_l2_combuf_dma.
+ */
+bool ak98_l2_combuf_wait_dma_finish(u8 id);
+
+/**
+ * ak98_l2_combuf_cpu - Transfer data between memory and l2 common buffer in CPU mode
+ *  @ram_addr:	External RAM address(Physical)
+ *  @id:	L2 buffer ID
+ *  @bytes:	Data transfer size
+ *  @direction:	Data transfer direction between L2 memory and external RAM
+ *
+ *  NOTE: According to XuChang, if one transfer data from Peripheral --> L2 Buffer --> RAM, 
+ *            special care need to be taken when data size is NOT multiple of 64Bytes.
+ *            Pheripheral driver must check hardware signals to confirm data has been transfer from
+ *            peripheral to L2 buffer since L2 do NOT provide some mechanism to confirm data has
+ *            been in L2 Buffer. Driver can and only can call ak98_l2_combuf_cpu() to copy data from L2
+ *            Buffer --> RAM after checking hardware signals.
+ *            As to 64Bytes * n size data, L2 could check Buffer Status Status Counter to confirm that
+ *            Data has been transfer from peripheral to L2 buffer, so no hardware signals checking needed.
+ */
+void ak98_l2_combuf_cpu(unsigned long ram_addr, u8 id, unsigned int bytes, ak98_l2_dma_transfer_direction_t direction);
+
+/**
+ * ak98_l2_get_status - Get L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+u8 ak98_l2_get_status(u8 id);
+
+/**
+ * ak98_l2_clr_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+void ak98_l2_clr_status(u8 id);
+
+/**
+ * ak98_l2_set_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ *  @status:	Status to be set (0 ~ 8)
+ */
+void ak98_l2_set_status(u8 id, u8 status);
+
+#ifdef AK98_L2_DEBUG
+#define AK98_L2_PRINT_FUNCLINES() do { printk("%s(): line: %d\n", __func__, __LINE__); } while (0)
+
+static inline void ak98_l2_dump_registers(void)
+{
+	printk("AK98xx L2 Register Dumping Begin:\n");
+
+	printk("  rL2_DMAREQ(C080)        = 0x%08X, rL2_FRACDMAADDR(C084)     = 0x%0X\n",
+		(unsigned int)rL2_DMAREQ, (unsigned int)rL2_FRACDMAADDR);
+	printk("  rL2_CONBUF0_7(C088) = 0x%08X, rL2_CONBUF8_15(C08C) = 0x%0X\n",
+		(unsigned int)rL2_CONBUF0_7, (unsigned int)rL2_CONBUF8_15);
+	printk("  rL2_BUFASSIGN1(C090)    = 0x%08X, rL2_BUFINTEN(C09C)  = 0x%0X\n",
+		(unsigned int)rL2_BUFASSIGN1, (unsigned int)rL2_BUFINTEN);
+	printk("  rL2_BUFSTAT1(C0A0)      = 0x%08X, rL2_BUFSTAT2(C0A8)    = 0x%0X\n",
+		(unsigned int)rL2_BUFSTAT1, (unsigned int)rL2_BUFSTAT2);
+
+	printk("AK98xx L2 Register Dumping End.\n");
+}
+
+static inline void ak98_l2_print_array(const char *name, unsigned char *array, int len)
+{
+	int i;
+
+	printk("%s[%d] = {\n ", name, len);
+	for (i = 0; i < len; i++) {
+		printk(" 0x%02X,", array[i]);
+		if (i % 16 == 15)
+			printk("\n ");
+	}
+	printk("};\n");
+
+}
+
+#else
+#define AK98_L2_PRINT_FUNCLINES() do { } while (0)
+
+static inline void ak98_l2_dump_registers(void)
+{
+}
+static inline void ak98_l2_print_array(const char *name, unsigned int *array, int len)
+{
+}
+#endif
+
+#endif	/* __ASM_ARCH_L2_H */
diff --git a/arch/arm/mach-ak98/include/mach/l2_exebuf.h b/arch/arm/mach-ak98/include/mach/l2_exebuf.h
new file mode 100644
index 00000000000..43d28d858e6
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/l2_exebuf.h
@@ -0,0 +1,200 @@
+#ifndef __L2_EXEBUF

+#define __L2_EXEBUF

+

+

+#include <linux/io.h>

+#include <mach/gpio.h>

+#include <mach/map.h>

+

+

+#define L2_FRAC_ADDR				(AK98_VA_DEV + 0xc084)

+#define	CPU_CHIP_ID					(AK98_VA_SYSCTRL + 0x00)

+#define	CLOCK_DIV_REG				(AK98_VA_SYSCTRL + 0x04)

+#define	CLOCK_CTRL_REG				(AK98_VA_SYSCTRL + 0x0C)

+#define	PHY_CLOCK_CTRL_REG			(AK98_PA_SYSCTRL + 0x0C)

+#define PHY_CLOCK_DIV_REG   		(AK98_PA_SYSCTRL + 0x04)

+#define PHY_RAM_CFG_REG4			(AK98_PA_REGRAM + 0x0C)

+

+#define AK98_PA_WGPIO_POLARITY		(AK98_PA_SYSCTRL + 0x3C)

+#define AK98_PA_WGPIO_CLEAR			(AK98_PA_SYSCTRL + 0x40)

+#define AK98_PA_WGPIO_ENABLE		(AK98_PA_SYSCTRL + 0x44)

+#define AK98_PA_WGPIO_STATUS		(AK98_PA_SYSCTRL + 0x48)

+

+#define RAM_CFG_REG1				(AK98_VA_REGRAM + 0x00)

+#define RAM_CFG_REG2				(AK98_VA_REGRAM + 0x04)

+#define RAM_CFG_REG3				(AK98_VA_REGRAM + 0x08)

+#define RAM_CFG_REG4				(AK98_VA_REGRAM + 0x0C)

+#define RAM_CPU_CMD					(AK98_VA_REGRAM + 0x10)

+#define PHY_RAM_CFG_REG1			(AK98_PA_REGRAM + 0x00)

+#define PHY_RAM_CFG_REG2			(AK98_PA_REGRAM + 0x04)

+#define PHY_RAM_CFG_REG3			(AK98_PA_REGRAM + 0x08)

+#define PHY_RAM_CFG_REG4			(AK98_PA_REGRAM + 0x0C)

+#define PHY_RAM_CPU_CMD				(AK98_PA_REGRAM + 0x10)

+

+#define FIFO_R_EMPTY			(1 << 16)

+#define FIFO_CMD_EMPTY			(1 << 14)

+#define AUTO_REFRESH_EN			(1 << 0)

+#define RAM_CLOCK_DISABLE		(1 << 10)

+#define ENTER_STANDBY			(1 << 13)

+#define REFRESH_PERIOD_INTERVAL	(0x39f << 1)

+

+#define LED_PHY_ON	do {\

+	unsigned long value;\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x00a8);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x00a8);\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x0094);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x0094);\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x0098);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x0098);\

+	} while(0)

+	

+#define LED_PHY_OFF	do {\

+	unsigned long value;\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x00a8);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x00a8);\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x0094);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x0094);\

+	value = __raw_readl(AK98_PA_SYSCTRL + 0x0098);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_PA_SYSCTRL + 0x0098);\

+	} while(0)

+

+#define LED_VIRT_ON	do {\

+	unsigned long value;\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x00a8);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x00a8);\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x0094);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x0094);\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x0098);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x0098);\

+	} while(0)

+

+#define LED_VIRT_OFF	do {\

+	unsigned long value;\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x00a8);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x00a8);\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x0094);\

+	value &= ~(1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x0094);\

+	value = __raw_readl(AK98_VA_SYSCTRL + 0x0098);\

+	value |= (1 << 16);\

+	__raw_writel(value, AK98_VA_SYSCTRL + 0x0098);\

+	} while(0)

+

+#define DISABLE_CACHE_MMU()	do {\

+	__asm__ __volatile__(\

+		"1: mrc  p15, 0, r15, c7, c14, 3\n\t" /* test,clean,invalidate D cache */\

+		"bne  1b\n\t"\

+		"mcr  p15, 0, %0, c8, c7, 0\n\t" /* invalidate  I & D  TLBs */\

+		"mcr  p15, 0, %0, c7, c5, 0\n\t" /* invalidate I caches */\

+        "mrc  p15, 0, %0, c1, c0, 0\n\t"\

+        "bic  %0, %0, #0x1000\n\t"	/* disable Icache */\

+        "bic  %0, %0, #0x0005\n\t"	/* disable Dcache,mmu*/\

+        "ldr  %1, =l2_phys_run\n\t"	/* load 0x480000xx address */\

+        "b  suspend_turn_off_mmu\n\t"\

+        "   .align 5\n\t"			/* 32 byte aligned */\

+        "suspend_turn_off_mmu:\n\t"\

+        "mcr  p15, 0, %0, c1, c0, 0\n\t"\

+        "mov  pc, %1\n\t"		/* jumpto 0x480000xx then run */\

+        "l2_phys_run:\n\t"		/* mark the real running addr--> L2 buff */\

+        : : "r"(0),"r"(1));\

+	} while(0)

+

+#define ENABLE_CACHE_MMU()	do {\

+	__asm__ __volatile__(\

+		"mcr  p15, 0, %0, c8, c7, 0\n\t" /* invalidate I & D TLBs */\

+		"mcr  p15, 0, %0, c7, c7, 0\n\t" /* invalidate I & D caches */\

+		"mcr  p15, 0, %0, c7, c10, 4\n\t" /* drain write buffer */\

+		"mrc  p15, 0, %0, c1, c0, 0\n\t"\

+		"orr  %0, %0, #0x1000\n\t"\

+		"orr  %0, %0, #0x0005\n\t"\

+		"b	resume_turn_on_mmu\n\t"\

+		"	.align 5\n\t"\

+		"resume_turn_on_mmu:\n\t"\

+		"mcr  p15, 0, %0, c1, c0, 0\n\t"\

+		::"r"(2));\

+	} while(0)

+

+#define	PM_DELAY(time)	do { \

+	__asm__ __volatile__(\

+		"1:\n\t"	\

+		"subs %0, %0, #1\n\t"\

+		"bne 1b\n\t"\

+		::"r"(time));\

+	} while(0)

+

+#define DDR2_ENTER_POWERDOWN() do {\

+    /* send precharge all banks */\

+    __raw_writel(0x0aa00400, PHY_RAM_CPU_CMD);\

+    /* close odt and asserting low on cke ,close odt and send enter powerdown command */\

+    __raw_writel(0x04f00000, PHY_RAM_CPU_CMD);\

+    }while(0)

+

+#define DDR2_EXIT_POWERDOWN() do {\

+    /* exit precharge power-down mode after delay at least 3 tck */\

+    /* by asserting high on cke and odt remain low */\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    }while(0)

+

+

+#define DDR2_ENTER_SELFREFRESH() do {\

+    /* send precharge all banks */\

+    __raw_writel(0x0aa00400, PHY_RAM_CPU_CMD);\

+    /* close odt and delay taofd=2.5 tck */\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    PM_DELAY(0x1);\

+    /* asserting low on cke ,close odt and send enter self refresh command, entry self refresh */\

+    __raw_writel(0x04c00000, PHY_RAM_CPU_CMD);\

+    }while(0)

+

+#define DDR2_EXIT_SELFREFRESH() do {\

+    /* exit by asserting high on cke and odt remain low until txsrd=200tck */\

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    /* delay txsrd=200tck send nop cmd */ \

+    __raw_writel(0x02f00000, PHY_RAM_CPU_CMD);\

+    PM_DELAY(0x8);\

+    }while(0)

+

+#define DDR2_ENTER_AUTOREFRESH() do {\

+    /* send auto refresh and open odt high */\

+    __raw_writel(0x0ac00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x0ac00000, PHY_RAM_CPU_CMD);\

+    __raw_writel(0x0ac00000, PHY_RAM_CPU_CMD);\

+    }while(0)

+

+

+#define L2_LINK(flag)  __section(.l2mem_##flag)

+#define L2FUNC_NAME(name)	l2_enter_##name

+

+#define SPECIFIC_L2BUF_EXEC(flag, param1,param2,param3,param4) do {\

+	extern char _end_##flag[], _start_##flag[];\

+	int len;\

+	len = _end_##flag - _start_##flag;\

+	l2_exec_buf(_start_##flag,len, param1,param2,param3,param4);\

+}while(0)

+

+int l2_exec_buf(const char *vaddr, int len, unsigned long param1, 

+					unsigned long param2,unsigned long param3, unsigned long param4);

+void sdram_on_change(unsigned int memclk);

+

+void cpu_freq_suspend_check(void);

+void cpu_freq_resume_check(void);

+

+

+#endif	/* L2_EXEBUF */

+

+

diff --git a/arch/arm/mach-ak98/include/mach/l2cache.h b/arch/arm/mach-ak98/include/mach/l2cache.h
new file mode 100644
index 00000000000..55b227e710f
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/l2cache.h
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-ak98/include/l2cache.h
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_L2CACHE_H
+#define __ASM_ARCH_L2CACHE_H
+
+/*
+ * AK98xx L2Cache ON/OFF Flag
+ * AK98_L2CACHE_ENABLE=1        : L2 Cache ON
+ * Undefine AK98_L2CACHE_ENABLE : L2 Cache OFF
+ */
+#define AK98_L2CACHE_ENABLE	1
+
+#include <mach/ak880x_addr.h>
+#include <asm/io.h>
+
+#define AK98_VA_L2CACH_CFG	(AK98_VA_L2CACH + 0x0)
+
+void ak98_l2cache_init(void);
+void ak98_l2cache_clean_finish(void);
+void ak98_l2cache_invalidate(void);
+
+#endif	/* __ASM_ARCH_L2CACHE_H */
diff --git a/arch/arm/mach-ak98/include/mach/lib_l2.h b/arch/arm/mach-ak98/include/mach/lib_l2.h
new file mode 100644
index 00000000000..3618aa88509
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/lib_l2.h
@@ -0,0 +1,357 @@
+/**
+* @FILENAME: l2.h
+* @BRIEF l2 buffer driver head file
+* Copyright (C) 2007 Anyka (Guang zhou) Software Technology Co., LTD
+* @AUTHOR Pumbaa
+* @DATA 2007-09-11
+* @VERSION 1.8
+* @REF please refer to...
+*/
+
+/******************************************
+The following is an example to use mmc and sd driver APIs
+
+******************************************/
+#ifndef _ARCH_ARM_MACH_AK88_LIB_L2_H
+#define _ARCH_ARM_MACH_AK88_LIB_L2_H
+
+//#include "anyka_types.h"
+
+#define    BUF2MEM                0
+#define    MEM2BUF                1
+#define    L2_SINGLE_BUF_SIZE     512
+#define    L2_INVALIDE_BUF_ID     0xff
+
+typedef enum {
+	ADDR_USB_BULKOUT = 0,
+	ADDR_USB_BULKIN,	// 1
+	ADDR_USB_ISO,		// 2
+	ADDR_NFC,		// 3
+	ADDR_MMC_SD,		// 4
+	ADDR_SDIO,		// 5
+	ADDR_RESERVED,		// 6
+	ADDR_SPI1_RX,		// 7
+	ADDR_SPI1_TX,		// 8    
+	ADDR_DAC,		// 9
+	ADDR_SPI2_RX,		// 10            
+	ADDR_SPI2_TX		// 11
+} DEVICE_SELECT;
+
+/**
+* @BRIEF initial l2 buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_VOID:
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_Initial(T_VOID);
+void l2_init(void);
+
+/**
+* @BRIEF allocate a buffer which doesn't used by other device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 *buf_id : the pointer of the variable which storage return buffer id
+* @RETURN T_BOOL: if allocate a buffer successful, return AK_TRUE, otherwise, return AK_FALSE
+* @NOTE: to make sure buffer allocate by this function is avalid, user must check the return value
+*/
+//T_BOOL L2_AllocBuf(T_U8 *buf_id);
+unsigned char l2_alloc_buf(unsigned char *buf_id);
+
+/**
+* @BRIEF set device information
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device to be select for change it's information
+* @PARAM T_U8 buf_id0: a buffer of device used
+* @PARAM T_U8 buf_id0: anther buffer of device used
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_SetDevInfo(DEVICE_SELECT dev_slct, T_U8 buf_id, T_U8 buf_id1);
+void l2_set_devinfo(DEVICE_SELECT dev_slct, unsigned char buf_id,
+		    unsigned char buf_id1);
+
+/**
+* @BRIEF free a or two buffer(s) which used by a device
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_FreeBuf(DEVICE_SELECT dev_slct);
+void l2_free_buf(DEVICE_SELECT dev_slct);
+
+/**
+* @BRIEF set a buffer as device buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM DEVICE_SELECT dev_slct: the device which will not use buffer
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_SlctBuf(DEVICE_SELECT dev_sel, T_U8 buf_id);
+void l2_slct_buf(DEVICE_SELECT dev_sel, unsigned char buf_id);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+//T_VOID L2_ComBufDMA(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_dma(unsigned int ram_addr, unsigned char buf_id,
+		   unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer fraction data between memory and l2 common buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+//T_VOID L2_ComBufFracDMA(T_U32 ram_addr, T_U8 buf_id, T_U8 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_fracdma(unsigned int ram_addr, unsigned char buf_id,
+		       unsigned char buf_offset, unsigned int tran_byte,
+		       unsigned char tran_dir);
+
+/**
+* @BRIEF wait DMA transfer data between memory and common buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitComBufDMAFinish(T_U8 buf_id);
+void l2_wait_combuf_dmafinish(unsigned char buf_id);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with dma and fraction dma
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 512
+*/
+//T_VOID L2_ComBufTranData(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_tran_data(unsigned int ram_addr, unsigned char buf_id,
+			 unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 common buffer with cpu
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: 1. from RAM to buffer 0. from buffer to RAM
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 512
+*/
+//T_VOID L2_ComBufTranData_CPU(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_combuf_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+			     unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size must be a or multi 64 bytes, and less than 4096 bytes
+*/
+//T_VOID L2_UartBufDMA(T_U32 ram_addr, T_U8 uart_id, T_U32 tran_byte, T_U8 tran_dir);
+void l2_uartbuf_dma(unsigned int ram_addr, unsigned char uart_id,
+		    unsigned int tran_byte, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer fraction data between memory and l2 uart buffer with dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 buf_offset: the offset between buffer start address and transfer start address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: transfer size can be 1~64 byte(s), buffer offset can be 0~7, 1 mean 64 bytes data
+*/
+//T_VOID L2_UartBufFracDMA(T_U32 ram_addr, T_U8 uart_id, T_U8 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_uartbuf_fracdma(unsigned int ram_addr, unsigned char uart_id,
+			unsigned char buf_offset, unsigned int tran_byte,
+			unsigned char tran_dir);
+
+/**
+* @BRIEF wait DMA transfer data between memory and uart buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U8 tran_dir: the transfer direction
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitUartBufDMAFinish(T_U8 uart_id, T_U8 tran_dir);
+void l2_wait_uartbuf_dmafinish(unsigned char uart_id, unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data between memory and l2 uart buffer with dma and fraction dma mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U8 buf_id: the buffer id
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: parameter tran_byte must be less than 128
+*/
+//T_VOID L2_UartBufTxData(T_U32 ram_addr, T_U8 uart_id, T_U32 tran_byte);
+void l2_uartbuf_tx_data(unsigned int ram_addr, unsigned char uart_id,
+			unsigned int tran_byte);
+
+/**
+* @BRIEF wait fraction DMA transfer data between memory and buffer finish 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @RETURN T_VOID: 
+* @NOTE: 
+*/
+//T_VOID L2_WaitFracDMAFinish(T_VOID);
+void l2_wait_frac_dmafinish(void);
+
+/**
+* @BRIEF transfer data between memory and l2 buffer with CPU mode
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 ram_addr: the memory address
+* @PARAM T_U32 buf_addr: the buffer address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @PARAM T_U8 tran_dir: transfer data from memory to buffer or from buffer to memory
+* @RETURN T_VOID: 
+* @NOTE: if buffer is common buffer, the max value of tran_byte should be 512, if buffer is uart buffer, the
+        max value of tran_byte should be 128.
+*/
+//T_VOID L2_TranDataCPU(T_U32 ram_addr, T_U8 buf_id, T_U32 buf_offset, T_U32 tran_byte, T_U8 tran_dir);
+void l2_tran_data_cpu(unsigned int ram_addr, unsigned char buf_id,
+		      unsigned int buf_offset, unsigned int tran_byte,
+		      unsigned char tran_dir);
+
+/**
+* @BRIEF transfer data from a buffer to another buffer
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U32 dst_addr: the destination buffer address
+* @PARAM T_U32 src_addr: the source buffer address
+* @PARAM T_U32 tran_byte: the size of data which will be transfered
+* @RETURN T_VOID: 
+* @NOTE: all the parameter must be multiple of 4 bytes
+*/
+//T_VOID L2_LocalDMA(T_U32 dst_addr, T_U32 src_addr, T_U32 tran_byte);
+void l2_localdma(unsigned int dst_addr, unsigned int src_addr,
+		 unsigned int tran_byte);
+
+/**
+* @BRIEF return a common buffer current flag 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_BOOL: if return flag is 1, it mean buffer is full, otherwise mean buffer is empty 
+* @NOTE: buffer id should be 0~7
+*/
+//T_U8 L2_ComBufFlag(T_U8 buf_id);
+unsigned char l2_combuf_flag(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly set a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_SetComBufFlag(T_U8 buf_id);
+void l2_set_combuf_flag(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly clear a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_ClrComBufFlag(T_U8 buf_id);
+void l2_clr_combuf_flag(unsigned char buf_id);
+
+//T_VOID L2_ChangeSetFlag(T_U8 buf_id, T_U8 set_status_flag);
+void l2_change_set_flag(unsigned char buf_id, unsigned char set_status_flag);
+
+/**
+* @BRIEF forcibly clear a common buffer flag
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 0~7
+*/
+//T_VOID L2_ClrComBufStatus(T_U8 buf_id);
+void l2_clr_combuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF forcibly clear a uart buffer status to 0
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_VOID: 
+* @NOTE: buffer id should be 8~15
+*/
+//T_VOID L2_ClrUartBufStatus(T_U8 buf_id);
+void l2_clr_uartbuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF return a common buffer current flag 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_BOOL: if return flag is 1, it mean buffer is full, oterwise mean buffer is empty 
+* @NOTE: buffer id should be 0~7
+*/
+//T_U8 L2_ComBufStatus(T_U8 buf_id);
+unsigned char l2_combuf_status(unsigned char buf_id);
+
+/**
+* @BRIEF return a uart buffer current status 
+* @AUTHOR Pumbaa
+* @DATE 2007-07-19
+* @PARAM T_U8 buf_id: the buffer id
+* @RETURN T_U8: if return status is 2, it mean buffer is full, if return 1, it mean buffer is half full, oterwise 
+                mean buffer is empty 
+* @NOTE: buffer id should be 8~15
+*/
+//T_U8 L2_UartBufStatus(T_U8 buf_id);
+unsigned char l2_uartbuf_status(unsigned char buf_id);
+
+//unsigned long AKSET_BITS(unsigned long bits_result,/* void __iomem* */void* reg);
+//unsigned long AKCLR_BITS(unsigned long bits_result,/* void __iomem* */void* reg);
+//bool AKGET_BIT(unsigned long bit_result,/* void __iomem* */void* reg);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/lib_lcd.h b/arch/arm/mach-ak98/include/mach/lib_lcd.h
new file mode 100644
index 00000000000..caf267d5706
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/lib_lcd.h
@@ -0,0 +1,155 @@
+#ifndef __ARCH_ARM_MACH_AK88_LIB_LCD_H
+#define __ARCH_ARM_MACH_AK88_LIB_LCD_H
+
+#include <mach/map.h>
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+struct tft_lcd_timing_info {
+
+	u8 bus_width;		//24
+	u32 interlace;		//PROGRESS=1<<20   //interlace(1) or progress(0)
+	u8 hvg_pol;		//0xe              //h_sync(bit2),v_sync(bit1),gate(bit0) polarity
+	u16 rgb_bit;		//0x0888           //RGB or GBR(bit12, if 1:BGR),R(bits 11:8),G(bit 7:4),B(bit 3:0) bits
+
+	u32 clock_hz;		//30,000,000(30M)  //bit clock, clock cycle,unit HZ
+
+	u32 h_sync_hz;		//15711??          //h_sync cycle,unit HZ
+	u32 v_sync_001hz;	//5885             //v_sync cycle,unit 0.01HZ
+
+	u16 h_tot_clk;		//1058             //horizontal total cycle,unit clock
+	u16 h_disp_clk;		//800              //horizontal display cycle,unit clock
+	u16 h_front_porch_clk;	//170              //horizontal front porch,unit clock
+	u16 h_pulse_width_clk;	//48               //horizontal pulse width,unit clock
+	u16 h_back_porch_clk;	//40               //horizontal back porch,unit clock
+
+	u16 v_tot_clk;		//553              //vertical   total cycle,unit h_sync
+	u16 v_disp_clk;		//480              //vertical   display cycle,unit h_sync
+	u16 v_front_porch_clk;	//40               //vertical   front porch,unit clock
+	u16 v_pulse_width_clk;	//4                //vertical   pulse width,unit clock
+	u16 v_back_porch_clk;	//29               //vertical   back porch,unit clock
+
+	char *name;
+};
+
+//lcd panel info
+struct lcd_size {
+
+	u16 w_pixel;
+	u16 h_pixel;
+	u32 pixels;
+	u8 byte_per_pixel;
+	u32 ram_size;
+	u32 freq;
+};
+
+//display ram info
+struct display_ram {
+
+	u8 *p_rgb_base1;	//physical frame base
+	u8 *p_rgb_vrt_base1;
+	u32 rgb_len1;
+	u8 *p_rgb_base2;
+	u8 *p_rgb_vrt_base2;
+	u32 rgb_len2;
+
+	u8 *p_yuv1_base;
+	u8 *p_yuv1_vrt_base;
+	u32 yuv1_len;
+	u8 *p_yuv2_base;
+	u8 *p_yuv2_vrt_base;
+	u32 yuv2_len;
+
+	u8 *p_osd_base;
+	u8 *p_osd_vrt_base;
+	u32 osd_len;
+};
+
+//need refresh picture area
+struct picture_area {
+	u32 h_offset;
+	u32 v_offset;
+	u32 h_len;
+	u32 v_len;
+	u8 *buf;
+};
+
+typedef enum {
+	LCD_IF_MPU = 0,
+	LCD_IF_RGB,
+	LCD_IF_TVOUT
+} LCD_IF_MODE;
+
+#define AK98_LCD_CMD_REG1	      (AK98_VA_DISP + 0x00)
+#define AK98_LCD_REST_SIGNAL        (AK98_VA_DISP + 0x08)	//to send a reset signal
+#define AK98_LCD_RGB_CTRL1          (AK98_VA_DISP + 0x10)	//signal of RGB interface conf
+#define AK98_LCD_RGB_CTRL2          (AK98_VA_DISP + 0x14)	//buffer address setting and to enable virtual page func of data from RGB channel
+#define AK98_LCD_RGB_VIRPAGE_SIZE   (AK98_VA_DISP + 0x18)	//virtual page size of the data input from RGB channel
+#define AK98_LCD_RGB_VIRPAGE_OFFSET (AK98_VA_DISP + 0x1C)	//virtual page offset reg
+#define AK98_LCD_OSD_ADDR           (AK98_VA_DISP + 0x20)	//osd address
+#define AK98_LCD_BKG_COLO           (AK98_VA_DISP + 0x3C)	//background color
+#define AK98_LCD_RGB_CTRL3          (AK98_VA_DISP + 0x40)	//Horizontal/Vertical sync pulse width
+#define AK98_LCD_RGB_CTRL4          (AK98_VA_DISP + 0x44)	//Horizontal back porch width and display area width
+#define AK98_LCD_RGB_CTRL5          (AK98_VA_DISP + 0x48)	//Horizontal front porch width
+#define AK98_LCD_RGB_CTRL6          (AK98_VA_DISP + 0x4C)	//Vertical back porch width
+#define AK98_LCD_RGB_CTRL7          (AK98_VA_DISP + 0x50)	//Vertical front porch width
+#define AK98_LCD_RGB_CTRL8          (AK98_VA_DISP + 0x54)	//Vertical display area
+#define AK98_LCD_RGB_CTRL9          (AK98_VA_DISP + 0x58)	//Length of VOVSYNC signal
+#define AK98_LCD_RGB_OFFSET         (AK98_VA_DISP + 0xA8)	//Offset values of the data input from RGB channel
+#define AK98_LCD_RGB_SIZE           (AK98_VA_DISP + 0xAC)	//the size of the data input from RGB channel
+#define AK98_LCD_DISP_AREA          (AK98_VA_DISP + 0xB0)	//Display area size
+#define AK98_LCD_CMD_REG2           (AK98_VA_DISP + 0xB4)	//LCD command
+#define AK98_LCD_OPER_REG           (AK98_VA_DISP + 0xB8)	//to start the reflash func
+#define AK98_LCD_STATUS_REG         (AK98_VA_DISP + 0xBC)
+#define AK98_LCD_INT_ENAB           (AK98_VA_DISP + 0xC0)	//to enable interrupt
+//status_reg bits corespondents to int_enab_reg
+//0x2001,00bc bits corespondents to 0x2001,00c0
+
+#define AK98_LCD_SOFT_CTRL          (AK98_VA_DISP + 0xC8)	//software control
+
+#define AK98_LCD_CLOCK_CONF         (AK98_VA_DISP + 0xE8)	//LCD clock configuration
+
+#define STATUS_BUF_EMPTY_ALARM		(0x1UL << 18)
+#define STATUS_ALERT_VALID		(0x1UL << 17)
+#define STATUS_TV_REFRESH_START		(0x1UL << 10)
+#define STATUS_TV_REFRESH_OK		(0x1UL << 9)
+#define STATUS_RGB_EVEN_START		(0x1UL << 8)
+#define STATUS_RGB_EVEN_DONE		(0x1UL << 7)
+#define STATUS_RGB_ODD_START		(0x1UL << 6)
+#define STATUS_RGB_ODD_DONE		(0x1UL << 5)
+#define STATUS_RGB_REFRESH_START	(0x1UL << 4)
+#define STATUS_RGB_REFRESH_OK		(0x1UL << 3)
+#define STATUS_MPU_REFRESH_OK		(0x1UL << 2)
+#define STATUS_MPU_REFRESH_START	(0x1UL << 1)
+#define STATUS_SYS_ERROR		(0x1UL << 0)
+
+void set_ahb_priority(void);
+
+//extern void rgbcontroller_set_interface(LCD_IF_MODE if_mode);
+void bsplcd_set_panel_power(int en /*1=open,0=close */ );	//pullup TFT_VGH_L and TFT_AVDD
+void baselcd_set_panel_backlight(int en /*en=0:close; en=1:open */ );
+void baselcd_reset_controller(void);	//to rest power clock reg bit19
+void baselcd_reset_panel(void);	//lcd panel reset
+
+void lcd_controller_start_clock(void);
+void lcd_controller_stop_clock(void);
+void lcd_controller_fastdma(void);
+
+void lcd_update(void);
+void lcd_dump_reg(void);
+
+void baselcd_controller_init(int en);
+void lcd_rgb_set_interface(LCD_IF_MODE if_mode);
+bool lcd_fb_init_ram(unsigned long dma_addr, unsigned long xres,
+		     unsigned long yres);
+void lcd_rgb_set_pclk(unsigned long pll1_clk, unsigned lcd_clk);
+void lcd_fb_set_timing(struct anyka_lcdfb_info *sinfo, u32 pll1_freq);
+
+void lcd_rgb_start_refresh(void);
+void lcd_rgb_stop_refresh(void);
+void lcd_interrupt_mask(unsigned bits_result, bool disable);
+
+void display_init(void);
+bool OEMIPLInit(void);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/lib_uart.h b/arch/arm/mach-ak98/include/mach/lib_uart.h
new file mode 100644
index 00000000000..84dc04a173b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/lib_uart.h
@@ -0,0 +1,243 @@
+/**
+ * @file uart.h
+ * @brief UART driver header file
+ *
+ * This file provides UART APIs: UART initialization, write data to UART, read data from
+ * UART, register callback function to handle data from UART, and interrupt handler.
+ * Copyright (C) 2005 Anyka (GuangZhou) Software Technology Co., Ltd.
+ * @author ZouMai
+ * @date 2005-07-14
+ * @version 1.0
+ */
+
+#ifndef __ARCH_ARM_MACH_AK88_LIB_UART_H__
+#define __ARCH_ARM_MACH_AK88_LIB_UART_H__
+
+#include <asm/io.h>
+#include <mach/map.h>
+
+//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#include <mach/regs-uart.h>
+
+
+//#include "common-regs.h"
+/**
+ * @brief UART port define
+ *	define port name with port number
+ */
+typedef enum {
+	uiUART0 = 0,
+#ifdef CHIP_780X
+	uiUART1,
+	uiUART2,
+#endif
+	uiUART3,
+
+	MAX_UART_NUM		/* UART number */
+} T_UART_ID;
+
+typedef enum {
+	UART_RX_buf_full = 1,
+	UART_INT_timeout,
+	UART_R_err,
+	UART_RX_ov,
+	UART_TX_end,
+	UART_Rx_th_int_sta,
+	UART_Tx_th_int_sta,
+} UART_STATU_REG04;
+
+#define MODULE_UART uiUART0
+
+//#define uart_id2register(uart_id/*0~3*/)  (unsigned int) (AK98_UART_BASE+(unsigned int)(uart_id/*0~3*/)*0x1000)  //0x20026000
+
+static inline char ak880x_uart_get_tx_rdy(unsigned char uart_id)
+{
+	unsigned int status;
+	//status=__raw_readl(uart_id2register(uart_id)+0x04);
+
+	status = __raw_readl(AK98_UART_CFG_REG2(uart_id));
+
+	if (status & (1 << 19))
+		return 1;
+	else
+		return 0;
+}
+
+static inline char ak880x_uart_get_rx_rdy(unsigned char uart_id)
+{
+	unsigned int status;
+	//status=__raw_readl(uart_id2register(uart_id)+0x04);
+	status = __raw_readl(AK98_UART_CFG_REG2(uart_id));
+
+	if (status & (1 << 2))
+		return 1;
+	else if (status & (1 << 1))
+		return 1;
+	else
+		return 0;
+
+	//0x20026004
+	//bit[2]:timeout:1=the receiving timeout occurs.
+	//bit[1]:RX_buf_full:1=the receive buffer is full.
+}
+
+void uart_clock_ctl(unsigned char uart_id, unsigned char enable);
+void uart_pin_ctl(unsigned char uart_id);
+
+unsigned int uart_get_int_status(unsigned char uart_id, unsigned test_status);
+
+void uart_clear_tx_status(unsigned char uart_id);
+void uart_clear_rx_status(unsigned char uart_id);
+unsigned int uart_clear_rx_timeout(unsigned char uart_id);	//return timeout_count
+void uart_clear_rx_buffull(unsigned char uart_id);
+void uart_clear_rx_err(unsigned char uart_id);
+
+void uart_clear_rx_th(unsigned char uart_id);
+void uart_reen_rx_th(unsigned char uart_id);
+
+unsigned char uart_wait_tx_finish(unsigned char uart_id);
+unsigned char uart_get_tx_empty(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+unsigned char uart_wait_rx_timeout(unsigned char uart_id);
+unsigned char uart_get_rx_timeout(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+unsigned char uart_get_rx_buffull(unsigned char uart_id);
+/*yes:return 1;  no :return 0;*/
+
+unsigned int uart_read_timeout(unsigned char uart_id, unsigned char *chr);
+/*when timeout is occur,read all the rxfifo data,return real read number*/
+
+unsigned int uart_read_buffull(unsigned char uart_id, unsigned char *chr);
+/*when RX_buf_full is occur,read all the rxfifo data,return real read number*/
+
+/**
+ * @brief UART callback define
+ *	define UART callback type
+ */
+//typedef T_VOID (*T_fUART_CALLBACK)(T_VOID);
+typedef void (*t_fuart_callback) (void);
+
+/**
+ * @brief Initialize UART
+ *
+ * Initialize UART base on UART ID, baudrate and system clock. If user want to change
+ * baudrate or system clock is changed, user should call this function to initialize
+ * UART again.
+ * Function uart_init() must be called before call any other UART functions
+ * @author ZouMai
+ * @date 2005-07-13
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] unsigned int baud_rate: Baud rate, use UART_BAUD_9600, UART_BAUD_19200 ...
+ * @return unsigned char: Init UART OK or not
+ * @retval AK_TRUE: Successfully initialized UART. AK_FALSE: Initializing UART failed.
+ */
+
+unsigned char uart_init(unsigned char uart_id, unsigned int baud_rate,
+			unsigned int sys_clk);
+
+//unsigned char uart_enable_int(unsigned char uart_id/*0~3*/);
+
+extern void uart_close_interrupt(unsigned char uart_id /*0~3 */ );
+extern void uart_open_interrupt(unsigned char uart_id /*0~3 */ );
+
+void uart_free(unsigned char uart_id);
+
+/**
+ * @brief Write one character to UART base on UART ID
+ *
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] unsigned char chr: The character which will be written to UART
+ * @return unsigned char: Write character OK or not
+ * @retval AK_TRUE: Successfully written character to UART. AK_FALSE: Writing character to UART failed.
+ */
+
+unsigned char uart_write_chr(unsigned char uart_id, unsigned char chr);
+
+/**
+ * @brief Write string to UART base on UART ID
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param unsigned char uart_id: UART ID
+ * @param unsigned char *str: The string which will be written to UART
+ * @return unsigned int: Length of the data which have been written to UART
+ * @retval
+ */
+
+unsigned int uart_write_str(unsigned char uart_id, unsigned char *str);
+
+unsigned char uart_write_buf(unsigned char uart_id /*0~3 */ ,
+			     unsigned char *chr,
+			     unsigned int byte_nbr
+			     /*<60,last 4 bytes(0x3c/0x7c) write 0 */ );
+
+/**
+ * @brief Write string data to UART
+ *
+ * Write data to UART base on UART ID and data length
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-16
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] const unsigned char* data: Constant data to be written to UART, this data needn't be end with '\0'
+ * @param[in] unsigned int data_len: Data length
+ * @return unsigned int
+ * @retval Length of the data which have been written to UART
+ */
+unsigned int uart_write(unsigned char uart_id, const unsigned char *data,
+			unsigned int data_len);
+
+unsigned int uart_write_dma(unsigned char uart_id, const unsigned char *chr,
+			    unsigned int byte_nbr);
+
+/**
+ * @brief Read a character from UART
+ *
+ * This function will not return until get a character from UART
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[out] unsigned char *chr: character for return
+ * @return unsigned char: Got character or not
+ * @retval return AK_TRUE
+ */
+unsigned char uart_read_chr(unsigned char uart_id, unsigned char *chr);
+
+/**
+ * @brief Register a callback function to process UART received data.
+ *
+ * This function words only in the UART interrupt mode.
+ * Caution: The macro definition "__ENABLE_UARTxx_INT__" must be defined. 
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: UART ID
+ * @param[in] t_fuart_callback callback_func: Callback function
+ * @return void
+ * @retval
+ */
+
+void uart_set_callback(unsigned char uart_id, t_fuart_callback callback_func);
+
+/**
+ * @brief Register a callback function to process UART received data.
+ *
+ * This function words only in the UART interrupt mode.
+ * Caution: The macro definition "__ENABLE_UARTxx_INT__" must be defined. 
+ * Function uart_init() must be called before call this function
+ * @author ZouMai
+ * @date 2004-09-17
+ * @param[in] unsigned char uart_id: uart_id
+ * @param[in] t_fuart_callback callback_func: Callback function
+ * @return void
+ * @retval
+ */
+unsigned char uart_read_chr_asy(unsigned char uart_id, unsigned char *chr);
+
+/*@}*/
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/mac.h b/arch/arm/mach-ak98/include/mach/mac.h
new file mode 100644
index 00000000000..a36a00d9df2
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/mac.h
@@ -0,0 +1,9 @@
+/* platfrom data for platfrom device structure's platfrom_data field */
+
+#define MAC_ADDR_LEN 6
+#define MAC_ADDR_STRING_LEN (MAC_ADDR_LEN * 3 - 1)
+
+struct ak98_mac_data {
+	unsigned int	flags;
+	unsigned char	dev_addr[MAC_ADDR_LEN];
+};
diff --git a/arch/arm/mach-ak98/include/mach/map.h b/arch/arm/mach-ak98/include/mach/map.h
new file mode 100644
index 00000000000..8dfffb778b6
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/map.h
@@ -0,0 +1,154 @@
+/* arch/arm/arch-ak98/include/mach/map.h
+ *
+ * AK98 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+#ifndef __ASSEMBLY__
+#define AK98_ADDR(x)		((void __iomem *)0xF0000000 + (x))
+#else
+#define AK98_ADDR(x)		(0xF0000000 + (x))
+#endif
+
+#define AK98_VA_OCROM		AK98_ADDR(0x00000000)
+#define AK98_PA_OCROM		0x00000000
+#define AK98_SZ_OCROM		3 * SZ_16K	/* 48KB */
+
+#define AK98_VA_SYSCTRL		AK98_ADDR(0x00100000)
+#define AK98_PA_SYSCTRL		(0x08000000)
+#define AK98_SZ_SYSCTRL		SZ_64K		/* 64KB */
+
+/* some sub system control register */
+#define AK98_VA_SUBCTRL		AK98_ADDR(0x00200000)
+#define AK98_PA_SUBCTRL		(0x20000000)
+#define AK98_SZ_SUBCTRL		SZ_1M 	 	/* 1MB */
+
+#define AK98_VA_H264MEM		(AK98_VA_SUBCTRL + 0x0)
+#define AK98_PA_H264MEM		(AK98_PA_SUBCTRL + 0x0)
+#define AK98_SZ_H264MEM		2 * SZ_16K 	/* 32KB */
+
+#define AK98_VA_CAMER		(AK98_VA_SUBCTRL + 0xC000)
+#define AK98_PA_CAMER		(AK98_PA_SUBCTRL + 0xC000)
+
+#define AK98_VA_DISP		(AK98_VA_SUBCTRL + 0xD000)
+#define AK98_PA_DISP		(AK98_PA_SUBCTRL + 0xD000)
+
+#define AK98_VA_REGRAM		(AK98_VA_SUBCTRL + 0xE000)
+#define AK98_PA_REGRAM		(AK98_PA_SUBCTRL + 0xE000)
+
+#define AK98_VA_L2CACH		(AK98_VA_SUBCTRL + 0xF000)
+#define AK98_PA_L2CACH		(AK98_PA_SUBCTRL + 0xF000)
+
+/* reference base addr for register control */
+#define AK98_VA_DEV		(AK98_VA_SUBCTRL + 0x20000)
+#define AK98_PA_DEV		(AK98_PA_SUBCTRL + 0x20000)
+
+#define AK98_VA_MMC			(AK98_VA_DEV + 0x0000)
+#define AK98_PA_MMC			(AK98_PA_DEV + 0x0000)
+
+#define AK98_VA_SDIO		(AK98_VA_DEV + 0x1000)
+#define AK98_PA_SDIO		(AK98_PA_DEV + 0x1000)
+
+#define AK98_VA_2DACC		(AK98_VA_DEV + 0x2000)
+#define AK98_PA_2DACC		(AK98_PA_DEV + 0x2000)
+
+#define AK98_VA_I2C			(AK98_VA_DEV + 0x3000)
+#define AK98_PA_I2C			(AK98_PA_DEV + 0x3000)
+
+#define AK98_VA_SPI1		(AK98_VA_DEV + 0x4000)
+#define AK98_PA_SPI1		(AK98_PA_DEV + 0x4000)
+
+#define AK98_VA_SPI2		(AK98_VA_DEV + 0x5000)
+#define AK98_PA_SPI2		(AK98_PA_DEV + 0x5000)
+
+#define AK98_VA_UART		(AK98_VA_DEV + 0x6000)
+#define AK98_PA_UART		(AK98_PA_DEV + 0x6000)
+
+#define AK98_VA_NFCTRL		(AK98_VA_SUBCTRL + 0x2A000)
+#define AK98_PA_NFCTRL		(AK98_PA_SUBCTRL + 0x2A000)
+
+#define AK98_VA_ECCCTRL	    (AK98_VA_SUBCTRL + 0x2B000)
+#define AK98_PA_ECCCTRL	    (AK98_PA_SUBCTRL + 0x2B000)
+
+
+#define AK98_VA_ECC			(AK98_VA_DEV + 0xB000)
+#define AK98_PA_ECC			(AK98_PA_DEV + 0xB000)
+
+#define AK98_VA_L2CTRL		(AK98_VA_DEV + 0xC000)
+#define AK98_PA_L2CTRL		(AK98_PA_DEV + 0xC000)
+
+#define AK98_VA_ADC			(AK98_VA_DEV + 0xD000)
+#define AK98_PA_ADC			(AK98_PA_DEV + 0xD000)
+
+#define AK98_VA_DAC			(AK98_VA_DEV + 0xE000)
+#define AK98_PA_DAC			(AK98_PA_DEV + 0xE000)
+
+#define AK98_VA_ROTCTRL		(AK98_VA_DEV + 0xF000)
+#define AK98_PA_ROTCTRL		(AK98_PA_DEV + 0xF000)
+
+#define AK98_VA_PCM			(AK98_VA_SUBCTRL + 0x30000)
+#define AK98_PA_PCM			(AK98_PA_SUBCTRL + 0x30000)
+
+#define AK98_VA_IMAGE		(AK98_VA_SUBCTRL + 0x40000)
+#define AK98_PA_IMAGE		(AK98_PA_SUBCTRL + 0x40000)
+
+#define AK98_VA_MOTCTRL		(AK98_VA_SUBCTRL + 0x41000)
+#define AK98_PA_MOTCTRL		(AK98_PA_SUBCTRL + 0x41000)
+
+#define AK98_VA_RMVB		(AK98_VA_SUBCTRL + 0x70000)
+#define AK98_PA_RMVB		(AK98_PA_SUBCTRL + 0x70000)
+
+#define AK98_VA_MPEG2		(AK98_VA_SUBCTRL + 0x71000)
+#define AK98_PA_MPEG2		(AK98_PA_SUBCTRL + 0x71000)
+
+#define AK98_VA_RHUFF		(AK98_VA_SUBCTRL + 0x72000)
+#define AK98_PA_RHUFF		(AK98_PA_SUBCTRL + 0x72000)
+
+#define AK98_VA_L2MEM		AK98_ADDR(0x00300000)
+#define AK98_PA_L2MEM		(0x48000000)
+#define AK98_SZ_L2MEM		SZ_1M /* 2 * 64KB */
+
+#define AK98_VA_MAC			AK98_ADDR(0x00400000)
+#define AK98_PA_MAC			(0x60000000)
+#define AK98_SZ_MAC			2 * SZ_64K  /* 2 * 64KB */
+
+#define AK98_VA_USB			AK98_ADDR(0x00500000)
+#define AK98_PA_USB			(0x70000000)
+#define AK98_SZ_USB			SZ_1M
+
+/*
+ * This is used for the CPU specific mappings that may be needed, so that
+ * they do not need to directly used AK98_ADDR() and thus make it easier to
+ * modify the space for mapping.
+ */
+#define	write_ramb(v, p)		(*(volatile unsigned char *)(p) = (v))
+#define write_ramw(v, p)		(*(volatile unsigned short *)(p) = (v))
+#define write_raml(v, p)		(*(volatile unsigned long *)(p) = (v))
+
+#define read_ramb(p)			(*(volatile unsigned char *)(p))
+#define read_ramw(p)			(*(volatile unsigned short *)(p))
+#define read_raml(p)			(*(volatile unsigned long *)(p))
+
+#define write_buf(v, p)			(*(volatile unsigned long *)(p) = (v))
+#define read_buf(p)				(*(volatile unsigned long *)(p))
+
+/*
+ * This is used mode:
+ * #define rTIME1_CON      REG_VA_VAL(AK98_VA_SYS, 0x0018)
+ * #define rTIME2_CON      REG_VA_VAL(AK98_VA_SYS, 0x001C)
+ */
+#define REG_VA_VAL(base_addr, offset)	(*(volatile unsigned long *)((base_addr) + (offset)))
+#define REG_VA_ADDR(base_addr, offset)	((base_addr) + (offset))
+
+#define REG_PA_VAL(base_addr, offset)	(*(volatile unsigned long *)((base_addr) + (offset)))
+#define REG_PA_ADDR(base_addr, offset)	((base_addr) + (offset))
+
+
+#endif  /* __ASM_ARCH_MAP_H */
+
diff --git a/arch/arm/mach-ak98/include/mach/memory.h b/arch/arm/mach-ak98/include/mach/memory.h
new file mode 100644
index 00000000000..1f4424a7774
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/memory.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-ak98/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#ifdef CONFIG_VIDEO_RESERVED_MEM_SIZE
+#define PHYS_OFFSET		(CONFIG_RAM_BASE + CONFIG_VIDEO_RESERVED_MEM_SIZE)
+#else
+#define PHYS_OFFSET		UL(0x80000000)
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#define __virt_to_bus(x)	(x - PAGE_OFFSET + PHYS_OFFSET)
+#define __bus_to_virt(x)	(x - PHYS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/nand.h b/arch/arm/mach-ak98/include/mach/nand.h
new file mode 100644
index 00000000000..a079c9845ef
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/nand.h
@@ -0,0 +1,37 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* struct ak98_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips	 = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name		 = name of set (optional)
+ * nr_map	 = map for low-layer logical to physical chip numbers (option)
+ * partitions	 = mtd partition list
+*/
+
+struct ak98_nand_set {
+	int nr_chips;
+	int nr_partitions;
+	char *name;
+	int *nr_map;
+	struct mtd_partition *partitions;
+
+	/* timing information for controller */
+	unsigned int cmd_len;
+	unsigned int data_len;
+	unsigned char col_cycle;
+	unsigned char row_cycle;
+};
+
+struct ak98_platform_nand {
+	int nr_sets;
+	struct ak98_nand_set *sets;
+
+	void (*select_chip) (struct ak98_nand_set *, int chip);
+};
diff --git a/arch/arm/mach-ak98/include/mach/pm.h b/arch/arm/mach-ak98/include/mach/pm.h
new file mode 100644
index 00000000000..c7c6d51081f
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/pm.h
@@ -0,0 +1,24 @@
+#ifndef __PM_H
+#define	__PM_H
+
+#include <mach/l2_exebuf.h>
+
+
+/* ak98_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+extern int __init ak98_pm_init(void);
+#else
+static inline int ak98_pm_init(void)
+{
+	return 0;
+}
+#endif
+
+#endif /* __PM_H */
+
+
diff --git a/arch/arm/mach-ak98/include/mach/pwm.h b/arch/arm/mach-ak98/include/mach/pwm.h
new file mode 100644
index 00000000000..a5dfb658bdc
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/pwm.h
@@ -0,0 +1,43 @@
+/*

+ */

+#ifndef _AK98_PWM_H_

+#define _AK98_PWM_H_ __FILE__

+

+#define AK98_PWM1_CTRL	(AK98_VA_SYSCTRL+0x2C)

+#define AK98_PWM2_CTRL	(AK98_VA_SYSCTRL+0x30)

+#define AK98_PWM3_CTRL	(AK98_VA_SYSCTRL+0xB4)

+#define AK98_PWM4_CTRL	(AK98_VA_SYSCTRL+0xB8)

+

+

+struct ak98_pwm {

+	unsigned int id;

+	unsigned int gpio;

+	unsigned char __iomem *pwm_ctrl;

+	unsigned short high;

+	unsigned short low;

+	unsigned short pwm_clk;

+};

+

+struct ak98_platform_pwm_bl_data {

+	int pwm_id;

+	unsigned int max_brightness;

+	unsigned int dft_brightness;

+	unsigned int pwm_clk;

+	int (*init)(struct ak98_pwm *dev);

+	int (*notify)(int brightness);

+	void (*exit)(struct ak98_pwm *dev);

+};

+

+

+extern struct ak98_pwm ak98_pwm1;

+extern struct ak98_pwm ak98_pwm2;

+extern struct ak98_pwm ak98_pwm3;

+extern struct ak98_pwm ak98_pwm4;

+

+int ak98_pwm_enable(struct ak98_pwm *pwm);

+int ak98_pwm_config(struct ak98_pwm *pwm, unsigned short high, unsigned short low);

+void ak98_pwm_disable(struct ak98_pwm *pwm);

+struct ak98_pwm *ak98_pwm_request(int pwm_id);

+

+

+#endif				/* _AK98_PWM_H_ */

diff --git a/arch/arm/mach-ak98/include/mach/reg.h b/arch/arm/mach-ak98/include/mach/reg.h
new file mode 100644
index 00000000000..1fdd28afb57
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/reg.h
@@ -0,0 +1,18 @@
+/*
+ * reg.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _REG_H_
+#define _REG_H_
+
+#define SOFT_RST_CLKCON1	(0x0800000C)
+
+void ak98_sys_ctrl_reg_set(unsigned long reg_phy_addr, unsigned long reg_mask, unsigned long reg_val);
+
+#endif /* _REG_H_ */
+
diff --git a/arch/arm/mach-ak98/include/mach/regs-adc.h b/arch/arm/mach-ak98/include/mach/regs-adc.h
new file mode 100644
index 00000000000..91391659740
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-adc.h
@@ -0,0 +1,44 @@
+#ifndef	_AK98_ADC_H_
+#define _AK98_ADC_H_ __FILE__
+
+#define AK98_ANALOG_CTRL1	(AK98_VA_SYSCTRL+0x5C)
+#define AD5_sel1		(1 << 29)
+#define BAT_ON			(1 << 28)
+#define RM_DIR			(1 << 27)
+#define PD_TS			(1 << 26)
+
+#define AK98_ADC1_CTRL	(AK98_VA_SYSCTRL+0x60)
+
+#define AK98_WTPF_CTRL				(AK98_VA_SYSCTRL+0x128)
+#define AK98_PENDOWN_CTRL			(AK98_VA_SYSCTRL+0x12C)
+#define AK98_PENDOWN_CTRL_REG_WRITE (AK98_VA_SYSCTRL+0x134)
+
+#define AK98_ANALOG_CTRL2	(AK98_VA_SYSCTRL+0x64)
+#define ADC1_en			(1 << 8)
+#define bat_en			(1 << 9)
+#define TS_en			(1 << 10)
+#define AD5_sel			(1 << 11)
+#define TS_threshold08		(0x08 << 17)
+#define TS_threshold1023	(0x3ff << 17)
+#define TS_ctrl255		(0xff << 0)
+#define TS_ctrl05		(0x05 << 0)
+
+#define AK98_ADC1_STATUS	(AK98_VA_SYSCTRL+0x70)
+#define YN_int			(1 << 23)
+#define YP_int			(1 << 22)
+#define XN_int			(1 << 21)
+#define XP_int			(1 << 20)
+
+#define AK98_CLK_DIV2		(AK98_VA_SYSCTRL+0x08)
+#define ADC1_pd			(1 << 29)
+#define ADC1_rst		(1 << 22)
+#define ADC1_CLK_en		(1 << 3)
+#define ADC1_DIV0		(0 << 0)	/* ADC CLOCK=12M/(ADC1_DIV+1) */
+#define ADC1_DIV1		(1 << 0)
+#define ADC1_DIV2		(2 << 0)
+#define ADC1_DIV3		(3 << 0)
+
+#define AK98_X_COORDINATE	(AK98_VA_SYSCTRL+0x68)
+#define AK98_Y_COORDINATE	(AK98_VA_SYSCTRL+0x6C)
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/regs-comm.h b/arch/arm/mach-ak98/include/mach/regs-comm.h
new file mode 100644
index 00000000000..7d4369648b0
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-comm.h
@@ -0,0 +1,121 @@
+
+/*
+ * arch/arm/mach-ak98/include/mach/ak98_comm.h
+ */
+#ifndef __REGS_COMM_H_
+#define __REGS_COMM_H_
+
+#include <mach/map.h>
+
+/************************ CLOCK/POWER*****************************/
+#define rCHIP_ID			REG_VA_VAL(AK98_VA_SYSCTRL, 0x0000)
+
+#define rCLK_DIV1           REG_VA_VAL(AK98_VA_SYSCTRL, 0x0004)
+#define rCLK_DIV2           REG_VA_VAL(AK98_VA_SYSCTRL, 0x0008)
+#define rCLK_CON1        	REG_VA_VAL(AK98_VA_SYSCTRL, 0x000C)
+#define rCLK_CON2        	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0010)
+
+#define rMULFUN_CON2       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0014)
+#define rMULFUN_CON1       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0058)
+
+#define rSHAREPIN_CON1   	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0078)
+#define rSHAREPIN_CON2   	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0074)
+
+#define rPPU_PPD1			REG_VA_VAL(AK98_VA_SYSCTRL, 0x009C)
+#define rPPU_PPD2 			REG_VA_VAL(AK98_VA_SYSCTRL, 0x00A0)
+#define rPPU_PPD3			REG_VA_VAL(AK98_VA_SYSCTRL, 0x00A4)
+#define rPPU_PPD4			REG_VA_VAL(AK98_VA_SYSCTRL, 0x00A8)
+#define rMCGPIO_PPD			REG_VA_VAL(AK98_VA_SYSCTRL, 0x0120)
+
+#define rIO_CON1           	REG_VA_VAL(AK98_VA_SYSCTRL, 0x00D4)
+#define rIO_CON2           	REG_VA_VAL(AK98_VA_SYSCTRL, 0x00D8)
+
+/*************************** CRC *****************************/
+#define rCRC_CON 	        REG_VA_VAL(AK98_VA_L2CTRL, 0xA4)
+#define rCRC_POLYLEN   		REG_VA_VAL(AK98_VA_SYSCTRL, 0x00AC)
+#define rCRC_COEFCON   		REG_VA_VAL(AK98_VA_SYSCTRL, 0x00B0)
+#define rCRC_RESULT    		REG_VA_VAL(AK98_VA_SYSCTRL, 0x00D0)
+
+/************************** IRQ ******************************/
+#define rIRQ_MASK           REG_VA_VAL(AK98_VA_SYSCTRL, 0x0034)
+#define rFIQ_MASK           REG_VA_VAL(AK98_VA_SYSCTRL, 0x0038)
+#define rINT_STAT           REG_VA_VAL(AK98_VA_SYSCTRL, 0x00CC)
+#define rINT_STATEN	        REG_VA_VAL(AK98_VA_SYSCTRL, 0x004C)
+
+/************************** RTC ******************************/
+#define rRTCUSB_CON         REG_VA_VAL(AK98_VA_SYSCTRL, 0x0050)
+#define rRTC_BOOTMOD        REG_VA_VAL(AK98_VA_SYSCTRL, 0x0054)
+#define rWKUPGPIO_POL       REG_VA_VAL(AK98_VA_SYSCTRL, 0x003C)
+#define rWKUPGPIO_CLR		REG_VA_VAL(AK98_VA_SYSCTRL, 0x0040)
+#define rWKUPGPIO_EN        REG_VA_VAL(AK98_VA_SYSCTRL, 0x0044)
+#define rWKUPGPIO_STAT      REG_VA_VAL(AK98_VA_SYSCTRL, 0x0048)
+
+/*********************** PWM **********************************/
+#define rPWM1_CON       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x002C)
+#define rPWM2_CON       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0030)
+#define rPWM3_CON       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x00B4)
+#define rPWM4_CON       	REG_VA_VAL(AK98_VA_SYSCTRL, 0x00B8)
+
+/********************* TIMER **********************************/
+#define rTIMER1_CON      	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0018)
+#define rTIMER2_CON      	REG_VA_VAL(AK98_VA_SYSCTRL, 0x001C)
+#define rTIMER3_CON      	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0020)
+#define rTIMER4_CON      	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0024)
+#define rTIMER5_CON      	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0028)
+
+#define rTIMER1_RDBACK    	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0100)
+#define rTIMER2_RDBACK    	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0104)
+#define rTIMER3_RDBACK    	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0108)
+#define rTIMER4_RDBACK    	REG_VA_VAL(AK98_VA_SYSCTRL, 0x010C)
+#define rTIMER5_RDBACK    	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0110)
+
+/******************** ANALOG *********************************/
+#define rADC1_CON			REG_VA_VAL(AK98_VA_SYSCTRL, 0x0060)
+#define rADC1_STAT          REG_VA_VAL(AK98_VA_SYSCTRL, 0x0070)
+#define rADC2_CON           REG_VA_VAL(AK98_VA_ADC, 0x00)
+#define rADC2_DATA          REG_VA_VAL(AK98_VA_ADC, 0x04)
+
+#define rTSWTIME_PENDFILT	REG_VA_VAL(AK98_VA_SYSCTRL, 0x0128)
+#define rPENDFILT_CON		REG_VA_VAL(AK98_VA_SYSCTRL, 0x012C)
+#define rTS_XVAL			REG_VA_VAL(AK98_VA_SYSCTRL, 0x0068)
+#define rTS_YVAL			REG_VA_VAL(AK98_VA_SYSCTRL, 0x006C)
+
+#define rANALOG_CON1        REG_VA_VAL(AK98_VA_SYSCTRL, 0x0130)
+#define rANALOG_CON2        REG_VA_VAL(AK98_VA_SYSCTRL, 0x0134)
+#define rANALOG_CON3        REG_VA_VAL(AK98_VA_SYSCTRL, 0x005C)
+#define rANALOG_CON4        REG_VA_VAL(AK98_VA_SYSCTRL, 0x0064)
+
+#define rDAC_CON			REG_VA_VAL(AK98_VA_DAC, 0x00)
+#define rDAC_CPUDATA		REG_VA_VAL(AK98_VA_DAC, 0x08)
+
+/****************** RAM CONTROLER ********************************/
+#define rRAMIO_CON 	       	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE078)
+#define rMEM_CON1          	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE000)
+#define rMEM_CON2          	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE004)
+#define rMEM_CON3          	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE008)
+#define rMEM_CON4          	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE00C)
+#define rCPU_CMD            REG_VA_VAL(AK98_VA_SUBCTRL, 0xE010)
+#define rAHBTIME_PICE_CON   REG_VA_VAL(AK98_VA_SUBCTRL, 0xE014)
+#define rAHB_PRI1   	   	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE018)
+#define rAHB_PRI2			REG_VA_VAL(AK98_VA_SUBCTRL, 0xE01C)
+#define rDLL_CON           	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE020)
+#define rRTIME_CAL_CON     	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE024)
+
+#define rDELAY_LCON1   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE028)
+#define rDELAY_LCON2   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE02C)
+#define rDELAY_LCON3   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE030)
+#define rDELAY_LCON4   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE034)
+#define rDELAY_LCON5   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE038)
+#define rDELAY_LCON6   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE03A)
+#define rDELAY_LCON7   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE040)
+#define rDELAY_LCON8   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE044)
+#define rDELAY_LCON9   		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE048)
+#define rDELAY_LCON10  		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE04C)
+#define rDELAY_LCON11  		REG_VA_VAL(AK98_VA_SUBCTRL, 0xE050)
+#define rDELAY_EN_LCON1    	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE054)
+#define rDELAY_EN_LCON2    	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE058)
+#define rDLLDCC_CON       	REG_VA_VAL(AK98_VA_SUBCTRL, 0xE05C)
+
+
+#endif  /* __REG_COMM_H_ */
+
diff --git a/arch/arm/mach-ak98/include/mach/regs-gpio.h b/arch/arm/mach-ak98/include/mach/regs-gpio.h
new file mode 100644
index 00000000000..51e3d5c58ad
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-gpio.h
@@ -0,0 +1,90 @@
+/*
+ * arch/arm/mach-ak98/include/mach/ak98_gpio.h
+ */
+#ifndef __REGS_GPIO_H_
+#define __REGS_GPIO_H_
+
+#include <mach/map.h>
+
+#define rGPIO_DIR1      REG_VA_VAL(AK98_VA_SYSCTRL, 0x007C)
+#define rGPIO_DIR2      REG_VA_VAL(AK98_VA_SYSCTRL, 0x0084)
+#define rGPIO_DIR3      REG_VA_VAL(AK98_VA_SYSCTRL, 0x008C)
+#define rGPIO_DIR4      REG_VA_VAL(AK98_VA_SYSCTRL, 0x0094)
+#define rGPIO_DIR5      REG_VA_VAL(AK98_VA_SYSCTRL, 0x011C)
+
+#define rGPIO_OUT1   REG_VA_VAL(AK98_VA_SYSCTRL, 0x0080)
+#define rGPIO_OUT2   REG_VA_VAL(AK98_VA_SYSCTRL, 0x0088)
+#define rGPIO_OUT3   REG_VA_VAL(AK98_VA_SYSCTRL, 0x0090)
+#define rGPIO_OUT4   REG_VA_VAL(AK98_VA_SYSCTRL, 0x0098)
+#define rGPIO_OUT5   REG_VA_VAL(AK98_VA_SYSCTRL, 0x0118)
+
+#define rGPIO_IN1    REG_VA_VAL(AK98_VA_SYSCTRL, 0x00BC)
+#define rGPIO_IN2    REG_VA_VAL(AK98_VA_SYSCTRL, 0x00C0)
+#define rGPIO_IN3    REG_VA_VAL(AK98_VA_SYSCTRL, 0x00C4)
+#define rGPIO_IN4    REG_VA_VAL(AK98_VA_SYSCTRL, 0x00C8)
+#define rGPIO_IN5    REG_VA_VAL(AK98_VA_SYSCTRL, 0x0124)
+
+#define rGPIO_INT1   REG_VA_VAL(AK98_VA_SYSCTRL, 0x00E0)
+#define rGPIO_INT2   REG_VA_VAL(AK98_VA_SYSCTRL, 0x00E4)
+#define rGPIO_INT3   REG_VA_VAL(AK98_VA_SYSCTRL, 0x00E8)
+#define rGPIO_INT4   REG_VA_VAL(AK98_VA_SYSCTRL, 0x00EC)
+
+#define rGPIO_INTPOL1  REG_VA_VAL(AK98_VA_SYSCTRL, 0x00F0)
+#define rGPIO_INTPOL2  REG_VA_VAL(AK98_VA_SYSCTRL, 0x00F4)
+#define rGPIO_INTPOL3  REG_VA_VAL(AK98_VA_SYSCTRL, 0x00F8)
+#define rGPIO_INTPOL4  REG_VA_VAL(AK98_VA_SYSCTRL, 0x00FC)
+
+/*
+ * The other mode defined
+ *
+ * #define AK98_GPIO_DIR(n)			(AK98_VA_SYSCTRL + 0x007C + (n) * 8) //n = 0 ~ 3
+ * #define AK98_GPIO_OUT(n)			(AK98_VA_SYSCTRL + 0x0080 + (n) * 8) //n = 0 ~ 3
+ * #define AK98_GPIO_IN(n)  		(AK98_VA_SYSCTRL + 0x00BC + (n) * 4) //n = 0 ~ 3
+ * #define AK98_GPIO_INT(n)  		(AK98_VA_SYSCTRL + 0x00E0 + (n) * 4) //n = 0 ~ 3
+ * #define AK98_GPIO_INT_POLA(n)  	(AK98_VA_SYSCTRL + 0x00F0 + (n) * 4) //n = 0 ~ 3
+ *
+ */
+
+//#define rGPIO_DIR1      REG_VA_VAL(AK98_GPIO_DIR(0), 0x00)
+
+/************************** GPIO ***********************************/
+#define AK98_GPIO_DIR(n)       (AK98_VA_SYSCTRL+0x007C+n*8) //n=0~3
+#define AK98_PA_GPIO_DIR(n)       (AK98_PA_SYS+0x007C+n*8)  //n=0~3
+
+//0x7C for GPIO[0] ~ GPIO[31]
+//0x84 for GPIO[32] ~ GPIO[63]
+//0x8C for GPIO[64] ~ GPIO[79], bit20:DGPIO[19],bit29:DGPIO[28]
+//0x94 for bit[9:6]: DGPIO[0]~ DGPIO[3]
+
+#define AK98_GPIO_OUT(n)         (AK98_VA_SYSCTRL+0x0080+n*8)   //n=0~3
+#define AK98_PA_GPIO_OUT(n)         (AK98_PA_SYS+0x0080+n*8)    //n=0~3
+
+//0x80
+//0x88
+//0x90
+//0x98
+
+#define AK98_GPIO_IN(n)          (AK98_VA_SYSCTRL+0x00BC+n*4)   //n=0~3
+#define AK98_PA_GPIO_IN(n)          (AK98_PA_SYS+0x00BC+n*4)    //n=0~3
+
+//0xBC
+//0xC0
+//0xC4
+//0xC8
+
+#define AK98_GPIO_INT_EN1         (AK98_VA_SYSCTRL+0x00E0+n*4)  //n=0~3
+#define AK98_PA_GPIO_INT_EN1         (AK98_VA_SYSCTRL+0x00E0+n*4)   //n=0~3
+//0xE0
+//0xE4
+//0xE8
+//0xEC
+
+#define AK98_GPIO_INT_POLA1       (AK98_VA_SYSCTRL+0x00F0+n*4)  //n=0~3
+#define AK98_PA_GPIO_INT_POLA1       (AK98_VA_SYSCTRL+0x00F0+n*4)   //n=0~3
+//0xF0
+//0xF4
+//0xF8
+//0xFC
+
+#endif /* __REGS_GPIO_H_ */
+
diff --git a/arch/arm/mach-ak98/include/mach/regs-l2.h b/arch/arm/mach-ak98/include/mach/regs-l2.h
new file mode 100644
index 00000000000..1ba0570dbae
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-l2.h
@@ -0,0 +1,99 @@
+
+/*
+ * arch/arm/mach-ak98/include/mach/l2.h
+ */
+#ifndef __REGS_L2_H_
+#define __REGS_L2_H_
+
+#include <mach/map.h>
+
+/*************************** L2 CACHE ******************************/
+#define rL2CACH_CON         REG_VA_VAL(AK98_VA_SUBCTRL, 0xF000)
+#define rSTARTADDR_SEC0     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF010)
+#define rSTARTADDR_SEC1     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF020)
+#define rSTARTADDR_SEC2     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF030)
+#define rSTARTADDR_SEC3     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF040)
+#define rSTARTADDR_SEC4     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF050)
+#define rSTARTADDR_SEC5     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF060)
+#define rSTARTADDR_SEC6     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF070)
+#define rSTARTADDR_SEC7     REG_VA_VAL(AK98_VA_SUBCTRL, 0xF080)
+
+#define rENDADDR_SEC0       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF014)
+#define rENDADDR_SEC1       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF024)
+#define rENDADDR_SEC2       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF034)
+#define rENDADDR_SEC3       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF044)
+#define rENDADDR_SEC4       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF054)
+#define rENDADDR_SEC5       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF064)
+#define rENDADDR_SEC6       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF074)
+#define rENDADDR_SEC7       REG_VA_VAL(AK98_VA_SUBCTRL, 0xF084)
+
+/*************************** L2 MEMORY CONTROL *********************/
+#define rL2DMA_ADDRBUF0			REG_VA_VAL(AK98_VA_L2CTRL, 0x00)
+#define rL2DMA_ADDRBUF1			REG_VA_VAL(AK98_VA_L2CTRL, 0x04)
+#define rL2DMA_ADDRBUF2			REG_VA_VAL(AK98_VA_L2CTRL, 0x08)
+#define rL2DMA_ADDRBUF3			REG_VA_VAL(AK98_VA_L2CTRL, 0x0C)
+#define rL2DMA_ADDRBUF4			REG_VA_VAL(AK98_VA_L2CTRL, 0x10)
+#define rL2DMA_ADDRBUF5			REG_VA_VAL(AK98_VA_L2CTRL, 0x14)
+#define rL2DMA_ADDRBUF6			REG_VA_VAL(AK98_VA_L2CTRL, 0x18)
+#define rL2DMA_ADDRBUF7			REG_VA_VAL(AK98_VA_L2CTRL, 0x1C)
+#define rL2DMA_ADDRBUF8			REG_VA_VAL(AK98_VA_L2CTRL, 0x20)
+#define rL2DMA_ADDRBUF9			REG_VA_VAL(AK98_VA_L2CTRL, 0x24)
+#define rL2DMA_ADDRBUF10		REG_VA_VAL(AK98_VA_L2CTRL, 0x28)
+#define rL2DMA_ADDRBUF11		REG_VA_VAL(AK98_VA_L2CTRL, 0x2C)
+#define rL2DMA_ADDRBUF12		REG_VA_VAL(AK98_VA_L2CTRL, 0x30)
+#define rL2DMA_ADDRBUF13		REG_VA_VAL(AK98_VA_L2CTRL, 0x34)
+#define rL2DMA_ADDRBUF14		REG_VA_VAL(AK98_VA_L2CTRL, 0x38)
+#define rL2DMA_ADDRBUF15		REG_VA_VAL(AK98_VA_L2CTRL, 0x3C)
+
+#define rL2DMA_CONBUF0			REG_VA_VAL(AK98_VA_L2CTRL, 0x40)
+#define rL2DMA_CONBUF1			REG_VA_VAL(AK98_VA_L2CTRL, 0x44)
+#define rL2DMA_CONBUF2			REG_VA_VAL(AK98_VA_L2CTRL, 0x48)
+#define rL2DMA_CONBUF3			REG_VA_VAL(AK98_VA_L2CTRL, 0x4C)
+#define rL2DMA_CONBUF4			REG_VA_VAL(AK98_VA_L2CTRL, 0x50)
+#define rL2DMA_CONBUF5			REG_VA_VAL(AK98_VA_L2CTRL, 0x54)
+#define rL2DMA_CONBUF6			REG_VA_VAL(AK98_VA_L2CTRL, 0x58)
+#define rL2DMA_CONBUF7			REG_VA_VAL(AK98_VA_L2CTRL, 0x5C)
+#define rL2DMA_CONBUF8			REG_VA_VAL(AK98_VA_L2CTRL, 0x60)
+#define rL2DMA_CONBUF9			REG_VA_VAL(AK98_VA_L2CTRL, 0x64)
+#define rL2DMA_CONBUF10			REG_VA_VAL(AK98_VA_L2CTRL, 0x68)
+#define rL2DMA_CONBUF11			REG_VA_VAL(AK98_VA_L2CTRL, 0x6C)
+#define rL2DMA_CONBUF12			REG_VA_VAL(AK98_VA_L2CTRL, 0x70)
+#define rL2DMA_CONBUF13			REG_VA_VAL(AK98_VA_L2CTRL, 0x74)
+#define rL2DMA_CONBUF14			REG_VA_VAL(AK98_VA_L2CTRL, 0x78)
+#define rL2DMA_CONBUF15			REG_VA_VAL(AK98_VA_L2CTRL, 0x7C)
+
+#define rL2_DMAREQ              REG_VA_VAL(AK98_VA_L2CTRL, 0x80)
+#define rL2_FRACDMAADDR         REG_VA_VAL(AK98_VA_L2CTRL, 0x84)
+#define rL2_CONBUF0_7           REG_VA_VAL(AK98_VA_L2CTRL, 0x88)  
+#define rL2_CONBUF8_15          REG_VA_VAL(AK98_VA_L2CTRL, 0x8C) 
+#define rL2_BUFASSIGN1          REG_VA_VAL(AK98_VA_L2CTRL, 0x90) 
+#define rL2_BUFASSIGN2          REG_VA_VAL(AK98_VA_L2CTRL, 0x94) 
+#define rL2_LDMACON             REG_VA_VAL(AK98_VA_L2CTRL, 0x98) 
+#define rL2_BUFINTEN            REG_VA_VAL(AK98_VA_L2CTRL, 0x9C) 
+#define rL2_BUFSTAT1            REG_VA_VAL(AK98_VA_L2CTRL, 0xA0) 
+#define rL2_BUFSTAT2			REG_VA_VAL(AK98_VA_L2CTRL, 0xA8) 
+
+/*************************** L2 MEMORY BUFFER **********************/
+#define rL2_ADDRBUF0            REG_VA_VAL(AK98_VA_L2MEM, 0x0000)
+#define rL2_ADDRBUF1            REG_VA_VAL(AK98_VA_L2MEM, 0x0200)
+#define rL2_ADDRBUF2            REG_VA_VAL(AK98_VA_L2MEM, 0x0400)
+#define rL2_ADDRBUF3            REG_VA_VAL(AK98_VA_L2MEM, 0x0600)
+#define rL2_ADDRBUF4            REG_VA_VAL(AK98_VA_L2MEM, 0x0800)
+#define rL2_ADDRBUF5            REG_VA_VAL(AK98_VA_L2MEM, 0x0A00)
+#define rL2_ADDRBUF6            REG_VA_VAL(AK98_VA_L2MEM, 0x0C00)
+#define rL2_ADDRBUF7            REG_VA_VAL(AK98_VA_L2MEM, 0x0E00)
+
+#define rL2_ADDRTX1_BUF8        REG_VA_VAL(AK98_VA_L2MEM, 0x1000)
+#define rL2_ADDRRX1_BUF9        REG_VA_VAL(AK98_VA_L2MEM, 0x1080)
+#define rL2_ADDRTX2_BUF10       REG_VA_VAL(AK98_VA_L2MEM, 0x1100)
+#define rL2_ADDRRX2_BUF11       REG_VA_VAL(AK98_VA_L2MEM, 0x1180)
+#define rL2_ADDRTX3_BUF12       REG_VA_VAL(AK98_VA_L2MEM, 0x1200)
+#define rL2_ADDRRX3_BUF13       REG_VA_VAL(AK98_VA_L2MEM, 0x1280)
+#define rL2_ADDRTX4_BUF14       REG_VA_VAL(AK98_VA_L2MEM, 0x1300)
+#define rL2_ADDRRX4_BUF15       REG_VA_VAL(AK98_VA_L2MEM, 0x1380)
+
+#define rL2_ADDRUSB_BUF16       REG_VA_VAL(AK98_VA_L2MEM, 0x1400)
+
+
+
+#endif  /* __REGS_L2_H_ */
diff --git a/arch/arm/mach-ak98/include/mach/regs-lcd.h b/arch/arm/mach-ak98/include/mach/regs-lcd.h
new file mode 100755
index 00000000000..7165163146a
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-lcd.h
@@ -0,0 +1,100 @@
+#ifndef _AK98_LCD_REGS_H
+#define _AK98_LCD_REGS_H
+
+#include <mach/map.h>
+
+/* system control registers */
+#define AK98_CLK_DIV1               (AK98_VA_SYSCTRL + 0x04)
+#define AK98_CLKRST_CTRL1           (AK98_VA_SYSCTRL + 0x0C)
+
+#define AK98_MULTIFUNC_CTRL_REG1    (AK98_VA_SYSCTRL + 0x58)
+
+#define AK98_SRDPIN_CTRL1           (AK98_VA_SYSCTRL + 0x78)
+#define AK98_SRDPIN_CTRL2           (AK98_VA_SYSCTRL + 0x74)
+
+#define AK98_PUPD2                  (AK98_VA_SYSCTRL + 0xA0)
+#define AK98_PUPD3                  (AK98_VA_SYSCTRL + 0xA4)
+#define AK98_PUPD4                  (AK98_VA_SYSCTRL + 0xA8)
+
+#define AK98_AHB_PRIORITY1          (AK98_VA_REGRAM + 0x18)
+#define AK98_AHB_PRIORITY2          (AK98_VA_REGRAM + 0x1C)
+
+/* LCD controller registers */
+#define AK98_LCD_CMD1               (AK98_VA_DISP + 0x00)
+#define AK98_LCD_RESET              (AK98_VA_DISP + 0x08)	//to send a reset signal
+#define AK98_RGBIF_CTRL1            (AK98_VA_DISP + 0x10)	//signal of RGB interface conf
+#define AK98_RGBIF_CTRL2            (AK98_VA_DISP + 0x14)	//buffer address setting and to enable virtual page func of data from RGB channel
+#define AK98_RGB_VPAGE_SIZE         (AK98_VA_DISP + 0x18)	//virtual page size of the data input from RGB channel
+#define AK98_RGB_VPAGE_OFFSET       (AK98_VA_DISP + 0x1C)	//virtual page offset reg
+#define AK98_BG_COLOR               (AK98_VA_DISP + 0x3C)	//background color
+#define AK98_RGBIF_CTRL3            (AK98_VA_DISP + 0x40)	//Horizontal/Vertical sync pulse width
+#define AK98_RGBIF_CTRL4            (AK98_VA_DISP + 0x44)	//Horizontal back porch width and display area width
+#define AK98_RGBIF_CTRL5            (AK98_VA_DISP + 0x48)	//Horizontal front porch width
+#define AK98_RGBIF_CTRL6            (AK98_VA_DISP + 0x4C)	//Vertical back porch width
+#define AK98_RGBIF_CTRL7            (AK98_VA_DISP + 0x50)	//Vertical front porch width
+#define AK98_RGBIF_CTRL8            (AK98_VA_DISP + 0x54)	//Vertical display area
+#define AK98_RGBIF_CTRL9            (AK98_VA_DISP + 0x58)	//Length of VOVSYNC signal
+#define AK98_RGB_OFFSET             (AK98_VA_DISP + 0xA8)	//Offset values of the data input from RGB channel
+#define AK98_RGB_SIZE               (AK98_VA_DISP + 0xAC)	//the size of the data input from RGB channel
+#define AK98_DISP_SIZE              (AK98_VA_DISP + 0xB0)	//Display area size
+#define AK98_LCD_CMD2               (AK98_VA_DISP + 0xB4)	//LCD command
+#define AK98_LCD_OPER               (AK98_VA_DISP + 0xB8)	//to start the reflash func
+#define AK98_LCD_STATUS             (AK98_VA_DISP + 0xBC)
+#define AK98_LCD_INT_ENAB           (AK98_VA_DISP + 0xC0)	//to enable interrupt
+//status_reg bits corespondents to int_enab_reg
+//0x2001,00bc bits corespondents to 0x2001,00c0
+#define AK98_LCD_SOFT_CTRL          (AK98_VA_DISP + 0xC8)	//software control
+#define AK98_LCD_CLKCONF            (AK98_VA_DISP + 0xE8)	//LCD clock configuration
+
+/* registers for overlay1 */
+#define AK98_OV1_YADDR                (AK98_VA_DISP + 0x5C)
+#define AK98_OV1_UADDR                (AK98_VA_DISP + 0x60)
+#define AK98_OV1_VADDR                (AK98_VA_DISP + 0x64)
+#define AK98_OV1_HORI_CONF            (AK98_VA_DISP + 0x68)
+#define AK98_OV1_VERT_CONF            (AK98_VA_DISP + 0x6C)
+#define AK98_OV1_SCALER               (AK98_VA_DISP + 0x70)
+#define AK98_OV1_DISP_CONF            (AK98_VA_DISP + 0x74)
+#define AK98_OV1_VPAGE_SIZE           (AK98_VA_DISP + 0x78)
+#define AK98_OV1_VPAGE_OFFSET         (AK98_VA_DISP + 0x7C)
+
+/* registers for overlay2 */
+#define AK98_OV2_YADDR                (AK98_VA_DISP + 0x80)
+#define AK98_OV2_UADDR                (AK98_VA_DISP + 0x84)
+#define AK98_OV2_VADDR                (AK98_VA_DISP + 0x88)
+#define AK98_OV2_HORI_CONF            (AK98_VA_DISP + 0x8C)
+#define AK98_OV2_VERT_CONF            (AK98_VA_DISP + 0x90)
+#define AK98_OV2_SCALER               (AK98_VA_DISP + 0x94)
+#define AK98_OV2_DISP_CONF            (AK98_VA_DISP + 0x98)
+
+/* registers for osd */
+#define AK98_OSD_ADDR                 (AK98_VA_DISP + 0x20)
+#define AK98_OSD_COLOR1               (AK98_VA_DISP + 0x28)
+#define AK98_OSD_COLOR2               (AK98_VA_DISP + 0x2C)
+#define AK98_OSD_COLOR3               (AK98_VA_DISP + 0x30)
+#define AK98_OSD_COLOR4               (AK98_VA_DISP + 0x34)
+#define AK98_OSD_COLOR5               (AK98_VA_DISP + 0xD0)
+#define AK98_OSD_COLOR6               (AK98_VA_DISP + 0xD4)
+#define AK98_OSD_COLOR7               (AK98_VA_DISP + 0xD8)
+#define AK98_OSD_COLOR8               (AK98_VA_DISP + 0xDC)
+#define AK98_OSD_OFFSET               (AK98_VA_DISP + 0x24)
+#define AK98_OSD_SIZE_ALPHA           (AK98_VA_DISP + 0x38)
+
+#define TVOUT_CHROMA_FREQ_REG         (AK98_VA_DISP + 0x0100)
+#define TVOUT_CTRL_REG1               (AK98_VA_DISP + 0x0104)
+#define TVOUT_PARA_CONFIG_REG1        (AK98_VA_DISP + 0x0108)
+#define TVOUT_PARA_CONFIG_REG2        (AK98_VA_DISP + 0x010c)
+#define TVOUT_PARA_CONFIG_REG3        (AK98_VA_DISP + 0x0110)
+#define TVOUT_PARA_CONFIG_REG4        (AK98_VA_DISP + 0x0114)
+#define TVOUT_PARA_CONFIG_REG5        (AK98_VA_DISP + 0x0118)
+#define TVOUT_PARA_CONFIG_REG6        (AK98_VA_DISP + 0x011c)
+#define TVOUT_CTRL_REG2               (AK98_VA_DISP + 0x0120)
+
+/*
+#define BITFIELD(high, low) (high-low+1), low
+#define THPW_BITS BITFIELD(23,11)
+*/
+
+#define AKLCD_VPAGE_WIDTH_MAX                1280
+#define AKLCD_VPAGE_HEIGHT_MAX               1024
+
+#endif	/* _AK98_LCD_REGS_H */
diff --git a/arch/arm/mach-ak98/include/mach/regs-uart.h b/arch/arm/mach-ak98/include/mach/regs-uart.h
new file mode 100644
index 00000000000..255dcd31a49
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/regs-uart.h
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/mach-ak98/include/mach/uart.h
+ */
+#ifndef __UART_H_
+#define __UART_H_
+
+#include <mach/map.h>
+
+
+#define AK98_VA_UART_REG(n)	     	(AK98_VA_DEV + 0x6000 + 0x1000 * (n)) //n = 0 ~ 3
+#define AK98_PA_UART_REG(n) 	    (AK98_PA_DEV + 0x6000 + 0x1000 * (n)) //n = 0 ~ 3
+
+/********************* uart1~4 ****************************/
+//n = 0 ~ 3
+/*
+#define rUART_CON1(n)          REG_VA_VAL(AK98_VA_UART_REG(n), 0x00)
+#define rUART_CON2(n)          REG_VA_VAL(AK98_VA_UART_REG(n), 0x04)
+#define rUART_DATACON(n)	    REG_VA_VAL(AK98_VA_UART_REG(n), 0x08)
+#define rUART_TXRXBUF(n)      	REG_VA_VAL(AK98_VA_UART_REG(n), 0x0C)
+#define rUART_RXBUF(n)         REG_VA_VAL(AK98_VA_UART_REG(n), 0x10)
+#define rUART_BCK_RXBUF(n)    	REG_VA_VAL(AK98_VA_UART_REG(n), 0x14)
+#define rUART_SBIT_TIMEOUT(n) 	REG_VA_VAL(AK98_VA_UART_REG(n), 0x18)
+*/
+
+/******************** uart1 *******************************/
+#define rUART1_CON1             REG_VA_VAL(AK98_VA_UART_REG(0), 0x00)
+#define rUART1_CON2             REG_VA_VAL(AK98_VA_UART_REG(0), 0x04)
+#define rUART1_DATACON	        REG_VA_VAL(AK98_VA_UART_REG(0), 0x08)
+#define rUART1_TXRXBUF         	REG_VA_VAL(AK98_VA_UART_REG(0), 0x0C)
+#define rUART1_RXBUF            REG_VA_VAL(AK98_VA_UART_REG(0), 0x10)
+#define rUART1_BCK_RXBUF       	REG_VA_VAL(AK98_VA_UART_REG(0), 0x14)
+#define rUART1_SBIT_TIMEOUT 	REG_VA_VAL(AK98_VA_UART_REG(0), 0x18)
+
+/******************** uart2 *******************************/
+#define rUART2_CON1             REG_VA_VAL(AK98_VA_UART_REG(1), 0x00)
+#define rUART2_CON2             REG_VA_VAL(AK98_VA_UART_REG(1), 0x04)
+#define rUART2_DATACON        	REG_VA_VAL(AK98_VA_UART_REG(1), 0x08)
+#define rUART2_TXRXBUF        	REG_VA_VAL(AK98_VA_UART_REG(1), 0x0C)
+#define rUART2_RXBUF            REG_VA_VAL(AK98_VA_UART_REG(1), 0x10)
+#define rUART2_BCK_RXBUF      	REG_VA_VAL(AK98_VA_UART_REG(1), 0x14)
+#define rUART2_SBIT_TIMEOUT 	REG_VA_VAL(AK98_VA_UART_REG(1), 0x18)
+
+/******************** uart3 *******************************/
+#define rUART3_CON1             REG_VA_VAL(AK98_VA_UART_REG(2), 0x00)
+#define rUART3_CON2             REG_VA_VAL(AK98_VA_UART_REG(2), 0x04)
+#define rUART3_DATACON        	REG_VA_VAL(AK98_VA_UART_REG(2), 0x08)
+#define rUART3_TXRXBUF         	REG_VA_VAL(AK98_VA_UART_REG(2), 0x0C)
+#define rUART3_RXBUF            REG_VA_VAL(AK98_VA_UART_REG(2), 0x10)
+#define rUART3_BCK_RXBUF       	REG_VA_VAL(AK98_VA_UART_REG(2), 0x14)
+#define rUART3_SBIT_TIMEOUT		REG_VA_VAL(AK98_VA_UART_REG(2), 0x18)
+
+/******************** uart4 *******************************/
+#define rUART4_CON1             REG_VA_VAL(AK98_VA_UART_REG(3), 0x00)
+#define rUART4_CON2             REG_VA_VAL(AK98_VA_UART_REG(3), 0x04)
+#define rUART4_DATACON       	REG_VA_VAL(AK98_VA_UART_REG(3), 0x08)
+#define rUART4_TXRX_BUF         REG_VA_VAL(AK98_VA_UART_REG(3), 0x0C)
+#define rUART4_RXBUF            REG_VA_VAL(AK98_VA_UART_REG(3), 0x10)
+#define rUART4_BCK_RXBUF       	REG_VA_VAL(AK98_VA_UART_REG(3), 0x14)
+#define rUART4_SBIT_TIMEOUT  	REG_VA_VAL(AK98_VA_UART_REG(3), 0x18)
+
+
+/************************** UART *************************************/
+#define AK98_UART_CFG_REG1(n)       (AK98_VA_DEV+0x6000+(n)*0x1000)   //n=0 to 3   // 0x20026000,0x20027000,0x20028000,0x20029000
+#define AK98_UART_CFG_REG2(n)       (AK98_VA_DEV+0x6004+(n)*0x1000)   //n=0 to 3   // 0x20026004,0x20027004,0x20028004,0x20029004
+#define AK98_UART_DATA_CFG(n)       (AK98_VA_DEV+0x6008+(n)*0x1000)   //n=0 to 3   // 0x20026008,0x20027008,0x20028008,0x20029008
+#define AK98_UART_THREHOLD(n)       (AK98_VA_DEV+0x600C+(n)*0x1000)   //n=0 to 3   // 0x2002600C,0x2002700C,0x2002800C,0x2002900C
+#define AK98_UART_RX_DATA(n)        (AK98_VA_DEV+0x6010+(n)*0x1000)   //n=0 to 3   // 0x20026010,0x20027010,0x20028010,0x20029010
+
+
+#define UART_BOOT_SET
+
+#endif /* __UART_H_ */
+
+
+
+
diff --git a/arch/arm/mach-ak98/include/mach/reset.h b/arch/arm/mach-ak98/include/mach/reset.h
new file mode 100644
index 00000000000..7a38d03bd2b
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/reset.h
@@ -0,0 +1,9 @@
+/* include/asm/arch/reset.h
+ *
+ */
+#ifndef _AK98_RESET_H_
+#define _AK98_RESET_H_	__FILE__
+
+extern void (*ak98_arch_reset) (void);
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/rtc.h b/arch/arm/mach-ak98/include/mach/rtc.h
new file mode 100644
index 00000000000..12f68b41dad
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/rtc.h
@@ -0,0 +1,120 @@
+/*
+ * linux/arch/arm/mach-ak98/include/mach/rtc.h
+ *
+ * AK98 RTC related routines
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_RTC_H
+#define __ASM_ARCH_RTC_H
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/log2.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+
+#define EPOCH_START_YEAR	(1900)
+#define RTC_START_YEAR		(1970)
+#define RTC_YEAR_COUNT		(127)
+
+#define AK98_RTC_CONF		(AK98_VA_SYSCTRL + 0x50)
+#define AK98_RTC_DATA		(AK98_VA_SYSCTRL + 0x54)
+#define SYSCTRL_INT_CTRL        (AK98_VA_SYSCTRL + 0x4C)
+#define AK98_RTC_CDR		(AK98_VA_SYSCTRL + 0x04)
+#define RTC_RDY_EN		(1 << 24)
+
+#define RTC_WAKEUP_EN			(1 << 16)
+#define RTC_CONF_RTC_WR_EN	(1 << 25)
+#define RTC_CONF_RTC_EN		(1 << 24)
+#define RTC_CONF_RTC_READ	((1 << 21) | (2 << 18) | (1 << 17))
+#define RTC_CONF_RTC_WRITE	((1 << 21) | (2 << 18) | (0 << 17))
+
+#define AK98_RTC_REAL_TIME1	(0x0)
+#define AK98_RTC_REAL_TIME2	(0x1)
+#define AK98_RTC_REAL_TIME3	(0x2)
+#define AK98_RTC_ALARM_TIME1	(0x3)
+#define AK98_RTC_ALARM_TIME2	(0x4)
+#define AK98_RTC_ALARM_TIME3	(0x5)
+#define AK98_WDT_RTC_TIMER_CONF	(0x6)
+#define AK98_RTC_SETTING	(0x7)
+#define AK98_RTC_REG_MAX	AK98_RTC_SETTING
+
+#define RTC_ON 1
+#define RTC_OFF 0
+#define RTC_SETTING_REAL_TIME_RE	(1 << 4)
+#define RTC_SETTING_REAL_TIME_WR	(1 << 3)
+
+/*
+ * When the RTC module begins to receive/send data, bit [24] of Interrupt Enable/Status
+ * Register of System Control Module (Add: 0x0800, 004C) is set to 0; and then this
+ * bit is set to 1 automatically to indicate that the data has been well received/sent
+ */
+static void inline ak98_rtc_wait_ready(void)
+{
+	while (!(__raw_readl(SYSCTRL_INT_CTRL) & RTC_RDY_EN))
+		;
+}
+
+static void inline rtc_ready_irq_enable(void)
+{
+	unsigned long regval;
+
+	/*
+	 * Mask RTC Ready Interrupt
+	 */
+	regval = __raw_readl(SYSCTRL_INT_CTRL);
+	__raw_writel(regval | (1<<8), SYSCTRL_INT_CTRL);
+
+	/*
+	 * Wait for RTC Ready Interrupt to be cleared
+	 */
+	ak98_rtc_wait_ready();
+
+	/*
+	 * Enable RTC Register Read/Write
+	 */
+	regval = __raw_readl(AK98_RTC_CONF);
+	regval |= RTC_CONF_RTC_WR_EN;
+	__raw_writel(regval, AK98_RTC_CONF);
+}
+
+static void inline rtc_ready_irq_disable(void)
+{
+	unsigned long regval;
+	/*
+	 * Disable RTC Register Read/Write
+	 */
+	regval = __raw_readl(AK98_RTC_CONF);
+	regval &= ~RTC_CONF_RTC_WR_EN;
+	__raw_writel(regval, AK98_RTC_CONF);
+	
+	/*
+	 * Unmask RTC Ready Interrupt
+	 */
+	regval = __raw_readl(SYSCTRL_INT_CTRL);
+	__raw_writel(regval & ~(1<<8), SYSCTRL_INT_CTRL);
+}
+
+void ak98_rtc_power(int op);
+
+unsigned int ak98_rtc_read(unsigned int addr);
+unsigned int ak98_rtc_write(unsigned int addr, unsigned int value);
+unsigned int ak98_rtc_set_wpin(bool level);
+void ak98_reboot_sys_by_wtd(void);
+void ak98_reboot_sys_by_wakeup(void);
+
+#endif /*  __ASM_ARCH_RTC_H */
diff --git a/arch/arm/mach-ak98/include/mach/spi.h b/arch/arm/mach-ak98/include/mach/spi.h
new file mode 100644
index 00000000000..d7aac1014a2
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/spi.h
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-ak98/spi.h
+ */
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+struct ak98_spi_info {
+	unsigned long pin_cs;
+	unsigned long board_size;
+	unsigned short bus_num;
+	unsigned short num_cs;
+	unsigned short mode_bits;
+	char clk_name[20];
+	int mode;
+	struct spi_board_info *board_info;
+
+	void (*gpio_setup)(struct ak98_spi_info *spi, int enable);
+	void (*set_cs) (struct ak98_spi_info, int cs, int pol);
+};
+
+#define AK98_SPICON		(0x00)
+#define AK98_SPICON_CLKDIV	(0x7F<<8)
+#define AK98_SPICON_EN	(1<<6)
+#define AK98_SPICON_CS	(1<<5)
+#define AK98_SPICON_MS	(1<<4)
+#define AK98_SPICON_CPHA	(1<<3)
+#define AK98_SPICON_CPOL	(1<<2)
+#define AK98_SPICON_ARRM	(1<<1)
+#define AK98_SPICON_TGDM	(1<<0)
+
+#define AK98_SPISTA		(0x04)
+#define AK98_SPISTA_TIMEOUT	(1<<10)
+#define AK98_SPISTA_MPROC	(1<<9)
+#define AK98_SPISTA_TRANSF	(1<<8)
+#define AK98_SPISTA_RXOVER	(1<<7)
+#define AK98_SPISTA_RXHFULL	(1<<6)
+#define AK98_SPISTA_RXFULL	(1<<5)
+#define AK98_SPISTA_RXEMP	(1<<4)
+#define AK98_SPISTA_TXUNDER	(1<<3)
+#define AK98_SPISTA_TXHEMP	(1<<2)
+#define AK98_SPISTA_TXFULL	(1<<1)
+#define AK98_SPISTA_TXEMP	(1<<0)
+
+#define AK98_SPIINT		(0x08)
+#define AK98_SPIINT_TIMEOUT	(1<<10)
+#define AK98_SPIINT_MPROC	(1<<9)
+#define AK98_SPIINT_TRANSF	(1<<8)
+#define AK98_SPIINT_RXOVER	(1<<7)
+#define AK98_SPIINT_RXHFULL	(1<<6)
+#define AK98_SPIINT_RXFULL	(1<<5)
+#define AK98_SPIINT_RXEMP	(1<<4)
+#define AK98_SPIINT_TXUNDER	(1<<3)
+#define AK98_SPIINT_TXHEMP	(1<<2)
+#define AK98_SPIINT_TXFULL	(1<<1)
+#define AK98_SPIINT_TXEMP	(1<<0)
+
+#define AK98_SPICNT		(0x0C)
+
+#define AK98_SPIEXTX		(0x10)
+
+#define AK98_SPIEXRX		(0x14)
+
+#define AK98_SPIOUT		(0x18)
+
+#define AK98_SPIIN		(0x1C)
+
+#endif
diff --git a/arch/arm/mach-ak98/include/mach/system-reset.h b/arch/arm/mach-ak98/include/mach/system-reset.h
new file mode 100644
index 00000000000..77426f25339
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/system-reset.h
@@ -0,0 +1,42 @@
+/* arch/arm/mach-ak880x/include/mach/system-reset.h
+ * from arch/arm/mach-s3c2410/include/mach/system-reset.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * AK98 - System define for arch_reset() function
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+//#include <mach/hardware.h>
+//#include <mach/watchdog-reset.h>
+
+extern void (*ak880x_reset_hook) (void);
+
+static inline void arch_wdt_reset(void)
+{
+	//struct clk *wdtclk;
+
+	printk("arch_reset: attempting watchdog reset\n");
+
+	/* delay to allow the serial port to show the message */
+	mdelay(50);
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	if (mode == 's') {
+		cpu_reset(0);
+	}
+
+	if (ak880x_reset_hook)
+		ak880x_reset_hook();
+
+	arch_wdt_reset();
+
+	/* we'll take a jump through zero as a poor second */
+	cpu_reset(0);
+}
diff --git a/arch/arm/mach-ak98/include/mach/system.h b/arch/arm/mach-ak98/include/mach/system.h
new file mode 100644
index 00000000000..e73dbf51045
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/system.h
@@ -0,0 +1,35 @@
+/* linux/include/asm-arm/arch-ak98/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/proc-fns.h>
+#include <mach/reset.h>
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+	switch (mode) {
+	case 's':	/*  Software reset, using default */
+		cpu_reset(0);
+		break;
+	case 'h':	/*  Hardware reset, platform specific */
+		if (ak98_arch_reset)
+			ak98_arch_reset();
+		break;
+	default:
+		/*  Not Implemented Yet - Not needed */
+		break;
+	}
+}
+
+#endif	/*  __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-ak98/include/mach/timex.h b/arch/arm/mach-ak98/include/mach/timex.h
new file mode 100644
index 00000000000..452cf9adb6c
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/timex.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-ak880x/include/mach/timex.h
+ *
+ * AK88 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif				/* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ak98/include/mach/ts.h b/arch/arm/mach-ak98/include/mach/ts.h
new file mode 100644
index 00000000000..39bd91b6759
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/ts.h
@@ -0,0 +1,13 @@
+#ifndef __AK98_TS_H_
+#define __AK98_TS_H_ __FILE__
+
+struct ak98_ts_mach_info {
+	unsigned int irq;	/* use a macro convert gpio pin */
+	unsigned int irqpin;
+	unsigned int sample_rate;
+	unsigned int wait_time;
+};
+
+#endif				/* __AK98_TS_H_ */
+
+
diff --git a/arch/arm/mach-ak98/include/mach/uncompress.h b/arch/arm/mach-ak98/include/mach/uncompress.h
new file mode 100644
index 00000000000..f5403fad5da
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/uncompress.h
@@ -0,0 +1,319 @@
+/*
+ * linux/arch/arm/mach-ak98/include/mach/uncompress.h
+ *
+ */
+#ifndef __UNCOMPRESS_H_
+#define __UNCOMPRESS_H_
+
+#include <asm/sizes.h>
+
+#include <mach/map.h>
+#include <mach/regs-uart.h>
+
+#define L2_CACHE_CFG_REG	REG_PA_VAL(AK98_PA_L2CACH, 0x00)
+#define L2_CACHE_SECTION0_START	REG_PA_VAL(AK98_PA_L2CACH, 0x10)
+#define L2_CACHE_SECTION0_END	REG_PA_VAL(AK98_PA_L2CACH, 0x14)
+
+#define CONFIG_ANYKA_LL_DEBUG_UART0
+#define BAUD_RATE  115200
+
+/* L2 buffer register */
+#define L2BUF_CONF2_REG         REG_PA_VAL(AK98_PA_L2CTRL, 0x8C) //0x2002c08c
+
+#define UART0_TXBUF_CLR_BIT     16
+#define UART0_RXBUF_CLR_BIT     17
+#define UART1_TXBUF_CLR_BIT     18
+#define UART1_RXBUF_CLR_BIT     19
+#define UART2_TXBUF_CLR_BIT     20
+#define UART2_RXBUF_CLR_BIT     21
+#define UART3_TXBUF_CLR_BIT     22
+#define UART3_RXBUF_CLR_BIT     23
+
+/* L2 buffer address */
+#define L2BUF(addr)             (*(volatile unsigned long*)(addr))
+
+#define UART0_TXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1000) //0x48001000
+#define UART0_RXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1080)
+#define UART1_TXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1100)
+#define UART1_RXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1180)
+#define UART2_TXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1200)
+#define UART2_RXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1280)
+#define UART3_TXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1300)
+#define UART3_RXBUF_ADDR        REG_PA_ADDR(AK98_PA_L2MEM, 0x1380)
+
+#define ENDDING_OFFSET1         60
+#define ENDDING_OFFSET2         124
+
+/* Clock divider register */
+#define CLK_DIV_REG             REG_PA_VAL(AK98_PA_SYSCTRL, 0x0004) //0x08000004
+
+/* Pin configure registers */
+#define PPU_PPD1_REG           	REG_PA_VAL(AK98_PA_SYSCTRL, 0x009C) //0x0800009C
+#define GPIO_CTRL1_REG         	REG_PA_VAL(AK98_PA_SYSCTRL, 0x00D4) //0x080000D4
+
+/* pullup control: 0 - pulldown; 1 - pullup */
+#define CTS3_PU_BIT             27  //0x0800009c
+#define RTS3_PU_BIT             26
+#define URD3_PU_BIT             25
+#define UTD3_PU_BIT             24
+#define CTS2_PU_BIT             23
+#define RTS2_PU_BIT             22
+#define URD2_PU_BIT             21
+#define UTD2_PU_BIT             20
+#define CTS1_PU_BIT             19
+#define RTS1_PU_BIT             18
+#define URD1_PU_BIT             17
+#define UTD1_PU_BIT             16
+#define URD0_PU_BIT             15
+#define UTD0_PU_BIT             14
+/* pullup/pulldown enable, Active High*/
+#define RTS3_PE_BIT             25  //0x080000d4
+#define CTS3_PE_BIT             24
+#define UTD3_PE_BIT             23
+#define URD3_PE_BIT             22
+#define RTS2_PE_BIT             21
+#define CTS2_PE_BIT             20
+#define UTD2_PE_BIT             19
+#define URD2_PE_BIT             18
+#define RTS1_PE_BIT             17
+#define CTS1_PE_BIT             16
+#define UTD1_PE_BIT             15
+#define URD1_PE_BIT             14
+/* input enable, Active Low */
+#define RTS3_IE_BIT             13  //0x080000d4
+#define CTS3_IE_BIT             12
+#define UTD3_IE_BIT             11
+#define URD3_IE_BIT             10
+#define RTS2_IE_BIT             9
+#define CTS2_IE_BIT             8
+#define UTD2_IE_BIT             7
+#define URD2_IE_BIT             6
+#define RTS1_IE_BIT             5
+#define CTS1_IE_BIT             4
+#define UTD1_IE_BIT             3
+#define URD1_IE_BIT             2
+
+/* Clock control register */
+#define CLK_CTRL_REG1			REG_PA_VAL(AK98_PA_SYSCTRL, 0x000C) //0x0800000C
+#define CLK_CTRL_REG2		 	REG_PA_VAL(AK98_PA_SYSCTRL, 0x0010) //0x08000010
+
+#define UART0_ENABLE_BIT        12  //0x0800000C
+#define UART1_ENABLE_BIT        4 	//0x08000010
+#define UART2_ENABLE_BIT        5 	//0x08000010
+#define UART3_ENABLE_BIT        6  	//0x08000010
+
+/* Shared pin control reigsters */
+#define SRDPIN_CTRL1_REG     	REG_PA_VAL(AK98_PA_SYSCTRL, 0x0078) //0x08000078
+#define SRDPIN_CTRL2_REG     	REG_PA_VAL(AK98_PA_SYSCTRL, 0x0074) //0x08000074
+
+#define SRDPIN_UART0_RXTX_BIT   9   //0x08000078
+
+#define SRDPIN_UART1_RXTX_BIT   10  //0x08000078
+#define SRDPIN_UART1_RTSCTS_BIT 11  //0x08000078
+#define SRDPIN_UART2_RXTX_BIT   12  //0x08000078
+#define SRDPIN_UART2_RTSCTS_BIT 13  //0x08000078
+#define SRDPIN_UART3_RXTX_BIT   14  //0x08000078
+#define SRDPIN_UART3_RTSCTS_BIT 15  //0x08000078
+
+#define SRDPIN_UART3_SDIO_BIT   1   //0x08000074, 01: used for uart3
+
+/** ************ UART registers *****************************/
+#define UART0_CONF1_REG			REG_PA_VAL(AK98_PA_UART_REG(0), 0x00) //0x20026000
+#define UART0_CONF2_REG			REG_PA_VAL(AK98_PA_UART_REG(0), 0x04)
+#define UART0_DATA_CONF_REG		REG_PA_VAL(AK98_PA_UART_REG(0), 0x08)
+#define UART0_BUF_THRE_REG		REG_PA_VAL(AK98_PA_UART_REG(0), 0x0C)
+#define UART0_BUF_STOPBIT_REG		REG_PA_VAL(AK98_PA_UART_REG(0), 0x18)
+
+#define UART1_CONF1_REG			REG_PA_VAL(AK98_PA_UART_REG(1), 0x00) //0x20027000
+#define UART1_CONF2_REG			REG_PA_VAL(AK98_PA_UART_REG(1), 0x04)
+#define UART1_DATA_CONF_REG		REG_PA_VAL(AK98_PA_UART_REG(1), 0x08)
+#define UART1_BUF_THRE_REG		REG_PA_VAL(AK98_PA_UART_REG(1), 0x0C)
+#define UART1_BUF_STOPBIT_REG		REG_PA_VAL(AK98_PA_UART_REG(1), 0x18)
+
+
+#define UART2_CONF1_REG			REG_PA_VAL(AK98_PA_UART_REG(2), 0x00) //0x20028000
+#define UART2_CONF2_REG			REG_PA_VAL(AK98_PA_UART_REG(2), 0x04)
+#define UART2_DATA_CONF_REG		REG_PA_VAL(AK98_PA_UART_REG(2), 0x08)
+#define UART2_BUF_THRE_REG		REG_PA_VAL(AK98_PA_UART_REG(2), 0x0C)
+#define UART2_BUF_STOPBIT_REG		REG_PA_VAL(AK98_PA_UART_REG(2), 0x18)
+
+
+#define UART3_CONF1_REG			REG_PA_VAL(AK98_PA_UART_REG(3), 0x00) //0x20029000
+#define UART3_CONF2_REG			REG_PA_VAL(AK98_PA_UART_REG(3), 0x04)
+#define UART3_DATA_CONF_REG		REG_PA_VAL(AK98_PA_UART_REG(3), 0x08)
+#define UART3_BUF_THRE_REG		REG_PA_VAL(AK98_PA_UART_REG(3), 0x0C)
+#define UART3_BUF_STOPBIT_REG		REG_PA_VAL(AK98_PA_UART_REG(3), 0x18)
+
+
+/* bit define of UARTx_CONF1_REG */
+#define BAUD_RATE_DIV_BIT       0   //baudrate value
+#define CTS_SEL_BIT             18
+#define RTS_SEL_BIT             19
+#define PORT_ENABLE_BIT         21  //0: disable, 1:enable
+#define TX_STATUS_CLR_BIT       28
+#define RX_STATUS_CLR_BIT       29
+
+/* bit define of UARTx_CONF2_REG */
+#define TX_COUNT_BIT            4
+#define TX_COUNT_VALID_BIT      16
+#define TX_END_BIT              19
+#define TX_END_MASK             (1 << TX_END_BIT)
+
+#if defined CONFIG_ANYKA_LL_DEBUG_UART3
+#define UART_TXBUF_CLR_BIT      UART3_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART3_RXTX_BIT
+#define URD_PU_BIT              URD3_PU_BIT
+#define UTD_PU_BIT              UTD3_PU_BIT
+#define URD_PE_BIT              URD3_PE_BIT
+#define UTD_PE_BIT              UTD3_PE_BIT
+#define URD_IE_BIT              URD3_IE_BIT
+#define UTD_IE_BIT              UTD3_IE_BIT
+#define UART_ENABLE_BIT         UART3_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART3_TXBUF_ADDR
+#define UART_CONF1_REG          UART3_CONF1_REG
+#define UART_CONF2_REG          UART3_CONF2_REG
+#define UART_DATA_CONF_REG      UART3_DATA_CONF_REG
+#define UART_BUF_STOPBIT_REG	UART3_BUF_STOPBIT_REG
+
+#elif defined CONFIG_ANYKA_LL_DEBUG_UART2
+#define UART_TXBUF_CLR_BIT      UART2_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART2_RXTX_BIT
+#define URD_PU_BIT              URD2_PU_BIT
+#define UTD_PU_BIT              UTD2_PU_BIT
+#define URD_PE_BIT              URD2_PE_BIT
+#define UTD_PE_BIT              UTD2_PE_BIT
+#define URD_IE_BIT              URD2_IE_BIT
+#define UTD_IE_BIT              UTD2_IE_BIT
+#define UART_ENABLE_BIT         UART2_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART2_TXBUF_ADDR
+#define UART_CONF1_REG          UART2_CONF1_REG
+#define UART_CONF2_REG          UART2_CONF2_REG
+#define UART_DATA_CONF_REG      UART2_DATA_CONF_REG
+#define UART_BUF_STOPBIT_REG	UART2_BUF_STOPBIT_REG
+#elif defined CONFIG_ANYKA_LL_DEBUG_UART1
+#define UART_TXBUF_CLR_BIT      UART1_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART1_RXTX_BIT
+#define URD_PU_BIT              URD1_PU_BIT
+#define UTD_PU_BIT              UTD1_PU_BIT
+#define URD_PE_BIT              URD1_PE_BIT
+#define UTD_PE_BIT              UTD1_PE_BIT
+#define URD_IE_BIT              URD1_IE_BIT
+#define UTD_IE_BIT              UTD1_IE_BIT
+#define UART_ENABLE_BIT         UART1_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART1_TXBUF_ADDR
+#define UART_CONF1_REG          UART1_CONF1_REG
+#define UART_CONF2_REG          UART1_CONF2_REG
+#define UART_DATA_CONF_REG      UART1_DATA_CONF_REG
+#define UART_BUF_STOPBIT_REG	UART1_BUF_STOPBIT_REG
+#elif  defined CONFIG_ANYKA_LL_DEBUG_UART0
+#define UART_TXBUF_CLR_BIT      UART0_TXBUF_CLR_BIT
+#define SRDPIN_UART_RXTX_BIT    SRDPIN_UART0_RXTX_BIT
+#define URD_PU_BIT              URD0_PU_BIT
+#define UTD_PU_BIT              UTD0_PU_BIT
+#define UART_ENABLE_BIT         UART0_ENABLE_BIT
+#define UART_TXBUF_ADDR         UART0_TXBUF_ADDR
+#define UART_CONF1_REG          UART0_CONF1_REG
+#define UART_CONF2_REG          UART0_CONF2_REG
+#define UART_DATA_CONF_REG      UART0_DATA_CONF_REG
+#define UART_BUF_STOPBIT_REG	UART0_BUF_STOPBIT_REG
+
+#else
+#error One of UART0 ~ UART4 Must be defined
+#endif
+
+static inline void flush(void)
+{
+}
+
+static unsigned int uidiv(unsigned int num, unsigned int den)
+{
+	unsigned int i;
+
+	if (den == 1)
+		return num;
+
+	i = 1;
+	while (den * i < num)
+		i++;
+
+	return i-1;
+}
+
+static void uart_init(void)
+{
+	unsigned int pll_clk, asic_clk, clk_div;
+	unsigned int asic_div;
+
+	/* enable uart clock control */
+#ifdef CONFIG_ANYKA_LL_DEBUG_UART0
+	CLK_CTRL_REG1 &= ~(0x1 << UART_ENABLE_BIT);
+#else
+	CLK_CTRL_REG2 &= ~(0x1 << UART_ENABLE_BIT);
+#endif
+
+	/* configuration shared pins to UART */
+	SRDPIN_CTRL1_REG |= (0x1 << SRDPIN_UART_RXTX_BIT);
+#ifdef CONFIG_ANYKA_LL_DEBUG_UART3
+	SRDPIN_CTRL2_REG &= ~(0x3 << SRDPIN_UART3_SDIO_BIT);
+	SRDPIN_CTRL2_REG |= (0x1 << SRDPIN_UART3_SDIO_BIT);
+#endif
+
+	/* configuration uart pin */
+	PPU_PPD1_REG |= (0x1 << URD_PU_BIT) | (0x1 << UTD_PU_BIT);
+#ifndef CONFIG_ANYKA_LL_DEBUG_UART0
+	GPIO_CTRL1_REG |= (0x1 << URD_PE_BIT) | (0x1 << UTD_PE_BIT);
+	GPIO_CTRL1_REG &= ~(0x1 << UTD_IE_BIT);
+	GPIO_CTRL1_REG |= (0x1 << URD_IE_BIT);
+#endif
+
+	/* Set baud rate, PLL CLK = 240M, CLK168M = 120M, ASIC CLK = 60M */
+	pll_clk = uidiv(4 * (CLK_DIV_REG & 0x3f) + 180, (((CLK_DIV_REG >> 17 )& 0xf ) + 1));
+	asic_div = (CLK_DIV_REG >> 6) & 0x7;
+	if (asic_div == 0)
+		asic_div = 1;
+	asic_clk = (pll_clk >> asic_div) * 1000 * 1000;
+	clk_div = uidiv(asic_clk, BAUD_RATE) - 1;
+	UART_CONF1_REG &= ~((0x1 << TX_STATUS_CLR_BIT) | (0x1 << RX_STATUS_CLR_BIT) | 0xFF);
+	UART_CONF1_REG |= (0x1 << TX_STATUS_CLR_BIT) | (0x1 << RX_STATUS_CLR_BIT) | clk_div; 
+	
+#ifndef CONFIG_ANYKA_LL_DEBUG_UART0
+	/* Disable flow control */
+	UART_CONF1_REG |= (0x1 << CTS_SEL_BIT) | (0x1 << RTS_SEL_BIT);
+#endif
+	UART_BUF_STOPBIT_REG = (0x1F << 16) | (0x1 << 0);
+
+	/* enable uart port */
+	UART_CONF1_REG |= (0x1 << PORT_ENABLE_BIT);
+}
+
+
+/* print a char to uart */
+static void putc(char c)
+{
+	/* Clear uart tx buffer */
+	L2BUF_CONF2_REG   |= (0x1 << UART_TXBUF_CLR_BIT);
+
+	/* write char to uart buffer */
+	L2BUF(UART_TXBUF_ADDR) = (unsigned long)c;
+	L2BUF(UART_TXBUF_ADDR + ENDDING_OFFSET1) = (unsigned long)'\0';
+	
+	/* Clear uart tx count register */
+	UART_CONF1_REG |= (0x1 << TX_STATUS_CLR_BIT);
+
+	/* Send buffer */
+	UART_CONF2_REG |= (1 << TX_COUNT_BIT) | (0x1 << TX_COUNT_VALID_BIT);
+
+	/* Wait for finish */
+	while((UART_CONF2_REG & TX_END_MASK) == 0) {
+	}
+}
+
+static inline void arch_decomp_setup(void)
+{
+	uart_init();
+}
+
+/* nothing to do */
+#define arch_decomp_wdog()
+
+#endif   /* __UNCOMPRESS_H_ */
diff --git a/arch/arm/mach-ak98/include/mach/vmalloc.h b/arch/arm/mach-ak98/include/mach/vmalloc.h
new file mode 100644
index 00000000000..68dc357caef
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/vmalloc.h
@@ -0,0 +1,15 @@
+/* linux/arch/arm/mach-ak880x/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * ANYKA 8801 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END		(0xE0000000)
+
+#endif				/* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-ak98/include/mach/wifi.h b/arch/arm/mach-ak98/include/mach/wifi.h
new file mode 100644
index 00000000000..8d3e19eeec9
--- /dev/null
+++ b/arch/arm/mach-ak98/include/mach/wifi.h
@@ -0,0 +1,28 @@
+/*
+ * wifi.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _WIFI_H
+
+#include <mach/gpio.h>
+
+struct wifi_control_data {
+	struct gpio_info gpio_on;
+	struct gpio_info gpio_off;
+	int power_on_delay;
+	int power_off_delay;
+};
+
+struct ak98_wifi_platform_data {
+	int (*power_on)(void);
+	int (*power_off)(void);
+};
+
+
+#endif /* _WIFI_H */
+
diff --git a/arch/arm/mach-ak98/irq.c b/arch/arm/mach-ak98/irq.c
new file mode 100644
index 00000000000..bf04c9cd994
--- /dev/null
+++ b/arch/arm/mach-ak98/irq.c
@@ -0,0 +1,325 @@
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/ak98-gpio.h>
+
+
+#include "cpu.h"
+#include "irq.h"
+
+#define AK98_CLKDIV1		(AK98_VA_SYSCTRL + 0x04)
+#define AK98_IRQ_MASK		(AK98_VA_SYSCTRL + 0x34)
+#define AK98_FIQ_MASK		(AK98_VA_SYSCTRL + 0x38)
+#define AK98_INT_STATUS		(AK98_VA_SYSCTRL + 0xCC)
+#define	AK98_SYSCTRL_INT_CTRL	(AK98_VA_SYSCTRL + 0x4C)
+
+#define AK98_GPIO_INT_CTRL0	(AK98_VA_SYSCTRL + 0xE0)
+#define AK98_GPIO_INT_CTRL1	(AK98_VA_SYSCTRL + 0xE4)
+#define AK98_GPIO_INT_CTRL2	(AK98_VA_SYSCTRL + 0xE8)
+#define AK98_GPIO_INT_CTRL3	(AK98_VA_SYSCTRL + 0xEC)
+
+#define AK98_GPIO_INPUT0	(AK98_VA_SYSCTRL + 0xBC)
+#define AK98_GPIO_INPUT1	(AK98_VA_SYSCTRL + 0xC0)
+#define AK98_GPIO_INPUT2	(AK98_VA_SYSCTRL + 0xC4)
+#define AK98_GPIO_INPUT3	(AK98_VA_SYSCTRL + 0xC8)
+
+#define AK98_GPIO_INTP0		(AK98_VA_SYSCTRL + 0xF0)
+#define AK98_GPIO_INTP1		(AK98_VA_SYSCTRL + 0xF4)
+#define AK98_GPIO_INTP2		(AK98_VA_SYSCTRL + 0xF8)
+#define AK98_GPIO_INTP3		(AK98_VA_SYSCTRL + 0xFC)
+
+#define AK98_L2MEM_IRQ_ENABLE	(AK98_VA_L2CTRL + 0x9C)
+
+/*
+ * Disable interrupt number "irq"
+ */
+static void ak98_mask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	unsigned long bitval = (1UL << irq);
+
+	mask = __raw_readl(AK98_IRQ_MASK);
+
+	__raw_writel(mask & ~bitval, AK98_IRQ_MASK);
+}
+
+/*
+ * Enable interrupt number "irq"
+ */
+static void ak98_unmask_irq(unsigned int irq)
+{
+	unsigned long mask;
+	unsigned long bitval = (1UL << irq);
+
+	mask = __raw_readl(AK98_IRQ_MASK);
+
+	__raw_writel(mask | bitval, AK98_IRQ_MASK);
+}
+
+static struct irq_chip ak98_irq_chip = {
+	.name = "ak98xx",
+	.mask_ack = ak98_mask_irq,
+	.mask = ak98_mask_irq,
+	.unmask = ak98_unmask_irq,
+};
+
+static void sysctrl_mask_irq(unsigned int irq)
+{
+	unsigned long sysctrl;
+	unsigned long bitval = ~(1 << (irq - IRQ_TOUCHPANEL));
+
+	sysctrl = __raw_readl(AK98_SYSCTRL_INT_CTRL);
+
+	__raw_writel(sysctrl & bitval, AK98_SYSCTRL_INT_CTRL);
+}
+
+static void sysctrl_unmask_irq(unsigned int irq)
+{
+	unsigned long sysctrl;
+	unsigned long bitval = (1 << (irq - IRQ_TOUCHPANEL));
+
+	sysctrl = __raw_readl(AK98_SYSCTRL_INT_CTRL);
+
+	__raw_writel(sysctrl | bitval, AK98_SYSCTRL_INT_CTRL);
+}
+
+static int sysctrl_set_wake(unsigned int irq, unsigned int on)
+{
+	unsigned long clkdiv1;
+
+	if (irq == IRQ_RTC_ALARM) {
+
+		clkdiv1 = __raw_readl(AK98_CLKDIV1);
+
+		if (on == 1)
+			clkdiv1 |= (1 << 16);
+		else
+			clkdiv1 &= ~(1 << 16);
+
+		__raw_writel(clkdiv1, AK98_CLKDIV1);
+
+		return 0;
+	}
+
+	return 0;
+}
+
+static struct irq_chip ak98_sysctrl_chip = {
+	.name = "ak-sysctrl",
+	.mask_ack = sysctrl_mask_irq,
+	.mask = sysctrl_mask_irq,
+	.unmask = sysctrl_unmask_irq,
+	.set_wake = sysctrl_set_wake,
+};
+
+static void ak98_sysctrl_handler(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned long regval;
+	unsigned long intpnd;
+	unsigned int offset = 0;
+
+	regval = __raw_readl(AK98_SYSCTRL_INT_CTRL);
+
+	intpnd = (regval & 0x7FF) & ((regval & 0x7FF0000) >> 16);
+
+	offset = 0;
+	for (offset = 0; intpnd && offset < 32; offset++) {
+
+		if (intpnd & (1 << offset))
+			intpnd &= ~(1 << offset);
+		else
+			continue;
+
+		irq = AK98_SYSCTRL_IRQ(offset);
+
+		generic_handle_irq(irq);
+	}
+}
+
+static void ak98_gpioirq_mask(unsigned int irq)
+{
+	void __iomem *gpio_ctrl = AK98_GPIO_INT_CTRL0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+	regval &= ~(1 << (irq % 32));
+
+	__raw_writel(regval, gpio_ctrl);
+}
+
+static int ak98_gpioirq_set_type(unsigned int irq, unsigned int type)
+{
+	void __iomem *gpio_ctrl = AK98_GPIO_INTP0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+
+	if (type == IRQ_TYPE_LEVEL_HIGH)
+		regval &= ~(1 << (irq % 32));
+	else if (type == IRQ_TYPE_LEVEL_LOW)
+		regval |= (1 << (irq % 32));
+	else {
+		printk("Not support irq type\n");
+		return -1;
+	}
+
+	/* printk("0x%x, %d\n", gpio_ctrl, irq%32); */
+
+	__raw_writel(regval, gpio_ctrl);
+
+	return 0;
+}
+
+static void ak98_gpioirq_unmask(unsigned int irq)
+{
+	void __iomem *gpio_ctrl = AK98_GPIO_INT_CTRL0;
+	unsigned long regval;
+
+	irq -= IRQ_GPIO_0;
+	gpio_ctrl += (irq / 32) * 4;
+
+	regval = __raw_readl(gpio_ctrl);
+	regval |= (1 << (irq % 32));
+
+	/* printk("0x%x, %d\n", gpio_ctrl, irq%32); */
+
+	__raw_writel(regval, gpio_ctrl);
+}
+
+static int ak98_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+	unsigned long wgpio_enable;
+
+	wgpio_enable = __raw_readl(AK98_WGPIO_ENABLE);
+
+	if (irq >= IRQ_GPIO_5 && irq <= IRQ_GPIO_7)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_5));
+
+	else if (irq >= IRQ_GPIO_10 && irq <= IRQ_GPIO_13)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_10 + 3));
+
+	else if (irq >= IRQ_GPIO_16 && irq <= IRQ_GPIO_19)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_16 + 7));
+
+	else if (irq >= IRQ_GPIO_24 && irq <= IRQ_GPIO_27)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_24 + 11));
+
+	else if (irq >= IRQ_GPIO_72 && irq <= IRQ_GPIO_75)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_72 + 15));
+
+	else if (irq >= IRQ_GPIO_104 && irq <= IRQ_GPIO_107)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_104 + 19));
+	
+	else if (irq >= IRQ_GPIO_109 && irq <= IRQ_GPIO_113)
+		wgpio_enable |= (1 << (irq - IRQ_GPIO_109 + 24));
+	
+	else if (irq == IRQ_GPIO_84)
+		wgpio_enable |= (1 << 23);
+	
+	else {
+		printk("Not WGPIO IRQ: %d\n", irq);
+		return -1;
+	}
+
+	__raw_writel(wgpio_enable, AK98_WGPIO_ENABLE);
+
+	return 0;
+}
+
+static struct irq_chip ak98_gpioirq_chip = {
+	.name = "gpio_irq",
+	.mask_ack = ak98_gpioirq_mask,
+	.mask = ak98_gpioirq_mask,
+	.set_type = ak98_gpioirq_set_type,
+	.unmask = ak98_gpioirq_unmask,
+	.set_wake = ak98_gpio_irq_set_wake,
+};
+
+static void ak98_gpio_irqhandler(unsigned int irq, struct irq_desc *desc)
+{
+	unsigned long enabled_irq;
+	unsigned int i;
+	unsigned int off;
+
+	for (i = 0; i < 4; i++) {
+		enabled_irq = __raw_readl(AK98_GPIO_INT_CTRL0 + i * 4);
+
+		while (enabled_irq) {
+			off = __ffs(enabled_irq);
+			enabled_irq &= ~(1 << off);
+			if (test_bit(off, AK98_GPIO_INTP0 + i * 4) !=
+			    test_bit(off, AK98_GPIO_INPUT0 + i * 4)) {
+				irq = IRQ_GPIO_0 + i * 32 + off;
+				generic_handle_irq(irq);
+			}
+		}
+	}
+}
+
+/* ak98_init_irq
+ *
+ * Initialise AK7801 IRQ system
+ */
+
+void __init ak98_init_irq(void)
+{
+	int i;
+
+	/* 1st, clear all interrupts */
+	__raw_readl(AK98_INT_STATUS);
+	__raw_readl(AK98_SYSCTRL_INT_CTRL);
+
+	/* 2nd, mask all interrutps */
+	__raw_writel(0x0, AK98_IRQ_MASK);
+	__raw_writel(0x0, AK98_FIQ_MASK);
+	__raw_writel(0x0, AK98_SYSCTRL_INT_CTRL);
+
+	/* mask all gpio interrupts */
+	__raw_writel(0x0, AK98_GPIO_INT_CTRL0);
+	__raw_writel(0x0, AK98_GPIO_INT_CTRL1);
+	__raw_writel(0x0, AK98_GPIO_INT_CTRL2);
+	__raw_writel(0x0, AK98_GPIO_INT_CTRL3);
+
+	/* mask all l2 interrupts */
+	__raw_writel(0x0, AK98_L2MEM_IRQ_ENABLE);
+
+	for (i = 0; i <= IRQ_PCM; i++) {
+		set_irq_chip(i, &ak98_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_SYSCTRL, ak98_sysctrl_handler);
+
+	for (i = IRQ_TOUCHPANEL; i <= IRQ_PEN_DOWN_FILTER; i++) {
+		set_irq_chip(i, &ak98_sysctrl_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_GPIO, ak98_gpio_irqhandler);
+
+	for (i = IRQ_GPIO_0; i <= IRQ_GPIO_116; i++) {
+		set_irq_chip(i, &ak98_gpioirq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+}
diff --git a/arch/arm/mach-ak98/irq.h b/arch/arm/mach-ak98/irq.h
new file mode 100644
index 00000000000..652d8b34d4e
--- /dev/null
+++ b/arch/arm/mach-ak98/irq.h
@@ -0,0 +1 @@
+void __init ak98_init_irq(void);
diff --git a/arch/arm/mach-ak98/l2.c b/arch/arm/mach-ak98/l2.c
new file mode 100644
index 00000000000..8c90d158534
--- /dev/null
+++ b/arch/arm/mach-ak98/l2.c
@@ -0,0 +1,1123 @@
+/*
+ * linux/arch/arm/mach-ak98/l2.c
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/stddef.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+ 
+#include <asm/dma.h>
+#include <asm/sizes.h>
+
+#include <mach/regs-comm.h> 
+#include <mach/l2cache.h> 
+#include <mach/l2.h>
+
+static ak98_l2_buffer_info_t ak98_l2_buffer_info[AK98_L2_COMMON_BUFFER_NUM];
+static ak98_l2_dma_info_t ak98_l2_dma_info[AK98_L2_COMMON_BUFFER_NUM + AK98_L2_UART_BUFFER_NUM];
+static bool ak98_l2_frac_started = false;	/* L2 fraction DMA start flag */
+static ak98_l2_device_info_t ak98_l2_device_info[] = {
+	{ ADDR_USB_EP2,		BUF_NULL },
+	{ ADDR_USB_EP3,		BUF_NULL },
+	{ ADDR_USB_EP4,		BUF_NULL },
+	{ ADDR_NFC,		BUF_NULL },
+	{ ADDR_MMC_SD,		BUF_NULL },
+	{ ADDR_SDIO,		BUF_NULL },
+	{ ADDR_RESERVED,	BUF_NULL },
+	{ ADDR_SPI1_RX,		BUF_NULL },
+	{ ADDR_SPI1_TX,		BUF_NULL },
+	{ ADDR_DAC,		BUF_NULL },
+	{ ADDR_SPI2_RX,		BUF_NULL },
+	{ ADDR_SPI2_TX,		BUF_NULL },
+	{ ADDR_PCM_RX,		BUF_NULL },
+	{ ADDR_PCM_TX,		BUF_NULL },
+	{ ADDR_ADC,		BUF_NULL },
+	{ ADDR_USB_EP5, 	BUF_NULL },
+	{ ADDR_USB_EP6, 	BUF_NULL },
+};
+
+static int l2_wait = 0;
+static wait_queue_head_t l2_wq;
+
+static void ak98_l2_combuf_ctrl(u8 id, bool enable);
+static void ak98_l2_select_combuf(ak98_l2_device_t device, u8 id);
+static void ak98_l2_assert_combuf_id(u8 id);
+static void ak98_l2_assert_buf_id(u8 id);
+static void ak98_l2_clear_dma(u8 id);
+static void ak98_l2_frac_dma(unsigned long ram_addr, u8 id, u8 frac_offset,
+	unsigned int bytes, ak98_l2_dma_transfer_direction_t direction, bool intr_enable);
+static u32 ak98_l2_get_addr(u8 id);
+static bool ak98_l2_get_dma_param(unsigned int bytes, unsigned int *low, unsigned int *high);
+static void ak98_l2_dma(unsigned long ram_addr, u8 id, unsigned int bytes,
+		ak98_l2_dma_transfer_direction_t direction, bool intr_enable);
+static bool ak98_l2_wait_dma_finish(u8 id);
+static void ak98_l2_cpu(unsigned long ram_addr, u8 id,
+	unsigned long buf_offset, unsigned int bytes, ak98_l2_dma_transfer_direction_t direction);
+static irqreturn_t ak98_l2_interrupt_handler(int irq, void *dev_id);
+
+/**
+ * ak98_l2_assert_buf_id - Assert a L2 buffer ID is valid
+ *  @id:		L2 buffer ID
+ *
+ *  NOTE: Assert only L2 common buffer and UART buffer, USB buffer is not checked.
+ *            Since this function is called internally by other L2 API, invalid id will cause
+ *            linux kernel to oops for bug tracking.
+ */
+static void ak98_l2_assert_buf_id(u8 id)
+{
+	if (id >= AK98_L2_COMMON_BUFFER_NUM + AK98_L2_UART_BUFFER_NUM)
+		BUG();
+}
+
+/**
+ * ak98_l2_assert_combuf_id - Assert a L2 common buffer ID is valid
+ *  @id:		L2 buffer ID
+ *
+ *  NOTE: Assert only L2 common buffer, UART & USB buffer is not checked.
+ *            Since this function is called internally by other L2 API, invalid id will cause
+ *            linux kernel to oops for bug tracking.
+ */
+static void ak98_l2_assert_combuf_id(u8 id)
+{
+	if (id >= AK98_L2_COMMON_BUFFER_NUM)
+		BUG();
+}
+
+/**
+ * ak98_l2_combuf_ctrl - L2 buffer enable/disable
+ *  @id:		L2 buffer ID
+ *  @enable:	true to enable L2 buffer, false to disable L2 buffer 
+ */
+static void ak98_l2_combuf_ctrl(u8 id, bool enable)
+{
+	unsigned long regval;
+	unsigned long flags;
+
+	ak98_l2_assert_buf_id(id);
+
+	local_irq_save(flags);
+	
+	regval = rL2_CONBUF0_7;
+	if (enable) {
+		/* Enable L2 buffer & L2 Buffer DMA */
+		regval |= (1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START)) |
+			(1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_VLD_START));
+	} else {
+		/* Disable L2 buffer & L2 Buffer DMA */
+		regval &= ~((1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_DMA_VLD_START)) |
+			(1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_VLD_START)));
+	}
+	rL2_CONBUF0_7 = regval;
+
+	local_irq_restore(flags);
+
+}
+
+/**
+ * ak98_l2_select_combuf - Select a L2 buffer for given device
+ *  @device:	Device which need to assign a L2 buffer
+ *  @id:		L2 buffer ID
+ */
+static void ak98_l2_select_combuf(ak98_l2_device_t device, u8 id)
+{
+	unsigned long regval;
+	unsigned long bits_offset;
+	
+	ak98_l2_assert_combuf_id(id);
+
+	if ((u8)device < 10) {
+		/*
+		 * USB Bulkout ~ DAC (Device 0 ~ 9) is controlled by Buffer Assignment Register 1
+		 */
+		regval = rL2_BUFASSIGN1;
+		bits_offset = (u8)device * 3;
+		regval &= ~(0x7 << bits_offset);
+		regval |= ((id & 0x7) << bits_offset);
+		rL2_BUFASSIGN1 = regval;
+	} else {
+		/*
+		 * SPI2 Rx ~ ADC (Device 10 ~ 14) is controlled by Buffer Assignment Register 2
+		 */
+		regval = rL2_BUFASSIGN2;
+		bits_offset = ((u8)device - 10) * 3;
+		regval &= ~(0x7 << bits_offset);
+		regval |= ((id & 0x7) << bits_offset);
+		rL2_BUFASSIGN2 = regval;
+	}
+
+}
+
+/**
+ * ak98_l2_clear_dma - Clear L2 buffer DMA status
+ *  @id:		L2 buffer ID which need to clear DMA status
+ */
+static void ak98_l2_clear_dma(u8 id)
+{
+	bool dmapending;
+	u8 status;
+	
+	dmapending = rL2_DMAREQ & (1 << (id + AK98_L2_DMA_REQ_BUF_START));
+	status = ak98_l2_get_status(id);
+
+	if (status == 0) {
+		return ;	/* NO DMA request, so do nothing */
+	}
+
+	/*
+	 * Wait until DMA request of this L2 buffer is finished.
+	 */
+	while (dmapending) {
+		printk("ak98-l2: unfinished DMA in buf[%d].\n", id);
+		ak98_l2_clr_status(id);
+		dmapending = rL2_DMAREQ & (1 << (id + AK98_L2_DMA_REQ_BUF_START));
+	}
+
+}
+
+/**
+ * ak98_l2_frac_dma - Start data tranferring between memory and l2 common buffer in fraction DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @frac_offset:	The region offset between buffer start address and transfer start address
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ *
+ *  NOTE: Data transfer size should be 1~64Bytes, frac_offset should be 0~7 (*64Bytes)
+ */
+static void ak98_l2_frac_dma(unsigned long ram_addr, u8 id, u8 frac_offset,
+	unsigned int bytes, ak98_l2_dma_transfer_direction_t direction,	bool intr_enable)
+{
+	u32 bufaddr;
+	u32 highaddr;
+	unsigned long regval;
+	unsigned long flags;
+
+#if 0
+	printk("%s(): ram_addr=0x%08X, l2 buffer id=%d, frac_offset=%d, bytes=%d, direction=%s, intr_enable=%d.\n",
+		__func__, (unsigned int)ram_addr, id, frac_offset, bytes, (direction == BUF2MEM)?"BUF2MEM":"MEM2BUF", intr_enable);
+#endif
+
+	if (bytes == 0) {
+		printk("ak98-l2: no need to start fraction dma transfer: bytes=0.\n");
+		return ;
+	}
+
+	local_irq_save(flags);
+
+	/*
+	 * Set fraction external RAM address.
+	 */
+	highaddr = (ram_addr << 2) & 0xC0000000;
+	 
+	regval = rL2_FRACDMAADDR;
+	regval &= ~AK98_L2_FRAC_DMA_LOW_ADDR_MASK;
+	regval |= (ram_addr & AK98_L2_FRAC_DMA_LOW_ADDR_MASK) | highaddr;
+	rL2_FRACDMAADDR = regval;
+
+	/* Set fraction DMA address */
+	bufaddr = (id < AK98_L2_COMMON_BUFFER_NUM) ? ((id & 0x7) << 3) | (frac_offset & 0x7) :
+		(0x40 + ((id - AK98_L2_COMMON_BUFFER_NUM) << 1)) | (frac_offset & 0x1);
+
+	/* Clear other fraction DMA request and info */
+	regval = rL2_DMAREQ;
+	regval &= ~(AK98_L2_DMA_REQ_FRAC_DMA_LEN_MASK | AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_MASK |
+		AK98_L2_DMA_REQ_FRAC_DMA_REQ | AK98_L2_DMA_REQ_BUF_REQ_MASK);
+
+	switch (direction) {
+	case MEM2BUF:
+		if (bytes & 0x1)
+			bytes = bytes + 1;	/* Round to even number when read data from external ram */
+		regval |= AK98_L2_DMA_REQ_FRAC_DMA_REQ | AK98_L2_DMA_REQ_FRAC_DMA_DIR_WR |
+			(bufaddr << AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START) |
+			((bytes - 1) << AK98_L2_DMA_REQ_FRAC_DMA_LEN_START);
+		rL2_DMAREQ = regval;
+		break;
+	case BUF2MEM:
+		regval &= ~(AK98_L2_DMA_REQ_FRAC_DMA_DIR_WR);
+		regval |= AK98_L2_DMA_REQ_FRAC_DMA_REQ |
+			(bufaddr << AK98_L2_DMA_REQ_FRAC_DMA_L2_ADDR_START) |
+			((bytes - 1) << AK98_L2_DMA_REQ_FRAC_DMA_LEN_START);
+		rL2_DMAREQ = regval;
+		break;
+	default:
+		BUG();
+	}
+
+	if (intr_enable) {
+		regval = rL2_BUFINTEN;
+		regval |= AK98_L2_DMA_INTR_ENABLE_FRAC_INTR_EN;
+		rL2_BUFINTEN = regval;
+	}
+
+	local_irq_restore(flags);
+}
+
+/**
+ * ak98_l2_get_addr - Get L2 memory start address for given L2 buffer
+ *  @id:		L2 buffer ID
+ *  Return L2 memory start address(Logical/Virtual) (NOT physical address)
+ */
+static u32 ak98_l2_get_addr(u8 id)
+{
+	u32 bufaddr = 0;
+
+	if (id < AK98_L2_UART_BUFFER_INDEX) {	/* L2 common buffer */
+		bufaddr = (u32)AK98_VA_L2MEM + AK98_L2_COMMON_BUFFER_OFFSET +
+			id * AK98_L2_COMMON_BUFFER_LEN;
+	} else if (id < AK98_L2_USB_HOST_BUFFER_INDEX) {	/* UART L2 buffer */
+		bufaddr = (u32)AK98_VA_L2MEM + AK98_L2_UART_BUFFER_OFFSET + 
+			(id - AK98_L2_COMMON_BUFFER_NUM) * AK98_L2_UART_BUFFER_LEN;
+	} else if (id == AK98_L2_USB_HOST_BUFFER_INDEX) {	/* USB Host L2 buffer */
+		bufaddr = (u32)AK98_VA_L2MEM + AK98_L2_USB_HOST_BUFFER_OFFSET;
+	} else if (id < AK98_L2_USB_BUFFER_OFFSET) {	/* USB L2 buffer */
+		bufaddr = (u32)AK98_VA_L2MEM + AK98_L2_USB_BUFFER_OFFSET +
+			(id - AK98_L2_USB_BUFFER_INDEX) * AK98_L2_USB_BUFFER_LEN;
+	} else {
+		printk("ak98-l2: invalid buffer id %d.\n", (int)id);
+	}
+
+	return bufaddr;
+}
+
+/**
+ * ak98_l2_get_dma_param - Calculate l2 buffer big loop/small loop counter value
+ *  @bytes:		L2 buffer ID
+ *  @low:			CNT_cfg (bit[7:0] of DMA Operation Times Configuration Register)
+ *  @high:		CNT_cfg_H (bit[23:16] of DMA Operation Times Configuration Register)
+ *  Return true when correct counter value (high/low) is found, else return false.
+ *
+ *  NOTE: Use a simplified calculation method for L2 buffer 0~7 and 8~15 for bytes > 8KB
+ */
+static bool ak98_l2_get_dma_param(unsigned int bytes, unsigned int *low, unsigned int *high)
+{
+	unsigned int factor;
+	unsigned int dma_times = bytes / AK98_DMA_ONE_SHOT_LEN;
+
+	if (bytes <= 8 * 1024) {
+		*low = dma_times;
+		*high = 0;
+
+		return true;
+	} else if (dma_times & 0x7) {
+		printk("ak98-l2: Invalid L2 DMA buffer size(%u).\n", bytes);
+		return false;
+	}
+
+	factor = 16 * 8;
+
+	while (factor > 0) {
+		if ((dma_times % factor) == 0) {
+			*low = factor;
+			*high = dma_times / factor - 1;
+
+			return (*high < 0xFF) ? true : false;
+		}
+
+		factor -= 8;
+	}
+	
+	return false;
+}
+
+
+/**
+ * ak98_l2_dma - Start data tranferring between memory and l2 buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ */
+static void ak98_l2_dma(unsigned long ram_addr, u8 id, unsigned int bytes,
+	ak98_l2_dma_transfer_direction_t direction, bool intr_enable)
+{
+	unsigned long regid;
+	unsigned long regval;
+	unsigned long flags;
+	unsigned int cnt_low;
+	unsigned int cnt_high;
+
+#if 0
+	printk("%s(): ram_addr=0x%0X, id=%d, bytes=%d, direction=%d, intr_enable=%d.\n",
+		__func__, (unsigned int)ram_addr, id, bytes, direction, intr_enable);
+#endif
+	if (bytes == 0) {
+		printk("ak98-l2: no need to start dma transfer: bytes=0.\n");
+		return ;
+	}
+
+	if (!ak98_l2_get_dma_param(bytes, &cnt_low, &cnt_high)) {
+		printk("ak98-l2: L2 DMA buffer size error: bytes=%d.\n", bytes);
+		return ;
+	}
+	
+	if (ak98_l2_dma_info[id].dma_start || ak98_l2_dma_info[id].dma_frac_start) {
+		printk("ak98-l2: unable to start dma, dma NOT finished, buf id=%d.\n", (int)id);
+		return ;
+	}
+
+	ak98_l2_dma_info[id].dma_op_times = bytes / AK98_DMA_ONE_SHOT_LEN;
+	ak98_l2_dma_info[id].dma_frac_data_len = bytes % AK98_DMA_ONE_SHOT_LEN;
+	ak98_l2_dma_info[id].dma_addr = (void *)ram_addr;
+	ak98_l2_dma_info[id].direction = direction;
+	ak98_l2_dma_info[id].intr_enable = intr_enable;
+	ak98_l2_dma_info[id].need_frac = false;
+
+	if (ak98_l2_dma_info[id].dma_frac_data_len > 0) {
+		ak98_l2_dma_info[id].need_frac = true;
+		ak98_l2_dma_info[id].dma_frac_addr = (void *)(u8 *)ak98_l2_dma_info[id].dma_addr +
+			ak98_l2_dma_info[id].dma_op_times* AK98_DMA_ONE_SHOT_LEN;
+		ak98_l2_dma_info[id].dma_frac_offset = ak98_l2_dma_info[id].dma_op_times;
+	}
+
+	if (ak98_l2_dma_info[id].dma_op_times== 0) {
+		/*
+		 * If DMA transfer size < 64, we start fraction DMA immediately.
+		 */
+		 
+		ak98_l2_dma_info[id].dma_start = false;
+		ak98_l2_dma_info[id].dma_frac_start = true;
+
+		ak98_l2_frac_dma((unsigned long)ak98_l2_dma_info[id].dma_frac_addr, id,
+			ak98_l2_dma_info[id].dma_frac_offset, ak98_l2_dma_info[id].dma_frac_data_len,
+			ak98_l2_dma_info[id].direction, intr_enable);
+		return ;
+	}
+	ak98_l2_dma_info[id].dma_start = true;
+
+	local_irq_save(flags);
+
+	ak98_l2cache_invalidate();
+
+	/*
+	 * Set address of external RAM
+	 */
+	regval = (unsigned long)ak98_l2_dma_info[id].dma_addr;
+	regid = (unsigned long)vL2DMA_ADDRBUF0 + id * 4;
+	__raw_writel(regval, regid);
+
+	/*
+	 * Set DMA operation times
+	 */
+	regid = (unsigned long)vL2DMA_CONBUF0 + id * 4;
+	regval = (cnt_high << 16) | (cnt_low & 0xFF);
+	__raw_writel(regval, regid);
+
+	/*
+	 * Set DMA direction for L2 common buffer
+	 */
+	if (id < AK98_L2_COMMON_BUFFER_NUM) {
+		regval = rL2_CONBUF0_7;
+		if (ak98_l2_dma_info[id].direction == MEM2BUF) {
+			regval |= (1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_DIR_START));;
+		} else {
+			regval &= ~(1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_DIR_START)); 
+		}
+		rL2_CONBUF0_7 = regval;
+	}
+
+	
+	/*
+	 * Start buffer DMA request
+	 */
+	regval = rL2_DMAREQ;
+	regval &= ~(AK98_L2_DMA_REQ_FRAC_DMA_REQ | AK98_L2_DMA_REQ_BUF_REQ_MASK);
+	if (id < AK98_L2_COMMON_BUFFER_NUM) {
+		regval |= (1 << (id + AK98_L2_DMA_REQ_BUF_START));
+	} else {
+		regval |= (1 << ((id - AK98_L2_UART_BUF_START_ID + AK98_L2_UART_BUF_CFG_BUF_START)));
+	}
+	rL2_DMAREQ = regval;
+
+	
+	/*
+	 * Enable DMA interrupt now
+	 */
+	if (intr_enable) {
+		regval = rL2_BUFINTEN;
+		if (id < AK98_L2_COMMON_BUFFER_NUM) {
+			regval |= 1 << (id + AK98_L2_DMA_INTR_ENABLE_BUF_START);
+		} else {
+			regval |= 1 << (id - AK98_L2_COMMON_BUFFER_NUM + AK98_L2_DMA_INTR_ENABLE_UART_BUF_START);
+		}
+		rL2_BUFINTEN = regval;
+	}
+
+	local_irq_restore(flags);
+}
+
+/**
+ * ak98_l2_wait_dma_finish - Wait for L2 DMA to finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak98_l2_dma.
+ */
+static bool ak98_l2_wait_dma_finish(u8 id)
+{
+	unsigned int timeout;
+	unsigned long dmareq;
+	unsigned long dma_bit;
+	const unsigned int max_wait_time = AK98_L2_MAX_DMA_WAIT_TIME;
+
+	timeout = 0;
+	if (ak98_l2_dma_info[id].dma_start) {
+		dma_bit = (id < AK98_L2_COMMON_BUFFER_NUM) ? (1 << (id + AK98_L2_DMA_REQ_BUF_START)) :
+			(1 << (id - AK98_L2_COMMON_BUFFER_NUM + AK98_L2_DMA_REQ_UART_BUF_REQ_START));
+		do {
+			dmareq = rL2_DMAREQ;
+		} while((dmareq & dma_bit) && timeout++ < max_wait_time);
+
+		ak98_l2_dma_info[id].dma_start = false;
+
+		if (timeout >= max_wait_time) {
+			printk("ak98-l2: wait dma timeout, buf id=%d, status=%d.\n", id, ak98_l2_get_status(id));
+			ak98_l2_clear_dma(id);
+			__raw_writel(0x0, vL2DMA_CONBUF0 + id * 4);
+			return false;
+		}
+
+		/*
+		 * If fraction DMA  is NOT need, then everything is done.
+		 */
+		if (!ak98_l2_dma_info[id].need_frac) {
+			return true;
+		}	
+
+
+		/*
+		 * Start fraction DMA here for remain bytes transfer (<64Bytes).
+		 */
+		ak98_l2_dma_info[id].dma_frac_start = true;
+		ak98_l2_frac_dma((unsigned long)ak98_l2_dma_info[id].dma_frac_addr, id,
+			ak98_l2_dma_info[id].dma_frac_offset, ak98_l2_dma_info[id].dma_frac_data_len,
+			ak98_l2_dma_info[id].direction, false);
+
+	}
+
+	/*
+	 * Fraction DMA handling starts here.
+	 */
+	if (ak98_l2_dma_info[id].dma_frac_start) {
+		timeout = 0;
+		do {
+			dmareq = rL2_DMAREQ;
+		} while((dmareq & AK98_L2_DMA_REQ_FRAC_DMA_REQ) && (timeout++ < max_wait_time));
+
+		ak98_l2_dma_info[id].dma_frac_start = false;
+
+		if (timeout >= max_wait_time) {
+			printk("ak98-l2:wait frac dma timeout, buf id=%d, status=%d.\n", id, ak98_l2_get_status(id));
+			return false;
+		}
+
+		if ((ak98_l2_dma_info[id].direction == MEM2BUF) && 
+			(ak98_l2_dma_info[id].dma_frac_data_len < 60)) {
+
+			unsigned int bufaddr;
+
+			bufaddr = ak98_l2_get_addr(id);
+			write_buf(0, bufaddr + (ak98_l2_dma_info[id].dma_frac_offset & 0x1FF) + 60);
+		}
+	}
+
+	return true;
+}
+
+/**
+ * ak98_l2_interrupt_handler - L2 memory interrupt handler
+ *  @irq:	IRQ number for L2 memory (Must be IRQ_L2MEM)
+ *  @dev_id:	Device specific information used by interrupt handler
+ *
+ *  NOTE: Only shared IRQ need to check @irq & @dev_id.
+ *            No need to check them here since L2 memory IRQ is NOT shared IRQ.
+ */
+static irqreturn_t ak98_l2_interrupt_handler(int irq, void *dev_id)
+{
+	unsigned long regval;
+	int i = 0;
+
+	regval = rL2_DMAREQ;
+
+	for (i = 0; i < AK98_L2_COMMON_BUFFER_NUM; i++) {
+		unsigned long dmapending = regval & (1 << ( i + AK98_L2_DMA_REQ_BUF_START));
+
+		if (ak98_l2_dma_info[i].dma_start && !dmapending) {
+			if (!ak98_l2_frac_started && ak98_l2_dma_info[i].need_frac) {
+				ak98_l2_dma_info[i].dma_frac_start = true;
+				ak98_l2_dma_info[i].dma_start = false;
+
+				ak98_l2_frac_dma((unsigned long)ak98_l2_dma_info[i].dma_frac_addr, i,
+					ak98_l2_dma_info[i].dma_frac_offset, ak98_l2_dma_info[i].dma_frac_data_len,
+					ak98_l2_dma_info[i].direction, true);
+
+				ak98_l2_frac_started = true;
+			} else {
+				/* DMA has finished */
+				unsigned long regval;
+
+				regval = rL2_BUFINTEN;
+				regval &= ~(1 << (i + AK98_L2_DMA_INTR_ENABLE_BUF_START));
+				rL2_BUFINTEN = regval;
+
+				ak98_l2_dma_info[i].dma_start = false;
+
+				if (ak98_l2_dma_info[i].callback_func != NULL)
+					ak98_l2_dma_info[i].callback_func(ak98_l2_dma_info[i].data);
+				
+			}
+		}
+
+		if (ak98_l2_dma_info[i].dma_frac_start) {
+			unsigned long frac_dmapending = regval & AK98_L2_DMA_REQ_FRAC_DMA_REQ;
+			if (ak98_l2_frac_started && !frac_dmapending) {
+				ak98_l2_frac_started = false;
+
+				switch (ak98_l2_dma_info[i].direction) {
+				case MEM2BUF:
+					if (ak98_l2_dma_info[i].dma_frac_data_len <= 60)
+						__raw_writel(0x0, AK98_VA_L2MEM + i * 512 + 0x1FC);
+					break;
+				case BUF2MEM:
+					if (ak98_l2_dma_info[i].dma_frac_data_len <= 512 - 4)
+						ak98_l2_clear_dma(i);
+					break;
+				default:
+					BUG();
+				}
+				ak98_l2_dma_info[i].dma_frac_start = false;
+
+				if (ak98_l2_dma_info[i].callback_func != NULL)
+					ak98_l2_dma_info[i].callback_func(ak98_l2_dma_info[i].data);
+				
+			}
+		}
+		
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * ak98_l2_cpu - Transfer data between memory and l2 buffer in CPU mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID
+ *  @buf_offset:	The buffer offset
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ */
+static void ak98_l2_cpu(unsigned long ram_addr, u8 id,
+	unsigned long buf_offset, unsigned int bytes, ak98_l2_dma_transfer_direction_t direction)
+{
+	int i;
+	int j;
+	unsigned long trans_no;
+	unsigned long frac_no;
+	unsigned long buf_count;
+	unsigned long buf_remain;
+	unsigned long temp_ram;
+	unsigned long temp_buf;
+	unsigned long bufaddr;
+	
+	/*
+	 * L2 buffer caller MUST guarantee L2 buffer offset is 4-byte aligned
+	 */
+	if (unlikely(buf_offset % 4))
+		BUG();
+
+	bufaddr = ak98_l2_get_addr(id);
+
+	if (bufaddr == 0) {
+		return ;
+	}
+
+	bufaddr += buf_offset;
+	trans_no = bytes / 4;
+	frac_no = bytes % 4;
+
+	buf_count = (buf_offset + bytes) / AK98_L2_BUF_STATUS_MULTIPLY_RATIO;
+	buf_remain = (buf_offset + bytes) % AK98_L2_BUF_STATUS_MULTIPLY_RATIO;
+
+	switch (direction) {
+	case MEM2BUF:
+		if (ram_addr % 4) {
+			for (i = 0; i < trans_no; i++) {
+				temp_ram = 0;
+				for (j = 0; j < 4; j++)
+					temp_ram |= ((read_ramb(ram_addr + i*4 + j))<<(j*8));
+				write_buf(temp_ram, (bufaddr + i * 4));
+			}
+			if (frac_no) {
+				temp_ram = 0;
+				for (j = 0; j < frac_no; j++)
+					temp_ram |= ((read_ramb(ram_addr + trans_no*4 + j))<<(j*8));
+				write_buf(temp_ram, (bufaddr + trans_no * 4));
+			}
+		} else {
+			for (i = 0; i < trans_no; i++)
+				write_buf(read_raml(ram_addr + i*4), (bufaddr + i*4));
+			if (frac_no)
+				write_buf(read_raml(ram_addr + trans_no*4), (bufaddr + trans_no*4));
+		}
+		
+		/*
+		 * If we do NOT write data to L2 in multiple of 64Bytes, we must write something to the 4Bytes in 64Bytes-
+		 * boundary so that CPU knows writing ends..
+		 */
+		if ((buf_remain > 0) && (buf_remain <= AK98_L2_BUF_STATUS_MULTIPLY_RATIO - 4))
+			write_buf(0, (bufaddr - buf_offset + buf_count*AK98_L2_BUF_STATUS_MULTIPLY_RATIO + AK98_L2_BUF_STATUS_MULTIPLY_RATIO - 4));
+		break;
+	case BUF2MEM:
+		if (ram_addr % 4) {
+			for (i = 0; i < trans_no; i++) {
+				temp_buf = read_buf(bufaddr + i * 4);
+				for (j = 0; j < 4; j++)
+					write_ramb((u8)((temp_buf>>j*8) & 0xFF), (ram_addr + i*4 + j));
+			}
+			if (frac_no) {
+				temp_buf = read_buf(bufaddr+trans_no*4);
+				for (j = 0; j < frac_no; j++)
+					write_ramb((u8)((temp_buf>>j*8) & 0xFF), (ram_addr + trans_no*4 + j));
+			}
+		} else {
+			for (i = 0; i < trans_no; i++)
+				write_raml(read_buf(bufaddr+i*4), (ram_addr+i*4));
+			if (frac_no) {
+				temp_buf = read_buf(bufaddr+trans_no*4);
+				temp_ram = read_raml(ram_addr+trans_no*4);
+				temp_buf &= ((1<<(frac_no*8+1))-1);
+				temp_ram &= ~((1<<(frac_no*8+1))-1);
+				temp_ram |= temp_buf;
+				write_raml(temp_ram, (ram_addr+trans_no*4));
+			}
+		}
+		
+		/*
+		 * If we do NOT read data from L2 in multiple of 64Bytes, we must read the 4Bytes in 64Bytes-
+		 * boundary so that CPU knows reading ends..
+		 */
+		if ((buf_remain > 0) && (buf_remain <= AK98_L2_BUF_STATUS_MULTIPLY_RATIO - 4))
+			temp_buf = read_buf(bufaddr-buf_offset+buf_count*AK98_L2_BUF_STATUS_MULTIPLY_RATIO+AK98_L2_BUF_STATUS_MULTIPLY_RATIO - 4);
+		break;
+	default:
+		BUG();
+	}
+
+}
+
+
+
+/**
+ * ak98_l2_init - Initialize linux kernel L2 memory support
+ */
+void __init ak98_l2_init(void)
+{
+	int i;
+	int retval;
+
+	/*
+	 * Enable L2 controller working clock
+	 */
+	rCLK_CON1 &= ~(1 << 3);
+
+	/*
+	 * Initialize all L2 common buffer status to IDLE(could be allocated)
+	 */
+	for (i = 0; i < AK98_L2_COMMON_BUFFER_NUM; i++) {
+		ak98_l2_buffer_info[i].id = (u8)i;
+		ak98_l2_buffer_info[i].usable = L2_STAT_IDLE;
+		ak98_l2_buffer_info[i].used_time = 0;
+	}
+
+	/* L2 Memory Register initializations */
+	rL2_DMAREQ = AK98_L2_DMA_REQ_EN;
+	rL2_FRACDMAADDR = AK98_L2_FRAC_DMA_AHB_FLAG_EN | AK98_L2_FRAC_DMA_LDMA_FLAG_EN;
+	rL2_CONBUF0_7 = 0x0;
+	rL2_CONBUF8_15 = AK98_L2_UART_BUF_CFG_UART_EN_MASK | AK98_L2_UART_BUF_CFG_UART_CLR_MASK;
+	rL2_BUFINTEN = 0x0;
+	rL2_BUFASSIGN1 = 0x0;
+	rL2_BUFASSIGN2 = 0x0;
+
+	/* Initialize L2 DMA information status */
+	memset(ak98_l2_dma_info, 0, ARRAY_SIZE(ak98_l2_dma_info));
+
+	/* Initialize global L2 fraction DMA start flag */
+	ak98_l2_frac_started = false;
+
+	init_waitqueue_head(&l2_wq);
+
+	/* L2 Memory Interrupt handler registered */
+	if ((retval = request_irq(IRQ_L2MEM, &ak98_l2_interrupt_handler, IRQF_DISABLED, "ak98-l2", NULL)) < 0)
+		printk(KERN_ERR "ak98-l2: failed to request_irq, irq number: %d, retval=%d.\n", IRQ_L2MEM, retval);
+
+	printk("AK98xx: L2 memory support initialized\n");
+}
+
+/**
+ * ak98_l2_alloc - Allocate a common L2 buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak98_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ */
+u8 ak98_l2_alloc(ak98_l2_device_t device)
+{
+	int i;
+	u16 used_times = MAX_L2_BUFFER_USED_TIMES;
+	u8 id = BUF_NULL;
+	u8 first_id = BUF_NULL;
+	unsigned long flags;
+	bool l2_allocated = false;
+
+	if (unlikely(device == ADDR_RESERVED)) {
+		printk("ak98_l2: unable to allocate l2 buffer for reserved device.\n");
+		
+		return BUF_NULL;
+	}
+
+	if (unlikely(ak98_l2_device_info[(u8)device].id != BUF_NULL)) {
+		printk("ak98_l2: device %d already have a l2 buffer %d\n",
+			(int)(u8)device, (int)(u8)ak98_l2_device_info[(u8)device].id);
+		
+		return ak98_l2_device_info[(u8)device].id;
+	}
+
+	do {
+		local_irq_save(flags);
+
+		l2_allocated = false;
+
+		for (i = 1; i < AK98_L2_COMMON_BUFFER_NUM; i++) {
+			if (ak98_l2_buffer_info[i].usable == L2_STAT_IDLE) {
+				if (first_id == BUF_NULL) {
+					first_id = ak98_l2_buffer_info[i].id;
+					used_times = ak98_l2_buffer_info[i].used_time;
+					id = first_id;
+				}
+				if (ak98_l2_buffer_info[i].used_time < used_times) {
+					used_times = ak98_l2_buffer_info[i].used_time;
+					id = ak98_l2_buffer_info[i].id;
+				}
+			}
+		}
+
+		if (unlikely(first_id == BUF_NULL)) {
+			local_irq_restore(flags);
+			l2_wait = 0;
+			wait_event(l2_wq, l2_wait);
+		} else {
+			l2_allocated = true;
+		}
+	} while (!l2_allocated);
+
+	/*
+	 * Got a L2 buffer successfully...
+	 */
+	ak98_l2_buffer_info[id].usable = L2_STAT_USED;
+	ak98_l2_buffer_info[id].used_time++;
+	if (ak98_l2_buffer_info[id].used_time == 0) {
+		/*
+		 * In case when the new allocated L2 buffer has been used MAX_L2_BUFFER_USED_TIMES,
+		 * we just clear all L2 buffer used times as a simpfied method of balancing 8 L2 buffer usage.
+		 */
+		for (i = 0; i < AK98_L2_COMMON_BUFFER_NUM; i++)
+			ak98_l2_buffer_info[i].used_time = 0;
+	}
+
+	/* Enable L2 buffer */
+	ak98_l2_combuf_ctrl(id, true);
+
+	/* Change device info */
+	ak98_l2_device_info[device].id = id;
+
+	/* Select L2 common buffer for device */
+	ak98_l2_select_combuf(device, id);
+
+	local_irq_restore(flags);
+
+	/* Clear L2 buffer status */
+	ak98_l2_clr_status(id);
+
+	return id;
+}
+EXPORT_SYMBOL(ak98_l2_alloc);
+
+/**
+ * ak98_l2_free - Free L2 common buffer for given device
+ *  @device:	Device ID which need common L2 buffer
+ *  Return L2 buffer ID (0 ~ 7)
+ *
+ *  Only common L2 buffers(ID 0 ~ 7) could be allocated by ak98_l2_alloc.
+ *  Other L2 buffers (UART/USB used) is handled by corresponding devices directly.
+ *  NOTE: Return the previous L2 buffer ID if a L2 buffer has been allocated to the device.
+ *            This means one device could get only one L2 buffer maximum.
+ */
+void ak98_l2_free(ak98_l2_device_t device)
+{
+	u8 id;
+	unsigned long regval;
+	unsigned long flags;
+
+	id = ak98_l2_device_info[(u8)device].id;
+	if (unlikely(id == BUF_NULL)) {
+		printk("ak98-l2: trying to free invalid buffer id %d\n", (int)id);
+		return ;
+	}
+
+	ak98_l2_clear_dma(id);
+
+	local_irq_save(flags);
+
+	/*
+	 * Disable DMA interrupt of this L2 buffer.
+	 */
+	regval = rL2_BUFINTEN;
+	regval &= ~(1 << (id + AK98_L2_DMA_INTR_ENABLE_BUF_START));
+	rL2_BUFINTEN = regval;
+
+	/* Set DMA count to 0 */
+	__raw_writel(0x0, vL2DMA_CONBUF0 + id * 4);
+
+	/* Disable this L2 buffer */
+	ak98_l2_combuf_ctrl(id, false);
+
+	/* Clear DMA & DMA fraction flags */
+	if (ak98_l2_dma_info[id].dma_start || ak98_l2_dma_info[id].dma_frac_start) {
+		ak98_l2_dma_info[id].dma_start = false;
+		ak98_l2_dma_info[id].dma_frac_start = false;
+	}
+
+	ak98_l2_dma_info[id].callback_func = NULL;
+	ak98_l2_dma_info[id].data = 0;
+
+	ak98_l2_device_info[(u8)device].id = BUF_NULL;
+	ak98_l2_buffer_info[id].usable = L2_STAT_IDLE;
+
+	l2_wait = 1;
+	wake_up(&l2_wq);
+	
+	local_irq_restore(flags);
+
+}
+EXPORT_SYMBOL(ak98_l2_free);
+
+/**
+ * ak98_l2_set_dma_callback - Set callback function when L2 DMA/fraction DMA interrupt handler is done
+ *  @id:	L2 buffer ID
+ *  @func:	Callback function
+ *  Return true(Always)
+ *  
+ *  NOTE: Caller MUST guarantee that L2 buffer ID is valid. And since the callback function is called
+ *  in interrupt handler, it MUST NOT call any functions which may sleep.
+ */
+bool ak98_l2_set_dma_callback(u8 id, ak98_l2_callback_func_t func, unsigned long data)
+{
+	if (unlikely(id >= AK98_L2_COMMON_BUFFER_NUM)) {
+		printk(KERN_ERR "ak98-l2: Set dma callback, invalid buf id[%d].\n", id);
+		return false;
+	}
+
+	if (unlikely(ak98_l2_dma_info[id].dma_start || ak98_l2_dma_info[id].dma_frac_start)) {
+		printk(KERN_ERR "ak98-l2: Set dma callback, dma not finished.\n");
+		return false;
+	}
+
+	ak98_l2_dma_info[id].callback_func = func;
+	ak98_l2_dma_info[id].data = data;
+
+	return true;
+}
+EXPORT_SYMBOL(ak98_l2_set_dma_callback);
+
+/**
+ * ak98_l2_combuf_dma - Start data tranferring between memory and l2 common buffer in DMA mode
+ *  @ram_addr:		External RAM address(Physical)
+ *  @id:		L2 buffer ID involved in DMA transfer
+ *  @bytes:		Data transfer size
+ *  @direction:		Data transfer direction between L2 memory and external RAM 
+ *  @intr_enable:	Open interrupt for this L2 buffer or not
+ */
+void ak98_l2_combuf_dma(unsigned long ram_addr, u8 id, unsigned int bytes, ak98_l2_dma_transfer_direction_t direction, bool intr_enable)
+{
+	if (unlikely(id >= AK98_L2_COMMON_BUFFER_NUM)) {
+		printk("ak98-l2: begin common buffer dma, error buf id=[%d].\n", id);
+		return ;
+	}
+
+	ak98_l2_dma(ram_addr, id, bytes, direction, intr_enable);
+}
+EXPORT_SYMBOL(ak98_l2_combuf_dma);
+
+/**
+ * ak98_l2_combuf_wait_dma_finish - Wait for L2 DMA to finish
+ *  @id:	L2 buffer ID involved in DMA transfer
+ *  Return true: DMA transfer finished successfully.
+ *            false: DMA transfer failed.
+ *  NOTE: DMA transfer is started by ak98_l2_combuf_dma.
+ */
+bool ak98_l2_combuf_wait_dma_finish(u8 id)
+{
+	if (unlikely(id >= AK98_L2_COMMON_BUFFER_NUM)) {
+		printk("ak98-l2: begin common buffer dma, error buf id=[%d].\n", id);
+		return false;
+	}
+	return ak98_l2_wait_dma_finish(id);
+}
+EXPORT_SYMBOL(ak98_l2_combuf_wait_dma_finish);
+
+/**
+ * ak98_l2_combuf_cpu - Transfer data between memory and l2 common buffer in CPU mode
+ *  @ram_addr:	External RAM address(Physical)
+ *  @id:	L2 buffer ID
+ *  @bytes:	Data transfer size
+ *  @direction:	Data transfer direction between L2 memory and external RAM
+ *
+ *  NOTE: According to XuChang, if one transfer data from Peripheral --> L2 Buffer --> RAM, 
+ *            special care need to be taken when data size is NOT multiple of 64Bytes.
+ *            Pheripheral driver must check hardware signals to confirm data has been transfer from
+ *            peripheral to L2 buffer since L2 do NOT provide some mechanism to confirm data has
+ *            been in L2 Buffer. Driver can and only can call ak98_l2_combuf_cpu() to copy data from L2
+ *            Buffer --> RAM after checking hardware signals.
+ *            As to 64Bytes * n size data, L2 could check Buffer Status Status Counter to confirm that
+ *            Data has been transfer from peripheral to L2 buffer, so no hardware signals checking needed.
+ */
+void ak98_l2_combuf_cpu(unsigned long ram_addr, u8 id,
+	unsigned int bytes, ak98_l2_dma_transfer_direction_t direction)
+{
+	int i;
+	int loop;
+	int remain;
+
+	loop = bytes / AK98_L2_BUF_STATUS_MULTIPLY_RATIO;
+	remain = bytes % AK98_L2_BUF_STATUS_MULTIPLY_RATIO;
+
+	switch (direction) {
+	case MEM2BUF:
+		for (i = 0; i < loop; i++) {
+			
+			while (ak98_l2_get_status(id) == (AK98_L2_BUFFER_SIZE / AK98_L2_BUF_STATUS_MULTIPLY_RATIO))
+				;	/* Waiting for L2 buffer to NOT full(means writable) */
+			
+			ak98_l2_cpu(ram_addr + i * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(i % 8) * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, AK98_L2_BUF_STATUS_MULTIPLY_RATIO, direction);
+		}
+		if (remain > 0) {
+			while (ak98_l2_get_status(id) > 0)
+				;	/* Waiting for L2 buffer to empty */
+
+			ak98_l2_cpu(ram_addr + loop * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(loop % 8) * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, remain, direction);
+		}
+		break;
+	case BUF2MEM:
+		for (i = 0; i < loop; i++) {
+			while (ak98_l2_get_status(id) == 0)
+				;	/* Waiting for L2 buffer to be not empty (means readable) */
+			
+			ak98_l2_cpu(ram_addr + i * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(i % 8) * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, AK98_L2_BUF_STATUS_MULTIPLY_RATIO, direction);
+			
+		}
+		if (remain > 0) {
+			ak98_l2_cpu(ram_addr + loop * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, id,
+				(loop % 8) * AK98_L2_BUF_STATUS_MULTIPLY_RATIO, remain, direction);
+		}
+		break;
+	default:
+		BUG();
+	}
+}
+EXPORT_SYMBOL(ak98_l2_combuf_cpu);
+
+/**
+ * ak98_l2_get_status - Get L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+u8 ak98_l2_get_status(u8 id)
+{
+	ak98_l2_assert_buf_id(id);
+
+	return (id < AK98_L2_COMMON_BUFFER_NUM) ? (rL2_BUFSTAT1 >> (id * 4)) & 0xF :
+		(rL2_BUFSTAT2 >> ((id - AK98_L2_UART_BUF_START_ID) << 1)) & 0x3;
+}
+EXPORT_SYMBOL(ak98_l2_get_status);
+
+/**
+ * ak98_l2_clr_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ */
+void ak98_l2_clr_status(u8 id)
+{
+	unsigned long flags;
+
+	ak98_l2_assert_buf_id(id);
+	
+	local_irq_save(flags);
+
+	if (id < AK98_L2_COMMON_BUFFER_NUM) {
+		rL2_CONBUF0_7 |= 1 << (id + AK98_L2_COMMON_BUF_CFG_BUF_CLR_START);
+	} else {
+		rL2_CONBUF8_15 |= (1 << (id - AK98_L2_UART_BUF_START_ID + AK98_L2_UART_BUF_CFG_BUF_START));
+	}
+
+	local_irq_restore(flags);
+
+}
+EXPORT_SYMBOL(ak98_l2_clr_status);
+
+/**
+ * ak98_l2_set_status - Clear L2 buffer status
+ *  @id:	L2 buffer ID
+ *  @status:	Status to be set (0 ~ 8)
+ */
+void ak98_l2_set_status(u8 id, u8 status)
+{
+	unsigned long regval;
+	unsigned long flags;
+	
+	ak98_l2_assert_buf_id(id);
+
+	if ((id >= AK98_L2_COMMON_BUFFER_NUM) || status > MAX_L2_DMA_STATUS_VALUE)
+		BUG();
+
+	local_irq_save(flags);
+
+	/*
+	 * Enable CPU-controlled buffer function and set L2 buffer `id' status
+	 * status = current number of data in the CPU controlled buffer.
+	 */
+	regval = rL2_CONBUF8_15;
+	regval &= ~(AK98_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK | AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK);
+	regval |= (id << AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_START) | AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		(status << AK98_L2_UART_BUF_CFG_CPU_BUF_NUM_START);
+	rL2_CONBUF8_15 = regval;
+
+	/*
+	* Disable CPU-controlled buffer function
+	*/
+	regval = rL2_CONBUF8_15;
+	regval &= ~(AK98_l2_UART_BUF_CFG_CPU_BUF_NUM_MASK | AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_EN |
+		AK98_L2_UART_BUF_CFG_CPU_BUF_SEL_MASK);
+	rL2_CONBUF8_15 = regval;
+
+	local_irq_restore(flags);
+
+}
+EXPORT_SYMBOL(ak98_l2_set_status);
diff --git a/arch/arm/mach-ak98/l2_exebuf.c b/arch/arm/mach-ak98/l2_exebuf.c
new file mode 100644
index 00000000000..ba945a67c41
--- /dev/null
+++ b/arch/arm/mach-ak98/l2_exebuf.c
@@ -0,0 +1,72 @@
+/*
+ * arch/arm/mach-ak98/l2_exebuf.c
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <mach/regs-l2.h>
+#include <mach/l2_exebuf.h>
+
+// #define PM_DEBUG
+#define L2_BUFFER0_SIZE		512
+
+void (*jumpto_L2)(unsigned long param1,unsigned long param2,
+					unsigned long param3,unsigned long param4);
+
+#ifdef PM_DEBUG
+static void pm_printf(const char *start, int len)
+{
+	int i;
+	unsigned char local_l2mem[L2_BUFFER0_SIZE] = {0} ;
+
+	printk("start = %p, len = %d\n", start, len);
+	for (i = 0; i < len; i += 4) {
+		*(unsigned long *)(local_l2mem + i) = 
+			*(volatile unsigned long *)(AK98_VA_L2MEM + i);
+	}
+	for (i = 0; i < len; i++) {
+		printk(" 0x%02x", local_l2mem[i]);	
+		if (i % 16 == 15) printk("\n");
+	}
+}
+#endif
+
+/*
+ * copy from ddr2 to l2 memory to run, and exit standby
+ */
+int l2_exec_buf(const char *vaddr, int len, unsigned long param1,
+unsigned long param2,unsigned long param3,unsigned long param4)
+{
+	unsigned long i, flags ;
+
+    //disable ARM interrupt
+    local_irq_save(flags);
+
+	memset((void *)AK98_VA_L2MEM, 0, L2_BUFFER0_SIZE);
+	
+	//copy from ddr2 to l2 memory
+	for (i = 0; i < len; i += 4) {
+		*(volatile unsigned long *)(AK98_VA_L2MEM + i) = 
+			*(unsigned long *)(vaddr + i);
+	}
+#ifdef PM_DEBUG
+	pm_printf(vaddr, len);
+#endif
+
+	REG32(AK98_VA_L2CTRL + 0x84) &= ~(1 << 29);
+
+	//jumpto_L2 run
+	jumpto_L2 = (void *)(AK98_VA_L2MEM);
+	jumpto_L2(param1,param2,param3,param4);
+
+	REG32(AK98_VA_L2CTRL + 0x84) |= (1 << 29);
+	
+	//enable ARM interrupt
+	local_irq_restore(flags);
+	return 0;
+}
+
+
diff --git a/arch/arm/mach-ak98/l2cache.c b/arch/arm/mach-ak98/l2cache.c
new file mode 100644
index 00000000000..390fd34bb6f
--- /dev/null
+++ b/arch/arm/mach-ak98/l2cache.c
@@ -0,0 +1,192 @@
+/*
+ * linux/arch/arm/mach-ak98/l2cache.c
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/stddef.h>
+#include <linux/irq.h>
+ 
+#include <asm/dma.h>
+#include <asm/sizes.h>
+#include <asm/setup.h>
+
+#include <mach/l2cache.h>
+
+
+#ifdef AK98_L2CACHE_ENABLE
+
+static DEFINE_SPINLOCK(l2cache_lock);
+
+
+#define L2_CACHE_CFG_REG	REG_VA_VAL(AK98_VA_L2CACH, 0x00)
+#define L2_CACHE_SECTION0_START	REG_VA_VAL(AK98_VA_L2CACH, 0x10)
+#define L2_CACHE_SECTION0_END	REG_VA_VAL(AK98_VA_L2CACH, 0x14)
+#define L2_CACHE_SECTION7_END	REG_VA_VAL(AK98_VA_L2CACH, 0x84)
+
+void ak98_l2cache_init(void)
+{
+	volatile int i;
+	unsigned long start_addr;
+	unsigned long end_addr;
+
+	if (meminfo.nr_banks == 0) {
+		printk("Fatal error: NO memory banks defined!\n");
+		BUG();
+	}
+
+	if (meminfo.nr_banks > 1)
+		printk("Warning: memory banks != 1, mapping only first bank for L2 cache\n");
+
+	start_addr = meminfo.bank[0].start;
+	end_addr = start_addr + meminfo.bank[0].size;
+	
+	/* Enable L2 Cache Invalidation */
+	L2_CACHE_CFG_REG |= (1 << 26) | (1 << 27);
+
+	/* Wait for L2 Cache for initialization */
+	while (L2_CACHE_CFG_REG & (1 << 25))
+		;
+
+	/* Invalidation finished */
+	L2_CACHE_CFG_REG &= ~((1 << 26) | (1 << 27));
+
+	/* Wait for enough clock cycles */
+	for (i = 0; i < 3000; i++)
+		;
+
+	/* Disable all 8 L2 cache sections */
+	L2_CACHE_CFG_REG &= ~(0xFF);
+
+	/*
+	 * Configure the first section to map whole RAM
+	 * Start address: Low 14bits must be 0
+	 * End address: Low 14bits must be 1
+	 */
+	printk("Mapping RAM region 0x%lx - 0x%lx to L2 cache section 0\n",
+		start_addr, end_addr);
+	L2_CACHE_SECTION0_START = start_addr & 0xFFFFC000;
+	L2_CACHE_SECTION0_END = (end_addr - 1) | 0x3FFF;
+
+	/* Enable L2 cache section 0 */
+	L2_CACHE_CFG_REG |= (1 << 0);
+
+	/*
+	 * AK9805 V3 & up:
+	 *   Force L2 Cache rready3 == 0 to resolve data abort error
+	 * NOTE: Do *NOT* affect AK9801 & other version CPU
+	 */
+	L2_CACHE_SECTION7_END |= 1;
+}
+EXPORT_SYMBOL(ak98_l2cache_init);
+
+void ak98_l2cache_clean_finish(void)
+{
+	int count = 0;
+	unsigned long regval;
+	volatile int i;
+	unsigned long flags;
+	
+	spin_lock_irqsave(&l2cache_lock, flags);
+
+	/*
+	 * Wait for AHB1-4 channel to be free
+	 */
+	do {
+		regval = L2_CACHE_CFG_REG;
+	} while ((((regval >> 16) & 0xF) || ((regval >> 24) & 0x1)) & (count++ < 3000));
+	
+	if (count >= 3000) {
+		printk("Failed to clean and finish L2 cache!!\n");
+		BUG();
+	}
+
+	for (i = 0; i < 100; i++)
+		;
+	
+	spin_unlock_irqrestore(&l2cache_lock, flags);
+
+}
+EXPORT_SYMBOL(ak98_l2cache_clean_finish);
+
+void ak98_l2cache_invalidate(void)
+{
+	/*
+	 * Assume that we only use Section 0 of L2 Cache to map whole RAM, modify the following code
+	 * when the assumption is broken.
+	 */
+
+	volatile int i;
+	unsigned long flags;
+
+	spin_lock_irqsave(&l2cache_lock, flags);
+
+	/*
+	 * Disable L2 Cache Section 0
+	 */
+	L2_CACHE_CFG_REG &= ~(1 << 0);
+
+	/*
+	 * Clear all L2 entries & the read line buffer between CPU and external RAM for non-L2 section.
+	 * That is, invalidate L2 Cache.
+	 */
+	L2_CACHE_CFG_REG |= (1 << 26) | (1 << 27);
+
+	/*
+	 * Wait until L2 Cache initialization finished.
+	 */
+	while (L2_CACHE_CFG_REG & (1 << 25))
+		;
+	/*
+	 * L2 invalidate finished.
+	 */
+	L2_CACHE_CFG_REG &= ~((1 << 26) | (1 << 27));
+
+	/*
+	 * Delay for a relative long time (> 128 clocks) for all AHB Channel of RAM Controller
+	 * free and +128 clocks
+	 */
+	for (i = 0; i < 30; i++)
+		;
+
+	/*
+	 * Enable L2 Cache Section 0
+	 */
+	L2_CACHE_CFG_REG |= (1 << 0);
+
+	spin_unlock_irqrestore(&l2cache_lock, flags);
+	
+	return ;
+}
+EXPORT_SYMBOL(ak98_l2cache_invalidate);
+
+#else	/*  !AK98_L2CACHE_ENABLE */
+
+void ak98_l2cache_init(void)
+{
+}
+EXPORT_SYMBOL(ak98_l2cache_init);
+
+void ak98_l2cache_clean_finish(void)
+{
+}
+EXPORT_SYMBOL(ak98_l2cache_clean_finish);
+
+void ak98_l2cache_invalidate(void)
+{
+}
+EXPORT_SYMBOL(ak98_l2cache_invalidate);
+
+#endif	/*  AK98_L2CACHE_ENABLE */
diff --git a/arch/arm/mach-ak98/l2mem.c b/arch/arm/mach-ak98/l2mem.c
new file mode 100644
index 00000000000..8b137891791
--- /dev/null
+++ b/arch/arm/mach-ak98/l2mem.c
@@ -0,0 +1 @@
+
diff --git a/arch/arm/mach-ak98/mach-athena.c b/arch/arm/mach-ak98/mach-athena.c
new file mode 100755
index 00000000000..001b52d3149
--- /dev/null
+++ b/arch/arm/mach-ak98/mach-athena.c
@@ -0,0 +1,1109 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/input/ak98matrix_keypad.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/mxc622x.h>
+#include <linux/mmc328x.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/nand.h>
+#include <mach/ts.h>
+#include <mach/spi.h>
+#include <mach/gpio.h>
+#include <mach/reset.h>
+#include <mach/devices.h>
+#include <mach/ak98_mci.h>
+#include <mach/bat.h>
+#include <mach/ak_sensor.h>
+
+#include <linux/fb.h>
+#include <video/anyka_lcdc.h>
+
+#include <mach/map.h>
+#include <mach/lib_lcd.h>
+#include <mach/rtc.h>
+#include <linux/delay.h>
+
+#include <linux/i2c/cp2007.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/ak98_hal.h>
+#include <mach/l2.h>
+#include <mach/regs-comm.h>
+#include <mach/pwm.h>
+#include <mach/wifi.h>
+#include <mach/clock.h>
+#include <mach/gpio_keys.h>
+#include <linux/i2c/aw9523.h>
+#include <media/soc_camera.h>
+#include <media/hi253.h>
+#include <media/ov772x.h>
+
+
+
+#include "cpu.h"
+#include "irq.h"
+
+
+  	#define DBG_UART_ID  0
+	#define LCD_TFT      0
+
+void (*ak98_arch_reset)(void);
+
+/*
+ * LCD Controller
+ */
+//#if defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+#if defined(CONFIG_FB_AK98) || defined(CONFIG_FB_AK98_DEBUG)
+static struct fb_videomode ak98_tft_vga_modes[] = {
+	{
+ 	 .name = "HSD070IDW1-A10",
+	 .refresh = 60,
+	 .xres = 800,.yres = 480,
+	 .pixclock = 30000000,
+
+	 .left_margin = 40,.right_margin = 170,
+	 .upper_margin = 29,.lower_margin = 40,
+	 .hsync_len = 48,.vsync_len = 4,
+
+	 .sync = 0,
+	 .vmode = FB_VMODE_NONINTERLACED,
+	 },
+
+	{
+	 .name = "Q07021-701",
+	 .refresh = 60,
+	 .xres = 800,.yres = 600,
+ 	 .pixclock = 40000000,
+
+	 .left_margin = 88,.right_margin = 112,
+	 .upper_margin = 39,.lower_margin = 21,
+	 .hsync_len = 48,.vsync_len = 3,
+
+	 .sync = 0,
+	 .vmode = FB_VMODE_NONINTERLACED,
+	 },
+
+};
+
+static struct fb_monspecs ak98fb_default_monspecs = {
+	.manufacturer = "HIT",
+	.monitor = "TX09D70VM1CCA",
+
+	.modedb = &ak98_tft_vga_modes[LCD_TFT],
+	.modedb_len = ARRAY_SIZE(ak98_tft_vga_modes),
+	.hfmin = 15000,
+	.hfmax = 64000,
+	.vfmin = 50,
+	.vfmax = 150,
+};
+
+static void ak98_lcdc_power_control(int on)
+{
+
+#if 1
+	if (on)
+		//open LCD controller clock
+		AKCLR_BITS(1UL << 3, rCLK_CON1);	//0x0800000C
+	else
+		//close LCD controller clock
+		AKSET_BITS(1UL << 3, rCLK_CON1);	//0x0800000C
+
+	//panel power on
+	bsplcd_set_panel_power(on);	//pullup TFT_VGH_L and TFT_AVDD
+
+	//panel backlight
+	baselcd_set_panel_backlight(on);	//will clear memory after memory setting
+
+	printk("ak98_lcdc_power_control(%d)\n", on);
+
+#endif
+
+}
+
+/* Driver datas */
+static struct anyka_lcdfb_info __initdata ak98_lcdc_data = {
+	.lcdcon_is_backlight = true,
+	.default_bpp = 16,
+	//.default_dmacon                       = ANYKA_LCDC_DMAEN,
+	//.default_lcdcon2              = AK88_DEFAULT_LCDCON2,
+	.default_monspecs = &ak98fb_default_monspecs,
+	.anyka_lcdfb_power_control = ak98_lcdc_power_control,
+	.guard_time = 1,
+	//if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_RGB) {
+	.lcd_wiring_mode = ANYKA_LCDC_WIRING_RGB,	//RGB:565 mode
+};
+
+#else
+static struct anyka_lcdfb_info __initdata ak98_lcdc_data;
+#endif				//for defined(CONFIG_FB_ANYKA) || defined(CONFIG_FB_ANYKA_MODULE)
+
+
+/* NAND parititon */
+/* for each block=512K */
+static struct mtd_partition athena_evt_nand_part[] = {
+[0] = {
+		.name = "Bootloader",
+		.size = SZ_512K,                 // 0 to 0
+		.offset = 0,
+		.mask_flags = MTD_WRITEABLE,
+       },
+[1] = {
+		.name = "SYS",
+		.size = SZ_256M , 			
+ 		.offset = MTDPART_OFS_APPEND,
+ 		},
+[2] = {
+		.name = "DATA",
+ 		.size = SZ_256M  , 		
+   		.offset = MTDPART_OFS_APPEND,
+ 		},
+[3] = {
+		.name = "TEST",
+ 		.size = SZ_256M ,  		
+  		.offset = MTDPART_OFS_APPEND,
+		},
+[4] = {
+		.name = "GUI",              
+		.size = MTDPART_SIZ_FULL,        
+		.offset = MTDPART_OFS_APPEND,
+		}
+};
+
+static struct ak98_nand_set athena_evt_nand_sets[] = {
+	[0] = {
+	       .name = "NAND",
+	       .nr_chips = 1,
+	       .nr_partitions = ARRAY_SIZE(athena_evt_nand_part),
+	       .partitions = athena_evt_nand_part,
+	      // .cmd_len = 0xF5BD1,	//0x93791
+	       .cmd_len = 0xF5AD1,
+	       .data_len = 0xF5C5C,	//0x91517
+	      // .data_len = 0x91717,
+	       }
+};
+
+static struct ak98_platform_nand athena_evt_nand_info = {
+	.nr_sets = ARRAY_SIZE(athena_evt_nand_sets),
+	.sets = athena_evt_nand_sets,
+};
+
+/*
+ * AK98 matrix Keyboard Device
+ */
+#define KEY_CENTER	KEY_REPLY
+static const uint32_t athena_keypad_keymap[] = {
+	KEY(0, 0, KEY_VOLUMEUP),
+	KEY(0, 1, KEY_RIGHT),
+	KEY(0, 2, KEY_MENU),
+	KEY(1, 0, KEY_UP),
+	KEY(1, 1, KEY_CENTER),
+	KEY(1, 2, KEY_DOWN),
+	KEY(2, 0, KEY_VOLUMEDOWN),
+	KEY(2, 1, KEY_LEFT),
+	KEY(2, 2, KEY_HOME),
+};
+
+static struct matrix_keymap_data athena_keypad_keymap_data = {
+	.keymap		= athena_keypad_keymap,
+	.keymap_size	= ARRAY_SIZE(athena_keypad_keymap),
+};
+
+/*
+{ AK98_GPIO_106, AK98_GPIO_107, AK98_GPIO_109 };
+{ AK98_GPIO_2, AK98_GPIO_3, AK98_GPIO_4 };
+
+*/
+static const int athena_keypad_row_gpios[] = 
+	//{ AW9523_GPIO_P00, AW9523_GPIO_P01, AW9523_GPIO_P02 };
+	{ AK98_GPIO_106, AK98_GPIO_107, AK98_GPIO_109 };
+static const int athena_keypad_col_gpios[] = 
+	//{ AW9523_GPIO_P11, AW9523_GPIO_P12, AW9523_GPIO_P13 };
+	{ AK98_GPIO_2, AK98_GPIO_3, AK98_GPIO_4 };
+
+static struct matrix_keypad_platform_data athena_keypad_pdata = {
+	.keymap_data	= &athena_keypad_keymap_data,
+	.row_gpios		= athena_keypad_row_gpios,
+	.col_gpios		= athena_keypad_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(athena_keypad_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(athena_keypad_col_gpios),
+	.col_scan_delay_us	= 10,
+	.debounce_ms		= 30,
+	.active_low		= 1,
+	.wakeup			= 0,
+	.row_gpios_cfginfo = {
+				.pin 		= -1,
+				.pulldown	= -1,
+				.pullup		= -1,
+				.dir		= AK98_GPIO_DIR_INPUT,
+				.value		= -1,
+				.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+		},
+	.col_gpios_cfginfo = {
+				.pin		= -1,
+				.pulldown	= -1,
+				.pullup		= -1,
+				.dir 		= AK98_GPIO_DIR_OUTPUT,
+				.value		= AK98_GPIO_OUT_LOW, /* default state of output gpios*/
+				.int_pol	= -1,
+		},
+	.grounding		= false, /* grounding line should be the end line*/
+};
+
+static struct platform_device athena_keypad_device = {
+	.name		= "matrix-keypad",
+	.id		= -1,
+	.dev		= {
+		.platform_data = &athena_keypad_pdata,
+	},
+};
+
+
+
+
+/*
+ * GPIO Buttons
+ */
+static struct ak98_gpio_keys_button athena_buttons[] = {
+	{			
+		.code		= KEY_ESC,
+		.gpio		= AK98_GPIO_73,
+		.active_low	= 0,
+		.desc		= "btn_ESC",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	{			
+		.code		= KEY_PAGEUP,
+		.gpio		= AK98_GPIO_72,
+		.active_low	= 0,
+		.desc		= "btn_PAGEUP",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	{			
+		.code		= KEY_PAGEDOWN,
+		.gpio		= AK98_GPIO_74,
+		.active_low	= 0,
+		.desc		= "btn_PAGEDOWN",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	{	
+		.code		= KEY_MENU,
+		.gpio		= AK98_GPIO_104,
+		.active_low	= 0,
+		.desc		= "btn_Menu",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+		.pullup		= -1,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	{	
+		.code		= KEY_POWER,
+		.gpio		= AK98_GPIO_7,
+		.active_low	= 1,
+		.desc		= "btn_powerdown",
+		.debounce_interval = 30,
+		.wakeup		= 1,
+		.pulldown	= AK98_PULLDOWN_DISABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+	},
+	
+};
+
+static struct ak98_gpio_keys_platform_data athena_button_data = {
+	.buttons	= athena_buttons,
+	.nbuttons	= ARRAY_SIZE(athena_buttons),
+};
+
+	
+static struct platform_device athena_button_device = {
+	.name		= "gpio_keys",
+	.id			= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &athena_button_data,
+	}
+};
+
+/* MMC/SD */
+
+#ifdef CONFIG_FOUR_DATA_LINE
+struct ak98_mci_platform_data mci_plat_data = {
+	.gpio_cd  = AK98_GPIO_75,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource ak98_mmc_resource[] = {
+	[0] = {
+		.start = 0x20020000,
+		.end = 0x20020000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC_SD,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+#elif defined CONFIG_EIGHT_DATA_LINE
+struct ak98_mci_platform_data mci_plat_data = {
+	.gpio_cd  = AK98_GPIO_75,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource ak98_mmc_resource[] = {
+	[0] = {
+		.start = 0x20020000,
+		.end = 0x20020000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC_SD,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+#else
+struct ak98_mci_platform_data mci_plat_data = {
+
+};
+
+static struct resource ak98_mmc_resource[] = {
+
+};
+#endif
+
+struct platform_device ak98_mmc_device = {
+	.name = "ak98_mci",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_mmc_resource),
+	.resource = ak98_mmc_resource,
+	.dev = {
+		.platform_data = &mci_plat_data,
+	},
+};
+
+
+/* SDIO */
+struct ak98_mci_platform_data sdio_plat_data = {
+	.gpio_cd  = AK98_GPIO_18,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource ak98_sdio_resource[] = {
+	[0] = {
+		.start = 0x20021000,
+		.end = 0x20021000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SDIO,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ak98_sdio_device = {
+	.name = "ak98_sdio",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_sdio_resource),
+	.resource = ak98_sdio_resource,
+	.dev = {
+		.platform_data = &sdio_plat_data,
+	},
+};
+
+static int bl_init(struct ak98_pwm *dev)
+{	
+	int ret = ak98_pwm_enable(dev);
+	if (ret == 0)
+		ak98_gpio_pulldown(dev->gpio, AK98_PULLDOWN_DISABLE);
+	
+	return ret;
+}
+
+static void bl_exit(struct ak98_pwm *dev)
+{
+	ak98_pwm_disable(dev);
+}
+
+struct ak98_platform_pwm_bl_data ak98pwm_backlight_data = {
+	.pwm_id = 1,
+		.max_brightness = 255,
+		.dft_brightness = 200,
+#if defined CONFIG_LCD_PANEL_QD043003C0_40
+		.pwm_clk = 4000,
+#elif defined CONFIG_LCD_PANEL_LW700AT9009
+		.pwm_clk = 6000,
+#else
+		.pwm_clk = 1024,
+#endif
+
+		.init = bl_init,
+		.notify = NULL,
+		.exit = bl_exit,
+};
+
+/* ts */
+static void ts_init_hwinit(const struct cp2007_intpin_info *intpin_info)
+{
+	//as gpio
+	ak98_setpin_as_gpio(intpin_info->pin);
+	//input mode
+	ak98_gpio_cfgpin(intpin_info->pin, intpin_info->dir);
+	// pulldown/pullup setting
+	if (intpin_info->pulldown == AK98_PULLDOWN_DISABLE || intpin_info->pulldown == AK98_PULLDOWN_ENABLE)
+		ak98_gpio_pulldown(intpin_info->pin, intpin_info->pulldown);
+	if (intpin_info->pullup == AK98_PULLUP_DISABLE || intpin_info->pullup == AK98_PULLUP_ENABLE)
+		ak98_gpio_pullup(intpin_info->pin, intpin_info->pullup);
+	//active low
+	ak98_gpio_intpol(intpin_info->pin, intpin_info->int_pol);
+}
+
+static int ts_is_pen_down(unsigned int pin)
+{
+	unsigned int ret;	
+
+	ret = ak98_gpio_getpin(pin);
+
+	return ret ? 0 : 1;
+}
+
+
+struct cp2007_ts_platform_data cp2007_ts_info = {
+	.origin_pos 	= ORIGIN_TOPLEFT,/* determined by the way the touch screen chip is connected*/
+	.x_plate_ohms	= 252,
+	.is_pen_down	= ts_is_pen_down,
+	.init_ts_hw		= ts_init_hwinit,
+	.intpin_info	= {
+			.pin 		= AK98_GPIO_6,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+		},
+};
+
+static struct i2c_board_info ak98_ts_devices[] __initdata = {
+	{
+		I2C_BOARD_INFO("cp2007_ts", 0x48),
+		.type		= "cp2007_ts",
+		.platform_data	= &cp2007_ts_info,
+		.irq		= IRQ_GPIO_6,
+	},
+};
+
+
+
+static struct ak98_ts_mach_info ak98adc_ts_info = {
+	.irq = IRQ_GPIO_107,
+	.irqpin = AK98_GPIO_107,
+	.sample_rate = 800,
+	.wait_time = 5,
+};
+
+struct wifi_control_data athena_wifi_control_data = {
+	.gpio_on = {
+		.pin		= AK98_GPIO_3,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.pullup		= -1,
+		.value		= AK98_GPIO_HIGH,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.int_pol	= -1,
+	},
+	.gpio_off = {
+		.pin		= AK98_GPIO_3,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.pullup		= -1,
+		.value		= AK98_GPIO_LOW,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.int_pol	= -1,
+	},
+	.power_on_delay   = 2000,
+	.power_off_delay  = 0,
+};
+
+static int athena_rtl8188_wifi_power_on(void)
+{
+	struct wifi_control_data *p = &athena_wifi_control_data;
+
+	if (p->gpio_on.pin > 0) {
+			ak98_gpio_set(&p->gpio_on);
+	}
+
+	msleep(p->power_on_delay);
+	printk("RTL8188: Power ON.\n");
+
+	return 0;
+}
+
+static int athena_rtl8188_wifi_power_off(void)
+{
+	struct wifi_control_data *p = &athena_wifi_control_data;
+
+	if (p->gpio_off.pin > 0) {
+			ak98_gpio_set(&p->gpio_off);
+	}
+
+	msleep(p->power_off_delay);
+	printk("RTL8188: Power OFF.\n");
+
+	return 0;
+}
+
+static struct ak98_wifi_platform_data athena_rtl8188_wifi_info = {
+	.power_on	= athena_rtl8188_wifi_power_on,
+	.power_off	= athena_rtl8188_wifi_power_off,
+};
+
+struct platform_device ak98_wifi_rtl8188_device = {
+	.name = "rtl8188",
+	.id = -1,
+	.dev = {
+		.platform_data = &athena_rtl8188_wifi_info,
+	},
+};
+
+/*ak98 battery mach info*/
+
+// sample of battery charge capacity and time,(capacity,time)
+static int charge_capacity[] 	= {0,70,90,96, 100};
+static int charge_times[]	 	= {0,45,70,105,180};
+
+// sample of battery charge capacity and voltage,(capacity,voltage)
+static int charge_capacity_voltage[] 	= {0,     2,	  8,    95,    100};
+static int charge_voltage[]		 		= {3300*2,3400*2,3650*2,4000*2,4100*2};
+
+
+// sample of battery discharge capacity and voltage,(capacity,voltage)
+static int discharge_capacity[]	 = {0,     2,	  8,     95,    100};
+static int discharge_voltage[]	 = {3300*2,3400*2,3650*2,4000*2,4100*2};
+
+static struct ak98_bat_mach_info ak98_bat_info = {
+	.gpio_init	= ak98_gpio_set,
+	
+	.usb_gpio	= {
+		.active 	= AK98_GPIO_HIGH,
+		.irq		= IRQ_GPIO_110, 
+		.pindata	={
+			.pin		= AK98_GPIO_110,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup 	= -1,
+			.value		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= -1,
+		},	
+	},
+	
+	.ac_gpio	= { 
+		.active 	= AK98_GPIO_HIGH,
+		.irq		= IRQ_GPIO_5, 
+		.pindata	={
+			.pin		= AK98_GPIO_5,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup 	= -1,
+			.value		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= -1,
+		},	
+	},
+
+	.state_gpio = {
+		.active 	= AK98_GPIO_HIGH,
+		.irq		= -ENOSYS, 
+		.pindata	={
+			.pin		= AK98_GPIO_71,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup 	= -1,
+			.value		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= -1,
+		},	
+	},
+	
+	.bat_mach_info	= {
+		.voltage_sample 	= 6,			// the sample of read voltage
+		.power_down_level	= 5,			// power down if(capacity <= power_down_level) 
+		.max_voltage		= 4200 * 2,		// max battery voltage	
+		.min_voltage		= 3300 * 2,		// min battery voltage	
+		.full_capacity		= 100,
+		.charge_max_time	= 180,
+	},
+	
+	.bat_adc	= {
+		.sample_rate		= 800,			// the same as touch screen
+		.wait_time			= 5,			// the same as touch screen
+		.up_resistance		= 47,
+		.dw_resistance		= 20,
+		.voltage_correct	= 65,			// battery correct factor
+		.adc_avdd			= 3300,
+	},
+
+	.charge		={
+		.capacity	= charge_capacity,
+		.time		= charge_times,
+		.length		= sizeof(charge_capacity),
+		.points		= sizeof(charge_capacity) / sizeof(charge_capacity[0]),
+	},
+
+	.charge_cv	={
+		.capacity	= charge_capacity_voltage,
+		.voltage	= charge_voltage,
+		.length 	= sizeof(charge_capacity_voltage),
+		.points 	= sizeof(charge_capacity_voltage) / sizeof(charge_capacity_voltage[0]),
+	},
+
+	.discharge 	={
+		.capacity	= discharge_capacity,
+		.voltage	= discharge_voltage,
+		.length		= sizeof(discharge_capacity),
+		.points		= sizeof(discharge_capacity) / sizeof(discharge_capacity[0]),
+	},
+};
+
+static void check_poweroff_init(void)
+{
+	//NULL
+}
+
+void check_poweroff(void)
+{
+	//NULL
+}
+
+/*end ak98 battery mach info*/
+
+void spi_pin_setup(struct ak98_spi_info *spi, int enable)
+{
+	if (enable)
+	{
+		ak98_group_config(ePIN_AS_SPI1);
+	}
+	else
+	{
+		ak98_setpin_as_gpio(AK98_GPIO_76);
+		ak98_setpin_as_gpio(AK98_GPIO_77);
+		ak98_setpin_as_gpio(AK98_GPIO_78);
+		ak98_setpin_as_gpio(AK98_GPIO_79);
+	}
+}
+
+struct ak98_spi_info ak98_spi1_info = {
+	.num_cs = 1,
+	.bus_num = 1,
+	.gpio_setup = spi_pin_setup,
+	.clk_name = "spi1_clk",
+	.mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH,
+	.mode = 0,
+};
+
+struct spi_board_info spidev_info = {
+	.modalias = "spidev",
+	.bus_num = 1,
+	.chip_select = 0,
+	.mode = SPI_MODE_0,	
+};
+
+struct spi_board_info ar7643_info = {
+	.modalias = "ar7643-spi",
+	.bus_num = 1,
+	.chip_select = 0,
+	.mode = SPI_MODE_0,	
+	.max_speed_hz = 1000000,
+};
+
+/* sensor */
+struct platform_device ak_sensor_device = {
+	.name = "ak_sensor",
+	.id = -1,
+};
+
+#undef	GSENSOR_EXIST
+#undef	MSENSOR_EXIST
+#undef	OSENSOR_EXIST
+#define GSENSOR_EXIST	(1)
+#define MSENSOR_EXIST	(1)
+#if (GSENSOR_EXIST && MSENSOR_EXIST)
+#define OSENSOR_EXIST	(1)
+#else
+#define OSENSOR_EXIST	(0)
+#endif
+
+static struct sensor_t ak98_sensors[] = {
+#ifdef CONFIG_SENSORS_MXC622X
+	{
+		.name		= "MXC622X",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_ACCELEROMETER,	
+		.maxRange	= "20",
+		.resolution	= "1531",
+		.power		= "5",
+		.dir		= "2",
+		.exist		= GSENSOR_EXIST,
+	},
+#endif
+#ifdef CONFIG_SENSORS_MMC328X
+	{
+		.name		= "MMC328X",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_MAGNETIC_FIELD,	
+		.maxRange	= "40",
+		.resolution	= "1953",
+		.power		= "3",
+		.dir		= "7",
+		.exist		= MSENSOR_EXIST,
+	},
+#endif
+	{
+		.name		= "Mag & Acc Combo Orientation Sensor",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_ORIENTATION,
+		.maxRange	= "20",
+		.resolution	= "10000",
+		.power		= "0",
+		.exist		= OSENSOR_EXIST,
+	},
+	{
+	},
+};
+
+static struct sensor_platform_data sensor_info = {
+	.sensors	= ak98_sensors,
+};
+ 
+#ifdef CONFIG_SENSORS_MXC622X
+static struct mxc622x_platform_data mxc622x_pdata = {
+	.hw_init	= ak98_gpio_set,
+	.irq		= IRQ_GPIO_109,
+	.gpio		= {
+		.pin		= AK98_GPIO_109,
+		.pulldown	= AK98_PULLDOWN_DISABLE,
+		.pullup		= AK98_PULLUP_ENABLE,
+		.value		= -1,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= -1,
+	}, 
+	.exist = GSENSOR_EXIST,
+};
+#endif
+
+static struct i2c_board_info ak98_sensor_devices[] __initdata = {
+#ifdef CONFIG_SENSORS_MXC622X
+	{
+		I2C_BOARD_INFO(MXC622X_I2C_NAME, MXC622X_I2C_ADDR),
+		.platform_data = &mxc622x_pdata,
+	},
+#endif
+#ifdef CONFIG_SENSORS_MMC328X
+	{
+		I2C_BOARD_INFO(MMC328X_I2C_NAME, MMC328X_I2C_ADDR),
+	},
+#endif
+	{
+	},
+};
+
+
+/* aw9523 GPIO expander */
+struct gpio_info aw9523_gpios[] = {
+	{
+		.pin 		= AK98_GPIO_106,
+		.pulldown 	= AK98_PULLDOWN_DISABLE,
+		.pullup 	= -1,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.value 		= -1,
+		.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+	},		
+};
+
+struct aw9523_platform_data aw9523_info = {
+	.gpio_base 	= AW9523_GPIO_P00,
+	.irq_base	= IRQ_AW9523_P00,
+	.parent_irq	= IRQ_GPIO_106,
+	.p0xmod		= AW9523_MOD_PUSHPULL,
+	.gpios 		= aw9523_gpios,
+	.npins		= ARRAY_SIZE(aw9523_gpios),
+};
+
+static struct i2c_board_info ak98_aw9523_ext[] __initdata = {
+	{
+		I2C_BOARD_INFO("aw9523_ext", 0x58),
+		.type	= "aw9523_ext",
+		.irq	= IRQ_GPIO_106,
+		.platform_data = &aw9523_info,
+	},
+};
+
+struct ak98pcm_platform_data ak98pcm_plat_data =
+{
+	.hpdet_gpio =
+	{
+		.pin        = AK98_GPIO_115,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.pullup		= AK98_PULLUP_ENABLE,
+		.pulldown	= AK98_PULLDOWN_DISABLE,
+		.value      = -1,
+		.int_pol	= -1,
+	},
+	.spk_down_gpio =
+	{
+		.pin        = AK98_GPIO_105,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.pullup		= -1,
+		.pulldown	= AK98_PULLDOWN_ENABLE,
+		.value      = AK98_GPIO_LOW,
+		.int_pol	= -1,
+	},
+	.hpmute_gpio =
+	{
+		.pin        = AK98_GPIO_1,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.pullup		= AK98_PULLUP_DISABLE,
+		.pulldown	= -1,
+		.value      = AK98_GPIO_LOW,
+		.int_pol	= -1,
+	},
+
+	.hp_on_value          = AK98_GPIO_LOW,
+	.hpdet_irq            = IRQ_GPIO_115,
+	.bIsHPmuteUsed        = 0,
+	.hp_mute_enable_value = AK98_GPIO_HIGH,
+	.bIsMetalfixed        = 0,
+};
+struct resource akpcm_resources[] = {
+	[0] = {
+			.start = 0x08000000,
+			.end = 0x0800FFFF,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_AnalogCtrlRegs",
+		  },
+	[1] = {
+			.start = 0x2002E000,
+			.end = 0x2002E00F,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_I2SCtrlRegs",
+		  },
+	[2] = {
+			.start = 0x2002D000,
+			.end = 0x2002D00F,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_ADC2ModeCfgRegs",
+		  },
+};
+static u64 snd_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device ak98pcm_device = {
+	.name = "snd_ak98pcm",
+	.id = 0,
+	
+	.dev = {
+			 .dma_mask	   = &snd_dma_mask,
+			 .coherent_dma_mask = DMA_BIT_MASK(32),
+			 .platform_data = &ak98pcm_plat_data,
+		   },	
+	.resource = akpcm_resources,
+	.num_resources = ARRAY_SIZE(akpcm_resources),
+};
+
+/* for sensor power control in Athena*/ 
+static int hi253_camera_power(struct device *dev, int on)
+{
+	if (on) {
+		printk(KERN_DEBUG "ov772x power on:\n");
+		ak98_gpio_cfgpin(AK98_GPIO_104, AK98_GPIO_DIR_OUTPUT);
+		ak98_gpio_setpin(AK98_GPIO_104, AK98_GPIO_HIGH);			
+		mdelay(10);		
+		ak98_gpio_setpin(AK98_GPIO_104, AK98_GPIO_LOW);	
+
+		/*reset the camera */
+		ak98_gpio_cfgpin(AK98_GPIO_102, AK98_GPIO_DIR_OUTPUT);
+//		ak98_gpio_setpin(AK98_GPIO_102, AK98_GPIO_HIGH);	
+	
+		ak98_gpio_setpin(AK98_GPIO_102, AK98_GPIO_LOW);	
+		mdelay(100);
+		ak98_gpio_setpin(AK98_GPIO_102, AK98_GPIO_HIGH);
+	} else {
+		printk(KERN_DEBUG "ov772x power down(not off):\n");
+	
+		ak98_gpio_setpin(AK98_GPIO_104, AK98_GPIO_HIGH); 
+	}
+	
+	return 0;
+}
+
+struct i2c_board_info ak98_camara_devices[] = {
+	{
+		I2C_BOARD_INFO("hi253", 0x20),
+	},
+};
+
+#if 0
+struct i2c_board_info ak98_camara_devices[] = {
+	{
+		I2C_BOARD_INFO("ov772x", 0x21), 		
+	},
+};
+#endif
+
+static struct hi253_camera_info  ak98_hi253_camera_info = {
+	.buswidth = SOCAM_DATAWIDTH_8,
+	.link = {
+		.bus_id = 98,
+		.power = hi253_camera_power,
+		.board_info = &ak98_camara_devices[0],
+		.i2c_adapter_id = 0,		
+	}	
+};
+
+#if 0
+static struct ov772x_camera_info  ak98_ov772x_camera_info = {
+	.buswidth = SOCAM_DATAWIDTH_8,
+	.link = {
+		.bus_id = 98,
+		.power = hi253_camera_power,
+		.board_info = &ak98_camara_devices[0],
+		.i2c_adapter_id = 0,		
+	}	
+};
+#endif
+
+/* fake device for soc_camera subsystem */
+static struct platform_device soc_camera_interface = {
+	.name = "soc-camera-pdrv",
+	.id   = -1,
+	.dev = {
+		.platform_data = &ak98_hi253_camera_info.link,
+	}
+};
+
+
+/* platform devices */
+static struct platform_device *athena_evt_platform_devices[] __initdata = {
+	//&ak98_led_device,
+	&ak98_rtc_device,
+	&ak98_uart0_device,
+	&ak98_uart1_device,
+	&ak98_uart2_device,
+	&ak98_uart3_device,
+	//&ak98_gpio_trkball_device,
+	//&ak98_kpd_device,
+	&ak98_nand_device,
+	&ak98_lcd_device,
+	&ak98_mmx_device,
+	&ak98_mmx_pmem,
+	//&ak98_snd_device,
+	&ak98_spi1_device,
+	&ak98_i2c_device,
+	&ak98_battery_power,
+	&athena_button_device,
+	&athena_keypad_device,
+	&ak98_mmc_device,
+	&ak98_sdio_device,
+	&ak98_usb_device,
+	&ak98_usb_fs_hcd_device,
+	&ak98_mac_device,
+	&ak98pcm_device,
+	&ak98_android_usb,
+	&ak98_android_usb_mass_storage,
+	&ak98adc_ts_device,
+	&ak98pwm_backlight_device,
+	&ak98_wifi_rtl8188_device,
+	&ak98_freq_policy_device,
+	&ak_sensor_device,
+	&soc_camera_interface,	
+	&ak98_camera_interface,	
+};
+
+static void athena_power_off(void)
+{
+	/*
+	 * Do a real power off by polling WAKEUP pin to low
+	 */
+	ak98_rtc_set_wpin(0);
+	ak98_gpio_cfgpin(AK98_GPIO_10, AK98_GPIO_DIR_INPUT);
+	ak98_gpio_pullup(AK98_GPIO_10, AK98_PULLUP_DISABLE);
+}
+
+static void athena_reset(void)
+{
+	ak98_reboot_sys_by_wtd();
+}
+
+static void __init athena_evt_machine_init(void)
+{
+	pm_power_off = athena_power_off;
+	ak98_arch_reset = athena_reset;
+
+	ak98_nand_device.dev.platform_data = &athena_evt_nand_info;
+	i2c_register_board_info(0, ak98_ts_devices, ARRAY_SIZE(ak98_ts_devices));
+	i2c_register_board_info(0, ak98_sensor_devices, ARRAY_SIZE(ak98_sensor_devices));
+	i2c_register_board_info(0, ak98_aw9523_ext, ARRAY_SIZE(ak98_aw9523_ext));
+	ak_sensor_device.dev.platform_data = &sensor_info;
+   
+	ak98adc_ts_device.dev.platform_data = &ak98adc_ts_info; 
+  	// set battery platform_data
+	ak98_battery_power.dev.platform_data = &ak98_bat_info;
+	ak98pwm_backlight_device.dev.platform_data = &ak98pwm_backlight_data;
+  
+	spidev_info.max_speed_hz = ak98_get_asic_clk()/2;	   
+	//spi_register_board_info(&spidev_info, 1);
+	spi_register_board_info(&ar7643_info, 1);
+	ak98_spi1_device.dev.platform_data = &ak98_spi1_info;
+	/* register platform devices */
+	platform_add_devices(athena_evt_platform_devices,
+		ARRAY_SIZE(athena_evt_platform_devices));
+
+	/* Initialize L2 buffer */
+	ak98_l2_init();
+
+}
+
+MACHINE_START(AK9801_ATHENA, "BOARD_AK9801ATHENA")
+
+/* Maintainer: */
+	.phys_io = 0x20000000,
+	.io_pg_offst = ((0xF0200000) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.init_irq = ak98_init_irq,
+	.map_io = ak98_map_io,
+	.init_machine = athena_evt_machine_init,
+	.timer = &ak98_timer, 
+MACHINE_END
diff --git a/arch/arm/mach-ak98/mach-mp5.c b/arch/arm/mach-ak98/mach-mp5.c
new file mode 100644
index 00000000000..35b24643e70
--- /dev/null
+++ b/arch/arm/mach-ak98/mach-mp5.c
@@ -0,0 +1,902 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c/aw9523.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/input/ak98matrix_keypad.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/mxc622x.h>
+#include <linux/mmc328x.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/nand.h>
+#include <mach/ts.h>
+#include <mach/spi.h>
+#include <mach/gpio.h>
+#include <mach/reset.h>
+#include <mach/devices.h>
+#include <mach/ak98_mci.h>
+#include <mach/regs-comm.h>
+#include <mach/bat.h>
+#include <mach/ak_sensor.h>
+#include <mach/map.h>
+#include <mach/lib_lcd.h>
+#include <mach/rtc.h>
+
+#include <linux/i2c/cp2007.h>
+#include <linux/dma-mapping.h>
+#include <mach/ak98_hal.h>
+#include <mach/l2.h>
+#include <mach/pwm.h>
+#include <mach/wifi.h>
+#include <mach/gpio_keys.h>
+#include <media/soc_camera.h>
+#include <media/hi253.h>
+#include <media/ov772x.h>
+
+
+#include "cpu.h"
+#include "irq.h"
+
+
+
+void (*ak98_arch_reset)(void);
+static void mp5_power_off(void);
+
+
+/* NAND parititon */
+/* for each block=512K */
+static struct mtd_partition mp5_nand_part[] = {
+[0] = {
+		.name = "Bootloader",
+		.size = SZ_512K,                 // 0 to 0
+		.offset = 0,
+		.mask_flags = MTD_WRITEABLE,
+       },
+[1] = {
+		.name = "SYS",
+		.size = SZ_256M , 			
+ 		.offset = MTDPART_OFS_APPEND,
+ 		},
+[2] = {
+		.name = "DATA",
+ 		.size = SZ_256M  , 		
+   		.offset = MTDPART_OFS_APPEND,
+ 		},
+[3] = {
+		.name = "TEST",
+ 		.size = SZ_256M ,  		
+  		.offset = MTDPART_OFS_APPEND,
+		},
+[4] = {
+		.name = "GUI",              
+		.size = MTDPART_SIZ_FULL,        
+		.offset = MTDPART_OFS_APPEND,
+		}
+};
+
+static struct ak98_nand_set mp5_nand_sets[] = {
+	[0] = {
+	       .name = "NAND",
+	       .nr_chips = 1,
+	       .nr_partitions = ARRAY_SIZE(mp5_nand_part),
+	       .partitions = mp5_nand_part,
+	      // .cmd_len = 0xF5BD1,	//0x93791
+	       .cmd_len = 0xF5AD1,
+	       .data_len = 0xF5C5C,	//0x91517
+	      // .data_len = 0x91717,
+	       }
+};
+
+static struct ak98_platform_nand mp5_nand_info = {
+	.nr_sets = ARRAY_SIZE(mp5_nand_sets),
+	.sets = mp5_nand_sets,
+};
+
+
+/* aw9523 GPIO expander */
+struct gpio_info aw9523_gpios[] = {
+	{
+		.pin 		= AK98_GPIO_6,
+		.pulldown 	= AK98_PULLDOWN_DISABLE,
+		.pullup 	= -1,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.value 		= -1,
+		.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+	},		
+};
+
+struct aw9523_platform_data aw9523_info = {
+	.gpio_base 	= AW9523_GPIO_P00,
+	.irq_base	= IRQ_AW9523_P00,
+	.parent_irq	= IRQ_GPIO_6,
+	.p0xmod		= AW9523_MOD_PUSHPULL,
+	.gpios 		= aw9523_gpios,
+	.npins		= ARRAY_SIZE(aw9523_gpios),
+};
+
+static struct i2c_board_info ak98_aw9523_ext[] __initdata = {
+	{
+		I2C_BOARD_INFO("aw9523_ext", 0x58),
+		.type	= "aw9523_ext",
+		.irq	= IRQ_GPIO_6,
+		.platform_data = &aw9523_info,
+	},
+};
+
+
+struct platform_device ak98_ar7643ts_device = {
+	.name = "ar7643-ts",
+	.id = -1,
+};
+
+
+/*
+* AK98 matrix Keyboard Device
+*/
+static const uint32_t athena_keypad_keymap[] = {
+	KEY(0, 0, KEY_VOLUMEUP),
+	KEY(0, 1, KEY_MENU),	
+	KEY(1, 0, KEY_VOLUMEDOWN),
+	KEY(1, 1, KEY_BACK),	
+};
+
+static struct matrix_keymap_data athena_keypad_keymap_data = {
+	.keymap		= athena_keypad_keymap,
+	.keymap_size	= ARRAY_SIZE(athena_keypad_keymap),
+};
+
+
+/* gpios whose direction is input should be row gpios */
+static const int athena_keypad_row_gpios[] = 
+{  AK98_GPIO_102, AK98_GPIO_103 };
+/* gpios whose direction is out should be row gpios */
+static const int athena_keypad_col_gpios[] = 
+{ AK98_GPIO_1 };
+
+static struct matrix_keypad_platform_data athena_keypad_pdata = {
+	.keymap_data	= &athena_keypad_keymap_data,
+	.row_gpios		= athena_keypad_row_gpios,
+	.col_gpios		= athena_keypad_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(athena_keypad_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(athena_keypad_col_gpios),
+	.col_scan_delay_us	= 10,
+	.debounce_ms		= 30,
+	.active_low		= 1,
+	.wakeup			= 0,
+	.row_gpios_cfginfo = {
+				.pin 		= -1,
+				.pulldown	= -1,
+				.pullup		= -1,
+				.dir		= AK98_GPIO_DIR_INPUT,
+				.value		= -1,
+				.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+		},
+	.col_gpios_cfginfo = {
+				.pin		= -1,
+				.pulldown	= -1,
+				.pullup		= AK98_PULLUP_DISABLE,
+				.dir 		= AK98_GPIO_DIR_OUTPUT,
+				.value		= AK98_GPIO_OUT_LOW, /* default state of output gpios*/
+				.int_pol	= -1,
+		},
+	.grounding		= true, /* grounding line should be the end line*/
+				
+};
+
+static struct platform_device athena_keypad_device = {
+	.name		= "matrix-keypad",
+	.id		= -1,
+	.dev		= {
+	.platform_data = &athena_keypad_pdata,
+	},
+};
+
+
+
+/*
+ * GPIO Buttons
+ */
+static struct ak98_gpio_keys_button mp5_buttons[] = {
+	
+	{	
+		.code		= KEY_POWER,
+		.gpio		= AK98_GPIO_13,
+		.active_low	= 0,
+		.desc		= "btn_powerdown",
+		.debounce_interval = 30,
+		.wakeup		= 1,
+		.pullup		= -1,
+		.pulldown	= AK98_PULLDOWN_DISABLE,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	
+};
+
+static struct ak98_gpio_keys_platform_data mp5_button_data = {
+	.buttons	= mp5_buttons,
+	.nbuttons	= ARRAY_SIZE(mp5_buttons),
+};
+
+	
+static struct platform_device mp5_button_device = {
+	.name		= "gpio_keys",
+	.id			= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &mp5_button_data,
+	}
+};
+
+/* MMC/SD */
+
+struct ak98_mci_platform_data mp5_mci_plat_data = {
+	.gpio_cd  = AK98_GPIO_5,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource ak98_mmc_resource[] = {
+	[0] = {
+		.start = 0x20020000,
+		.end = 0x20020000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC_SD,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ak98_mmc_device = {
+	.name = "ak98_mci",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_mmc_resource),
+	.resource = ak98_mmc_resource,
+	.dev = {
+		.platform_data = &mp5_mci_plat_data,
+	},
+};
+
+/* SDIO */
+struct ak98_mci_platform_data mp5_sdio_plat_data = {
+	.gpio_cd  = -ENOSYS,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource ak98_sdio_resource[] = {
+	[0] = {
+		.start = 0x20021000,
+		.end = 0x20021000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SDIO,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ak98_sdio_device = {
+	.name = "ak98_sdio",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(ak98_sdio_resource),
+	.resource = ak98_sdio_resource,
+	.dev = {
+		.platform_data = &mp5_sdio_plat_data,
+	},
+};
+
+static int bl_init(struct ak98_pwm *dev)
+{	
+	int ret = ak98_pwm_enable(dev);
+	if (ret == 0)
+		ak98_gpio_pulldown(dev->gpio, AK98_PULLDOWN_DISABLE);
+	
+	return ret;
+}
+
+static void bl_exit(struct ak98_pwm *dev)
+{
+	ak98_pwm_disable(dev);
+}
+
+struct ak98_platform_pwm_bl_data ak98pwm_backlight_data = {
+	.pwm_id = 1,
+		.max_brightness = 255,
+		.dft_brightness = 200,
+#if defined CONFIG_LCD_PANEL_QD043003C0_40
+		.pwm_clk = 240,
+#elif defined CONFIG_LCD_PANEL_LW700AT9009
+		.pwm_clk = 240,
+#else
+		.pwm_clk = 240,
+#endif
+
+		.init = bl_init,
+		.notify = NULL,
+		.exit = bl_exit,
+};
+
+/* ts */
+static void ts_init_hwinit(const struct cp2007_intpin_info *intpin_info)
+{
+	//as gpio
+	ak98_setpin_as_gpio(intpin_info->pin);
+	//input mode
+	ak98_gpio_cfgpin(intpin_info->pin, intpin_info->dir);
+	// pulldown/pullup setting
+	if (intpin_info->pulldown == AK98_PULLDOWN_DISABLE || intpin_info->pulldown == AK98_PULLDOWN_ENABLE)
+		ak98_gpio_pulldown(intpin_info->pin, intpin_info->pulldown);
+	if (intpin_info->pullup == AK98_PULLUP_DISABLE || intpin_info->pullup == AK98_PULLUP_ENABLE)
+		ak98_gpio_pullup(intpin_info->pin, intpin_info->pullup);
+	//active low
+	ak98_gpio_intpol(intpin_info->pin, intpin_info->int_pol);
+}
+
+static int ts_is_pen_down(unsigned int pin)
+{
+	unsigned int ret;	
+
+	ret = ak98_gpio_getpin(pin);
+
+	return ret ? 0 : 1;
+}
+
+
+struct cp2007_ts_platform_data cp2007_ts_info = {
+	.origin_pos 	= ORIGIN_BOTTOMLEFT,
+	.x_plate_ohms	= 252,
+	.is_pen_down	= ts_is_pen_down,
+	.init_ts_hw		= ts_init_hwinit,
+	.intpin_info	= {
+			.pin 		= AK98_GPIO_19,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= AK98_GPIO_INT_LOWLEVEL,
+		},
+};
+
+static struct i2c_board_info ak98_ts_devices[] __initdata = {
+	{
+		I2C_BOARD_INFO("cp2007_ts", 0x48),
+		.type		= "cp2007_ts",
+		.platform_data	= &cp2007_ts_info,
+		.irq		= IRQ_GPIO_19,
+	},
+};
+
+
+
+/* sensor */
+struct platform_device ak_sensor_device = {
+	.name = "ak_sensor",
+	.id = -1,
+};
+
+#undef	GSENSOR_EXIST
+#undef	MSENSOR_EXIST
+#undef	OSENSOR_EXIST
+#define GSENSOR_EXIST	(1)
+#define MSENSOR_EXIST	(1)
+#if (GSENSOR_EXIST && MSENSOR_EXIST)
+#define OSENSOR_EXIST	(1)
+#else
+#define OSENSOR_EXIST	(0)
+#endif
+
+static struct sensor_t ak98_sensors[] = {
+#ifdef CONFIG_SENSORS_MXC622X
+	{
+		.name		= "MXC622X",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_ACCELEROMETER,	
+		.maxRange	= "20",
+		.resolution	= "1531",
+		.power		= "5",
+		.dir		= "7",
+		.exist		= GSENSOR_EXIST,
+	},
+#endif
+#ifdef CONFIG_SENSORS_MMC328X
+	{
+		.name		= "MMC328X",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_MAGNETIC_FIELD,	
+		.maxRange	= "40",
+		.resolution	= "1953",
+		.power		= "3",
+		.dir		= "6",
+		.exist		= MSENSOR_EXIST,
+	},
+#endif
+	{
+		.name		= "Mag & Acc Combo Orientation Sensor",
+		.vendor		= "MEMSIC",
+		.type		= SENSOR_ORIENTATION,
+		.maxRange	= "20",
+		.resolution	= "10000",
+		.power		= "0",
+		.exist		= OSENSOR_EXIST,
+	},
+	{
+	},
+};
+
+static struct sensor_platform_data sensor_info = {
+	.sensors	= ak98_sensors,
+};
+ 
+#ifdef CONFIG_SENSORS_MXC622X
+static struct mxc622x_platform_data mxc622x_pdata = {
+	.hw_init	= ak98_gpio_set,
+	.irq		= IRQ_AW9523_P04,
+	.gpio		= {
+		.pin		= AW9523_GPIO_P04,
+		.pulldown	= -1,
+		.pullup		= -1,
+		.value		= -1,
+		.dir		= AK98_GPIO_DIR_INPUT,
+		.int_pol	= -1,
+	}, 
+	.exist = GSENSOR_EXIST,
+};
+#endif
+
+static struct i2c_board_info ak98_sensor_devices[] __initdata = {
+#ifdef CONFIG_SENSORS_MXC622X
+	{
+		I2C_BOARD_INFO(MXC622X_I2C_NAME, MXC622X_I2C_ADDR),
+		.platform_data = &mxc622x_pdata,
+	},
+#endif
+#ifdef CONFIG_SENSORS_MMC328X
+	{
+		I2C_BOARD_INFO(MMC328X_I2C_NAME, MMC328X_I2C_ADDR),
+	},
+#endif
+	{
+	},
+};
+
+struct wifi_control_data athena_wifi_control_data = {
+	.gpio_on = {
+		.pin		= AW9523_GPIO_P17,
+		.pulldown	= -1,
+		.pullup		= -1,
+		.value		= AK98_GPIO_OUT_HIGH,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.int_pol	= -1,
+	},
+	.gpio_off = {
+		.pin		= AW9523_GPIO_P17,
+		.pulldown	= -1,
+		.pullup		= -1,
+		.value		= AK98_GPIO_OUT_LOW,
+		.dir		= AK98_GPIO_DIR_OUTPUT,
+		.int_pol	= -1,
+	},
+	.power_on_delay   = 2000,
+	.power_off_delay  = 0,
+};
+
+static int athena_rtl8188_wifi_power_on(void)
+{
+	struct wifi_control_data *p = &athena_wifi_control_data;
+
+	if (p->gpio_on.pin > 0) {
+			ak98_gpio_set(&p->gpio_on);
+	}
+
+	msleep(p->power_on_delay);
+	printk("RTL8188: Power ON.\n");
+
+	return 0;
+}
+
+static int athena_rtl8188_wifi_power_off(void)
+{
+	struct wifi_control_data *p = &athena_wifi_control_data;
+
+	if (p->gpio_off.pin > 0) {
+			ak98_gpio_set(&p->gpio_off);
+	}
+
+	msleep(p->power_off_delay);
+	printk("RTL8188: Power OFF.\n");
+
+	return 0;
+}
+
+static struct ak98_wifi_platform_data athena_rtl8188_wifi_info = {
+	.power_on	= athena_rtl8188_wifi_power_on,
+	.power_off	= athena_rtl8188_wifi_power_off,
+};
+
+struct platform_device ak98_wifi_rtl8188_device = {
+	.name = "rtl8188",
+	.id = -1,
+	.dev = {
+		.platform_data = &athena_rtl8188_wifi_info,
+	},
+};
+
+/*ak98 battery mach info*/
+
+// sample of battery charge capacity and time,(capacity,time)
+static int charge_capacity[]	 = {0,67,74,96, 100};
+static int charge_times[]		 = {0,88,159,189,245};
+
+static int charge_capacity_voltage[]	= {0,   4,   62,  75,  99};
+static int charge_voltage[]				= {3310,3542,3948,3968,4200};
+
+// sample of battery discharge capacity and voltage,(capacity,voltage)
+static int discharge_capacity[] 	= {0,   6,   10,  41,  58,  100};
+static int discharge_voltage[]		= {2874,3300,3384,3668,3729,4100};
+
+
+static struct ak98_bat_mach_info ak98_bat_info = {
+
+	.gpio_init	= ak98_gpio_set,
+	
+	.usb_gpio	= {
+		.active 	= -1,
+		.irq		= -ENOSYS, 
+		.pindata	={
+			.pin		= -1,
+			.pulldown	= -1,
+			.pullup 	= -1,
+			.value		= -1,
+			.dir		= -1,
+			.int_pol	= -1,
+		},	
+	},
+	
+	.ac_gpio	= { 
+		.active 	= AK98_GPIO_HIGH,
+		.irq		= IRQ_GPIO_115, 
+		.pindata	={
+			.pin		= AK98_GPIO_115,
+			.pulldown	= -1,
+			.pullup 	= AK98_PULLUP_DISABLE,
+			.value		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= -1,
+		},	
+	},
+
+	.state_gpio	= {
+		.active 	= AK98_GPIO_HIGH,
+		.irq		= -ENOSYS, 
+		.pindata	={
+			.pin		= AK98_GPIO_18,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.pullup 	= AK98_PULLUP_ENABLE,
+			.value		= -1,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.int_pol	= -1,
+		},	
+	},
+	
+	.bat_mach_info	= {
+		.voltage_sample 	= 6,			// the sample of read voltage
+		.power_down_level	= 10,			// power down if(capacity <= power_down_level) 
+		.max_voltage		= 4200, 		// max battery voltage	
+		.min_voltage		= 3300, 		// min battery voltage
+		.full_capacity		= 100,			// battery full 
+		.charge_max_time	= 245,			// battery charge full time
+	},
+
+	.bat_adc	= {
+		.sample_rate		= 800,			// the same as touch screen
+		.wait_time			= 5,			// the same as touch screen
+		.up_resistance		= 12,
+		.dw_resistance		= 15,
+		.voltage_correct	= 32,			// battery correct factor
+		.adc_avdd			= 3300,			// avdd voltage
+		.adc_poweroff		= 600,			// about vbat = 3.5v
+	},
+
+	.charge 	={
+		.capacity	= charge_capacity,
+		.time		= charge_times,
+		.length 	= sizeof(charge_capacity),
+		.points 	= sizeof(charge_capacity) / sizeof(charge_capacity[0]),
+	},
+
+	.charge_cv	={
+		.capacity	= charge_capacity_voltage,
+		.voltage	= charge_voltage,
+		.length 	= sizeof(charge_capacity_voltage),
+		.points 	= sizeof(charge_capacity_voltage) / sizeof(charge_capacity_voltage[0]),
+	},
+	
+	.discharge	={
+		.capacity	= discharge_capacity,
+		.voltage	= discharge_voltage,
+		.length 	= sizeof(discharge_capacity),
+		.points 	= sizeof(discharge_capacity) / sizeof(discharge_capacity[0]),
+	},
+};
+
+// check poweroff
+static void check_poweroff_init(void)
+{
+	struct ak98_bat_mach_info *info = &ak98_bat_info;
+	info->gpio_init(&info->ac_gpio.pindata);
+	ak98_init_ADC1(info->bat_adc.sample_rate, info->bat_adc.wait_time);
+}
+
+void check_poweroff(void)
+{
+	int pinstate;
+	struct ak98_bat_mach_info *info = &ak98_bat_info;
+	
+	pinstate = ak98_gpio_getpin((unsigned int)info->ac_gpio.pindata.pin);
+
+	// check if charging
+	if (pinstate != info->ac_gpio.active)		
+	{
+		int ad4_value = 0;
+		unsigned int count = 0;
+		
+		ak98_power_ADC1(POWER_ON);
+		ak98_enable_bat_mon();	
+		
+		count = 5;
+		while ( count-- )
+		{
+			mdelay(1);							//delay for get next point ad4
+			ad4_value += ak98_read_voltage();	//0x3ff for 10 bit adc
+		}
+		
+		ak98_disable_bat_mon();
+		ak98_power_ADC1(POWER_OFF);  
+		ad4_value = ad4_value / 5;				// average of read voltage
+		
+		if (ad4_value <= info->bat_adc.adc_poweroff)
+		{
+			printk("=========ad4=%d;power off=========\n",ad4_value);
+			mp5_power_off();			
+		}
+		
+	}
+
+}
+
+// check powerof end
+/*end ak98 battery mach info*/
+
+struct ak98pcm_platform_data ak98pcm_plat_data =
+{
+	.hpdet_gpio =
+	{
+			.pin        = AK98_GPIO_7,
+			.dir		= AK98_GPIO_DIR_INPUT,
+			.pullup		= -1,
+			.pulldown	= AK98_PULLDOWN_DISABLE,
+			.value      = -1,
+			.int_pol	= AK98_GPIO_INT_HIGHLEVEL,
+	},
+	.spk_down_gpio =
+	{
+			.pin        = AW9523_GPIO_P10,
+			.dir		= AK98_GPIO_DIR_OUTPUT,
+			.pullup		= -1,
+			.pulldown	= -1,
+			.value      = AK98_GPIO_OUT_LOW,
+			.int_pol	= -1,
+	},
+	.hpmute_gpio =
+	{
+			.pin        = AK98_GPIO_2,
+			.dir		= AK98_GPIO_DIR_OUTPUT,
+			.pullup		= AK98_PULLUP_DISABLE,
+			.pulldown	= -1,
+			.value      = AK98_GPIO_LOW,
+			.int_pol	= -1,
+	},
+
+	.hp_on_value          = AK98_GPIO_HIGH,
+	.hpdet_irq            = IRQ_GPIO_7,
+	.bIsHPmuteUsed        = 1,
+	.hp_mute_enable_value = AK98_GPIO_HIGH,
+	.bIsMetalfixed        = 1,
+};
+
+struct resource akpcm_resources[] = {
+	[0] = {
+			.start = 0x08000000,
+			.end = 0x0800FFFF,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_AnalogCtrlRegs",
+		  },
+	[1] = {
+			.start = 0x2002E000,
+			.end = 0x2002E00F,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_I2SCtrlRegs",
+		  },
+	[2] = {
+			.start = 0x2002D000,
+			.end = 0x2002D00F,
+			.flags = (int)IORESOURCE_MEM,
+			.name = "ak98pcm_ADC2ModeCfgRegs",
+		  },
+};
+static u64 snd_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device ak98pcm_device = {
+	.name = "snd_ak98pcm",
+	.id = 0,
+	
+	.dev = {
+			 .dma_mask	   = &snd_dma_mask,
+			 .coherent_dma_mask = DMA_BIT_MASK(32),
+			 .platform_data = &ak98pcm_plat_data,
+		   },	
+	.resource = akpcm_resources,
+	.num_resources = ARRAY_SIZE(akpcm_resources),
+};
+
+/* for sensor power control */ 
+
+static int hi253_camera_power(struct device *dev, int on)
+{
+	if (on) {
+		printk(KERN_DEBUG "hi253 power on\n");
+		ak98_gpio_cfgpin(AK98_GPIO_3, AK98_GPIO_DIR_OUTPUT);
+		ak98_gpio_setpin(AK98_GPIO_3, AK98_GPIO_HIGH);			
+		mdelay(10);		
+		ak98_gpio_setpin(AK98_GPIO_3, AK98_GPIO_LOW);	
+
+		/*reset the camera */
+		ak98_gpio_cfgpin(AK98_GPIO_4, AK98_GPIO_DIR_OUTPUT);
+//		ak98_gpio_setpin(AK98_GPIO_102, AK98_GPIO_HIGH);	
+	
+		ak98_gpio_setpin(AK98_GPIO_4, AK98_GPIO_LOW);	
+		mdelay(100);
+		ak98_gpio_setpin(AK98_GPIO_4, AK98_GPIO_HIGH);
+	} else {
+		printk(KERN_DEBUG "hi253 power down\n");
+	
+		ak98_gpio_setpin(AK98_GPIO_3, AK98_GPIO_HIGH); 
+	}
+	
+	return 0;
+}
+
+/* hi253 image sensor's board information */
+static struct i2c_board_info ak98_camara_devices[] = {
+	{
+		I2C_BOARD_INFO("hi253", 0x20),
+	},
+};
+
+static struct hi253_camera_info  ak98_hi253_camera_info = {
+	.buswidth = SOCAM_DATAWIDTH_8,
+	.link = {
+		.bus_id = 98,
+		.power = hi253_camera_power,
+		.board_info = &ak98_camara_devices[0],
+		.i2c_adapter_id = 0,		
+	}	
+};
+
+/* fake device for soc_camera subsystem */
+static struct platform_device soc_camera_interface = {
+	.name = "soc-camera-pdrv",
+	.id   = -1,
+	.dev = {
+		.platform_data = &ak98_hi253_camera_info.link,
+	}
+};
+
+/* platform devices */
+static struct platform_device *mp5_platform_devices[] __initdata = {
+	//&ak98_led_device,
+	&ak98_rtc_device,
+	&ak98_uart0_device,
+	&ak98_uart1_device,
+	&ak98_nand_device,
+	&ak98_lcd_device,
+	&ak98_mmx_device,
+	&ak98_mmx_pmem,
+	&ak98_i2c_device,
+	&ak98_battery_power,
+	&mp5_button_device,
+	&ak98_mmc_device,
+	&ak98_sdio_device,
+	&ak98_usb_device,
+	&ak98_usb_fs_hcd_device,
+	&ak98pcm_device,
+	&ak98_android_usb,
+	&ak98_android_usb_mass_storage,
+	&ak98pwm_backlight_device,
+	&ak98_wifi_rtl8188_device,
+	&ak98_freq_policy_device,
+	&athena_keypad_device,
+	&ak_sensor_device,
+	&soc_camera_interface,	
+	&ak98_camera_interface,	
+
+};
+
+static void mp5_power_off(void)
+{
+	/*
+	 * Do a real power off by polling WAKEUP pin to low
+	 */
+	ak98_rtc_set_wpin(0);
+}
+
+static void mp5_reset(void)
+{
+	ak98_reboot_sys_by_wtd();
+}
+
+static void __init mp5_machine_init(void)
+{
+	check_poweroff_init();
+	check_poweroff();
+
+	pm_power_off = mp5_power_off;
+	ak98_arch_reset = mp5_reset;
+	
+	ak98_nand_device.dev.platform_data = &mp5_nand_info;
+
+	i2c_register_board_info(0, ak98_ts_devices, ARRAY_SIZE(ak98_ts_devices));
+	i2c_register_board_info(0, ak98_sensor_devices, ARRAY_SIZE(ak98_sensor_devices));
+	i2c_register_board_info(0, ak98_aw9523_ext, ARRAY_SIZE(ak98_aw9523_ext));
+
+	ak_sensor_device.dev.platform_data = &sensor_info;
+
+  	// set battery platform_data
+	ak98_battery_power.dev.platform_data = &ak98_bat_info;
+	ak98pwm_backlight_device.dev.platform_data = &ak98pwm_backlight_data;
+	
+	/* register platform devices */
+	platform_add_devices(mp5_platform_devices,
+		ARRAY_SIZE(mp5_platform_devices));
+
+	/* Initialize L2 buffer */
+	ak98_l2_init();
+
+}
+
+
+
+MACHINE_START(AK9805_MP5, "BOARD_AK9801ATHENA")
+/* Maintainer: */
+	.phys_io = 0x20000000,
+	.io_pg_offst = ((0xF0200000) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.init_irq = ak98_init_irq,
+	.map_io = ak98_map_io,
+	.init_machine = mp5_machine_init,
+	.timer = &ak98_timer, 
+MACHINE_END
diff --git a/arch/arm/mach-ak98/mach-tv908.c b/arch/arm/mach-ak98/mach-tv908.c
new file mode 100755
index 00000000000..40e0aa96425
--- /dev/null
+++ b/arch/arm/mach-ak98/mach-tv908.c
@@ -0,0 +1,281 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c/aw9523.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/gpio_keys.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/input.h>
+#include <linux/spi/spi.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/nand.h>
+#include <mach/ts.h>
+#include <mach/spi.h>
+#include <mach/gpio.h>
+#include <mach/reset.h>
+#include <mach/devices.h>
+#include <mach/ak98_mci.h>
+#include <mach/regs-comm.h>
+#include <mach/map.h>
+#include <mach/lib_lcd.h>
+#include <mach/rtc.h>
+
+#include <mach/l2.h>
+
+#include "cpu.h"
+#include "irq.h"
+
+
+void (*ak98_arch_reset)(void);
+
+/* NAND parititon */
+/* for each block=512K */
+static struct mtd_partition tv908_evt_nand_part[] = {
+[0] = {
+		.name = "Bootloader",
+		.size = SZ_512K,                 // 0 to 0
+		.offset = 0,
+		.mask_flags = MTD_WRITEABLE,
+       },
+[1] = {
+		.name = "SYS",
+		.size = SZ_256M , 			
+ 		.offset = MTDPART_OFS_APPEND,
+ 		},
+[2] = {
+		.name = "DATA",
+ 		.size = SZ_256M  , 		
+   		.offset = MTDPART_OFS_APPEND,
+ 		},
+[3] = {
+		.name = "TEST",
+ 		.size = SZ_256M ,  		
+  		.offset = MTDPART_OFS_APPEND,
+		},
+[4] = {
+		.name = "GUI",              
+		.size = MTDPART_SIZ_FULL,        
+		.offset = MTDPART_OFS_APPEND,
+		}
+};
+
+static struct ak98_nand_set tv908_evt_nand_sets[] = {
+	[0] = {
+	       .name = "NAND",
+	       .nr_chips = 1,
+	       .nr_partitions = ARRAY_SIZE(tv908_evt_nand_part),
+	       .partitions = tv908_evt_nand_part,
+	      // .cmd_len = 0xF5BD1,	//0x93791
+	       .cmd_len = 0xF5AD1,
+	       .data_len = 0xF5C5C,	//0x91517
+	      // .data_len = 0x91717,
+	       }
+};
+
+static struct ak98_platform_nand tv908_evt_nand_info = {
+	.nr_sets = ARRAY_SIZE(tv908_evt_nand_sets),
+	.sets = tv908_evt_nand_sets,
+};
+
+static struct i2c_board_info aw9523_ext_gpio_info[] = {
+    {
+        I2C_BOARD_INFO("aw9523", 0x58),
+    },
+};
+
+struct platform_device ak98_ar7643ts_device = {
+	.name = "ar7643-ts",
+	.id = -1,
+};
+
+/*
+ * GPIO Buttons
+ */
+static struct gpio_keys_button tv908_buttons[] = {
+	{			
+		.code		= KEY_BACK,
+		.gpio		= AK98_GPIO_104,
+		.active_low	= 0,
+		.desc		= "btn_Back",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+	},
+	{	
+		.code		= KEY_MENU,
+		.gpio		= AK98_GPIO_105,
+		.active_low	= 0,
+		.desc		= "btn_Menu",
+		.debounce_interval = 30,
+		.wakeup		= 1,
+	},
+	{	
+		.code		= KEY_POWER,
+		.gpio		= AK98_GPIO_13,
+		.active_low	= 1,
+		.desc		= "btn_powerdown",
+		.debounce_interval = 30,
+		.wakeup		= 0,
+	}
+};
+
+static struct gpio_keys_platform_data tv908_button_data = {
+	.buttons	= tv908_buttons,
+	.nbuttons	= ARRAY_SIZE(tv908_buttons),
+};
+
+static struct platform_device tv908_button_device = {
+	.name		= "gpio_keys",
+	.id			= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &tv908_button_data,
+	}
+};
+
+/* MMC/SD */
+
+struct ak98_mci_platform_data tv908_mci_plat_data = {
+	.gpio_cd  = AK98_GPIO_5,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource tv908_mmc_resource[] = {
+	[0] = {
+		.start = 0x20020000,
+		.end = 0x20020000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC_SD,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device tv908_mmc_device = {
+	.name = "ak98_mci",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(tv908_mmc_resource),
+	.resource = tv908_mmc_resource,
+	.dev = {
+		.platform_data = &tv908_mci_plat_data,
+	},
+};
+
+/* SDIO */
+struct ak98_mci_platform_data tv908_sdio_plat_data = {
+	.gpio_cd  = -ENOSYS,
+	.gpio_wp  = -ENOSYS,
+};
+
+static struct resource tv908_sdio_resource[] = {
+	[0] = {
+		.start = 0x20021000,
+		.end = 0x20021000 + 0x43,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_SDIO,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device tv908_sdio_device = {
+	.name = "ak98_sdio",
+	.id = -1,
+	.num_resources = ARRAY_SIZE(tv908_sdio_resource),
+	.resource = tv908_sdio_resource,
+	.dev = {
+		.platform_data = &tv908_sdio_plat_data,
+	},
+};
+
+
+/* platform devices */
+static struct platform_device *tv908_evt_platform_devices[] __initdata = {
+	//&ak98_led_device,
+	&ak98_rtc_device,
+	&ak98_uart0_device,
+	&ak98_uart1_device,
+	&ak98_uart3_device,
+	&ak98_nand_device,
+	&ak98_lcd_device,
+	&ak98_mmx_device,
+	&ak98_mmx_pmem,
+	&ak98_i2c_device,
+	&ak98_battery_power,
+	&tv908_button_device,
+	&tv908_mmc_device,
+	&tv908_sdio_device,
+	&ak98_usb_device,
+	&ak98_usb_fs_hcd_device,
+	&ak98pcm_device,
+	&ak98_android_usb,
+	&ak98_android_usb_mass_storage,
+	&ak98_ar7643ts_device,
+};
+
+static void tv908_power_off(void)
+{
+	/*
+	 * Do a real power off by polling WAKEUP pin to low
+	 */
+	ak98_rtc_set_wpin(0);
+}
+
+static void tv908_reset(void)
+{
+	ak98_reboot_sys();
+}
+
+static void __init tv908_evt_machine_init(void)
+{
+	pm_power_off = tv908_power_off;
+	ak98_arch_reset = tv908_reset;
+	
+	ak98_nand_device.dev.platform_data = &tv908_evt_nand_info;
+	i2c_register_board_info(0, aw9523_ext_gpio_info,
+                    ARRAY_SIZE(aw9523_ext_gpio_info));
+	
+	/* register platform devices */
+	platform_add_devices(tv908_evt_platform_devices,
+		ARRAY_SIZE(tv908_evt_platform_devices));
+
+	/* Initialize L2 buffer */
+	ak98_l2_init();
+
+}
+
+//MACHINE_START(AK9805_TV908, "BOARD_AK9805TV908")
+MACHINE_START(AK9805_TV908, "BOARD_AK9801ATHENA")
+/* Maintainer: */
+	.phys_io = 0x20000000,
+	.io_pg_offst = ((0xF0200000) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.init_irq = ak98_init_irq,
+	.map_io = ak98_map_io,
+	.init_machine = tv908_evt_machine_init,
+	.timer = &ak98_timer, 
+MACHINE_END
diff --git a/arch/arm/mach-ak98/pm.c b/arch/arm/mach-ak98/pm.c
new file mode 100644
index 00000000000..620efc558ef
--- /dev/null
+++ b/arch/arm/mach-ak98/pm.c
@@ -0,0 +1,148 @@
+/*
+ * linux/arch/arm/mach-ak98/pm.c
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+
+#include <mach/l2.h>
+#include <mach/l2_exebuf.h>
+
+void check_poweroff(void);
+
+static suspend_state_t target_state;
+
+#if 0
+static ak98_pm_debug_init(void)
+{
+}
+#else
+#define ak98_pm_debug_init() do { } while(0)
+#endif
+
+static int ak98_pm_valid_state(suspend_state_t state)
+{
+    switch (state) {
+        case PM_SUSPEND_ON:
+        case PM_SUSPEND_MEM:
+            return 1;
+        default:
+            return 0;
+    }
+}
+
+/*
+ * Called after processes are frozen, but before we shutdown devices.
+ */
+static int ak98_pm_begin(suspend_state_t state)
+{
+    target_state = state;
+    return 0;
+}
+
+void L2_LINK(standby) L2FUNC_NAME(standby)(unsigned long param1,
+    unsigned long param2,unsigned long param3, unsigned long param4)
+{
+	// check this bit and unitil both are empty 
+	while(!((REG32(RAM_CFG_REG4) & (FIFO_R_EMPTY | FIFO_CMD_EMPTY)) == (FIFO_R_EMPTY | FIFO_CMD_EMPTY)))
+		;
+	
+	// setup periodic of refresh interval and disable auto-refresh
+	REG32(RAM_CFG_REG4) = REFRESH_PERIOD_INTERVAL;
+
+	// invalidate and disable mmu
+    DISABLE_CACHE_MMU();
+	
+    // send all bank precharge
+    DDR2_ENTER_SELFREFRESH();
+    PM_DELAY(0x10);//at least more than 1 tck
+    
+    // disable ram clock
+    REG32(PHY_CLOCK_CTRL_REG) |= RAM_CLOCK_DISABLE;
+
+    // enter standby
+    REG32(PHY_CLOCK_DIV_REG) |= ENTER_STANDBY;
+    PM_DELAY(0x2000);  //at least more than 3 tck only for selfresh
+
+    // enable ram clock
+    REG32(PHY_CLOCK_CTRL_REG) &= ~RAM_CLOCK_DISABLE;
+
+	/* instruction:
+	 *	PM_DELAY(0x1) = 128.8ns  when mem clk = 200M 
+	 */
+    PM_DELAY(0x10); // at least more than 1 tck prior exit self  refresh
+    
+    // exit DDR2 self-refresch
+    DDR2_EXIT_SELFREFRESH();
+	
+	// send auto refresh and open odt high
+    DDR2_ENTER_AUTOREFRESH();
+
+	// enable auto-refresh
+    REG32(PHY_RAM_CFG_REG4) = REFRESH_PERIOD_INTERVAL | AUTO_REFRESH_EN;
+    PM_DELAY(0x100);
+
+    // enable ICache & DCache, mmu
+	ENABLE_CACHE_MMU();
+}
+
+static int ak98_pm_enter(suspend_state_t state)
+{
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	ak98_pm_debug_init();
+	flush_cache_all();
+
+	// change from low to normal mode  before enter standby if current is low mode 
+	cpu_freq_suspend_check();
+	
+	SPECIFIC_L2BUF_EXEC(standby, 0,0,0,0);
+
+	// check power off
+	check_poweroff();	
+
+	// restore low mode
+	cpu_freq_resume_check();
+	
+	local_irq_restore(flags);
+	return 0;
+}
+
+/*
+ * Called right prior to thawing processes.
+ */
+static void ak98_pm_end(void)
+{
+    target_state = PM_SUSPEND_ON;
+}
+
+static struct platform_suspend_ops ak98_pm_ops = {
+	.valid	= ak98_pm_valid_state,
+	.begin	= ak98_pm_begin,
+	.enter	= ak98_pm_enter,
+	.end	= ak98_pm_end,
+};
+
+/* ak98_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+int __init ak98_pm_init(void)
+{
+	printk("AK98 Power Management, (c) 2010 ANYKA\n");
+	suspend_set_ops(&ak98_pm_ops);
+
+	return 0;
+}
+arch_initcall(ak98_pm_init);
+
diff --git a/arch/arm/mach-ak98/pwm.c b/arch/arm/mach-ak98/pwm.c
new file mode 100644
index 00000000000..b9ce3eb113b
--- /dev/null
+++ b/arch/arm/mach-ak98/pwm.c
@@ -0,0 +1,134 @@
+/* 
+ * AK98 PWM controler driver 
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/gpio.h>
+#include <mach/pwm.h>
+
+struct ak98_pwm ak98_pwm1 = {
+	.id = 1,
+	.gpio = AK98_GPIO_9,
+	.pwm_ctrl = AK98_PWM1_CTRL,
+};
+
+struct ak98_pwm ak98_pwm2 = {
+	.id = 2,
+	.gpio = AK98_GPIO_10,
+	.pwm_ctrl = AK98_PWM2_CTRL,
+};
+
+struct ak98_pwm ak98_pwm3 = {
+	.id = 3,
+	.gpio = AK98_GPIO_11,
+	.pwm_ctrl = AK98_PWM3_CTRL,
+};
+
+struct ak98_pwm ak98_pwm4 = {
+	.id = 4,
+	.gpio = AK98_GPIO_12,
+	.pwm_ctrl = AK98_PWM4_CTRL,
+};
+
+int ak98_pwm_enable(struct ak98_pwm *pwm)
+{
+	switch(pwm->id) {
+		case 1:
+			ak98_group_config(ePIN_AS_PWM1);			
+			break;
+		case 2:
+			ak98_group_config(ePIN_AS_PWM2);
+			break;
+		case 3:
+			ak98_group_config(ePIN_AS_PWM3);
+			break;
+		case 4:
+			ak98_group_config(ePIN_AS_PWM4);
+			break;
+		default:
+			printk("init pwm error");
+			return -1;
+	}
+	return 0;
+}
+
+EXPORT_SYMBOL(ak98_pwm_enable);
+
+static int ak98_pwm_set_duty_cycle(struct ak98_pwm *pwm, unsigned short high, unsigned short low)
+{	
+	__raw_writel(high << 16 | low, pwm->pwm_ctrl);
+	return 0;
+}
+
+
+static int ak98_pwm_get_duty_cycle(struct ak98_pwm *pwm, unsigned short *high, unsigned short *low)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(pwm->pwm_ctrl);
+
+	*high = regval >> 16;
+	*low = regval & 0xFFFF;
+
+	return 0;
+}
+
+
+
+void ak98_pwm_disable(struct ak98_pwm *pwm)
+{
+	switch(pwm->id) {
+		case 1:
+			ak98_setpin_as_gpio(pwm->gpio);
+			break;
+		case 2:
+			ak98_setpin_as_gpio(pwm->gpio);
+			break;
+		case 3:
+			ak98_setpin_as_gpio(pwm->gpio);
+			break;
+		case 4:
+			ak98_setpin_as_gpio(pwm->gpio);
+			break;
+		default:
+			printk("init pwm error");
+	}
+}
+
+EXPORT_SYMBOL(ak98_pwm_disable);
+
+
+struct ak98_pwm *ak98_pwm_request(int pwm_id)
+{
+	switch(pwm_id) {
+		case 1:
+			return &ak98_pwm1;
+		case 2:
+			return &ak98_pwm2;
+		case 3:
+			return &ak98_pwm3;
+		case 4:
+			return &ak98_pwm4;
+		default:
+			printk("wrong pwm_id! should be between 1 and 4");
+	}
+	return NULL;
+}
+
+EXPORT_SYMBOL(ak98_pwm_request);
+
+int ak98_pwm_config(struct ak98_pwm *pwm, unsigned short high, unsigned short low)
+{
+	return ak98_pwm_set_duty_cycle(pwm, high, low);
+}
+EXPORT_SYMBOL(ak98_pwm_config);
+
diff --git a/arch/arm/mach-ak98/reg.c b/arch/arm/mach-ak98/reg.c
new file mode 100644
index 00000000000..48dbf943331
--- /dev/null
+++ b/arch/arm/mach-ak98/reg.c
@@ -0,0 +1,49 @@
+/*
+ * reg.c - Register Access Routines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+static DEFINE_SPINLOCK(sys_ctrl_reg_lock);
+
+/*
+ * @brief AK98xx system control register setting routine
+ * @author Li Xiaoping
+ * @date 2011-07-04
+ * @param reg_phy_addr [in] Register Physical Address
+ * @param reg_mask [in] Bit mask of the bits which need to be set
+ * @param reg_val [in] The value of the bits which need to be set
+ * @return void
+ * @note This routine is created in order to solve the problem of access the sam system control
+ *       register from different kernel path (ISR, system call, etc...).
+ * @note This routine depends on that corresponding registers are mapped, currently this is
+ *       done in ak98_map_io(), so be careful about ak98_map_io() changes.
+ * @sample ak98_sys_ctrl_reg_set(0x0800000C, (1 << 29), (1 << 29)) will set bit 29 of 
+ *       Clock Control and Soft Reset Control Register to 1
+ */
+void ak98_sys_ctrl_reg_set(unsigned long reg_phy_addr, unsigned long reg_mask, unsigned long reg_val)
+{
+	unsigned long flags;
+	unsigned long val;
+	unsigned long reg_virt_addr;
+
+	BUG_ON((reg_phy_addr < AK98_PA_SYSCTRL) || (reg_phy_addr > (AK98_PA_SYSCTRL + AK98_SZ_SYSCTRL)));
+
+	spin_lock_irqsave(&sys_ctrl_reg_lock, flags);
+
+	reg_virt_addr = (unsigned long)AK98_VA_SYSCTRL + reg_phy_addr - AK98_PA_SYSCTRL;
+	val = __raw_readl(reg_virt_addr);
+	val = (val & ~reg_mask) | (reg_val & reg_mask);
+	__raw_writel(val, reg_virt_addr);
+
+	spin_unlock_irqrestore(&sys_ctrl_reg_lock, flags);	
+}
+EXPORT_SYMBOL(ak98_sys_ctrl_reg_set);
diff --git a/arch/arm/mach-ak98/rtc.c b/arch/arm/mach-ak98/rtc.c
new file mode 100644
index 00000000000..039aff27c78
--- /dev/null
+++ b/arch/arm/mach-ak98/rtc.c
@@ -0,0 +1,325 @@
+/*
+ * linux/arch/arm/mach-ak98/rtc.c
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/clk.h>
+#include <linux/log2.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/rtc.h>
+
+
+static int rtc_cnt = 0;
+
+#undef REG32
+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))
+
+//reboot system by watchdog
+void ak98_reboot_sys_by_wtd(void)
+{
+	unsigned long val;	
+	unsigned long flags;
+	//static spinlock_t loc_lock;
+
+	//spin_lock_init(&loc_lock);
+	//spin_lock(&loc_lock);
+	local_irq_save(flags);
+	ak98_rtc_power(RTC_ON);
+
+	//select wdt
+	val = ak98_rtc_read(AK98_RTC_SETTING);	
+	val |= (1 << 10);	
+	ak98_rtc_write(AK98_RTC_SETTING, val);	
+	
+	//clear timer
+	val = ak98_rtc_read(AK98_RTC_SETTING);
+	val |= (1<<6);
+	ak98_rtc_write(AK98_RTC_SETTING, val);
+	
+
+	//enable watchdog timer
+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);
+	val |= (1<<13);
+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);
+		
+	//set timer
+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);
+	val &= (1<<13);
+	val |= (5 & 0x1FFF);
+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);
+
+	
+	//open watchdog and watchdog output
+	val = ak98_rtc_read(AK98_RTC_SETTING);
+	val |= ((1<<5) | (1<<2));
+	ak98_rtc_write(AK98_RTC_SETTING, val);
+
+	local_irq_restore(flags);
+//	spin_unlock(&loc_lock);
+}
+EXPORT_SYMBOL(ak98_reboot_sys_by_wtd);
+
+void ak98_reboot_sys_by_wakeup(void)
+{
+	//static spinlock_t loc_lock;
+	struct rtc_time ptm;
+	struct rtc_time *tm = &ptm;
+	//unsigned char mdays[13] = {0,31,28,31,30,31,30,31,31,30,31,30,31};
+	unsigned long flags;
+	
+	unsigned long rtcset;
+	unsigned long rtc_time1;
+	unsigned long rtc_time2;
+	unsigned long rtc_time3;	
+	
+	unsigned long rtc_alarm1;
+	unsigned long rtc_alarm2;
+	unsigned long rtc_alarm3;	
+	unsigned int val_1, val_2;
+	unsigned long time;
+	
+	//spin_lock_init(&loc_lock);
+	//spin_lock(&loc_lock);
+	local_irq_save(flags);
+	ak98_rtc_power(RTC_ON);
+	
+	rtcset = ak98_rtc_read(AK98_RTC_SETTING);
+	rtcset |= RTC_SETTING_REAL_TIME_RE;
+	ak98_rtc_write(AK98_RTC_SETTING, rtcset);
+	
+	rtc_time1 = ak98_rtc_read(AK98_RTC_REAL_TIME1);
+	rtc_time2 = ak98_rtc_read(AK98_RTC_REAL_TIME2);
+	rtc_time3 = ak98_rtc_read(AK98_RTC_REAL_TIME3);
+	
+	tm->tm_year  = ((rtc_time3 >> 4) & 0x7F) - EPOCH_START_YEAR + RTC_START_YEAR;
+	tm->tm_mon   = (rtc_time3 & 0xF) - 1;
+	tm->tm_mday  = (rtc_time2 >> 5) & 0x1F;
+	tm->tm_hour  = rtc_time2 & 0x1F;
+	tm->tm_min   = (rtc_time1 >> 6) & 0x3F;
+	tm->tm_sec   = rtc_time1 & 0x3F;
+	tm->tm_wday  = (rtc_time2 >> 10) & 0x7;
+	tm->tm_isdst = -1;	
+	
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+	
+	
+	rtc_alarm1 &= ~(0xFFF);
+	rtc_alarm2 &= ~(0x3FF);
+	rtc_alarm3 &= ~(0x7FF);
+	
+	#define DELAY_TIME 5
+	
+	rtc_tm_to_time(tm, &time);
+
+	time += DELAY_TIME;
+
+	rtc_time_to_tm(time, tm);
+	/*tm->tm_sec += DELAY_TIME;
+	
+	if (tm->tm_sec >= 60) 
+	{
+		tm->tm_sec -= 60;
+		tm->tm_min++;
+		if (tm->tm_min >= 60)
+		{
+			tm->tm_min = 0;
+			tm->tm_hour++;						
+			if (tm->tm_hour >= 24)
+			{
+				tm->tm_hour = 0;
+				tm->tm_mday++;
+				if ((tm->tm_year%400==0) || ((tm->tm_year%100!=0) && (tm->tm_year%4==0))) 
+					mdays[2] = 29;
+				if (tm->tm_mday > mdays[tm->tm_mon])
+				{
+					tm->tm_mday = 1;
+					tm->tm_mon++;
+					if (tm->tm_mon > 12)
+					{
+						tm->tm_mon = 1;
+						tm->tm_year++;
+					}
+				}
+			}
+		}
+			
+	}*/
+	rtc_alarm1 |= ((tm->tm_min << 6) + tm->tm_sec);
+	rtc_alarm2 |= ((tm->tm_mday << 5) + tm->tm_hour);
+	rtc_alarm3 |= (((tm->tm_year + EPOCH_START_YEAR - RTC_START_YEAR) << 4) + (tm->tm_mon + 1));
+	
+	ak98_rtc_write(AK98_RTC_ALARM_TIME1, rtc_alarm1);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME2, rtc_alarm2);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME3, rtc_alarm3);
+	
+	val_1 = REG32(AK98_RTC_CDR);
+	
+	
+	val_2 = ak98_rtc_read(AK98_RTC_SETTING);
+	
+	if (1)
+	{
+		/* enable wakeup signal */
+		val_1 |= RTC_WAKEUP_EN;// | RTC_WAKEUP_SIGNAL_LOWACTIVE);
+		REG32(AK98_RTC_CDR) =  val_1;
+		
+		val_2 |= (1<<2);
+		ak98_rtc_write(AK98_RTC_SETTING, val_2);
+	} 
+	
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+	
+	rtc_alarm1 |= (1<<13);
+	rtc_alarm2 |= (1<<13);
+	rtc_alarm3 |= (1<<13);
+	
+	ak98_rtc_write(AK98_RTC_ALARM_TIME1, rtc_alarm1);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME2, rtc_alarm2);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME3, rtc_alarm3);	
+
+	local_irq_restore(flags);
+//	spin_unlock(&loc_lock);
+	ak98_rtc_set_wpin(0);
+}
+
+EXPORT_SYMBOL(ak98_reboot_sys_by_wakeup);
+
+void ak98_rtc_power(int op)
+{
+	unsigned long rtcconf;
+
+	switch(op)
+	{
+	case RTC_ON:
+		if (++rtc_cnt == 1)
+		{
+			rtcconf = __raw_readl(AK98_RTC_CONF);
+			rtcconf |= RTC_CONF_RTC_EN;
+			__raw_writel(rtcconf, AK98_RTC_CONF);
+		}
+		break;
+		/*
+		When RTC is powered off, this bit(AK98_RTC_CONF [24] ) should be set to 0
+	*/
+	case RTC_OFF:
+		if (!(--rtc_cnt))
+		{
+			rtcconf = __raw_readl(AK98_RTC_CONF);
+			rtcconf &= ~RTC_CONF_RTC_EN;
+			__raw_writel(rtcconf, AK98_RTC_CONF);
+		}
+		break;
+	default:
+		printk("Error RTC power operation.\n");
+		break;
+	}
+}
+
+EXPORT_SYMBOL(ak98_rtc_power);
+
+
+unsigned int ak98_rtc_read(unsigned int addr)
+{
+	unsigned long regval = 0;
+	unsigned long flags;
+
+	if (addr > AK98_RTC_REG_MAX) {
+		printk("%s(): Invalid RTC Register, address=%d\n",
+			__func__, addr);
+		return -1;
+	}
+
+	local_irq_save(flags);
+
+	rtc_ready_irq_enable();
+
+	regval  = __raw_readl(AK98_RTC_CONF);
+	regval  &= ~(0x3FFFFF) ;
+	regval  |= (RTC_CONF_RTC_READ | (addr << 14));
+	__raw_writel(regval, AK98_RTC_CONF);
+
+	ak98_rtc_wait_ready();
+
+	regval = __raw_readl(AK98_RTC_DATA);
+	regval &= 0x3FFF;
+	
+	rtc_ready_irq_disable();
+
+	local_irq_restore(flags);
+	
+	return regval;
+}
+EXPORT_SYMBOL(ak98_rtc_read);
+
+unsigned int ak98_rtc_write(unsigned int addr, unsigned int value)
+{
+	unsigned long regval = 0;
+	unsigned long flags;
+
+	if (addr > AK98_RTC_REG_MAX) {
+		printk("%s(): Invalid RTC Register, address=%d\n",
+			__func__, addr);
+		return -1;
+	}
+
+	local_irq_save(flags);
+
+	rtc_ready_irq_enable();
+
+	regval  = __raw_readl(AK98_RTC_CONF);
+	regval  &= ~0x3FFFFF;
+	regval  |= (RTC_CONF_RTC_WRITE | (addr << 14) | value);
+	__raw_writel(regval, AK98_RTC_CONF);
+
+	ak98_rtc_wait_ready();
+	
+	rtc_ready_irq_disable();
+
+	local_irq_restore(flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_rtc_write);
+
+unsigned int ak98_rtc_set_wpin(bool level)
+{
+	unsigned long regval;
+	unsigned int bit;
+
+	ak98_rtc_power(RTC_ON);
+
+	bit = level ? 8 : 7;
+
+	regval = ak98_rtc_read(AK98_RTC_SETTING);
+	regval |= (1 << bit);
+	ak98_rtc_write(AK98_RTC_SETTING, regval);
+
+	while (ak98_rtc_read(AK98_RTC_SETTING) & (1 << bit))
+		;
+
+	return 0;
+}
+EXPORT_SYMBOL(ak98_rtc_set_wpin);
diff --git a/arch/arm/mach-ak98/time.c b/arch/arm/mach-ak98/time.c
new file mode 100644
index 00000000000..b9ae99de7ff
--- /dev/null
+++ b/arch/arm/mach-ak98/time.c
@@ -0,0 +1,187 @@
+/* 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#if 0
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#endif
+#include <asm/mach/time.h>
+
+#include <mach/map.h>
+
+#define	AK98_TIMER1_CTRL	(AK98_VA_SYSCTRL+0x18)
+#define	AK98_TIMER1_READ	(AK98_VA_SYSCTRL+0x100)
+#define	AK98_TIMER2_CTRL	(AK98_VA_SYSCTRL+0x1C)
+
+#define AK98_SYSCTRL_IRQ_CTRL	(AK98_VA_SYSCTRL+0x4C)
+#define	AK98_IRQ_MASK		(AK98_VA_SYSCTRL+0x34)
+
+#define TIMER_ENABLE		(1<<26)
+#define TIMER_LOAD_NEWCNT	(1<<27)
+#define TIMER_INT_CLR		(1<<28)
+#define TIMER_INT_STA		(1<<29)
+#define TIMER_CNT		(12000000/HZ)
+#define TIMER_CNT_MASK		(0x3F<<26)
+
+static u_int64_t ghrtick = 0;
+static unsigned long timer_startval;
+
+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
+{
+	return (ticks * 1000 / 12000000);
+}
+
+/*
+ * Returns microsecond  since last clock interrupt.  Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ *
+ * FIXME: this need be checked 
+ */
+static unsigned long ak98_gettimeoffset(void)
+{
+	unsigned long tval;
+	unsigned long tdone;
+	unsigned long tcnt;
+
+	/* work out how many ticks have gone since last timer interrupt */
+
+	tval = __raw_readl(AK98_TIMER1_CTRL);
+
+	tcnt = tval & ~TIMER_CNT_MASK;
+
+	tdone = timer_startval - tcnt;
+
+	if (tval & TIMER_INT_STA) {	/* Timer1 has generated interrupt, and not clear */
+
+		/* Reread timer counter */
+		tval = __raw_readl(AK98_TIMER1_CTRL);
+		tcnt = tval & ~TIMER_CNT_MASK;
+
+		tdone = timer_startval - tcnt;
+
+		if (tcnt != 0)
+			tdone += timer_startval;
+	}
+
+	return timer_ticks_to_usec(tdone);
+}
+
+static void ak98_timer_setup(unsigned long timecnt)
+{
+	unsigned long tctrl;
+
+	/* setting timer1 ctrl */
+#if 0
+	__raw_writel(TIMER_INT_CLR, AK98_TIMER1_CTRL);
+	__raw_writel(timecnt & ~TIMER_CNT_MASK, AK98_TIMER1_CTRL);
+
+	tctrl = __raw_readl(AK98_TIMER1_CTRL);
+	tctrl |= (TIMER_LOAD_NEWCNT | TIMER_ENABLE);
+	__raw_writel(tctrl, AK98_TIMER1_CTRL);
+#else				/* reload */
+	*(volatile unsigned int *)(AK98_TIMER1_CTRL) |=
+	    TIMER_INT_CLR | TIMER_ENABLE;
+#endif
+}
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t ak98_timer_interrupt(int irq, void *dev_id)
+{
+	/* printk("%s\n", __FUNCTION__); */
+
+	if (__raw_readl(AK98_TIMER1_CTRL) & TIMER_INT_STA) {
+
+        ghrtick += TIMER_CNT;
+
+		timer_tick();
+
+		ak98_timer_setup(timer_startval);
+	}
+
+	return IRQ_HANDLED;
+}
+
+#if 1
+u_int64_t ak98_gethrtick(void)
+{
+    unsigned long timecnt = 0;
+    
+    timecnt = __raw_readl(AK98_TIMER1_READ);
+    
+    timecnt &= (~TIMER_CNT_MASK);
+    
+    return (ghrtick + (u_int64_t)(TIMER_CNT-timecnt));
+}
+
+unsigned long ak98_gettimeofcycle(void)
+{
+    unsigned long timecnt = 0;
+
+    timecnt = __raw_readl(AK98_TIMER1_READ);
+
+    timecnt &= (~TIMER_CNT_MASK);
+
+    return (TIMER_CNT - timecnt) / 12;
+}
+#endif
+
+static struct irqaction ak98_timer_irq = {
+	.name = "timer tick",
+	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler = ak98_timer_interrupt,
+};
+
+static void __init ak98_timer_init(void)
+{
+#if 0
+	timer_startval = TIMER_CNT;
+
+	/* setting timer1 ctrl */
+	ak98_timer_setup(timer_startval);
+#else
+	unsigned long tctrl;
+	unsigned long timecnt = TIMER_CNT;
+	__raw_writel(TIMER_INT_CLR, AK98_TIMER1_CTRL);
+	__raw_writel(timecnt & ~TIMER_CNT_MASK, AK98_TIMER1_CTRL);
+
+	tctrl = __raw_readl(AK98_TIMER1_CTRL);
+	tctrl |= (TIMER_LOAD_NEWCNT | TIMER_ENABLE);
+	__raw_writel(tctrl, AK98_TIMER1_CTRL);
+#endif
+
+	/* setup irq handler for IRQ_TIMER */
+	setup_irq(IRQ_TIMER1, &ak98_timer_irq);
+    ghrtick = 0;
+}
+
+struct sys_timer ak98_timer = {
+	.init = ak98_timer_init,
+	.offset = ak98_gettimeoffset,
+//      .resume         = ak98_timer_setup
+};
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 295e25dd638..037cb2dc8ce 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -248,6 +248,11 @@ ENTRY(v6_dma_clean_range)
  *	- end     - virtual end address of region
  */
 ENTRY(v6_dma_flush_range)
+#ifdef CONFIG_CACHE_FLUSH_RANGE_LIMIT
+	sub	r2, r1, r0
+	cmp	r2, #CONFIG_CACHE_FLUSH_RANGE_LIMIT
+	bhi	v6_dma_flush_dcache_all
+#endif
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef HARVARD_CACHE
@@ -262,6 +267,18 @@ ENTRY(v6_dma_flush_range)
 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
 	mov	pc, lr
 
+#ifdef CONFIG_CACHE_FLUSH_RANGE_LIMIT
+v6_dma_flush_dcache_all:
+	mov	r0, #0
+#ifdef HARVARD_CACHE
+	mcr	p15, 0, r0, c7, c14, 0		@ D cache clean+invalidate
+#else
+	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
+#endif
+	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer
+	mov	pc, lr
+#endif
+
 	__INITDATA
 
 	.type	v6_cache_fns, #object
diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile
index 88e31f549f5..555a74c8433 100644
--- a/arch/arm/oprofile/Makefile
+++ b/arch/arm/oprofile/Makefile
@@ -12,3 +12,4 @@ oprofile-$(CONFIG_OPROFILE_ARM11_CORE)	+= op_model_arm11_core.o
 oprofile-$(CONFIG_OPROFILE_ARMV6)	+= op_model_v6.o
 oprofile-$(CONFIG_OPROFILE_MPCORE)	+= op_model_mpcore.o
 oprofile-$(CONFIG_OPROFILE_ARMV7)	+= op_model_v7.o
+oprofile-$(CONFIG_OPROFILE_AK98)	+= op_model_ak98.o
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 3fcd752d614..a34fced1175 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -149,6 +149,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 	spec = &op_armv7_spec;
 #endif
 
+#ifdef CONFIG_OPROFILE_AK98
+	spec = &op_ak98_spec;
+#endif
+
 	if (spec) {
 		ret = spec->init();
 		if (ret < 0)
diff --git a/arch/arm/oprofile/op_arm_model.h b/arch/arm/oprofile/op_arm_model.h
index 8c4e4f6a1de..ced84765f5f 100644
--- a/arch/arm/oprofile/op_arm_model.h
+++ b/arch/arm/oprofile/op_arm_model.h
@@ -27,6 +27,7 @@ extern struct op_arm_model_spec op_xscale_spec;
 extern struct op_arm_model_spec op_armv6_spec;
 extern struct op_arm_model_spec op_mpcore_spec;
 extern struct op_arm_model_spec op_armv7_spec;
+extern struct op_arm_model_spec op_ak98_spec;
 
 extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth);
 
diff --git a/arch/arm/oprofile/op_model_ak98.c b/arch/arm/oprofile/op_model_ak98.c
new file mode 100755
index 00000000000..5e5f0d02466
--- /dev/null
+++ b/arch/arm/oprofile/op_model_ak98.c
@@ -0,0 +1,111 @@
+/**

+ * @file op_model_ak98.c

+ * ak98 Performance Monitor Driver

+ *

+ * Based on op_model_v6.c

+ *

+ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>

+ * @remark Copyright 2000-2004 MontaVista Software Inc

+ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>

+ * @remark Copyright 2004 Intel Corporation

+ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>

+ * @remark Copyright 2004 OProfile Authors

+ *

+ * @remark Read the file COPYING

+ *

+ * @author Oxygen 

+ */

+

+/* #define DEBUG */

+#include <linux/types.h>

+#include <linux/errno.h>

+#include <linux/sched.h>

+#include <linux/oprofile.h>

+#include <linux/interrupt.h>

+#include <linux/irq.h>

+

+#include "op_counter.h"

+#include "op_arm_model.h"

+

+#include <asm/io.h>

+#include <asm/mach/time.h>

+#include <mach/map.h>

+#include <mach/clock.h>

+

+#define	AK98_TIMER2_CTRL	(AK98_VA_SYSCTRL+0x1C)

+

+#define AK98_SYSCTRL_IRQ_CTRL	(AK98_VA_SYSCTRL+0x4C)

+#define	AK98_IRQ_MASK		(AK98_VA_SYSCTRL+0x34)

+

+#define TIMER_ENABLE		(1<<26)

+#define TIMER_LOAD_NEWCNT	(1<<27)

+#define TIMER_INT_CLR		(1<<28)

+#define TIMER_INT_STA		(1<<29)

+#define TIMER_CNT_MASK		(0x3F<<26)

+

+

+/*

+ * CPU counters' IRQ handler (one IRQ per CPU)

+ */

+static irqreturn_t ak98_timer_interrupt(int irq, void *arg)

+{

+	struct pt_regs *regs = get_irq_regs();

+	

+	oprofile_add_sample(regs, 0);//CCNT

+	

+	/* Clear counter flag(s) */

+	*(volatile unsigned int *)(AK98_TIMER2_CTRL) |= TIMER_INT_CLR | TIMER_ENABLE;

+	return IRQ_HANDLED;

+}

+

+static struct irqaction ak98_timer_irq = {

+	.name = "oprofile cnt",

+	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,

+	.handler = ak98_timer_interrupt,

+};

+

+

+static void ak98_pmu_stop(void)

+{

+    //stop timer

+    __raw_writel(TIMER_INT_CLR, AK98_TIMER2_CTRL);

+	//release_irq

+    remove_irq(IRQ_TIMER2, &ak98_timer_irq);    

+}

+

+static int ak98_pmu_start(void)

+{	

+    unsigned long tctrl;

+    unsigned long timecnt = counter_config[0].count * 12 / (ak98_get_cpu_clk() / MHz);

+    

+    /* setup irq handler for IRQ_TIMER */

+	setup_irq(IRQ_TIMER2, &ak98_timer_irq);

+

+    __raw_writel(TIMER_INT_CLR, AK98_TIMER2_CTRL);

+    __raw_writel(timecnt & ~TIMER_CNT_MASK, AK98_TIMER2_CTRL);

+

+    tctrl = __raw_readl(AK98_TIMER2_CTRL);

+    tctrl |= (TIMER_LOAD_NEWCNT | TIMER_ENABLE);

+    __raw_writel(tctrl, AK98_TIMER2_CTRL);

+    

+	return 0;

+}

+

+static int ak98_detect_pmu(void)

+{

+	return 0;

+}

+

+static int ak98_setup_pmu(void)

+{

+    return 0;

+}

+

+struct op_arm_model_spec op_ak98_spec = {

+	.init		= ak98_detect_pmu,

+	.num_counters	= 1,

+	.setup_ctrs	= ak98_setup_pmu,

+	.start		= ak98_pmu_start,

+	.stop		= ak98_pmu_stop,

+	.name		= "timer",

+};

diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 07b976da617..0f03ef3becd 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -2536,3 +2536,8 @@ c3ax03			MACH_C3AX03		C3AX03			2549
 mxt_td60		MACH_MXT_TD60		MXT_TD60		2550
 esyx			MACH_ESYX		ESYX			2551
 bulldog			MACH_BULLDOG		BULLDOG			2553
+ak88			MACH_AK88			AK88	 	    2684
+ak9801_athena	MACH_AK9801_ATHENA	AK9801_ATHENA   2685
+ak9805_tv908	MACH_AK9805_TV908	AK9805_TV908	2686
+ak9805_mp5		MACH_AK9805_MP5		AK9805_MP5		2687
+
diff --git a/arch/sh/boot/compressed/vmlinux.scr b/arch/sh/boot/compressed/vmlinux.scr
deleted file mode 100644
index f02382ae5c4..00000000000
--- a/arch/sh/boot/compressed/vmlinux.scr
+++ /dev/null
@@ -1,10 +0,0 @@
-SECTIONS
-{
-  .rodata.compressed : {
-	input_len = .;
-	LONG(input_data_end - input_data) input_data = .;
-	*(.data)
-	output_len = . - 4;
-	input_data_end = .;
-	}
-}
diff --git a/arch/sh/boot/romimage/vmlinux.scr b/arch/sh/boot/romimage/vmlinux.scr
deleted file mode 100644
index 287c08f8b4b..00000000000
--- a/arch/sh/boot/romimage/vmlinux.scr
+++ /dev/null
@@ -1,6 +0,0 @@
-SECTIONS
-{
-  .text : {
-	*(.data)
-	}
-}
diff --git a/block/blk-core.c b/block/blk-core.c
index 71da5111120..ae835b42b6a 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -1569,11 +1569,12 @@ void submit_bio(int rw, struct bio *bio)
 
 		if (unlikely(block_dump)) {
 			char b[BDEVNAME_SIZE];
-			printk(KERN_DEBUG "%s(%d): %s block %Lu on %s\n",
+			printk(KERN_DEBUG "%s(%d): %s block %Lu on %s (%u sectors)\n",
 			current->comm, task_pid_nr(current),
 				(rw & WRITE) ? "WRITE" : "READ",
 				(unsigned long long)bio->bi_sector,
-				bdevname(bio->bi_bdev, b));
+				bdevname(bio->bi_bdev, b),
+				count);
 		}
 	}
 
diff --git a/block/genhd.c b/block/genhd.c
index 517e4332cb3..2ba9e7a7ead 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -541,13 +541,15 @@ void add_disk(struct gendisk *disk)
 	disk->major = MAJOR(devt);
 	disk->first_minor = MINOR(devt);
 
+    /* Register BDI before referencing it from bdev */ 
+    bdi = &disk->queue->backing_dev_info;
+    bdi_register_dev(bdi, disk_devt(disk));
+
 	blk_register_region(disk_devt(disk), disk->minors, NULL,
 			    exact_match, exact_lock, disk);
 	register_disk(disk);
 	blk_register_queue(disk);
-
-	bdi = &disk->queue->backing_dev_info;
-	bdi_register_dev(bdi, disk_devt(disk));
+	
 	retval = sysfs_create_link(&disk_to_dev(disk)->kobj, &bdi->dev->kobj,
 				   "bdi");
 	WARN_ON(retval);
@@ -994,6 +996,22 @@ static void disk_release(struct device *dev)
 	free_part_stats(&disk->part0);
 	kfree(disk);
 }
+
+static int disk_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+	struct gendisk *disk = dev_to_disk(dev);
+	struct disk_part_iter piter;
+	struct hd_struct *part;
+	int cnt = 0;
+
+	disk_part_iter_init(&piter, disk, 0);
+	while((part = disk_part_iter_next(&piter)))
+		cnt++;
+	disk_part_iter_exit(&piter);
+	add_uevent_var(env, "NPARTS=%u", cnt);
+	return 0;
+}
+
 struct class block_class = {
 	.name		= "block",
 };
@@ -1012,6 +1030,7 @@ static struct device_type disk_type = {
 	.groups		= disk_attr_groups,
 	.release	= disk_release,
 	.devnode	= block_devnode,
+	.uevent		= disk_uevent,
 };
 
 #ifdef CONFIG_PROC_FS
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 48bbdbe43e6..100b3949513 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -90,6 +90,8 @@ source "drivers/memstick/Kconfig"
 
 source "drivers/leds/Kconfig"
 
+source "drivers/switch/Kconfig"
+
 source "drivers/accessibility/Kconfig"
 
 source "drivers/infiniband/Kconfig"
@@ -113,4 +115,5 @@ source "drivers/xen/Kconfig"
 source "drivers/staging/Kconfig"
 
 source "drivers/platform/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 6ee53c7a57a..184395a78ab 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -94,6 +94,7 @@ obj-y				+= idle/
 obj-$(CONFIG_MMC)		+= mmc/
 obj-$(CONFIG_MEMSTICK)		+= memstick/
 obj-$(CONFIG_NEW_LEDS)		+= leds/
+obj-$(CONFIG_SWITCH)		+= switch/
 obj-$(CONFIG_INFINIBAND)	+= infiniband/
 obj-$(CONFIG_SGI_SN)		+= sn/
 obj-y				+= firmware/
@@ -111,3 +112,5 @@ obj-$(CONFIG_VLYNQ)		+= vlynq/
 obj-$(CONFIG_STAGING)		+= staging/
 obj-y				+= platform/
 obj-y				+= ieee802154/
+
+
diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
index 8aa2443182d..55b9e6bd4f1 100644
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -25,6 +25,7 @@
 #include <linux/resume-trace.h>
 #include <linux/rwsem.h>
 #include <linux/interrupt.h>
+#include <linux/timer.h>
 
 #include "../base.h"
 #include "power.h"
@@ -43,6 +44,9 @@ LIST_HEAD(dpm_list);
 
 static DEFINE_MUTEX(dpm_list_mtx);
 
+static void dpm_drv_timeout(unsigned long data);
+static DEFINE_TIMER(dpm_drv_wd, dpm_drv_timeout, 0, 0);
+
 /*
  * Set once the preparation of devices for a PM transition has started, reset
  * before starting to resume devices.  Protected by dpm_list_mtx.
@@ -432,6 +436,45 @@ static int device_resume(struct device *dev, pm_message_t state)
 }
 
 /**
+ *	dpm_drv_timeout - Driver suspend / resume watchdog handler
+ *	@data: struct device which timed out
+ *
+ * 	Called when a driver has timed out suspending or resuming.
+ * 	There's not much we can do here to recover so
+ * 	BUG() out for a crash-dump
+ *
+ */
+static void dpm_drv_timeout(unsigned long data)
+{
+	struct device *dev = (struct device *) data;
+
+	printk(KERN_EMERG "**** DPM device timeout: %s (%s)\n", dev_name(dev),
+	       (dev->driver ? dev->driver->name : "no driver"));
+	BUG();
+}
+
+/**
+ *	dpm_drv_wdset - Sets up driver suspend/resume watchdog timer.
+ *	@dev: struct device which we're guarding.
+ *
+ */
+static void dpm_drv_wdset(struct device *dev)
+{
+	dpm_drv_wd.data = (unsigned long) dev;
+	mod_timer(&dpm_drv_wd, jiffies + (HZ * 3));
+}
+
+/**
+ *	dpm_drv_wdclr - clears driver suspend/resume watchdog timer.
+ *	@dev: struct device which we're no longer guarding.
+ *
+ */
+static void dpm_drv_wdclr(struct device *dev)
+{
+	del_timer_sync(&dpm_drv_wd);
+}
+
+/**
  * dpm_resume - Execute "resume" callbacks for non-sysdev devices.
  * @state: PM transition of the system being carried out.
  *
@@ -689,7 +732,9 @@ static int dpm_suspend(pm_message_t state)
 		get_device(dev);
 		mutex_unlock(&dpm_list_mtx);
 
+		dpm_drv_wdset(dev);
 		error = device_suspend(dev, state);
+		dpm_drv_wdclr(dev);
 
 		mutex_lock(&dpm_list_mtx);
 		if (error) {
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 6aad99ec4e0..efdc34a8660 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -88,6 +88,19 @@ config VT_HW_CONSOLE_BINDING
 	 information. For framebuffer console users, please refer to
 	 <file:Documentation/fb/fbcon.txt>.
 
+config DEVMEM
+	bool "Memory device driver"
+	default y
+	help
+	  The memory driver provides two character devices, mem and kmem, which
+	  provide access to the system's memory. The mem device is a view of
+	  physical memory, and each byte in the device corresponds to the
+	  matching physical address. The kmem device is the same as mem, but
+	  the addresses correspond to the kernel's virtual address space rather
+	  than physical memory. These devices are standard parts of a Linux
+	  system and most users should say Y here. You might say N if very
+	  security conscience or memory is tight.
+
 config DEVKMEM
 	bool "/dev/kmem virtual device support"
 	default y
@@ -1116,6 +1129,10 @@ config DEVPORT
 	depends on ISA || PCI
 	default y
 
+config DCC_TTY
+	tristate "DCC tty driver"
+	depends on ARM
+
 source "drivers/s390/char/Kconfig"
 
 endmenu
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 19a79dd79ee..ee776cb54ec 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_IPMI_HANDLER)	+= ipmi/
 obj-$(CONFIG_HANGCHECK_TIMER)	+= hangcheck-timer.o
 obj-$(CONFIG_TCG_TPM)		+= tpm/
 
+obj-$(CONFIG_DCC_TTY)		+= dcc_tty.o
 obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
 
 obj-$(CONFIG_JS_RTC)		+= js-rtc.o
diff --git a/drivers/char/dcc_tty.c b/drivers/char/dcc_tty.c
new file mode 100644
index 00000000000..a787accdcb1
--- /dev/null
+++ b/drivers/char/dcc_tty.c
@@ -0,0 +1,326 @@
+/* drivers/char/dcc_tty.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/console.h>
+#include <linux/hrtimer.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/tty_flip.h>
+
+MODULE_DESCRIPTION("DCC TTY Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+
+static spinlock_t g_dcc_tty_lock = SPIN_LOCK_UNLOCKED;
+static struct hrtimer g_dcc_timer;
+static char g_dcc_buffer[16];
+static int g_dcc_buffer_head;
+static int g_dcc_buffer_count;
+static unsigned g_dcc_write_delay_usecs = 1;
+static struct tty_driver *g_dcc_tty_driver;
+static struct tty_struct *g_dcc_tty;
+static int g_dcc_tty_open_count;
+
+static void dcc_poll_locked(void)
+{
+	char ch;
+	int rch;
+	int written;
+
+	while (g_dcc_buffer_count) {
+		ch = g_dcc_buffer[g_dcc_buffer_head];
+		asm(
+			"mrc 14, 0, r15, c0, c1, 0\n"
+			"mcrcc 14, 0, %1, c0, c5, 0\n"
+			"movcc %0, #1\n"
+			"movcs %0, #0\n"
+			: "=r" (written)
+			: "r" (ch)
+		);
+		if (written) {
+			if (ch == '\n')
+				g_dcc_buffer[g_dcc_buffer_head] = '\r';
+			else {
+				g_dcc_buffer_head = (g_dcc_buffer_head + 1) % ARRAY_SIZE(g_dcc_buffer);
+				g_dcc_buffer_count--;
+				if (g_dcc_tty)
+					tty_wakeup(g_dcc_tty);
+			}
+			g_dcc_write_delay_usecs = 1;
+		} else {
+			if (g_dcc_write_delay_usecs > 0x100)
+				break;
+			g_dcc_write_delay_usecs <<= 1;
+			udelay(g_dcc_write_delay_usecs);
+		}
+	}
+
+	if (g_dcc_tty && !test_bit(TTY_THROTTLED, &g_dcc_tty->flags)) {
+		asm(
+			"mrc 14, 0, %0, c0, c1, 0\n"
+			"tst %0, #(1 << 30)\n"
+			"moveq %0, #-1\n"
+			"mrcne 14, 0, %0, c0, c5, 0\n"
+			: "=r" (rch)
+		);
+		if (rch >= 0) {
+			ch = rch;
+			tty_insert_flip_string(g_dcc_tty, &ch, 1);
+			tty_flip_buffer_push(g_dcc_tty);
+		}
+	}
+
+
+	if (g_dcc_buffer_count)
+		hrtimer_start(&g_dcc_timer, ktime_set(0, g_dcc_write_delay_usecs * NSEC_PER_USEC), HRTIMER_MODE_REL);
+	else
+		hrtimer_start(&g_dcc_timer, ktime_set(0, 20 * NSEC_PER_MSEC), HRTIMER_MODE_REL);
+}
+
+static int dcc_tty_open(struct tty_struct * tty, struct file * filp)
+{
+	int ret;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&g_dcc_tty_lock, irq_flags);
+	if (g_dcc_tty == NULL || g_dcc_tty == tty) {
+		g_dcc_tty = tty;
+		g_dcc_tty_open_count++;
+		ret = 0;
+	} else
+		ret = -EBUSY;
+	spin_unlock_irqrestore(&g_dcc_tty_lock, irq_flags);
+
+	printk("dcc_tty_open, tty %p, f_flags %x, returned %d\n", tty, filp->f_flags, ret);
+
+	return ret;
+}
+
+static void dcc_tty_close(struct tty_struct * tty, struct file * filp)
+{
+	printk("dcc_tty_close, tty %p, f_flags %x\n", tty, filp->f_flags);
+	if (g_dcc_tty == tty) {
+		if (--g_dcc_tty_open_count == 0)
+			g_dcc_tty = NULL;
+	}
+}
+
+static int dcc_write(const unsigned char *buf_start, int count)
+{
+	const unsigned char *buf = buf_start;
+	unsigned long irq_flags;
+	int copy_len;
+	int space_left;
+	int tail;
+
+	if (count < 1)
+		return 0;
+
+	spin_lock_irqsave(&g_dcc_tty_lock, irq_flags);
+	do {
+		tail = (g_dcc_buffer_head + g_dcc_buffer_count) % ARRAY_SIZE(g_dcc_buffer);
+		copy_len = ARRAY_SIZE(g_dcc_buffer) - tail;
+		space_left = ARRAY_SIZE(g_dcc_buffer) - g_dcc_buffer_count;
+		if (copy_len > space_left)
+			copy_len = space_left;
+		if (copy_len > count)
+			copy_len = count;
+		memcpy(&g_dcc_buffer[tail], buf, copy_len);
+		g_dcc_buffer_count += copy_len;
+		buf += copy_len;
+		count -= copy_len;
+		if (copy_len < count && copy_len < space_left) {
+			space_left -= copy_len;
+			copy_len = count;
+			if (copy_len > space_left) {
+				copy_len = space_left;
+			}
+			memcpy(g_dcc_buffer, buf, copy_len);
+			buf += copy_len;
+			count -= copy_len;
+			g_dcc_buffer_count += copy_len;
+		}
+		dcc_poll_locked();
+		space_left = ARRAY_SIZE(g_dcc_buffer) - g_dcc_buffer_count;
+	} while(count && space_left);
+	spin_unlock_irqrestore(&g_dcc_tty_lock, irq_flags);
+	return buf - buf_start;
+}
+
+static int dcc_tty_write(struct tty_struct * tty, const unsigned char *buf, int count)
+{
+	int ret;
+	/* printk("dcc_tty_write %p, %d\n", buf, count); */
+	ret = dcc_write(buf, count);
+	if (ret != count)
+		printk("dcc_tty_write %p, %d, returned %d\n", buf, count, ret);
+	return ret;
+}
+
+static int dcc_tty_write_room(struct tty_struct *tty)
+{
+	int space_left;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&g_dcc_tty_lock, irq_flags);
+	space_left = ARRAY_SIZE(g_dcc_buffer) - g_dcc_buffer_count;
+	spin_unlock_irqrestore(&g_dcc_tty_lock, irq_flags);
+	return space_left;
+}
+
+static int dcc_tty_chars_in_buffer(struct tty_struct *tty)
+{
+	int ret;
+	asm(
+		"mrc 14, 0, %0, c0, c1, 0\n"
+		"mov %0, %0, LSR #30\n"
+		"and %0, %0, #1\n"
+		: "=r" (ret)
+	);
+	return ret;
+}
+
+static void dcc_tty_unthrottle(struct tty_struct * tty)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&g_dcc_tty_lock, irq_flags);
+	dcc_poll_locked();
+	spin_unlock_irqrestore(&g_dcc_tty_lock, irq_flags);
+}
+
+static enum hrtimer_restart dcc_tty_timer_func(struct hrtimer *timer)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&g_dcc_tty_lock, irq_flags);
+	dcc_poll_locked();
+	spin_unlock_irqrestore(&g_dcc_tty_lock, irq_flags);
+	return HRTIMER_NORESTART;
+}
+
+void dcc_console_write(struct console *co, const char *b, unsigned count)
+{
+#if 1
+	dcc_write(b, count);
+#else
+	/* blocking printk */
+	while (count > 0) {
+		int written;
+		written = dcc_write(b, count);
+		if (written) {
+			b += written;
+			count -= written;
+		}
+	}
+#endif
+}
+
+static struct tty_driver *dcc_console_device(struct console *c, int *index)
+{
+	*index = 0;
+	return g_dcc_tty_driver;
+}
+
+static int __init dcc_console_setup(struct console *co, char *options)
+{
+	if (co->index != 0)
+		return -ENODEV;
+	return 0;
+}
+
+
+static struct console dcc_console =
+{
+	.name		= "ttyDCC",
+	.write		= dcc_console_write,
+	.device		= dcc_console_device,
+	.setup		= dcc_console_setup,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+};
+
+static struct tty_operations dcc_tty_ops = {
+	.open = dcc_tty_open,
+	.close = dcc_tty_close,
+	.write = dcc_tty_write,
+	.write_room = dcc_tty_write_room,
+	.chars_in_buffer = dcc_tty_chars_in_buffer,
+	.unthrottle = dcc_tty_unthrottle,
+};
+
+static int __init dcc_tty_init(void)
+{
+	int ret;
+
+	hrtimer_init(&g_dcc_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	g_dcc_timer.function = dcc_tty_timer_func;
+
+	g_dcc_tty_driver = alloc_tty_driver(1);
+	if (!g_dcc_tty_driver) {
+		printk(KERN_ERR "dcc_tty_probe: alloc_tty_driver failed\n");
+		ret = -ENOMEM;
+		goto err_alloc_tty_driver_failed;
+	}
+	g_dcc_tty_driver->owner = THIS_MODULE;
+	g_dcc_tty_driver->driver_name = "dcc";
+	g_dcc_tty_driver->name = "ttyDCC";
+	g_dcc_tty_driver->major = 0; // auto assign
+	g_dcc_tty_driver->minor_start = 0;
+	g_dcc_tty_driver->type = TTY_DRIVER_TYPE_SERIAL;
+	g_dcc_tty_driver->subtype = SERIAL_TYPE_NORMAL;
+	g_dcc_tty_driver->init_termios = tty_std_termios;
+	g_dcc_tty_driver->flags = TTY_DRIVER_RESET_TERMIOS | TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
+	tty_set_operations(g_dcc_tty_driver, &dcc_tty_ops);
+	ret = tty_register_driver(g_dcc_tty_driver);
+	if (ret) {
+		printk(KERN_ERR "dcc_tty_probe: tty_register_driver failed, %d\n", ret);
+		goto err_tty_register_driver_failed;
+	}
+	tty_register_device(g_dcc_tty_driver, 0, NULL);
+
+	register_console(&dcc_console);
+	hrtimer_start(&g_dcc_timer, ktime_set(0, 0), HRTIMER_MODE_REL);
+
+	return 0;
+
+err_tty_register_driver_failed:
+	put_tty_driver(g_dcc_tty_driver);
+	g_dcc_tty_driver = NULL;
+err_alloc_tty_driver_failed:
+	return ret;
+}
+
+static void  __exit dcc_tty_exit(void)
+{
+	int ret;
+
+	tty_unregister_device(g_dcc_tty_driver, 0);
+	ret = tty_unregister_driver(g_dcc_tty_driver);
+	if (ret < 0) {
+		printk(KERN_ERR "dcc_tty_remove: tty_unregister_driver failed, %d\n", ret);
+	} else {
+		put_tty_driver(g_dcc_tty_driver);
+	}
+	g_dcc_tty_driver = NULL;
+}
+
+module_init(dcc_tty_init);
+module_exit(dcc_tty_exit);
+
+
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
index aef3fb42150..6df298845b3 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -93,6 +93,7 @@ static inline int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
 }
 #endif
 
+#if defined(CONFIG_DEVMEM) || defined(CONFIG_DEVKMEM)
 #ifdef CONFIG_STRICT_DEVMEM
 static inline int range_is_allowed(unsigned long pfn, unsigned long size)
 {
@@ -118,7 +119,9 @@ static inline int range_is_allowed(unsigned long pfn, unsigned long size)
 	return 1;
 }
 #endif
+#endif
 
+#ifdef CONFIG_DEVMEM
 void __attribute__((weak)) unxlate_dev_mem_ptr(unsigned long phys, void *addr)
 {
 }
@@ -267,6 +270,9 @@ static ssize_t write_mem(struct file * file, const char __user * buf,
 	*ppos += written;
 	return written;
 }
+#endif	/* CONFIG_DEVMEM */
+
+#if defined(CONFIG_DEVMEM) || defined(CONFIG_DEVKMEM)
 
 int __attribute__((weak)) phys_mem_access_prot_allowed(struct file *file,
 	unsigned long pfn, unsigned long size, pgprot_t *vma_prot)
@@ -353,6 +359,7 @@ static int mmap_mem(struct file * file, struct vm_area_struct * vma)
 	}
 	return 0;
 }
+#endif	/* CONFIG_DEVMEM */
 
 #ifdef CONFIG_DEVKMEM
 static int mmap_kmem(struct file * file, struct vm_area_struct * vma)
@@ -732,6 +739,8 @@ static loff_t null_lseek(struct file * file, loff_t offset, int orig)
 	return file->f_pos = 0;
 }
 
+#if defined(CONFIG_DEVMEM) || defined(CONFIG_DEVKMEM) || defined(CONFIG_DEVPORT)
+
 /*
  * The memory devices use the full 32/64 bits of the offset, and so we cannot
  * check against negative addresses: they are ok. The return value is weird,
@@ -763,10 +772,14 @@ static loff_t memory_lseek(struct file * file, loff_t offset, int orig)
 	return ret;
 }
 
+#endif
+
+#if defined(CONFIG_DEVMEM) || defined(CONFIG_DEVKMEM) || defined(CONFIG_DEVPORT)
 static int open_port(struct inode * inode, struct file * filp)
 {
 	return capable(CAP_SYS_RAWIO) ? 0 : -EPERM;
 }
+#endif
 
 #define zero_lseek	null_lseek
 #define full_lseek      null_lseek
@@ -776,6 +789,7 @@ static int open_port(struct inode * inode, struct file * filp)
 #define open_kmem	open_mem
 #define open_oldmem	open_mem
 
+#ifdef CONFIG_DEVMEM
 static const struct file_operations mem_fops = {
 	.llseek		= memory_lseek,
 	.read		= read_mem,
@@ -784,6 +798,7 @@ static const struct file_operations mem_fops = {
 	.open		= open_mem,
 	.get_unmapped_area = get_unmapped_area_mem,
 };
+#endif
 
 #ifdef CONFIG_DEVKMEM
 static const struct file_operations kmem_fops = {
@@ -872,7 +887,9 @@ static const struct memdev {
 	const struct file_operations *fops;
 	struct backing_dev_info *dev_info;
 } devlist[] = {
+#ifdef CONFIG_DEVMEM
 	 [1] = { "mem", 0, &mem_fops, &directly_mappable_cdev_bdi },
+#endif
 #ifdef CONFIG_DEVKMEM
 	 [2] = { "kmem", 0, &kmem_fops, &directly_mappable_cdev_bdi },
 #endif
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index ff57c40e9b8..08bc0d66ac7 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -284,7 +284,7 @@ static inline void cpufreq_debug_disable_ratelimit(void) { return; }
 static unsigned long l_p_j_ref;
 static unsigned int  l_p_j_ref_freq;
 
-static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
+void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
 {
 	if (ci->flags & CPUFREQ_CONST_LOOPS)
 		return;
@@ -305,7 +305,7 @@ static void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
 	}
 }
 #else
-static inline void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
+inline void adjust_jiffies(unsigned long val, struct cpufreq_freqs *ci)
 {
 	return;
 }
@@ -325,11 +325,12 @@ void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state)
 	struct cpufreq_policy *policy;
 
 	BUG_ON(irqs_disabled());
-
+	
+#ifndef CONFIG_ARCH_AK98
 	freqs->flags = cpufreq_driver->flags;
+#endif
 	dprintk("notification %u of frequency transition to %u kHz\n",
 		state, freqs->new);
-
 	policy = per_cpu(cpufreq_cpu_data, freqs->cpu);
 	switch (state) {
 
@@ -338,6 +339,7 @@ void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state)
 		 * which is not equal to what the cpufreq core thinks is
 		 * "old frequency".
 		 */
+	#ifndef CONFIG_ARCH_AK98
 		if (!(cpufreq_driver->flags & CPUFREQ_CONST_LOOPS)) {
 			if ((policy) && (policy->cpu == freqs->cpu) &&
 			    (policy->cur) && (policy->cur != freqs->old)) {
@@ -347,6 +349,7 @@ void cpufreq_notify_transition(struct cpufreq_freqs *freqs, unsigned int state)
 				freqs->old = policy->cur;
 			}
 		}
+	#endif
 		srcu_notifier_call_chain(&cpufreq_transition_notifier_list,
 				CPUFREQ_PRECHANGE, freqs);
 		adjust_jiffies(CPUFREQ_PRECHANGE, freqs);
diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
index 4b34ade2332..5211924e45f 100644
--- a/drivers/cpufreq/cpufreq_ondemand.c
+++ b/drivers/cpufreq/cpufreq_ondemand.c
@@ -576,7 +576,9 @@ static void do_dbs_timer(struct work_struct *work)
 	/* We want all CPUs to do sampling nearly on same jiffy */
 	int delay = usecs_to_jiffies(dbs_tuners_ins.sampling_rate);
 
-	delay -= jiffies % delay;
+	if (num_online_cpus() > 1)
+		delay -= jiffies % delay;
+
 	mutex_lock(&dbs_info->timer_mutex);
 
 	/* Common NORMAL_SAMPLE setup */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index e8fe7f169e2..d9223558a93 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -778,4 +778,22 @@ config SCx200_ACB
 	  This support is also available as a module.  If so, the module
 	  will be called scx200_acb.
 
+config I2C_AK88
+	tristate "AK88 I2C Driver"
+	depends on ARCH_AK88
+	help
+	  Say Y here to enable support for I2C driver for AK88.
+
+config I2C_AK98
+	tristate "AK98 I2C Driver"
+	depends on ARCH_AK98
+	help
+	  Say Y here to enable support for I2C driver for AK98.
+
+config I2C_AW9523_GPIO
+	tristate "AW9523 EXPEND GPIO Driver"
+	depends on ARCH_AK98 && I2C_AK98
+	help
+	  Say Y here to enable support AW9523 expand GPIO driver.
+
 endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index ff937ac69f5..276eee0ee42 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -74,6 +74,9 @@ obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
 obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
 obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
 obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
+obj-$(CONFIG_I2C_AK88)		+= i2c-ak88.o
+obj-$(CONFIG_I2C_AK98)		+= i2c-ak98.o
+obj-$(CONFIG_I2C_AW9523_GPIO)	+= aw9523.o
 
 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/i2c/busses/aw9523.c b/drivers/i2c/busses/aw9523.c
new file mode 100755
index 00000000000..5a37569d8fc
--- /dev/null
+++ b/drivers/i2c/busses/aw9523.c
@@ -0,0 +1,611 @@
+/*
+ *  ak98 aw9523.c - expand 16 bit I/O ports
+ *
+ *  Copyright (C) 2011 Anyka electronic Ltd
+ *
+ *  Derived from drivers/i2c/busses/aw9523.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; 
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/i2c/aw9523.h>
+#include <linux/irq.h>
+#include <mach/irqs.h>
+#include <mach/gpio.h>
+#include <linux/interrupt.h>
+
+
+//#define AW9523_DEBUG
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef AW9523_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+
+static struct aw9523_chip *chip;
+static int g_input_update=0;
+
+
+static void		aw9523_gpioirq_enable(unsigned int irq)
+{
+	PDEBUG("Entering %s %u\n", __FUNCTION__, irq); 
+	ak98_gpio_intcfg(ak98_irq_to_gpio(irq), AK98_GPIO_INT_ENABLE);
+}
+static void		aw9523_gpioirq_disable(unsigned int irq)
+{
+	PDEBUG("Entering %s %u\n", __FUNCTION__, irq);
+	ak98_gpio_intcfg(ak98_irq_to_gpio(irq), AK98_GPIO_INT_DISABLE);
+}
+
+static void aw9523_gpioirq_mask(unsigned int irq)
+{
+	unsigned pino = irq - chip->pdata->irq_base + chip->pdata->gpio_base;
+	int index, off;
+
+	PDEBUG("Entering %s %u\n", __FUNCTION__, irq);
+	pino -= AW9523_GPIO_P00;
+	
+	index = pino / 8;
+	off = pino % 8;
+
+	if (index)
+	{
+		chip->irq_mask1 |= (1u << off);
+	}
+	else
+	{
+		chip->irq_mask0 |= (1u << off);
+	}
+}
+
+static void aw9523_gpioirq_unmask(unsigned int irq)
+{
+	unsigned pino = irq - chip->pdata->irq_base + chip->pdata->gpio_base;
+	int index, off;
+
+	PDEBUG("Entering %s %u\n", __FUNCTION__, irq);
+	pino -= AW9523_GPIO_P00;
+	
+	index = pino / 8;
+	off = pino % 8;
+
+	if (index)
+	{
+		chip->irq_mask1 &= ~(1u << off);
+	}
+	else
+	{
+		chip->irq_mask0 &= ~(1u << off);
+	}
+}
+
+static struct irq_chip aw9523_gpio_chip = {
+	.name = "aw9523_irq",
+	.mask_ack = aw9523_gpioirq_mask,
+	.mask = aw9523_gpioirq_mask,
+	.unmask = aw9523_gpioirq_unmask,
+	.enable = aw9523_gpioirq_unmask,//,aw9523_gpioirq_enable,
+	.disable = aw9523_gpioirq_mask,
+};
+
+static int aw9523_write_reg(struct i2c_client *client, int reg, uint8_t val)
+{
+	int ret;
+
+	ret = i2c_smbus_write_byte_data(client, reg, val);
+	if (ret < 0) {
+		dev_err(&client->dev, "failed reading register\n");
+		return ret;
+	}
+	return 0;
+}
+
+
+static int aw9523_read_reg(struct i2c_client *client, int reg, uint8_t *val)
+{
+	int ret;
+	
+	ret = i2c_smbus_read_byte_data(client, reg);
+	if (ret < 0) {
+		dev_err(&client->dev, "failed writing register\n");
+		return ret;
+	}
+
+	*val = (uint8_t)ret;
+	return 0;
+}
+
+
+
+//unsigned int irq, struct irq_desc *desc
+static void aw9523_irq_dispatch(int irqno, void *dev_id)
+{
+	uint8_t input0, input1;
+	int i, off;
+
+	PDEBUG("Entering %s ......  %d\n", __FUNCTION__, irqno);
+	aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT0, &input0);	
+	PDEBUG("input0: 0x%x\n", input0);
+	aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT1, &input1);
+	PDEBUG("input1: 0x%x\n", input1);
+	
+	if (input0 != chip->reg_input0)
+	{
+		PDEBUG("old input0: 0x%x\n", chip->reg_input0);
+		for (i = AW9523_GPIO_P00; i<=AW9523_GPIO_P07; i++)
+		{
+			off = i-AW9523_GPIO_P00;
+			if ( ((input0 & (1u << off)) != (chip->reg_input0 & (1u << off))) &&
+				((chip->irq_mask0 & (1u << off)) == 0) )
+			{
+				//pin i had intrrupt		
+				PDEBUG("dispatch:  %d\n", i - chip->pdata->gpio_base + chip->pdata->irq_base);
+				generic_handle_irq(i - chip->pdata->gpio_base + chip->pdata->irq_base);
+			}
+		}
+		chip->reg_input0 = input0;
+	}
+
+	if (input1 != chip->reg_input1)
+	{
+		for (i = AW9523_GPIO_P10; i<=AW9523_GPIO_P17; i++)
+		{
+			off = i-AW9523_GPIO_P10;
+			if ( ((input1 & (1u << off)) != (chip->reg_input1 & (1u << off))) &&
+				((chip->irq_mask1 & (1u << off)) == 0) )
+			{
+				//pin i had intrrupt
+				generic_handle_irq(i - chip->pdata->gpio_base + chip->pdata->irq_base);
+			}
+		}
+		chip->reg_input1 = input1;
+	}
+
+	enable_irq(chip->pdata->parent_irq);
+
+}
+
+static void aw9523_irq_setup( void )
+{
+	int i;
+	
+	chip->irq_mask0 = chip->irq_mask1 = 0;
+	
+	for (i=IRQ_AW9523_P00; i<=IRQ_AW9523_P17; i++)
+	{
+		set_irq_chip(i, &aw9523_gpio_chip);
+		set_irq_handler(i, handle_level_irq);		
+		set_irq_flags(i, IRQF_VALID);
+	}
+}
+
+
+int aw9523_gpio_to_irq(unsigned int pino)
+{
+	return chip->pdata->irq_base + (pino - chip->pdata->gpio_base);
+}
+EXPORT_SYMBOL(aw9523_gpio_to_irq);
+
+int aw9523_irq_to_gpio(unsigned int irq)
+{
+	return chip->pdata->gpio_base + (irq - chip->pdata->irq_base);
+}
+
+
+int aw9523_gpio_intcfg(unsigned int pino, unsigned int enable)
+{
+	int ret, index, off;
+	uint8_t reg_val;
+
+	pino -= AW9523_GPIO_P00;
+
+	PDEBUG("%s  %u  %u\n", __FUNCTION__, pino, enable);
+	if(pino > PMAX) 
+	{
+		panic("expand GPIO not existing\n");
+		return -1;
+	}
+	
+	index = pino / 8;
+	off = pino % 8;
+
+	if (index)
+	{
+		/* 0: enable   1: disable*/
+		if (enable == AK98_GPIO_INT_ENABLE)
+		{
+			reg_val = chip->reg_int1 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_INTN_PORT1, reg_val);
+		}
+		else if (enable == AK98_GPIO_INT_DISABLE)
+		{
+			reg_val = chip->reg_int1 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_INTN_PORT1, reg_val);
+		}
+		else
+			panic("Bad parameter passed to aw9523_int_cfg");
+		chip->reg_int1 = reg_val;
+	}
+	else
+	{
+		if (enable == AK98_GPIO_INT_ENABLE)
+		{
+			reg_val = chip->reg_int0 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_INTN_PORT0, reg_val);
+		}
+		else if (enable == AK98_GPIO_INT_DISABLE)
+		{
+			reg_val = chip->reg_int0 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_INTN_PORT0, reg_val);
+		}
+		else
+			panic("Bad parameter passed to aw9523_int_cfg");
+		chip->reg_int0 = reg_val;
+	}
+
+	return 0;
+}
+
+EXPORT_SYMBOL(aw9523_gpio_intcfg);
+
+
+int aw9523_gpio_dircfg(unsigned int pino, unsigned int direction)
+{
+	int ret, index, off;
+	uint8_t reg_val;
+
+	pino -= AW9523_GPIO_P00;
+
+	PDEBUG("%s  %u  %u\n", __FUNCTION__, pino, direction);
+	if(pino > PMAX) 
+	{
+		panic("expand GPIO not existing\n");
+		return -1;
+	}
+	
+	index = pino / 8;
+	off = pino % 8;
+
+	if(index) 
+	{
+		/* 0: OUTPUT  1: INPUT*/
+		if(direction == AK98_GPIO_DIR_INPUT)
+		{
+			reg_val = chip->reg_direction1 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_CFG_PORT1, reg_val);
+		}
+		else if(direction == AK98_GPIO_DIR_OUTPUT){
+			reg_val = chip->reg_direction1 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_CFG_PORT1, reg_val);
+		} 
+		else 
+			panic("AW9523 GPIO direction error");
+		if(ret)
+		{
+			PDEBUG("%s Error happend\n", __FUNCTION__);
+			return ret;
+		}
+		chip->reg_direction1 = reg_val;
+	}
+	else 
+	{
+		if(direction == AK98_GPIO_DIR_INPUT){
+			reg_val = chip->reg_direction0 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_CFG_PORT0, reg_val);
+		}
+		else if(direction == AK98_GPIO_DIR_OUTPUT){
+			reg_val = chip->reg_direction0 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_CFG_PORT0, reg_val);
+		} else panic("AW9523 GPIO direction error");
+		if(ret)
+			return ret;
+		chip->reg_direction0 = reg_val;
+	}
+	g_input_update = 1;	
+	return 0;	
+}
+EXPORT_SYMBOL(aw9523_gpio_dircfg);
+
+
+int aw9523_gpio_setpin(unsigned int pino, unsigned int level)
+{
+	int ret, index, off;
+	uint8_t reg_val;
+
+	pino -= AW9523_GPIO_P00;
+
+	PDEBUG("%s  %d  %d\n", __FUNCTION__, pino, level);
+	if(pino > PMAX) {
+		panic("expand GPIO not existing\n");
+		return -1;
+	}
+	
+	index = pino / 8;
+	off = pino % 8;
+
+	/* 1: output HIGH   0: output LOW*/
+	if(index) 
+	{
+		if(level == AK98_GPIO_OUT_HIGH)
+		{
+			reg_val = chip->reg_output1 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_OUTPUT_PORT1, reg_val);
+		}
+		else if(level == AK98_GPIO_OUT_LOW)
+		{
+			reg_val = chip->reg_output1 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_OUTPUT_PORT1, reg_val);
+		} 
+		else 
+			panic("AW9523 GPIO level error");
+		if(ret)
+			return -1;
+		chip->reg_output1 = reg_val;
+		
+	}
+	else 
+	{
+		if(level == AK98_GPIO_OUT_HIGH) {
+			reg_val = chip->reg_output0 | (1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_OUTPUT_PORT0, reg_val);
+		}
+		else if(level == AK98_GPIO_OUT_LOW){
+			reg_val = chip->reg_output0 & ~(1u << off);
+			ret = aw9523_write_reg(chip->client, AW9523_REG_OUTPUT_PORT0, reg_val);
+		} 
+		else panic("AW9523 GPIO level error");
+		if(ret)
+			return -1;
+		chip->reg_output0 = reg_val;
+	}	
+	/* input state may change*/	
+	g_input_update = 1;
+	return 0;
+}
+EXPORT_SYMBOL(aw9523_gpio_setpin);
+
+int aw9523_gpio_getpin(unsigned int pino)
+{
+	int ret=0, index, off;
+	uint8_t reg_val;
+	
+	pino -= AW9523_GPIO_P00;
+
+	if(pino > PMAX) {
+		panic("expand GPIO not existing\n");
+		return -1;
+	}
+
+	//PDEBUG("%s  %d  %d\n", __FUNCTION__, pino, g_input_update);
+	index = pino / 8;
+	off = pino % 8;
+	
+	if(index) 
+	{
+		if (g_input_update)
+		{
+			ret = aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT1, &reg_val);
+			chip->reg_input1 = reg_val;
+			g_input_update = 0;
+		}
+		else
+			reg_val = chip->reg_input1;
+	}
+	else
+	{
+		if (g_input_update)
+		{
+			ret = aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT0, &reg_val);
+			chip->reg_input0 = reg_val;
+			g_input_update = 0;
+		}
+		else
+			reg_val = chip->reg_input0;
+	}
+	
+	if(ret < 0)
+		return 0;
+
+	//printk("--input0: 0x%x\n", reg_val);
+	return (reg_val & (1u << off)) ? 1 : 0;
+}
+EXPORT_SYMBOL(aw9523_gpio_getpin);
+
+/* function: set group port0 working module
+ * param module:
+ *	1: push-pull  0: open-drain
+ * param pino: pin number
+ */
+static int aw9523_gpio_setmod(int mode)
+{
+	uint8_t reg_val = 0;
+	int ret;
+	
+	if (mode == AW9523_MOD_PUSHPULL)
+		reg_val = (1u << 4);
+	else if (mode == AW9523_MOD_OPENDRAIN)
+		;
+	else 
+		panic("AW9523 GPIO mode error");
+	
+	ret = aw9523_write_reg(chip->client, AW9523_REG_GPOMD, reg_val);
+	if(ret)
+		return ret;
+	chip->reg_setmod = reg_val;
+	
+	return 0;
+}
+
+static int aw9523_init_gpio(struct aw9523_chip *chip)
+{
+	int ret, i;
+
+	
+	/* default mode of P00 - P07 is OPEN-DRAIN*/
+	/* setup gpio push-pull */
+	ret = aw9523_gpio_setmod(AW9523_MOD_PUSHPULL);
+
+	if (ret)
+		return -1;
+	
+	for (i=AW9523_GPIO_P00; i<=AW9523_GPIO_P17; i++)
+	{
+		ak98_gpio_dircfg(i, AK98_GPIO_DIR_INPUT);
+		ak98_gpio_intcfg(i, AK98_GPIO_INT_DISABLE);		
+	}
+		
+	return 0;
+}
+
+#if 0
+static void aw9523_print_regs(void)
+{
+	PDEBUG("output0: 0x%x\n", chip->reg_output0);	
+	PDEBUG("output1: 0x%x\n", chip->reg_output1);	
+	PDEBUG("dir 0: 0x%x\n", chip->reg_direction0);	
+	PDEBUG("dir 1: 0x%x\n", chip->reg_direction1);	
+	PDEBUG("mode: 0x%x\n", chip->reg_setmod);	
+	PDEBUG("int 0: 0x%x\n", chip->reg_int0);	
+	PDEBUG("int 1: 0x%x\n", chip->reg_int1);	
+	PDEBUG("input 0: 0x%x\n", chip->reg_input0);
+	PDEBUG("input 1: 0x%x\n", chip->reg_input1);
+}
+#endif
+
+static void aw9523_get_regs_value(struct aw9523_chip *chip)
+{
+
+	aw9523_read_reg(chip->client, AW9523_REG_OUTPUT_PORT0, &chip->reg_output0);
+	aw9523_read_reg(chip->client, AW9523_REG_OUTPUT_PORT1, &chip->reg_output1);
+	aw9523_read_reg(chip->client, AW9523_REG_CFG_PORT0, &chip->reg_direction0);
+	aw9523_read_reg(chip->client, AW9523_REG_CFG_PORT1, &chip->reg_direction1);
+	aw9523_read_reg(chip->client, AW9523_REG_GPOMD, &chip->reg_setmod);
+	aw9523_read_reg(chip->client, AW9523_REG_INTN_PORT0, &chip->reg_int0);
+	aw9523_read_reg(chip->client, AW9523_REG_INTN_PORT1, &chip->reg_int1);
+	aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT0, &chip->reg_input0);
+	aw9523_read_reg(chip->client, AW9523_REG_INPUT_PORT1, &chip->reg_input1);
+}
+
+
+static irqreturn_t aw9523_gpio_irq(int irqno, void *dev_id)
+{
+
+	PDEBUG("Entering %s %u\n", __FUNCTION__, irqno);
+
+	disable_irq_nosync(chip->pdata->parent_irq);	
+	aw9523_irq_dispatch(irqno, dev_id);	
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit aw9523_probe(struct i2c_client *client,
+				   const struct i2c_device_id *id)
+{
+	struct aw9523_platform_data *pdata = client->dev.platform_data;
+	int ret, i;
+
+	if (!pdata) 
+	{
+		dev_err(&client->dev, "platform data is required!\n");
+		return -EINVAL;
+	}
+	chip = kzalloc(sizeof(struct aw9523_chip), GFP_KERNEL);
+	if (chip == NULL) {
+		dev_err(&client->dev, "failed to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	chip->client = client;
+	chip->reg_setmod = pdata->p0xmod;
+	chip->pdata = pdata;
+		
+	/* initialize cached registers from their original values.
+	 * we can't share this chip with another i2c master.
+	 */
+	
+
+	i2c_set_clientdata(client, chip);
+	mutex_init(&(chip->aw9523_lock));
+
+	ret = aw9523_init_gpio(chip);
+	if (ret != 0)
+		goto out_failed;
+	
+	aw9523_get_regs_value(chip);
+	aw9523_irq_setup();
+
+	for (i=0; i<pdata->npins; i++)
+		ak98_gpio_set(&(pdata->gpios[i]));
+	
+	ret = request_threaded_irq(chip->pdata->parent_irq, NULL, aw9523_gpio_irq, IRQF_ONESHOT, "aw9523_irq", chip);
+	if (ret != 0) 
+	{
+		dev_err(&(client->dev), "cannot claim IRQ %d\n", chip->pdata->parent_irq);
+		goto out_failed;
+	}
+
+	PDEBUG("Load AW9523 successfully.\n");
+	return 0;
+
+out_failed:
+	kfree(chip);
+	return ret;
+}
+
+static int aw9523_remove(struct i2c_client *client)
+{
+	mutex_destroy(&chip->aw9523_lock);
+	free_irq(chip->pdata->parent_irq, chip);
+	kfree(chip);
+
+	return 0;
+}
+static const struct i2c_device_id aw9523_id[] = {
+	{ "aw9523_ext", 16},
+	{ },
+};
+
+static struct i2c_driver aw9523_driver = {
+	.driver = {
+		.name	= "aw9523_ext",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= aw9523_probe,
+	.remove		= aw9523_remove,
+	.id_table	= aw9523_id,
+};
+
+static int __init aw9523_init(void)
+{
+	
+	return i2c_add_driver(&aw9523_driver);
+}
+/* register after i2c postcore initcall and before
+ * subsys initcalls that may rely on these GPIOs
+ */
+subsys_initcall(aw9523_init);
+
+static void __exit aw9523_exit(void)
+{
+	i2c_del_driver(&aw9523_driver);
+}
+module_exit(aw9523_exit);
+MODULE_AUTHOR("Anyka zhou_wenyong@anyka.oa");
+MODULE_DESCRIPTION("GPIO expander driver for AW9523");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-ak88.c b/drivers/i2c/busses/i2c-ak88.c
new file mode 100644
index 00000000000..a139c5a2e77
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ak88.c
@@ -0,0 +1,570 @@
+/* 
+ * linux/drivers/i2c/busses/i2c-ak880x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/gpio.h>
+
+#define I2CSCLPIN AK88_DGPIO_0
+#define I2CSDAPIN AK88_DGPIO_1
+
+static unsigned char IICDS = 0;
+
+/* i2c controller state */
+
+enum ak880x_i2c_state {
+	STATE_IDLE,
+	STATE_START,
+	STATE_READ,
+	STATE_WRITE,
+	STATE_STOP
+};
+
+struct ak880x_i2c {
+	spinlock_t		lock;
+	wait_queue_head_t	wait;
+
+	struct i2c_msg		*msg;
+	unsigned int		msg_num;
+	unsigned int		msg_idx;
+	unsigned int		msg_ptr;
+
+	unsigned int		tx_setup;
+
+	enum ak880x_i2c_state	state;
+
+	void __iomem		*regs;
+	struct clk		*clk;
+	struct device		*dev;
+	struct resource		*irq;
+	struct resource		*ioarea;
+	struct i2c_adapter	adap;
+};
+
+/* default platform data to use if not supplied in the platform_device
+*/
+
+static struct ak880x_platform_i2c ak880x_i2c_default_platform = {
+	.flags		= 0,
+	.slave_addr	= 0x10,
+	.bus_freq	= 100*1000,
+	.max_freq	= 400*1000,
+//	.sda_delay	= S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+
+/* ak880x_i2c_get_platformdata
+ *
+ * get the platform data associated with the given device, or return
+ * the default if there is none
+ */
+
+static inline struct ak880x_platform_i2c *ak880x_i2c_get_platformdata(struct device *dev)
+{
+	if (dev->platform_data != NULL)
+		return (struct ak880x_platform_i2c *)dev->platform_data;
+
+	return &ak880x_i2c_default_platform;
+}
+
+static inline void set_scl(int high)
+{
+	ak880x_gpio_setpin(I2CSCLPIN, high);
+}
+static inline void set_sda(int high)
+{
+	ak880x_gpio_setpin(I2CSDAPIN, high);
+}
+static inline void scl_in(void)
+{
+	ak880x_gpio_cfgpin(I2CSCLPIN, AK88_GPIO_IN_0);
+}
+static inline void scl_out(void)
+{
+	ak880x_gpio_cfgpin(I2CSCLPIN, AK88_GPIO_OUT_0);
+}
+static inline void sda_in(void)
+{
+	ak880x_gpio_cfgpin(I2CSDAPIN, AK88_GPIO_IN_0);
+}
+static inline void sda_out(void)
+{
+	ak880x_gpio_cfgpin(I2CSDAPIN, AK88_GPIO_OUT_0);
+}
+static inline int get_sda(void)
+{
+	int ret;
+	ret = ak880x_gpio_getpin(I2CSDAPIN);
+	if(ret)
+		return 1;
+	else 
+		return 0;
+}
+
+static void i2c_message_start(struct ak880x_i2c *i2c, struct i2c_msg *msg)
+{
+	
+}
+
+/* #define T 800 */
+#define T 8
+/*
+ * return 1 if get an ack, else return 0
+ */
+static inline int wait_ack(void)
+{
+	int ret;
+	set_scl(0);
+	sda_in();
+	udelay(T/2);
+	set_scl(1);
+	udelay(T/4);
+	ret = get_sda();
+	udelay(T/4);
+
+	set_scl(0);
+	//udelay(1300);
+	return !ret;
+}
+
+/* #define T0 200 */
+#define T0 10
+static inline void start_condition(void)
+{
+	sda_out();
+
+	set_sda(1);
+	set_scl(1);
+	udelay(T0);
+
+	set_sda(0);
+	udelay(T0);
+
+	set_scl(0);
+	udelay(T0);
+}
+static inline void stop_condition(void)
+{
+	sda_out();
+
+	set_sda(0);
+	udelay(T0);
+
+	set_scl(1);
+	udelay(T0);
+
+	set_sda(1);
+	udelay(T0);
+}
+
+#if 0
+// anyka version
+static int write_byte(unsigned char data)
+{
+    unsigned char i,ret;
+    unsigned char mask_bit[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01};
+	sda_out();
+
+    for (i=0; i<8; i++)
+    {
+        if (data & mask_bit[i])
+        {
+            set_sda(1);
+        } else
+        {
+            set_sda(0);
+        }
+        udelay(5);
+        set_scl(1);
+        udelay(10);
+        set_scl(0);
+        udelay(5);
+    }
+    //read the bit of answer
+	set_sda(1);
+    sda_in();
+    udelay(5);
+    set_scl(1);
+    udelay(5);
+    if (get_sda() == 0)
+        ret = 0;
+    else ret = -1;
+    udelay(5);
+    set_scl(0);
+    udelay(5);
+    sda_out();
+    return ret;
+}
+
+static unsigned char read_byte(void)
+{
+    unsigned char i, ret = 0;
+	sda_in();
+    for (i=0; i<8; i++)
+    {
+        udelay(5);
+        set_scl(1);
+
+        ret <<= 1;
+        if (get_sda() == 1)
+        {
+            ret += 1;
+        }
+
+        udelay(10);
+        set_scl(0);
+        udelay(5);
+    }
+
+    //write the bit of answer
+    sda_out();
+    //set_sccb_pin(gpio.sio_d);
+	set_sda(1);
+    udelay(5);
+    //set_sccb_pin(gpio.sio_c);
+	set_scl(1);
+    udelay(5);
+    //clr_sccb_pin(gpio.sio_c);
+	set_scl(0);
+    udelay(5);
+
+    return ret;
+}
+#endif
+
+
+
+
+#if 1
+// samsung version
+static int write_byte(unsigned char data)
+{
+	int j;
+	sda_out();
+	for(j=7; j>=0; --j)
+	{
+		set_scl(0);
+		udelay(T/4);
+		set_sda((data>>j) & 0x1);
+		udelay(T/4);
+		set_scl(1);
+		udelay(T/2);
+	}
+	set_scl(0);
+	#if 0
+	wait_ack();
+	sda_out();
+	set_sda(1);
+	return 0;
+	#endif
+	if(wait_ack())
+	{
+		sda_out();
+		set_sda(1);
+	}
+	else
+	{
+		//stop_condition();
+		return -1;
+	}
+	return 0;	
+}
+static unsigned char read_byte(void)
+{
+	int j;
+	unsigned char data = 0;
+	sda_in();
+	for(j=7; j>=0; --j)
+	{
+		set_scl(0);
+		udelay(T/2);
+		set_scl(1);
+		udelay(T/4);
+		data |= (get_sda()<<j);
+		udelay(T/4);
+	}
+	set_scl(0);
+	/* send ACK */
+	sda_out();
+	set_scl(0);
+	udelay(T/4);
+	set_sda(0);
+	udelay(T/4);
+	set_scl(1);
+	udelay(T/2);
+
+	set_scl(0);
+	set_sda(1);
+	return data&0xff;
+}
+#endif
+/* ak880x_i2c_doxfer
+ *
+ * this starts an i2c transfer
+ */
+static int ak880x_i2c_doxfer(struct ak880x_i2c *i2c, struct i2c_msg *msgs, int num)
+{
+	int i,k; 
+	int rw_flag;	// 0 for write, 1 for read 
+	struct i2c_msg *p;
+
+	if(i2c)
+	{
+		i2c->msg = msgs;
+		i2c->msg_num = num;
+		i2c->msg_ptr = 0;
+		i2c->msg_idx = 0;
+	}
+
+	/* printk("num=%d\n", num); */
+
+	start_condition();
+	for(i=0; i<num; ++i)
+	{
+		p = msgs + i;
+		IICDS = (p->addr << 1) & ~1;
+		if(p->flags & I2C_M_RD)
+			rw_flag = 1;
+		else
+			rw_flag = 0;
+		if(p->flags & I2C_M_REV_DIR_ADDR)
+			rw_flag ^= 1;
+		IICDS |= rw_flag;
+	
+		/* start_condition(); */
+		/* send the address byte */
+		if(write_byte(IICDS) < 0)
+		{
+			stop_condition();
+			return -EAGAIN;
+		}
+		if(rw_flag == 0)
+		{
+			/* write */
+			for(k=0; k<p->len; ++k)
+			{
+				IICDS = p->buf[k];
+				if(write_byte(IICDS) < 0)
+				{
+					stop_condition();
+					return -EAGAIN;
+				}
+			}
+		}
+		else
+		{
+			/* read */
+			for(k=0; k<p->len; ++k)
+			{
+				IICDS = read_byte();
+				p->buf[k] = IICDS;
+			}
+		}
+		/* stop_condition(); */
+	}
+	stop_condition(); /* for ta801 rda5802 */ 
+	msleep(1);
+
+	return num;
+}
+
+/* ak880x_i2c_xfer
+ *
+ * first port of call from the i2c bus code when an message needs
+ * transferring across the i2c bus.
+ */
+
+static int ak880x_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg *msgs, int num)
+{
+	struct ak880x_i2c *i2c = (struct ak880x_i2c *)adap->algo_data;
+	int retry;
+	int ret;
+	
+	for(retry=0; retry<adap->retries; retry++)
+	{
+		ret = ak880x_i2c_doxfer(i2c, msgs, num);
+		if(ret != -EAGAIN)
+			return ret;
+		udelay(100);
+	}
+	return -EREMOTEIO;
+}
+
+/* declare our i2c functionality */
+static u32 ak880x_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+/* i2c bus registration info */
+
+static const struct i2c_algorithm ak880x_i2c_algorithm = {
+	.master_xfer		= ak880x_i2c_xfer,
+	.functionality		= ak880x_i2c_func,
+};
+
+static struct ak880x_i2c ak880x_i2c = {
+	.lock		= __SPIN_LOCK_UNLOCKED(ak880x_i2c.lock),
+	.wait		= __WAIT_QUEUE_HEAD_INITIALIZER(ak880x_i2c.wait),
+	.tx_setup	= 50,
+	.adap		= {
+		.name			= "ak880x-i2c",
+		.owner			= THIS_MODULE,
+		.algo			= &ak880x_i2c_algorithm,
+		.retries		= 2,
+		.class			= I2C_CLASS_HWMON,
+	},
+};
+
+
+/* ak880x_i2c_init
+ *
+ * initialise the hardware, set the IO lines and frequency 
+ */
+
+static int ak880x_i2c_init(struct ak880x_i2c *i2c)
+{
+	/* Setup GPIO for Software I2C bus */
+
+	/* I2CSCL */
+	scl_out();
+	set_scl(1);
+	/*
+	ak880x_gpio_cfgpin(I2CSCLPIN, AK88_GPIO_OUT_0);
+	ak880x_gpio_setpin(I2CSCLPIN, 1);
+	*/
+	/* I2CSDA */
+	sda_out();
+	set_sda(1);
+	/*
+	ak880x_gpio_cfgpin(I2CSDAPIN, AK88_GPIO_OUT_0);
+	ak880x_gpio_setpin(I2CSDAPIN, 1);
+	*/
+
+	return 0;
+}
+
+/* ak880x_i2c_probe
+ *
+ * called by the bus driver when a suitable device is found
+ */
+
+static void test(void)
+{
+	unsigned char c = 0x5f;
+	int val;
+	struct i2c_msg  msg = {0x30, 0, 1, &c};
+	val = ak880x_i2c_doxfer(NULL, &msg, 1);
+	printk("return %d\n", val);
+}
+static int ak880x_i2c_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct ak880x_i2c *i2c = &ak880x_i2c;
+
+	/*printk("Enterring %s\n", __FUNCTION__);*/
+
+	i2c->adap.algo_data = i2c;
+	i2c->adap.dev.parent = &pdev->dev;
+	ret = ak880x_i2c_init(i2c);
+
+	ret = i2c_add_adapter(&i2c->adap);
+	if(ret < 0)
+		goto out;
+	platform_set_drvdata(pdev, i2c);
+	#if 0
+	while(1)
+	{
+		test();
+	}
+	#endif
+
+out:
+	return ret;
+}
+
+static int ak880x_i2c_remove(struct platform_device *pdev)
+{
+	struct ak880x_i2c *i2c;
+
+	/*printk("Enterring %s\n", __FUNCTION__);*/
+
+	i2c = platform_get_drvdata(pdev);
+	i2c_del_adapter(&i2c->adap);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ak880x_i2c_resume(struct platform_device *dev)
+{
+	/*printk("Enterring %s\n", __FUNCTION__);*/
+
+	return 0;
+}
+
+#else
+#define ak880x_i2c_resume NULL
+#endif
+
+/* device driver for platform bus bits */
+
+static struct platform_driver ak880x_i2c_driver = {
+	.probe		= ak880x_i2c_probe,
+	.remove		= ak880x_i2c_remove,
+	.resume		= ak880x_i2c_resume,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ak880x-i2c",
+	},
+};
+
+static int __init i2c_adap_ak880x_init(void)
+{
+	printk("AK88 I2C (base gpio), (c) 2010 AK88");
+
+	return platform_driver_register(&ak880x_i2c_driver);
+}
+
+static void __exit i2c_adap_ak880x_exit(void)
+{
+	platform_driver_unregister(&ak880x_i2c_driver);
+}
+
+module_init(i2c_adap_ak880x_init);
+module_exit(i2c_adap_ak880x_exit);
+
+MODULE_DESCRIPTION("AK88 I2C Bus driver");
+MODULE_AUTHOR("anyka");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-ak98.c b/drivers/i2c/busses/i2c-ak98.c
new file mode 100755
index 00000000000..5a250ab8f20
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ak98.c
@@ -0,0 +1,956 @@
+/* linux/drivers/i2c/busses/i2c-ak98.c
+ *
+ * Copyright (C) 2010 Anyka
+ *
+ * AK9801 I2C Controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/semaphore.h>
+
+
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/clock.h>
+
+#include <mach/gpio.h>
+#include <mach/i2c.h>
+#include <mach/regs-comm.h>
+
+
+#define AK98_I2C_INTERRUPT_MODE
+
+/* i2c controller state */
+enum ak98_i2c_state {
+	STATE_READ,
+	STATE_WRITE
+};
+
+enum read_data_addr {
+	READ_ADDR,
+	READ_DATA
+};
+
+struct ak98_i2c {
+	spinlock_t		lock;
+	wait_queue_head_t	wait;
+	unsigned int		suspended:1;
+
+	struct i2c_msg		*msg;
+	unsigned int		msg_num;
+	unsigned int		msg_idx;
+	unsigned int		msg_ptr;
+
+	unsigned int		irq;
+	unsigned long		clkrate;
+
+	enum ak98_i2c_state	state;
+	enum read_data_addr	read_value;
+	
+	void __iomem		*regs;
+	struct clk			*clk;
+	struct device		*dev;
+	struct resource		*ioarea;
+	struct i2c_adapter	adap;
+
+#ifdef CONFIG_CPU_FREQ
+	struct notifier_block	freq_transition;
+#endif
+};
+
+
+static struct semaphore xfer_sem;
+
+
+/* ~~~~~~~~~~~ poll mode ~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+#ifdef AK98_I2C_POLL_MODE
+
+
+
+/*
+ * Poll the i2c status register until the specified bit is set.
+ * Return 1 if transfer finished.
+ */
+static short ak98_poll_status(void)
+{
+	do {
+	} while (!(__raw_readl(AK98_I2C_CTRL) & INT_PEND_FLAG));
+
+	return 1;
+}
+
+static int xfer_read(struct ak98_i2c *i2c, unsigned char *buf, int length)
+{
+	int i,j, ctrl_value;
+	unsigned long ret, reg_value;
+	unsigned char *p = buf;
+	int idx = 0;
+
+	if((length - 1) > 16)
+		ctrl_value = 16;
+	else
+		ctrl_value = length;
+	
+	ret = __raw_readl(AK98_I2C_CTRL);
+	ret |= (AK98_I2C_START | AK98_I2C_ACKEN | AK98_I2C_TXRXSEL | AK98_I2C_CLR_DELAY);
+	ret &= ~((0xf) << AK98_I2C_TRX_BYTE);
+	ret |= ((ctrl_value - 1) << AK98_I2C_TRX_BYTE);
+	ret &= ~(INT_PEND_FLAG);
+	__raw_writel(ret, AK98_I2C_CTRL);
+
+	for (i = 0; i < length / 16; i++) {
+		
+		if (!ak98_poll_status()) {
+			dev_dbg(&i2c->adap.dev, "RXRDY timeout\n");
+			return -ETIMEDOUT;
+		}
+
+		for (j = 0; j < 4; j++) {
+			reg_value = __raw_readl(AK98_I2C_DATA0 + j * 4);			
+			*(unsigned long *)p++ = reg_value;
+		}
+	}
+
+	if (!ak98_poll_status()) {
+		dev_dbg(&i2c->adap.dev, "RXRDY timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	idx = 0;
+	for (; idx < (length % 16) / 4; idx++) {
+		unsigned long regval = __raw_readl(AK98_I2C_DATA0 + idx / 4);
+		regval = swab32(regval);
+		*(unsigned long *)p++ = regval;
+	}
+	if (length % 4) {
+		unsigned long regval;
+		if (!ak98_poll_status()) {
+			dev_dbg(&i2c->adap.dev, "RXRDY timeout\n");
+			return -ETIMEDOUT;
+		}
+		
+		regval = __raw_readl(AK98_I2C_DATA0 + idx / 4);
+		for (i = 0; i < length % 4; i++) {
+			*p++ = (regval >> (i * 8)) & 0xFF;
+		}
+	}
+	//mdelay(1);
+
+	return 0;
+}
+
+static void wait_xfer_write(struct ak98_i2c *i2c, int length)
+{
+	unsigned long ret;
+	
+	ret = __raw_readl(AK98_I2C_CTRL);
+	ret |= (AK98_I2C_START);
+	ret &= ~(AK98_I2C_TXRXSEL | INT_PEND_FLAG);
+	ret &= ~((0xf) << AK98_I2C_TRX_BYTE);
+	ret |= ((length - 1)<< AK98_I2C_TRX_BYTE);
+	__raw_writel(ret, AK98_I2C_CTRL);
+
+	if (!ak98_poll_status()) {
+		dev_info(&i2c->adap.dev, "TXRDY timeout\n");
+		return ;
+	}
+	//mdelay(5);
+}
+
+static int xfer_write(struct ak98_i2c *i2c, unsigned char *buf, int length)
+{	
+	unsigned int i;
+	unsigned long reg_value;
+	unsigned int num_count, num_char;
+	int ctrl_value, num_bck = length;
+	unsigned char *p = buf;
+	
+	if((length - 1) > 15)
+		ctrl_value = 16;
+	else
+		ctrl_value = length;
+	
+	num_count = num_bck / 16;
+	num_char = num_bck % 16;
+	
+	while(num_count--) {
+		for(i = 0; i < 4; i++) {			
+			reg_value = *(unsigned long *)p++;
+   			__raw_writel(reg_value, AK98_I2C_DATA0 + i * 4);
+		}
+		
+		wait_xfer_write(i2c, 16);
+	}
+	
+    if(num_char > 0) {
+        unsigned long value = 0;
+        for(i = 0; i < num_char; i+=4) {
+			value = *(unsigned long *)p;
+			__raw_writel(value, AK98_I2C_DATA0 + i);
+		}
+		wait_xfer_write(i2c, ctrl_value);
+	}
+	
+	return 0;
+}
+
+static int ak98_i2c_doxfer(struct ak98_i2c *i2c, struct i2c_msg *msgs, int num)
+{
+	unsigned int addr = (msgs->addr & 0x7f) << 1;
+	int i, ret, rw_flag;
+
+	dev_dbg(&i2c->adap.dev, "ak98_i2c_xfer: processing %d messages:\n", num);
+	
+	for (i = 0; i < num; i++) {
+		if (msgs->flags & I2C_M_RD) {
+			addr |= AK98_I2C_READ;
+			rw_flag = 1;
+		} else {
+			rw_flag = 0;
+		}
+		if (msgs->flags & I2C_M_REV_DIR_ADDR)
+			addr ^= 1;
+		//printk(KERN_INFO "1:%lu\n", jiffies);
+		__raw_writel((AK98_I2C_CMD_EN | AK98_I2C_START_BIT)|addr, AK98_I2C_CMD1);
+		//printk(KERN_INFO "2:%lu\n", jiffies);
+		if(msgs->len && msgs->buf) {
+			if (rw_flag == 1)
+				ret = xfer_read(i2c, msgs->buf, msgs->len);
+			else
+				ret = xfer_write(i2c, msgs->buf, msgs->len);
+			
+			if (ret)
+				return ret;
+		}
+		//printk(KERN_INFO "3:%lu\n", jiffies);
+		dev_dbg(&i2c->adap.dev, "transfer complete\n");
+		msgs++;		/* next message */
+	}
+	return i;
+}
+#endif
+
+/* ~~~~~~~~~~~ INTER MODE ~~~~~~~~~~~~~~~~~~~ */
+
+#ifdef AK98_I2C_INTERRUPT_MODE 
+
+static void clear_int_flag(void)
+{
+	unsigned long tmp;
+
+	tmp = __raw_readl(AK98_I2C_CTRL);
+	tmp &= ~INT_PEND_FLAG;
+	__raw_writel(tmp, AK98_I2C_CTRL);
+}
+
+/* irq disable functions */
+static void ak98_i2c_disable_irq(struct ak98_i2c *i2c)
+{
+	unsigned long tmp;
+	
+	tmp = __raw_readl(AK98_I2C_CTRL);
+	__raw_writel(tmp & ~AK98_I2C_INTEN, AK98_I2C_CTRL);
+}
+
+static inline void ak98_i2c_master_complete(struct ak98_i2c *i2c, int ret)
+{
+	dev_dbg(i2c->dev, "master_complete %d\n", ret);
+
+	i2c->msg_ptr = 0;
+	i2c->msg = NULL;
+	i2c->msg_num = 0;
+	if (ret)
+		i2c->msg_idx = ret;
+	
+	wake_up(&i2c->wait);
+}
+
+static inline void ak98_i2c_stop(struct ak98_i2c *i2c, int ret)
+{
+	dev_dbg(i2c->dev, "STOP\n");
+
+	ak98_i2c_master_complete(i2c, ret);
+	ak98_i2c_disable_irq(i2c);
+}
+
+static int ak98_i2c_irq_transfer(struct ak98_i2c *i2c)
+{
+	unsigned int addr = (i2c->msg->addr & 0x7f) << 1;
+	unsigned int num_char, i, length;
+	unsigned long stat, regval = 0;
+	unsigned char *p = i2c->msg->buf;
+
+read_next:
+	if(i2c->msg_idx < i2c->msg_num) {
+		if (i2c->msg->len == 0) {
+			ak98_i2c_stop(i2c, 0);
+			return 0;
+		}
+		
+		stat = __raw_readl(AK98_I2C_CTRL);
+		stat &= ~(0xf << 9);
+		if (i2c->msg->flags & I2C_M_RD) {
+			addr |= AK98_I2C_READ ;
+			i2c->state = STATE_READ ;
+			stat |= AK98_I2C_TXRXSEL ;
+		} 
+		else {
+			i2c->state = STATE_WRITE ;
+			stat &= ~AK98_I2C_TXRXSEL ;
+		}
+	
+		if (i2c->msg->flags & I2C_M_REV_DIR_ADDR)
+			addr ^= 1;
+		
+		__raw_writel((AK98_I2C_CMD_EN | AK98_I2C_START_BIT)|addr, AK98_I2C_CMD1);
+		
+		switch(i2c->state) {
+			case STATE_WRITE:
+				if (i2c->msg->len > 16) {
+						printk("Error, needed debug more data transmitted.\n");
+						return 0;
+				}
+				if (i2c->msg_ptr < i2c->msg->len) {
+					
+					num_char = i2c->msg->len % 16;
+
+					if (num_char > 0) {
+						__raw_writel(stat | ((num_char - 1) << 9), AK98_I2C_CTRL);
+						for(i = 0; i < num_char; i+=4) {
+							regval = *(unsigned long *)p;
+							__raw_writel(regval, AK98_I2C_DATA0 + i);
+						}
+						i2c->msg_ptr += num_char;			
+					}
+					
+					if(i2c->msg_ptr >= i2c->msg->len){
+						i2c->msg_ptr = 0;
+						i2c->msg_idx++;
+						i2c->msg++;
+					}
+					
+					stat = __raw_readl(AK98_I2C_CTRL);
+					__raw_writel(stat | AK98_I2C_START, AK98_I2C_CTRL);				
+				}
+				break;
+
+			case STATE_READ:
+				length = i2c->msg->len;
+				if (i2c->msg->len > 16) {
+					printk("Error, needed debug more data transmitted.\n");
+					return 0;
+				}
+				__raw_writel(stat | ((length - 1) << 9), AK98_I2C_CTRL);
+				
+				if(i2c->read_value == READ_ADDR) {
+					stat = __raw_readl(AK98_I2C_CTRL);
+					__raw_writel(stat | AK98_I2C_START, AK98_I2C_CTRL);
+					i2c->read_value = READ_DATA;
+				} else {
+					if (i2c->msg_ptr < i2c->msg->len) {
+
+						num_char = i2c->msg->len % 16;
+
+						if (num_char > 0) {
+							for (i = 0; i < num_char; i+=4) {
+								regval = __raw_readl(AK98_I2C_DATA0 + i);
+								*(unsigned long *)p++ = regval;
+							}
+							i2c->msg_ptr += num_char;
+						}
+						
+						if (i2c->msg_ptr >= i2c->msg->len) {
+							/* we need to go to the next i2c message */
+							dev_dbg(i2c->dev, "READ: Next Message\n");
+											
+							i2c->msg_ptr = 0;
+							i2c->msg_idx++;
+							i2c->msg++;
+							
+							if(i2c->msg_idx >= i2c->msg_num) {
+								ak98_i2c_stop(i2c, 0);
+								return 0;
+							}
+						}
+						i2c->read_value = READ_ADDR;
+						goto read_next;
+					}							
+				}
+				break;
+		}	
+	} 
+	else {
+		ak98_i2c_stop(i2c, 0);
+	}
+	return 0;
+}
+
+/* ak98_i2c_irq
+ *
+ * top level IRQ servicing routine
+*/
+static irqreturn_t ak98_i2c_irq(int irqno, void *dev_id)
+{
+	struct ak98_i2c *i2c = dev_id;
+
+	clear_int_flag();
+
+	/* pretty much this leaves us with the fact that we've
+	 * transmitted or received whatever byte we last sent */
+	
+	ak98_i2c_irq_transfer(i2c);
+
+	return IRQ_HANDLED;
+}
+
+static int ak98_i2c_doxfer(struct ak98_i2c *i2c, struct i2c_msg *msgs, int num)
+{
+	unsigned long timeout, stat;
+	int ret;
+
+	if (i2c->suspended)
+		return -EIO;
+
+	spin_lock_irq(&i2c->lock);
+	i2c->msg     = msgs;
+	i2c->msg_num = num;
+	i2c->msg_ptr = 0;
+	i2c->msg_idx = 0;
+	i2c->read_value = READ_ADDR;
+	//printk(KERN_INFO "1: %lu\n", jiffies);
+	ak98_i2c_irq_transfer(i2c);
+	//printk(KERN_INFO "1: %lu\n", jiffies);
+	stat = __raw_readl(AK98_I2C_CTRL);
+	stat |= AK98_I2C_INTEN | AK98_I2C_ACKEN;
+	__raw_writel(stat, AK98_I2C_CTRL);
+
+	spin_unlock_irq(&i2c->lock);
+	//printk(KERN_INFO "2: %lu\n\n", jiffies);
+	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
+
+	ret = i2c->msg_idx;
+
+	/* having these next two as dev_err() makes life very
+	 * noisy when doing an i2cdetect */
+
+	if (timeout == 0)
+		dev_info(i2c->dev, "timeout\n");
+	else if (ret != num)
+		dev_info(i2c->dev, "incomplete xfer (%d)\n", ret);
+
+	return ret;
+}
+#endif
+
+
+/* ak98_i2c_xfer
+ *
+ * first port of call from the i2c bus code when an message needs
+ * transferring across the i2c bus.
+*/
+static int ak98_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg *msgs, int num)
+{
+	struct ak98_i2c *i2c = (struct ak98_i2c *)adap->algo_data;
+	int retry;
+	int ret;
+
+	down(&xfer_sem);
+	for (retry = 0; retry < adap->retries; retry++) {
+	
+		ret = ak98_i2c_doxfer(i2c, msgs, num);
+	
+		if (ret != -EAGAIN)
+		{
+			up(&xfer_sem);
+			return ret;
+		}
+
+		dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
+
+		udelay(100);
+	}
+	
+	up(&xfer_sem);
+	return -EREMOTEIO;
+}
+
+/* declare our i2c functionality */
+static u32 ak98_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+/* i2c bus registration info */
+
+static const struct i2c_algorithm ak98_i2c_algorithm = {
+	.master_xfer		= ak98_i2c_xfer,
+	.functionality		= ak98_i2c_func,
+};
+
+/* ak98_i2c_calcdivisor
+ *
+ * return the divisor settings for a given frequency
+*/
+static int ak98_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
+				   unsigned int *div1, unsigned int *divs)
+{
+	unsigned int calc_divs = clkin / wanted / 2;
+	unsigned int calc_div1;
+
+	if (calc_divs > (16*16))
+		calc_div1 = 512;
+	else
+		calc_div1 = 16;
+
+	calc_divs /= calc_div1;
+
+	if (calc_divs == 0)
+		calc_divs = 1;
+	if (calc_divs > 16)
+		calc_divs = 16;
+
+	*divs = calc_divs;
+	*div1 = calc_div1;
+
+	return clkin / ((calc_divs * 2)* calc_div1);
+}
+
+/* ak98_i2c_clockrate
+ *
+ * work out a divisor for the user requested frequency setting,
+ * either by the requested frequency, or scanning the acceptable
+ * range of frequencies until something is found
+*/
+static int ak98_i2c_clockrate(struct ak98_i2c *i2c, unsigned int *got)
+{
+	struct ak98_platform_i2c *pdata = i2c->dev->platform_data;
+	unsigned long clkin = ak98_get_asic_clk();
+	unsigned int divs, div1;
+	unsigned long target_frequency;
+	u32 i2c_val, sda_delay;
+	int freq;
+
+	i2c->clkrate = clkin;
+	clkin /= 1000;		/* clkin now in KHz */
+	
+	dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
+
+	target_frequency = pdata->frequency ? pdata->frequency : 100000;
+	//target_frequency *= 4;
+	target_frequency /= 1000; /* Target frequency now in KHz */
+
+	//printk(KERN_INFO "target: %lu\n", target_frequency);
+	freq = ak98_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
+	//printk(KERN_INFO "change to: %lu\n", freq);
+	if (freq > target_frequency) {
+		dev_err(i2c->dev,
+			"Unable to achieve desired frequency %luKHz."	\
+			" Lowest achievable %dKHz\n", target_frequency, freq);
+		// return -EINVAL;
+	}
+
+	*got = freq;
+
+	i2c_val = __raw_readl(AK98_I2C_CTRL);
+	i2c_val &= ~(AK98_TX_CLK_DIV | AK98_I2C_TXDIV_512);
+	i2c_val |= (divs-1);
+
+	if (div1 == 512)
+		i2c_val |= AK98_I2C_TXDIV_512;
+	
+	__raw_writel(i2c_val, AK98_I2C_CTRL);
+
+	if (pdata->sda_delay) {
+		sda_delay = (freq / 1000) * pdata->sda_delay;
+		sda_delay /= 1000000;
+		sda_delay = DIV_ROUND_UP(sda_delay, 5);
+		if (sda_delay > 3)
+			sda_delay = AK98_I2C_CLR_DELAY;
+		
+		sda_delay |= AK98_I2C_SDA_DELAY;
+	} else
+		sda_delay = ~AK98_I2C_CLR_DELAY;
+
+	i2c_val |= sda_delay;
+	__raw_writel(i2c_val, AK98_I2C_CTRL);
+
+	return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+
+#define freq_to_i2c(_n) container_of(_n, struct ak98_i2c, freq_transition)
+
+static int ak98_i2c_cpufreq_transition(struct notifier_block *nb,
+					  unsigned long val, void *data)
+{
+	struct ak98_i2c *i2c = freq_to_i2c(nb);
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+	unsigned int old_clk = freqs->old_cpufreq.asic_clk;
+	unsigned int new_clk = freqs->new_cpufreq.asic_clk;
+	unsigned long flags;
+	unsigned int got;
+	int ret;
+
+	if (val == CPUFREQ_PRECHANGE)
+	{
+		down(&xfer_sem);
+	}
+	else if (val == CPUFREQ_POSTCHANGE)
+	{	
+		if (old_clk != new_clk)
+		{
+			spin_lock_irqsave(&i2c->lock, flags);
+			ret = ak98_i2c_clockrate(i2c, &got);
+			//printk("setting freq %u\n", got);
+			spin_unlock_irqrestore(&i2c->lock, flags);
+
+			if (ret < 0)
+				dev_err(i2c->dev, "cannot find frequency\n");
+			else
+				dev_info(i2c->dev, "setting freq %d\n", got);
+			
+		}
+		up(&xfer_sem);
+	}
+	
+	return 0;
+}
+
+static inline int ak98_i2c_register_cpufreq(struct ak98_i2c *i2c)
+{
+	i2c->freq_transition.notifier_call = ak98_i2c_cpufreq_transition;
+	return cpufreq_register_notifier(&i2c->freq_transition,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void ak98_i2c_deregister_cpufreq(struct ak98_i2c *i2c)
+{
+	cpufreq_unregister_notifier(&i2c->freq_transition,
+				    CPUFREQ_TRANSITION_NOTIFIER);
+}
+#else
+static inline int ak98_i2c_register_cpufreq(struct ak98_i2c *i2c)
+{
+	return 0;
+}
+static inline void ak98_i2c_deregister_cpufreq(struct ak98_i2c *i2c)
+{
+}
+#endif
+
+/* ak98_i2c_init
+ *
+ * initialise the controller, set the IO lines and frequency
+*/
+static int ak98_i2c_init(struct ak98_i2c *i2c)
+{
+	struct ak98_platform_i2c *pdata;
+	unsigned int freq ;
+
+	/*
+	 * Reset I2C Controller
+	 */
+	rCLK_CON2 |= (1 << 21);
+	rCLK_CON2 &= ~(1 << 21);
+
+	/* get the plafrom data */
+	pdata = i2c->dev->platform_data;
+
+	/* inititalise the gpio */
+	ak98_group_config(ePIN_AS_I2C);
+
+	__raw_writel( AK98_I2C_INTEN | AK98_I2C_ACKEN, AK98_I2C_CTRL);
+	
+	/* we need to work out the divisors for the clock... */
+#if 0
+	ret = __raw_readl(AK98_I2C_CTRL);
+	ret |= ((ak98_get_asic_clk()/2/512/100000 - 1) | (1<<6));
+	__raw_writel(ret, AK98_I2C_CTRL);
+	
+#else
+	if (ak98_i2c_clockrate(i2c, &freq) != 0) {
+		__raw_writel(0, AK98_I2C_CTRL);
+		dev_err(i2c->dev, "cannot meet bus frequency required\n");
+		return -EINVAL;
+	}
+#endif
+
+	/* todo - check that the i2c lines aren't being dragged anywhere */
+
+	dev_dbg(i2c->dev, "bus frequency set to %d KHz\n", freq);
+
+	printk("2345 bus frequency set to %d KHz\n", freq);
+	
+	return 0;
+}
+
+
+/* ak98_i2c_probe
+ *
+ * called by the bus driver when a suitable device is found
+*/
+static int ak98_i2c_probe(struct platform_device *pdev)
+{
+	struct ak98_i2c *i2c;
+	struct ak98_platform_i2c *pdata;
+	struct resource *res;
+	int ret;
+	
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data\n");
+		return -EINVAL;
+	}
+
+	i2c = kzalloc(sizeof(struct ak98_i2c), GFP_KERNEL);
+	if (!i2c) {
+		dev_err(&pdev->dev, "no memory for state\n");
+		return -ENOMEM;
+	}		
+
+	strlcpy(i2c->adap.name, "ak98-i2c", sizeof(i2c->adap.name));
+	i2c->adap.owner   = THIS_MODULE;
+	i2c->adap.algo    = &ak98_i2c_algorithm;
+	i2c->adap.retries = 2;
+	i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+
+	spin_lock_init(&i2c->lock);
+	init_waitqueue_head(&i2c->wait);
+
+	/* find the clock and enable it */
+
+	i2c->dev = &pdev->dev;
+	i2c->clk = clk_get(&pdev->dev, "i2c_clk");
+	if (IS_ERR(i2c->clk)) {
+		dev_err(&pdev->dev, "cannot get clock\n");
+		ret = -ENOENT;
+		goto err_noclk;
+	}
+
+	dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
+		
+	clk_enable(i2c->clk);
+
+	/* map the registers */
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot find IO resource\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	i2c->ioarea = request_mem_region(res->start, resource_size(res), pdev->name);
+	if (i2c->ioarea == NULL) {
+		dev_err(&pdev->dev, "cannot request IO\n");
+		ret = -ENXIO;
+		goto err_clk;
+	}
+
+	i2c->regs = ioremap(res->start, resource_size(res));
+	if (i2c->regs == NULL) {
+		dev_err(&pdev->dev, "cannot map IO\n");
+		ret = -ENXIO;
+		goto err_ioarea;
+	}
+
+	dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
+
+	/* setup info block for the i2c core */
+
+	i2c->adap.algo_data = i2c;
+	i2c->adap.dev.parent = &pdev->dev;
+
+	/* initialise the i2c controller */
+
+	ret = ak98_i2c_init(i2c);
+	if (ret != 0)
+		goto err_iomap;
+
+	/* find the IRQ for this unit (note, this relies on the init call to
+	 * ensure no current IRQs pending
+	 */
+	i2c->irq = ret = platform_get_irq(pdev, 0);
+	if (ret <= 0) {
+		dev_err(&pdev->dev, "cannot find IRQ\n");
+		goto err_iomap;
+	}
+	
+#ifdef AK98_I2C_INTERRUPT_MODE	
+	ret = request_irq(i2c->irq, ak98_i2c_irq, IRQF_DISABLED, dev_name(&pdev->dev), i2c);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
+		goto err_iomap;
+	}
+#endif
+
+	sema_init(&xfer_sem, 1);
+	ret = ak98_i2c_register_cpufreq(i2c);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
+		goto err_irq;
+	}
+	
+	i2c->adap.nr = pdata->bus_num;
+	ret = i2c_add_numbered_adapter(&i2c->adap);
+
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+		goto err_cpufreq;
+	}
+
+	platform_set_drvdata(pdev, i2c);
+
+	dev_info(&pdev->dev, "%s: AK98 I2C adapter\n", dev_name(&i2c->adap.dev));
+	
+	return 0;
+
+ err_cpufreq:
+	ak98_i2c_deregister_cpufreq(i2c);
+
+ err_irq:
+	free_irq(i2c->irq, i2c);
+
+ err_iomap:
+	iounmap(i2c->regs);
+
+ err_ioarea:
+	release_resource(i2c->ioarea);
+	kfree(i2c->ioarea);
+
+ err_clk:
+	clk_disable(i2c->clk);
+	clk_put(i2c->clk);
+
+ err_noclk:
+	kfree(i2c);
+	return ret;
+}
+
+
+/* ak98_i2c_remove
+ *
+ * called when device is removed from the bus
+*/
+static int ak98_i2c_remove(struct platform_device *pdev)
+{
+	struct ak98_i2c *i2c = platform_get_drvdata(pdev);
+
+	ak98_i2c_deregister_cpufreq(i2c);
+
+	i2c_del_adapter(&i2c->adap);
+	free_irq(i2c->irq, i2c);
+
+	clk_disable(i2c->clk);
+	clk_put(i2c->clk);
+
+	iounmap(i2c->regs);
+
+	release_resource(i2c->ioarea);
+	
+	kfree(i2c->ioarea);
+	kfree(i2c);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ak98_i2c_suspend_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ak98_i2c *i2c = platform_get_drvdata(pdev);
+	struct ak98_platform_i2c *pdata = pdev->dev.platform_data;
+	int i;
+	
+	down(&xfer_sem);
+	i2c->suspended = 1;
+
+	clk_disable(i2c->clk);
+	clk_put(i2c->clk);
+
+	for (i=0; i<pdata->npins; i++)
+		ak98_gpio_set(&(pdata->gpios[i]));
+
+	return 0;
+}
+
+static int ak98_i2c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ak98_i2c *i2c = platform_get_drvdata(pdev);
+
+	i2c->suspended = 0;
+	clk_enable(i2c->clk);
+	ak98_i2c_init(i2c);
+	up(&xfer_sem);
+	return 0;
+}
+
+static struct dev_pm_ops ak98_i2c_dev_pm_ops = {
+	.suspend_noirq = ak98_i2c_suspend_noirq,
+	.resume = ak98_i2c_resume,
+};
+
+#define AK98_DEV_PM_OPS (&ak98_i2c_dev_pm_ops)
+#else
+#define AK98_DEV_PM_OPS NULL
+#endif
+
+/* device driver for platform bus bits */
+static struct platform_driver ak98_i2c_driver = {
+	.probe		= ak98_i2c_probe,
+	.remove		= ak98_i2c_remove,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ak98-i2c",
+		.pm	= AK98_DEV_PM_OPS,	
+	},
+};
+
+static int __init i2c_adap_ak98_init(void)
+{
+	return platform_driver_register(&ak98_i2c_driver);
+}
+subsys_initcall(i2c_adap_ak98_init);
+
+static void __exit i2c_adap_ak98_exit(void)
+{
+	platform_driver_unregister(&ak98_i2c_driver);
+}
+module_exit(i2c_adap_ak98_exit);
+
+MODULE_DESCRIPTION("AK980X I2C Bus driver");
+MODULE_AUTHOR("Anaka, <xxx@xxx.com>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/i2c/chips/Kconfig b/drivers/i2c/chips/Kconfig
index f9618f4d4e4..4074d34d46e 100644
--- a/drivers/i2c/chips/Kconfig
+++ b/drivers/i2c/chips/Kconfig
@@ -26,4 +26,32 @@ config SENSORS_TSL2550
 	  This driver can also be built as a module.  If so, the module
 	  will be called tsl2550.
 
+config SENSORS_PCA963X
+	tristate "Philips PCA963X 4-bit I2C-bus LED"
+	depends on I2C && EXPERIMENTAL
+	help
+	 If you say yes here you get support for the Philips PCA963X
+	 4-bit I2C-bus LED.
+
+	 This driver can also be built as a module.  If so, the module
+	 will be called pca963X.
+
+config SENSORS_MXC622X
+	tristate "MEMSIC Acceleration Sensor Support"
+	depends on I2C
+	help
+	  If you say yes here you get support for the MEMSIC acceleration sensor
+
+config SENSORS_MMC328X
+	tristate "MEMSIC Magnetic Sensor Support"
+	depends on I2C
+	help
+	  If you say yes here you get support for the MEMSIC magnateic sensor
+
+config ECOMPASS
+	tristate "MEMSIC eCompass Support"
+	depends on I2C && INPUT
+	help
+	  If you say yes here you get support for the MEMSIC eCompass
+
 endmenu
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 749cf360629..33ed8c21c76 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -11,7 +11,11 @@
 #
 
 obj-$(CONFIG_DS1682)		+= ds1682.o
+obj-$(CONFIG_SENSORS_PCA963X)	+= pca963x.o
 obj-$(CONFIG_SENSORS_TSL2550)	+= tsl2550.o
+obj-$(CONFIG_SENSORS_MXC622X)	+= mxc622x.o
+obj-$(CONFIG_SENSORS_MMC328X)	+= mmc328x.o
+obj-$(CONFIG_ECOMPASS)			+= mecs.o
 
 ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/i2c/chips/mecs.c b/drivers/i2c/chips/mecs.c
new file mode 100755
index 00000000000..3e405135cac
--- /dev/null
+++ b/drivers/i2c/chips/mecs.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/miscdevice.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/workqueue.h>
+#include <linux/freezer.h>
+#include <asm/uaccess.h>
+
+#include "mecs.h"
+
+#define DEBUG			0
+
+#define ECS_DATA_DEV_NAME	"ecompass_data"
+#define ECS_CTRL_DEV_NAME	"ecompass_ctrl"
+
+static int ecs_ctrl_open(struct inode *inode, struct file *file);
+static int ecs_ctrl_release(struct inode *inode, struct file *file);
+static int ecs_ctrl_ioctl(struct inode *inode, struct file *file, 
+	unsigned int cmd, unsigned long arg);
+
+static DECLARE_WAIT_QUEUE_HEAD(open_wq);
+
+static atomic_t	open_count;
+static atomic_t	open_flag;
+static atomic_t	reserve_open_flag;
+
+static atomic_t	a_flag;
+static atomic_t	m_flag;
+static atomic_t	o_flag;
+
+static short ecompass_delay = 0;
+
+
+static struct input_dev *ecs_data_device;
+
+static struct file_operations ecs_ctrl_fops = {
+	.owner		= THIS_MODULE,
+	.open		= ecs_ctrl_open,
+	.release	= ecs_ctrl_release,
+	.ioctl		= ecs_ctrl_ioctl,
+};
+
+static struct miscdevice ecs_ctrl_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = ECS_CTRL_DEV_NAME,
+	.fops = &ecs_ctrl_fops,
+};
+
+static int ecs_ctrl_open(struct inode *inode, struct file *file)
+{
+#if 1
+	atomic_set(&reserve_open_flag, 1);
+	atomic_set(&open_flag, 1);
+	atomic_set(&open_count, 1);
+	wake_up(&open_wq);
+
+	return 0;
+#else
+	int ret = -1;
+
+	if (atomic_cmpxchg(&open_count, 0, 1) == 0) {
+		if (atomic_cmpxchg(&open_flag, 0, 1) == 0) {
+			atomic_set(&reserve_open_flag, 1);
+			wake_up(&open_wq);
+			ret = 0;
+		}
+	}
+
+	return ret;
+#endif
+}
+
+static int ecs_ctrl_release(struct inode *inode, struct file *file)
+{
+	atomic_set(&reserve_open_flag, 0);
+	atomic_set(&open_flag, 0);
+	atomic_set(&open_count, 0);
+	wake_up(&open_wq);
+
+	return 0;
+}
+
+static int ecs_ctrl_ioctl(struct inode *inode, struct file *file, 
+	unsigned int cmd, unsigned long arg)
+{
+	void __user *pa = (void __user *)arg;
+	short flag;
+	short delay;
+	int parms[4];
+	int ypr[12];
+
+	switch (cmd) {
+	case ECOMPASS_IOC_SET_MODE:
+		break;
+	case ECOMPASS_IOC_SET_DELAY:
+		if (copy_from_user(&delay, pa, sizeof(delay)))
+			return -EFAULT;
+		ecompass_delay = delay;
+		break;
+	case ECOMPASS_IOC_GET_DELAY:
+		delay = ecompass_delay;
+		if (copy_to_user(pa, &delay, sizeof(delay)))
+			return -EFAULT;
+		break;
+
+	case ECOMPASS_IOC_SET_AFLAG:
+		if (copy_from_user(&flag, pa, sizeof(flag)))
+			return -EFAULT;
+		if (flag < 0 || flag > 1)
+			return -EINVAL;
+		atomic_set(&a_flag, flag);
+		break;
+	case ECOMPASS_IOC_GET_AFLAG:
+		flag = atomic_read(&a_flag);
+		if (copy_to_user(pa, &flag, sizeof(flag)))
+			return -EFAULT;
+		break;
+	case ECOMPASS_IOC_SET_MFLAG:
+		if (copy_from_user(&flag, pa, sizeof(flag)))
+			return -EFAULT;
+		if (flag < 0 || flag > 1)
+			return -EINVAL;
+		atomic_set(&m_flag, flag);
+		break;
+	case ECOMPASS_IOC_GET_MFLAG:
+		flag = atomic_read(&m_flag);
+		if (copy_to_user(pa, &flag, sizeof(flag)))
+			return -EFAULT;
+		break;
+	case ECOMPASS_IOC_SET_OFLAG:
+		if (copy_from_user(&flag, pa, sizeof(flag)))
+			return -EFAULT;
+		if (flag < 0 || flag > 1)
+			return -EINVAL;
+		atomic_set(&o_flag, flag);
+		break;
+	case ECOMPASS_IOC_GET_OFLAG:
+		flag = atomic_read(&o_flag);
+		if (copy_to_user(pa, &flag, sizeof(flag)))
+			return -EFAULT;
+		break;
+
+	case ECOMPASS_IOC_SET_APARMS:
+		if (copy_from_user(parms, pa, sizeof(parms)))
+			return -EFAULT;
+		/* acceleration x-axis */
+		input_set_abs_params(ecs_data_device, ABS_X, 
+			parms[0], parms[1], parms[2], parms[3]);
+		/* acceleration y-axis */
+		input_set_abs_params(ecs_data_device, ABS_Y, 
+			parms[0], parms[1], parms[2], parms[3]);
+		/* acceleration z-axis */
+		input_set_abs_params(ecs_data_device, ABS_Z, 
+			parms[0], parms[1], parms[2], parms[3]);
+		break;
+	case ECOMPASS_IOC_GET_APARMS:
+		break;
+	case ECOMPASS_IOC_SET_MPARMS:
+		if (copy_from_user(parms, pa, sizeof(parms)))
+			return -EFAULT;
+		/* magnetic raw x-axis */
+		input_set_abs_params(ecs_data_device, ABS_HAT0X, 
+			parms[0], parms[1], parms[2], parms[3]);
+		/* magnetic raw y-axis */
+		input_set_abs_params(ecs_data_device, ABS_HAT0Y, 
+			parms[0], parms[1], parms[2], parms[3]);
+		/* magnetic raw z-axis */
+		input_set_abs_params(ecs_data_device, ABS_BRAKE, 
+			parms[0], parms[1], parms[2], parms[3]);
+		break;
+	case ECOMPASS_IOC_GET_MPARMS:
+		break;
+	case ECOMPASS_IOC_SET_OPARMS_YAW:
+		if (copy_from_user(parms, pa, sizeof(parms)))
+			return -EFAULT;
+		/* orientation yaw */
+		input_set_abs_params(ecs_data_device, ABS_RX, 
+			parms[0], parms[1], parms[2], parms[3]);
+		break;
+	case ECOMPASS_IOC_GET_OPARMS_YAW:
+		break;
+	case ECOMPASS_IOC_SET_OPARMS_PITCH:
+		if (copy_from_user(parms, pa, sizeof(parms)))
+			return -EFAULT;
+		/* orientation pitch */
+		input_set_abs_params(ecs_data_device, ABS_RY, 
+			parms[0], parms[1], parms[2], parms[3]);
+		break;
+	case ECOMPASS_IOC_GET_OPARMS_PITCH:
+		break;
+	case ECOMPASS_IOC_SET_OPARMS_ROLL:
+		if (copy_from_user(parms, pa, sizeof(parms)))
+			return -EFAULT;
+		/* orientation roll */
+		input_set_abs_params(ecs_data_device, ABS_RZ, 
+			parms[0], parms[1], parms[2], parms[3]);
+		break;
+	case ECOMPASS_IOC_GET_OPARMS_ROLL:
+		break;
+
+	case ECOMPASS_IOC_SET_YPR:
+		if (copy_from_user(ypr, pa, sizeof(ypr)))
+			return -EFAULT;
+		/* Report acceleration sensor information */
+		if (atomic_read(&a_flag)) {
+			input_report_abs(ecs_data_device, ABS_X, ypr[0]);
+			input_report_abs(ecs_data_device, ABS_Y, ypr[1]);
+			input_report_abs(ecs_data_device, ABS_Z, ypr[2]);
+			input_report_abs(ecs_data_device, ABS_WHEEL, ypr[3]);
+		}
+
+		/* Report magnetic sensor information */
+		if (atomic_read(&m_flag)) {
+			input_report_abs(ecs_data_device, ABS_HAT0X, ypr[4]);
+			input_report_abs(ecs_data_device, ABS_HAT0Y, ypr[5]);
+			input_report_abs(ecs_data_device, ABS_BRAKE, ypr[6]);
+			input_report_abs(ecs_data_device, ABS_GAS, ypr[7]);
+		}
+
+		/* Report orientation information */
+		if (atomic_read(&o_flag)) {
+			input_report_abs(ecs_data_device, ABS_RX, ypr[8]);
+			input_report_abs(ecs_data_device, ABS_RY, ypr[9]);
+			input_report_abs(ecs_data_device, ABS_RZ, ypr[10]);
+			input_report_abs(ecs_data_device, ABS_RUDDER, ypr[11]);
+		}
+
+		input_sync(ecs_data_device);
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static ssize_t ecs_ctrl_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	ssize_t ret = 0;
+
+	sprintf(buf, "ecompass_ctrl");
+	ret = strlen(buf) + 1;
+
+	return ret;
+}
+
+static DEVICE_ATTR(ecs_ctrl, S_IRUGO, ecs_ctrl_show, NULL);
+
+static int __init ecompass_init(void)
+{
+	int res = 0;
+
+	pr_info("ecompass driver: init\n");
+
+	ecs_data_device = input_allocate_device();
+	if (!ecs_data_device) {
+		res = -ENOMEM;
+		pr_err("%s: failed to allocate input device\n", __FUNCTION__);
+		goto out;
+	}
+
+	set_bit(EV_ABS, ecs_data_device->evbit);
+
+	/* 32768 == 1g, range -4g ~ +4g */
+	/* acceleration x-axis */
+	input_set_abs_params(ecs_data_device, ABS_X, 
+		-32768*4, 32768*4, 0, 0);
+	/* acceleration y-axis */
+	input_set_abs_params(ecs_data_device, ABS_Y, 
+		-32768*4, 32768*4, 0, 0);
+	/* acceleration z-axis */
+	input_set_abs_params(ecs_data_device, ABS_Z, 
+		-32768*4, 32768*4, 0, 0);
+
+	/* 32768 == 1gauss, range -4gauss ~ +4gauss */
+	/* magnetic raw x-axis */
+	input_set_abs_params(ecs_data_device, ABS_HAT0X, 
+		-32768*4, 32768*4, 0, 0);
+	/* magnetic raw y-axis */
+	input_set_abs_params(ecs_data_device, ABS_HAT0Y, 
+		-32768*4, 32768*4, 0, 0);
+	/* magnetic raw z-axis */
+	input_set_abs_params(ecs_data_device, ABS_BRAKE, 
+		-32768*4, 32768*4, 0, 0);
+
+	/* 65536 == 360degree */
+	/* orientation yaw, 0 ~ 360 */
+	input_set_abs_params(ecs_data_device, ABS_RX, 
+		0, 65536, 0, 0);
+	/* orientation pitch, -180 ~ 180 */
+	input_set_abs_params(ecs_data_device, ABS_RY, 
+		-65536/2, 65536/2, 0, 0);
+	/* orientation roll, -90 ~ 90 */
+	input_set_abs_params(ecs_data_device, ABS_RZ, 
+		-65536/4, 65536/4, 0, 0);
+
+	ecs_data_device->name = ECS_DATA_DEV_NAME;
+	res = input_register_device(ecs_data_device);
+	if (res) {
+		pr_err("%s: unable to register input device: %s\n",
+			__FUNCTION__, ecs_data_device->name);
+		goto out_free_input;
+	}
+
+	res = misc_register(&ecs_ctrl_device);
+	if (res) {
+		pr_err("%s: ecs_ctrl_device register failed\n", __FUNCTION__);
+		goto out_free_input;
+	}
+	res = device_create_file(ecs_ctrl_device.this_device, &dev_attr_ecs_ctrl);
+	if (res) {
+		pr_err("%s: device_create_file failed\n", __FUNCTION__);
+		goto out_deregister_misc;
+	}
+
+	return 0;
+
+out_deregister_misc:
+	misc_deregister(&ecs_ctrl_device);
+out_free_input:
+	input_free_device(ecs_data_device);
+out:
+	return res;
+}
+
+static void __exit ecompass_exit(void)
+{
+	pr_info("ecompass driver: exit\n");
+	device_remove_file(ecs_ctrl_device.this_device, &dev_attr_ecs_ctrl);
+	misc_deregister(&ecs_ctrl_device);
+	input_free_device(ecs_data_device);
+}
+
+module_init(ecompass_init);
+module_exit(ecompass_exit);
+
+MODULE_AUTHOR("Robbie Cao<hjcao@memsic.com>");
+MODULE_DESCRIPTION("MEMSIC eCompass Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/i2c/chips/mecs.h b/drivers/i2c/chips/mecs.h
new file mode 100755
index 00000000000..39890395b36
--- /dev/null
+++ b/drivers/i2c/chips/mecs.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+/*
+ * Definitions for ECOMPASS magnetic sensor chip.
+ */
+#ifndef __ECOMPASS_H__
+#define __ECOMPASS_H__
+
+#include <linux/ioctl.h>
+
+/* Use 'e' as magic number */
+#define ECOMPASS_IOM			'e'
+
+/* IOCTLs for ECOMPASS device */
+#define ECOMPASS_IOC_SET_MODE		_IOW(ECOMPASS_IOM, 0x00, short)
+#define ECOMPASS_IOC_SET_DELAY		_IOW(ECOMPASS_IOM, 0x01, short)
+#define ECOMPASS_IOC_GET_DELAY		_IOR(ECOMPASS_IOM, 0x02, short)
+
+#define ECOMPASS_IOC_SET_AFLAG		_IOW(ECOMPASS_IOM, 0x10, short)
+#define ECOMPASS_IOC_GET_AFLAG		_IOR(ECOMPASS_IOM, 0x11, short)
+#define ECOMPASS_IOC_SET_MFLAG		_IOW(ECOMPASS_IOM, 0x12, short)
+#define ECOMPASS_IOC_GET_MFLAG		_IOR(ECOMPASS_IOM, 0x13, short)
+#define ECOMPASS_IOC_SET_OFLAG		_IOW(ECOMPASS_IOM, 0x14, short)
+#define ECOMPASS_IOC_GET_OFLAG		_IOR(ECOMPASS_IOM, 0x15, short)
+
+#define ECOMPASS_IOC_SET_APARMS		_IOW(ECOMPASS_IOM, 0x20, int[4])
+#define ECOMPASS_IOC_GET_APARMS		_IOR(ECOMPASS_IOM, 0x21, int[4])
+#define ECOMPASS_IOC_SET_MPARMS		_IOW(ECOMPASS_IOM, 0x22, int[4])
+#define ECOMPASS_IOC_GET_MPARMS		_IOR(ECOMPASS_IOM, 0x23, int[4])
+#define ECOMPASS_IOC_SET_OPARMS_YAW	_IOW(ECOMPASS_IOM, 0x24, int[4])
+#define ECOMPASS_IOC_GET_OPARMS_YAW	_IOR(ECOMPASS_IOM, 0x25, int[4])
+#define ECOMPASS_IOC_SET_OPARMS_PITCH	_IOW(ECOMPASS_IOM, 0x26, int[4])
+#define ECOMPASS_IOC_GET_OPARMS_PITCH	_IOR(ECOMPASS_IOM, 0x27, int[4])
+#define ECOMPASS_IOC_SET_OPARMS_ROLL	_IOW(ECOMPASS_IOM, 0x28, int[4])
+#define ECOMPASS_IOC_GET_OPARMS_ROLL	_IOR(ECOMPASS_IOM, 0x29, int[4])
+
+#define ECOMPASS_IOC_SET_YPR		_IOW(ECOMPASS_IOM, 0x30, int[12])
+
+
+#endif /* __ECOMPASS_H__ */
+
diff --git a/drivers/i2c/chips/mmc328x.c b/drivers/i2c/chips/mmc328x.c
new file mode 100755
index 00000000000..9f8f4cf7108
--- /dev/null
+++ b/drivers/i2c/chips/mmc328x.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ * 	Dale Hou
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/miscdevice.h>
+#include <linux/mutex.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/sysctl.h>
+#include <asm/uaccess.h>
+
+#include <linux/mmc328x.h>
+
+#define DEBUG				0
+#define MAX_FAILURE_COUNT	3
+#define READMD				1
+
+#define MMC328X_DELAY_TM	10	/* ms */
+#define MMC328X_DELAY_RM	10	/* ms */
+#define MMC328X_DELAY_STDN	1	/* ms */
+
+#define MMC328X_RETRY_COUNT	3
+#define MMC328X_RESET_INTV	10
+
+#define MMC328X_DEV_NAME	"mmc328x"
+
+static u32 read_idx = 0;
+
+static struct i2c_client *this_client;
+
+static int mmc328x_i2c_rx_data(char *buf, int len)
+{
+	uint8_t i;
+	struct i2c_msg msgs[] = {
+		{
+			.addr	= this_client->addr,
+			.flags	= 0,
+			.len	= 1,
+			.buf	= buf,
+		},
+		{
+			.addr	= this_client->addr,
+			.flags	= I2C_M_RD,
+			.len	= len,
+			.buf	= buf,
+		}
+	};
+
+	for (i = 0; i < MMC328X_RETRY_COUNT; i++) {
+		if (i2c_transfer(this_client->adapter, msgs, 2) >= 0) {
+			break;
+		}
+		mdelay(10);
+	}
+
+	if (i >= MMC328X_RETRY_COUNT) {
+		pr_err("%s: retry over %d\n", __FUNCTION__, MMC328X_RETRY_COUNT);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int mmc328x_i2c_tx_data(char *buf, int len)
+{
+	uint8_t i;
+	struct i2c_msg msg[] = {
+		{
+			.addr	= this_client->addr,
+			.flags	= 0,
+			.len	= len,
+			.buf	= buf,
+		}
+	};
+	
+	for (i = 0; i < MMC328X_RETRY_COUNT; i++) {
+		if (i2c_transfer(this_client->adapter, msg, 1) >= 0) {
+			break;
+		}
+		mdelay(10);
+	}
+
+	if (i >= MMC328X_RETRY_COUNT) {
+		pr_err("%s: retry over %d\n", __FUNCTION__, MMC328X_RETRY_COUNT);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int mmc328x_open(struct inode *inode, struct file *file)
+{
+	return nonseekable_open(inode, file);
+}
+
+static int mmc328x_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mmc328x_ioctl(struct inode *inode, struct file *file, 
+	unsigned int cmd, unsigned long arg)
+{
+	void __user *pa = (void __user *)arg;
+	unsigned char data[16] = {0};
+	int vec[3] = {0};
+	int MD_times = 0;
+
+	switch (cmd) {
+	case MMC328X_IOC_TM:
+		data[0] = MMC328X_REG_CTRL;
+		data[1] = MMC328X_CTRL_TM;
+		if (mmc328x_i2c_tx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		/* wait TM done for coming data read */
+		msleep(MMC328X_DELAY_TM);
+		break;
+	case MMC328X_IOC_RM:
+		data[0] = MMC328X_REG_CTRL;
+		data[1] = MMC328X_CTRL_RM;
+		if (mmc328x_i2c_tx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		/* wait external capacitor charging done for next SET/RESET */
+		msleep(MMC328X_DELAY_RM);
+		break;
+	case MMC328X_IOC_READ:
+		data[0] = MMC328X_REG_DATA;
+		if (mmc328x_i2c_rx_data(data, 6) < 0) {
+			return -EFAULT;
+		}
+		vec[0] = data[1] << 8 | data[0];
+		vec[1] = data[3] << 8 | data[2];
+		vec[2] = data[5] << 8 | data[4];
+	#if DEBUG
+		printk("[X - %04x] [Y - %04x] [Z - %04x]\n", 
+			vec[0], vec[1], vec[2]);
+	#endif
+		if (copy_to_user(pa, vec, sizeof(vec))) {
+			return -EFAULT;
+		}
+		break;
+	case MMC328X_IOC_READXYZ:
+		/* do RM every MMC328X_RESET_INTV times read */
+		if (!(read_idx % MMC328X_RESET_INTV)) {
+			/* RM */
+/* For Some Unknow Reason, Use the SMBUS Protocol Temporarily */  
+#if 0
+			data[0] = MMC328X_REG_CTRL;
+			data[1] = MMC328X_CTRL_RM;
+			/* not check return value here, assume it always OK */
+			if (mmc328x_i2c_tx_data(data, 2) < 0) {
+				return -EFAULT;
+			}
+#else
+			i2c_smbus_write_byte_data(this_client, MMC328X_REG_CTRL, MMC328X_CTRL_RM);
+#endif
+			/* wait external capacitor charging done for next RM */
+			msleep(MMC328X_DELAY_RM);
+		}
+#if 0
+		/* send TM cmd before read */
+		data[0] = MMC328X_REG_CTRL;
+		data[1] = MMC328X_CTRL_TM;
+		/* not check return value here, assume it always OK */
+		if (mmc328x_i2c_tx_data(data, 2)  < 0) {
+			return -EFAULT;
+		}
+#else
+		i2c_smbus_write_byte_data(this_client, MMC328X_REG_CTRL, MMC328X_CTRL_TM);
+#endif	
+		/* wait TM done for coming data read */
+		msleep(MMC328X_DELAY_TM);
+#if READMD
+		/* Read MD */
+#if 0
+		data[0] = MMC328X_REG_DS;
+		if (mmc328x_i2c_rx_data(data, 1) < 0) {
+			return -EFAULT;
+		}
+#else
+		data[0] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DS);
+#endif
+		while (!(data[0] & 0x01)) {
+			msleep(1);
+#if 0
+			/* Read MD again*/
+			data[0] = MMC328X_REG_DS;
+			if (mmc328x_i2c_rx_data(data, 1) < 0) {
+				return -EFAULT;
+			}
+#else
+		data[0] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DS);
+#endif
+			if (data[0] & 0x01) break;
+			MD_times++;
+			if (MD_times > 2) {
+		#if DEBUG
+				printk("TM not work!!");
+		#endif
+				return -EFAULT;
+			}
+		}
+#endif		
+		/* read xyz raw data */
+		read_idx++;
+#if 0
+		data[0] = MMC328X_REG_DATA;
+		if (mmc328x_i2c_rx_data(data, 6) < 0) {
+			return -EFAULT;
+		}
+#else
+		data[0] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA);
+		data[1] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA + 1);
+		data[2] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA + 2);
+		data[3] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA + 3);
+		data[4] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA + 4);
+		data[5] = i2c_smbus_read_byte_data(this_client, MMC328X_REG_DATA + 5);
+#endif
+
+		vec[0] = data[1] << 8 | data[0];
+		vec[1] = data[3] << 8 | data[2];
+		vec[2] = data[5] << 8 | data[4];
+	#if DEBUG
+		printk("[X - %04x] [Y - %04x] [Z - %04x]\n", 
+			vec[0], vec[1], vec[2]);
+	#endif
+		if (copy_to_user(pa, vec, sizeof(vec))) {
+			return -EFAULT;
+		}
+
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static ssize_t mmc328x_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	ssize_t ret = 0;
+
+	sprintf(buf, "MMC328X");
+	ret = strlen(buf) + 1;
+
+	return ret;
+}
+
+static DEVICE_ATTR(mmc328x, S_IRUGO, mmc328x_show, NULL);
+
+static struct file_operations mmc328x_fops = {
+	.owner		= THIS_MODULE,
+	.open		= mmc328x_open,
+	.release	= mmc328x_release,
+	.ioctl		= mmc328x_ioctl,
+};
+
+static struct miscdevice mmc328x_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = MMC328X_DEV_NAME,
+	.fops = &mmc328x_fops,
+};
+
+static int mmc328x_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	unsigned char data[16] = {0};
+	int res = 0;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		pr_err("%s: functionality check failed\n", __FUNCTION__);
+		res = -ENODEV;
+		goto out;
+	}
+	this_client = client;
+
+	res = misc_register(&mmc328x_device);
+	if (res) {
+		pr_err("%s: mmc328x_device register failed\n", __FUNCTION__);
+		goto out;
+	}
+	res = device_create_file(&client->dev, &dev_attr_mmc328x);
+	if (res) {
+		pr_err("%s: device_create_file failed\n", __FUNCTION__);
+		goto out_deregister;
+	}
+
+	/* send ST cmd to mag sensor first of all */
+	data[0] = MMC328X_REG_CTRL;
+	data[1] = MMC328X_CTRL_RM;
+	if (mmc328x_i2c_tx_data(data, 2) < 0) {
+		/* assume RM always success */
+	}
+	/* wait external capacitor charging done for next RM */
+	msleep(MMC328X_DELAY_RM);
+
+	return 0;
+
+out_deregister:
+	misc_deregister(&mmc328x_device);
+out:
+	return res;
+}
+
+static int mmc328x_remove(struct i2c_client *client)
+{
+	device_remove_file(&client->dev, &dev_attr_mmc328x);
+	misc_deregister(&mmc328x_device);
+
+	return 0;
+}
+
+static const struct i2c_device_id mmc328x_id[] = {
+	{ MMC328X_I2C_NAME, 0 },
+	{ }
+};
+
+static struct i2c_driver mmc328x_driver = {
+	.probe 		= mmc328x_probe,
+	.remove 	= mmc328x_remove,
+	.id_table	= mmc328x_id,
+	.driver 	= {
+		.owner	= THIS_MODULE,
+		.name	= MMC328X_I2C_NAME,
+	},
+};
+
+
+static int __init mmc328x_init(void)
+{
+	pr_info("mmc328x driver: init\n");
+	return i2c_add_driver(&mmc328x_driver);
+}
+
+static void __exit mmc328x_exit(void)
+{
+	pr_info("mmc328x driver: exit\n");
+	i2c_del_driver(&mmc328x_driver);
+}
+
+module_init(mmc328x_init);
+module_exit(mmc328x_exit);
+
+MODULE_AUTHOR("Dale Hou<byhou@memsic.com>");
+MODULE_DESCRIPTION("MEMSIC MMC328X Magnetic Sensor Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/i2c/chips/mxc622x.c b/drivers/i2c/chips/mxc622x.c
new file mode 100755
index 00000000000..6a4869780b0
--- /dev/null
+++ b/drivers/i2c/chips/mxc622x.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/miscdevice.h>
+#include <linux/mutex.h>
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/sysctl.h>
+#include <asm/uaccess.h>
+
+#include <linux/mxc622x.h>
+
+#define DEBUG			0
+#define MAX_FAILURE_COUNT	3
+
+#define MXC622X_DELAY_PWRON	300	/* ms, >= 300 ms */
+#define MXC622X_DELAY_PWRDN	1	/* ms */
+#define MXC622X_DELAY_SETDETECTION	MXC622X_DELAY_PWRON
+
+#define MXC622X_RETRY_COUNT	3
+
+struct mxc622x_accl_data {
+	const struct mxc622x_platform_data *pdata;
+	struct i2c_client *client;
+};
+
+static struct mxc622x_accl_data *mxc622x_data;
+
+static int mxc622x_i2c_rx_data(char *buf, int len)
+{
+	uint8_t i;
+	struct i2c_msg msgs[] = {
+		{
+			.addr	= mxc622x_data->client->addr,
+			.flags	= 0,
+			.len	= 1,
+			.buf	= buf,
+		},
+		{
+			.addr	= mxc622x_data->client->addr,
+			.flags	= I2C_M_RD,
+			.len	= len,
+			.buf	= buf,
+		}
+	};
+
+	for (i = 0; i < MXC622X_RETRY_COUNT; i++) {
+		if (i2c_transfer(mxc622x_data->client->adapter, msgs, 2) > 0) {
+			break;
+		}
+		mdelay(10);
+	}
+
+	if (i >= MXC622X_RETRY_COUNT) {
+		pr_err("%s: retry over %d\n", __FUNCTION__, MXC622X_RETRY_COUNT);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int mxc622x_i2c_tx_data(char *buf, int len)
+{
+	uint8_t i;
+	struct i2c_msg msg[] = {
+		{
+			.addr	= mxc622x_data->client->addr,
+			.flags	= 0,
+			.len	= len,
+			.buf	= buf,
+		}
+	};
+	
+	for (i = 0; i < MXC622X_RETRY_COUNT; i++) {
+		if (i2c_transfer(mxc622x_data->client->adapter, msg, 1) > 0) {
+			break;
+		}
+		mdelay(10);
+	}
+
+	if (i >= MXC622X_RETRY_COUNT) {
+		pr_err("%s: retry over %d\n", __FUNCTION__, MXC622X_RETRY_COUNT);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int mxc622x_open(struct inode *inode, struct file *file)
+{
+	return nonseekable_open(inode, file);
+}
+
+static int mxc622x_release(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int mxc622x_ioctl(struct inode *inode, struct file *file,
+	unsigned int cmd, unsigned long arg)
+{
+	void __user *pa = (void __user *)arg;
+	unsigned char data[16] = {0};
+	int vec[3] = {0};
+
+	switch (cmd) {
+	case MXC622X_IOC_PWRON:
+		data[0] = MXC622X_REG_CTRL;
+		data[1] = MXC622X_CTRL_PWRON;
+		if (mxc622x_i2c_tx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		/* wait PWRON done */
+		msleep(MXC622X_DELAY_PWRON);
+		break;
+	case MXC622X_IOC_PWRDN:
+		data[0] = MXC622X_REG_CTRL;
+		data[1] = MXC622X_CTRL_PWRDN;
+		if (mxc622x_i2c_tx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		/* wait PWRDN done */
+		msleep(MXC622X_DELAY_PWRDN);
+		break;
+	case MXC622X_IOC_READXYZ:
+		data[0] = MXC622X_REG_DATA;
+		if (mxc622x_i2c_rx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		vec[0] = (int)data[0];
+		vec[1] = (int)data[1];
+		vec[2] = (int)data[2];
+	#if DEBUG
+		printk("[X - %04x] [Y - %04x] [Z - %04x]\n", 
+			vec[0], vec[1], vec[2]);
+	#endif
+		if (copy_to_user(pa, vec, sizeof(vec))) {
+			return -EFAULT;
+		}
+		break;
+	case MXC622X_IOC_READSTATUS:
+		data[0] = MXC622X_REG_DATA;
+		if (mxc622x_i2c_rx_data(data, 3) < 0) {
+			return -EFAULT;
+		}
+		vec[0] = (int)data[0];
+		vec[1] = (int)data[1];
+		vec[2] = (unsigned int)data[2];
+	#if DEBUG
+		printk("[X - %04x] [Y - %04x] [STATUS - %04x]\n", 
+			vec[0], vec[1], vec[2]);
+	#endif
+		if (copy_to_user(pa, vec, sizeof(vec))) {
+			return -EFAULT;
+		}
+		break;
+	case MXC622X_IOC_SETDETECTION:
+		data[0] = MXC622X_REG_CTRL;
+		if (copy_from_user(&(data[1]), pa, sizeof(unsigned char))) {
+			return -EFAULT;
+		}
+		if (mxc622x_i2c_tx_data(data, 2) < 0) {
+			return -EFAULT;
+		}
+		/* wait SETDETECTION done */
+		msleep(MXC622X_DELAY_SETDETECTION);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static struct file_operations mxc622x_fops = {
+       .owner          = THIS_MODULE,
+       .open           = mxc622x_open,
+       .release        = mxc622x_release,
+       .ioctl          = mxc622x_ioctl,
+};
+
+static struct miscdevice mxc622x_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "mxc622x",
+	.fops = &mxc622x_fops,
+};
+
+int mxc622x_probe(struct i2c_client *client, const struct i2c_device_id *id)
+{
+	int res = 0;
+	const struct mxc622x_platform_data *pdata = client->dev.platform_data;
+	
+	if(!pdata->exist)
+		return -EINVAL;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		pr_err("%s: functionality check failed\n", __FUNCTION__);
+		res = -ENODEV;
+		goto out;
+	}
+
+	mxc622x_data = kzalloc(sizeof(struct mxc622x_accl_data), GFP_KERNEL);
+	if (!mxc622x_data) {
+		pr_err("%s: mxc622x_accl_data alloc failed\n", __FUNCTION__);
+		res = -ENOMEM;
+		goto out;
+	}
+	
+	mxc622x_data->pdata = pdata;
+	mxc622x_data->client = client;
+	i2c_set_clientdata(client, mxc622x_data);
+
+	res = misc_register(&mxc622x_device);
+	if (res) {
+		pr_err("%s: mxc622x_device register failed\n", __FUNCTION__);
+		goto out_deregister;
+	}
+
+	return 0;
+
+out_deregister:
+	kfree(mxc622x_data);
+out:
+	return res;
+}
+
+static int mxc622x_remove(struct i2c_client *client)
+{
+	misc_deregister(&mxc622x_device);
+	kfree(mxc622x_data);
+
+	return 0;
+}
+
+static const struct i2c_device_id mxc622x_id[] = {
+	{ MXC622X_I2C_NAME, 0 },
+	{ }
+};
+
+static struct i2c_driver mxc622x_driver = {
+	.probe 		= mxc622x_probe,
+	.remove 	= mxc622x_remove,
+	.id_table	= mxc622x_id,
+	.driver 	= {
+		.owner	= THIS_MODULE,
+		.name = MXC622X_I2C_NAME,
+	},
+};
+
+static int __init mxc622x_init(void)
+{
+	pr_info("mxc622x driver: init\n");
+	return i2c_add_driver(&mxc622x_driver);
+}
+
+static void __exit mxc622x_exit(void)
+{
+	pr_info("mxc622x driver: exit\n");
+	i2c_del_driver(&mxc622x_driver);
+}
+
+module_init(mxc622x_init);
+module_exit(mxc622x_exit);
+
+MODULE_AUTHOR("Robbie Cao<hjcao@memsic.com>");
+MODULE_DESCRIPTION("MEMSIC MXC622X (DTOS) Accelerometer Sensor Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/i2c/chips/pca963x.c b/drivers/i2c/chips/pca963x.c
new file mode 100644
index 00000000000..37cc9d91477
--- /dev/null
+++ b/drivers/i2c/chips/pca963x.c
@@ -0,0 +1,430 @@
+/* pca963x.c - 4-bit I2C-bus LED driver
+ *
+ * Copyright (C) 2008 HTC Corporation.
+ * Author: Shan-Fu Chiou <sfchiou@gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/leds.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+static uint8_t address[] = { 0x02, 0x03, 0x04 };
+static DEFINE_SPINLOCK(pca963x_lock);
+
+enum op_t {
+	OP_SET_BLINK,
+	OP_SET_GRPPWM,
+	OP_SET_GRPFREQ,
+	OP_SET_BLUE_BRIGHTNESS,
+	OP_SET_GREEN_BRIGHTNESS,
+	OP_SET_RED_BRIGHTNESS,
+};
+
+enum power_mode {
+	MODE_SLEEP,
+	MODE_NORMAL,
+};
+
+struct pca963x_t {
+	uint8_t colors[3];
+	uint8_t blink;
+	uint8_t grppwm;
+	uint8_t grpfreq;
+};
+
+struct pca963x_data {
+	struct pca963x_t data;
+	uint8_t dirty;
+	uint8_t status;
+	enum power_mode mode;
+	struct work_struct work;
+	struct i2c_client *client;
+	struct led_classdev leds[3];	/* blue, green, red */
+};
+
+static ssize_t pca963x_blink_show(struct device *dev,
+				  struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	if (((pca963x->dirty >> OP_SET_BLINK) & 0x01))
+		flush_scheduled_work();
+	return sprintf(buf, "%u\n", pca963x->data.blink);
+}
+
+static ssize_t pca963x_blink_store(struct device *dev,
+				   struct device_attribute *attr,
+				   const char *buf, size_t count)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	int val = -1;
+
+	sscanf(buf, "%u", &val);
+	if (val < 0 || val > 1)
+		return -EINVAL;
+
+	spin_lock(&pca963x_lock);
+	pca963x->dirty |= 1 << OP_SET_BLINK;
+	pca963x->data.blink = val;
+	spin_unlock(&pca963x_lock);
+	schedule_work(&pca963x->work);
+
+	return count;
+}
+
+static DEVICE_ATTR(blink, 0644, pca963x_blink_show, pca963x_blink_store);
+
+static ssize_t pca963x_grpfreq_show(struct device *dev,
+				    struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	if (((pca963x->dirty >> OP_SET_GRPFREQ) & 0x01))
+		flush_scheduled_work();
+	return sprintf(buf, "%u\n", pca963x->data.grpfreq);
+}
+
+static ssize_t pca963x_grpfreq_store(struct device *dev,
+				     struct device_attribute *attr,
+				     const char *buf, size_t count)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	unsigned long val = simple_strtoul(buf, NULL, 10);
+
+	if (val > 0xff)
+		return -EINVAL;
+
+	spin_lock(&pca963x_lock);
+	pca963x->dirty |= 1 << OP_SET_GRPFREQ;
+	pca963x->data.grpfreq = val;
+	spin_unlock(&pca963x_lock);
+	schedule_work(&pca963x->work);
+
+	return count;
+}
+
+static DEVICE_ATTR(grpfreq, 0644, pca963x_grpfreq_show, pca963x_grpfreq_store);
+
+static ssize_t pca963x_grppwm_show(struct device *dev,
+				   struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	if (((pca963x->dirty >> OP_SET_GRPPWM) & 0x01))
+		flush_scheduled_work();
+	return sprintf(buf, "%u\n", pca963x->data.grppwm);
+}
+
+static ssize_t pca963x_grppwm_store(struct device *dev,
+				    struct device_attribute *attr,
+				    const char *buf, size_t count)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	unsigned long val = simple_strtoul(buf, NULL, 10);
+
+	if (val > 0xff)
+		return -EINVAL;
+
+	spin_lock(&pca963x_lock);
+	pca963x->dirty |= 1 << OP_SET_GRPPWM;
+	pca963x->data.grppwm = val;
+	spin_unlock(&pca963x_lock);
+	schedule_work(&pca963x->work);
+
+	return count;
+}
+
+static DEVICE_ATTR(grppwm, 0644, pca963x_grppwm_show, pca963x_grppwm_store);
+
+static void led_brightness_set(struct led_classdev *led_cdev,
+			       enum led_brightness brightness)
+{
+	struct pca963x_data *pca963x;
+	int idx = 2;
+
+	spin_lock(&pca963x_lock);
+	if (!strcmp(led_cdev->name, "blue")) {
+		idx = 0;
+	} else if (!strcmp(led_cdev->name, "green")) {
+		idx = 1;
+	} else {
+		idx = 2;
+	}
+	pca963x = container_of(led_cdev, struct pca963x_data, leds[idx]);
+	pca963x->data.colors[idx] = brightness;
+	pca963x->dirty |= (1 << (OP_SET_BLUE_BRIGHTNESS + idx));
+	spin_unlock(&pca963x_lock);
+
+	schedule_work(&pca963x->work);
+
+}
+
+static void pca963x_update_brightness(struct pca963x_data *pca963x, int idx,
+				      int brightness)
+{
+	if (brightness > LED_OFF) {
+		if (brightness == LED_FULL) {
+			pca963x->status &= ~(1 << idx);
+			pca963x->status |= (1 << (idx + 4));
+		} else {
+			pca963x->status |= (1 << idx);
+			pca963x->status &= ~(1 << (idx + 4));
+		}
+	} else {
+		pca963x->status &= ~(1 << idx);
+		pca963x->status &= ~(1 << (idx + 4));
+	}
+	i2c_smbus_write_byte_data(pca963x->client, address[idx], brightness);
+}
+
+static void pca963x_work_func(struct work_struct *work)
+{
+	int ret;
+	uint8_t dirty = 0;
+	struct pca963x_t work_data;
+	struct pca963x_data *pca963x =
+	    container_of(work, struct pca963x_data, work);
+
+	spin_lock(&pca963x_lock);
+	work_data = pca963x->data;
+	dirty = pca963x->dirty;
+	pca963x->dirty = 0;
+	spin_unlock(&pca963x_lock);
+
+	ret = i2c_smbus_read_byte_data(pca963x->client, 0x00);
+	/* check if should switch to normal mode */
+	if (!pca963x->mode) {
+		i2c_smbus_write_byte_data(pca963x->client, 0x00, 0x01);
+		pca963x->mode = MODE_NORMAL;
+		i2c_smbus_write_byte_data(pca963x->client, 0x08, 0xFF);
+	}
+
+	if ((dirty >> OP_SET_BLINK) & 0x01) {
+		ret = i2c_smbus_read_byte_data(pca963x->client, 0x01);
+		if (work_data.blink)	/* enable blinking */
+			i2c_smbus_write_byte_data(pca963x->client, 0x01,
+						  ret | 0x20);
+		else {
+			/* set group duty cycle control to default */
+			i2c_smbus_write_byte_data(pca963x->client, 0x06, 0xFF);
+			/* set group frequency to default */
+			i2c_smbus_write_byte_data(pca963x->client, 0x07, 0x00);
+			/* enable dimming */
+			i2c_smbus_write_byte_data(pca963x->client, 0x01,
+						  ret & 0xDF);
+		}
+	}
+
+	if ((dirty >> OP_SET_GRPPWM) & 0x01) {
+		i2c_smbus_write_byte_data(pca963x->client, 0x06,
+					  work_data.grppwm);
+	}
+
+	if ((dirty >> OP_SET_GRPFREQ) & 0x01) {
+		i2c_smbus_write_byte_data(pca963x->client, 0x07,
+					  work_data.grpfreq);
+	}
+
+	if ((dirty >> OP_SET_BLUE_BRIGHTNESS) & 0x01)
+		pca963x_update_brightness(pca963x, 0, work_data.colors[0]);
+
+	if ((dirty >> OP_SET_GREEN_BRIGHTNESS) & 0x01)
+		pca963x_update_brightness(pca963x, 1, work_data.colors[1]);
+
+	if ((dirty >> OP_SET_RED_BRIGHTNESS) & 0x01)
+		pca963x_update_brightness(pca963x, 2, work_data.colors[2]);
+
+	/* check if could go to low power mode */
+	if (((pca963x->status & 0x0F) == 0) && (!work_data.blink)) {
+		i2c_smbus_write_byte_data(pca963x->client, 0x08, 0xAA);
+		i2c_smbus_write_byte_data(pca963x->client, 0x00, 0x11);
+		pca963x->mode = MODE_SLEEP;
+	}
+}
+
+static void set_pca963x_default(struct i2c_client *client)
+{
+	i2c_smbus_write_byte_data(client, 0x00, 0x01);
+	i2c_smbus_write_byte_data(client, 0x01, 0x00);
+	/* set all LEDx brightness off */
+	i2c_smbus_write_byte_data(client, address[0], LED_OFF);
+	i2c_smbus_write_byte_data(client, address[1], LED_OFF);
+	i2c_smbus_write_byte_data(client, address[2], LED_OFF);
+	/* set group duty cycle control to default */
+	i2c_smbus_write_byte_data(client, 0x06, 0xFF);
+	/* set group frequency to default */
+	i2c_smbus_write_byte_data(client, 0x07, 0x00);
+	/*
+	 * set LEDx individual brightness and group dimming/blinking
+	 * can be controlled by * its PWMx register and GRPPWM registers.
+	 */
+	i2c_smbus_write_byte_data(client, 0x08, 0xFF);
+	/* low power mode. oscillator off */
+	i2c_smbus_write_byte_data(client, 0x00, 0x11);
+}
+
+static int pca963x_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	int ret = 0;
+
+	struct pca963x_data *pca963x;
+
+	if (!i2c_check_functionality(client->adapter,
+				I2C_FUNC_SMBUS_BYTE_DATA)) {
+		ret = -ENODEV;
+		goto exit;
+	}
+
+	pca963x = kzalloc(sizeof(struct pca963x_data), GFP_KERNEL);
+	if (pca963x == NULL) {
+		ret = -ENOMEM;
+		goto err_alloc_failed;
+	}
+
+	INIT_WORK(&pca963x->work, pca963x_work_func);
+
+	pca963x->client = client;
+
+	pca963x->leds[0].name = "blue";
+	pca963x->leds[0].brightness = LED_OFF;
+	pca963x->leds[0].brightness_set = led_brightness_set;
+
+	pca963x->leds[1].name = "green";
+	pca963x->leds[1].brightness = LED_OFF;
+	pca963x->leds[1].brightness_set = led_brightness_set;
+
+	pca963x->leds[2].name = "red";
+	pca963x->leds[2].brightness = LED_OFF;
+	pca963x->leds[2].brightness_set = led_brightness_set;
+
+	pca963x->dirty = 0;
+	pca963x->status = 0;
+
+	pca963x->data.colors[0] = LED_OFF;
+	pca963x->data.colors[1] = LED_OFF;
+	pca963x->data.colors[2] = LED_OFF;
+	pca963x->data.blink = 0;
+	pca963x->data.grppwm = 0;
+	pca963x->data.grpfreq = 0;
+	i2c_set_clientdata(client, pca963x);
+
+	set_pca963x_default(client);
+	pca963x->mode = MODE_SLEEP;
+
+	/* blue */
+	ret = led_classdev_register(&client->dev, &pca963x->leds[0]);
+	if (ret < 0) {
+		printk(KERN_ERR "pca963x: led_classdev_register failed\n");
+		goto err_led0_classdev_register_failed;
+	}
+	/* green */
+	ret = led_classdev_register(&client->dev, &pca963x->leds[1]);
+	if (ret < 0) {
+		printk(KERN_ERR "pca963x: led_classdev_register failed\n");
+		goto err_led1_classdev_register_failed;
+	}
+	/* red */
+	ret = led_classdev_register(&client->dev, &pca963x->leds[2]);
+	if (ret < 0) {
+		printk(KERN_ERR "pca963x: led_classdev_register failed\n");
+		goto err_led2_classdev_register_failed;
+	}
+
+	ret = device_create_file(&client->dev, &dev_attr_blink);
+	ret = device_create_file(&client->dev, &dev_attr_grppwm);
+	ret = device_create_file(&client->dev, &dev_attr_grpfreq);
+
+	return 0;
+
+err_led2_classdev_register_failed:
+	led_classdev_unregister(&pca963x->leds[2]);
+err_led1_classdev_register_failed:
+	led_classdev_unregister(&pca963x->leds[1]);
+err_led0_classdev_register_failed:
+	led_classdev_unregister(&pca963x->leds[0]);
+err_alloc_failed:
+	kfree(pca963x);
+exit:
+	return ret;
+}
+
+static int pca963x_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	flush_scheduled_work();
+	return 0;
+}
+
+static int pca963x_remove(struct i2c_client *client)
+{
+	struct pca963x_data *pca963x = i2c_get_clientdata(client);
+
+	cancel_work_sync(&pca963x->work);
+	device_remove_file(&client->dev, &dev_attr_blink);
+	device_remove_file(&client->dev, &dev_attr_grppwm);
+	device_remove_file(&client->dev, &dev_attr_grpfreq);
+	set_pca963x_default(client);
+	led_classdev_unregister(&pca963x->leds[0]);
+	led_classdev_unregister(&pca963x->leds[1]);
+	led_classdev_unregister(&pca963x->leds[2]);
+
+	kfree(pca963x);
+	return 0;
+}
+
+static const struct i2c_device_id pca963x_id[] = {
+	{ "pca963x", 0 },
+	{ }
+};
+
+static struct i2c_driver pca963x_driver = {
+	.driver = {
+		   .name = "pca963x",
+		   },
+	.probe = pca963x_probe,
+	.suspend = pca963x_suspend,
+	.remove = pca963x_remove,
+	.id_table = pca963x_id,
+};
+
+static int __init pca963x_init(void)
+{
+	return i2c_add_driver(&pca963x_driver);
+}
+
+static void __exit pca963x_exit(void)
+{
+	i2c_del_driver(&pca963x_driver);
+}
+
+MODULE_AUTHOR("Shan-Fu Chiou <sfchiou@gmail.com>");
+MODULE_DESCRIPTION("pca963x driver");
+MODULE_LICENSE("GPL");
+
+module_init(pca963x_init);
+module_exit(pca963x_exit);
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index cd50c00ab20..de0fa993055 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -149,6 +149,15 @@ config INPUT_APMPOWER
 	  To compile this driver as a module, choose M here: the
 	  module will be called apm-power.
 
+config INPUT_KEYRESET
+	tristate "Reset key"
+	depends on INPUT
+	---help---
+	  Say Y here if you want to reboot when some keys are pressed;
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called keyreset.
+
 config XEN_KBDDEV_FRONTEND
 	tristate "Xen virtual keyboard and mouse support"
 	depends on XEN_FBDEV_FRONTEND
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 4c9c745a702..eef9e24eab9 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_INPUT_TOUCHSCREEN)	+= touchscreen/
 obj-$(CONFIG_INPUT_MISC)	+= misc/
 
 obj-$(CONFIG_INPUT_APMPOWER)	+= apm-power.o
+obj-$(CONFIG_INPUT_KEYRESET)	+= keyreset.o
 
 obj-$(CONFIG_XEN_KBDDEV_FRONTEND)	+= xen-kbdfront.o
diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c
index dee6706038a..eb938d2297a 100644
--- a/drivers/input/evdev.c
+++ b/drivers/input/evdev.c
@@ -20,6 +20,7 @@
 #include <linux/input.h>
 #include <linux/major.h>
 #include <linux/device.h>
+#include <linux/wakelock.h>
 #include "input-compat.h"
 
 struct evdev {
@@ -43,6 +44,8 @@ struct evdev_client {
 	struct fasync_struct *fasync;
 	struct evdev *evdev;
 	struct list_head node;
+	struct wake_lock wake_lock;
+	char name[28];
 };
 
 static struct evdev *evdev_table[EVDEV_MINORS];
@@ -55,6 +58,7 @@ static void evdev_pass_event(struct evdev_client *client,
 	 * Interrupts are disabled, just acquire the lock
 	 */
 	spin_lock(&client->buffer_lock);
+	wake_lock_timeout(&client->wake_lock, 5 * HZ);
 	client->buffer[client->head++] = *event;
 	client->head &= EVDEV_BUFFER_SIZE - 1;
 	spin_unlock(&client->buffer_lock);
@@ -71,8 +75,11 @@ static void evdev_event(struct input_handle *handle,
 	struct evdev *evdev = handle->private;
 	struct evdev_client *client;
 	struct input_event event;
+	struct timespec ts;
 
-	do_gettimeofday(&event.time);
+	ktime_get_ts(&ts);
+	event.time.tv_sec = ts.tv_sec;
+	event.time.tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 	event.type = type;
 	event.code = code;
 	event.value = value;
@@ -233,6 +240,7 @@ static int evdev_release(struct inode *inode, struct file *file)
 	mutex_unlock(&evdev->mutex);
 
 	evdev_detach_client(evdev, client);
+	wake_lock_destroy(&client->wake_lock);
 	kfree(client);
 
 	evdev_close_device(evdev);
@@ -269,6 +277,9 @@ static int evdev_open(struct inode *inode, struct file *file)
 	}
 
 	spin_lock_init(&client->buffer_lock);
+	snprintf(client->name, sizeof(client->name), "%s-%d",
+			dev_name(&evdev->dev), task_tgid_vnr(current));
+	wake_lock_init(&client->wake_lock, WAKE_LOCK_SUSPEND, client->name);
 	client->evdev = evdev;
 	evdev_attach_client(evdev, client);
 
@@ -332,6 +343,8 @@ static int evdev_fetch_next_event(struct evdev_client *client,
 	if (have_event) {
 		*event = client->buffer[client->tail++];
 		client->tail &= EVDEV_BUFFER_SIZE - 1;
+		if (client->head == client->tail)
+			wake_unlock(&client->wake_lock);
 	}
 
 	spin_unlock_irq(&client->buffer_lock);
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index ee98b1bc5d8..6e05b53f1f2 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -423,4 +423,23 @@ config KEYBOARD_W90P910
 	  To compile this driver as a module, choose M here: the
 	  module will be called w90p910_keypad.
 
+config KEYBOARD_AK98_2KEY
+	tristate "ak98_gpio_2key Buttons"
+	depends on ARCH_AK98
+	help
+	  This driver implements support for buttons connected
+	  to GPIO pins of various CPUs (and some other chips).
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called ak98_gpio_2keys.
+
+config KEYBOARD_AK98_KEYPAD
+	tristate "ak98 matrix keypad support"
+	depends on ARCH_AK98
+	help
+	  This driver implements support for buttons connected
+	  to GPIO pins of various CPUs (and some other chips).
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called ak98_matrix_keypad.
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index babad5e58b7..7da8f492dbc 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -37,3 +37,5 @@ obj-$(CONFIG_KEYBOARD_TOSA)		+= tosakbd.o
 obj-$(CONFIG_KEYBOARD_TWL4030)		+= twl4030_keypad.o
 obj-$(CONFIG_KEYBOARD_XTKBD)		+= xtkbd.o
 obj-$(CONFIG_KEYBOARD_W90P910)		+= w90p910_keypad.o
+obj-$(CONFIG_KEYBOARD_AK98_2KEY)	+= ak98_gpio_2keys.o
+obj-$(CONFIG_KEYBOARD_AK98_KEYPAD)	+= ak98_matrix_keypad.o
\ No newline at end of file
diff --git a/drivers/input/keyboard/ak98_gpio_2keys.c b/drivers/input/keyboard/ak98_gpio_2keys.c
new file mode 100755
index 00000000000..cf1d8f067c3
--- /dev/null
+++ b/drivers/input/keyboard/ak98_gpio_2keys.c
@@ -0,0 +1,380 @@
+/* 
+ * drivers/input/keyboard/ak98_gpio_2keys.c
+ * 
+ * Driver for keys on GPIO lines capable of generating interrupts.
+ * 
+ *   Copyright 2010 Anyka
+ *
+ * - gpio-keys.c
+ *	Copyright (c) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/pm.h>
+#include <linux/sysctl.h>
+#include <linux/proc_fs.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/workqueue.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <mach/gpio_keys.h>
+
+struct gpio_button_data {
+	struct ak98_gpio_keys_button *button;
+	struct input_dev *input;
+	struct timer_list timer;
+	struct work_struct work;
+};
+
+struct gpio_keys_drvdata {
+	struct input_dev *input;
+	struct gpio_button_data data[0];
+};
+
+static int gpio_get_value(unsigned long pin)
+{
+	return ak98_gpio_getpin(pin);
+}
+
+static int gpio_init(struct ak98_gpio_keys_button *button_data)
+{
+	ak98_setpin_as_gpio(button_data->gpio);
+	ak98_gpio_cfgpin(button_data->gpio, button_data->dir);
+	if (button_data->pullup == AK98_PULLUP_ENABLE || button_data->pullup == AK98_PULLUP_DISABLE)
+		ak98_gpio_pullup(button_data->gpio, button_data->pullup);
+	if (button_data->pulldown == AK98_PULLDOWN_ENABLE || button_data->pulldown == AK98_PULLDOWN_DISABLE)
+		ak98_gpio_pulldown(button_data->gpio, button_data->pulldown);
+	ak98_gpio_intpol(button_data->gpio, button_data->int_pol);
+	
+	return 0;
+}
+
+#if 0
+static int gpio_direction_input(unsigned long pin)
+{
+	ak98_setpin_as_gpio(pin);
+	ak98_gpio_cfgpin(pin, AK98_GPIO_DIR_INPUT);
+	if(pin == AK98_GPIO_115) {
+		ak98_gpio_pullup(pin, AK98_PULLUP_ENABLE);
+		ak98_gpio_intpol(pin, AK98_GPIO_INT_LOWLEVEL);
+	}
+	else {
+		ak98_gpio_pulldown(pin, AK98_PULLDOWN_ENABLE);
+		ak98_gpio_intpol(pin, AK98_GPIO_INT_HIGHLEVEL);
+	}
+	
+	return 0;
+}
+#endif
+
+static void disable_button_irq(unsigned int irq)
+{
+	unsigned int pin;
+
+	pin = ak98_irq_to_gpio(irq);
+	ak98_gpio_intpol(pin, AK98_GPIO_INT_LOWLEVEL);
+}
+static void enable_button_irq(unsigned int irq)
+{
+	unsigned int pin;
+
+	pin = ak98_irq_to_gpio(irq);	
+	ak98_gpio_intpol(pin, AK98_GPIO_INT_HIGHLEVEL);
+}
+
+static void gpio_keys_report_event(struct work_struct *work)
+{
+	struct gpio_button_data *bdata =
+		container_of(work, struct gpio_button_data, work);
+	struct ak98_gpio_keys_button *button = bdata->button;
+	struct input_dev *input = bdata->input;
+	unsigned int type = button->type ?: EV_KEY;
+	int state = (gpio_get_value(button->gpio) ? 1 : 0) ^ button->active_low;
+	
+	input_event(input, type, button->code, !!state);
+	input_sync(input);
+}
+
+static void gpio_keys_timer(unsigned long _data)
+{
+	struct gpio_button_data *data = (struct gpio_button_data *)_data;
+	
+	schedule_work(&data->work);
+}
+
+static irqreturn_t gpio_keys_isr(int irq, void *dev_id)
+{
+	struct gpio_button_data *bdata = dev_id;
+	struct ak98_gpio_keys_button *button = bdata->button;
+
+	BUG_ON(irq != ak98_gpio_to_irq(button->gpio));
+
+	//disalbe gpio_irq when the button down
+	if(gpio_get_value(button->gpio))
+		disable_button_irq(irq);
+
+	//enable gpiot_irq when the button up
+	if (!gpio_get_value(button->gpio))
+		enable_button_irq(irq);
+
+	if (button->debounce_interval)
+		mod_timer(&bdata->timer,
+			jiffies + msecs_to_jiffies(button->debounce_interval));
+	else
+		schedule_work(&bdata->work);
+
+	return IRQ_HANDLED;
+}
+
+
+
+static int __devinit gpio_keys_probe(struct platform_device *pdev)
+{	
+	struct ak98_gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_keys_drvdata *ddata;
+	
+	struct input_dev *input;
+	int i, error;
+	int wakeup = 0;
+
+	ddata = kzalloc(sizeof(struct gpio_keys_drvdata) +
+			pdata->nbuttons * sizeof(struct gpio_button_data),
+			GFP_KERNEL);
+	input = input_allocate_device();
+	if (!ddata || !input) {
+		error = -ENOMEM;
+		goto fail1;
+	}
+
+	platform_set_drvdata(pdev, ddata);
+
+	input->name = pdev->name;
+	input->phys = "gpio-keys/input0";
+	input->dev.parent = &pdev->dev;
+
+	input->id.bustype = BUS_HOST;
+	input->id.vendor = 0x0001;
+	input->id.product = 0x0001;
+	input->id.version = 0x0100;
+
+	/* Enable auto repeat feature of Linux input subsystem */
+	if (pdata->rep)
+		__set_bit(EV_REP, input->evbit);
+	
+	//__set_bit(SW_LID, input->swbit); don't not need now
+
+	ddata->input = input;
+
+
+	for (i = 0; i < pdata->nbuttons; i++) 
+	{
+		struct ak98_gpio_keys_button *button = &pdata->buttons[i];
+		struct gpio_button_data *bdata = &ddata->data[i];
+
+		int irq;
+		unsigned int type = button->type ?: EV_KEY;
+		
+		bdata->input = input;
+		bdata->button = button;
+		
+		setup_timer(&bdata->timer,
+		    gpio_keys_timer, (unsigned long)bdata);
+		
+		INIT_WORK(&bdata->work, gpio_keys_report_event);
+		
+	
+		error = gpio_init(button);
+		if (error < 0) {
+			pr_err("gpio-keys: failed to configure input"
+				" direction for GPIO %d, error %d\n",
+				button->gpio, error);
+			ak98_gpio_free(button->gpio);
+			goto fail2;
+		}
+
+		irq = ak98_gpio_to_irq(button->gpio);
+		if (irq < 0) {
+			error = irq;
+			pr_err("gpio-keys: Unable to get irq number"
+				" for GPIO %d, error %d\n",
+				button->gpio, error);
+			ak98_gpio_free(button->gpio);
+			goto fail2;
+		}
+
+		error = request_irq(irq, gpio_keys_isr, 
+			        (button->active_low)?(IRQF_TRIGGER_LOW):(IRQF_TRIGGER_HIGH),
+				    button->desc ? button->desc : "gpio_keys", bdata);
+	
+		if (error) {
+			pr_err("gpio-keys: Unable to claim irq %d; error %d\n",
+				irq, error);
+			ak98_gpio_free(button->gpio);
+			goto fail2;
+		}
+
+		if (button->wakeup)
+			wakeup = 1;
+
+		input_set_capability(input, type, button->code);
+
+#ifdef CONFIG_PM
+		ak98_gpio_wakeup_pol(button->gpio, button->active_low?(AK98_FALLING_TRIGGERED):(AK98_RISING_TRIGGERED));
+#endif
+	}
+
+	
+	error = input_register_device(input);
+	if (error) {
+		pr_err("gpio-keys: Unable to register input device, "
+			"error: %d\n", error);
+		goto fail2;
+	}
+
+	device_init_wakeup(&pdev->dev, wakeup);
+
+	return 0;
+
+ fail2:
+	while (--i >= 0) {
+		free_irq(ak98_gpio_to_irq(pdata->buttons[i].gpio), &ddata->data[i]);
+		if (pdata->buttons[i].debounce_interval)
+			del_timer_sync(&ddata->data[i].timer);
+		cancel_work_sync(&ddata->data[i].work);
+		ak98_gpio_free(pdata->buttons[i].gpio);
+	}
+
+	platform_set_drvdata(pdev, NULL);
+ fail1:
+	input_free_device(input);
+	kfree(ddata);
+
+	return error;
+}
+
+static int __devexit gpio_keys_remove(struct platform_device *pdev)
+{	
+	struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+
+	struct gpio_keys_drvdata *ddata = platform_get_drvdata(pdev);
+	struct input_dev *input = ddata->input;
+	int i;
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	for (i = 0; i < pdata->nbuttons; i++) {
+		int irq = ak98_gpio_to_irq(pdata->buttons[i].gpio);
+		free_irq(irq, &ddata->data[i]);
+		if (pdata->buttons[i].debounce_interval)
+			del_timer_sync(&ddata->data[i].timer);
+		cancel_work_sync(&ddata->data[i].work);
+		ak98_gpio_free(pdata->buttons[i].gpio);
+	}
+
+	input_unregister_device(input);
+
+	return 0;
+}
+
+#if 0
+static void print()
+{
+	printk("-------------------------\n");
+	printk("Po:\t%x\n", REG32(AK98_WGPIO_POLARITY));
+	printk("Cle:\t%x\n", REG32(AK98_WGPIO_CLEAR));
+	printk("Ena:\t%x\n", REG32(AK98_WGPIO_ENABLE));
+	printk("Sta:\t%x\n", REG32(AK98_WGPIO_STATUS));
+	printk("-------------------------\n");
+}
+#endif
+
+#ifdef CONFIG_PM
+static int gpio_keys_suspend(struct device *dev)
+{
+
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ak98_gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+	
+	int i;
+
+	if (device_may_wakeup(&pdev->dev)) {
+		for (i = 0; i < pdata->nbuttons; i++) {
+			struct ak98_gpio_keys_button *button = &pdata->buttons[i];
+			if (button->wakeup) 
+			{
+				ak98_gpio_wakeup(button->gpio, AK98_WAKEUP_ENABLE);				
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_keys_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ak98_gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+		
+	int i;
+
+	if (device_may_wakeup(&pdev->dev)) {
+		for (i = 0; i < pdata->nbuttons; i++) {
+			struct ak98_gpio_keys_button *button = &pdata->buttons[i];
+			if (button->wakeup) 
+			{
+				ak98_gpio_wakeup(button->gpio, AK98_WAKEUP_DISABLE);				
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops gpio_keys_pm_ops = {
+	.suspend	= gpio_keys_suspend,
+	.resume		= gpio_keys_resume,
+};
+#endif
+
+static struct platform_driver gpio_keys_device_driver = {
+	.probe		= gpio_keys_probe,
+	.remove		= __devexit_p(gpio_keys_remove),
+	.driver		= {
+		.name	= "gpio_keys",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &gpio_keys_pm_ops,
+#endif
+	}
+};
+
+static int __init gpio_keys_init(void)
+{
+	return platform_driver_register(&gpio_keys_device_driver);
+}
+
+static void __exit gpio_keys_exit(void)
+{
+	platform_driver_unregister(&gpio_keys_device_driver);
+}
+
+module_init(gpio_keys_init);
+module_exit(gpio_keys_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Anyka <xx@anyka.oa");
+MODULE_DESCRIPTION("Keyboard driver for CPU GPIOs");
+MODULE_ALIAS("platform:gpio-keys");
diff --git a/drivers/input/keyboard/ak98_matrix_keypad.c b/drivers/input/keyboard/ak98_matrix_keypad.c
new file mode 100644
index 00000000000..21f1b5dceaa
--- /dev/null
+++ b/drivers/input/keyboard/ak98_matrix_keypad.c
@@ -0,0 +1,570 @@
+/*
+ *  GPIO driven matrix keyboard driver
+ *
+ *  Copyright (c) 2010 Anyka <zhou_wenyong@anyka.oa>
+ *
+ *  Based on matrix_keypad.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/input/ak98matrix_keypad.h>
+#include <mach/gpio.h>
+
+struct matrix_keypad {
+	const struct matrix_keypad_platform_data *pdata;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+
+	uint32_t last_key_state[MATRIX_MAX_COLS];
+	struct delayed_work work;
+	bool scan_pending;
+	bool stopped;
+	spinlock_t lock;
+	bool start_close_int;
+};
+
+static int gpio_request(unsigned long gpio, const char *label)
+{
+	return ak98_gpio_request(gpio, label);
+}
+static void gpio_free(unsigned long gpio)
+{
+	ak98_gpio_free(gpio);
+}
+
+static int gpio_to_irq(unsigned long pin)
+{
+	return ak98_gpio_to_irq(pin);
+}
+
+
+static inline int gpio_get_value_cansleep(unsigned gpio)
+{
+	might_sleep();
+	return ak98_gpio_getpin(gpio);
+}
+static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+{
+	might_sleep();
+	ak98_gpio_setpin(gpio, value);
+}
+
+/*
+ * NOTE: normally the GPIO has to be put into HiZ when de-activated to cause
+ * minmal side effect when scanning other columns, here it is configured to
+ * be input, and it should work on most platforms.
+ */
+static void __activate_col(const struct matrix_keypad_platform_data *pdata,
+			   int col, bool on)
+{
+	bool level_on = pdata->active_low;
+	int i;
+
+	for (i=0; i<pdata->num_col_gpios;i++)
+	{
+		if (i == col)
+			continue;
+		if (on) 
+		{
+			ak98_gpio_setpin(pdata->col_gpios[i], level_on);
+		} 
+		else 
+		{
+			ak98_gpio_setpin(pdata->col_gpios[i], !level_on);
+		}
+	}
+}
+
+static void activate_other_col(const struct matrix_keypad_platform_data *pdata,
+			 int col, bool on)
+{
+	__activate_col(pdata, col, on);
+
+	if (on && pdata->col_scan_delay_us)
+		udelay(pdata->col_scan_delay_us);
+}
+
+static bool row_asserted(const struct matrix_keypad_platform_data *pdata,
+			 int row)
+{
+	return gpio_get_value_cansleep(pdata->row_gpios[row]) ?
+			!pdata->active_low : pdata->active_low;
+}
+
+static void enable_row_irqs(struct matrix_keypad *keypad)
+{
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++)
+		enable_irq(gpio_to_irq(pdata->row_gpios[i]));
+}
+
+static void disable_row_irqs(struct matrix_keypad *keypad)
+{
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++)
+		disable_irq_nosync(gpio_to_irq(pdata->row_gpios[i]));
+}
+
+static void print_code(int code, int state)	
+{	
+	switch(code)
+	{
+	case KEY_VOLUMEUP:
+		printk("KEY_VOLUMEUP  "); break;
+	case KEY_RIGHT:
+		printk("KEY_RIGHT  "); break;
+	case KEY_MENU:
+		printk("KEY_MENU  "); break;
+	case KEY_UP:
+		printk("KEY_UP  "); break;
+	case KEY_REPLY:
+		printk("KEY_CENTER  "); break;
+	case KEY_DOWN:
+		printk("KEY_DOWN  "); break;
+	case KEY_VOLUMEDOWN:
+		printk("KEY_VOLUMEDOWN  "); break;
+	case KEY_LEFT:
+		printk("KEY_LEFT  "); break;
+	case KEY_HOME:
+		printk("KEY_HOME  "); break;
+	case KEY_BACK:
+		printk("KEY_BACK  "); break;
+	}
+	printk("%s \n", state?"Down":"Up");
+	
+	
+}
+
+
+/*
+ * This gets the keys from keyboard and reports it to input subsystem
+ */
+static void matrix_keypad_scan(struct work_struct *work)
+{
+	struct matrix_keypad *keypad =
+		container_of(work, struct matrix_keypad, work.work);
+	struct input_dev *input_dev = keypad->input_dev;
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	uint32_t new_state[MATRIX_MAX_COLS];
+	int row, col, code, num_cols;
+
+	/* de-activate all columns for scanning */
+	
+	
+	memset(new_state, 0, sizeof(new_state));
+
+
+	num_cols = pdata->num_col_gpios;
+	if (pdata->grounding)
+		num_cols++;
+	for (col = 0; col < num_cols; col++)
+	{		
+		activate_other_col(pdata, col, true);	
+		for (row = 0; row < pdata->num_row_gpios; row++)
+		{
+			new_state[col] |=
+				row_asserted(pdata, row) ? (1 << row) : 0;
+			
+		}	
+		
+		activate_other_col(pdata, col, false);
+	}	
+
+	/*
+	 *  if the button pressed is connected to the grounding line, the state of the row input line
+	 * connected to the button pressed will keep low level when we activate other lines
+	*/
+	if (pdata->grounding)
+	{
+		for (row=0; row < pdata->num_row_gpios; row++) 
+		{
+			for (col=0; col<num_cols; col++)
+				if ( !(new_state[col]&(1<<row)))
+					break;
+			if (col == num_cols)
+			{
+				//grounding line at the end
+				for (col=0; col<num_cols-1; col++)
+				{
+					new_state[col] = new_state[col] & (~(1<<row));
+				}
+			}
+		}
+
+	}
+	/* update input status, needed if keypad is connected to AW9523 */
+	ak98_gpio_getpin(pdata->row_gpios[0]);
+
+	num_cols = pdata->num_col_gpios;
+	if (pdata->grounding)
+		num_cols++;
+	for (col = 0; col < num_cols; col++) {
+		uint32_t bits_changed;
+
+		bits_changed = (keypad->last_key_state[col] ^ new_state[col]);
+
+		
+		if (bits_changed == 0)
+			continue;
+
+		for (row = 0; row < pdata->num_row_gpios; row++) {
+			if ((bits_changed & (1 << row)) == 0)
+				continue;
+
+			code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+			input_event(input_dev, EV_MSC, MSC_SCAN, code);
+			input_report_key(input_dev,
+					 keypad->keycodes[code],
+					 new_state[col] & (1 << row));
+			//print_code(keypad->keycodes[code], new_state[col] & (1 << row));
+		}
+	}
+	input_sync(input_dev);
+
+	memcpy(keypad->last_key_state, new_state, sizeof(new_state));
+
+
+	/* Enable IRQs again */
+	spin_lock_irq(&keypad->lock);
+	keypad->scan_pending = false;
+	enable_row_irqs(keypad);
+	spin_unlock_irq(&keypad->lock);
+}
+
+static irqreturn_t matrix_keypad_interrupt(int irq, void *id)
+{
+	struct matrix_keypad *keypad = id;
+	unsigned long flags;
+	static int i=0;
+
+	spin_lock_irqsave(&keypad->lock, flags);
+
+	/*
+	 * See if another IRQ beaten us to it and scheduled the
+	 * scan already. In that case we should not try to
+	 * disable IRQs again.
+	 */
+	if (unlikely(keypad->scan_pending || keypad->stopped))
+		goto out;
+
+	disable_row_irqs(keypad);
+	keypad->scan_pending = true;
+	schedule_delayed_work(&keypad->work,
+		msecs_to_jiffies(keypad->pdata->debounce_ms));
+
+out:
+	/* 
+	  *	if disable_row_irqs(keypad); in init_matrix_gpio is not reached, then
+	  *	we need excuting it here. otherwise system can not start successfully if
+	  *	one key is pressed when starting system.
+	*/
+	if (!keypad->start_close_int)
+	{
+		disable_row_irqs(keypad);
+		keypad->start_close_int = true;
+	}
+	spin_unlock_irqrestore(&keypad->lock, flags);
+	return IRQ_HANDLED;
+}
+
+static int matrix_keypad_start(struct input_dev *dev)
+{
+	struct matrix_keypad *keypad = input_get_drvdata(dev);
+
+	keypad->stopped = false;
+	mb();
+
+	/*
+	 * Schedule an immediate key scan to capture current key state;
+	 * columns will be activated and IRQs be enabled after the scan.
+	 */
+	schedule_delayed_work(&keypad->work, 0);
+
+	return 0;
+}
+
+static void matrix_keypad_stop(struct input_dev *dev)
+{
+	struct matrix_keypad *keypad = input_get_drvdata(dev);
+
+	keypad->stopped = true;
+	mb();
+	flush_work(&keypad->work.work);
+	/*
+	 * matrix_keypad_scan() will leave IRQs enabled;
+	 * we should disable them now.
+	 */
+	disable_row_irqs(keypad);
+}
+
+#ifdef CONFIG_PM
+static int matrix_keypad_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	matrix_keypad_stop(keypad->input_dev);
+
+	if (device_may_wakeup(&pdev->dev))
+		for (i = 0; i < pdata->num_row_gpios; i++)
+			enable_irq_wake(gpio_to_irq(pdata->row_gpios[i]));
+
+	return 0;
+}
+
+static int matrix_keypad_resume(struct platform_device *pdev)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	if (device_may_wakeup(&pdev->dev))
+		for (i = 0; i < pdata->num_row_gpios; i++)
+			disable_irq_wake(gpio_to_irq(pdata->row_gpios[i]));
+
+	matrix_keypad_start(keypad->input_dev);
+
+	return 0;
+}
+#else
+#define matrix_keypad_suspend	NULL
+#define matrix_keypad_resume	NULL
+#endif
+
+static int __devinit init_matrix_gpio(struct platform_device *pdev,
+					struct matrix_keypad *keypad)
+{
+	struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i, err = -(EINVAL);
+	unsigned long flags;
+
+	/* to fix the bug: can not start OS if one key is pressed when starting OS */
+	keypad->start_close_int = false;
+	/* initialized strobe lines as outputs, activated */
+	for (i = 0; i < pdata->num_col_gpios; i++) {
+			
+		err = gpio_request(pdata->col_gpios[i], "matrix_kbd_col");
+		if (err) {
+			dev_err(&pdev->dev,
+				"failed to request GPIO%d for COL%d\n",
+				pdata->col_gpios[i], i);
+			goto err_free_cols;
+		}
+		pdata->col_gpios_cfginfo.pin = pdata->col_gpios[i];
+		ak98_gpio_set(&(pdata->col_gpios_cfginfo));	
+		
+	}
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		
+		err = gpio_request(pdata->row_gpios[i], "matrix_kbd_row");
+		if (err) {
+			dev_err(&pdev->dev,
+				"failed to request GPIO%d for ROW%d\n",
+				pdata->row_gpios[i], i);
+			goto err_free_rows;
+		}
+		pdata->row_gpios_cfginfo.pin = pdata->row_gpios[i];
+		ak98_gpio_set(&(pdata->row_gpios_cfginfo));
+		ak98_gpio_intcfg(pdata->row_gpios[i], AK98_GPIO_INT_ENABLE);		
+	}
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		err = request_irq(gpio_to_irq(pdata->row_gpios[i]),
+				matrix_keypad_interrupt,
+				IRQF_DISABLED,
+				"matrix-keypad", keypad);
+		if (err) {
+			dev_err(&pdev->dev,
+				"Unable to acquire interrupt for GPIO line %i\n",
+				pdata->row_gpios[i]);
+			goto err_free_irqs;
+		}
+	}
+	
+	/* update input status, needed if keypad is connected to AW9523 */
+	ak98_gpio_getpin(pdata->row_gpios[0]);
+	
+	spin_lock_irqsave(&keypad->lock, flags);
+	/* initialized as disabled - enabled by input->open */
+	if (!keypad->start_close_int)
+	{
+		disable_row_irqs(keypad);
+		keypad->start_close_int = true;
+	}
+	spin_unlock_irqrestore(&keypad->lock, flags);
+	return 0;
+
+err_free_irqs:
+	while (--i >= 0)
+		free_irq(gpio_to_irq(pdata->row_gpios[i]), keypad);
+	i = pdata->num_row_gpios;
+err_free_rows:
+	while (--i >= 0)
+		gpio_free(pdata->row_gpios[i]);
+	i = pdata->num_col_gpios;
+err_free_cols:
+	while (--i >= 0)
+		gpio_free(pdata->col_gpios[i]);
+
+	return err;
+}
+
+static int __devinit matrix_keypad_probe(struct platform_device *pdev)
+{
+	const struct matrix_keypad_platform_data *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct matrix_keypad *keypad;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	int err;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	row_shift = get_count_order(pdata->num_col_gpios);
+	if (pdata->grounding)
+		row_shift++;
+
+	keypad = kzalloc(sizeof(struct matrix_keypad), GFP_KERNEL);
+	keycodes = kzalloc((pdata->num_row_gpios << (row_shift)) *
+				sizeof(*keycodes),
+			   GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !keycodes || !input_dev) {
+		err = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	keypad->input_dev = input_dev;
+	keypad->pdata = pdata;
+	keypad->keycodes = keycodes;
+		
+	keypad->row_shift = row_shift;	
+	keypad->stopped = true;
+	INIT_DELAYED_WORK(&keypad->work, matrix_keypad_scan);
+	spin_lock_init(&keypad->lock);
+
+	input_dev->name		= pdev->name;
+	input_dev->id.bustype	= BUS_HOST;
+	input_dev->dev.parent	= &pdev->dev;
+	input_dev->evbit[0]	= BIT_MASK(EV_KEY);// | BIT_MASK(EV_REP);
+	input_dev->open		= matrix_keypad_start;
+	input_dev->close	= matrix_keypad_stop;
+
+	input_dev->keycode	= keycodes;
+	input_dev->keycodesize	= sizeof(*keycodes);
+	input_dev->keycodemax	= pdata->num_row_gpios << (row_shift);
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+				   input_dev->keycode, input_dev->keybit);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+	input_set_drvdata(input_dev, keypad);
+
+	err = init_matrix_gpio(pdev, keypad);
+	if (err)
+		goto err_free_mem;
+
+	err = input_register_device(keypad->input_dev);
+	if (err)
+		goto err_free_mem;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+
+	return 0;
+
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keycodes);
+	kfree(keypad);
+	return err;
+}
+
+static int __devexit matrix_keypad_remove(struct platform_device *pdev)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		free_irq(gpio_to_irq(pdata->row_gpios[i]), keypad);
+		gpio_free(pdata->row_gpios[i]);
+	}
+
+	for (i = 0; i < pdata->num_col_gpios; i++)
+		gpio_free(pdata->col_gpios[i]);
+
+	input_unregister_device(keypad->input_dev);
+	platform_set_drvdata(pdev, NULL);
+	kfree(keypad->keycodes);
+	kfree(keypad);
+
+	return 0;
+}
+
+static struct platform_driver matrix_keypad_driver = {
+	.probe		= matrix_keypad_probe,
+	.remove		= __devexit_p(matrix_keypad_remove),
+	.suspend	= matrix_keypad_suspend,
+	.resume		= matrix_keypad_resume,
+	.driver		= {
+		.name	= "matrix-keypad",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init matrix_keypad_init(void)
+{
+	return platform_driver_register(&matrix_keypad_driver);
+}
+
+static void __exit matrix_keypad_exit(void)
+{
+	platform_driver_unregister(&matrix_keypad_driver);
+}
+
+module_init(matrix_keypad_init);
+module_exit(matrix_keypad_exit);
+
+MODULE_AUTHOR("Anyka <xxx@anyka.oa>");
+MODULE_DESCRIPTION("GPIO Driven Matrix Keypad Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:matrix-keypad");
+
diff --git a/drivers/input/keyboard/ak98mp5_matrix_keypad.c b/drivers/input/keyboard/ak98mp5_matrix_keypad.c
new file mode 100755
index 00000000000..cead53bc69b
--- /dev/null
+++ b/drivers/input/keyboard/ak98mp5_matrix_keypad.c
@@ -0,0 +1,559 @@
+/*
+ *  GPIO driven matrix keyboard driver
+ *
+ *  Copyright (c) 2010 Anyka <zhou_wenyong@anyka.oa>
+ *
+ *  Based on matrix_keypad.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/input/ak98matrix_keypad.h>
+#include <mach/gpio.h>
+
+struct matrix_keypad {
+	const struct matrix_keypad_platform_data *pdata;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+
+	uint32_t last_key_state[MATRIX_MAX_COLS];
+	struct delayed_work work;
+	bool scan_pending;
+	bool stopped;
+	spinlock_t lock;
+	bool start_close_int;
+};
+
+static int gpio_request(unsigned long gpio, const char *label)
+{
+	return ak98_gpio_request(gpio, label);
+}
+static void gpio_free(unsigned long gpio)
+{
+	ak98_gpio_free(gpio);
+}
+
+static int gpio_to_irq(unsigned long pin)
+{
+	return ak98_gpio_to_irq(pin);
+}
+
+
+static inline int gpio_get_value_cansleep(unsigned gpio)
+{
+	might_sleep();
+	return ak98_gpio_getpin(gpio);
+}
+static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+{
+	might_sleep();
+	ak98_gpio_setpin(gpio, value);
+}
+
+/*
+ * NOTE: normally the GPIO has to be put into HiZ when de-activated to cause
+ * minmal side effect when scanning other columns, here it is configured to
+ * be input, and it should work on most platforms.
+ */
+static void __activate_col(const struct matrix_keypad_platform_data *pdata,
+			   int col, bool on)
+{
+	bool level_on = pdata->active_low;
+	int i;
+
+	for (i=0; i<pdata->num_col_gpios;i++)
+	{
+		if (i == col)
+			continue;
+		if (on) 
+		{
+			ak98_gpio_setpin(pdata->col_gpios[i], level_on);
+		} 
+		else 
+		{
+			ak98_gpio_setpin(pdata->col_gpios[i], !level_on);
+		}
+	}
+}
+
+static void activate_other_col(const struct matrix_keypad_platform_data *pdata,
+			 int col, bool on)
+{
+	__activate_col(pdata, col, on);
+
+	if (on && pdata->col_scan_delay_us)
+		udelay(pdata->col_scan_delay_us);
+}
+
+static bool row_asserted(const struct matrix_keypad_platform_data *pdata,
+			 int row)
+{
+	return gpio_get_value_cansleep(pdata->row_gpios[row]) ?
+			!pdata->active_low : pdata->active_low;
+}
+
+static void enable_row_irqs(struct matrix_keypad *keypad)
+{
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++)
+		enable_irq(gpio_to_irq(pdata->row_gpios[i]));
+}
+
+static void disable_row_irqs(struct matrix_keypad *keypad)
+{
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++)
+		disable_irq_nosync(gpio_to_irq(pdata->row_gpios[i]));
+}
+
+static void print_code(int code, int state)	
+{	
+	switch(code)
+	{
+	case KEY_VOLUMEUP:
+		printk("KEY_VOLUMEUP  "); break;
+	case KEY_RIGHT:
+		printk("KEY_RIGHT  "); break;
+	case KEY_MENU:
+		printk("KEY_MENU  "); break;
+	case KEY_UP:
+		printk("KEY_UP  "); break;
+	case KEY_REPLY:
+		printk("KEY_CENTER  "); break;
+	case KEY_DOWN:
+		printk("KEY_DOWN  "); break;
+	case KEY_VOLUMEDOWN:
+		printk("KEY_VOLUMEDOWN  "); break;
+	case KEY_LEFT:
+		printk("KEY_LEFT  "); break;
+	case KEY_HOME:
+		printk("KEY_HOME  "); break;
+	case KEY_BACK:
+		printk("KEY_BACK  "); break;
+	}
+	printk("%s \n", state?"Down":"Up");
+	
+	
+}
+
+
+/*
+ * This gets the keys from keyboard and reports it to input subsystem
+ */
+static void matrix_keypad_scan(struct work_struct *work)
+{
+	struct matrix_keypad *keypad =
+		container_of(work, struct matrix_keypad, work.work);
+	struct input_dev *input_dev = keypad->input_dev;
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	uint32_t new_state[MATRIX_MAX_COLS];
+	int row, col, code, num_cols;
+
+	/* de-activate all columns for scanning */
+	
+	
+	memset(new_state, 0, sizeof(new_state));
+
+
+	num_cols = pdata->num_col_gpios;
+	if (pdata->grounding)
+		num_cols++;
+	for (col = 0; col < num_cols; col++)
+	{		
+		activate_other_col(pdata, col, true);	
+		for (row = 0; row < pdata->num_row_gpios; row++)
+		{
+			new_state[col] |=
+				row_asserted(pdata, row) ? (1 << row) : 0;
+			
+		}	
+		
+		activate_other_col(pdata, col, false);
+	}	
+
+	if (pdata->grounding)
+	{
+		for (row=0; row < pdata->num_row_gpios; row++) 
+		{
+			if ( (new_state[0]&(1<<row)) && (new_state[1]&(1<<row)) )
+			{		
+				new_state[0] = new_state[0] & (~(1<<row));
+			}
+		}
+
+	}
+	/* update input status, needed if keypad is connected to AW9523 */
+	ak98_gpio_getpin(pdata->row_gpios[0]);
+
+	num_cols = pdata->num_col_gpios;
+	if (pdata->grounding)
+		num_cols++;
+	for (col = 0; col < num_cols; col++) {
+		uint32_t bits_changed;
+
+		bits_changed = (keypad->last_key_state[col] ^ new_state[col]);
+
+		
+		if (bits_changed == 0)
+			continue;
+
+		for (row = 0; row < pdata->num_row_gpios; row++) {
+			if ((bits_changed & (1 << row)) == 0)
+				continue;
+
+			code = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+			input_event(input_dev, EV_MSC, MSC_SCAN, code);
+			input_report_key(input_dev,
+					 keypad->keycodes[code],
+					 new_state[col] & (1 << row));
+			//print_code(keypad->keycodes[code], new_state[col] & (1 << row));
+		}
+	}
+	input_sync(input_dev);
+
+	memcpy(keypad->last_key_state, new_state, sizeof(new_state));
+
+
+	/* Enable IRQs again */
+	spin_lock_irq(&keypad->lock);
+	keypad->scan_pending = false;
+	enable_row_irqs(keypad);
+	spin_unlock_irq(&keypad->lock);
+}
+
+static irqreturn_t matrix_keypad_interrupt(int irq, void *id)
+{
+	struct matrix_keypad *keypad = id;
+	unsigned long flags;
+	static int i=0;
+
+	spin_lock_irqsave(&keypad->lock, flags);
+
+	/*
+	 * See if another IRQ beaten us to it and scheduled the
+	 * scan already. In that case we should not try to
+	 * disable IRQs again.
+	 */
+	if (unlikely(keypad->scan_pending || keypad->stopped))
+		goto out;
+
+	disable_row_irqs(keypad);
+	keypad->scan_pending = true;
+	schedule_delayed_work(&keypad->work,
+		msecs_to_jiffies(keypad->pdata->debounce_ms));
+
+out:
+	/* 
+	  *	if disable_row_irqs(keypad); in init_matrix_gpio is not reached, then
+	  *	we need excuting it here. otherwise system can not start successfully if
+	  *	one key is pressed when starting system.
+	*/
+	if (!keypad->start_close_int)
+	{
+		disable_row_irqs(keypad);
+		keypad->start_close_int = true;
+	}
+	spin_unlock_irqrestore(&keypad->lock, flags);
+	return IRQ_HANDLED;
+}
+
+static int matrix_keypad_start(struct input_dev *dev)
+{
+	struct matrix_keypad *keypad = input_get_drvdata(dev);
+
+	keypad->stopped = false;
+	mb();
+
+	/*
+	 * Schedule an immediate key scan to capture current key state;
+	 * columns will be activated and IRQs be enabled after the scan.
+	 */
+	schedule_delayed_work(&keypad->work, 0);
+
+	return 0;
+}
+
+static void matrix_keypad_stop(struct input_dev *dev)
+{
+	struct matrix_keypad *keypad = input_get_drvdata(dev);
+
+	keypad->stopped = true;
+	mb();
+	flush_work(&keypad->work.work);
+	/*
+	 * matrix_keypad_scan() will leave IRQs enabled;
+	 * we should disable them now.
+	 */
+	disable_row_irqs(keypad);
+}
+
+#ifdef CONFIG_PM
+static int matrix_keypad_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	matrix_keypad_stop(keypad->input_dev);
+
+	if (device_may_wakeup(&pdev->dev))
+		for (i = 0; i < pdata->num_row_gpios; i++)
+			enable_irq_wake(gpio_to_irq(pdata->row_gpios[i]));
+
+	return 0;
+}
+
+static int matrix_keypad_resume(struct platform_device *pdev)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	if (device_may_wakeup(&pdev->dev))
+		for (i = 0; i < pdata->num_row_gpios; i++)
+			disable_irq_wake(gpio_to_irq(pdata->row_gpios[i]));
+
+	matrix_keypad_start(keypad->input_dev);
+
+	return 0;
+}
+#else
+#define matrix_keypad_suspend	NULL
+#define matrix_keypad_resume	NULL
+#endif
+
+static int __devinit init_matrix_gpio(struct platform_device *pdev,
+					struct matrix_keypad *keypad)
+{
+	struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i, err = -(EINVAL);
+	unsigned long flags;
+
+	/* to fix the bug: can not start OS if one key is pressed when starting OS */
+	keypad->start_close_int = false;
+	/* initialized strobe lines as outputs, activated */
+	for (i = 0; i < pdata->num_col_gpios; i++) {
+			
+		err = gpio_request(pdata->col_gpios[i], "matrix_kbd_col");
+		if (err) {
+			dev_err(&pdev->dev,
+				"failed to request GPIO%d for COL%d\n",
+				pdata->col_gpios[i], i);
+			goto err_free_cols;
+		}
+		pdata->col_gpios_cfginfo.pin = pdata->col_gpios[i];
+		ak98_gpio_set(&(pdata->col_gpios_cfginfo));	
+		
+	}
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		
+		err = gpio_request(pdata->row_gpios[i], "matrix_kbd_row");
+		if (err) {
+			dev_err(&pdev->dev,
+				"failed to request GPIO%d for ROW%d\n",
+				pdata->row_gpios[i], i);
+			goto err_free_rows;
+		}
+		pdata->row_gpios_cfginfo.pin = pdata->row_gpios[i];
+		ak98_gpio_set(&(pdata->row_gpios_cfginfo));
+		ak98_gpio_intcfg(pdata->row_gpios[i], AK98_GPIO_INT_ENABLE);		
+	}
+
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		err = request_irq(gpio_to_irq(pdata->row_gpios[i]),
+				matrix_keypad_interrupt,
+				IRQF_DISABLED,
+				"matrix-keypad", keypad);
+		if (err) {
+			dev_err(&pdev->dev,
+				"Unable to acquire interrupt for GPIO line %i\n",
+				pdata->row_gpios[i]);
+			goto err_free_irqs;
+		}
+	}
+	
+	/* update input status, needed if keypad is connected to AW9523 */
+	ak98_gpio_getpin(pdata->row_gpios[0]);
+	
+	spin_lock_irqsave(&keypad->lock, flags);
+	/* initialized as disabled - enabled by input->open */
+	if (!keypad->start_close_int)
+	{
+		disable_row_irqs(keypad);
+		keypad->start_close_int = true;
+	}
+	spin_unlock_irqrestore(&keypad->lock, flags);
+	return 0;
+
+err_free_irqs:
+	while (--i >= 0)
+		free_irq(gpio_to_irq(pdata->row_gpios[i]), keypad);
+	i = pdata->num_row_gpios;
+err_free_rows:
+	while (--i >= 0)
+		gpio_free(pdata->row_gpios[i]);
+	i = pdata->num_col_gpios;
+err_free_cols:
+	while (--i >= 0)
+		gpio_free(pdata->col_gpios[i]);
+
+	return err;
+}
+
+static int __devinit matrix_keypad_probe(struct platform_device *pdev)
+{
+	const struct matrix_keypad_platform_data *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct matrix_keypad *keypad;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	int err;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	row_shift = get_count_order(pdata->num_col_gpios);
+	if (pdata->grounding)
+		row_shift++;
+
+	keypad = kzalloc(sizeof(struct matrix_keypad), GFP_KERNEL);
+	keycodes = kzalloc((pdata->num_row_gpios << (row_shift)) *
+				sizeof(*keycodes),
+			   GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !keycodes || !input_dev) {
+		err = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	keypad->input_dev = input_dev;
+	keypad->pdata = pdata;
+	keypad->keycodes = keycodes;
+		
+	keypad->row_shift = row_shift;	
+	keypad->stopped = true;
+	INIT_DELAYED_WORK(&keypad->work, matrix_keypad_scan);
+	spin_lock_init(&keypad->lock);
+
+	input_dev->name		= pdev->name;
+	input_dev->id.bustype	= BUS_HOST;
+	input_dev->dev.parent	= &pdev->dev;
+	input_dev->evbit[0]	= BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
+	input_dev->open		= matrix_keypad_start;
+	input_dev->close	= matrix_keypad_stop;
+
+	input_dev->keycode	= keycodes;
+	input_dev->keycodesize	= sizeof(*keycodes);
+	input_dev->keycodemax	= pdata->num_row_gpios << (row_shift);
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+				   input_dev->keycode, input_dev->keybit);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+	input_set_drvdata(input_dev, keypad);
+
+	err = init_matrix_gpio(pdev, keypad);
+	if (err)
+		goto err_free_mem;
+
+	err = input_register_device(keypad->input_dev);
+	if (err)
+		goto err_free_mem;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+
+	return 0;
+
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keycodes);
+	kfree(keypad);
+	return err;
+}
+
+static int __devexit matrix_keypad_remove(struct platform_device *pdev)
+{
+	struct matrix_keypad *keypad = platform_get_drvdata(pdev);
+	const struct matrix_keypad_platform_data *pdata = keypad->pdata;
+	int i;
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	for (i = 0; i < pdata->num_row_gpios; i++) {
+		free_irq(gpio_to_irq(pdata->row_gpios[i]), keypad);
+		gpio_free(pdata->row_gpios[i]);
+	}
+
+	for (i = 0; i < pdata->num_col_gpios; i++)
+		gpio_free(pdata->col_gpios[i]);
+
+	input_unregister_device(keypad->input_dev);
+	platform_set_drvdata(pdev, NULL);
+	kfree(keypad->keycodes);
+	kfree(keypad);
+
+	return 0;
+}
+
+static struct platform_driver matrix_keypad_driver = {
+	.probe		= matrix_keypad_probe,
+	.remove		= __devexit_p(matrix_keypad_remove),
+	.suspend	= matrix_keypad_suspend,
+	.resume		= matrix_keypad_resume,
+	.driver		= {
+		.name	= "matrix-keypad",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init matrix_keypad_init(void)
+{
+	return platform_driver_register(&matrix_keypad_driver);
+}
+
+static void __exit matrix_keypad_exit(void)
+{
+	platform_driver_unregister(&matrix_keypad_driver);
+}
+
+module_init(matrix_keypad_init);
+module_exit(matrix_keypad_exit);
+
+MODULE_AUTHOR("Anyka <xxx@anyka.oa>");
+MODULE_DESCRIPTION("GPIO Driven Matrix Keypad Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:matrix-keypad");
+
diff --git a/drivers/input/keyboard/atkbd.c b/drivers/input/keyboard/atkbd.c
index 28e6110d1ff..f97788506ce 100644
--- a/drivers/input/keyboard/atkbd.c
+++ b/drivers/input/keyboard/atkbd.c
@@ -63,6 +63,10 @@ static int atkbd_extra;
 module_param_named(extra, atkbd_extra, bool, 0);
 MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and similar keyboards");
 
+#if defined CONFIG_BOARD_AK8802EBOOK && defined CONFIG_MOUSE_AK88_TRKBALL
+extern struct input_dev *ak88_trkball_input_dev;
+#endif
+
 /*
  * Scancode to keycode tables. These are just the default setting, and
  * are loadable via a userland utility.
@@ -211,6 +215,10 @@ struct atkbd {
 	unsigned char softrepeat;
 	unsigned char softraw;
 	unsigned char scroll;
+#if defined CONFIG_BOARD_AK8802EBOOK && defined CONFIG_MOUSE_AK88_TRKBALL
+	unsigned char left_btn;
+	unsigned char left_btn_pressed;
+#endif
 	unsigned char enabled;
 
 	/* Accessed only from interrupt */
@@ -510,7 +518,38 @@ static irqreturn_t atkbd_interrupt(struct serio *serio, unsigned char data,
 		input_report_rel(dev, REL_WHEEL, scroll);
 		input_report_rel(dev, REL_HWHEEL, hscroll);
 		input_sync(dev);
+#if defined CONFIG_BOARD_AK8802EBOOK && defined CONFIG_MOUSE_AK88_TRKBALL
+	} else if (atkbd->left_btn) {
+		switch (click) {
+		case 1:
+			if (atkbd->left_btn_pressed == 0) {
+				if (ak88_trkball_input_dev) {
+					input_report_key(ak88_trkball_input_dev,
+							 BTN_LEFT, click);
+					input_sync(ak88_trkball_input_dev);
+				} else {
+					input_report_key(dev, BTN_LEFT, click);
+					input_sync(dev);
+				}
+				atkbd->left_btn_pressed = 1;
+			}
+			break;
+		case 0:
+			if (ak88_trkball_input_dev) {
+				input_report_key(ak88_trkball_input_dev,
+						 BTN_LEFT, click);
+				input_sync(ak88_trkball_input_dev);
+			} else {
+				input_report_key(dev, BTN_LEFT, click);
+				input_sync(dev);
+			}
+			atkbd->left_btn_pressed = 0;
+			break;
+		}
+	}
+#else
 	}
+#endif
 
 	atkbd->release = 0;
 out:
@@ -1056,6 +1095,12 @@ static void atkbd_set_device_attrs(struct atkbd *atkbd)
 		__set_bit(BTN_MIDDLE, input_dev->keybit);
 	}
 
+#if defined CONFIG_BOARD_AK8802EBOOK && defined CONFIG_MOUSE_AK88_TRKBALL
+	if (atkbd->left_btn) {
+		__set_bit(BTN_LEFT, input_dev->keybit);
+	}
+#endif
+
 	input_dev->keycode = atkbd->keycode;
 	input_dev->keycodesize = sizeof(unsigned short);
 	input_dev->keycodemax = ARRAY_SIZE(atkbd_set2_keycode);
@@ -1102,6 +1147,11 @@ static int atkbd_connect(struct serio *serio, struct serio_driver *drv)
 	atkbd->softrepeat = atkbd_softrepeat;
 	atkbd->scroll = atkbd_scroll;
 
+#if defined CONFIG_BOARD_AK8802EBOOK && defined CONFIG_MOUSE_AK88_TRKBALL
+	atkbd->left_btn = 1;
+	atkbd->left_btn_pressed = 0;
+#endif
+
 	if (atkbd->softrepeat)
 		atkbd->softraw = 1;
 
diff --git a/drivers/input/keyreset.c b/drivers/input/keyreset.c
new file mode 100644
index 00000000000..4905692a54f
--- /dev/null
+++ b/drivers/input/keyreset.c
@@ -0,0 +1,229 @@
+/* drivers/input/keyreset.c
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/input.h>
+#include <linux/keyreset.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/sched.h>
+#include <linux/syscalls.h>
+
+
+struct keyreset_state {
+	struct input_handler input_handler;
+	unsigned long keybit[BITS_TO_LONGS(KEY_CNT)];
+	unsigned long upbit[BITS_TO_LONGS(KEY_CNT)];
+	unsigned long key[BITS_TO_LONGS(KEY_CNT)];
+	spinlock_t lock;
+	int key_down_target;
+	int key_down;
+	int key_up;
+	int restart_disabled;
+};
+
+int restart_requested;
+static void deferred_restart(struct work_struct *dummy)
+{
+	restart_requested = 2;
+	sys_sync();
+	restart_requested = 3;
+	kernel_restart(NULL);
+}
+static DECLARE_WORK(restart_work, deferred_restart);
+
+static void keyreset_event(struct input_handle *handle, unsigned int type,
+			   unsigned int code, int value)
+{
+	unsigned long flags;
+	struct keyreset_state *state = handle->private;
+
+	if (type != EV_KEY)
+		return;
+
+	if (code >= KEY_MAX)
+		return;
+
+	if (!test_bit(code, state->keybit))
+		return;
+
+	spin_lock_irqsave(&state->lock, flags);
+	if (!test_bit(code, state->key) == !value)
+		goto done;
+	__change_bit(code, state->key);
+	if (test_bit(code, state->upbit)) {
+		if (value) {
+			state->restart_disabled = 1;
+			state->key_up++;
+		} else
+			state->key_up--;
+	} else {
+		if (value)
+			state->key_down++;
+		else
+			state->key_down--;
+	}
+	if (state->key_down == 0 && state->key_up == 0)
+		state->restart_disabled = 0;
+
+	pr_debug("reset key changed %d %d new state %d-%d-%d\n", code, value,
+		 state->key_down, state->key_up, state->restart_disabled);
+
+	if (value && !state->restart_disabled &&
+	    state->key_down == state->key_down_target) {
+		state->restart_disabled = 1;
+		if (restart_requested)
+			panic("keyboard reset failed, %d", restart_requested);
+		pr_info("keyboard reset\n");
+		schedule_work(&restart_work);
+		restart_requested = 1;
+	}
+done:
+	spin_unlock_irqrestore(&state->lock, flags);
+}
+
+static int keyreset_connect(struct input_handler *handler,
+					  struct input_dev *dev,
+					  const struct input_device_id *id)
+{
+	int i;
+	int ret;
+	struct input_handle *handle;
+	struct keyreset_state *state =
+		container_of(handler, struct keyreset_state, input_handler);
+
+	for (i = 0; i < KEY_MAX; i++) {
+		if (test_bit(i, state->keybit) && test_bit(i, dev->keybit))
+			break;
+	}
+	if (i == KEY_MAX)
+		return -ENODEV;
+
+	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+	if (!handle)
+		return -ENOMEM;
+
+	handle->dev = dev;
+	handle->handler = handler;
+	handle->name = "keyreset";
+	handle->private = state;
+
+	ret = input_register_handle(handle);
+	if (ret)
+		goto err_input_register_handle;
+
+	ret = input_open_device(handle);
+	if (ret)
+		goto err_input_open_device;
+
+	pr_info("using input dev %s for key reset\n", dev->name);
+
+	return 0;
+
+err_input_open_device:
+	input_unregister_handle(handle);
+err_input_register_handle:
+	kfree(handle);
+	return ret;
+}
+
+static void keyreset_disconnect(struct input_handle *handle)
+{
+	input_close_device(handle);
+	input_unregister_handle(handle);
+	kfree(handle);
+}
+
+static const struct input_device_id keyreset_ids[] = {
+	{
+		.flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+		.evbit = { BIT_MASK(EV_KEY) },
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(input, keyreset_ids);
+
+static int keyreset_probe(struct platform_device *pdev)
+{
+	int ret;
+	int key, *keyp;
+	struct keyreset_state *state;
+	struct keyreset_platform_data *pdata = pdev->dev.platform_data;
+
+	if (!pdata)
+		return -EINVAL;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	spin_lock_init(&state->lock);
+	keyp = pdata->keys_down;
+	while ((key = *keyp++)) {
+		if (key >= KEY_MAX)
+			continue;
+		state->key_down_target++;
+		__set_bit(key, state->keybit);
+	}
+	if (pdata->keys_up) {
+		keyp = pdata->keys_up;
+		while ((key = *keyp++)) {
+			if (key >= KEY_MAX)
+				continue;
+			__set_bit(key, state->keybit);
+			__set_bit(key, state->upbit);
+		}
+	}
+	state->input_handler.event = keyreset_event;
+	state->input_handler.connect = keyreset_connect;
+	state->input_handler.disconnect = keyreset_disconnect;
+	state->input_handler.name = KEYRESET_NAME;
+	state->input_handler.id_table = keyreset_ids;
+	ret = input_register_handler(&state->input_handler);
+	if (ret) {
+		kfree(state);
+		return ret;
+	}
+	platform_set_drvdata(pdev, state);
+	return 0;
+}
+
+int keyreset_remove(struct platform_device *pdev)
+{
+	struct keyreset_state *state = platform_get_drvdata(pdev);
+	input_unregister_handler(&state->input_handler);
+	kfree(state);
+	return 0;
+}
+
+
+struct platform_driver keyreset_driver = {
+	.driver.name = KEYRESET_NAME,
+	.probe = keyreset_probe,
+	.remove = keyreset_remove,
+};
+
+static int __init keyreset_init(void)
+{
+	return platform_driver_register(&keyreset_driver);
+}
+
+static void __exit keyreset_exit(void)
+{
+	return platform_driver_unregister(&keyreset_driver);
+}
+
+module_init(keyreset_init);
+module_exit(keyreset_exit);
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index a9bb2544b2d..0b0b6182cad 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -132,6 +132,17 @@ config INPUT_ATI_REMOTE2
 	  To compile this driver as a module, choose M here: the module will be
 	  called ati_remote2.
 
+config INPUT_KEYCHORD
+	tristate "Key chord input driver support"
+	help
+	  Say Y here if you want to enable the key chord driver
+	  accessible at /dev/keychord.  This driver can be used
+	  for receiving notifications when client specified key
+	  combinations are pressed.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called keychord.
+
 config INPUT_KEYSPAN_REMOTE
 	tristate "Keyspan DMR USB remote control (EXPERIMENTAL)"
 	depends on EXPERIMENTAL
@@ -240,6 +251,11 @@ config INPUT_WINBOND_CIR
 	  To compile this driver as a module, choose M here: the module will be
 	  called winbond_cir.
 
+config INPUT_GPIO
+	tristate "GPIO driver support"
+	help
+	  Say Y here if you want to support gpio based keys, wheels etc...
+
 config HP_SDC_RTC
 	tristate "HP SDC Real Time Clock"
 	depends on (GSC || HP300) && SERIO
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index a8b84854fb7..42a5a5a90e7 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -12,8 +12,10 @@ obj-$(CONFIG_INPUT_BFIN_ROTARY)		+= bfin_rotary.o
 obj-$(CONFIG_INPUT_CM109)		+= cm109.o
 obj-$(CONFIG_INPUT_COBALT_BTNS)		+= cobalt_btns.o
 obj-$(CONFIG_INPUT_DM355EVM)		+= dm355evm_keys.o
+obj-$(CONFIG_INPUT_GPIO)		+= gpio_event.o gpio_matrix.o gpio_input.o gpio_output.o gpio_axis.o
 obj-$(CONFIG_HP_SDC_RTC)		+= hp_sdc_rtc.o
 obj-$(CONFIG_INPUT_IXP4XX_BEEPER)	+= ixp4xx-beeper.o
+obj-$(CONFIG_INPUT_KEYCHORD)		+= keychord.o
 obj-$(CONFIG_INPUT_KEYSPAN_REMOTE)	+= keyspan_remote.o
 obj-$(CONFIG_INPUT_M68K_BEEP)		+= m68kspkr.o
 obj-$(CONFIG_INPUT_PCAP)		+= pcap_keys.o
diff --git a/drivers/input/misc/gpio_axis.c b/drivers/input/misc/gpio_axis.c
new file mode 100644
index 00000000000..30b9f5681ce
--- /dev/null
+++ b/drivers/input/misc/gpio_axis.c
@@ -0,0 +1,191 @@
+/* drivers/input/misc/gpio_axis.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/interrupt.h>
+
+struct gpio_axis_state {
+	struct gpio_event_input_devs *input_devs;
+	struct gpio_event_axis_info *info;
+	uint32_t pos;
+};
+
+uint16_t gpio_axis_4bit_gray_map_table[] = {
+	[0x0] = 0x0, [0x1] = 0x1, /* 0000 0001 */
+	[0x3] = 0x2, [0x2] = 0x3, /* 0011 0010 */
+	[0x6] = 0x4, [0x7] = 0x5, /* 0110 0111 */
+	[0x5] = 0x6, [0x4] = 0x7, /* 0101 0100 */
+	[0xc] = 0x8, [0xd] = 0x9, /* 1100 1101 */
+	[0xf] = 0xa, [0xe] = 0xb, /* 1111 1110 */
+	[0xa] = 0xc, [0xb] = 0xd, /* 1010 1011 */
+	[0x9] = 0xe, [0x8] = 0xf, /* 1001 1000 */
+};
+uint16_t gpio_axis_4bit_gray_map(struct gpio_event_axis_info *info, uint16_t in)
+{
+	return gpio_axis_4bit_gray_map_table[in];
+}
+
+uint16_t gpio_axis_5bit_singletrack_map_table[] = {
+	[0x10] = 0x00, [0x14] = 0x01, [0x1c] = 0x02, /*     10000 10100 11100 */
+	[0x1e] = 0x03, [0x1a] = 0x04, [0x18] = 0x05, /*     11110 11010 11000 */
+	[0x08] = 0x06, [0x0a] = 0x07, [0x0e] = 0x08, /*    01000 01010 01110  */
+	[0x0f] = 0x09, [0x0d] = 0x0a, [0x0c] = 0x0b, /*    01111 01101 01100  */
+	[0x04] = 0x0c, [0x05] = 0x0d, [0x07] = 0x0e, /*   00100 00101 00111   */
+	[0x17] = 0x0f, [0x16] = 0x10, [0x06] = 0x11, /*   10111 10110 00110   */
+	[0x02] = 0x12, [0x12] = 0x13, [0x13] = 0x14, /*  00010 10010 10011    */
+	[0x1b] = 0x15, [0x0b] = 0x16, [0x03] = 0x17, /*  11011 01011 00011    */
+	[0x01] = 0x18, [0x09] = 0x19, [0x19] = 0x1a, /* 00001 01001 11001     */
+	[0x1d] = 0x1b, [0x15] = 0x1c, [0x11] = 0x1d, /* 11101 10101 10001     */
+};
+uint16_t gpio_axis_5bit_singletrack_map(
+	struct gpio_event_axis_info *info, uint16_t in)
+{
+	return gpio_axis_5bit_singletrack_map_table[in];
+}
+
+static void gpio_event_update_axis(struct gpio_axis_state *as, int report)
+{
+	struct gpio_event_axis_info *ai = as->info;
+	int i;
+	int change;
+	uint16_t state = 0;
+	uint16_t pos;
+	uint16_t old_pos = as->pos;
+	for (i = ai->count - 1; i >= 0; i--)
+		state = (state << 1) | gpio_get_value(ai->gpio[i]);
+	pos = ai->map(ai, state);
+	if (ai->flags & GPIOEAF_PRINT_RAW)
+		pr_info("axis %d-%d raw %x, pos %d -> %d\n",
+			ai->type, ai->code, state, old_pos, pos);
+	if (report && pos != old_pos) {
+		if (ai->type == EV_REL) {
+			change = (ai->decoded_size + pos - old_pos) %
+				  ai->decoded_size;
+			if (change > ai->decoded_size / 2)
+				change -= ai->decoded_size;
+			if (change == ai->decoded_size / 2) {
+				if (ai->flags & GPIOEAF_PRINT_EVENT)
+					pr_info("axis %d-%d unknown direction, "
+						"pos %d -> %d\n", ai->type,
+						ai->code, old_pos, pos);
+				change = 0; /* no closest direction */
+			}
+			if (ai->flags & GPIOEAF_PRINT_EVENT)
+				pr_info("axis %d-%d change %d\n",
+					ai->type, ai->code, change);
+			input_report_rel(as->input_devs->dev[ai->dev],
+						ai->code, change);
+		} else {
+			if (ai->flags & GPIOEAF_PRINT_EVENT)
+				pr_info("axis %d-%d now %d\n",
+					ai->type, ai->code, pos);
+			input_event(as->input_devs->dev[ai->dev],
+					ai->type, ai->code, pos);
+		}
+		input_sync(as->input_devs->dev[ai->dev]);
+	}
+	as->pos = pos;
+}
+
+static irqreturn_t gpio_axis_irq_handler(int irq, void *dev_id)
+{
+	struct gpio_axis_state *as = dev_id;
+	gpio_event_update_axis(as, 1);
+	return IRQ_HANDLED;
+}
+
+int gpio_event_axis_func(struct gpio_event_input_devs *input_devs,
+			 struct gpio_event_info *info, void **data, int func)
+{
+	int ret;
+	int i;
+	int irq;
+	struct gpio_event_axis_info *ai;
+	struct gpio_axis_state *as;
+
+	ai = container_of(info, struct gpio_event_axis_info, info);
+	if (func == GPIO_EVENT_FUNC_SUSPEND) {
+		for (i = 0; i < ai->count; i++)
+			disable_irq(gpio_to_irq(ai->gpio[i]));
+		return 0;
+	}
+	if (func == GPIO_EVENT_FUNC_RESUME) {
+		for (i = 0; i < ai->count; i++)
+			enable_irq(gpio_to_irq(ai->gpio[i]));
+		return 0;
+	}
+
+	if (func == GPIO_EVENT_FUNC_INIT) {
+		*data = as = kmalloc(sizeof(*as), GFP_KERNEL);
+		if (as == NULL) {
+			ret = -ENOMEM;
+			goto err_alloc_axis_state_failed;
+		}
+		as->input_devs = input_devs;
+		as->info = ai;
+		if (ai->dev >= input_devs->count) {
+			pr_err("gpio_event_axis: bad device index %d >= %d "
+				"for %d:%d\n", ai->dev, input_devs->count,
+				ai->type, ai->code);
+			ret = -EINVAL;
+			goto err_bad_device_index;
+		}
+
+		input_set_capability(input_devs->dev[ai->dev],
+				     ai->type, ai->code);
+		if (ai->type == EV_ABS) {
+			input_set_abs_params(input_devs->dev[ai->dev], ai->code,
+					     0, ai->decoded_size - 1, 0, 0);
+		}
+		for (i = 0; i < ai->count; i++) {
+			ret = gpio_request(ai->gpio[i], "gpio_event_axis");
+			if (ret < 0)
+				goto err_request_gpio_failed;
+			ret = gpio_direction_input(ai->gpio[i]);
+			if (ret < 0)
+				goto err_gpio_direction_input_failed;
+			ret = irq = gpio_to_irq(ai->gpio[i]);
+			if (ret < 0)
+				goto err_get_irq_num_failed;
+			ret = request_irq(irq, gpio_axis_irq_handler,
+					  IRQF_TRIGGER_RISING |
+					  IRQF_TRIGGER_FALLING,
+					  "gpio_event_axis", as);
+			if (ret < 0)
+				goto err_request_irq_failed;
+		}
+		gpio_event_update_axis(as, 0);
+		return 0;
+	}
+
+	ret = 0;
+	as = *data;
+	for (i = ai->count - 1; i >= 0; i--) {
+		free_irq(gpio_to_irq(ai->gpio[i]), as);
+err_request_irq_failed:
+err_get_irq_num_failed:
+err_gpio_direction_input_failed:
+		gpio_free(ai->gpio[i]);
+err_request_gpio_failed:
+		;
+	}
+err_bad_device_index:
+	kfree(as);
+	*data = NULL;
+err_alloc_axis_state_failed:
+	return ret;
+}
diff --git a/drivers/input/misc/gpio_event.c b/drivers/input/misc/gpio_event.c
new file mode 100644
index 00000000000..139b3600ed7
--- /dev/null
+++ b/drivers/input/misc/gpio_event.c
@@ -0,0 +1,259 @@
+/* drivers/input/misc/gpio_event.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/earlysuspend.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/gpio_event.h>
+#include <linux/hrtimer.h>
+#include <linux/platform_device.h>
+
+struct gpio_event {
+	struct gpio_event_input_devs *input_devs;
+	const struct gpio_event_platform_data *info;
+	struct early_suspend early_suspend;
+	void *state[0];
+};
+
+static int gpio_input_event(
+	struct input_dev *dev, unsigned int type, unsigned int code, int value)
+{
+	int i;
+	int devnr;
+	int ret = 0;
+	int tmp_ret;
+	struct gpio_event_info **ii;
+	struct gpio_event *ip = input_get_drvdata(dev);
+
+	for (devnr = 0; devnr < ip->input_devs->count; devnr++)
+		if (ip->input_devs->dev[devnr] == dev)
+			break;
+	if (devnr == ip->input_devs->count) {
+		pr_err("gpio_input_event: unknown device %p\n", dev);
+		return -EIO;
+	}
+
+	for (i = 0, ii = ip->info->info; i < ip->info->info_count; i++, ii++) {
+		if ((*ii)->event) {
+			tmp_ret = (*ii)->event(ip->input_devs, *ii,
+						&ip->state[i],
+						devnr, type, code, value);
+			if (tmp_ret)
+				ret = tmp_ret;
+		}
+	}
+	return ret;
+}
+
+static int gpio_event_call_all_func(struct gpio_event *ip, int func)
+{
+	int i;
+	int ret;
+	struct gpio_event_info **ii;
+
+	if (func == GPIO_EVENT_FUNC_INIT || func == GPIO_EVENT_FUNC_RESUME) {
+		ii = ip->info->info;
+		for (i = 0; i < ip->info->info_count; i++, ii++) {
+			if ((*ii)->func == NULL) {
+				ret = -ENODEV;
+				pr_err("gpio_event_probe: Incomplete pdata, "
+					"no function\n");
+				goto err_no_func;
+			}
+			if (func == GPIO_EVENT_FUNC_RESUME && (*ii)->no_suspend)
+				continue;
+			ret = (*ii)->func(ip->input_devs, *ii, &ip->state[i],
+					  func);
+			if (ret) {
+				pr_err("gpio_event_probe: function failed\n");
+				goto err_func_failed;
+			}
+		}
+		return 0;
+	}
+
+	ret = 0;
+	i = ip->info->info_count;
+	ii = ip->info->info + i;
+	while (i > 0) {
+		i--;
+		ii--;
+		if ((func & ~1) == GPIO_EVENT_FUNC_SUSPEND && (*ii)->no_suspend)
+			continue;
+		(*ii)->func(ip->input_devs, *ii, &ip->state[i], func & ~1);
+err_func_failed:
+err_no_func:
+		;
+	}
+	return ret;
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void gpio_event_suspend(struct early_suspend *h)
+{
+	struct gpio_event *ip;
+	ip = container_of(h, struct gpio_event, early_suspend);
+	gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_SUSPEND);
+	ip->info->power(ip->info, 0);
+}
+
+void gpio_event_resume(struct early_suspend *h)
+{
+	struct gpio_event *ip;
+	ip = container_of(h, struct gpio_event, early_suspend);
+	ip->info->power(ip->info, 1);
+	gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_RESUME);
+}
+#endif
+
+static int __init gpio_event_probe(struct platform_device *pdev)
+{
+	int err;
+	struct gpio_event *ip;
+	struct gpio_event_platform_data *event_info;
+	int dev_count = 1;
+	int i;
+	int registered = 0;
+
+	event_info = pdev->dev.platform_data;
+	if (event_info == NULL) {
+		pr_err("gpio_event_probe: No pdata\n");
+		return -ENODEV;
+	}
+	if ((!event_info->name && !event_info->names[0]) ||
+	    !event_info->info || !event_info->info_count) {
+		pr_err("gpio_event_probe: Incomplete pdata\n");
+		return -ENODEV;
+	}
+	if (!event_info->name)
+		while (event_info->names[dev_count])
+			dev_count++;
+	ip = kzalloc(sizeof(*ip) +
+		     sizeof(ip->state[0]) * event_info->info_count +
+		     sizeof(*ip->input_devs) +
+		     sizeof(ip->input_devs->dev[0]) * dev_count, GFP_KERNEL);
+	if (ip == NULL) {
+		err = -ENOMEM;
+		pr_err("gpio_event_probe: Failed to allocate private data\n");
+		goto err_kp_alloc_failed;
+	}
+	ip->input_devs = (void*)&ip->state[event_info->info_count];
+	platform_set_drvdata(pdev, ip);
+
+	for (i = 0; i < dev_count; i++) {
+		struct input_dev *input_dev = input_allocate_device();
+		if (input_dev == NULL) {
+			err = -ENOMEM;
+			pr_err("gpio_event_probe: "
+				"Failed to allocate input device\n");
+			goto err_input_dev_alloc_failed;
+		}
+		input_set_drvdata(input_dev, ip);
+		input_dev->name = event_info->name ?
+					event_info->name : event_info->names[i];
+		input_dev->event = gpio_input_event;
+		ip->input_devs->dev[i] = input_dev;
+	}
+	ip->input_devs->count = dev_count;
+	ip->info = event_info;
+	if (event_info->power) {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		ip->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
+		ip->early_suspend.suspend = gpio_event_suspend;
+		ip->early_suspend.resume = gpio_event_resume;
+		register_early_suspend(&ip->early_suspend);
+#endif
+		ip->info->power(ip->info, 1);
+	}
+
+	err = gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_INIT);
+	if (err)
+		goto err_call_all_func_failed;
+
+	for (i = 0; i < dev_count; i++) {
+		err = input_register_device(ip->input_devs->dev[i]);
+		if (err) {
+			pr_err("gpio_event_probe: Unable to register %s "
+				"input device\n", ip->input_devs->dev[i]->name);
+			goto err_input_register_device_failed;
+		}
+		registered++;
+	}
+
+	return 0;
+
+err_input_register_device_failed:
+	gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
+err_call_all_func_failed:
+	if (event_info->power) {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		unregister_early_suspend(&ip->early_suspend);
+#endif
+		ip->info->power(ip->info, 0);
+	}
+	for (i = 0; i < registered; i++)
+		input_unregister_device(ip->input_devs->dev[i]);
+	for (i = dev_count - 1; i >= registered; i--) {
+		input_free_device(ip->input_devs->dev[i]);
+err_input_dev_alloc_failed:
+		;
+	}
+	kfree(ip);
+err_kp_alloc_failed:
+	return err;
+}
+
+static int gpio_event_remove(struct platform_device *pdev)
+{
+	struct gpio_event *ip = platform_get_drvdata(pdev);
+	int i;
+
+	gpio_event_call_all_func(ip, GPIO_EVENT_FUNC_UNINIT);
+	if (ip->info->power) {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+		unregister_early_suspend(&ip->early_suspend);
+#endif
+		ip->info->power(ip->info, 0);
+	}
+	for (i = 0; i < ip->input_devs->count; i++)
+		input_unregister_device(ip->input_devs->dev[i]);
+	kfree(ip);
+	return 0;
+}
+
+static struct platform_driver gpio_event_driver = {
+	.probe		= gpio_event_probe,
+	.remove		= gpio_event_remove,
+	.driver		= {
+		.name	= GPIO_EVENT_DEV_NAME,
+	},
+};
+
+static int __devinit gpio_event_init(void)
+{
+	return platform_driver_register(&gpio_event_driver);
+}
+
+static void __exit gpio_event_exit(void)
+{
+	platform_driver_unregister(&gpio_event_driver);
+}
+
+module_init(gpio_event_init);
+module_exit(gpio_event_exit);
+
+MODULE_DESCRIPTION("GPIO Event Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/input/misc/gpio_input.c b/drivers/input/misc/gpio_input.c
new file mode 100644
index 00000000000..7e66f8cbd75
--- /dev/null
+++ b/drivers/input/misc/gpio_input.c
@@ -0,0 +1,352 @@
+/* drivers/input/misc/gpio_input.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/hrtimer.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/wakelock.h>
+
+enum {
+	DEBOUNCE_UNSTABLE     = BIT(0),	/* Got irq, while debouncing */
+	DEBOUNCE_PRESSED      = BIT(1),
+	DEBOUNCE_NOTPRESSED   = BIT(2),
+	DEBOUNCE_WAIT_IRQ     = BIT(3),	/* Stable irq state */
+	DEBOUNCE_POLL         = BIT(4),	/* Stable polling state */
+
+	DEBOUNCE_UNKNOWN =
+		DEBOUNCE_PRESSED | DEBOUNCE_NOTPRESSED,
+};
+
+struct gpio_key_state {
+	struct gpio_input_state *ds;
+	uint8_t debounce;
+};
+
+struct gpio_input_state {
+	struct gpio_event_input_devs *input_devs;
+	const struct gpio_event_input_info *info;
+	struct hrtimer timer;
+	int use_irq;
+	int debounce_count;
+	spinlock_t irq_lock;
+	struct wake_lock wake_lock;
+	struct gpio_key_state key_state[0];
+};
+
+static enum hrtimer_restart gpio_event_input_timer_func(struct hrtimer *timer)
+{
+	int i;
+	int pressed;
+	struct gpio_input_state *ds =
+		container_of(timer, struct gpio_input_state, timer);
+	unsigned gpio_flags = ds->info->flags;
+	unsigned npolarity;
+	int nkeys = ds->info->keymap_size;
+	const struct gpio_event_direct_entry *key_entry;
+	struct gpio_key_state *key_state;
+	unsigned long irqflags;
+	uint8_t debounce;
+
+#if 0
+	key_entry = kp->keys_info->keymap;
+	key_state = kp->key_state;
+	for (i = 0; i < nkeys; i++, key_entry++, key_state++)
+		pr_info("gpio_read_detect_status %d %d\n", key_entry->gpio,
+			gpio_read_detect_status(key_entry->gpio));
+#endif
+	key_entry = ds->info->keymap;
+	key_state = ds->key_state;
+	spin_lock_irqsave(&ds->irq_lock, irqflags);
+	for (i = 0; i < nkeys; i++, key_entry++, key_state++) {
+		debounce = key_state->debounce;
+		if (debounce & DEBOUNCE_WAIT_IRQ)
+			continue;
+		if (key_state->debounce & DEBOUNCE_UNSTABLE) {
+			debounce = key_state->debounce = DEBOUNCE_UNKNOWN;
+			enable_irq(gpio_to_irq(key_entry->gpio));
+			pr_info("gpio_keys_scan_keys: key %x-%x, %d "
+				"(%d) continue debounce\n",
+				ds->info->type, key_entry->code,
+				i, key_entry->gpio);
+		}
+		npolarity = !(gpio_flags & GPIOEDF_ACTIVE_HIGH);
+		pressed = gpio_get_value(key_entry->gpio) ^ npolarity;
+		if (debounce & DEBOUNCE_POLL) {
+			if (pressed == !(debounce & DEBOUNCE_PRESSED)) {
+				ds->debounce_count++;
+				key_state->debounce = DEBOUNCE_UNKNOWN;
+				if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
+					pr_info("gpio_keys_scan_keys: key %x-"
+						"%x, %d (%d) start debounce\n",
+						ds->info->type, key_entry->code,
+						i, key_entry->gpio);
+			}
+			continue;
+		}
+		if (pressed && (debounce & DEBOUNCE_NOTPRESSED)) {
+			if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
+				pr_info("gpio_keys_scan_keys: key %x-%x, %d "
+					"(%d) debounce pressed 1\n",
+					ds->info->type, key_entry->code,
+					i, key_entry->gpio);
+			key_state->debounce = DEBOUNCE_PRESSED;
+			continue;
+		}
+		if (!pressed && (debounce & DEBOUNCE_PRESSED)) {
+			if (gpio_flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
+				pr_info("gpio_keys_scan_keys: key %x-%x, %d "
+					"(%d) debounce pressed 0\n",
+					ds->info->type, key_entry->code,
+					i, key_entry->gpio);
+			key_state->debounce = DEBOUNCE_NOTPRESSED;
+			continue;
+		}
+		/* key is stable */
+		ds->debounce_count--;
+		if (ds->use_irq)
+			key_state->debounce |= DEBOUNCE_WAIT_IRQ;
+		else
+			key_state->debounce |= DEBOUNCE_POLL;
+		if (gpio_flags & GPIOEDF_PRINT_KEYS)
+			pr_info("gpio_keys_scan_keys: key %x-%x, %d (%d) "
+				"changed to %d\n", ds->info->type,
+				key_entry->code, i, key_entry->gpio, pressed);
+		input_event(ds->input_devs->dev[key_entry->dev], ds->info->type,
+			    key_entry->code, pressed);
+	}
+
+#if 0
+	key_entry = kp->keys_info->keymap;
+	key_state = kp->key_state;
+	for (i = 0; i < nkeys; i++, key_entry++, key_state++) {
+		pr_info("gpio_read_detect_status %d %d\n", key_entry->gpio,
+			gpio_read_detect_status(key_entry->gpio));
+	}
+#endif
+
+	if (ds->debounce_count)
+		hrtimer_start(timer, ds->info->debounce_time, HRTIMER_MODE_REL);
+	else if (!ds->use_irq)
+		hrtimer_start(timer, ds->info->poll_time, HRTIMER_MODE_REL);
+	else
+		wake_unlock(&ds->wake_lock);
+
+	spin_unlock_irqrestore(&ds->irq_lock, irqflags);
+
+	return HRTIMER_NORESTART;
+}
+
+static irqreturn_t gpio_event_input_irq_handler(int irq, void *dev_id)
+{
+	struct gpio_key_state *ks = dev_id;
+	struct gpio_input_state *ds = ks->ds;
+	int keymap_index = ks - ds->key_state;
+	const struct gpio_event_direct_entry *key_entry;
+	unsigned long irqflags;
+	int pressed;
+
+	if (!ds->use_irq)
+		return IRQ_HANDLED;
+
+	key_entry = &ds->info->keymap[keymap_index];
+
+	if (ds->info->debounce_time.tv64) {
+		spin_lock_irqsave(&ds->irq_lock, irqflags);
+		if (ks->debounce & DEBOUNCE_WAIT_IRQ) {
+			ks->debounce = DEBOUNCE_UNKNOWN;
+			if (ds->debounce_count++ == 0) {
+				wake_lock(&ds->wake_lock);
+				hrtimer_start(
+					&ds->timer, ds->info->debounce_time,
+					HRTIMER_MODE_REL);
+			}
+			if (ds->info->flags & GPIOEDF_PRINT_KEY_DEBOUNCE)
+				pr_info("gpio_event_input_irq_handler: "
+					"key %x-%x, %d (%d) start debounce\n",
+					ds->info->type, key_entry->code,
+					keymap_index, key_entry->gpio);
+		} else {
+			disable_irq_nosync(irq);
+			ks->debounce = DEBOUNCE_UNSTABLE;
+		}
+		spin_unlock_irqrestore(&ds->irq_lock, irqflags);
+	} else {
+		pressed = gpio_get_value(key_entry->gpio) ^
+			!(ds->info->flags & GPIOEDF_ACTIVE_HIGH);
+		if (ds->info->flags & GPIOEDF_PRINT_KEYS)
+			pr_info("gpio_event_input_irq_handler: key %x-%x, %d "
+				"(%d) changed to %d\n",
+				ds->info->type, key_entry->code, keymap_index,
+				key_entry->gpio, pressed);
+		input_event(ds->input_devs->dev[key_entry->dev], ds->info->type,
+			    key_entry->code, pressed);
+	}
+	return IRQ_HANDLED;
+}
+
+static int gpio_event_input_request_irqs(struct gpio_input_state *ds)
+{
+	int i;
+	int err;
+	unsigned int irq;
+	unsigned long req_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+
+	for (i = 0; i < ds->info->keymap_size; i++) {
+		err = irq = gpio_to_irq(ds->info->keymap[i].gpio);
+		if (err < 0)
+			goto err_gpio_get_irq_num_failed;
+		err = request_irq(irq, gpio_event_input_irq_handler,
+				  req_flags, "gpio_keys", &ds->key_state[i]);
+		if (err) {
+			pr_err("gpio_event_input_request_irqs: request_irq "
+				"failed for input %d, irq %d\n",
+				ds->info->keymap[i].gpio, irq);
+			goto err_request_irq_failed;
+		}
+		enable_irq_wake(irq);
+	}
+	return 0;
+
+	for (i = ds->info->keymap_size - 1; i >= 0; i--) {
+		free_irq(gpio_to_irq(ds->info->keymap[i].gpio),
+			 &ds->key_state[i]);
+err_request_irq_failed:
+err_gpio_get_irq_num_failed:
+		;
+	}
+	return err;
+}
+
+int gpio_event_input_func(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data, int func)
+{
+	int ret;
+	int i;
+	unsigned long irqflags;
+	struct gpio_event_input_info *di;
+	struct gpio_input_state *ds = *data;
+
+	di = container_of(info, struct gpio_event_input_info, info);
+
+	if (func == GPIO_EVENT_FUNC_SUSPEND) {
+		if (ds->use_irq)
+			for (i = 0; i < di->keymap_size; i++)
+				disable_irq(gpio_to_irq(di->keymap[i].gpio));
+		hrtimer_cancel(&ds->timer);
+		return 0;
+	}
+	if (func == GPIO_EVENT_FUNC_RESUME) {
+		spin_lock_irqsave(&ds->irq_lock, irqflags);
+		if (ds->use_irq)
+			for (i = 0; i < di->keymap_size; i++)
+				enable_irq(gpio_to_irq(di->keymap[i].gpio));
+		hrtimer_start(&ds->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
+		spin_unlock_irqrestore(&ds->irq_lock, irqflags);
+		return 0;
+	}
+
+	if (func == GPIO_EVENT_FUNC_INIT) {
+		if (ktime_to_ns(di->poll_time) <= 0)
+			di->poll_time = ktime_set(0, 20 * NSEC_PER_MSEC);
+
+		*data = ds = kzalloc(sizeof(*ds) + sizeof(ds->key_state[0]) *
+					di->keymap_size, GFP_KERNEL);
+		if (ds == NULL) {
+			ret = -ENOMEM;
+			pr_err("gpio_event_input_func: "
+				"Failed to allocate private data\n");
+			goto err_ds_alloc_failed;
+		}
+		ds->debounce_count = di->keymap_size;
+		ds->input_devs = input_devs;
+		ds->info = di;
+		wake_lock_init(&ds->wake_lock, WAKE_LOCK_SUSPEND, "gpio_input");
+		spin_lock_init(&ds->irq_lock);
+
+		for (i = 0; i < di->keymap_size; i++) {
+			int dev = di->keymap[i].dev;
+			if (dev >= input_devs->count) {
+				pr_err("gpio_event_input_func: bad device "
+					"index %d >= %d for key code %d\n",
+					dev, input_devs->count,
+					di->keymap[i].code);
+				ret = -EINVAL;
+				goto err_bad_keymap;
+			}
+			input_set_capability(input_devs->dev[dev], di->type,
+					     di->keymap[i].code);
+			ds->key_state[i].ds = ds;
+			ds->key_state[i].debounce = DEBOUNCE_UNKNOWN;
+		}
+
+		for (i = 0; i < di->keymap_size; i++) {
+			ret = gpio_request(di->keymap[i].gpio, "gpio_kp_in");
+			if (ret) {
+				pr_err("gpio_event_input_func: gpio_request "
+					"failed for %d\n", di->keymap[i].gpio);
+				goto err_gpio_request_failed;
+			}
+			ret = gpio_direction_input(di->keymap[i].gpio);
+			if (ret) {
+				pr_err("gpio_event_input_func: "
+					"gpio_direction_input failed for %d\n",
+					di->keymap[i].gpio);
+				goto err_gpio_configure_failed;
+			}
+		}
+
+		ret = gpio_event_input_request_irqs(ds);
+
+		spin_lock_irqsave(&ds->irq_lock, irqflags);
+		ds->use_irq = ret == 0;
+
+		pr_info("GPIO Input Driver: Start gpio inputs for %s%s in %s "
+			"mode\n", input_devs->dev[0]->name,
+			(input_devs->count > 1) ? "..." : "",
+			ret == 0 ? "interrupt" : "polling");
+
+		hrtimer_init(&ds->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		ds->timer.function = gpio_event_input_timer_func;
+		hrtimer_start(&ds->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
+		spin_unlock_irqrestore(&ds->irq_lock, irqflags);
+		return 0;
+	}
+
+	ret = 0;
+	spin_lock_irqsave(&ds->irq_lock, irqflags);
+	hrtimer_cancel(&ds->timer);
+	if (ds->use_irq) {
+		for (i = di->keymap_size - 1; i >= 0; i--) {
+			free_irq(gpio_to_irq(di->keymap[i].gpio),
+				 &ds->key_state[i]);
+		}
+	}
+	spin_unlock_irqrestore(&ds->irq_lock, irqflags);
+
+	for (i = di->keymap_size - 1; i >= 0; i--) {
+err_gpio_configure_failed:
+		gpio_free(di->keymap[i].gpio);
+err_gpio_request_failed:
+		;
+	}
+err_bad_keymap:
+	wake_lock_destroy(&ds->wake_lock);
+	kfree(ds);
+err_ds_alloc_failed:
+	return ret;
+}
diff --git a/drivers/input/misc/gpio_matrix.c b/drivers/input/misc/gpio_matrix.c
new file mode 100644
index 00000000000..90866c4dcc6
--- /dev/null
+++ b/drivers/input/misc/gpio_matrix.c
@@ -0,0 +1,422 @@
+/* drivers/input/misc/gpio_matrix.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+#include <linux/hrtimer.h>
+#include <linux/interrupt.h>
+#include <linux/wakelock.h>
+
+struct gpio_kp {
+	struct gpio_event_input_devs *input_devs;
+	struct gpio_event_matrix_info *keypad_info;
+	struct hrtimer timer;
+	struct wake_lock wake_lock;
+	int current_output;
+	unsigned int use_irq:1;
+	unsigned int key_state_changed:1;
+	unsigned int last_key_state_changed:1;
+	unsigned int some_keys_pressed:2;
+	unsigned long keys_pressed[0];
+};
+
+static void clear_phantom_key(struct gpio_kp *kp, int out, int in)
+{
+	struct gpio_event_matrix_info *mi = kp->keypad_info;
+	int key_index = out * mi->ninputs + in;
+	unsigned short keyentry = mi->keymap[key_index];
+	unsigned short keycode = keyentry & MATRIX_KEY_MASK;
+	unsigned short dev = keyentry >> MATRIX_CODE_BITS;
+
+	if (!test_bit(keycode, kp->input_devs->dev[dev]->key)) {
+		if (mi->flags & GPIOKPF_PRINT_PHANTOM_KEYS)
+			pr_info("gpiomatrix: phantom key %x, %d-%d (%d-%d) "
+				"cleared\n", keycode, out, in,
+				mi->output_gpios[out], mi->input_gpios[in]);
+		__clear_bit(key_index, kp->keys_pressed);
+	} else {
+		if (mi->flags & GPIOKPF_PRINT_PHANTOM_KEYS)
+			pr_info("gpiomatrix: phantom key %x, %d-%d (%d-%d) "
+				"not cleared\n", keycode, out, in,
+				mi->output_gpios[out], mi->input_gpios[in]);
+	}
+}
+
+static int restore_keys_for_input(struct gpio_kp *kp, int out, int in)
+{
+	int rv = 0;
+	int key_index;
+
+	key_index = out * kp->keypad_info->ninputs + in;
+	while (out < kp->keypad_info->noutputs) {
+		if (test_bit(key_index, kp->keys_pressed)) {
+			rv = 1;
+			clear_phantom_key(kp, out, in);
+		}
+		key_index += kp->keypad_info->ninputs;
+		out++;
+	}
+	return rv;
+}
+
+static void remove_phantom_keys(struct gpio_kp *kp)
+{
+	int out, in, inp;
+	int key_index;
+
+	if (kp->some_keys_pressed < 3)
+		return;
+
+	for (out = 0; out < kp->keypad_info->noutputs; out++) {
+		inp = -1;
+		key_index = out * kp->keypad_info->ninputs;
+		for (in = 0; in < kp->keypad_info->ninputs; in++, key_index++) {
+			if (test_bit(key_index, kp->keys_pressed)) {
+				if (inp == -1) {
+					inp = in;
+					continue;
+				}
+				if (inp >= 0) {
+					if (!restore_keys_for_input(kp, out + 1,
+									inp))
+						break;
+					clear_phantom_key(kp, out, inp);
+					inp = -2;
+				}
+				restore_keys_for_input(kp, out, in);
+			}
+		}
+	}
+}
+
+static void report_key(struct gpio_kp *kp, int key_index, int out, int in)
+{
+	struct gpio_event_matrix_info *mi = kp->keypad_info;
+	int pressed = test_bit(key_index, kp->keys_pressed);
+	unsigned short keyentry = mi->keymap[key_index];
+	unsigned short keycode = keyentry & MATRIX_KEY_MASK;
+	unsigned short dev = keyentry >> MATRIX_CODE_BITS;
+
+	if (pressed != test_bit(keycode, kp->input_devs->dev[dev]->key)) {
+		if (keycode == KEY_RESERVED) {
+			if (mi->flags & GPIOKPF_PRINT_UNMAPPED_KEYS)
+				pr_info("gpiomatrix: unmapped key, %d-%d "
+					"(%d-%d) changed to %d\n",
+					out, in, mi->output_gpios[out],
+					mi->input_gpios[in], pressed);
+		} else {
+			if (mi->flags & GPIOKPF_PRINT_MAPPED_KEYS)
+				pr_info("gpiomatrix: key %x, %d-%d (%d-%d) "
+					"changed to %d\n", keycode,
+					out, in, mi->output_gpios[out],
+					mi->input_gpios[in], pressed);
+			input_report_key(kp->input_devs->dev[dev], keycode, pressed);
+		}
+	}
+}
+
+static enum hrtimer_restart gpio_keypad_timer_func(struct hrtimer *timer)
+{
+	int out, in;
+	int key_index;
+	int gpio;
+	struct gpio_kp *kp = container_of(timer, struct gpio_kp, timer);
+	struct gpio_event_matrix_info *mi = kp->keypad_info;
+	unsigned gpio_keypad_flags = mi->flags;
+	unsigned polarity = !!(gpio_keypad_flags & GPIOKPF_ACTIVE_HIGH);
+
+	out = kp->current_output;
+	if (out == mi->noutputs) {
+		out = 0;
+		kp->last_key_state_changed = kp->key_state_changed;
+		kp->key_state_changed = 0;
+		kp->some_keys_pressed = 0;
+	} else {
+		key_index = out * mi->ninputs;
+		for (in = 0; in < mi->ninputs; in++, key_index++) {
+			gpio = mi->input_gpios[in];
+			if (gpio_get_value(gpio) ^ !polarity) {
+				if (kp->some_keys_pressed < 3)
+					kp->some_keys_pressed++;
+				kp->key_state_changed |= !__test_and_set_bit(
+						key_index, kp->keys_pressed);
+			} else
+				kp->key_state_changed |= __test_and_clear_bit(
+						key_index, kp->keys_pressed);
+		}
+		gpio = mi->output_gpios[out];
+		if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
+			gpio_set_value(gpio, !polarity);
+		else
+			gpio_direction_input(gpio);
+		out++;
+	}
+	kp->current_output = out;
+	if (out < mi->noutputs) {
+		gpio = mi->output_gpios[out];
+		if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
+			gpio_set_value(gpio, polarity);
+		else
+			gpio_direction_output(gpio, polarity);
+		hrtimer_start(timer, mi->settle_time, HRTIMER_MODE_REL);
+		return HRTIMER_NORESTART;
+	}
+	if (gpio_keypad_flags & GPIOKPF_DEBOUNCE) {
+		if (kp->key_state_changed) {
+			hrtimer_start(&kp->timer, mi->debounce_delay,
+				      HRTIMER_MODE_REL);
+			return HRTIMER_NORESTART;
+		}
+		kp->key_state_changed = kp->last_key_state_changed;
+	}
+	if (kp->key_state_changed) {
+		if (gpio_keypad_flags & GPIOKPF_REMOVE_SOME_PHANTOM_KEYS)
+			remove_phantom_keys(kp);
+		key_index = 0;
+		for (out = 0; out < mi->noutputs; out++)
+			for (in = 0; in < mi->ninputs; in++, key_index++)
+				report_key(kp, key_index, out, in);
+	}
+	if (!kp->use_irq || kp->some_keys_pressed) {
+		hrtimer_start(timer, mi->poll_time, HRTIMER_MODE_REL);
+		return HRTIMER_NORESTART;
+	}
+
+	/* No keys are pressed, reenable interrupt */
+	for (out = 0; out < mi->noutputs; out++) {
+		if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
+			gpio_set_value(mi->output_gpios[out], polarity);
+		else
+			gpio_direction_output(mi->output_gpios[out], polarity);
+	}
+	for (in = 0; in < mi->ninputs; in++)
+		enable_irq(gpio_to_irq(mi->input_gpios[in]));
+	wake_unlock(&kp->wake_lock);
+	return HRTIMER_NORESTART;
+}
+
+static irqreturn_t gpio_keypad_irq_handler(int irq_in, void *dev_id)
+{
+	int i;
+	struct gpio_kp *kp = dev_id;
+	struct gpio_event_matrix_info *mi = kp->keypad_info;
+	unsigned gpio_keypad_flags = mi->flags;
+
+	if (!kp->use_irq) /* ignore interrupt while registering the handler */
+		return IRQ_HANDLED;
+
+	for (i = 0; i < mi->ninputs; i++)
+		disable_irq_nosync(gpio_to_irq(mi->input_gpios[i]));
+	for (i = 0; i < mi->noutputs; i++) {
+		if (gpio_keypad_flags & GPIOKPF_DRIVE_INACTIVE)
+			gpio_set_value(mi->output_gpios[i],
+				!(gpio_keypad_flags & GPIOKPF_ACTIVE_HIGH));
+		else
+			gpio_direction_input(mi->output_gpios[i]);
+	}
+	wake_lock(&kp->wake_lock);
+	hrtimer_start(&kp->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
+	return IRQ_HANDLED;
+}
+
+static int gpio_keypad_request_irqs(struct gpio_kp *kp)
+{
+	int i;
+	int err;
+	unsigned int irq;
+	unsigned long request_flags;
+	struct gpio_event_matrix_info *mi = kp->keypad_info;
+
+	switch (mi->flags & (GPIOKPF_ACTIVE_HIGH|GPIOKPF_LEVEL_TRIGGERED_IRQ)) {
+	default:
+		request_flags = IRQF_TRIGGER_FALLING;
+		break;
+	case GPIOKPF_ACTIVE_HIGH:
+		request_flags = IRQF_TRIGGER_RISING;
+		break;
+	case GPIOKPF_LEVEL_TRIGGERED_IRQ:
+		request_flags = IRQF_TRIGGER_LOW;
+		break;
+	case GPIOKPF_LEVEL_TRIGGERED_IRQ | GPIOKPF_ACTIVE_HIGH:
+		request_flags = IRQF_TRIGGER_HIGH;
+		break;
+	}
+
+	for (i = 0; i < mi->ninputs; i++) {
+		err = irq = gpio_to_irq(mi->input_gpios[i]);
+		if (err < 0)
+			goto err_gpio_get_irq_num_failed;
+		err = request_irq(irq, gpio_keypad_irq_handler, request_flags,
+				  "gpio_kp", kp);
+		if (err) {
+			pr_err("gpiomatrix: request_irq failed for input %d, "
+				"irq %d\n", mi->input_gpios[i], irq);
+			goto err_request_irq_failed;
+		}
+		err = set_irq_wake(irq, 1);
+		if (err) {
+			pr_err("gpiomatrix: set_irq_wake failed for input %d, "
+				"irq %d\n", mi->input_gpios[i], irq);
+		}
+		disable_irq(irq);
+	}
+	return 0;
+
+	for (i = mi->noutputs - 1; i >= 0; i--) {
+		free_irq(gpio_to_irq(mi->input_gpios[i]), kp);
+err_request_irq_failed:
+err_gpio_get_irq_num_failed:
+		;
+	}
+	return err;
+}
+
+int gpio_event_matrix_func(struct gpio_event_input_devs *input_devs,
+	struct gpio_event_info *info, void **data, int func)
+{
+	int i;
+	int err;
+	int key_count;
+	struct gpio_kp *kp;
+	struct gpio_event_matrix_info *mi;
+
+	mi = container_of(info, struct gpio_event_matrix_info, info);
+	if (func == GPIO_EVENT_FUNC_SUSPEND || func == GPIO_EVENT_FUNC_RESUME) {
+		/* TODO: disable scanning */
+		return 0;
+	}
+
+	if (func == GPIO_EVENT_FUNC_INIT) {
+		if (mi->keymap == NULL ||
+		   mi->input_gpios == NULL ||
+		   mi->output_gpios == NULL) {
+			err = -ENODEV;
+			pr_err("gpiomatrix: Incomplete pdata\n");
+			goto err_invalid_platform_data;
+		}
+		key_count = mi->ninputs * mi->noutputs;
+
+		*data = kp = kzalloc(sizeof(*kp) + sizeof(kp->keys_pressed[0]) *
+				     BITS_TO_LONGS(key_count), GFP_KERNEL);
+		if (kp == NULL) {
+			err = -ENOMEM;
+			pr_err("gpiomatrix: Failed to allocate private data\n");
+			goto err_kp_alloc_failed;
+		}
+		kp->input_devs = input_devs;
+		kp->keypad_info = mi;
+		for (i = 0; i < key_count; i++) {
+			unsigned short keyentry = mi->keymap[i];
+			unsigned short keycode = keyentry & MATRIX_KEY_MASK;
+			unsigned short dev = keyentry >> MATRIX_CODE_BITS;
+			if (dev >= input_devs->count) {
+				pr_err("gpiomatrix: bad device index %d >= "
+					"%d for key code %d\n",
+					dev, input_devs->count, keycode);
+				err = -EINVAL;
+				goto err_bad_keymap;
+			}
+			if (keycode && keycode <= KEY_MAX)
+				input_set_capability(input_devs->dev[dev],
+							EV_KEY, keycode);
+		}
+
+		for (i = 0; i < mi->noutputs; i++) {
+			if (gpio_cansleep(mi->output_gpios[i])) {
+				pr_err("gpiomatrix: unsupported output gpio %d,"
+					" can sleep\n", mi->output_gpios[i]);
+				err = -EINVAL;
+				goto err_request_output_gpio_failed;
+			}
+			err = gpio_request(mi->output_gpios[i], "gpio_kp_out");
+			if (err) {
+				pr_err("gpiomatrix: gpio_request failed for "
+					"output %d\n", mi->output_gpios[i]);
+				goto err_request_output_gpio_failed;
+			}
+			if (mi->flags & GPIOKPF_DRIVE_INACTIVE)
+				err = gpio_direction_output(mi->output_gpios[i],
+					!(mi->flags & GPIOKPF_ACTIVE_HIGH));
+			else
+				err = gpio_direction_input(mi->output_gpios[i]);
+			if (err) {
+				pr_err("gpiomatrix: gpio_configure failed for "
+					"output %d\n", mi->output_gpios[i]);
+				goto err_output_gpio_configure_failed;
+			}
+		}
+		for (i = 0; i < mi->ninputs; i++) {
+			err = gpio_request(mi->input_gpios[i], "gpio_kp_in");
+			if (err) {
+				pr_err("gpiomatrix: gpio_request failed for "
+					"input %d\n", mi->input_gpios[i]);
+				goto err_request_input_gpio_failed;
+			}
+			err = gpio_direction_input(mi->input_gpios[i]);
+			if (err) {
+				pr_err("gpiomatrix: gpio_direction_input failed"
+					" for input %d\n", mi->input_gpios[i]);
+				goto err_gpio_direction_input_failed;
+			}
+		}
+		kp->current_output = mi->noutputs;
+		kp->key_state_changed = 1;
+
+		hrtimer_init(&kp->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		kp->timer.function = gpio_keypad_timer_func;
+		wake_lock_init(&kp->wake_lock, WAKE_LOCK_SUSPEND, "gpio_kp");
+		err = gpio_keypad_request_irqs(kp);
+		kp->use_irq = err == 0;
+
+		pr_info("GPIO Matrix Keypad Driver: Start keypad matrix for "
+			"%s%s in %s mode\n", input_devs->dev[0]->name,
+			(input_devs->count > 1) ? "..." : "",
+			kp->use_irq ? "interrupt" : "polling");
+
+		if (kp->use_irq)
+			wake_lock(&kp->wake_lock);
+		hrtimer_start(&kp->timer, ktime_set(0, 0), HRTIMER_MODE_REL);
+
+		return 0;
+	}
+
+	err = 0;
+	kp = *data;
+
+	if (kp->use_irq)
+		for (i = mi->noutputs - 1; i >= 0; i--)
+			free_irq(gpio_to_irq(mi->input_gpios[i]), kp);
+
+	hrtimer_cancel(&kp->timer);
+	wake_lock_destroy(&kp->wake_lock);
+	for (i = mi->noutputs - 1; i >= 0; i--) {
+err_gpio_direction_input_failed:
+		gpio_free(mi->input_gpios[i]);
+err_request_input_gpio_failed:
+		;
+	}
+	for (i = mi->noutputs - 1; i >= 0; i--) {
+err_output_gpio_configure_failed:
+		gpio_free(mi->output_gpios[i]);
+err_request_output_gpio_failed:
+		;
+	}
+err_bad_keymap:
+	kfree(kp);
+err_kp_alloc_failed:
+err_invalid_platform_data:
+	return err;
+}
diff --git a/drivers/input/misc/gpio_output.c b/drivers/input/misc/gpio_output.c
new file mode 100644
index 00000000000..2aac2fad0a1
--- /dev/null
+++ b/drivers/input/misc/gpio_output.c
@@ -0,0 +1,97 @@
+/* drivers/input/misc/gpio_output.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_event.h>
+
+int gpio_event_output_event(
+	struct gpio_event_input_devs *input_devs, struct gpio_event_info *info,
+	void **data, unsigned int dev, unsigned int type,
+	unsigned int code, int value)
+{
+	int i;
+	struct gpio_event_output_info *oi;
+	oi = container_of(info, struct gpio_event_output_info, info);
+	if (type != oi->type)
+		return 0;
+	if (!(oi->flags & GPIOEDF_ACTIVE_HIGH))
+		value = !value;
+	for (i = 0; i < oi->keymap_size; i++)
+		if (dev == oi->keymap[i].dev && code == oi->keymap[i].code)
+			gpio_set_value(oi->keymap[i].gpio, value);
+	return 0;
+}
+
+int gpio_event_output_func(
+	struct gpio_event_input_devs *input_devs, struct gpio_event_info *info,
+	void **data, int func)
+{
+	int ret;
+	int i;
+	struct gpio_event_output_info *oi;
+	oi = container_of(info, struct gpio_event_output_info, info);
+
+	if (func == GPIO_EVENT_FUNC_SUSPEND || func == GPIO_EVENT_FUNC_RESUME)
+		return 0;
+
+	if (func == GPIO_EVENT_FUNC_INIT) {
+		int output_level = !(oi->flags & GPIOEDF_ACTIVE_HIGH);
+
+		for (i = 0; i < oi->keymap_size; i++) {
+			int dev = oi->keymap[i].dev;
+			if (dev >= input_devs->count) {
+				pr_err("gpio_event_output_func: bad device "
+					"index %d >= %d for key code %d\n",
+					dev, input_devs->count,
+					oi->keymap[i].code);
+				ret = -EINVAL;
+				goto err_bad_keymap;
+			}
+			input_set_capability(input_devs->dev[dev], oi->type,
+					     oi->keymap[i].code);
+		}
+
+		for (i = 0; i < oi->keymap_size; i++) {
+			ret = gpio_request(oi->keymap[i].gpio,
+					   "gpio_event_output");
+			if (ret) {
+				pr_err("gpio_event_output_func: gpio_request "
+					"failed for %d\n", oi->keymap[i].gpio);
+				goto err_gpio_request_failed;
+			}
+			ret = gpio_direction_output(oi->keymap[i].gpio,
+						    output_level);
+			if (ret) {
+				pr_err("gpio_event_output_func: "
+					"gpio_direction_output failed for %d\n",
+					oi->keymap[i].gpio);
+				goto err_gpio_direction_output_failed;
+			}
+		}
+		return 0;
+	}
+
+	ret = 0;
+	for (i = oi->keymap_size - 1; i >= 0; i--) {
+err_gpio_direction_output_failed:
+		gpio_free(oi->keymap[i].gpio);
+err_gpio_request_failed:
+		;
+	}
+err_bad_keymap:
+	return ret;
+}
+
diff --git a/drivers/input/misc/keychord.c b/drivers/input/misc/keychord.c
new file mode 100644
index 00000000000..ca23905f304
--- /dev/null
+++ b/drivers/input/misc/keychord.c
@@ -0,0 +1,387 @@
+/*
+ *  drivers/input/misc/keychord.c
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#include <linux/poll.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/smp_lock.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/keychord.h>
+#include <linux/sched.h>
+
+#define KEYCHORD_NAME		"keychord"
+#define BUFFER_SIZE			16
+
+MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
+MODULE_DESCRIPTION("Key chord input driver");
+MODULE_SUPPORTED_DEVICE("keychord");
+MODULE_LICENSE("GPL");
+
+#define NEXT_KEYCHORD(kc) ((struct input_keychord *) \
+		((char *)kc + sizeof(struct input_keychord) + \
+		kc->count * sizeof(kc->keycodes[0])))
+
+struct keychord_device {
+	struct input_handler	input_handler;
+	int			registered;
+
+	/* list of keychords to monitor */
+	struct input_keychord	*keychords;
+	int			keychord_count;
+
+	/* bitmask of keys contained in our keychords */
+	unsigned long keybit[BITS_TO_LONGS(KEY_CNT)];
+	/* current state of the keys */
+	unsigned long keystate[BITS_TO_LONGS(KEY_CNT)];
+	/* number of keys that are currently pressed */
+	int key_down;
+
+	/* second input_device_id is needed for null termination */
+	struct input_device_id  device_ids[2];
+
+	spinlock_t		lock;
+	wait_queue_head_t	waitq;
+	unsigned char		head;
+	unsigned char		tail;
+	__u16			buff[BUFFER_SIZE];
+};
+
+static int check_keychord(struct keychord_device *kdev,
+		struct input_keychord *keychord)
+{
+	int i;
+
+	if (keychord->count != kdev->key_down)
+		return 0;
+
+	for (i = 0; i < keychord->count; i++) {
+		if (!test_bit(keychord->keycodes[i], kdev->keystate))
+			return 0;
+	}
+
+	/* we have a match */
+	return 1;
+}
+
+static void keychord_event(struct input_handle *handle, unsigned int type,
+			   unsigned int code, int value)
+{
+	struct keychord_device *kdev = handle->private;
+	struct input_keychord *keychord;
+	unsigned long flags;
+	int i, got_chord = 0;
+
+	if (type != EV_KEY || code >= KEY_MAX)
+		return;
+
+	spin_lock_irqsave(&kdev->lock, flags);
+	/* do nothing if key state did not change */
+	if (!test_bit(code, kdev->keystate) == !value)
+		goto done;
+	__change_bit(code, kdev->keystate);
+	if (value)
+		kdev->key_down++;
+	else
+		kdev->key_down--;
+
+	/* don't notify on key up */
+	if (!value)
+		goto done;
+	/* ignore this event if it is not one of the keys we are monitoring */
+	if (!test_bit(code, kdev->keybit))
+		goto done;
+
+	keychord = kdev->keychords;
+	if (!keychord)
+		goto done;
+
+	/* check to see if the keyboard state matches any keychords */
+	for (i = 0; i < kdev->keychord_count; i++) {
+		if (check_keychord(kdev, keychord)) {
+			kdev->buff[kdev->head] = keychord->id;
+			kdev->head = (kdev->head + 1) % BUFFER_SIZE;
+			got_chord = 1;
+			break;
+		}
+		/* skip to next keychord */
+		keychord = NEXT_KEYCHORD(keychord);
+	}
+
+done:
+	spin_unlock_irqrestore(&kdev->lock, flags);
+
+	if (got_chord)
+		wake_up_interruptible(&kdev->waitq);
+}
+
+static int keychord_connect(struct input_handler *handler,
+					  struct input_dev *dev,
+					  const struct input_device_id *id)
+{
+	int i, ret;
+	struct input_handle *handle;
+	struct keychord_device *kdev =
+		container_of(handler, struct keychord_device, input_handler);
+
+	/*
+	 * ignore this input device if it does not contain any keycodes
+	 * that we are monitoring
+	 */
+	for (i = 0; i < KEY_MAX; i++) {
+		if (test_bit(i, kdev->keybit) && test_bit(i, dev->keybit))
+			break;
+	}
+	if (i == KEY_MAX)
+		return -ENODEV;
+
+	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+	if (!handle)
+		return -ENOMEM;
+
+	handle->dev = dev;
+	handle->handler = handler;
+	handle->name = KEYCHORD_NAME;
+	handle->private = kdev;
+
+	ret = input_register_handle(handle);
+	if (ret)
+		goto err_input_register_handle;
+
+	ret = input_open_device(handle);
+	if (ret)
+		goto err_input_open_device;
+
+	pr_info("keychord: using input dev %s for fevent\n", dev->name);
+
+	return 0;
+
+err_input_open_device:
+	input_unregister_handle(handle);
+err_input_register_handle:
+	kfree(handle);
+	return ret;
+}
+
+static void keychord_disconnect(struct input_handle *handle)
+{
+	input_close_device(handle);
+	input_unregister_handle(handle);
+	kfree(handle);
+}
+
+/*
+ * keychord_read is used to read keychord events from the driver
+ */
+static ssize_t keychord_read(struct file *file, char __user *buffer,
+		size_t count, loff_t *ppos)
+{
+	struct keychord_device *kdev = file->private_data;
+	__u16   id;
+	int retval;
+	unsigned long flags;
+
+	if (count < sizeof(id))
+		return -EINVAL;
+	count = sizeof(id);
+
+	if (kdev->head == kdev->tail && (file->f_flags & O_NONBLOCK))
+		return -EAGAIN;
+
+	retval = wait_event_interruptible(kdev->waitq,
+			kdev->head != kdev->tail);
+	if (retval)
+		return retval;
+
+	spin_lock_irqsave(&kdev->lock, flags);
+	/* pop a keychord ID off the queue */
+	id = kdev->buff[kdev->tail];
+	kdev->tail = (kdev->tail + 1) % BUFFER_SIZE;
+	spin_unlock_irqrestore(&kdev->lock, flags);
+
+	if (copy_to_user(buffer, &id, count))
+		return -EFAULT;
+
+	return count;
+}
+
+/*
+ * keychord_write is used to configure the driver
+ */
+static ssize_t keychord_write(struct file *file, const char __user *buffer,
+		size_t count, loff_t *ppos)
+{
+	struct keychord_device *kdev = file->private_data;
+	struct input_keychord *keychords = 0;
+	struct input_keychord *keychord, *next, *end;
+	int ret, i, key;
+	unsigned long flags;
+
+	if (count < sizeof(struct input_keychord))
+		return -EINVAL;
+	keychords = kzalloc(count, GFP_KERNEL);
+	if (!keychords)
+		return -ENOMEM;
+
+	/* read list of keychords from userspace */
+	if (copy_from_user(keychords, buffer, count)) {
+		kfree(keychords);
+		return -EFAULT;
+	}
+
+	/* unregister handler before changing configuration */
+	if (kdev->registered) {
+		input_unregister_handler(&kdev->input_handler);
+		kdev->registered = 0;
+	}
+
+	spin_lock_irqsave(&kdev->lock, flags);
+	/* clear any existing configuration */
+	kfree(kdev->keychords);
+	kdev->keychords = 0;
+	kdev->keychord_count = 0;
+	kdev->key_down = 0;
+	memset(kdev->keybit, 0, sizeof(kdev->keybit));
+	memset(kdev->keystate, 0, sizeof(kdev->keystate));
+	kdev->head = kdev->tail = 0;
+
+	keychord = keychords;
+	end = (struct input_keychord *)((char *)keychord + count);
+
+	while (keychord < end) {
+		next = NEXT_KEYCHORD(keychord);
+		if (keychord->count <= 0 || next > end) {
+			pr_err("keychord: invalid keycode count %d\n",
+				keychord->count);
+			goto err_unlock_return;
+		}
+		if (keychord->version != KEYCHORD_VERSION) {
+			pr_err("keychord: unsupported version %d\n",
+				keychord->version);
+			goto err_unlock_return;
+		}
+
+		/* keep track of the keys we are monitoring in keybit */
+		for (i = 0; i < keychord->count; i++) {
+			key = keychord->keycodes[i];
+			if (key < 0 || key >= KEY_CNT) {
+				pr_err("keychord: keycode %d out of range\n",
+					key);
+				goto err_unlock_return;
+			}
+			__set_bit(key, kdev->keybit);
+		}
+
+		kdev->keychord_count++;
+		keychord = next;
+	}
+
+	kdev->keychords = keychords;
+	spin_unlock_irqrestore(&kdev->lock, flags);
+
+	ret = input_register_handler(&kdev->input_handler);
+	if (ret) {
+		kfree(keychords);
+		kdev->keychords = 0;
+		return ret;
+	}
+	kdev->registered = 1;
+
+	return count;
+
+err_unlock_return:
+	spin_unlock_irqrestore(&kdev->lock, flags);
+	kfree(keychords);
+	return -EINVAL;
+}
+
+static unsigned int keychord_poll(struct file *file, poll_table *wait)
+{
+	struct keychord_device *kdev = file->private_data;
+
+	poll_wait(file, &kdev->waitq, wait);
+
+	if (kdev->head != kdev->tail)
+		return POLLIN | POLLRDNORM;
+
+	return 0;
+}
+
+static int keychord_open(struct inode *inode, struct file *file)
+{
+	struct keychord_device *kdev;
+
+	kdev = kzalloc(sizeof(struct keychord_device), GFP_KERNEL);
+	if (!kdev)
+		return -ENOMEM;
+
+	spin_lock_init(&kdev->lock);
+	init_waitqueue_head(&kdev->waitq);
+
+	kdev->input_handler.event = keychord_event;
+	kdev->input_handler.connect = keychord_connect;
+	kdev->input_handler.disconnect = keychord_disconnect;
+	kdev->input_handler.name = KEYCHORD_NAME;
+	kdev->input_handler.id_table = kdev->device_ids;
+
+	kdev->device_ids[0].flags = INPUT_DEVICE_ID_MATCH_EVBIT;
+	__set_bit(EV_KEY, kdev->device_ids[0].evbit);
+
+	file->private_data = kdev;
+
+	return 0;
+}
+
+static int keychord_release(struct inode *inode, struct file *file)
+{
+	struct keychord_device *kdev = file->private_data;
+
+	if (kdev->registered)
+		input_unregister_handler(&kdev->input_handler);
+	kfree(kdev);
+
+	return 0;
+}
+
+static const struct file_operations keychord_fops = {
+	.owner		= THIS_MODULE,
+	.open		= keychord_open,
+	.release	= keychord_release,
+	.read		= keychord_read,
+	.write		= keychord_write,
+	.poll		= keychord_poll,
+};
+
+static struct miscdevice keychord_misc = {
+	.fops		= &keychord_fops,
+	.name		= KEYCHORD_NAME,
+	.minor		= MISC_DYNAMIC_MINOR,
+};
+
+static int __init keychord_init(void)
+{
+	return misc_register(&keychord_misc);
+}
+
+static void __exit keychord_exit(void)
+{
+	misc_deregister(&keychord_misc);
+}
+
+module_init(keychord_init);
+module_exit(keychord_exit);
diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig
index 3feeb3af8ab..c729f67b8ed 100644
--- a/drivers/input/mouse/Kconfig
+++ b/drivers/input/mouse/Kconfig
@@ -292,6 +292,12 @@ config MOUSE_PXA930_TRKBALL
 	help
 	  Say Y here to support PXA930 Trackball mouse.
 
+config MOUSE_AK88_TRKBALL
+	tristate "AK88 gpio trackball mouse"
+	depends on BOARD_AK8802EBOOK
+	help
+	  Say Y here to support AK880x gpio trackball mouse.
+
 config MOUSE_MAPLE
 	tristate "Maple mouse (for the Dreamcast)"
 	depends on MAPLE
diff --git a/drivers/input/mouse/Makefile b/drivers/input/mouse/Makefile
index 570c84a4a65..89ef602e583 100644
--- a/drivers/input/mouse/Makefile
+++ b/drivers/input/mouse/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_MOUSE_RISCPC)		+= rpcmouse.o
 obj-$(CONFIG_MOUSE_SERIAL)		+= sermouse.o
 obj-$(CONFIG_MOUSE_SYNAPTICS_I2C)	+= synaptics_i2c.o
 obj-$(CONFIG_MOUSE_VSXXXAA)		+= vsxxxaa.o
+obj-$(CONFIG_MOUSE_AK88_TRKBALL)	+= ak88_trkball.o
 
 psmouse-objs := psmouse-base.o synaptics.o
 
diff --git a/drivers/input/mouse/ak88_trkball.c b/drivers/input/mouse/ak88_trkball.c
new file mode 100644
index 00000000000..622b1d80e4a
--- /dev/null
+++ b/drivers/input/mouse/ak88_trkball.c
@@ -0,0 +1,299 @@
+/* 
+ * AK8802 gpio track ball mouse driver
+ *
+ * Copyright (C) 2010 Anyka Ltd.
+ * 2010-06-09: Jacky Lau <liu_zhuyuan@anyka.com>
+ *             initial version
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/version.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+struct input_dev *ak88_trkball_input_dev;
+
+#define TRKBALL_GPIO_COUNT 4
+
+struct ak880x_trkball {
+	unsigned int irq_type[TRKBALL_GPIO_COUNT];
+};
+
+struct ak880x_trkball_irq_settings {
+	const char *name;
+	irq_handler_t handler;
+};
+
+static irqreturn_t ak880x_trkball_up_interrupt(int irq, void *dev_id);
+static irqreturn_t ak880x_trkball_down_interrupt(int irq, void *dev_id);
+static irqreturn_t ak880x_trkball_left_interrupt(int irq, void *dev_id);
+static irqreturn_t ak880x_trkball_right_interrupt(int irq, void *dev_id);
+
+static struct ak880x_trkball_irq_settings ak880x_trkball_gpio_irq_settings[TRKBALL_GPIO_COUNT] = {
+	{
+		.name    = "UP GPIO IRQ",
+		.handler = ak880x_trkball_up_interrupt,
+	}, {
+		.name    = "DOWN GPIO IRQ",
+		.handler = ak880x_trkball_down_interrupt,
+	}, {
+		.name    = "LEFT GPIO IRQ",
+		.handler = ak880x_trkball_left_interrupt,
+	}, {
+		.name    = "RIGHT GPIO IRQ",
+		.handler = ak880x_trkball_right_interrupt,
+	},
+};
+
+static irqreturn_t ak880x_trkball_up_interrupt(int irq, void *dev_id)
+{
+	struct input_dev *input = dev_id;
+	struct ak880x_trkball *trkball = input_get_drvdata(input);
+
+	input_report_rel(input, REL_Y, -1);
+	input_sync(input);
+
+	if (trkball->irq_type[0] == IRQ_TYPE_LEVEL_LOW) {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+		trkball->irq_type[0] = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
+		trkball->irq_type[0] = IRQ_TYPE_LEVEL_LOW;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t ak880x_trkball_down_interrupt(int irq, void *dev_id)
+{
+	struct input_dev *input = dev_id;
+	struct ak880x_trkball *trkball = input_get_drvdata(input);
+
+	input_report_rel(input, REL_Y, 1);
+	input_sync(input);
+
+	if (trkball->irq_type[1] == IRQ_TYPE_LEVEL_LOW) {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+		trkball->irq_type[1] = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
+		trkball->irq_type[1] = IRQ_TYPE_LEVEL_LOW;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t ak880x_trkball_left_interrupt(int irq, void *dev_id)
+{
+	struct input_dev *input = dev_id;
+	struct ak880x_trkball *trkball = input_get_drvdata(input);
+
+	input_report_rel(input, REL_X, -1);
+	input_sync(input);
+
+	if (trkball->irq_type[2] == IRQ_TYPE_LEVEL_LOW) {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+		trkball->irq_type[2] = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
+		trkball->irq_type[2] = IRQ_TYPE_LEVEL_LOW;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t ak880x_trkball_right_interrupt(int irq, void *dev_id)
+{
+	struct input_dev *input = dev_id;
+	struct ak880x_trkball *trkball = input_get_drvdata(input);
+
+	input_report_rel(input, REL_X, 1);
+	input_sync(input);
+
+	if (trkball->irq_type[3] == IRQ_TYPE_LEVEL_LOW) {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+		trkball->irq_type[3] = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
+		trkball->irq_type[3] = IRQ_TYPE_LEVEL_LOW;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static atomic_t trkball_ref = ATOMIC_INIT(0);
+
+static int ak880x_trkball_open(struct input_dev *dev)
+{
+	int ref;
+
+	ref = atomic_inc_return(&trkball_ref);
+	if (ref == 1) {
+		/* for track ball power */
+		AK88_GPIO_PCM_JTAG(AK88_SHARE_GPIO);
+		ak880x_gpio_pullup(AK88_GPIO_3, AK88_GPIO_PUPD_ENABLE);
+		ak880x_gpio_cfgpin(AK88_GPIO_3, AK88_GPIO_OUT_0);
+		/* power on */
+		ak880x_gpio_setpin(AK88_GPIO_3, 1);
+	}
+
+	return 0;
+}
+
+static void ak880x_trkball_close(struct input_dev *dev)
+{
+	int ref;
+
+	ref = atomic_dec_return(&trkball_ref);
+	if (ref == 0) {
+		/* track ball power off */
+		ak880x_gpio_setpin(AK88_GPIO_3, 0);
+	}
+
+	return;
+}
+
+static int __devinit ak880x_trkball_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct ak880x_trkball *trkball;
+	struct input_dev *input;
+	int irq[TRKBALL_GPIO_COUNT], i, error;
+#if 0
+	int gpio;
+#endif
+
+	for (i = 0; i < TRKBALL_GPIO_COUNT; i++) {
+		irq[i] = -1;
+	}
+
+	trkball = kzalloc(sizeof(struct ak880x_trkball), GFP_KERNEL);
+	if (!trkball)
+		return -ENOMEM;
+
+	input = input_allocate_device();
+	if (!input) {
+		dev_err(&pdev->dev, "failed to allocate input device\n");
+		error = -ENOMEM;
+		goto failed;
+	}
+
+	input->name = pdev->name;
+	input->id.bustype = BUS_HOST;
+	input->open = ak880x_trkball_open;
+	input->close = ak880x_trkball_close;
+	input->dev.parent = &pdev->dev;
+	input_set_drvdata(input, trkball);
+
+	input_set_capability(input, EV_REL, REL_X);
+	input_set_capability(input, EV_REL, REL_Y);
+	input_set_capability(input, EV_KEY, BTN_LEFT);
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(&pdev->dev, "unable to register input device\n");
+		goto failed_free_input;
+	}
+
+	platform_set_drvdata(pdev, input);
+
+#if 0	/* track ball gpio setting, UNNECESSARY */
+	AK88_GPIO_SPI1(AK88_SHARE_GPIO);
+#endif
+
+	/* track ball irq setting */
+	for (i = 0; i < TRKBALL_GPIO_COUNT; i++) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, ak880x_trkball_gpio_irq_settings[i].name);
+		if (res == NULL) {
+			dev_err(&pdev->dev, "failed to get trkball irq\n");
+			error = -ENXIO;
+			goto failed_free_irq;
+		}
+
+#if 0			/* track ball gpio setting, UNNECESSARY */
+		gpio = ak880x_irq_to_gpio(res->start);
+		ak880x_gpio_pullup(gpio, AK88_GPIO_PUPD_DISABLE);
+		ak880x_gpio_cfgpin(gpio, AK88_GPIO_IN_0);
+#endif
+
+		irq[i] = res->start;
+		trkball->irq_type[i] = res->flags & IORESOURCE_BITS;
+		set_irq_type(irq[i], trkball->irq_type[i]);
+		error = request_irq(irq[i], ak880x_trkball_gpio_irq_settings[i].handler,
+				    IRQF_DISABLED, pdev->name, input);
+		if (error) {
+			dev_err(&pdev->dev, "failed to request irq: %d\n", error);
+			goto failed_free_irq;
+		}
+	}
+
+	ak88_trkball_input_dev = input;
+
+	return 0;
+
+failed_free_irq:
+	for (i = 0; i < TRKBALL_GPIO_COUNT; i++) {
+		if (irq[i] >= 0)
+			free_irq(irq[i], input);
+	}
+failed_free_input:
+	input_free_device(input);
+failed:
+	kfree(trkball);
+	return error;
+}
+
+static int __devexit ak880x_trkball_remove(struct platform_device *pdev)
+{
+	struct input_dev *input = platform_get_drvdata(pdev);
+	struct ak880x_trkball *trkball = input_get_drvdata(input);
+	int irq, i;
+
+	ak88_trkball_input_dev = NULL;
+
+	for (i = 0; i < TRKBALL_GPIO_COUNT; i++) {
+		irq = platform_get_irq(pdev, i);
+		free_irq(irq, input);
+	}
+
+	input_unregister_device(input);
+	kfree(trkball);
+
+	return 0;
+}
+
+static struct platform_driver ak880x_trkball_driver = {
+	.driver		= {
+		.name	= "ak880x-trkball",
+	},
+	.probe		= ak880x_trkball_probe,
+	.remove		= __devexit_p(ak880x_trkball_remove),
+};
+
+static int __init ak880x_trkball_init(void)
+{
+	return platform_driver_register(&ak880x_trkball_driver);
+}
+
+static void __exit ak880x_trkball_exit(void)
+{
+	platform_driver_unregister(&ak880x_trkball_driver);
+}
+
+module_init(ak880x_trkball_init);
+module_exit(ak880x_trkball_exit);
+
+MODULE_AUTHOR("Jacky Lau <liu_zhuyuan@anyka.com>");
+MODULE_DESCRIPTION("Ak8802 ebook Trackball Mouse Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 8cc453c85ea..4a64dd40434 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -271,6 +271,12 @@ config TOUCHSCREEN_MIGOR
 	  To compile this driver as a module, choose M here: the
 	  module will be called migor_ts.
 
+config TOUCHSCREEN_SYNAPTICS_I2C_RMI
+	tristate "Synaptics i2c touchscreen"
+	depends on I2C
+	help
+	  This enables support for Synaptics RMI over I2C based touchscreens.
+
 config TOUCHSCREEN_TOUCHRIGHT
 	tristate "Touchright serial touchscreen"
 	select SERIO
@@ -530,4 +536,61 @@ config TOUCHSCREEN_PCAP
 
 	  To compile this driver as a module, choose M here: the
 	  module will be called pcap_ts.
+
+config TOUCHSCREEN_AK88
+        tristate "AK88 touchscreen"
+        depends on ARCH_AK88
+        help
+          This enables support for the AK88 touchscreen interface.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ak88_ts.
+
+config TOUCHSCREEN_AK88_DEBUG
+        boolean "AK88 touchscreen debug messages"
+        depends on TOUCHSCREEN_AK88
+        default y
+        help
+          Select this if you want debug messages
+
+config TOUCHSCREEN_AK98
+        tristate "AK98 CP2007 touchscreen"
+        depends on ARCH_AK98
+        help
+          This enables support for the AK98 touchscreen interface.
+
+          To compile this driver as a module, choose M here: the
+          module will be called cp2007_ts.
+
+config TOUCHSCREEN_AK98_DEBUG
+        boolean "AK98 touchscreen debug messages"
+        depends on TOUCHSCREEN_AK98
+        default n
+        help
+          Select this if you want debug messages
+          
+config TOUCHSCREEN_AK98ADC
+        tristate "AK98 ADC touchscreen"
+        depends on ARCH_AK98
+        help
+          This enables support for the AK98 ADC touchscreen interface.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ak98adc_ts.
+config TOUCHSCREEN_AK98_AR7643
+        tristate "AK98 AR7643 touchscreen"
+        depends on ARCH_AK98
+        help
+          This enables support for the AK98 AR7643 touchscreen interface.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ar7643_ts.
+config TOUCHSCREEN_AK98_AR7643_SPI
+        tristate "AK98 SPI AR7643 touchscreen"
+        depends on ARCH_AK98
+        help
+          This enables support for the AK98 SPI AR7643 touchscreen interface.
+
+          To compile this driver as a module, choose M here: the
+          module will be called ar7643.
 endif
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 15fa62cffc7..58257327fc3 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_TOUCHSCREEN_HP7XX)		+= jornada720_ts.o
 obj-$(CONFIG_TOUCHSCREEN_HTCPEN)	+= htcpen.o
 obj-$(CONFIG_TOUCHSCREEN_USB_COMPOSITE)	+= usbtouchscreen.o
 obj-$(CONFIG_TOUCHSCREEN_PENMOUNT)	+= penmount.o
+obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI)	+= synaptics_i2c_rmi.o
 obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213)	+= touchit213.o
 obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT)	+= touchright.o
 obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN)	+= touchwin.o
@@ -42,3 +43,9 @@ obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE)	+= mainstone-wm97xx.o
 obj-$(CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE)	+= zylonite-wm97xx.o
 obj-$(CONFIG_TOUCHSCREEN_W90X900)	+= w90p910_ts.o
 obj-$(CONFIG_TOUCHSCREEN_PCAP)		+= pcap_ts.o
+obj-$(CONFIG_TOUCHSCREEN_AK88)		+= ak88_ts.o
+obj-$(CONFIG_TOUCHSCREEN_AK98)		+= tscp2007.o
+obj-$(CONFIG_TOUCHSCREEN_AK98ADC)	+= ak98adc_ts.o
+obj-$(CONFIG_TOUCHSCREEN_AK98_AR7643)	+= ar7643_ts.o
+obj-$(CONFIG_TOUCHSCREEN_AK98_AR7643_SPI)	+= ar7643.o
+
diff --git a/drivers/input/touchscreen/ak88_ts.c b/drivers/input/touchscreen/ak88_ts.c
new file mode 100644
index 00000000000..ae9786dcb6b
--- /dev/null
+++ b/drivers/input/touchscreen/ak88_ts.c
@@ -0,0 +1,335 @@
+/*
+ * drivers/input/touchscreen/ak880x_ts.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <mach/regs-adc.h>
+#include <mach/gpio.h>
+#include <mach/ts.h>
+
+/* For ts.dev.id.version */
+#define AK88TSVERSION	0x0101
+
+/*
+ * Definitions & global arrays.
+ */
+
+static char *ak880xts_name = "AK88 TouchScreen";
+
+/*
+ * Per-touchscreen data.
+ */
+
+struct ak880xts {
+	struct input_dev *dev;
+	unsigned int state_pin;
+	unsigned int irq;
+	long xp;
+	long yp;
+	int count;
+	int shift;
+	char phys[32];
+};
+
+static struct ak880xts ts;
+
+static void touch_timer_handler(unsigned long data);
+static struct timer_list touch_timer = TIMER_INITIALIZER(touch_timer_handler, 0, 0);
+
+#define ADC_MAIN_CLK	(12 * 1000000)	/* 12MHz */
+#define ADC_CLK		( 4 * 1000000)	/*  4MHz */
+
+#define TS_POWER_ON_ADC		*(volatile unsigned long*)(AK88_ANALOG_CTRL1) &= ~(1<<26)
+#define TS_POWER_OFF_ADC	*(volatile unsigned long*)(AK88_ANALOG_CTRL1) |= (1<<26)
+// Read ADC power  status ,   1-- off    (for AK3223)
+#define TS_ADC_POWER_STA	(*(volatile unsigned long*)(AK88_ANALOG_CTRL1) & (1<<26))
+
+
+static void init_ts_hw(unsigned int SampleRate, unsigned int WaitTime)
+{
+#if 1
+	unsigned long ClkDiv = 0;
+	unsigned long bitcycle = 0;
+	unsigned long temp;
+	unsigned long HoldTime = 0;
+
+	//reset ADC1
+	*(volatile unsigned long *)AK88_CLK_DIV2 &= ~(1 << 22);
+	mdelay(1);
+	*(volatile unsigned long *)AK88_CLK_DIV2 |= (1 << 22);
+
+	ClkDiv = (ADC_MAIN_CLK / ADC_CLK) - 1;
+
+	temp = *(volatile unsigned long *)(AK88_CLK_DIV2);
+	temp &= ~(1 << 29);
+	temp |= (1 << 22) | (1 << 3) | (ClkDiv << 0);
+	*(volatile unsigned long *)AK88_CLK_DIV2 = temp;
+
+	/* because ADC1 is 5 channel multiplex*/
+	SampleRate	 = SampleRate * 5;
+	bitcycle	= (unsigned long)ADC_CLK / SampleRate;
+	HoldTime	= bitcycle - 1;
+
+	*(volatile unsigned long*)AK88_ADC1_CTRL = (HoldTime << 16) | bitcycle;
+
+	//power on touch screen interface, select 5 channel mode
+	*(volatile unsigned long*)AK88_ANALOG_CTRL1 |= (1 << 29);
+	*(volatile unsigned long*)AK88_ANALOG_CTRL1 &= ~((1 << 26) | (1 << 27)  | (1 << 28));
+
+	//Enable touch screen, set TS_THRESHOLD and TS_WaitTime
+	*(volatile unsigned long*)AK88_ANALOG_CTRL2 |= ((0x3FF << 17) | (WaitTime << 0) | (1 << 10));
+
+	//Enable ADC1
+	*(volatile unsigned long*)AK88_ANALOG_CTRL2 |= (1 << 8);
+
+	//Enable Battery monitor
+	*(volatile unsigned long*)AK88_ANALOG_CTRL1 |= (1 << 28);   //eable battery volatage divider
+
+#else
+	/* unsigned long regval; */
+
+	*(volatile unsigned long*)AK88_ANALOG_CTRL1 &= ~(PD_TS | RM_DIR);
+
+	*(volatile unsigned long*)AK88_ANALOG_CTRL1 |= AD5_sel1;
+
+	*(volatile unsigned long*)AK88_CLK_DIV2 &= ~ADC1_pd;
+	*(volatile unsigned long*)AK88_CLK_DIV2 |= (ADC1_rst | ADC1_CLK_en | ADC1_DIV2);
+
+	*(volatile unsigned long*)AK88_ADC1_CTRL = 0x04000401;
+
+	*(volatile unsigned long*)AK88_ANALOG_CTRL2 |= ( 0x08<<17 | TS_ctrl255 | TS_en);
+
+	/* 0x08000064 Enable ADC1 */
+	*(volatile unsigned long*)AK88_ANALOG_CTRL2 |= ADC1_en;
+#endif
+}
+
+static void touch_timer_handler(unsigned long data)
+{
+	volatile unsigned long xdata[4] = { 0, 0, 0, 0 };
+	volatile unsigned long ydata[4] = { 0, 0, 0, 0 };
+	unsigned int i = 0;
+
+	if (ak880x_gpio_getpin(ts.state_pin)) {
+		
+		input_report_key(ts.dev, BTN_TOUCH, 0);
+		input_report_abs(ts.dev, ABS_PRESSURE, 0);
+		input_sync(ts.dev);
+
+		enable_irq(ts.irq);
+
+	} else {
+
+		while (TS_ADC_POWER_STA != 0) {
+			TS_POWER_ON_ADC;
+			udelay(10);
+		}
+
+		while (i++ < 3) {
+
+			mb();
+
+			xdata[i] = __raw_readl(AK88_X_COORDINATE) & 0x3FF;
+			ydata[i] = __raw_readl(AK88_Y_COORDINATE) & 0x3FF;
+
+			mdelay(1);
+
+#ifdef	CONFIG_TOUCHSCREEN_AK88_DEBUG
+			/* FIXME:
+			 * åŽæ“—…Ž‰æ“—ˆ™é‡Œçš„打å�å”蟡‰¸‘æ�è�”¼ŒTG3æ’…�æ’Ÿ•æ âˆª‡†æ“—ˆ‡éŠ��鈭†åš—Œéœ€é–¬�é�鞈£ çž�鞎Šè…¦ */
+			printk(KERN_DEBUG "XP: %ld\n", xdata[i]);
+			printk(KERN_DEBUG "YP: %ld\n", ydata[i]);
+#endif
+		}
+
+		while (TS_ADC_POWER_STA == 0) {
+			TS_POWER_OFF_ADC;
+			udelay(10);
+		}
+
+		input_report_abs(ts.dev, ABS_X, xdata[2]);
+		input_report_abs(ts.dev, ABS_Y, ydata[2]);
+
+		input_report_key(ts.dev, BTN_TOUCH, 1);
+		input_report_abs(ts.dev, ABS_PRESSURE, 1);
+
+		input_sync(ts.dev);
+
+		/* modify timer */
+		mod_timer(&touch_timer, jiffies+HZ/100);
+	}
+}
+
+/* 
+ * touch screen interrupt handler.
+ */
+static irqreturn_t ak7801ts_irqhandler(int irq, void *dev)
+{
+	disable_irq(irq);
+
+	/* printk("%s: irq no %d\n", __FUNCTION__, irq); */
+	
+	/* touch_timer_handler(0); */
+	mod_timer(&touch_timer, jiffies+HZ/100);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * The functions for inserting/removing us as a module.
+ */
+
+static int __init ak880x_ts_probe(struct platform_device *dev)
+{
+	struct ak880x_ts_mach_info *info;
+
+	info = (struct ak880x_ts_mach_info *)dev->dev.platform_data;
+	if (!info) {
+		printk(KERN_ERR "no platform data for ts\n");
+		return -EINVAL;
+	}
+
+	/* initialize hardware */
+	init_ts_hw(info->sample_rate, info->wait_time);
+	TS_POWER_OFF_ADC;
+
+	/* Initialise input stuff */
+	memset(&ts, 0, sizeof(struct ak880xts));
+	ts.dev = input_allocate_device();
+	if (!ts.dev)
+		return -ENOMEM;
+
+	ts.dev->evbit[0] = BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
+	ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_WORD(BTN_TOUCH);
+	input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0);
+	input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0);
+	input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0);
+
+	sprintf(ts.phys, "ts0");
+
+	//ts.dev->private = &ts;
+	ts.dev->name = ak880xts_name;
+	ts.dev->phys = ts.phys;
+	ts.dev->id.bustype = BUS_RS232;
+	ts.dev->id.vendor = 0xDEAD;
+	ts.dev->id.product = 0xBEEF;
+	ts.dev->id.version = AK88TSVERSION;
+
+	ts.state_pin	= info->irqpin;
+	ts.irq		= info->irq;
+
+	ak880x_gpio_cfgpin(info->irqpin, AK88_GPIO_IN_0); 
+	ak880x_gpio_pullup(info->irqpin, 1);
+	
+	set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
+#if 1
+	if (request_irq(info->irq, ak7801ts_irqhandler, 0, "ak880x_ts", ts.dev)) {
+		printk(KERN_ERR "Could not allocate IRQ %d\n", info->irq);
+		return -EIO;
+	}
+#endif
+
+	printk(KERN_INFO "%s successfully loaded\n", ak880xts_name);
+
+	/* All went ok, so register to the input system */
+	return input_register_device(ts.dev);
+}
+
+static int ak880x_ts_remove(struct platform_device *dev)
+{
+	struct ak880x_ts_mach_info *info;
+
+	info = (struct ak880x_ts_mach_info *)dev->dev.platform_data;
+	if (!info) {
+		printk(KERN_ERR "no platform data for ts\n");
+		return -EINVAL;
+	}
+
+	disable_irq(info->irq);
+	free_irq(info->irq, ts.dev);
+
+#if 0
+	if (adc_clock) {
+		clk_disable(adc_clock);
+		clk_put(adc_clock);
+		adc_clock = NULL;
+	}
+#endif
+
+	input_unregister_device(ts.dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int ak880x_ts_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int ak880x_ts_resume(struct platform_device *dev)
+{
+	return 0;
+}
+#endif
+
+
+static struct platform_driver ak880x_ts_driver = {
+	.driver		= {
+		.name	= "ak7801-ts",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= ak880x_ts_probe,
+	.remove		= ak880x_ts_remove,
+#ifdef	CONFIG_PM
+	.suspend	= ak880x_ts_suspend,
+	.resume		= ak880x_ts_resume,
+#endif
+};
+
+static int __init ak880x_ts_init(void)
+{
+	printk("AK88 Touchscreen Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_register(&ak880x_ts_driver);
+}
+
+static void __exit ak880x_ts_exit(void)
+{
+	platform_driver_unregister(&ak880x_ts_driver);
+}
+
+module_init(ak880x_ts_init);
+module_exit(ak880x_ts_exit);
+
+MODULE_AUTHOR("ANYKA");
+MODULE_DESCRIPTION("ak880x touchscreen driver");
+MODULE_LICENSE("GPL");
+
+
diff --git a/drivers/input/touchscreen/ak98adc_ts.c b/drivers/input/touchscreen/ak98adc_ts.c
new file mode 100644
index 00000000000..e3181abca18
--- /dev/null
+++ b/drivers/input/touchscreen/ak98adc_ts.c
@@ -0,0 +1,544 @@
+/*
+ * drivers/input/touchscreen/ak98_adc_ts.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <mach/regs-adc.h>
+#include <mach/gpio.h>
+#include <mach/ts.h>
+#include <mach/adc1.h>
+
+/* For ts.dev.id.version */
+#define AK98TSVERSION	0x0101
+#define MAX_10BIT		(0x3FF)
+#define AK98_GPIO_OUT_0		0
+#define AK98_GPIO_IN_0		1
+
+
+
+#define VARIANCE
+//#define ADC_DEBUG
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef ADC_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+/*
+ * Definitions & global arrays.
+ */
+
+static char *ak98ts_name = "AK98 ADC TouchScreen";
+
+
+struct TS_SAMPLE {
+	s32		x;
+	s32		y;
+};
+
+/*
+ * Per-touchscreen data.
+ */
+
+struct ak98ts {
+	struct input_dev *dev;
+	unsigned int state_pin;
+	unsigned int irq;
+	bool pendown;
+	bool first;
+	long xp;
+	long yp;
+	int count;
+	int shift;
+	char phys[32];
+};
+
+static struct ak98ts ts;
+
+/***********************************************************/
+
+#define PEROID_DELAY		3
+#define POLL_DELAY			10
+#define MAX_DELAY			50
+
+#define SLOW_DELTA			20
+
+
+/***********************************************************/
+
+#ifdef VARIANCE
+
+#define DEJITTER
+#define DEJITTER_2
+
+#define X_DELTA 		100  
+#define X_DELTA_MAX 	220  //max offset of X 
+#define Y_DELTA 		125  
+#define Y_DELTA_MAX 	300  //max offset of Y
+#define XY_DELTA 		(X_DELTA + Y_DELTA)
+#define TS_HZ 			15
+#define FAST_DELTA		(X_DELTA + Y_DELTA)
+
+#define MAX_SAMPLE 5
+#define SAMPLE_CNT 4
+
+enum 
+{
+	IX_XX=0,
+	IX_YY,
+	IX_LEN
+}TS_INDEX;
+
+//static void t_swap(void **a, void **b);
+//static s32 variance(struct input_dev *dev, s16 x, s16 y,  bool penup);
+static void variance(	struct TS_SAMPLE *samp, int cnt);
+
+
+
+#define NR_SAMPHISTLEN 4
+
+static const unsigned char weight [NR_SAMPHISTLEN - 1][NR_SAMPHISTLEN + 1] =
+{
+	/* The last element is pow2(SUM(0..3)) */
+	{ 5, 3, 0, 0, 3 },	/* When we have 2 samples ... */
+	{ 8, 5, 3, 0, 4 },	/* When we have 3 samples ... */
+	{ 6, 4, 3, 3, 4 },	/* When we have 4 samples ... */
+};
+
+struct dejitter2_info {	
+	int delta;
+	int x;
+	int y;
+	int nr;
+	int head;
+	struct TS_SAMPLE samp[NR_SAMPHISTLEN];
+};
+
+#define FAST_THRESHOLD 100
+static struct dejitter2_info djt2;
+static void average(struct dejitter2_info *djt, struct TS_SAMPLE *samp);
+static int dejitter(struct input_dev *dev, struct TS_SAMPLE *_samp, bool penup);
+
+
+#endif
+
+static int g_poll_delay = POLL_DELAY;
+#define ADC_MAIN_CLK	12 	/* 12MHz */
+#define ADC_CLK		( 4 * 1000000)	/*  4MHz */
+
+#define IS_PEN_DOWN(pin) (ak98_gpio_getpin(pin) ? 0:1)
+
+#define GET_XP() ( (REG32(AK98_X_COORDINATE) & 0xffc00) >> 10 )
+#define GET_XN() ( REG32(AK98_X_COORDINATE) & 0x3ff )
+#define GET_YP() ((REG32(AK98_Y_COORDINATE) & 0xffc00) >> 10 )
+#define GET_YN() ( REG32(AK98_Y_COORDINATE) & 0x3ff )
+
+static void touch_timer_handler(unsigned long data);
+static struct timer_list touch_timer = TIMER_INITIALIZER(touch_timer_handler, 0, 0);
+
+
+
+static void report_value(struct input_dev *dev, struct TS_SAMPLE *samp)
+{
+	PDEBUG("==%4d %4d \n", samp->x, samp->y);
+	
+	input_report_abs(dev, ABS_X, samp->x);
+	input_report_abs(dev, ABS_Y, samp->y);
+	input_report_abs(dev, ABS_PRESSURE, 1);
+	input_sync(dev);
+}
+
+
+static void set_pin(u32 pin)
+{
+	//as gpio
+	ak98_setpin_as_gpio(pin);
+	//input mode
+	ak98_gpio_cfgpin(pin, AK98_GPIO_DIR_INPUT);
+	//disable pulldown
+	ak98_gpio_pulldown(pin, AK98_PULLDOWN_DISABLE);
+	//active low
+	ak98_gpio_intpol(pin, AK98_GPIO_INT_LOWLEVEL);
+	
+}
+
+static void ak98_ts_sent_up_event(void )
+{
+	struct input_dev *input = ts.dev;		
+	
+	input_report_key(input, BTN_TOUCH, 0);
+	input_report_abs(input, ABS_PRESSURE, 0);
+	input_sync(input);
+}
+
+
+static void touch_timer_handler(unsigned long data)
+{
+	int i;
+	struct TS_SAMPLE samp[4];
+	
+	if (unlikely(!IS_PEN_DOWN(ts.state_pin)))
+	{
+		PDEBUG("pen up...\n");	
+		
+		dejitter(ts.dev, &(samp[0]), true);
+		ak98_ts_sent_up_event();
+		ts.pendown = false;
+		enable_irq(ts.irq);
+	}
+	else 
+	{
+		if (ts.pendown == false)
+		{
+			input_report_key(ts.dev, BTN_TOUCH, 1);	
+			//drop the first sample
+			ak98_power_ADC1(POWER_ON);		
+			ak98_power_ts(POWER_ON);
+			samp[0].x = GET_XP();
+			samp[0].y = GET_YP();
+			mdelay(2);
+			ak98_power_ts(POWER_OFF);
+			ak98_power_ADC1(POWER_OFF);	
+			mdelay(2);
+			ts.pendown = true;
+		}		
+		
+		for (i=0; i<SAMPLE_CNT; i++)
+		{
+			if (!IS_PEN_DOWN(ts.state_pin))
+				break;
+			ak98_power_ADC1(POWER_ON);		
+			ak98_power_ts(POWER_ON);
+			mdelay(2);
+			
+			samp[i].x = GET_XP();
+			samp[i].y = GET_YP();
+		
+		
+
+			PDEBUG("x=%d\ty=%d\n", xp,yp);
+			//printk("x=%d\ty=%d\t%d\n", xp,yp, g_poll_delay);
+			mdelay(2);
+			ak98_power_ts(POWER_OFF);
+			ak98_power_ADC1(POWER_OFF);	
+		}
+		if (i == SAMPLE_CNT || (i && ts.first == true))
+		{
+			if (ts.first == true)
+				ts.first = false;
+			variance(samp, i);	
+			samp[0].y = MAX_10BIT - samp[0].y;
+			PDEBUG("x = %4d\t y = %4d\n", samp[0].x, samp[0].y);
+			dejitter(ts.dev, &(samp[0]), false);			
+		}
+		
+		mod_timer(&touch_timer, jiffies+ msecs_to_jiffies(g_poll_delay));
+	}
+	
+}
+
+/* 
+ * touch screen interrupt handler.
+ */
+static irqreturn_t ak98ts_irqhandler(int irq, void *handle)
+{	
+	//PDEBUG("%s(): Entering..., irq=%d \n", __FUNCTION__, irq);		
+	if ( likely( IS_PEN_DOWN(ts.state_pin) ) ) 
+	{		
+		PDEBUG("pen down\n");
+				
+		g_poll_delay = POLL_DELAY;
+		disable_irq_nosync(ts.irq);	
+		ts.first = true;
+		//power_ts(POWER_ON);		
+		mod_timer(&(touch_timer), jiffies + msecs_to_jiffies(PEROID_DELAY));
+		
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * The functions for inserting/removing us as a module.
+ */
+
+static int __init ak98_ts_probe(struct platform_device *dev)
+{
+
+	struct ak98_ts_mach_info *info;
+
+	info = (struct ak98_ts_mach_info *)dev->dev.platform_data;
+	if (!info) {
+		printk(KERN_ERR "no platform data for ts\n");
+		return -EINVAL;
+	}
+
+	/* initialize hardware */
+	ak98_init_ADC1(info->sample_rate, info->wait_time);
+
+
+	/* Initialise input stuff */
+	memset(&ts, 0, sizeof(struct ak98ts));
+	ts.dev = input_allocate_device();
+	if (!ts.dev)
+		return -ENOMEM;
+
+	ts.dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+	input_set_abs_params(ts.dev, ABS_X, 0, MAX_10BIT, 0, 0);
+	input_set_abs_params(ts.dev, ABS_Y, 0, MAX_10BIT, 0, 0);
+	input_set_abs_params(ts.dev, ABS_PRESSURE, 0, MAX_10BIT, 0, 0);
+	
+	sprintf(ts.phys, "ts0");
+
+	//ts.dev->private = &ts;
+	ts.dev->name = ak98ts_name;
+	ts.dev->phys = ts.phys;
+	/*ts.dev->id.bustype = BUS_VIRTUAL;
+	ts.dev->id.vendor = 0xDEAD; 
+	ts.dev->id.product = 0xBEEF;
+	ts.dev->id.version = AK98TSVERSION;
+*/
+
+	ts.state_pin	= info->irqpin;//info->irqpin; //AK98_GPIO_90
+	ts.irq			= info->irq; //IRQ_GPIO_90
+	ts.pendown		= false;
+
+
+	//configure GPIO pin
+	set_pin(ts.state_pin);
+
+	PDEBUG("TS IRQ Number=%d, IRQ PIN=%d\n", info->irq, info->irqpin);
+
+
+	if (request_irq(info->irq, ak98ts_irqhandler, 0, "ak98adc_ts", 0)) {
+		printk(KERN_ERR "Could not allocate IRQ %d\n", info->irq);
+		return -EIO;
+	}
+
+#ifdef DEJITTER_2
+	djt2.head = 0;
+	djt2.delta = FAST_THRESHOLD;
+	djt2.nr = 0;
+#endif
+
+	printk(KERN_INFO "%s successfully loaded\n", ak98ts_name);
+
+	/* All went ok, so register to the input system */
+	return input_register_device(ts.dev);
+}
+
+static int ak98_ts_remove(struct platform_device *dev)
+{
+	struct ak98_ts_mach_info *info;
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	info = (struct ak98_ts_mach_info *)dev->dev.platform_data;
+	if (!info) {
+		printk(KERN_ERR "no platform data for ts\n");
+		return -EINVAL;
+	}
+
+	disable_irq(info->irq);
+	free_irq(info->irq, ts.dev);
+
+#if 0
+	if (adc_clock) {
+		clk_disable(adc_clock);
+		clk_put(adc_clock);
+		adc_clock = NULL;
+	}
+#endif
+
+	input_unregister_device(ts.dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int ak98_ts_suspend(struct platform_device *dev, pm_message_t state)
+{
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	return 0;
+}
+
+static int ak98_ts_resume(struct platform_device *dev)
+{
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+
+	return 0;
+}
+#endif
+
+
+static struct platform_driver ak98_ts_driver = {
+	.driver		= {
+		.name	= "ak98adc-ts",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= ak98_ts_probe,
+	.remove		= ak98_ts_remove,
+#ifdef	CONFIG_PM
+	.suspend	= ak98_ts_suspend,
+	.resume		= ak98_ts_resume,
+#endif
+};
+
+static int __init ak98_ts_init(void)
+{
+	printk("AK98 ADC Touchscreen Driver, (c) 2011 ANYKA\n");
+
+	return platform_driver_register(&ak98_ts_driver);
+}
+
+static void __exit ak98_ts_exit(void)
+{
+	platform_driver_unregister(&ak98_ts_driver);
+}
+
+
+static void variance(	struct TS_SAMPLE *samp, int cnt)
+{
+	int i, w[SAMPLE_CNT] = {0}, aver_x = 0, aver_y = 0, kmax;
+	int sum_x = 0, sum_y = 0;
+
+		
+	for (i = 0; i < cnt; i++)
+	{
+		sum_x += samp[i].x;
+		sum_y += samp[i].y;
+	}
+	aver_x = sum_x / cnt;
+	aver_y = sum_y / cnt;
+
+	if (cnt < 3)
+	{
+		samp[0].x = aver_x;
+		samp[0].y = aver_y;
+		return;
+	}
+	
+	w[0] = abs(samp[0].x - aver_x) + abs(samp[0].y - aver_y);	
+	kmax = 0;
+	
+	for (i = 1; i < cnt; i++)
+	{
+		w[i] = abs(samp[i].x - aver_x) + abs(samp[i].y - aver_y);
+		if (w[i] > w[kmax])
+		{
+			kmax = i;
+		}
+	}
+	samp[0].x = (sum_x - samp[kmax].x ) / (cnt - 1);
+	samp[0].y = (sum_y - samp[kmax].y ) / (cnt - 1);
+	
+}
+
+static void average(struct dejitter2_info *djt, struct TS_SAMPLE *samp)
+{
+	const unsigned char *w;
+	int sn = djt->head;
+	int i, x = 0, y = 0;
+//	unsigned int p = 0;
+
+        w = weight [djt->nr - 2];
+
+	for (i = 0; i < djt->nr; i++) 
+	{
+		sn = (sn - 1) & (NR_SAMPHISTLEN - 1);		
+		x += djt->samp [sn].x * w [i];
+		y += djt->samp [sn].y * w [i];
+	//	p += djt->samp [sn].p * w [i];
+		
+	}
+
+	//printk("%4d\t%4d\t%d\n", x, y, djt->nr);
+	samp->x = x >> w [NR_SAMPHISTLEN];
+	samp->y = y >> w [NR_SAMPHISTLEN];
+	//samp->pressure = p >> w [NR_SAMPHISTLEN];
+
+	PDEBUG("DEJITTER2----------------> %d %d %d\n",samp->x, samp->y, samp->pressure);
+}
+
+static int dejitter(struct input_dev *dev, struct TS_SAMPLE *_samp, bool penup)
+{	
+	static struct TS_SAMPLE temp;	
+
+	if (penup == true)
+	{				
+		djt2.head = 0;
+		djt2.nr = 0;;
+		return 1;
+	}
+
+	/* If the pen moves too fast, reset the backlog. */
+	if (djt2.nr)
+	{
+		int prev = (djt2.head - 1) & (NR_SAMPHISTLEN - 1);
+		if (abs(_samp->x - djt2.samp[prev].x) + abs(_samp->y - djt2.samp[prev].y) > djt2.delta)
+			djt2.nr = 0;
+	}
+
+	djt2.samp[djt2.head] = *_samp;
+	djt2.head = (djt2.head + 1) & (NR_SAMPHISTLEN - 1);
+	
+	if (djt2.nr < NR_SAMPHISTLEN)
+		++djt2.nr;
+	
+	if (djt2.nr == 1)
+	{
+		temp = *_samp;
+	}
+	else
+	{
+		average(&djt2, &temp);
+	}		
+
+	report_value(dev, &temp);
+	return 1;
+}
+
+
+
+module_init(ak98_ts_init);
+module_exit(ak98_ts_exit);
+
+MODULE_AUTHOR("ANYKA");
+MODULE_DESCRIPTION("ak98 ADC touchscreen driver");
+MODULE_LICENSE("GPL");
+
+
diff --git a/drivers/input/touchscreen/ar7643.c b/drivers/input/touchscreen/ar7643.c
new file mode 100755
index 00000000000..8a4c718dd9f
--- /dev/null
+++ b/drivers/input/touchscreen/ar7643.c
@@ -0,0 +1,574 @@
+/*
+* drivers/input/touchscreen/ar7643_ts.c
+* Copyright (C) 2011 ANYKA
+* Author: Zhou Wenyong
+*
+* AR7643 TouchScreen Driver for ak98
+*/
+
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <mach/gpio.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+
+
+//#define AR7643_DEBUG
+#define DEJITTER
+
+#define AR7642TSVERSION 0x01
+
+
+/* definitons of pin  */
+#define PIN_DOUT		AK98_GPIO_0 	
+#define PIN_CLK			AK98_GPIO_1
+#define PIN_CS			AK98_GPIO_2
+#define PIN_DIN			AK98_GPIO_3
+#define PIN_INT			AK98_GPIO_19
+#define AR7643_IRQ		IRQ_GPIO_19
+
+#define POLL_DELAY			5
+#define PEROID_DELAY		1
+
+#define	MAX_12BIT			(0xFFF)
+#define SAMPLE_CNT		4
+
+/* definitions of control byte */
+#define START_BIT		(1<<7)
+#define ADDR_X			(1<<4)
+#define ADDR_Y			(5<<4)
+
+#define GET_X           0xD0
+#define GET_Y			0x90
+#define CS_KEEP_LOW     1
+
+enum
+{
+	DOUT_BIT = 0,
+	CLK_BIT = 1,
+	CS_BIT = 2,
+	DIN_BIT = 3,
+	INT_BIT = 18
+};
+
+
+#define SET_PIN_HIGH(pin)	ak98_gpio_setpin(pin, AK98_GPIO_HIGH)
+#define SET_PIN_LOW(pin)	ak98_gpio_setpin(pin, AK98_GPIO_LOW)
+
+#define READ_PIN(pin)		ak98_gpio_getpin(pin)
+#define IS_PEN_DOWN(pin) (ak98_gpio_getpin(pin) ? 0:1)
+static struct workqueue_struct *ar7643_wq;
+
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef AR7643_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+
+/*
+ * Definitions & global arrays.
+ */
+
+static char *ar7643_name = "AR7643 SPI TouchScreen for AK98";
+//static spinlock_t ar7643_lock;
+static int ar7643_send_byte(u8 command);
+
+
+struct AR7643_SAMPLE {
+	s32		x;
+	s32		y;
+};
+
+/*
+ * Per-touchscreen data.
+ */
+
+struct ar7643 {
+	struct input_dev *dev;
+	bool pendown;
+	bool first;
+	long xp;
+	long yp;
+	int count;
+	int shift;
+	char phys[32];
+	u32 speed_hz;
+	struct spi_device *spi;
+	struct delayed_work	work;
+};
+static void ar7643_work(struct work_struct *work);//unsigned long data);
+static void get_xy(struct AR7643_SAMPLE *samp);
+
+
+
+static struct ar7643 ts;
+
+
+
+#ifdef DEJITTER
+
+#define NR_SAMPHISTLEN 4
+
+static const unsigned char weight [NR_SAMPHISTLEN - 1][NR_SAMPHISTLEN + 1] =
+{
+	/* The last element is pow2(SUM(0..3)) */
+	{ 5, 3, 0, 0, 3 },	/* When we have 2 samples ... */
+	{ 8, 5, 3, 0, 4 },	/* When we have 3 samples ... */
+	{ 6, 4, 3, 3, 4 },	/* When we have 4 samples ... */
+};
+
+struct dejitter_info {	
+	int delta;
+	int x;
+	int y;
+	int nr;
+	int head;
+	struct AR7643_SAMPLE samp[NR_SAMPHISTLEN];
+};
+
+#define FAST_THRESHOLD 100
+static struct dejitter_info djt;
+static void average(struct dejitter_info *djt, struct AR7643_SAMPLE *samp);
+static int dejitter(struct input_dev *dev, struct AR7643_SAMPLE *_samp, bool penup);
+
+
+#endif
+
+
+static void report_value(struct input_dev *dev, struct AR7643_SAMPLE *samp)
+{
+	PDEBUG("==%4d %4d \n", samp->x, samp->y);
+	
+	input_report_abs(dev, ABS_X, samp->x);
+	input_report_abs(dev, ABS_Y, samp->y);
+	input_report_abs(dev, ABS_PRESSURE, 1);
+	input_sync(dev);
+}
+
+static void pin_init(void)
+{
+	
+	ak98_setpin_as_gpio(PIN_INT);
+	ak98_gpio_pullup(PIN_INT, AK98_PULLUP_ENABLE);
+	ak98_gpio_pulldown(PIN_INT, AK98_PULLDOWN_DISABLE);
+	ak98_gpio_cfgpin(PIN_INT, AK98_GPIO_DIR_INPUT);
+	ak98_gpio_intpol(PIN_INT, AK98_GPIO_INT_LOWLEVEL);
+
+}
+
+static int ar7643_read_12bit(u8 comand, int *v)
+{
+	struct spi_message m;
+	struct spi_transfer	xfer;
+	int status;
+	int a=0;
+	
+	u8 cmd[3] = {0};
+	u8 buff[3] = {0};
+	cmd[0] = comand;
+	
+	spi_message_init(&m);	
+
+	xfer.tx_buf = cmd;
+	xfer.rx_buf = buff;
+	xfer.len = sizeof(cmd);
+	xfer.bits_per_word = 8;
+	xfer.speed_hz = ts.speed_hz;
+	xfer.cs_change = CS_KEEP_LOW ? 0:1; // 1: the #CS signal is LOW until all the data transmission has been finished
+	                                    // 0: the #CS signal is HIGH after a transmission of 8 bits data
+	                         
+	spi_message_add_tail(&xfer, &m);
+
+	status = spi_sync(ts.spi, &m);
+
+	a = buff[1]&0x7f;
+	a = ((a<<5) | ((buff[2]>>3)&0x1f));
+	
+	*v = a;	
+	return status;
+}
+
+static int get_pos(int *x, int *y)
+{
+	//int  count;
+
+	ar7643_read_12bit(GET_X, x);
+	ar7643_read_12bit(GET_Y, y);
+
+	//printk("x: %d  y: %d\n", *x, *y);
+	
+    return 0;
+}
+
+
+static void get_xy(struct AR7643_SAMPLE *samp)
+{
+	if (ts.first == true);
+	{
+		udelay(100);
+		get_pos(&(samp->x), &(samp->y));
+		ts.first = false;
+	}
+		
+	get_pos(&(samp->x), &(samp->y));
+	
+}
+
+
+
+static void ar7643_sent_up_event(void )
+{
+	struct input_dev *input = ts.dev;		
+	
+	input_report_key(input, BTN_TOUCH, 0);
+	input_report_abs(input, ABS_PRESSURE, 0);
+	input_sync(input);
+}
+
+/* 
+ * touch screen interrupt handler.
+ */
+static irqreturn_t ar7643_irqhandler(int irq, void *handle)
+{		
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	if ( likely( IS_PEN_DOWN(PIN_INT) ) ) 
+	{		
+		PDEBUG("pen down\n");		
+		disable_irq_nosync(AR7643_IRQ);		
+		ts.first = true;
+		queue_delayed_work(ar7643_wq, &(ts.work),
+				      msecs_to_jiffies(PEROID_DELAY));
+		//mod_timer(&(touch_timer), jiffies + msecs_to_jiffies(PEROID_DELAY));		
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void variance(	struct AR7643_SAMPLE *samp, int cnt)
+{
+	int i, w[SAMPLE_CNT] = {0}, aver_x = 0, aver_y = 0, kmax;
+	int sum_x = 0, sum_y = 0;
+
+		
+	for (i = 0; i < cnt; i++)
+	{
+		sum_x += samp[i].x;
+		sum_y += samp[i].y;
+	}
+	aver_x = sum_x / cnt;
+	aver_y = sum_y / cnt;
+
+	if (cnt < 3)
+	{
+		samp[0].x = aver_x;
+		samp[0].y = aver_y;
+		return;
+	}
+	
+	w[0] = abs(samp[0].x - aver_x) + abs(samp[0].y - aver_y);	
+	kmax = 0;
+	
+	for (i = 1; i < cnt; i++)
+	{
+		w[i] = abs(samp[i].x - aver_x) + abs(samp[i].y - aver_y);
+		if (w[i] > w[kmax])
+		{
+			kmax = i;
+		}
+	}
+	samp[0].x = (sum_x - samp[kmax].x ) / (cnt - 1);
+	samp[0].y = (sum_y - samp[kmax].y ) / (cnt - 1);
+	
+}
+
+static void ar7643_work(struct work_struct *work)//unsigned long data)
+{		
+	struct AR7643_SAMPLE samp[5];
+	int  i;
+	//static int flg = 0;
+	
+	if (unlikely(!IS_PEN_DOWN(PIN_INT)))
+	{
+		PDEBUG("pen up...\n");	
+		dejitter(ts.dev, &(samp[0]), true);
+		ar7643_sent_up_event();
+		ts.pendown = false;
+		enable_irq(AR7643_IRQ);
+		
+	}
+	else 
+	{
+		if (ts.pendown == false)
+		{
+			input_report_key(ts.dev, BTN_TOUCH, 1);	
+			
+			ts.pendown = true;
+		}		
+		
+	
+		for(i=0;i<SAMPLE_CNT;i++)
+		{
+			if (!IS_PEN_DOWN(PIN_INT))
+				break;
+			get_xy(&(samp[i]));				
+		}
+			
+		if (i == SAMPLE_CNT || (i && ts.first == true))
+		{
+			if (ts.first == true)
+				ts.first = false;
+			variance(samp, i);	
+			PDEBUG("x = %4d\t y = %4d\n", samp[0].x, samp[0].y);
+			dejitter(ts.dev, &(samp[0]), false);			
+		}
+
+		queue_delayed_work(ar7643_wq, &(ts.work),
+				      msecs_to_jiffies(POLL_DELAY));
+		//mod_timer(&touch_timer, jiffies+ msecs_to_jiffies(POLL_DELAY));
+	}
+	
+}
+
+
+static int ar7643_send_byte(u8 command)
+{
+	struct spi_message m;
+	struct spi_transfer	xfer;
+	int status;
+
+	u8 buff = command;
+
+	
+	spi_message_init(&m);
+
+	xfer.tx_buf = &buff;
+	xfer.rx_buf = NULL;
+	xfer.len = sizeof(buff);
+	xfer.bits_per_word = 8;
+	xfer.speed_hz = ts.speed_hz;
+
+	spi_message_add_tail(&xfer, &m);
+
+	status = spi_sync(ts.spi, &m);
+
+	
+	return status;
+}
+
+/*
+ * The functions for inserting/removing us as a module.
+ */
+
+static int __init ar7643_probe(struct spi_device *spi)
+{	
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	/* initialize hardware */
+	pin_init();
+
+	/* Initialise input stuff */
+	memset(&ts, 0, sizeof(struct ar7643));
+	ts.dev = input_allocate_device();
+	if (!ts.dev)
+		return -ENOMEM;
+	
+	ts.dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+	input_set_abs_params(ts.dev, ABS_X, 0, MAX_12BIT, 0, 0);
+	input_set_abs_params(ts.dev, ABS_Y, 0, MAX_12BIT, 0, 0);
+	input_set_abs_params(ts.dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);
+	
+	sprintf(ts.phys, "ar7643-spi");
+	
+	ts.dev->name = ar7643_name;
+	ts.dev->phys = ts.phys;
+	ts.speed_hz = spi->max_speed_hz;	
+	ts.pendown	= false;
+	ts.spi = spi;
+
+	INIT_DELAYED_WORK(&(ts.work), ar7643_work);	
+
+	if (request_irq(AR7643_IRQ, ar7643_irqhandler, 0, "ar7643_spi", 0)) {
+		printk(KERN_ERR "Could not allocate IRQ %d\n", AR7643_IRQ);
+		return -EIO;
+	}
+
+	#ifdef DEJITTER
+	djt.head = 0;
+	djt.delta = FAST_THRESHOLD;
+	djt.nr = 0;
+	#endif
+
+	//power down and enable PENIRQ	
+	ar7643_send_byte(0x80);
+	
+	printk(KERN_INFO "%s successfully loaded\n", ar7643_name);
+
+	/* All went ok, so register to the input system */
+	return input_register_device(ts.dev);
+}
+
+static int ar7643_remove(struct spi_device *spi)
+{
+	
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	
+
+	disable_irq(AR7643_IRQ);
+	free_irq(AR7643_IRQ, ts.dev);
+
+
+	input_unregister_device(ts.dev);
+
+	return 0;
+}
+
+#ifdef DEJITTER
+static void average(struct dejitter_info *djt, struct AR7643_SAMPLE *samp)
+{
+	const unsigned char *w;
+	int sn = djt->head;
+	int i, x = 0, y = 0;
+//	unsigned int p = 0;
+
+        w = weight [djt->nr - 2];
+
+	for (i = 0; i < djt->nr; i++) 
+	{
+		sn = (sn - 1) & (NR_SAMPHISTLEN - 1);		
+		x += djt->samp [sn].x * w [i];
+		y += djt->samp [sn].y * w [i];
+	//	p += djt->samp [sn].p * w [i];
+		
+	}
+
+	//printk("%4d\t%4d\t%d\n", x, y, djt->nr);
+	samp->x = x >> w [NR_SAMPHISTLEN];
+	samp->y = y >> w [NR_SAMPHISTLEN];
+	//samp->pressure = p >> w [NR_SAMPHISTLEN];
+
+	//PDEBUG("DEJITTER----------------> %d %d %d\n",samp->x, samp->y, 0);
+}
+
+static int dejitter(struct input_dev *dev, struct AR7643_SAMPLE *_samp, bool penup)
+{	
+	static struct AR7643_SAMPLE temp;	
+
+	if (penup == true)
+	{				
+		djt.head = 0;
+		djt.nr = 0;;
+		return 1;
+	}
+
+	/* If the pen moves too fast, reset the backlog. */
+	if (djt.nr)
+	{
+		int prev = (djt.head - 1) & (NR_SAMPHISTLEN - 1);
+		if (abs(_samp->x - djt.samp[prev].x) + abs(_samp->y - djt.samp[prev].y) > djt.delta)
+			djt.nr = 0;
+	}
+
+	djt.samp[djt.head] = *_samp;
+	djt.head = (djt.head + 1) & (NR_SAMPHISTLEN - 1);
+	
+	if (djt.nr < NR_SAMPHISTLEN)
+		++djt.nr;
+	
+	if (djt.nr == 1)
+	{
+		temp = *_samp;
+	}
+	else
+	{
+		average(&djt, &temp);
+	}		
+
+	report_value(dev, &temp);
+	return 1;
+}
+
+#endif
+
+#ifdef CONFIG_PM
+
+static int ar7643_suspend(struct spi_device *spi, pm_message_t state)
+{
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+	return 0;
+}
+
+static int ar7643_resume(struct spi_device *spi)
+{
+	PDEBUG("%s(): Entering...\n", __FUNCTION__);
+
+	return 0;
+}
+#endif
+
+static struct spi_driver ar7643_driver = {
+	.driver		= {
+		.name	= "ar7643-spi",
+		.bus	= &spi_bus_type,
+		.owner	= THIS_MODULE,
+	},
+	.probe		= ar7643_probe,
+	.remove		= ar7643_remove,
+#ifdef	CONFIG_PM
+	.suspend	= ar7643_suspend,
+	.resume		= ar7643_resume,
+#endif
+};
+
+static int __init ar7643_init(void)
+{
+	printk("AR7643 SPI Touchscreen Driver for AK98, (c) 2011 ANYKA\n");
+	ar7643_wq = create_singlethread_workqueue("ar7643_wq");
+	if (!ar7643_wq)
+		return -ENOMEM;
+	return spi_register_driver(&ar7643_driver);
+}
+
+static void __exit ar7643_exit(void)
+{	
+	if (ar7643_wq)
+			destroy_workqueue(ar7643_wq);
+
+	spi_unregister_driver(&ar7643_driver);
+}
+
+
+module_init(ar7643_init);
+module_exit(ar7643_exit);
+
+MODULE_AUTHOR("Anyka,Ltd");
+MODULE_DESCRIPTION("AR7643 SPI TouchScreen Driver");
+MODULE_LICENSE("GPL");
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/drivers/input/touchscreen/ar7643_ts.c b/drivers/input/touchscreen/ar7643_ts.c
new file mode 100644
index 00000000000..cbda7cb1000
--- /dev/null
+++ b/drivers/input/touchscreen/ar7643_ts.c
@@ -0,0 +1,557 @@
+/*

+* drivers/input/touchscreen/ar7643_ts.c

+* Copyright (C) 2011 ANYKA

+* Author: Zhou Wenyong

+*

+* AR7643 TouchScreen Driver for ak98

+*/

+

+

+#include <linux/platform_device.h>

+#include <linux/module.h>

+#include <linux/slab.h>

+#include <linux/input.h>

+#include <linux/interrupt.h>

+#include <linux/io.h>

+#include <mach/gpio.h>

+#include <linux/delay.h>

+

+

+//#define AR7643_DEBUG

+#define DEJITTER

+

+#define AR7642TSVERSION 0x01

+

+

+/* definitons of pin  */

+#define PIN_DOUT		AK98_GPIO_0 	

+#define PIN_CLK			AK98_GPIO_1

+#define PIN_CS			AK98_GPIO_2

+#define PIN_DIN			AK98_GPIO_3

+#define PIN_INT			AK98_GPIO_19

+#define AR7643_IRQ		IRQ_GPIO_19

+

+#define POLL_DELAY			15

+#define PEROID_DELAY		2

+

+#define	MAX_12BIT			(0xFFF)

+#define SAMPLE_CNT		4

+

+/* definitions of control byte */

+#define START_BIT		(1<<7)

+#define ADDR_X			(1<<4)

+#define ADDR_Y			(5<<4)

+

+#define GET_X           0xD0

+#define GET_Y			0x90

+

+

+enum

+{

+	DOUT_BIT = 0,

+	CLK_BIT = 1,

+	CS_BIT = 2,

+	DIN_BIT = 3,

+	INT_BIT = 18

+};

+

+

+#define SET_PIN_HIGH(pin)	ak98_gpio_setpin(pin, AK98_GPIO_HIGH)

+#define SET_PIN_LOW(pin)	ak98_gpio_setpin(pin, AK98_GPIO_LOW)

+

+#define READ_PIN(pin)		ak98_gpio_getpin(pin)

+#define IS_PEN_DOWN(pin) (ak98_gpio_getpin(pin) ? 0:1)

+

+

+#undef PDEBUG           /* undef it, just in case */

+#ifdef AR7643_DEBUG

+# ifdef __KERNEL__

+/* This one if debugging is on, and kernel space */

+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)

+# else

+/* This one for user space */

+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)

+# endif

+#else

+# define PDEBUG(fmt, args...) /* not debugging: nothing */

+#endif

+

+

+/*

+ * Definitions & global arrays.

+ */

+

+static char *ar7643ts_name = "AR7643 ADC TouchScreen for AK98";

+//static spinlock_t ar7643_lock;

+

+

+struct AR7643TS_SAMPLE {

+	s32		x;

+	s32		y;

+};

+

+/*

+ * Per-touchscreen data.

+ */

+

+struct ar7643ts {

+	struct input_dev *dev;

+	bool pendown;

+	bool first;

+	long xp;

+	long yp;

+	int count;

+	int shift;

+	char phys[32];

+};

+static void touch_timer_handler(unsigned long data);

+static void get_xy(struct AR7643TS_SAMPLE *samp);

+

+static struct timer_list touch_timer = TIMER_INITIALIZER(touch_timer_handler, 0, 0);

+

+

+static struct ar7643ts ts;

+

+

+

+#ifdef DEJITTER

+

+#define NR_SAMPHISTLEN 4

+

+static const unsigned char weight [NR_SAMPHISTLEN - 1][NR_SAMPHISTLEN + 1] =

+{

+	/* The last element is pow2(SUM(0..3)) */

+	{ 5, 3, 0, 0, 3 },	/* When we have 2 samples ... */

+	{ 8, 5, 3, 0, 4 },	/* When we have 3 samples ... */

+	{ 6, 4, 3, 3, 4 },	/* When we have 4 samples ... */

+};

+

+struct dejitter_info {	

+	int delta;

+	int x;

+	int y;

+	int nr;

+	int head;

+	struct AR7643TS_SAMPLE samp[NR_SAMPHISTLEN];

+};

+

+#define FAST_THRESHOLD 100

+static struct dejitter_info djt;

+static void average(struct dejitter_info *djt, struct AR7643TS_SAMPLE *samp);

+static int dejitter(struct input_dev *dev, struct AR7643TS_SAMPLE *_samp, bool penup);

+

+

+#endif

+

+

+static void report_value(struct input_dev *dev, struct AR7643TS_SAMPLE *samp)

+{

+	PDEBUG("==%4d %4d \n", samp->x, samp->y);

+	

+	input_report_abs(dev, ABS_X, samp->x);

+	input_report_abs(dev, ABS_Y, samp->y);

+	input_report_abs(dev, ABS_PRESSURE, 1);

+	input_sync(dev);

+}

+

+static void pin_init(void)

+{

+

+	ak98_setpin_as_gpio(PIN_DOUT);

+	ak98_gpio_pulldown(PIN_DOUT, AK98_PULLDOWN_DISABLE);

+	ak98_gpio_cfgpin(PIN_DOUT, AK98_GPIO_DIR_OUTPUT);

+	

+	ak98_setpin_as_gpio(PIN_CLK);

+	ak98_gpio_pullup(PIN_CLK, AK98_PULLUP_DISABLE);

+	ak98_gpio_cfgpin(PIN_CLK, AK98_GPIO_DIR_OUTPUT);

+	

+	ak98_setpin_as_gpio(PIN_CS);

+	ak98_gpio_pullup(PIN_CS, AK98_PULLUP_DISABLE);

+	ak98_gpio_cfgpin(PIN_CS, AK98_GPIO_DIR_OUTPUT);

+

+		

+	ak98_setpin_as_gpio(PIN_DIN);

+	ak98_gpio_pullup(PIN_DIN, AK98_PULLUP_DISABLE);

+	ak98_gpio_cfgpin(PIN_DIN, AK98_GPIO_DIR_INPUT);

+

+		

+	ak98_setpin_as_gpio(PIN_INT);

+	ak98_gpio_pullup(PIN_INT, AK98_PULLUP_ENABLE);

+	ak98_gpio_pulldown(PIN_INT, AK98_PULLDOWN_DISABLE);

+	ak98_gpio_cfgpin(PIN_INT, AK98_GPIO_DIR_INPUT);

+	ak98_gpio_intpol(PIN_INT, AK98_GPIO_INT_LOWLEVEL);

+

+}

+

+static void start(void)

+{

+	SET_PIN_LOW(PIN_CLK);

+	SET_PIN_HIGH(PIN_CS);

+	SET_PIN_HIGH(PIN_DOUT);

+	SET_PIN_HIGH(PIN_CLK);

+	SET_PIN_LOW(PIN_CS);

+}

+

+//write one byte

+static void send_cmd_to_ar7643(unsigned char num) 

+{

+    unsigned char count=0;

+

+	SET_PIN_LOW(PIN_DOUT);

+	SET_PIN_LOW(PIN_CLK);

+

+	//ÏÈ°ÑÊý¾Ý×¼±¸ºÃ£¬¼´ÉèºÃµçƽ£¬ÔÙÀ­¸ßCLKÏߣ¬Í¨Öª´Ó±¸¹ýÀ´È¡Êý¡£

+	for(count=0;count<8;count++)

+	{

+		if((num&0x80)==0x80)   

+			SET_PIN_HIGH(PIN_DOUT);

+		else 

+			SET_PIN_LOW(PIN_DOUT);

+

+		num<<=1;

+		SET_PIN_LOW(PIN_CLK);

+		SET_PIN_HIGH(PIN_CLK);

+	}

+    mdelay(1);

+}

+

+static int get_pos(int cmd)

+{

+	int x = 0, count;

+

+	send_cmd_to_ar7643(cmd);

+	SET_PIN_HIGH(PIN_CLK);

+	SET_PIN_LOW(PIN_CLK);

+

+	// ÏȲúÉúϽµÑØ£¬ÈôÓÉ豸׼±¸ºÃÊý¾Ý£¬ÔÙ¶ÁÈ¡µçƽ¡£

+    for(count=0;count<12;count++)

+    {

+        x<<=1;

+		SET_PIN_HIGH(PIN_CLK);

+        SET_PIN_LOW(PIN_CLK);

+        if(READ_PIN(PIN_DIN)) x++;

+    }

+	

+    return (x);

+}

+

+

+static void get_xy(struct AR7643TS_SAMPLE *samp)

+{

+	//assert(samp);

+

+	start();

+	if (ts.first == true);

+		mdelay(1);

+	samp->x = get_pos(GET_X);

+	samp->y = get_pos(GET_Y);

+

+	SET_PIN_HIGH(PIN_CS);	

+}

+

+

+

+static void ar7643ts_sent_up_event(void )

+{

+	struct input_dev *input = ts.dev;		

+	

+	input_report_key(input, BTN_TOUCH, 0);

+	input_report_abs(input, ABS_PRESSURE, 0);

+	input_sync(input);

+}

+

+/* 

+ * touch screen interrupt handler.

+ */

+static irqreturn_t ar7643ts_irqhandler(int irq, void *handle)

+{		

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+	if ( likely( IS_PEN_DOWN(PIN_INT) ) ) 

+	{		

+		PDEBUG("pen down\n");		

+		disable_irq_nosync(AR7643_IRQ);		

+		ts.first = true;

+		mod_timer(&(touch_timer), jiffies + msecs_to_jiffies(PEROID_DELAY));		

+	}

+

+	return IRQ_HANDLED;

+}

+

+static void variance(	struct AR7643TS_SAMPLE *samp, int cnt)

+{

+	int i, w[SAMPLE_CNT] = {0}, aver_x = 0, aver_y = 0, kmax;

+	int sum_x = 0, sum_y = 0;

+

+		

+	for (i = 0; i < cnt; i++)

+	{

+		sum_x += samp[i].x;

+		sum_y += samp[i].y;

+	}

+	aver_x = sum_x / cnt;

+	aver_y = sum_y / cnt;

+

+	if (cnt < 3)

+	{

+		samp[0].x = aver_x;

+		samp[0].y = aver_y;

+		return;

+	}

+	

+	w[0] = abs(samp[0].x - aver_x) + abs(samp[0].y - aver_y);	

+	kmax = 0;

+	

+	for (i = 1; i < cnt; i++)

+	{

+		w[i] = abs(samp[i].x - aver_x) + abs(samp[i].y - aver_y);

+		if (w[i] > w[kmax])

+		{

+			kmax = i;

+		}

+	}

+	samp[0].x = (sum_x - samp[kmax].x ) / (cnt - 1);

+	samp[0].y = (sum_y - samp[kmax].y ) / (cnt - 1);

+	

+}

+

+static void touch_timer_handler(unsigned long data)

+{		

+	struct AR7643TS_SAMPLE samp[5];

+	int  i;

+	

+	if (unlikely(!IS_PEN_DOWN(PIN_INT)))

+	{

+		PDEBUG("pen up...\n");	

+		dejitter(ts.dev, &(samp[0]), true);

+		ar7643ts_sent_up_event();

+		ts.pendown = false;

+		enable_irq(AR7643_IRQ);

+	}

+	else 

+	{

+		if (ts.pendown == false)

+		{

+			input_report_key(ts.dev, BTN_TOUCH, 1);	

+			

+			ts.pendown = true;

+		}		

+		

+	

+		for(i=0;i<SAMPLE_CNT;i++)

+		{

+			if (!IS_PEN_DOWN(PIN_INT))

+				break;

+			get_xy(&(samp[i]));				

+		}

+			

+		if (i == SAMPLE_CNT || (i && ts.first == true))

+		{

+			if (ts.first == true)

+				ts.first = false;

+			variance(samp, i);	

+			PDEBUG("x = %4d\t y = %4d\n", samp[0].x, samp[0].y);

+			dejitter(ts.dev, &(samp[0]), false);			

+		}

+

+

+		mod_timer(&touch_timer, jiffies+ msecs_to_jiffies(POLL_DELAY));

+	}

+	

+}

+

+/*

+ * The functions for inserting/removing us as a module.

+ */

+

+static int __init ar7643_ts_probe(struct platform_device *dev)

+{

+

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+	/* initialize hardware */

+	pin_init();

+

+	/* Initialise input stuff */

+	memset(&ts, 0, sizeof(struct ar7643ts));

+	ts.dev = input_allocate_device();

+	if (!ts.dev)

+		return -ENOMEM;

+	

+	ts.dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);

+	ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);

+

+	input_set_abs_params(ts.dev, ABS_X, 0, MAX_12BIT, 0, 0);

+	input_set_abs_params(ts.dev, ABS_Y, 0, MAX_12BIT, 0, 0);

+	input_set_abs_params(ts.dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);

+	

+	sprintf(ts.phys, "ar7643ts0");

+	

+	ts.dev->name = ar7643ts_name;

+	ts.dev->phys = ts.phys;

+	

+	PDEBUG("0x%x\n", ts.dev->dev.class);

+	PDEBUG("%s\n", ts.dev->dev.class->name);

+

+	

+	ts.pendown	= false;

+

+	if (request_irq(AR7643_IRQ, ar7643ts_irqhandler, 0, "ar7643adc_ts", 0)) {

+		printk(KERN_ERR "Could not allocate IRQ %d\n", AR7643_IRQ);

+		return -EIO;

+	}

+

+	#ifdef DEJITTER

+	djt.head = 0;

+	djt.delta = FAST_THRESHOLD;

+	djt.nr = 0;

+	#endif

+

+	printk(KERN_INFO "%s successfully loaded\n", ar7643ts_name);

+

+	/* All went ok, so register to the input system */

+	return input_register_device(ts.dev);

+}

+

+static int ar7643_ts_remove(struct platform_device *dev)

+{

+	

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+	

+

+	disable_irq(AR7643_IRQ);

+	free_irq(AR7643_IRQ, ts.dev);

+

+

+	input_unregister_device(ts.dev);

+

+	return 0;

+}

+

+#ifdef DEJITTER

+static void average(struct dejitter_info *djt, struct AR7643TS_SAMPLE *samp)

+{

+	const unsigned char *w;

+	int sn = djt->head;

+	int i, x = 0, y = 0;

+//	unsigned int p = 0;

+

+        w = weight [djt->nr - 2];

+

+	for (i = 0; i < djt->nr; i++) 

+	{

+		sn = (sn - 1) & (NR_SAMPHISTLEN - 1);		

+		x += djt->samp [sn].x * w [i];

+		y += djt->samp [sn].y * w [i];

+	//	p += djt->samp [sn].p * w [i];

+		

+	}

+

+	//printk("%4d\t%4d\t%d\n", x, y, djt->nr);

+	samp->x = x >> w [NR_SAMPHISTLEN];

+	samp->y = y >> w [NR_SAMPHISTLEN];

+	//samp->pressure = p >> w [NR_SAMPHISTLEN];

+

+	//PDEBUG("DEJITTER----------------> %d %d %d\n",samp->x, samp->y, 0);

+}

+

+static int dejitter(struct input_dev *dev, struct AR7643TS_SAMPLE *_samp, bool penup)

+{	

+	static struct AR7643TS_SAMPLE temp;	

+

+	if (penup == true)

+	{				

+		djt.head = 0;

+		djt.nr = 0;;

+		return 1;

+	}

+

+	/* If the pen moves too fast, reset the backlog. */

+	if (djt.nr)

+	{

+		int prev = (djt.head - 1) & (NR_SAMPHISTLEN - 1);

+		if (abs(_samp->x - djt.samp[prev].x) + abs(_samp->y - djt.samp[prev].y) > djt.delta)

+			djt.nr = 0;

+	}

+

+	djt.samp[djt.head] = *_samp;

+	djt.head = (djt.head + 1) & (NR_SAMPHISTLEN - 1);

+	

+	if (djt.nr < NR_SAMPHISTLEN)

+		++djt.nr;

+	

+	if (djt.nr == 1)

+	{

+		temp = *_samp;

+	}

+	else

+	{

+		average(&djt, &temp);

+	}		

+

+	report_value(dev, &temp);

+	return 1;

+}

+

+#endif

+

+#ifdef CONFIG_PM

+

+static int ar7643_ts_suspend(struct platform_device *dev, pm_message_t state)

+{

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+	return 0;

+}

+

+static int ar7643_ts_resume(struct platform_device *dev)

+{

+	PDEBUG("%s(): Entering...\n", __FUNCTION__);

+

+	return 0;

+}

+#endif

+

+static struct platform_driver ar7643_ts_driver = {

+	.driver		= {

+		.name	= "ar7643-ts",

+		.owner	= THIS_MODULE,

+	},

+	.probe		= ar7643_ts_probe,

+	.remove		= ar7643_ts_remove,

+#ifdef	CONFIG_PM

+	.suspend	= ar7643_ts_suspend,

+	.resume		= ar7643_ts_resume,

+#endif

+};

+

+static int __init ar7643_ts_init(void)

+{

+	printk("AR7643 ADC Touchscreen Driver for AK98, (c) 2011 ANYKA\n");

+

+	return platform_driver_register(&ar7643_ts_driver);

+}

+

+static void __exit ar7643_ts_exit(void)

+{

+	platform_driver_unregister(&ar7643_ts_driver);

+}

+

+

+module_init(ar7643_ts_init);

+module_exit(ar7643_ts_exit);

+

+MODULE_AUTHOR("Anyka,Ltd");

+MODULE_DESCRIPTION("AR7643 TouchScreen Driver");

+MODULE_LICENSE("GPL");

+

+

+

+

+

+

+

+

+

+

+

+

+

+

diff --git a/drivers/input/touchscreen/synaptics_i2c_rmi.c b/drivers/input/touchscreen/synaptics_i2c_rmi.c
new file mode 100644
index 00000000000..f37c0c0fba4
--- /dev/null
+++ b/drivers/input/touchscreen/synaptics_i2c_rmi.c
@@ -0,0 +1,674 @@
+/* drivers/input/keyboard/synaptics_i2c_rmi.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/earlysuspend.h>
+#include <linux/hrtimer.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/synaptics_i2c_rmi.h>
+
+static struct workqueue_struct *synaptics_wq;
+
+struct synaptics_ts_data {
+	uint16_t addr;
+	struct i2c_client *client;
+	struct input_dev *input_dev;
+	int use_irq;
+	bool has_relative_report;
+	struct hrtimer timer;
+	struct work_struct  work;
+	uint16_t max[2];
+	int snap_state[2][2];
+	int snap_down_on[2];
+	int snap_down_off[2];
+	int snap_up_on[2];
+	int snap_up_off[2];
+	int snap_down[2];
+	int snap_up[2];
+	uint32_t flags;
+	int reported_finger_count;
+	int8_t sensitivity_adjust;
+	int (*power)(int on);
+	struct early_suspend early_suspend;
+};
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void synaptics_ts_early_suspend(struct early_suspend *h);
+static void synaptics_ts_late_resume(struct early_suspend *h);
+#endif
+
+static int synaptics_init_panel(struct synaptics_ts_data *ts)
+{
+	int ret;
+
+	ret = i2c_smbus_write_byte_data(ts->client, 0xff, 0x10); /* page select = 0x10 */
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed for page select\n");
+		goto err_page_select_failed;
+	}
+	ret = i2c_smbus_write_byte_data(ts->client, 0x41, 0x04); /* Set "No Clip Z" */
+	if (ret < 0)
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed for No Clip Z\n");
+
+	ret = i2c_smbus_write_byte_data(ts->client, 0x44,
+					ts->sensitivity_adjust);
+	if (ret < 0)
+		pr_err("synaptics_ts: failed to set Sensitivity Adjust\n");
+
+err_page_select_failed:
+	ret = i2c_smbus_write_byte_data(ts->client, 0xff, 0x04); /* page select = 0x04 */
+	if (ret < 0)
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed for page select\n");
+	ret = i2c_smbus_write_byte_data(ts->client, 0xf0, 0x81); /* normal operation, 80 reports per second */
+	if (ret < 0)
+		printk(KERN_ERR "synaptics_ts_resume: i2c_smbus_write_byte_data failed\n");
+	return ret;
+}
+
+static void synaptics_ts_work_func(struct work_struct *work)
+{
+	int i;
+	int ret;
+	int bad_data = 0;
+	struct i2c_msg msg[2];
+	uint8_t start_reg;
+	uint8_t buf[15];
+	struct synaptics_ts_data *ts = container_of(work, struct synaptics_ts_data, work);
+	int buf_len = ts->has_relative_report ? 15 : 13;
+
+	msg[0].addr = ts->client->addr;
+	msg[0].flags = 0;
+	msg[0].len = 1;
+	msg[0].buf = &start_reg;
+	start_reg = 0x00;
+	msg[1].addr = ts->client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = buf_len;
+	msg[1].buf = buf;
+
+	/* printk("synaptics_ts_work_func\n"); */
+	for (i = 0; i < ((ts->use_irq && !bad_data) ? 1 : 10); i++) {
+		ret = i2c_transfer(ts->client->adapter, msg, 2);
+		if (ret < 0) {
+			printk(KERN_ERR "synaptics_ts_work_func: i2c_transfer failed\n");
+			bad_data = 1;
+		} else {
+			/* printk("synaptics_ts_work_func: %x %x %x %x %x %x" */
+			/*        " %x %x %x %x %x %x %x %x %x, ret %d\n", */
+			/*        buf[0], buf[1], buf[2], buf[3], */
+			/*        buf[4], buf[5], buf[6], buf[7], */
+			/*        buf[8], buf[9], buf[10], buf[11], */
+			/*        buf[12], buf[13], buf[14], ret); */
+			if ((buf[buf_len - 1] & 0xc0) != 0x40) {
+				printk(KERN_WARNING "synaptics_ts_work_func:"
+				       " bad read %x %x %x %x %x %x %x %x %x"
+				       " %x %x %x %x %x %x, ret %d\n",
+				       buf[0], buf[1], buf[2], buf[3],
+				       buf[4], buf[5], buf[6], buf[7],
+				       buf[8], buf[9], buf[10], buf[11],
+				       buf[12], buf[13], buf[14], ret);
+				if (bad_data)
+					synaptics_init_panel(ts);
+				bad_data = 1;
+				continue;
+			}
+			bad_data = 0;
+			if ((buf[buf_len - 1] & 1) == 0) {
+				/* printk("read %d coordinates\n", i); */
+				break;
+			} else {
+				int pos[2][2];
+				int f, a;
+				int base;
+				/* int x = buf[3] | (uint16_t)(buf[2] & 0x1f) << 8; */
+				/* int y = buf[5] | (uint16_t)(buf[4] & 0x1f) << 8; */
+				int z = buf[1];
+				int w = buf[0] >> 4;
+				int finger = buf[0] & 7;
+
+				/* int x2 = buf[3+6] | (uint16_t)(buf[2+6] & 0x1f) << 8; */
+				/* int y2 = buf[5+6] | (uint16_t)(buf[4+6] & 0x1f) << 8; */
+				/* int z2 = buf[1+6]; */
+				/* int w2 = buf[0+6] >> 4; */
+				/* int finger2 = buf[0+6] & 7; */
+
+				/* int dx = (int8_t)buf[12]; */
+				/* int dy = (int8_t)buf[13]; */
+				int finger2_pressed;
+
+				/* printk("x %4d, y %4d, z %3d, w %2d, F %d, 2nd: x %4d, y %4d, z %3d, w %2d, F %d, dx %4d, dy %4d\n", */
+				/*	x, y, z, w, finger, */
+				/*	x2, y2, z2, w2, finger2, */
+				/*	dx, dy); */
+
+				base = 2;
+				for (f = 0; f < 2; f++) {
+					uint32_t flip_flag = SYNAPTICS_FLIP_X;
+					for (a = 0; a < 2; a++) {
+						int p = buf[base + 1];
+						p |= (uint16_t)(buf[base] & 0x1f) << 8;
+						if (ts->flags & flip_flag)
+							p = ts->max[a] - p;
+						if (ts->flags & SYNAPTICS_SNAP_TO_INACTIVE_EDGE) {
+							if (ts->snap_state[f][a]) {
+								if (p <= ts->snap_down_off[a])
+									p = ts->snap_down[a];
+								else if (p >= ts->snap_up_off[a])
+									p = ts->snap_up[a];
+								else
+									ts->snap_state[f][a] = 0;
+							} else {
+								if (p <= ts->snap_down_on[a]) {
+									p = ts->snap_down[a];
+									ts->snap_state[f][a] = 1;
+								} else if (p >= ts->snap_up_on[a]) {
+									p = ts->snap_up[a];
+									ts->snap_state[f][a] = 1;
+								}
+							}
+						}
+						pos[f][a] = p;
+						base += 2;
+						flip_flag <<= 1;
+					}
+					base += 2;
+					if (ts->flags & SYNAPTICS_SWAP_XY)
+						swap(pos[f][0], pos[f][1]);
+				}
+				if (z) {
+					input_report_abs(ts->input_dev, ABS_X, pos[0][0]);
+					input_report_abs(ts->input_dev, ABS_Y, pos[0][1]);
+				}
+				input_report_abs(ts->input_dev, ABS_PRESSURE, z);
+				input_report_abs(ts->input_dev, ABS_TOOL_WIDTH, w);
+				input_report_key(ts->input_dev, BTN_TOUCH, finger);
+				finger2_pressed = finger > 1 && finger != 7;
+				input_report_key(ts->input_dev, BTN_2, finger2_pressed);
+				if (finger2_pressed) {
+					input_report_abs(ts->input_dev, ABS_HAT0X, pos[1][0]);
+					input_report_abs(ts->input_dev, ABS_HAT0Y, pos[1][1]);
+				}
+
+				if (!finger)
+					z = 0;
+				input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, z);
+				input_report_abs(ts->input_dev, ABS_MT_WIDTH_MAJOR, w);
+				input_report_abs(ts->input_dev, ABS_MT_POSITION_X, pos[0][0]);
+				input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, pos[0][1]);
+				input_mt_sync(ts->input_dev);
+				if (finger2_pressed) {
+					input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, z);
+					input_report_abs(ts->input_dev, ABS_MT_WIDTH_MAJOR, w);
+					input_report_abs(ts->input_dev, ABS_MT_POSITION_X, pos[1][0]);
+					input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, pos[1][1]);
+					input_mt_sync(ts->input_dev);
+				} else if (ts->reported_finger_count > 1) {
+					input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0);
+					input_report_abs(ts->input_dev, ABS_MT_WIDTH_MAJOR, 0);
+					input_mt_sync(ts->input_dev);
+				}
+				ts->reported_finger_count = finger;
+				input_sync(ts->input_dev);
+			}
+		}
+	}
+	if (ts->use_irq)
+		enable_irq(ts->client->irq);
+}
+
+static enum hrtimer_restart synaptics_ts_timer_func(struct hrtimer *timer)
+{
+	struct synaptics_ts_data *ts = container_of(timer, struct synaptics_ts_data, timer);
+	/* printk("synaptics_ts_timer_func\n"); */
+
+	queue_work(synaptics_wq, &ts->work);
+
+	hrtimer_start(&ts->timer, ktime_set(0, 12500000), HRTIMER_MODE_REL);
+	return HRTIMER_NORESTART;
+}
+
+static irqreturn_t synaptics_ts_irq_handler(int irq, void *dev_id)
+{
+	struct synaptics_ts_data *ts = dev_id;
+
+	/* printk("synaptics_ts_irq_handler\n"); */
+	disable_irq_nosync(ts->client->irq);
+	queue_work(synaptics_wq, &ts->work);
+	return IRQ_HANDLED;
+}
+
+static int synaptics_ts_probe(
+	struct i2c_client *client, const struct i2c_device_id *id)
+{
+	struct synaptics_ts_data *ts;
+	uint8_t buf0[4];
+	uint8_t buf1[8];
+	struct i2c_msg msg[2];
+	int ret = 0;
+	uint16_t max_x, max_y;
+	int fuzz_x, fuzz_y, fuzz_p, fuzz_w;
+	struct synaptics_i2c_rmi_platform_data *pdata;
+	unsigned long irqflags;
+	int inactive_area_left;
+	int inactive_area_right;
+	int inactive_area_top;
+	int inactive_area_bottom;
+	int snap_left_on;
+	int snap_left_off;
+	int snap_right_on;
+	int snap_right_off;
+	int snap_top_on;
+	int snap_top_off;
+	int snap_bottom_on;
+	int snap_bottom_off;
+	uint32_t panel_version;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		printk(KERN_ERR "synaptics_ts_probe: need I2C_FUNC_I2C\n");
+		ret = -ENODEV;
+		goto err_check_functionality_failed;
+	}
+
+	ts = kzalloc(sizeof(*ts), GFP_KERNEL);
+	if (ts == NULL) {
+		ret = -ENOMEM;
+		goto err_alloc_data_failed;
+	}
+	INIT_WORK(&ts->work, synaptics_ts_work_func);
+	ts->client = client;
+	i2c_set_clientdata(client, ts);
+	pdata = client->dev.platform_data;
+	if (pdata)
+		ts->power = pdata->power;
+	if (ts->power) {
+		ret = ts->power(1);
+		if (ret < 0) {
+			printk(KERN_ERR "synaptics_ts_probe power on failed\n");
+			goto err_power_failed;
+		}
+	}
+
+	ret = i2c_smbus_write_byte_data(ts->client, 0xf4, 0x01); /* device command = reset */
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed\n");
+		/* fail? */
+	}
+	{
+		int retry = 10;
+		while (retry-- > 0) {
+			ret = i2c_smbus_read_byte_data(ts->client, 0xe4);
+			if (ret >= 0)
+				break;
+			msleep(100);
+		}
+	}
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_byte_data failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: Product Major Version %x\n", ret);
+	panel_version = ret << 8;
+	ret = i2c_smbus_read_byte_data(ts->client, 0xe5);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_byte_data failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: Product Minor Version %x\n", ret);
+	panel_version |= ret;
+
+	ret = i2c_smbus_read_byte_data(ts->client, 0xe3);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_byte_data failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: product property %x\n", ret);
+
+	if (pdata) {
+		while (pdata->version > panel_version)
+			pdata++;
+		ts->flags = pdata->flags;
+		ts->sensitivity_adjust = pdata->sensitivity_adjust;
+		irqflags = pdata->irqflags;
+		inactive_area_left = pdata->inactive_left;
+		inactive_area_right = pdata->inactive_right;
+		inactive_area_top = pdata->inactive_top;
+		inactive_area_bottom = pdata->inactive_bottom;
+		snap_left_on = pdata->snap_left_on;
+		snap_left_off = pdata->snap_left_off;
+		snap_right_on = pdata->snap_right_on;
+		snap_right_off = pdata->snap_right_off;
+		snap_top_on = pdata->snap_top_on;
+		snap_top_off = pdata->snap_top_off;
+		snap_bottom_on = pdata->snap_bottom_on;
+		snap_bottom_off = pdata->snap_bottom_off;
+		fuzz_x = pdata->fuzz_x;
+		fuzz_y = pdata->fuzz_y;
+		fuzz_p = pdata->fuzz_p;
+		fuzz_w = pdata->fuzz_w;
+	} else {
+		irqflags = 0;
+		inactive_area_left = 0;
+		inactive_area_right = 0;
+		inactive_area_top = 0;
+		inactive_area_bottom = 0;
+		snap_left_on = 0;
+		snap_left_off = 0;
+		snap_right_on = 0;
+		snap_right_off = 0;
+		snap_top_on = 0;
+		snap_top_off = 0;
+		snap_bottom_on = 0;
+		snap_bottom_off = 0;
+		fuzz_x = 0;
+		fuzz_y = 0;
+		fuzz_p = 0;
+		fuzz_w = 0;
+	}
+
+	ret = i2c_smbus_read_byte_data(ts->client, 0xf0);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_byte_data failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: device control %x\n", ret);
+
+	ret = i2c_smbus_read_byte_data(ts->client, 0xf1);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_byte_data failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: interrupt enable %x\n", ret);
+
+	ret = i2c_smbus_write_byte_data(ts->client, 0xf1, 0); /* disable interrupt */
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed\n");
+		goto err_detect_failed;
+	}
+
+	msg[0].addr = ts->client->addr;
+	msg[0].flags = 0;
+	msg[0].len = 1;
+	msg[0].buf = buf0;
+	buf0[0] = 0xe0;
+	msg[1].addr = ts->client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = 8;
+	msg[1].buf = buf1;
+	ret = i2c_transfer(ts->client->adapter, msg, 2);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_transfer failed\n");
+		goto err_detect_failed;
+	}
+	printk(KERN_INFO "synaptics_ts_probe: 0xe0: %x %x %x %x %x %x %x %x\n",
+	       buf1[0], buf1[1], buf1[2], buf1[3],
+	       buf1[4], buf1[5], buf1[6], buf1[7]);
+
+	ret = i2c_smbus_write_byte_data(ts->client, 0xff, 0x10); /* page select = 0x10 */
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_write_byte_data failed for page select\n");
+		goto err_detect_failed;
+	}
+	ret = i2c_smbus_read_word_data(ts->client, 0x02);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_word_data failed\n");
+		goto err_detect_failed;
+	}
+	ts->has_relative_report = !(ret & 0x100);
+	printk(KERN_INFO "synaptics_ts_probe: Sensor properties %x\n", ret);
+	ret = i2c_smbus_read_word_data(ts->client, 0x04);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_word_data failed\n");
+		goto err_detect_failed;
+	}
+	ts->max[0] = max_x = (ret >> 8 & 0xff) | ((ret & 0x1f) << 8);
+	ret = i2c_smbus_read_word_data(ts->client, 0x06);
+	if (ret < 0) {
+		printk(KERN_ERR "i2c_smbus_read_word_data failed\n");
+		goto err_detect_failed;
+	}
+	ts->max[1] = max_y = (ret >> 8 & 0xff) | ((ret & 0x1f) << 8);
+	if (ts->flags & SYNAPTICS_SWAP_XY)
+		swap(max_x, max_y);
+
+	ret = synaptics_init_panel(ts); /* will also switch back to page 0x04 */
+	if (ret < 0) {
+		printk(KERN_ERR "synaptics_init_panel failed\n");
+		goto err_detect_failed;
+	}
+
+	ts->input_dev = input_allocate_device();
+	if (ts->input_dev == NULL) {
+		ret = -ENOMEM;
+		printk(KERN_ERR "synaptics_ts_probe: Failed to allocate input device\n");
+		goto err_input_dev_alloc_failed;
+	}
+	ts->input_dev->name = "synaptics-rmi-touchscreen";
+	set_bit(EV_SYN, ts->input_dev->evbit);
+	set_bit(EV_KEY, ts->input_dev->evbit);
+	set_bit(BTN_TOUCH, ts->input_dev->keybit);
+	set_bit(BTN_2, ts->input_dev->keybit);
+	set_bit(EV_ABS, ts->input_dev->evbit);
+	inactive_area_left = inactive_area_left * max_x / 0x10000;
+	inactive_area_right = inactive_area_right * max_x / 0x10000;
+	inactive_area_top = inactive_area_top * max_y / 0x10000;
+	inactive_area_bottom = inactive_area_bottom * max_y / 0x10000;
+	snap_left_on = snap_left_on * max_x / 0x10000;
+	snap_left_off = snap_left_off * max_x / 0x10000;
+	snap_right_on = snap_right_on * max_x / 0x10000;
+	snap_right_off = snap_right_off * max_x / 0x10000;
+	snap_top_on = snap_top_on * max_y / 0x10000;
+	snap_top_off = snap_top_off * max_y / 0x10000;
+	snap_bottom_on = snap_bottom_on * max_y / 0x10000;
+	snap_bottom_off = snap_bottom_off * max_y / 0x10000;
+	fuzz_x = fuzz_x * max_x / 0x10000;
+	fuzz_y = fuzz_y * max_y / 0x10000;
+	ts->snap_down[!!(ts->flags & SYNAPTICS_SWAP_XY)] = -inactive_area_left;
+	ts->snap_up[!!(ts->flags & SYNAPTICS_SWAP_XY)] = max_x + inactive_area_right;
+	ts->snap_down[!(ts->flags & SYNAPTICS_SWAP_XY)] = -inactive_area_top;
+	ts->snap_up[!(ts->flags & SYNAPTICS_SWAP_XY)] = max_y + inactive_area_bottom;
+	ts->snap_down_on[!!(ts->flags & SYNAPTICS_SWAP_XY)] = snap_left_on;
+	ts->snap_down_off[!!(ts->flags & SYNAPTICS_SWAP_XY)] = snap_left_off;
+	ts->snap_up_on[!!(ts->flags & SYNAPTICS_SWAP_XY)] = max_x - snap_right_on;
+	ts->snap_up_off[!!(ts->flags & SYNAPTICS_SWAP_XY)] = max_x - snap_right_off;
+	ts->snap_down_on[!(ts->flags & SYNAPTICS_SWAP_XY)] = snap_top_on;
+	ts->snap_down_off[!(ts->flags & SYNAPTICS_SWAP_XY)] = snap_top_off;
+	ts->snap_up_on[!(ts->flags & SYNAPTICS_SWAP_XY)] = max_y - snap_bottom_on;
+	ts->snap_up_off[!(ts->flags & SYNAPTICS_SWAP_XY)] = max_y - snap_bottom_off;
+	printk(KERN_INFO "synaptics_ts_probe: max_x %d, max_y %d\n", max_x, max_y);
+	printk(KERN_INFO "synaptics_ts_probe: inactive_x %d %d, inactive_y %d %d\n",
+	       inactive_area_left, inactive_area_right,
+	       inactive_area_top, inactive_area_bottom);
+	printk(KERN_INFO "synaptics_ts_probe: snap_x %d-%d %d-%d, snap_y %d-%d %d-%d\n",
+	       snap_left_on, snap_left_off, snap_right_on, snap_right_off,
+	       snap_top_on, snap_top_off, snap_bottom_on, snap_bottom_off);
+	input_set_abs_params(ts->input_dev, ABS_X, -inactive_area_left, max_x + inactive_area_right, fuzz_x, 0);
+	input_set_abs_params(ts->input_dev, ABS_Y, -inactive_area_top, max_y + inactive_area_bottom, fuzz_y, 0);
+	input_set_abs_params(ts->input_dev, ABS_PRESSURE, 0, 255, fuzz_p, 0);
+	input_set_abs_params(ts->input_dev, ABS_TOOL_WIDTH, 0, 15, fuzz_w, 0);
+	input_set_abs_params(ts->input_dev, ABS_HAT0X, -inactive_area_left, max_x + inactive_area_right, fuzz_x, 0);
+	input_set_abs_params(ts->input_dev, ABS_HAT0Y, -inactive_area_top, max_y + inactive_area_bottom, fuzz_y, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, -inactive_area_left, max_x + inactive_area_right, fuzz_x, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, -inactive_area_top, max_y + inactive_area_bottom, fuzz_y, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, fuzz_p, 0);
+	input_set_abs_params(ts->input_dev, ABS_MT_WIDTH_MAJOR, 0, 15, fuzz_w, 0);
+	/* ts->input_dev->name = ts->keypad_info->name; */
+	ret = input_register_device(ts->input_dev);
+	if (ret) {
+		printk(KERN_ERR "synaptics_ts_probe: Unable to register %s input device\n", ts->input_dev->name);
+		goto err_input_register_device_failed;
+	}
+	if (client->irq) {
+		ret = request_irq(client->irq, synaptics_ts_irq_handler, irqflags, client->name, ts);
+		if (ret == 0) {
+			ret = i2c_smbus_write_byte_data(ts->client, 0xf1, 0x01); /* enable abs int */
+			if (ret)
+				free_irq(client->irq, ts);
+		}
+		if (ret == 0)
+			ts->use_irq = 1;
+		else
+			dev_err(&client->dev, "request_irq failed\n");
+	}
+	if (!ts->use_irq) {
+		hrtimer_init(&ts->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+		ts->timer.function = synaptics_ts_timer_func;
+		hrtimer_start(&ts->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
+	}
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
+	ts->early_suspend.suspend = synaptics_ts_early_suspend;
+	ts->early_suspend.resume = synaptics_ts_late_resume;
+	register_early_suspend(&ts->early_suspend);
+#endif
+
+	printk(KERN_INFO "synaptics_ts_probe: Start touchscreen %s in %s mode\n", ts->input_dev->name, ts->use_irq ? "interrupt" : "polling");
+
+	return 0;
+
+err_input_register_device_failed:
+	input_free_device(ts->input_dev);
+
+err_input_dev_alloc_failed:
+err_detect_failed:
+err_power_failed:
+	kfree(ts);
+err_alloc_data_failed:
+err_check_functionality_failed:
+	return ret;
+}
+
+static int synaptics_ts_remove(struct i2c_client *client)
+{
+	struct synaptics_ts_data *ts = i2c_get_clientdata(client);
+	unregister_early_suspend(&ts->early_suspend);
+	if (ts->use_irq)
+		free_irq(client->irq, ts);
+	else
+		hrtimer_cancel(&ts->timer);
+	input_unregister_device(ts->input_dev);
+	kfree(ts);
+	return 0;
+}
+
+static int synaptics_ts_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	int ret;
+	struct synaptics_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts->use_irq)
+		disable_irq(client->irq);
+	else
+		hrtimer_cancel(&ts->timer);
+	ret = cancel_work_sync(&ts->work);
+	if (ret && ts->use_irq) /* if work was pending disable-count is now 2 */
+		enable_irq(client->irq);
+	ret = i2c_smbus_write_byte_data(ts->client, 0xf1, 0); /* disable interrupt */
+	if (ret < 0)
+		printk(KERN_ERR "synaptics_ts_suspend: i2c_smbus_write_byte_data failed\n");
+
+	ret = i2c_smbus_write_byte_data(client, 0xf0, 0x86); /* deep sleep */
+	if (ret < 0)
+		printk(KERN_ERR "synaptics_ts_suspend: i2c_smbus_write_byte_data failed\n");
+	if (ts->power) {
+		ret = ts->power(0);
+		if (ret < 0)
+			printk(KERN_ERR "synaptics_ts_resume power off failed\n");
+	}
+	return 0;
+}
+
+static int synaptics_ts_resume(struct i2c_client *client)
+{
+	int ret;
+	struct synaptics_ts_data *ts = i2c_get_clientdata(client);
+
+	if (ts->power) {
+		ret = ts->power(1);
+		if (ret < 0)
+			printk(KERN_ERR "synaptics_ts_resume power on failed\n");
+	}
+
+	synaptics_init_panel(ts);
+
+	if (ts->use_irq)
+		enable_irq(client->irq);
+
+	if (!ts->use_irq)
+		hrtimer_start(&ts->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
+	else
+		i2c_smbus_write_byte_data(ts->client, 0xf1, 0x01); /* enable abs int */
+
+	return 0;
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static void synaptics_ts_early_suspend(struct early_suspend *h)
+{
+	struct synaptics_ts_data *ts;
+	ts = container_of(h, struct synaptics_ts_data, early_suspend);
+	synaptics_ts_suspend(ts->client, PMSG_SUSPEND);
+}
+
+static void synaptics_ts_late_resume(struct early_suspend *h)
+{
+	struct synaptics_ts_data *ts;
+	ts = container_of(h, struct synaptics_ts_data, early_suspend);
+	synaptics_ts_resume(ts->client);
+}
+#endif
+
+static const struct i2c_device_id synaptics_ts_id[] = {
+	{ SYNAPTICS_I2C_RMI_NAME, 0 },
+	{ }
+};
+
+static struct i2c_driver synaptics_ts_driver = {
+	.probe		= synaptics_ts_probe,
+	.remove		= synaptics_ts_remove,
+#ifndef CONFIG_HAS_EARLYSUSPEND
+	.suspend	= synaptics_ts_suspend,
+	.resume		= synaptics_ts_resume,
+#endif
+	.id_table	= synaptics_ts_id,
+	.driver = {
+		.name	= SYNAPTICS_I2C_RMI_NAME,
+	},
+};
+
+static int __devinit synaptics_ts_init(void)
+{
+	synaptics_wq = create_singlethread_workqueue("synaptics_wq");
+	if (!synaptics_wq)
+		return -ENOMEM;
+	return i2c_add_driver(&synaptics_ts_driver);
+}
+
+static void __exit synaptics_ts_exit(void)
+{
+	i2c_del_driver(&synaptics_ts_driver);
+	if (synaptics_wq)
+		destroy_workqueue(synaptics_wq);
+}
+
+module_init(synaptics_ts_init);
+module_exit(synaptics_ts_exit);
+
+MODULE_DESCRIPTION("Synaptics Touchscreen Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/tscp2007.c b/drivers/input/touchscreen/tscp2007.c
new file mode 100755
index 00000000000..022fe43807c
--- /dev/null
+++ b/drivers/input/touchscreen/tscp2007.c
@@ -0,0 +1,835 @@
+/*
+ * drivers/input/touchscreen/cp2007_ts.c
+ *
+ * Copyright (c) 2010 Anyka, Ltd.
+ *
+ * Using code from:
+ *  -tsc2007.c
+ *   Copyright (c) 2008 Kwangwoo Lee
+ *  - ads7846.c
+ *	Copyright (c) 2005 David Brownell
+ *	Copyright (c) 2006 Nokia Corporation
+ *  - corgi_ts.c
+ *	Copyright (C) 2004-2005 Richard Purdie
+ *  - omap_ts.[hc], ads7846.h, ts_osk.c
+ *	Copyright (C) 2002 MontaVista Software
+ *	Copyright (C) 2004 Texas Instruments
+ *	Copyright (C) 2005 Dirk Behme
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/i2c/cp2007.h>
+#include <linux/io.h>
+#include <mach/gpio.h>
+#include <linux/mutex.h>
+
+
+#define TS_POLL_DELAY			1 /* ms delay between samples */
+#define TS_POLL_PERIOD			10 /* ms delay between samples */
+#define MIN_PRESSURE 100
+#define MAX_PRESSURE 700
+
+#define DEF_PRESSURE 1
+
+#define VARIANCE
+static struct workqueue_struct *tscp2007_wq;
+
+struct TS_SAMPLE {
+	s32		x;
+	s32		y;
+	u32	pressure;
+};
+
+static void report_value(struct input_dev *dev, struct TS_SAMPLE *samp);
+
+#ifdef VARIANCE
+
+#define P_DELTA			249
+/* 2-23 added by wenyong */
+#define X_DELTA 		234  
+#define X_DELTA_MAX 	500  //max offset of X 
+#define Y_DELTA 		330 
+#define Y_DELTA_MAX 	650  //max offset of Y
+#define XY_DELTA 		(X_DELTA + Y_DELTA)
+#define TS_HZ 			15
+#define FAST_DELTA		(X_DELTA + Y_DELTA)
+
+
+//static int X_WEIGHT[5] = {0, 22, 44, 66, 88};
+//static int Y_WEIGHT[5] = {0, 26, 52, 78, 104};
+#define NEXT_INDEX(i, size) (i==size - 1 ? 0:i+1)
+#define MAX_SAMPLE 5
+enum 
+{
+	IX_XX=0,
+	IX_YY,
+	IX_PP,
+	IX_LEN
+};
+
+static void t_swap(void **a, void **b);
+static s32 variance(struct input_dev *dev, s16 x, s16 y, u32 pressure, bool penup);
+
+static int dejitter(struct input_dev *dev, struct TS_SAMPLE *_samp, bool penup);
+
+
+#endif
+//#define TS_DEBUG
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef TS_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+
+#define CP2007_MEASURE_TEMP0	(0x0 << 4)
+#define CP2007_MEASURE_AUX		(0x2 << 4)
+#define CP2007_MEASURE_TEMP1	(0x4 << 4)
+#define CP2007_ACTIVATE_XN		(0x8 << 4)
+#define CP2007_ACTIVATE_YN		(0x9 << 4)
+#define CP2007_ACTIVATE_YP_XN	(0xa << 4)
+#define CP2007_SETUP			(0xb << 4)
+#define CP2007_MEASURE_X		(0xc << 4)
+#define CP2007_MEASURE_Y		(0xd << 4)
+#define CP2007_MEASURE_Z1		(0xe << 4)
+#define CP2007_MEASURE_Z2		(0xf << 4)
+
+
+#define CP2007_POWER_OFF_IRQ_EN	(0x0 << 2)
+#define CP2007_ADC_ON_IRQ_DIS0		(0x1 << 2)
+#define CP2007_ADC_OFF_IRQ_EN		(0x2 << 2)
+#define CP2007_ADC_ON_IRQ_DIS1		(0x3 << 2)
+
+#define CP2007_12BIT		(0x0 << 1)
+#define CP2007_8BIT			(0x1 << 1)
+
+#define	MAX_12BIT			((1 << 12) - 1)
+
+#define ADC_ON_12BIT	(CP2007_12BIT | CP2007_ADC_ON_IRQ_DIS0)
+
+
+#define ADC_ON_AND_ACTIVE (ADC_ON_12BIT | CP2007_ACTIVATE_YN | CP2007_ACTIVATE_XN | CP2007_ACTIVATE_YP_XN )
+#define READ_Y		(CP2007_12BIT | CP2007_MEASURE_Y )
+#define READ_Z1		(CP2007_12BIT | CP2007_MEASURE_Z1)
+#define READ_Z2		(CP2007_12BIT | CP2007_MEASURE_Z2)
+#define READ_X		(CP2007_12BIT | CP2007_MEASURE_X )
+#define PWRDOWN		(CP2007_12BIT | CP2007_POWER_OFF_IRQ_EN)
+#define ADCOFF 		(CP2007_12BIT | CP2007_ADC_OFF_IRQ_EN)
+
+
+struct ts_event {
+	u16	x;
+	u16	y;
+	u16	z1, z2;
+};
+
+struct cp2007_ts {
+	struct input_dev	*input;
+	char			phys[32];
+	struct delayed_work	work;
+	struct timer_list ts_timer;
+
+	struct i2c_client	*client;
+
+	u16			x_plate_ohms;
+
+	bool		pendown;
+	int			irq;
+	unsigned int intpin;
+	char		origin_pos;
+
+	int			(*is_pen_down)(unsigned int pin);
+	void		(*clear_penirq)(void);
+};
+
+struct mutex g_cp2007_mutex;
+
+static inline int cp2007_ts_xfer(struct cp2007_ts *tsc, u8 cmd)
+{
+	s32 data;
+	u16 val;
+
+	data = i2c_smbus_read_word_data(tsc->client, cmd);
+	if (data < 0) {
+		dev_err(&tsc->client->dev, "i2c io error: %d\n", data);
+		return data;
+	}
+
+	/* The protocol and raw data format from i2c interface:
+	 * S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
+	 * Where DataLow has [D11-D4], DataHigh has [D3-D0 << 4 | Dummy 4bit].
+	 */
+	val = swab16(data) >> 4;
+
+	dev_dbg(&tsc->client->dev, "data: 0x%x, val: 0x%x\n", data, val);
+
+	return val;
+}
+
+static void cp2007_ts_read_values(struct cp2007_ts *tsc, struct ts_event *tc)
+{
+	mutex_lock(&g_cp2007_mutex);
+	cp2007_ts_xfer(tsc, ADC_ON_AND_ACTIVE);
+	/* y- still on; turn on only y+ (and ADC) */
+	tc->y = cp2007_ts_xfer(tsc, READ_Y);
+
+	/* turn y- off, x+ on, then leave in lowpower */
+	tc->x = cp2007_ts_xfer(tsc, READ_X);
+
+	/* turn y+ off, x- on; we'll use formula #1 */
+	tc->z1 = cp2007_ts_xfer(tsc, READ_Z1);
+	tc->z2 = cp2007_ts_xfer(tsc, READ_Z2);
+
+	/* Prepare for next touch reading - power down ADC, enable PENIRQ */
+	cp2007_ts_xfer(tsc, PWRDOWN);
+	mutex_unlock(&g_cp2007_mutex);
+	
+}
+
+static u32 cp2007_ts_calculate_pressure(struct cp2007_ts *tsc, struct ts_event *tc)
+{
+	u32 rt = 0;
+
+	/* range filtering */
+	if (tc->x == MAX_12BIT)
+		tc->x = 0;
+
+	if (likely(tc->x && tc->z1)) {
+		/* compute touch pressure resistance using equation #1 */
+		rt = tc->z2 - tc->z1;
+		rt *= tc->x;
+		rt *= tsc->x_plate_ohms;
+		rt /= tc->z1;
+		//rt = (rt + 2047) >> 12;
+		rt = rt >> 12;
+	}
+
+	return rt;
+}
+
+static void cp2007_ts_send_up_event(struct cp2007_ts *tsc)
+{
+	struct input_dev *input = tsc->input;
+
+	dev_dbg(&tsc->client->dev, "UP\n");
+
+	input_report_key(input, BTN_TOUCH, 0);
+	input_report_abs(input, ABS_PRESSURE, 0);
+	input_sync(input);
+}
+
+static void cp2007_ts_work(struct work_struct *work)
+{
+	struct cp2007_ts *ts = container_of(to_delayed_work(work), struct cp2007_ts, work);
+	struct ts_event tc;
+	u32 rt;
+
+	/*
+	 * NOTE: We can't rely on the pressure to determine the pen down
+	 * state, even though this controller has a pressure sensor.
+	 * The pressure value can fluctuate for quite a while after
+	 * lifting the pen and in some cases may not even settle at the
+	 * expected value.
+	 *
+	 * The only safe way to check for the pen up condition is in the
+	 * work function by reading the pen signal state (it's a GPIO
+	 * and IRQ). Unfortunately such callback is not always available,
+	 * in that case we have rely on the pressure anyway.
+	 */
+
+	if (ts->is_pen_down) {	
+		if (unlikely(!ts->is_pen_down(ts->intpin))) {
+			#ifdef VARIANCE
+			variance(ts->input,0, 0,0, true);
+			#endif
+			PDEBUG("up event\n");
+			cp2007_ts_send_up_event(ts);
+			ts->pendown = false;		
+			goto out;
+		}
+
+		dev_dbg(&ts->client->dev, "pen is still down\n");
+	}
+
+		
+	cp2007_ts_read_values(ts, &tc);
+
+	rt = cp2007_ts_calculate_pressure(ts, &tc);
+	if (ts->origin_pos == ORIGIN_TOPLEFT)
+		tc.y = MAX_12BIT - tc.y;
+	
+	PDEBUG("%4d %4d %4d\n", tc.x, tc.y, rt);
+	if ( (rt < MIN_PRESSURE) || (rt > MAX_PRESSURE)) {
+		/*
+		 * Sample found inconsistent by debouncing or pressure is
+		 * beyond the maximum. Don't report it to user space,
+		 * repeat at least once more the measurement.
+		 */		
+		dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
+		PDEBUG("Ignored pressure %d\n", rt);
+		goto out;
+	}
+
+	if (rt) {
+		struct input_dev *input = ts->input;
+
+		if (!ts->pendown) {
+			dev_dbg(&ts->client->dev, "DOWN\n");
+
+			input_report_key(input, BTN_TOUCH, 1);
+			ts->pendown = true;
+		}
+
+		#ifdef VARIANCE
+		variance(input, tc.x, tc.y, rt, false);
+		#else
+		struct TS_SAMPLE samp = {tc.x,tc.y,rt};
+		report_value(input, &samp);
+/*		input_report_abs(input, ABS_X, tc.x);
+		input_report_abs(input, ABS_Y, tc.y);
+		input_report_abs(input, ABS_PRESSURE, rt);
+
+		input_sync(input);
+		*/
+		#endif
+
+		dev_dbg(&ts->client->dev, "point(%4d,%4d), pressure (%4u)\n",
+			tc.x, tc.y, rt);
+
+	} else if (!ts->is_pen_down && ts->pendown) {
+		/*
+		 * We don't have callback to check pendown state, so we
+		 * have to assume that since pressure reported is 0 the
+		 * pen was lifted up.
+		 */
+		#ifdef VARIANCE
+			variance(ts->input,tc.x, tc.y,0, true);
+		#endif
+		PDEBUG("  up event\n");
+		cp2007_ts_send_up_event(ts);
+		ts->pendown = false;
+	}
+
+ out:
+	if (ts->pendown) {		
+		queue_delayed_work(tscp2007_wq, &ts->work,
+				      msecs_to_jiffies(TS_POLL_PERIOD));
+	}
+	else
+	{
+		enable_irq(ts->irq);
+	}
+}
+
+static irqreturn_t cp2007_ts_irq(int irq, void *handle)
+{
+	struct cp2007_ts *ts = handle;
+
+	// if ts->is_pen_down is NULL, likely(ts->is_pen_down() will never be excuted
+	if (!ts->is_pen_down || likely(ts->is_pen_down(ts->intpin))) {		
+		disable_irq_nosync(ts->irq);
+		PDEBUG("pen down\n");
+		
+			queue_delayed_work(tscp2007_wq, &ts->work,
+				      msecs_to_jiffies(TS_POLL_DELAY));
+	}
+
+	if (ts->clear_penirq)
+		ts->clear_penirq();
+
+	return IRQ_HANDLED;
+}
+
+static void cp2007_ts_free_irq(struct cp2007_ts *ts)
+{
+	free_irq(ts->irq, ts);
+	if (cancel_delayed_work_sync(&ts->work)) {
+		/*
+		 * Work was pending, therefore we need to enable
+		 * IRQ here to balance the disable_irq() done in the
+		 * interrupt handler.
+		 */
+		enable_irq(ts->irq);
+	}
+}
+
+//2-23 added by wenyong
+
+static void report_value(struct input_dev *dev, struct TS_SAMPLE *samp)
+{
+	PDEBUG("==%4d %4d %4d\n", samp->x, samp->y, samp->pressure);
+	input_report_abs(dev, ABS_X, samp->x);
+	input_report_abs(dev, ABS_Y, samp->y);
+	input_report_abs(dev, ABS_PRESSURE, DEF_PRESSURE);//samp->pressure);
+	input_sync(dev);
+}
+
+
+#ifdef VARIANCE
+static void t_swap(void **a, void **b)
+{
+	void *c;
+	c = *a;
+	*a = *b;
+	*b = c;
+}
+
+static s32 variance(struct input_dev *dev, s16 x, s16 y, u32 pressure, bool penup)
+{
+	static s32 count=0, pre_p;
+	static u8 k1, k2, k3;
+	static struct TS_SAMPLE samp[2];
+	static struct TS_SAMPLE *sampA = &(samp[0]), *sampB = &(samp[1]);
+	static s32 time_delta, pre_jiffies;
+	PDEBUG("----: %d %d %d %d\n", count, x, y, pressure);
+
+	time_delta = (jiffies - pre_jiffies) * TS_HZ;
+	pre_jiffies = jiffies;
+	if (penup)
+	{			
+		goto AcceptSample;
+	}
+	
+	if (count && abs(pressure - pre_p) > P_DELTA)
+	{
+		//drop the first
+		if (count == 1)
+		{
+			sampA->x = x; sampA->y = y;
+			pre_p = pressure;
+		}
+		//else drop the current
+		
+		return 0;
+	}
+	
+	pre_p = pressure;
+
+	switch (count)
+	{
+	case 0:
+		sampA->x = x; sampA->y = y; //sampA->pressure = pressure;	
+		count = 1;
+		return 0;
+	case 1:
+		if ( (abs(x - sampA->x) + abs(y - sampA->y)) < (XY_DELTA + time_delta))
+		{
+			sampB->x = x; sampB->y = y; //sampB->pressure = pressure;
+			goto AcceptSample;
+		}
+		else
+		{
+			sampB->x = x; sampB->y = y; //sampB->pressure = pressure;
+			count++;
+			//PDEBUG("dur: %d\n", time_delta);
+			return 0;
+		}
+	case 2:
+		if ( (abs(x - sampB->x) + abs(y - sampB->y)) < (XY_DELTA + time_delta))
+		{
+			sampA->x = x; sampA->y = y; //sampA->pressure = pressure;
+			t_swap((void *)&sampA, (void *)&sampB);
+			count = 1;
+			PDEBUG("Drop A... %d\n", time_delta);
+			//goto AcceptSample;
+		}
+		else if ( (abs(x - sampA->x) + abs(y - sampA->y)) < (XY_DELTA + time_delta))
+		{
+			sampB->x = x; sampB->y = y; //sampB->pressure = pressure;
+			count = 1;
+			PDEBUG("Drop B... %d\n", time_delta);
+			//goto AcceptSample ;			
+		}
+		
+		else
+		{
+			k1 = abs(sampB->x - sampA->x) > X_DELTA_MAX || abs(sampB->y - sampA->y) > Y_DELTA_MAX;
+			k2 = abs(x - sampB->x) > X_DELTA_MAX || abs(y - sampB->y) > Y_DELTA_MAX;			
+			k3 = abs(x - sampA->x) > X_DELTA_MAX || abs(y - sampA->y) > Y_DELTA_MAX;
+			if ( (k1 == 0) && (k2 == 0) && (k3 == 0) )
+			{
+			//move fast
+				goto AcceptSample;
+			}
+			else if ( (k1 == 1) && (k2 == 1) && (k3 == 1) )
+			{
+				count = 1;
+				sampA->x = x; sampA->y = y; //sampA->pressure = pressure;
+				PDEBUG("  Drop A,B ...\n");
+				return 0;
+			}			
+			else if ( k2 == 0)
+			{
+				sampA->x = x; sampA->y = y; //sampA->pressure = pressure;
+				t_swap((void *)&sampA, (void *)&sampB);
+				PDEBUG("  Drop A...\n");
+				return 0;
+			}
+			else if ( k3 == 0)
+			{
+				sampB->x = x; sampB->y = y; //sampB->pressure = pressure;
+				PDEBUG("  Drop B...\n");
+				return 0;
+			}
+			else if (k1 == 0)
+			{
+				PDEBUG ("  Drop C...\n");
+				return 0;
+			}
+			//else move fast
+		}
+		goto AcceptSample;
+		
+	}
+AcceptSample:
+	if (count)
+	{	
+
+		dejitter(dev, sampA, false);
+		if (count == 2)
+		{
+			dejitter(dev, sampB, false);
+			sampA->x = x; sampA->y = y; //sampA->pressure = pressure;
+		}
+		else
+		{		
+			t_swap((void *)&sampA, (void *)&sampB);
+		}
+		count=1;		
+	}
+	if (penup)
+	{
+		count = 0;
+		dejitter(dev, sampA, true);
+	}
+	
+	return 1;
+}
+
+static void average(struct TS_SAMPLE *samp[5], int *sum, int count, struct TS_SAMPLE *temp)
+{
+	int w[MAX_SAMPLE], kmax, i, aver;
+	
+	temp->x = sum[IX_XX]/count;
+	temp->y = sum[IX_YY]/count;
+	//temp->pressure = sum[IX_PP]/count;	
+	
+	if (count > 2)
+	{		
+		aver = temp->x;
+		w[0] = abs(samp[0]->x - aver);
+		kmax = 0;
+		for (i=1; i<count; i++)
+		{
+			w[i] = abs(samp[i]->x - aver);
+			if (w[i] > w[kmax])
+				kmax = i;
+		}
+		
+		temp->x = (sum[IX_XX] - samp[kmax]->x) / (count - 1);
+		//temp->pressure = (sum[IX_PP] - samp[kmax]->pressure) / (count - 1);		
+	}
+	if (count > 2)
+	{
+		
+		aver = temp->y;
+		w[0] = abs(samp[0]->y - aver);
+		kmax = 0;
+		for (i=1; i<count; i++)
+		{
+			w[i] = abs(samp[i]->y - aver);
+			if (w[i] > w[kmax])
+				kmax = i;
+		}
+		
+		temp->y = (sum[IX_YY] - samp[kmax]->y) / (count - 1);
+		//temp->pressure = (sum[IX_PP] - samp[kmax]->pressure) / (count - 1);		
+	}
+}
+
+
+static int dejitter(struct input_dev *dev, struct TS_SAMPLE *_samp, bool penup)
+{
+	static int count=0, i, sum[IX_LEN];	
+	static bool flush = false, first = true;
+	static struct TS_SAMPLE temp, *tp;
+	static struct TS_SAMPLE sampP[MAX_SAMPLE];
+	static struct TS_SAMPLE *samp[5] = {&(sampP[0]), &(sampP[1]), &(sampP[2]), &(sampP[3]), &(sampP[4])};
+	
+	PDEBUG("de: %d %d %d %d %d\n", count, _samp->x, _samp->y, _samp->pressure, penup);
+	if ( penup == true)
+	{		
+
+		if (count > 3)
+		{
+			average(samp, sum, count, &temp);
+			
+			report_value(dev, &temp);				
+			count=0;		
+			first = true;
+			return 1;			
+		}	
+		
+		count = 0;
+		first = true;
+		return 0;
+	}
+
+	//noise often happen when pendown, so the first report sample is given special care
+	if ( count>3 && (abs(_samp->x - samp[count-1]->x) + abs(_samp->y - samp[count-1]->y)) > FAST_DELTA)
+	{
+		PDEBUG("flush\n");
+		flush = true;
+		goto Report;
+	}
+	*(samp[count]) = *_samp;
+	count++;
+	
+	switch (count)
+	{
+	case 1:
+		sum[IX_XX] = _samp->x;
+		sum[IX_YY] = _samp->y;
+		//sum[IX_PP] = _samp->pressure;
+		return 0;
+	case 2:	
+		sum[IX_XX] += _samp->x;
+		sum[IX_YY] += _samp->y;
+		//sum[IX_PP] += _samp->pressure;
+		return 0;
+	case 3:
+		sum[IX_XX] += _samp->x;
+		sum[IX_YY] += _samp->y;
+	//	sum[IX_PP] += _samp->pressure;
+		return 0;
+
+	case 4:
+	case 5:		
+		sum[IX_XX] += _samp->x;
+		sum[IX_YY] += _samp->y;
+	//	sum[IX_PP] += _samp->pressure;		
+
+
+Report:
+		temp.x = sum[IX_XX]/count;
+		temp.y = sum[IX_YY]/count;
+	//	temp.pressure = sum[IX_PP]/count;
+
+		if (count > 2)
+		{
+			average(samp, sum, count, &temp);
+		}
+		//move fast, flush the history
+		if (flush == true)
+		{
+			flush = false;			
+			*(samp[0]) = *_samp;
+			sum[IX_XX] = _samp->x;
+			sum[IX_YY] = _samp->y;
+		//	sum[IX_PP] =  _samp->pressure;
+			count = 1;
+		}
+		if (count == 5)
+		{
+			tp = samp[0];
+			sum[IX_XX] -= samp[0]->x;
+			sum[IX_YY] -= samp[0]->y;
+		//	sum[IX_PP] -= samp[0]->pressure;
+			for (i=0; i<4; i++)
+				samp[i] = samp[i+1];
+			samp[4] = tp;
+			count = 4;			
+		}		
+	}
+	
+	report_value(dev, &temp);	
+	return 1;		
+}
+
+#endif
+
+static int __devinit cp2007_ts_probe(struct i2c_client *client, 
+								const struct i2c_device_id *id)
+{
+	struct cp2007_ts *ts;
+	struct cp2007_ts_platform_data *pdata = client->dev.platform_data;
+	struct input_dev *input_dev;
+	int err;
+
+	if (!pdata) {
+		dev_err(&client->dev, "platform data is required!\n");
+		return -EINVAL;
+	}
+
+	if (!i2c_check_functionality(client->adapter,
+				     I2C_FUNC_SMBUS_READ_WORD_DATA))
+		return -EIO;
+
+	ts = kzalloc(sizeof(struct cp2007_ts), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!ts || !input_dev) {
+		err = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	ts->client = client;
+	ts->irq = client->irq;
+	ts->input = input_dev;
+	
+	INIT_DELAYED_WORK(&ts->work, cp2007_ts_work);	
+
+	ts->origin_pos		= pdata->origin_pos;
+	ts->x_plate_ohms	= pdata->x_plate_ohms;
+	ts->is_pen_down		= pdata->is_pen_down;
+	ts->clear_penirq	= pdata->clear_penirq;
+	ts->intpin			= pdata->intpin_info.pin;
+
+	ts->pendown = false;
+
+	mutex_init(&g_cp2007_mutex);
+	snprintf(ts->phys, sizeof(ts->phys), "%s/input0", dev_name(&client->dev));
+
+	input_dev->name = client->name;// "CP2007 Touchscreen";
+	input_dev->phys = ts->phys;
+	input_dev->id.bustype = BUS_I2C;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+	input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+	input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0);
+	input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0);
+	input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);
+
+	if (pdata->init_ts_hw)
+		pdata->init_ts_hw(&(pdata->intpin_info));
+
+	err = request_irq(ts->irq, cp2007_ts_irq, 0, client->dev.driver->name, ts);
+	if (err < 0) {
+		dev_err(&client->dev, "irq %d busy?\n", ts->irq);
+		goto err_free_mem;
+	}
+
+	/* Prepare for touch readings - power down ADC and enable PENIRQ */
+	err = cp2007_ts_xfer(ts, PWRDOWN);
+	if (err < 0)
+		goto err_free_irq;
+
+	err = input_register_device(input_dev);
+	if (err)
+		goto err_free_irq;
+
+	i2c_set_clientdata(client, ts);
+
+	return 0;
+
+ err_free_irq:
+	cp2007_ts_free_irq(ts);
+	if (pdata->exit_ts_hw)
+		pdata->exit_ts_hw();
+ err_free_mem:
+	input_free_device(input_dev);
+	kfree(ts);
+	return err;
+}
+
+static int __devexit cp2007_ts_remove(struct i2c_client *client)
+{
+	struct cp2007_ts	*ts = i2c_get_clientdata(client);
+	struct cp2007_ts_platform_data *pdata = client->dev.platform_data;
+
+	
+	cp2007_ts_free_irq(ts);
+	del_timer_sync(&(ts->ts_timer));
+	if (pdata->exit_ts_hw)
+		pdata->exit_ts_hw();
+
+	input_unregister_device(ts->input);
+	kfree(ts);
+	mutex_destroy(&g_cp2007_mutex);
+	return 0;
+}
+
+static struct i2c_device_id cp2007_ts_idtable[] = {
+	{ "cp2007_ts", 0 },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(i2c, cp2007_ts_idtable);
+
+
+#ifdef CONFIG_PM
+int cp2007_ts_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	struct cp2007_ts	*ts = i2c_get_clientdata(client);
+	mutex_lock(&g_cp2007_mutex);
+
+	//low consumption, disable PENIRQ
+	cp2007_ts_xfer(ts, (CP2007_12BIT | CP2007_ADC_ON_IRQ_DIS0));
+	
+	return 0;
+}
+int cp2007_ts_resume(struct i2c_client *client)
+{
+	struct cp2007_ts	*ts = i2c_get_clientdata(client);
+	//enable PENIRQ
+	cp2007_ts_xfer(ts, PWRDOWN);
+	mutex_unlock(&g_cp2007_mutex);
+	return 0;
+}
+#endif
+
+static struct i2c_driver cp2007_ts_driver = {
+	.driver = {
+		.owner	= THIS_MODULE,
+		.name	= "cp2007_ts"
+	},
+	.id_table	= cp2007_ts_idtable,
+	.probe		= cp2007_ts_probe,
+	.remove		= __devexit_p(cp2007_ts_remove),
+	#ifdef CONFIG_PM
+	.suspend 	= cp2007_ts_suspend,
+	.resume		= cp2007_ts_resume,
+	#else
+	.suspend	= NULL,
+	.resume		= NULL,
+	#endif
+};
+
+static int __init cp2007_ts_init(void)
+{
+	tscp2007_wq = create_singlethread_workqueue("tscp2007_wq");
+	if (!tscp2007_wq)
+		return -ENOMEM;
+	return i2c_add_driver(&cp2007_ts_driver);
+}
+
+static void __exit cp2007_ts_exit(void)
+{
+	if (tscp2007_wq)
+			destroy_workqueue(tscp2007_wq);
+
+	i2c_del_driver(&cp2007_ts_driver);
+}
+
+module_init(cp2007_ts_init);
+module_exit(cp2007_ts_exit);
+
+MODULE_AUTHOR("Anyka,Ltd");
+MODULE_DESCRIPTION("CP2007 TouchScreen Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index e4f599f20e3..823af25ff4e 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -236,6 +236,12 @@ config LEDS_BD2802
 	  This option enables support for BD2802GU RGB LED driver chips
 	  accessed via the I2C bus.
 
+config LEDS_AK88
+	tristate "LED Support for the AK88 EPC LEDS"
+	depends on LEDS_CLASS && ARCH_AK88
+	help
+          This option enables support for the AK88 EPC LEDS.
+
 comment "LED Triggers"
 
 config LEDS_TRIGGERS
@@ -301,6 +307,12 @@ config LEDS_TRIGGER_DEFAULT_ON
 	  This allows LEDs to be initialised in the ON state.
 	  If unsure, say Y.
 
+config LEDS_TRIGGER_SLEEP
+	tristate "LED Sleep Mode Trigger"
+	depends on LEDS_TRIGGERS && HAS_EARLYSUSPEND
+	help
+	  This turns LEDs on when the screen is off but the cpu still running.
+
 comment "iptables trigger is under Netfilter config (LED target)"
 	depends on LEDS_TRIGGERS
 
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 46d72704d60..9a0483c4d55 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_DA903X)		+= leds-da903x.o
 obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
 obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
 obj-$(CONFIG_LEDS_PWM)			+= leds-pwm.o
+obj-$(CONFIG_LEDS_AK88)			+= leds-ak88.o
 
 # LED SPI Drivers
 obj-$(CONFIG_LEDS_DAC124S085)		+= leds-dac124s085.o
@@ -40,3 +41,4 @@ obj-$(CONFIG_LEDS_TRIGGER_HEARTBEAT)	+= ledtrig-heartbeat.o
 obj-$(CONFIG_LEDS_TRIGGER_BACKLIGHT)	+= ledtrig-backlight.o
 obj-$(CONFIG_LEDS_TRIGGER_GPIO)		+= ledtrig-gpio.o
 obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)	+= ledtrig-default-on.o
+obj-$(CONFIG_LEDS_TRIGGER_SLEEP)	+= ledtrig-sleep.o
diff --git a/drivers/leds/leds-ak88.c b/drivers/leds/leds-ak88.c
new file mode 100644
index 00000000000..85645c822e7
--- /dev/null
+++ b/drivers/leds/leds-ak88.c
@@ -0,0 +1,171 @@
+/*
+ * drivers/leds/leds-ak880x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+
+#include <asm/io.h>
+
+#include <mach/hardware.h>
+#include <mach/ak880x_addr.h>
+
+static void dump_regs(void)
+{
+	int i=0;
+
+	for (i=0; i<4; i++) {
+		printk("UART%d\n", i);
+		printk("UART_CONF1:	0x%x\n", __raw_readl(AK88_VA_UART + i*0x1000 + 0x0));
+		printk("UART_CONF2:	0x%x\n", __raw_readl(AK88_VA_UART + i*0x1000 + 0x4));
+		printk("DATA_CONF:	0x%x\n", __raw_readl(AK88_VA_UART + i*0x1000 + 0x8));
+		printk("BUF_THRE:	0x%x\n", __raw_readl(AK88_VA_UART + i*0x1000 + 0xC));
+	}
+
+	printk("Clock Control: 0x%x\n", __raw_readl(AK88_VA_SYSCTRL + 0xC));
+}
+
+static void lcd_backlight (int on)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(0xf0100094);
+	regval &= ~(1<<13);
+	__raw_writel(regval, 0xf0100094);
+
+	if (on) {
+		regval = __raw_readl(0xf0100098);
+		regval |= (1<<13);
+		__raw_writel(regval, 0xf0100098);
+	} else {
+		regval = __raw_readl(0xf0100098);
+		regval &= ~(1<<13);
+		__raw_writel(regval, 0xf0100098);
+	}
+}
+
+static void backlight_led_set(struct led_classdev *led_cdev,
+			   enum led_brightness value)
+{
+	if (value)
+		lcd_backlight(1);
+	else
+		lcd_backlight(0);
+}
+
+static void keypad_led_set(struct led_classdev *led_cdev,
+		enum led_brightness value)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(0xf0100094);
+	regval &= ~(1<<17);
+	__raw_writel(regval, 0xf0100094);
+
+	if (value) {
+		regval = __raw_readl(0xf0100098);
+		regval |= (1<<17);
+		__raw_writel(regval, 0xf0100098);
+	} else {
+		regval = __raw_readl(0xf0100098);
+		regval &= ~(1<<17);
+		__raw_writel(regval, 0xf0100098);
+	}
+
+	/* dump_regs(); */
+	dump_regs();
+}
+
+static struct led_classdev backlight_led = {
+	.name			= "backlight_led",
+	.brightness_set		= backlight_led_set,
+};
+
+static struct led_classdev keypad_led = {
+	.name			= "keypad_led",
+	.brightness_set		= keypad_led_set,
+};
+
+#ifdef CONFIG_PM
+static int ak880xled_suspend(struct platform_device *dev, pm_message_t state)
+{
+	led_classdev_suspend(&ak880x_led);
+	return 0;
+}
+
+static int ak880xled_resume(struct platform_device *dev)
+{
+	led_classdev_resume(&ak880x_led);
+	return 0;
+}
+#endif
+
+static int ak880xled_probe(struct platform_device *pdev)
+{
+	int ret;
+	unsigned long regval;
+
+	/* printk("Enterring %s\n", __FUNCTION__); */
+
+	regval = __raw_readl(0xf0100094);
+	regval &= ~(1<<17);
+	__raw_writel(regval, 0xf0100094);
+
+	regval = __raw_readl(0xf0100098);
+	regval |= (1<<17);
+	__raw_writel(regval, 0xf0100098);
+	
+	ret = led_classdev_register(&pdev->dev, &backlight_led);
+	if (ret)
+		return ret;
+
+	ret = led_classdev_register(&pdev->dev, &keypad_led);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ak880xled_remove(struct platform_device *pdev)
+{
+	led_classdev_unregister(&keypad_led);
+	led_classdev_unregister(&backlight_led);
+
+	return 0;
+}
+
+static struct platform_driver ak880xled_driver = {
+	.probe		= ak880xled_probe,
+	.remove		= ak880xled_remove,
+#ifdef CONFIG_PM
+	.suspend	= ak880xled_suspend,
+	.resume		= ak880xled_resume,
+#endif
+	.driver		= {
+		.name		= "ak880x-led",
+	},
+};
+
+static int __init ak880xled_init(void)
+{
+	return platform_driver_register(&ak880xled_driver);
+}
+
+static void __exit ak880xled_exit(void)
+{
+	platform_driver_unregister(&ak880xled_driver);
+}
+
+module_init(ak880xled_init);
+module_exit(ak880xled_exit);
+
+MODULE_AUTHOR("ANYKA>");
+MODULE_DESCRIPTION("AK88 EVB LED driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/leds/ledtrig-sleep.c b/drivers/leds/ledtrig-sleep.c
new file mode 100644
index 00000000000..f1640421215
--- /dev/null
+++ b/drivers/leds/ledtrig-sleep.c
@@ -0,0 +1,80 @@
+/* drivers/leds/ledtrig-sleep.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/earlysuspend.h>
+#include <linux/leds.h>
+#include <linux/suspend.h>
+
+static int ledtrig_sleep_pm_callback(struct notifier_block *nfb,
+					unsigned long action,
+					void *ignored);
+
+DEFINE_LED_TRIGGER(ledtrig_sleep)
+static struct notifier_block ledtrig_sleep_pm_notifier = {
+	.notifier_call = ledtrig_sleep_pm_callback,
+	.priority = 0,
+};
+
+static void ledtrig_sleep_early_suspend(struct early_suspend *h)
+{
+	led_trigger_event(ledtrig_sleep, LED_FULL);
+}
+
+static void ledtrig_sleep_early_resume(struct early_suspend *h)
+{
+	led_trigger_event(ledtrig_sleep, LED_OFF);
+}
+
+static struct early_suspend ledtrig_sleep_early_suspend_handler = {
+	.suspend = ledtrig_sleep_early_suspend,
+	.resume = ledtrig_sleep_early_resume,
+};
+
+static int ledtrig_sleep_pm_callback(struct notifier_block *nfb,
+					unsigned long action,
+					void *ignored)
+{
+	switch (action) {
+	case PM_HIBERNATION_PREPARE:
+	case PM_SUSPEND_PREPARE:
+		led_trigger_event(ledtrig_sleep, LED_OFF);
+		return NOTIFY_OK;
+	case PM_POST_HIBERNATION:
+	case PM_POST_SUSPEND:
+		led_trigger_event(ledtrig_sleep, LED_FULL);
+		return NOTIFY_OK;
+	}
+
+	return NOTIFY_DONE;
+}
+
+static int __init ledtrig_sleep_init(void)
+{
+	led_trigger_register_simple("sleep", &ledtrig_sleep);
+	register_pm_notifier(&ledtrig_sleep_pm_notifier);
+	register_early_suspend(&ledtrig_sleep_early_suspend_handler);
+	return 0;
+}
+
+static void __exit ledtrig_sleep_exit(void)
+{
+	unregister_early_suspend(&ledtrig_sleep_early_suspend_handler);
+	unregister_pm_notifier(&ledtrig_sleep_pm_notifier);
+	led_trigger_unregister_simple(ledtrig_sleep);
+}
+
+module_init(ledtrig_sleep_init);
+module_exit(ledtrig_sleep_exit);
+
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index e6186b338a1..5599241c667 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -865,6 +865,12 @@ config SOC_CAMERA_OV772X
 	help
 	  This is a ov772x camera driver
 
+config SOC_CAMERA_HI253
+	tristate "hi253 camera support"
+	depends on SOC_CAMERA && I2C
+	help
+	  This is a hi253 camera driver
+
 config MX1_VIDEO
 	bool
 
@@ -909,6 +915,13 @@ config VIDEO_OMAP2
 	---help---
 	  This is a v4l2 driver for the TI OMAP2 camera capture interface
 
+config VIDEO_AK98
+	tristate "AK98 Camera Interface driver"
+	depends on VIDEO_DEV && SOC_CAMERA
+	select VIDEOBUF_DMA_CONTIG
+	---help---
+	  This is a v4l2 driver for the AK98 Camera Interface
+
 #
 # USB Multimedia device configuration
 #
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index e541932a789..679f60c22b9 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -77,6 +77,7 @@ obj-$(CONFIG_SOC_CAMERA_MT9M111)	+= mt9m111.o
 obj-$(CONFIG_SOC_CAMERA_MT9T031)	+= mt9t031.o
 obj-$(CONFIG_SOC_CAMERA_MT9V022)	+= mt9v022.o
 obj-$(CONFIG_SOC_CAMERA_OV772X)		+= ov772x.o
+obj-$(CONFIG_SOC_CAMERA_HI253)		+= hi253.o
 obj-$(CONFIG_SOC_CAMERA_TW9910)		+= tw9910.o
 
 # And now the v4l2 drivers:
@@ -154,6 +155,7 @@ obj-$(CONFIG_VIDEO_MX1)			+= mx1_camera.o
 obj-$(CONFIG_VIDEO_MX3)			+= mx3_camera.o
 obj-$(CONFIG_VIDEO_PXA27x)		+= pxa_camera.o
 obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
+obj-$(CONFIG_VIDEO_AK98)	+= ak98_camera.o
 
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
 
diff --git a/drivers/media/video/ak98_camera.c b/drivers/media/video/ak98_camera.c
new file mode 100644
index 00000000000..e8945337ad6
--- /dev/null
+++ b/drivers/media/video/ak98_camera.c
@@ -0,0 +1,876 @@
+/*

+  * @file ak980x camera.c

+  * @camera host driver for ak980x

+  * @Copyright (C) 2010 Anyka (Guangzhou) Microelectronics Technology Co

+  * @author wu_daochao

+  * @date 2011-04

+  * @version 

+  * @for more information , please refer to AK980x Programmer's Guide Mannul

+  */

+

+#include <linux/init.h>

+#include <linux/module.h>

+#include <linux/types.h>

+#include <linux/errno.h>

+#include <linux/slab.h>

+#include <linux/hardirq.h>

+#include <linux/interrupt.h>

+#include <linux/irqreturn.h>

+#include <linux/sched.h>

+#include <linux/clk.h>

+#include <linux/gpio.h>

+#include <linux/delay.h>

+#include <linux/platform_device.h>

+#include <linux/videodev2.h>

+

+#include <asm/io.h>

+

+#include <media/soc_camera.h>

+#include <media/videobuf-core.h>

+#include <media/videobuf-dma-contig.h>

+

+#include "ak98_camera.h"

+

+//define the image sensor controller register address

+#undef REG32

+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))

+

+#define CAMIF_DEBUG

+#ifdef CAMIF_DEBUG

+#define CAMDBG(stuff...) printk(KERN_DEBUG"CAMIF: " stuff)

+#else

+#define CAMDBG(fmt, args...) do{}while(0)

+#endif 

+

+struct ak98_buffer {

+	struct videobuf_buffer vb;

+	const struct soc_camera_data_format	*fmt;

+	int inwork;

+};

+

+struct ak98_camera_dev {

+	struct soc_camera_host soc_host;

+	struct soc_camera_device *icd;

+

+	void __iomem	*base;		// mapped baseaddress for CI register(0x2000c000)

+	struct resource *res;

+	struct clk	*clk;		// camif clk. it's parent is spll defined in clock.c

+	unsigned int	irq;

+

+	/* members to manage the dma and buffer*/

+	struct list_head capture;	

+	struct ak98_buffer	*active;

+	spinlock_t		lock;  /* for videobuf_queue , passed in init_videobuf */

+	

+	/* personal members for platform relative */

+	unsigned long mclk;	//clock for CI, 24MHz perhaps	

+	

+};

+

+

+/* for ak98_videobuf_release */

+static void free_buffer(struct videobuf_queue *vq, struct ak98_buffer *buf)

+{

+//	struct soc_camera_device *icd = vq->priv_data;

+	struct videobuf_buffer *vb = &buf->vb;

+	int i;

+	

+	BUG_ON(in_interrupt());

+

+	CAMDBG("%s (vb=0x%p) 0x%08lx %d\n", __func__,

+		vb, vb->baddr, vb->bsize);

+

+	/* This waits until this buffer is out of danger, i.e., until it is no

+	 * longer in STATE_QUEUED or STATE_ACTIVE */

+	videobuf_waiton(vb, 0, 0);

+	videobuf_dma_contig_free(vq, vb);

+

+	/* these code enable changing the fmt without closing the device*/

+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {

+		if (vb == vq->bufs[i]) {

+			kfree(vb);

+			vq->bufs[i] = NULL;

+		}

+	}

+//	vb->state = VIDEOBUF_NEEDS_INIT;

+}

+

+/* Called when application apply buffers */

+static int ak98_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 

+								unsigned int *size)

+{

+	struct soc_camera_device *icd = vq->priv_data;

+

+	*size = icd->user_width * icd->user_height *

+		((icd->current_fmt->depth + 7) >> 3);

+

+	CAMDBG("%s: icd->user_widh = %d, icd->user_height = %d",

+			__func__, icd->user_width, icd->user_height);

+	CAMDBG("%s: icd->current_fmt->depth = %d", __func__, icd->current_fmt->depth);

+

+	      

+	if (!*count)

+		*count = 32;

+

+	while (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)

+		(*count)--;

+	

+	CAMDBG("%s: count=%d, size=%d\n", __func__, *count, *size);

+	

+	return 0;

+}

+

+/* platform independent */

+static int ak98_videobuf_prepare(struct videobuf_queue *vq,

+			struct videobuf_buffer *vb, enum v4l2_field field)

+{

+	struct soc_camera_device *icd = vq->priv_data;

+	struct ak98_buffer *buf = container_of(vb, struct ak98_buffer, vb);

+	int ret;

+

+	CAMDBG("%s: baddr = 0x%08lx, bsize = %d\n", __func__, vb->baddr, vb->bsize);

+	

+	/* Added list head initialization on alloc */

+	WARN_ON(!list_empty(&vb->queue));

+	

+	BUG_ON(NULL == icd->current_fmt);

+	

+	/* I think, in buf_prepare you only have to protect global data,

+	 * the actual buffer is yours */

+	buf->inwork = 1;

+	

+	if (buf->fmt	!= icd->current_fmt ||

+		vb->width	!= icd->user_width ||

+		vb->height	!= icd->user_height ||

+		vb->field	!= field) {

+		buf->fmt	= icd->current_fmt;

+		vb->width	= icd->user_width;

+		vb->height	= icd->user_height;

+		vb->field	= field;

+		vb->state	= VIDEOBUF_NEEDS_INIT;

+	}

+	

+	vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);

+	if (0 != vb->baddr && vb->bsize < vb->size) {

+		ret = -EINVAL;

+		goto out;

+	}

+	

+	if (vb->state == VIDEOBUF_NEEDS_INIT) {

+		ret = videobuf_iolock(vq, vb, NULL);

+		if (ret) 

+			goto fail;

+		vb->state = VIDEOBUF_PREPARED;

+	}

+	

+	buf->inwork = 0;

+	return 0;

+	

+fail:

+	free_buffer(vq, buf);

+out:

+	buf->inwork = 0;

+	return ret;

+

+}

+

+static void ak98_videobuf_queue(struct videobuf_queue *vq, 

+								struct videobuf_buffer *vb)

+{

+	struct soc_camera_device *icd = vq->priv_data;

+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+	struct ak98_camera_dev *pcdev = ici->priv;

+	struct ak98_buffer *buf = container_of(vb, struct ak98_buffer, vb);

+	u32 dmaaddr;

+	u32 size;

+

+	CAMDBG("%s (vb=0x%p) baddr = 0x%08lx, bsize = %d\n", 

+		__func__,  vb,  vb->baddr, vb->bsize);

+

+	list_add_tail(&vb->queue, &pcdev->capture);

+

+	vb->state = VIDEOBUF_ACTIVE;

+

+	if (!pcdev->active) {

+		CAMDBG("pcdev->active == NULL\n");

+		

+		pcdev->active = buf;

+

+		/* convert the vadd to paddr */

+		dmaaddr = videobuf_to_dma_contig(vb); 

+		CAMDBG("%s: dmaaddr = 0x%08x\n", __func__, dmaaddr);	

+

+		size = vb->width * vb->height;

+		CAMDBG("size = %d, width = %d, height = %d\n", 

+			size, vb->width, vb->height);

+		

+		/* setup the address of dma */

+		REG32(pcdev->base + IMG_YODD) = dmaaddr;

+		REG32(pcdev->base + IMG_UODD) = dmaaddr + size;

+		REG32(pcdev->base + IMG_VODD) = dmaaddr + size /4 * 5;	

+		

+		REG32(pcdev->base + IMG_YEVE) = dmaaddr;

+		REG32(pcdev->base + IMG_UEVE) = dmaaddr + size;

+		REG32(pcdev->base + IMG_VEVE) = dmaaddr + size /4 * 5;	

+

+		/*

+		** @bit[5]:range of input yuv data for converting to RGB: 0, 16~235; 1, 0~255

+		** @bit[4]:0, capture;					1, preview.

+		** @bit[3]:0, disable vertical scaling; 		1, enable

+	 	** @bit[2]:0, disable horizontal scaling; 	1, enable. 

+		** @bit[1:0]:data format transformed by DMA: 00, rgb888 or jpeg; 01, yuv420	

+		*/

+

+		/* write command to capture and start dma transfer */

+		REG32(pcdev->base + IMG_CMD) = (0 << 4) | (0 << 3) | (0 << 2) | 0x01 | (0 << 5);

+	}

+}

+

+static void ak98_videobuf_release(struct videobuf_queue *vq, 

+					struct videobuf_buffer *vb)

+{

+	struct ak98_buffer *buf = container_of(vb, struct ak98_buffer, vb);	

+#ifdef DEBUG

+	struct soc_camera_device *icd = vq->priv_data;

+	struct device *dev = icd->dev.parent;

+	

+	CAMDBG("%s (vb=0x%p) 0x%08lx %d\n", __func__,

+		vb, vb->baddr, vb->bsize);

+

+

+	switch (vb->state) {

+	case VIDEOBUF_ACTIVE:

+		dev_dbg(dev, "%s (active)\n", __func__);

+		break;

+	case VIDEOBUF_QUEUED:

+		dev_dbg(dev, "%s (queued)\n", __func__);

+		break;

+	case VIDEOBUF_PREPARED:

+		dev_dbg(dev, "%s (prepared)\n", __func__);

+		break;

+	default:

+		dev_dbg(dev, "%s (unknown)\n", __func__);

+		break;

+	}

+#endif	

+//	dump_stack();

+

+	free_buffer(vq, buf);

+}

+

+static struct videobuf_queue_ops ak98_videobuf_ops = {

+	.buf_setup      = ak98_videobuf_setup,

+	.buf_prepare    = ak98_videobuf_prepare,

+	.buf_queue      = ak98_videobuf_queue,

+	.buf_release    = ak98_videobuf_release,

+};

+

+/* platform code*/

+static int ak98_camera_setup_dma(struct ak98_camera_dev *pcdev)

+{

+	struct videobuf_buffer *vb = &pcdev->active->vb;

+	struct device *dev = pcdev->icd->dev.parent;

+	u32 dmaaddr;

+	u32 size;

+

+	if (unlikely(!pcdev->active)) {

+		dev_err(dev, "DMA End IRQ with no active buffer\n");

+		return -EFAULT;

+	}

+	  

+	/* setup the DMA address for transferring */

+	dmaaddr = videobuf_to_dma_contig(vb); 

+	CAMDBG("%s: dmaaddr = 0x%08x\n", __func__, dmaaddr);	

+	

+	size = vb->width * vb->height;

+	CAMDBG("size = %d, width = %d, height = %d\n", 

+		size, vb->width, vb->height);

+

+	/* setup the address of dma */

+	REG32(pcdev->base + IMG_YODD) = dmaaddr;

+	REG32(pcdev->base + IMG_UODD) = dmaaddr + size;

+	REG32(pcdev->base + IMG_VODD) = dmaaddr + size /4 * 5;	

+	

+	REG32(pcdev->base + IMG_YEVE) = dmaaddr;

+	REG32(pcdev->base + IMG_UEVE) = dmaaddr + size;

+	REG32(pcdev->base + IMG_VEVE) = dmaaddr + size /4 * 5;	

+

+	/* 

+	** @bit[5]:range of input yuv data for converting to RGB: 0, 16~235; 1, 0~255

+	** @bit[4]:0, capture;					1, preview.

+	** @bit[3]:0, disable vertical scaling; 		1, enable

+ 	** @bit[2]:0, disable horizontal scaling; 	1, enable. 

+	** @bit[1:0]:data format transformed by DMA: 00, rgb888 or jpeg; 01, yuv420	

+	*/

+

+	/* write command to continue capturing */

+	REG32(pcdev->base + IMG_CMD) = (0 << 4) | (0 << 3) | (0 << 2) | 0x01 | (0 << 5);

+

+	return 0;

+}

+

+void *getRecordSyncSamples(void);

+

+//struct captureSync{

+//	unsigned long long adcCapture_bytes;

+//	struct timeval tv;

+//};

+

+

+/* platform code please fix me */

+static void ak98_camera_wakeup(struct ak98_camera_dev *pcdev,

+			      struct videobuf_buffer *vb,

+			      struct ak98_buffer *buf)

+{

+	struct captureSync * adctime;

+	struct timeval		cam_tv;

+	unsigned long		adc_stamp;

+	unsigned long		useconds;

+	/* _init is used to debug races, see comment in mx1_camera_reqbufs() */

+	list_del_init(&vb->queue);

+	vb->state = VIDEOBUF_DONE;

+	do_gettimeofday(&cam_tv);

+	vb->field_count++;

+

+	adctime = getRecordSyncSamples();

+	

+	/* figure out the timestamp of frame */

+	adc_stamp = adctime->adcCapture_bytes  >> 5;

+

+	if (cam_tv.tv_sec > adctime->tv.tv_sec) {

+		useconds = cam_tv.tv_usec + 1000000 - adctime->tv.tv_usec;

+	} else {

+		useconds = cam_tv.tv_usec -adctime->tv.tv_usec;

+	}	

+

+	vb->ts.tv_sec = adc_stamp / 1000;

+	vb->ts.tv_usec = (adc_stamp % 1000) * 1000 + useconds;

+

+	wake_up(&vb->done);

+

+	if (list_empty(&pcdev->capture)) {

+		CAMDBG("list_empty(&pcdev->capture)\n");

+		printk(KERN_DEBUG"list_empty(&pcdev->capture)\n");

+		pcdev->active = NULL;

+		return;

+	}

+

+	pcdev->active = list_entry(pcdev->capture.next,

+				   struct ak98_buffer, vb.queue);

+	

+	ak98_camera_setup_dma(pcdev);

+

+}

+

+/* fix me */

+static irqreturn_t ak98_camera_dma_irq(int channel, void *data)

+{

+	struct ak98_camera_dev *pcdev = data;

+	struct device *dev = pcdev->icd->dev.parent;

+	struct ak98_buffer *buf;

+	struct videobuf_buffer *vb;

+	unsigned long flags;

+	unsigned long tmpValue;

+

+	spin_lock_irqsave(&pcdev->lock, flags);

+

+	tmpValue = REG32(pcdev->base + IMG_STATUS);

+	

+	if ((tmpValue & 0x01) == 0x01)			//capture end

+	{

+		if ((tmpValue & 0x02) == 0x02)		//capture error

+		{

+			goto out;

+		}

+	}

+

+	if (unlikely(!pcdev->active)) {

+		dev_err(dev, "ak98_camera_dma_irqDMA End IRQ with no active buffer\n");

+		goto out;

+	}

+	

+	vb = &pcdev->active->vb;

+	buf = container_of(vb, struct ak98_buffer, vb);

+	WARN_ON(buf->inwork || list_empty(&vb->queue));

+

+	CAMDBG("%s (vb=0x%p) 0x%08lx %d\n", __func__,

+	vb, vb->baddr, vb->bsize);

+	

+	ak98_camera_wakeup(pcdev, vb, buf);

+

+out:

+	spin_unlock_irqrestore(&pcdev->lock, flags);

+	return IRQ_HANDLED;

+}	

+

+/* for ak98_camera_add_device, the function depends on platform*/

+static void ak98_camera_activate(struct ak98_camera_dev *pcdev)

+{

+	u32 m = 0;

+	u32 temp = 0;    

+	u32 Plck_Div = 0;

+	u32 Pll2_clk = 0;

+	u32 mod = 0xff;  

+	u32 mclk = pcdev->mclk;

+

+	CAMDBG("entry %s\n", __func__);

+

+	/* set the pin of camera module as camera function */

+	ak98_group_config(ePIN_AS_CAMERA);

+

+	/* enable the clock of camera module */

+	clk_enable(pcdev->clk);

+	mdelay(1);

+

+	/*

+	** set camera mclk, SPLL CLK is 120MHz~212MHz,SPLLCLK = 120+4*m

+	** mclk = SPLLCLK/2/(PCD+1) = temp/(PCD+1)

+	*/

+	for (m = 0; m <= 23; m++)

+	{

+		temp= 60 + 2 * m;

+		if (mod > (temp % mclk))

+		{

+			mod = temp % mclk;     //mod is the minimum value

+			Pll2_clk = m & 0xff;

+			Plck_Div = (temp / mclk - 1) & 0x07;

+		}

+	}

+	

+    	/* configure the spll clk and cisclk(mclk) */

+	REG32(pcdev->base + IMG_CONFIG) &= ~((0x1f << 19) | (0x07 << 16));

+	REG32(pcdev->base + IMG_CONFIG) |= (Pll2_clk << 19) | (Plck_Div << 16);

+

+	/* setup CCIR601/CCIR656

+	* * @bit[12]:0, CCIR 601; 1, CCIR 656. 

+	* * @bit[8]:vivref, 0, active low; 1, active hight

+	* * @bit[5]:input data format:0, jpeg; 1, yuv422	

+	*/

+	REG32(pcdev->base + IMG_CONFIG) &= ~(1 << 8);

+	REG32(pcdev->base + IMG_CONFIG) &= ~(1 << 12);	

+	REG32(pcdev->base + IMG_CONFIG) |= (1 << 5);  //should be stransferred to set_fmt

+}

+

+static int ak98_camera_add_device(struct soc_camera_device *icd)

+{

+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+	struct ak98_camera_dev *pcdev = ici->priv;

+

+	CAMDBG("entry %s\n", __func__);

+

+	/* The ak98 camera host driver only support one image sensor */

+	if (pcdev->icd)

+	{

+		return -EBUSY;

+	}

+

+	/* platform code */

+	ak98_camera_activate(pcdev);

+

+	pcdev->icd = icd;

+	

+	CAMDBG("Leave %s\n", __func__);

+

+	return 0;

+}

+

+static void ak98_camera_remove_device(struct soc_camera_device *icd)

+{

+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+	struct ak98_camera_dev *pcdev = ici->priv;

+

+	CAMDBG("entry %s\n", __func__);

+

+	BUG_ON(icd != pcdev->icd);

+

+	/* disable the clock of camera module */

+	clk_disable(pcdev->clk);

+	

+	pcdev->active = NULL;   

+	pcdev->icd = NULL;

+

+	CAMDBG("Leave %s\n", __func__);	

+}

+

+/* platform independent finished */

+static int ak98_camera_querycap(struct soc_camera_host *ici,

+			       struct v4l2_capability *cap)

+{

+	/* cap->name is set by the friendly caller:-> */

+	CAMDBG("entry %s\n", __func__);

+

+	strlcpy(cap->card, "ak98 soc_camera", sizeof(cap->card));

+	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;

+	

+	CAMDBG("Leave %s\n", __func__);

+

+	return 0;	

+}

+

+static int ak98_camera_get_crop(struct soc_camera_device *icd,

+			       struct v4l2_crop *a)

+{

+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);

+

+//	CAMDBG("entry %s\n", __func__);

+

+//	return v4l2_subdev_call(sd, video, g_crop, a);

+	return -1;

+}

+

+

+static int ak98_camera_set_crop(struct soc_camera_device *icd,

+			       struct v4l2_crop *a)

+{

+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);

+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+	struct ak98_camera_dev *pcdev = ici->priv;	

+	u32 IDimgH, IDimgV;

+	u32 tmpValue;

+

+	CAMDBG("entry %s\n", __func__);

+	

+	/* setup the crop */

+	tmpValue = REG32(pcdev->base + IMG_STATUS);    //clear status

+		

+	IDimgH = 65536 / a->c.width;

+	IDimgV = 65536 / a->c.height;

+	REG32(pcdev->base + IMG_HINFO1) = a->c.width | (a->c.width << 16);

+	REG32(pcdev->base + IMG_HINFO2) = IDimgH;

+	REG32(pcdev->base + IMG_VINFO1) = a->c.height | (a->c.height << 16);

+	REG32(pcdev->base + IMG_VINFO2) = IDimgV;

+

+	return v4l2_subdev_call(sd, video, s_crop, a);

+}

+

+

+/* platform independent finished */

+static int ak98_camera_try_fmt(struct soc_camera_device *icd,

+			      struct v4l2_format *f)

+{

+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);

+

+	CAMDBG("entry %s\n", __func__);

+

+	return v4l2_subdev_call(sd, video, try_fmt, f);

+}

+

+/* platform independent finished */

+static int ak98_camera_set_fmt(struct soc_camera_device *icd,

+			      struct v4l2_format *f)

+{

+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);

+//	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+//	struct ak98_camera_dev *pcdev = ici->priv;		

+	const struct soc_camera_format_xlate *xlate;

+	struct v4l2_pix_format *pix = &f->fmt.pix;

+	int ret;

+

+	CAMDBG("entry %s\n", __func__);

+

+	xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);

+	if (!xlate) {

+		dev_warn(icd->dev.parent, "Format %x not found\n",

+			 pix->pixelformat);

+		return -EINVAL;

+	}

+

+	/*  setup the format of pixels

+	* * @bit[5]:input data format:0, jpeg; 1, yuv422

+	*/	

+//	REG32(pcdev->base + IMG_CONFIG) |= (1UL << 5);	

+

+	ret = v4l2_subdev_call(sd, video, s_fmt, f);

+	if (!ret) {

+		icd->buswidth = xlate->buswidth;

+		icd->current_fmt = xlate->host_fmt;

+	}

+	

+	CAMDBG("Leave %s\n", __func__);

+	

+	return ret;

+}

+

+/* Maybe belong platform code fix me */

+static int ak98_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)

+{

+	unsigned long camera_flags, common_flags;

+	int ret;

+

+	CAMDBG("entry %s\n", __func__);

+

+	camera_flags = icd->ops->query_bus_param(icd);

+
+	/* MX1 supports only 8bit buswidth */
+	common_flags = soc_camera_bus_param_compatible(camera_flags,
+							       CSI_BUS_FLAGS);
+	if (!common_flags) {

+		return -EINVAL;

+	}

+	

+	icd->buswidth = 8;

+

+	ret = icd->ops->set_bus_param(icd, common_flags);
+	if (ret < 0) {

+		return ret;

+	}

+	

+	CAMDBG("Leave %s\n", __func__);

+	

+	return 0;

+}

+

+/* platform independent finished*/

+static void ak98_camera_init_videobuf(struct videobuf_queue *q,

+			struct soc_camera_device *icd)

+{

+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);

+	struct ak98_camera_dev *pcdev = ici->priv;

+

+	CAMDBG("entry %s\n", __func__);

+

+	videobuf_queue_dma_contig_init(q, &ak98_videobuf_ops, icd->dev.parent,

+					&pcdev->lock,

+					V4L2_BUF_TYPE_VIDEO_CAPTURE,

+					V4L2_FIELD_NONE,

+					sizeof(struct ak98_buffer), icd);

+}

+

+/* platform independent finished*/

+static int ak98_camera_reqbufs(struct soc_camera_file *icf, 

+			struct v4l2_requestbuffers *p)

+{

+	int i;

+

+	CAMDBG("entry %s\n", __func__);

+

+	/* This is for locking debugging only. I removed spinlocks and now I

+	 * check whether .prepare is ever called on a linked buffer, or whether

+	 * a dma IRQ can occur for an in-work or unlinked buffer. Until now

+	 * it hadn't triggered */

+	for (i = 0; i < p->count; i++) {

+		struct ak98_buffer *buf = container_of(icf->vb_vidq.bufs[i],

+						      struct ak98_buffer, vb);

+		buf->inwork = 0;

+		INIT_LIST_HEAD(&buf->vb.queue);

+	}

+	

+	CAMDBG("Leave %s\n", __func__);

+	

+	return 0;

+}

+

+/* platform independent */

+static unsigned int ak98_camera_poll(struct file *file, poll_table *pt)

+{

+	struct soc_camera_file *icf = file->private_data;

+	struct ak98_buffer *buf;

+

+	buf = list_entry(icf->vb_vidq.stream.next, struct ak98_buffer,

+			 vb.stream);

+

+	poll_wait(file, &buf->vb.done, pt);

+

+	if (buf->vb.state == VIDEOBUF_DONE ||

+	    buf->vb.state == VIDEOBUF_ERROR) {

+		return POLLIN | POLLRDNORM;

+	}	

+	

+	return 0;

+}

+

+

+static struct soc_camera_host_ops ak98_soc_camera_host_ops = {

+	.owner		= THIS_MODULE,

+	.add			= ak98_camera_add_device,

+	.remove		= ak98_camera_remove_device,

+	.querycap	= ak98_camera_querycap,

+	.get_crop		= ak98_camera_get_crop,

+	.set_crop		= ak98_camera_set_crop,

+	.set_fmt		= ak98_camera_set_fmt,

+	.try_fmt		= ak98_camera_try_fmt,

+	.set_bus_param	= ak98_camera_set_bus_param,	

+	.init_videobuf	= ak98_camera_init_videobuf,

+	.reqbufs		= ak98_camera_reqbufs,

+	.poll			= ak98_camera_poll,

+};

+

+static int __init ak98_camera_probe(struct platform_device *pdev)

+{

+	struct ak98_camera_dev *pcdev;

+	struct resource *res;

+	struct clk *clk;

+	void __iomem *base;

+	unsigned int irq;

+	int err = 0;

+

+	CAMDBG("entry %s\n", __func__);

+

+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

+	irq = platform_get_irq(pdev, 0);

+	if (!res || irq < 0)

+	{

+		err = -ENODEV;

+		goto exit;

+	}

+

+	/* get camera interface clock for the whole soc_camera module */

+	clk = clk_get(&pdev->dev, "camif_clk");

+	if (IS_ERR(clk)) {

+		err = PTR_ERR(clk);

+		goto exit;

+	}

+

+	/* 

+	** @allocate memory to struct ak98_camera, including struct soc_camera_host

+	** @and struct v4l2_device 

+	*/

+	pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);

+	if (NULL == pcdev)

+	{

+		err = -ENOMEM;

+		goto exit_put_clk;

+	}

+

+	/* @initailization for struct pcdev */

+	pcdev->res = res;

+	pcdev->irq = irq;	

+	pcdev->clk = clk;

+	pcdev->mclk = 24;

+	INIT_LIST_HEAD(&pcdev->capture);

+	spin_lock_init(&pcdev->lock);

+

+	/*

+	 * Request the regions.

+	 */

+	if (!request_mem_region(res->start, resource_size(res), AK98_CAM_DRV_NAME)) {

+		err = -EBUSY;

+		goto exit_kfree;

+	}

+

+	base = ioremap(res->start, resource_size(res));

+	if (!base) {

+		err = -ENOMEM;

+		goto exit_release;

+	}

+

+	pcdev->base = base;

+

+	/* request irq */	

+	err = request_irq(irq, ak98_camera_dma_irq, IRQF_DISABLED, "ak98_camera", pcdev);

+	if (err) {

+		err = -EBUSY;

+		goto exit_iounmap;

+	}

+

+	/*

+	** @register soc_camera_host

+	*/

+	pcdev->soc_host.drv_name	= AK98_CAM_DRV_NAME;

+	pcdev->soc_host.ops		= &ak98_soc_camera_host_ops;

+	pcdev->soc_host.priv		= pcdev;

+	pcdev->soc_host.v4l2_dev.dev	= &pdev->dev;

+	pcdev->soc_host.nr		= pdev->id;

+	err = soc_camera_host_register(&pcdev->soc_host);

+	if (err) {

+		goto exit_freeirq;

+	}

+

+	return 0;

+	

+exit_freeirq:

+	free_irq(irq, pcdev);

+exit_iounmap:

+	iounmap(base);

+exit_release:

+	release_mem_region(res->start, resource_size(res));

+exit_kfree:

+	kfree(pcdev);

+exit_put_clk:

+	clk_put(clk);

+exit:

+	return err;

+}

+

+static int __exit ak98_camera_remove(struct platform_device *pdev)

+{

+

+	struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);

+	struct ak98_camera_dev *pcdev = container_of(soc_host,

+					struct ak98_camera_dev, soc_host);

+	struct resource *res;

+

+	CAMDBG("entry %s\n", __func__);

+

+	/* free or disable irq */

+	disable_irq(pcdev->irq);

+

+	clk_put(pcdev->clk);

+

+	soc_camera_host_unregister(soc_host);

+

+	iounmap(pcdev->base);

+

+	res = pcdev->res;

+	release_mem_region(res->start, resource_size(res));

+

+	kfree(pcdev);

+

+	dev_info(&pdev->dev, "AK98 Camera driver unloaded\n");

+	

+	return 0;

+}

+

+static struct platform_driver ak98_camera_driver = {

+	.probe		= ak98_camera_probe,

+//	.remove		= ak98_camera_remove, 	

+	.driver		= {

+		.name = AK98_CAM_DRV_NAME,

+		.owner = THIS_MODULE,

+	},

+};

+

+static int __init ak98_camera_init(void)

+{

+	CAMDBG("entry %s\n", __func__);

+

+	return platform_driver_register(&ak98_camera_driver);

+}

+

+static void __exit ak98_camera_exit(void)

+{

+	CAMDBG("entry %s\n", __func__);

+

+	platform_driver_unregister(&ak98_camera_driver);

+}

+

+module_init(ak98_camera_init);

+module_exit(ak98_camera_exit);

+

+MODULE_LICENSE("GPL");

+MODULE_AUTHOR("wu_daochao <wu_daochao@anyka.oa>");

+MODULE_DESCRIPTION("Driver for aks980x Camera Interface");

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

diff --git a/drivers/media/video/ak98_camera.h b/drivers/media/video/ak98_camera.h
new file mode 100644
index 00000000000..56c0db24a3a
--- /dev/null
+++ b/drivers/media/video/ak98_camera.h
@@ -0,0 +1,108 @@
+

+#ifndef __AK98_CAMERA_H

+#define __AK98_CAMERA_H

+

+#define AK98_CAM_DRV_NAME 		"ak98_camera"

+#define MAX_VIDEO_MEM			16

+

+#define CSI_BUS_FLAGS	(SOCAM_MASTER | SOCAM_HSYNC_ACTIVE_HIGH | \

+			SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_LOW | \

+			SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING | \

+			SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_LOW | \

+			SOCAM_DATAWIDTH_8)

+

+#define AK98_CAMERA_MASTER			1

+#define AK98_CAMERA_DATAWIDTH_4		2

+#define AK98_CAMERA_DATAWIDTH_5		4

+#define AK98_CAMERA_DATAWIDTH_8		8

+#define AK98_CAMERA_DATAWIDTH_9		0x10

+#define AK98_CAMERA_DATAWIDTH_10	0x20

+

+/* Image Sensor Command Register */

+#define CICR_DATA_FMT	(0x3 << 0)

+#define CICR_HSCAL_EN	(1 << 2)

+#define CICR_VSCAL_EN	(1 << 3)

+#define CICR_MODE		(1 << 4)

+#define CICR_FULL_RANGE_YUV		(1 << 5)

+#define CICR_DATA_FMT_VAL(x)	(((x) << 0) & CICR_DATA_FMT)

+

+

+/* Personal */

+

+

+/** @{@name IMAGE sensor module register and bit map define

+ */

+#define IMAGE_MODULE_BASE_ADDR                          0x2000C000      // image sensor

+/* image capturing command */

+#define IMG_CMD                                0x0000

+/* Source/Destination image horizontal length */

+#define IMG_HINFO1                           0x0004

+/* Horizontal scalling information */

+#define IMG_HINFO2					0x0008

+/* Source/Destination image vertical length */

+#define IMG_VINFO1                           0x000C

+/* Horizontal scalling information */

+#define IMG_VINFO2                         	0x0010

+

+/* DMA starting address of external RAM for Y component of odd frame */                                                        

+#define IMG_YODD                          	0x0018

+#define IMG_UODD                          	0x001c

+#define IMG_VODD                           	0x0020

+#define IMG_RGBODD                       	0x0024

+#define IMG_YEVE                            	0x0028

+#define IMG_UEVE                            	0x002c

+#define IMG_VEVE                            	0x0030

+#define IMG_RGBEVE                        	0x0034

+/* Image sensor configuration */

+#define IMG_CONFIG                        	0x0040

+/* Status of the current frame */

+#define IMG_STATUS                        	0x0060

+/* The line number of a frame when JPEG-compressed format */

+#define IMG_NUM                             	0x0080

+/* Multiple function control register */ 

+//#define MUL_FUN_CTL_REG                                 (CHIP_CONF_BASE_ADDR | 0x0058)

+/** @} */

+

+

+

+

+/** @{@name IMAGE sensor module register and bit map define

+ */

+#define IMAGE_MODULE_BASE_ADDR                          0x2000C000      // image sensor

+/* image capturing command */

+#define IMG_CMD_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0000)

+/* Source/Destination image horizontal length */

+#define IMG_HINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0004)

+/* Horizontal scalling information */

+#define IMG_HINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0008)

+/* Source/Destination image vertical length */

+#define IMG_VINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x000C)

+/* Horizontal scalling information */

+#define IMG_VINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0010)

+

+/* DMA starting address of external RAM for Y component of odd frame */                                                        

+#define IMG_YADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0018)

+#define IMG_UADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x001c)

+#define IMG_VADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0020)

+#define IMG_RGBADDR_ODD                                 (IMAGE_MODULE_BASE_ADDR | 0x0024)

+#define IMG_YADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0028)

+#define IMG_UADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x002c)

+#define IMG_VADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0030)

+#define IMG_RGBADDR_EVE                                 (IMAGE_MODULE_BASE_ADDR | 0x0034)

+/* Image sensor configuration */

+#define IMG_CONFIG_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0040)

+/* Status of the current frame */

+#define IMG_STATUS_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0060)

+/* The line number of a frame when JPEG-compressed format */

+#define IMG_NUM_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0080)

+/* Multiple function control register */ 

+#define MUL_FUN_CTL_REG                                 (CHIP_CONF_BASE_ADDR | 0x0058)

+/** @} */

+

+struct captureSync{

+	unsigned long long adcCapture_bytes;

+	struct timeval tv;

+};

+

+

+#endif

diff --git a/drivers/media/video/hi253.c b/drivers/media/video/hi253.c
new file mode 100644
index 00000000000..09a8327bc08
--- /dev/null
+++ b/drivers/media/video/hi253.c
@@ -0,0 +1,2370 @@
+/*
+ * hi253 Camera Driver
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on ov7670 and soc_camera_platform driver,
+ *
+ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
+ * Copyright (C) 2008 Magnus Damm
+ * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/videodev2.h>
+#include <mach/gpio.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/v4l2-subdev.h>
+#include <media/soc_camera.h>
+
+#include <media/hi253.h>
+
+#define SENSOR_DEBUG
+#ifdef SENSOR_DEBUG
+#define SENDBG(stuff...) printk(KERN_DEBUG"SENSOR: " stuff)
+#else
+#define SENDBG(fmt, args...) do{}while(0)
+#endif 
+
+
+/* hi253 register address */
+#define PWRCTL			0x01
+#define PAGEMODE 		0x03
+#define DEVID			0x04
+#define PLLCTL1			0x0E
+#define PLLCTL2			0x0F
+
+/* hi253 register detail */
+
+/* PAGEMODE */
+
+
+/* PWRCTL PAGEMODE 0*/
+#define SCCB_RESET 			0x02	/* Reset to default value */
+#define SOFT_SLEEP_MODE 	0x01		/* Soft sleep mode */
+
+#define SOFT_SLEEP_ON		0x01	
+#define SOFT_SLEEP_OFF		0x00
+
+/* PLLCTL */
+
+
+/* PLLCTL2 */
+
+
+/*
+ * ID
+ */
+#define HI253_PID		0x92	 /* Product ID Number */
+
+
+/*
+ * struct
+ */
+
+struct hi253_color_format {
+	const struct soc_camera_data_format *format;
+};
+
+struct hi253_win_size {
+	char                     *name;
+	__u32                     width;
+	__u32                     height;
+//	unsigned char             com7_bit;
+	const struct regval_list *regs;
+};
+
+struct hi253_priv {
+	struct v4l2_subdev                	subdev;
+	struct hi253_camera_info        	*info;
+	const struct hi253_color_format 	*fmt;
+	const struct hi253_win_size     	*win;
+	int                               		model;
+};
+
+#define ENDMARKER { 0xff, 0xff }
+
+
+/*
+ * register setting for initialize 
+ */
+
+u32 HI253_pv_HI253_exposure_lines = 0x0249f0;
+u32 HI253_cp_HI253_exposure_lines = 0;
+
+
+
+/**---------------------------------------------------------------------------*
+ ** 						Local Variables 								 *
+ **---------------------------------------------------------------------------*/
+
+/*lint -save -e533 */
+const struct regval_list hi253_sensor_yuv640X480[]=
+{
+	{0x03, 0x18},
+	{0x10, 0x07},
+	{0x11, 0x00},
+	{0x12, 0x20},
+	{0x20, 0x02},
+	{0x21, 0x84}, //80},
+	{0x22, 0x01},
+	{0x23, 0xe0},
+	{0x24, 0x00},
+	{0x25, 0x04}, //00},
+	{0x26, 0x00},
+	{0x27, 0x00},
+	{0x28, 0x02},
+	{0x29, 0x84}, //80},
+	{0x2a, 0x01},
+	{0x2b, 0xe0},
+	{0x2c, 0x14},
+	{0x2d, 0x00},
+	{0x2e, 0x14},
+	{0x2f, 0x00},
+	{0x30, 0x66},
+	{0xff, 0xff},
+};
+
+const struct regval_list hi253_sensor_yuv1280X960[]=
+{  
+//{0x01, 0xf1}, //sleep off	
+//{0x0e, 0x00}, //PLL off
+//{0x03, 0x00},
+//{0x10, 0x00},
+//{0x11, 0x93}, //Windowing On, 1Frame Skip 93
+
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x20},
+{0x20, 0x05},
+{0x21, 0x00},
+{0x22, 0x03},
+{0x23, 0xc0},
+{0x24, 0x00},
+{0x25, 0x04},
+{0x26, 0x00},
+{0x27, 0x04},
+{0x28, 0x05},
+{0x29, 0x04},
+{0x2a, 0x03},
+{0x2b, 0xc4},
+{0x2c, 0x0a},
+{0x2d, 0x00},
+{0x2e, 0x0a},
+{0x2f, 0x00},
+{0x30, 0x41}, //41->44
+
+//{0x03, 0x20},
+//{0x10, 0x1c},
+//{0x03, 0x22},
+//{0x10, 0x6a},
+
+//{0x03, 0x00}, //Sleep Off	
+//{0x01, 0xc0}, // f8
+
+{0xff, 0xff},
+//{HI253_WRITE_DELAY,100}
+
+};
+
+const struct regval_list hi253_sensor_yuv352X288[] =
+	{  
+//	{0x01, 0x59}, //sleep on	
+//	{0x0e, 0x03}, //PLL on
+//	{0x0e, 0x73}, //PLLx2
+//	{0x03, 0x00},
+//	{0x10, 0x00},
+//	{0x11, 0x93}, //Windowing On, 1Frame Skip 93
+	
+	{0x03, 0x18},
+	{0x10, 0x07},
+	{0x11, 0x00},
+	{0x12, 0x20},
+	
+	{0x20, 0x01},   // 352
+	{0x21, 0x60},
+	{0x22, 0x01},  // 288
+	{0x23, 0x20},
+	
+	{0x24, 0x00},
+	{0x25, 0x04},
+	{0x26, 0x00},
+	{0x27, 0x04},
+	
+	{0x28, 0x01},
+	{0x29, 0x64},
+	{0x2a, 0x01},
+	{0x2b, 0x24},
+	
+	{0x2c, 0x21},
+	{0x2d, 0x55},
+	{0x2e, 0x24},
+	{0x2f, 0x5D},
+	
+	{0x30, 0x47}, //47
+
+//	{0x03, 0x00}, //Sleep Off	
+//	{0x01, 0x58}, // f8
+	
+	{0xff, 0xff},
+	//{HI253_WRITE_DELAY,100}
+
+};
+
+const struct regval_list hi253_sensor_yuv800X600[]=
+{
+{0x01, 0xf1}, //sleep off	
+{0x0e, 0x00}, //PLL off
+{0x03, 0x00},
+{0x10, 0x10},
+{0x11, 0x93}, //Windowing On, 1Frame Skip 93
+
+{0x03, 0x18},
+{0x10, 0x00},
+{0x11, 0x00},
+{0x12, 0x20},
+
+{0x03, 0x20},
+{0x10, 0x1c},
+{0x03, 0x22},
+{0x10, 0x6a},
+
+{0x03, 0x00}, //Sleep Off	
+{0x01, 0xc0}, // f8
+
+{0xff, 0xff},
+//{HI253_WRITE_DELAY,100}
+
+};
+
+const struct regval_list hi253_sensor_yuv1600X1200[]=
+{
+//{0x01, 0xf1}, //sleep off	
+//{0x0e, 0x00}, //PLL off
+//{0x03, 0x00},
+//{0x10, 0x00},
+//{0x11, 0x90}, //Windowing On, 1Frame Skip 93
+
+{0x03, 0x18},
+{0x10, 0x00},
+{0x11, 0x00},
+{0x12, 0x20},
+
+//{0x03, 0x20},
+//{0x10, 0x1c},
+//{0x03, 0x22},
+//{0x10, 0x6a},
+
+//{0x03, 0x00}, //Sleep Off	
+//{0x01, 0xc0}, // f8
+
+{0xff, 0xff},
+//{HI253_WRITE_DELAY,100}
+
+};
+
+
+/******************************************************************************/
+// Description: set brightness 
+// Global resource dependence: 
+// Author:
+// Note:
+//		level  must smaller than 8
+/******************************************************************************/
+ const struct regval_list HI253_brightness_tab[][7]=
+{
+{
+{0x03,0x10}, //-3
+{0x40,0xb0}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, //-2
+{0x40,0xa0}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, //-1
+{0x40,0x90}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, //0
+{0x40,0x00}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, // 1
+{0x40,0x10}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, // 2
+{0x40,0x20}, 
+{0xff,0xff},
+},
+{
+{0x03,0x10}, // +3
+{0x40,0x30}, 
+{0xff,0xff},
+},
+
+};
+
+const struct regval_list HI253_YUV_640X480[]=
+{
+{0x01, 0x61}, //sleep on   //backup : 0x01, 0xf9
+{0x08, 0x0f}, //Hi-Z on
+{0x01, 0x60}, //sleep off
+
+{0x03, 0x00}, // Dummy 750us START
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00}, // Dummy 750us END
+
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //PLLx2
+
+{0x03, 0x00}, // Dummy 750us START
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00}, // Dummy 750us END
+
+{0x0e, 0x00}, //PLL off
+{0x01, 0x51}, //sleep on
+{0x08, 0x00}, //Hi-Z off
+{0x01, 0xf3},
+{0x01, 0xf1},
+
+// PAGE 20
+{0x03, 0x20}, //page 20
+{0x10, 0x1c}, //ae off
+
+// PAGE 22
+{0x03, 0x22}, //page 22
+{0x10, 0x69}, //awb off
+
+//Initial Start
+{0x03, 0x00},
+{0x10, 0x00}, //Sub 1/2_Preview1 Mode, VSync Type2  00
+{0x11, 0x90}, //Windowing On, 1Frame Skip, Not rata
+{0x12, 0x04}, //rinsing edge  05
+{0x0b, 0xaa}, //ESD Check Register
+{0x0c, 0xaa}, //ESD Check Register
+{0x0d, 0xaa}, //ESD Check Register
+{0x20, 0x00}, //Windowing start point Y
+{0x21, 0x04},
+{0x22, 0x00}, //Windowing start point X
+{0x23, 0x07},
+{0x24, 0x04},
+{0x25, 0xb0},
+{0x26, 0x06},
+{0x27, 0x40}, //WINROW END
+{0x40, 0x01}, //Hblank 408
+{0x41, 0x98}, 
+{0x42, 0x00}, //Vblank 20
+{0x43, 0x14},
+{0x45, 0x04},
+{0x46, 0x18},
+{0x47, 0xd8},
+
+//BLC
+{0x80, 0x2e},
+{0x81, 0x7e},
+{0x82, 0x90},
+{0x83, 0x00},
+{0x84, 0x0c},
+{0x85, 0x00},
+{0x90, 0x0a}, //BLC_TIME_TH_ON
+{0x91, 0x0a}, //BLC_TIME_TH_OFF 
+{0x92, 0xd8}, //BLC_AG_TH_ON
+{0x93, 0xd0}, //BLC_AG_TH_OFF
+{0x94, 0x75},
+{0x95, 0x70},
+{0x96, 0xdc},
+{0x97, 0xfe},
+{0x98, 0x38},
+
+//OutDoor  BLC
+{0x99, 0x43},
+{0x9a, 0x43},
+{0x9b, 0x43},
+{0x9c, 0x43},
+
+//Dark BLC
+{0xa0, 0x00},
+{0xa2, 0x00},
+{0xa4, 0x00},
+{0xa6, 0x00},
+
+//Normal BLC
+{0xa8, 0x43},
+{0xaa, 0x43},
+{0xac, 0x43},
+{0xae, 0x43},
+
+
+/////// PAGE 2 START ///////
+{0x03, 0x02},
+{0x12, 0x03},
+{0x13, 0x03},
+{0x16, 0x00},
+{0x17, 0x8C},
+{0x18, 0x4c}, //Double_AG off
+{0x19, 0x00},
+{0x1a, 0x39}, //ADC400->560
+{0x1c, 0x09},
+{0x1d, 0x40},
+{0x1e, 0x30},
+{0x1f, 0x10},
+
+{0x20, 0x77},
+{0x21, 0xde},
+{0x22, 0xa7},
+{0x23, 0x30}, //CLAMP
+{0x27, 0x3c},
+{0x2b, 0x80},
+{0x2e, 0x11},
+{0x2f, 0xa1},
+{0x30, 0x05}, //For Hi-253 never no change 0x05
+
+{0x50, 0x20},
+{0x52, 0x01},
+{0x55, 0x1c},
+{0x56, 0x11},
+{0x5d, 0xa2},
+{0x5e, 0x5a},
+
+{0x60, 0x87},
+{0x61, 0x99},
+{0x62, 0x88},
+{0x63, 0x97},
+{0x64, 0x88},
+{0x65, 0x97},
+
+{0x67, 0x0c},
+{0x68, 0x0c},
+{0x69, 0x0c},
+
+{0x72, 0x89},
+{0x73, 0x96},
+{0x74, 0x89},
+{0x75, 0x96},
+{0x76, 0x89},
+{0x77, 0x96},
+
+{0x7c, 0x85},
+{0x7d, 0xaf},
+{0x80, 0x01},
+{0x81, 0x7f},
+{0x82, 0x13},
+
+{0x83, 0x24},
+{0x84, 0x7d},
+{0x85, 0x81},
+{0x86, 0x7d},
+{0x87, 0x81},
+
+{0x92, 0x48},
+{0x93, 0x54},
+{0x94, 0x7d},
+{0x95, 0x81},
+{0x96, 0x7d},
+{0x97, 0x81},
+
+{0xa0, 0x02},
+{0xa1, 0x7b},
+{0xa2, 0x02},
+{0xa3, 0x7b},
+{0xa4, 0x7b},
+{0xa5, 0x02},
+{0xa6, 0x7b},
+{0xa7, 0x02},
+
+{0xa8, 0x85},
+{0xa9, 0x8c},
+{0xaa, 0x85},
+{0xab, 0x8c},
+{0xac, 0x10},
+{0xad, 0x16},
+{0xae, 0x10},
+{0xaf, 0x16},
+
+{0xb0, 0x99},
+{0xb1, 0xa3},
+{0xb2, 0xa4},
+{0xb3, 0xae},
+{0xb4, 0x9b},
+{0xb5, 0xa2},
+{0xb6, 0xa6},
+{0xb7, 0xac},
+{0xb8, 0x9b},
+{0xb9, 0x9f},
+{0xba, 0xa6},
+{0xbb, 0xaa},
+{0xbc, 0x9b},
+{0xbd, 0x9f},
+{0xbe, 0xa6},
+{0xbf, 0xaa},
+
+{0xc4, 0x2c},
+{0xc5, 0x43},
+{0xc6, 0x63},
+{0xc7, 0x79},
+
+{0xc8, 0x2d},
+{0xc9, 0x42},
+{0xca, 0x2d},
+{0xcb, 0x42},
+{0xcc, 0x64},
+{0xcd, 0x78},
+{0xce, 0x64},
+{0xcf, 0x78},
+
+{0xd0, 0x0a},
+{0xd1, 0x09},
+{0xd4, 0x0a}, //DCDC_TIME_TH_ON
+{0xd5, 0x0a}, //DCDC_TIME_TH_OFF 
+{0xd6, 0xd8}, //DCDC_AG_TH_ON
+{0xd7, 0xd0}, //DCDC_AG_TH_OFF
+{0xe0, 0xc4},
+{0xe1, 0xc4},
+{0xe2, 0xc4},
+{0xe3, 0xc4},
+{0xe4, 0x00},
+{0xe8, 0x80},
+{0xe9, 0x40},
+{0xea, 0x7f},
+
+/////// PAGE 3 ///////
+{0x03, 0x03},
+{0x10, 0x10},
+
+/////// PAGE 10 START ///////
+{0x03, 0x10},
+{0x10, 0x01}, // CrYCbY // For Demoset 0x03
+{0x12, 0x30},
+{0x20, 0x00},
+
+{0x30, 0x00},
+{0x31, 0x00},
+{0x32, 0x00},
+{0x33, 0x00},
+
+{0x34, 0x30},
+{0x35, 0x00},
+{0x36, 0x00},
+{0x38, 0x00},
+{0x3e, 0x58},
+{0x3f, 0x00},
+
+{0x40, 0x80}, // YOFS
+{0x41, 0x00}, // DYOFS
+
+{0x60, 0x67},
+{0x61, 0x7c}, //7e //8e //88 //80
+{0x62, 0x7c}, //7e //8e //88 //80
+{0x63, 0x50}, //Double_AG 50->30
+{0x64, 0x41},
+
+{0x66, 0x42},
+{0x67, 0x20},
+
+{0x6a, 0x80}, //8a
+{0x6b, 0x84}, //74
+{0x6c, 0x80}, //7e //7a
+{0x6d, 0x80}, //8e
+
+//Don't touch//////////////////////////
+//{0x72, 0x84},
+//{0x76, 0x19},
+//{0x73, 0x70},
+//{0x74, 0x68},
+//{0x75, 0x60}, // white protection ON
+//{0x77, 0x0e}, //08 //0a
+//{0x78, 0x2a}, //20
+//{0x79, 0x08},
+////////////////////////////////////////
+
+/////// PAGE 11 START ///////
+{0x03, 0x11},
+{0x10, 0x7f},
+{0x11, 0x40},
+{0x12, 0x0a}, // Blue Max-Filter Delete
+{0x13, 0xbb},
+
+{0x26, 0x31}, // Double_AG 31->20
+{0x27, 0x34}, // Double_AG 34->22
+{0x28, 0x0f},
+{0x29, 0x10},
+{0x2b, 0x30},
+{0x2c, 0x32},
+
+//Out2 D-LPF th
+{0x30, 0x70},
+{0x31, 0x10},
+{0x32, 0x58},
+{0x33, 0x09},
+{0x34, 0x06},
+{0x35, 0x03},
+
+//Out1 D-LPF th
+{0x36, 0x70},
+{0x37, 0x18},
+{0x38, 0x58},
+{0x39, 0x09},
+{0x3a, 0x06},
+{0x3b, 0x03},
+
+//Indoor D-LPF th
+{0x3c, 0x80},
+{0x3d, 0x18},
+{0x3e, 0xa0}, //80
+{0x3f, 0x0c},
+{0x40, 0x09},
+{0x41, 0x06},
+
+{0x42, 0x80},
+{0x43, 0x18},
+{0x44, 0xa0}, //80
+{0x45, 0x12},
+{0x46, 0x10},
+{0x47, 0x10},
+
+{0x48, 0x90},
+{0x49, 0x40},
+{0x4a, 0x80},
+{0x4b, 0x13},
+{0x4c, 0x10},
+{0x4d, 0x11},
+
+{0x4e, 0x80},
+{0x4f, 0x30},
+{0x50, 0x80},
+{0x51, 0x13},
+{0x52, 0x10},
+{0x53, 0x13},
+
+{0x54, 0x11},
+{0x55, 0x17},
+{0x56, 0x20},
+{0x57, 0x01},
+{0x58, 0x00},
+{0x59, 0x00},
+
+{0x5a, 0x1f}, //18
+{0x5b, 0x00},
+{0x5c, 0x00},
+
+{0x60, 0x3f},
+{0x62, 0x60},
+{0x70, 0x06},
+
+/////// PAGE 12 START ///////
+{0x03, 0x12},
+{0x20, 0x0f},
+{0x21, 0x0f},
+
+{0x25, 0x00}, //0x30
+
+{0x28, 0x00},
+{0x29, 0x00},
+{0x2a, 0x00},
+
+{0x30, 0x50},
+{0x31, 0x18},
+{0x32, 0x32},
+{0x33, 0x40},
+{0x34, 0x50},
+{0x35, 0x70},
+{0x36, 0xa0},
+
+//Out2 th
+{0x40, 0xa0},
+{0x41, 0x40},
+{0x42, 0xa0},
+{0x43, 0x90},
+{0x44, 0x90},
+{0x45, 0x80},
+
+//Out1 th
+{0x46, 0xb0},
+{0x47, 0x55},
+{0x48, 0xa0},
+{0x49, 0x90},
+{0x4a, 0x90},
+{0x4b, 0x80},
+
+//Indoor th
+{0x4c, 0xb0},
+{0x4d, 0x40},
+{0x4e, 0x90},
+{0x4f, 0x90},
+{0x50, 0xa0},
+{0x51, 0x80},
+
+//Dark1 th
+{0x52, 0xb0},
+{0x53, 0x60},
+{0x54, 0xc0},
+{0x55, 0xc0},
+{0x56, 0xc0},
+{0x57, 0x80},
+
+//Dark2 th
+{0x58, 0x90},
+{0x59, 0x40},
+{0x5a, 0xd0},
+{0x5b, 0xd0},
+{0x5c, 0xe0},
+{0x5d, 0x80},
+
+//Dark3 th
+{0x5e, 0x88},
+{0x5f, 0x40},
+{0x60, 0xe0},
+{0x61, 0xe0},
+{0x62, 0xe0},
+{0x63, 0x80},
+
+{0x70, 0x15},
+{0x71, 0x01}, //Don't Touch register
+
+{0x72, 0x18},
+{0x73, 0x01}, //Don't Touch register
+
+{0x74, 0x25},
+{0x75, 0x15},
+
+{0x80, 0x20},
+{0x81, 0x40},
+{0x82, 0x65},
+{0x85, 0x1a},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x90, 0x5d}, //For Preview
+
+//Dont Touch register
+{0xD0, 0x0c},
+{0xD1, 0x80},
+{0xD2, 0x67},
+{0xD3, 0x00},
+{0xD4, 0x00},
+{0xD5, 0x02},
+{0xD6, 0xff},
+{0xD7, 0x18},
+//End
+{0x3b, 0x06},
+{0x3c, 0x06},
+
+{0xc5, 0x00},//55->48
+{0xc6, 0x00},//48->40
+
+/////// PAGE 13 START ///////
+{0x03, 0x13},
+//Edge
+{0x10, 0xcb},
+{0x11, 0x7b},
+{0x12, 0x07},
+{0x14, 0x00},
+
+{0x20, 0x15},
+{0x21, 0x13},
+{0x22, 0x33},
+{0x23, 0x05},
+{0x24, 0x09},
+
+{0x25, 0x0a},
+
+{0x26, 0x18},
+{0x27, 0x30},
+{0x29, 0x12},
+{0x2a, 0x50},
+
+//Low clip th
+{0x2b, 0x02},
+{0x2c, 0x02},
+{0x25, 0x06},
+{0x2d, 0x0c},
+{0x2e, 0x12},
+{0x2f, 0x12},
+
+//Out2 Edge
+{0x50, 0x10},
+{0x51, 0x14},
+{0x52, 0x12},
+{0x53, 0x0c},
+{0x54, 0x0f},
+{0x55, 0x0c},
+
+//Out1 Edge
+{0x56, 0x10},
+{0x57, 0x13},
+{0x58, 0x12},
+{0x59, 0x0c},
+{0x5a, 0x0f},
+{0x5b, 0x0c},
+
+//Indoor Edge
+{0x5c, 0x0a},
+{0x5d, 0x0b},
+{0x5e, 0x0a},
+{0x5f, 0x08},
+{0x60, 0x09},
+{0x61, 0x08},
+
+//Dark1 Edge
+{0x62, 0x08},
+{0x63, 0x08},
+{0x64, 0x08},
+{0x65, 0x06},
+{0x66, 0x06},
+{0x67, 0x06},
+
+//Dark2 Edge
+{0x68, 0x07},
+{0x69, 0x07},
+{0x6a, 0x07},
+{0x6b, 0x05},
+{0x6c, 0x05},
+{0x6d, 0x05},
+
+//Dark3 Edge
+{0x6e, 0x07},
+{0x6f, 0x07},
+{0x70, 0x07},
+{0x71, 0x05},
+{0x72, 0x05},
+{0x73, 0x05},
+
+//2DY
+{0x80, 0xfd},
+{0x81, 0x1f},
+{0x82, 0x05},
+{0x83, 0x31},
+
+{0x90, 0x05},
+{0x91, 0x05},
+{0x92, 0x33},
+{0x93, 0x30},
+{0x94, 0x03},
+{0x95, 0x14},
+{0x97, 0x20},
+{0x99, 0x20},
+
+{0xa0, 0x01},
+{0xa1, 0x02},
+{0xa2, 0x01},
+{0xa3, 0x02},
+{0xa4, 0x05},
+{0xa5, 0x05},
+{0xa6, 0x07},
+{0xa7, 0x08},
+{0xa8, 0x07},
+{0xa9, 0x08},
+{0xaa, 0x07},
+{0xab, 0x08},
+
+//Out2 
+{0xb0, 0x22},
+{0xb1, 0x2a},
+{0xb2, 0x28},
+{0xb3, 0x22},
+{0xb4, 0x2a},
+{0xb5, 0x28},
+
+//Out1 
+{0xb6, 0x22},
+{0xb7, 0x2a},
+{0xb8, 0x28},
+{0xb9, 0x22},
+{0xba, 0x2a},
+{0xbb, 0x28},
+
+//Indoor 
+{0xbc, 0x25},
+{0xbd, 0x2a},
+{0xbe, 0x27},
+{0xbf, 0x25},
+{0xc0, 0x2a},
+{0xc1, 0x27},
+
+//Dark1
+{0xc2, 0x1e},
+{0xc3, 0x24},
+{0xc4, 0x20},
+{0xc5, 0x1e},
+{0xc6, 0x24},
+{0xc7, 0x20},
+
+//Dark2
+{0xc8, 0x18},
+{0xc9, 0x20},
+{0xca, 0x1e},
+{0xcb, 0x18},
+{0xcc, 0x20},
+{0xcd, 0x1e},
+
+//Dark3 
+{0xce, 0x18},
+{0xcf, 0x20},
+{0xd0, 0x1e},
+{0xd1, 0x18},
+{0xd2, 0x20},
+{0xd3, 0x1e},
+
+/////// PAGE 14 START ///////
+{0x03, 0x14},
+{0x10, 0x11},
+
+{0x14, 0x80}, // GX
+{0x15, 0x80}, // GY
+{0x16, 0x80}, // RX
+{0x17, 0x80}, // RY
+{0x18, 0x80}, // BX
+{0x19, 0x80}, // BY
+
+{0x20, 0x60}, //X 60 //a0
+{0x21, 0x80}, //Y
+
+{0x22, 0x80},
+{0x23, 0x80},
+{0x24, 0x80},
+
+{0x30, 0xc8},
+{0x31, 0x2b},
+{0x32, 0x00},
+{0x33, 0x00},
+{0x34, 0x90},
+
+{0x40, 0x48}, //31
+{0x50, 0x34}, //23 //32
+{0x60, 0x29}, //1a //27
+{0x70, 0x34}, //23 //32
+
+/////// PAGE 15 START ///////
+{0x03, 0x15},
+{0x10, 0x0f},
+
+//Rstep H 16
+//Rstep L 14
+{0x14, 0x42}, //CMCOFSGH_Day //4c
+{0x15, 0x32}, //CMCOFSGM_CWF //3c
+{0x16, 0x24}, //CMCOFSGL_A //2e
+{0x17, 0x2f}, //CMC SIGN
+
+//CMC_Default_CWF
+{0x30, 0x8f},
+{0x31, 0x59},
+{0x32, 0x0a},
+{0x33, 0x15},
+{0x34, 0x5b},
+{0x35, 0x06},
+{0x36, 0x07},
+{0x37, 0x40},
+{0x38, 0x87}, //86
+
+//CMC OFS L_A
+{0x40, 0x92},
+{0x41, 0x1b},
+{0x42, 0x89},
+{0x43, 0x81},
+{0x44, 0x00},
+{0x45, 0x01},
+{0x46, 0x89},
+{0x47, 0x9e},
+{0x48, 0x28},
+
+//{0x40, 0x93},
+//{0x41, 0x1c},
+//{0x42, 0x89},
+//{0x43, 0x82},
+//{0x44, 0x01},
+//{0x45, 0x01},
+//{0x46, 0x8a},
+//{0x47, 0x9d},
+//{0x48, 0x28},
+
+//CMC POFS H_DAY
+{0x50, 0x02},
+{0x51, 0x82},
+{0x52, 0x00},
+{0x53, 0x07},
+{0x54, 0x11},
+{0x55, 0x98},
+{0x56, 0x00},
+{0x57, 0x0b},
+{0x58, 0x8b},
+
+{0x80, 0x03},
+{0x85, 0x40},
+{0x87, 0x02},
+{0x88, 0x00},
+{0x89, 0x00},
+{0x8a, 0x00},
+
+/////// PAGE 16 START ///////
+{0x03, 0x16},
+{0x10, 0x31},
+{0x18, 0x5e},// Double_AG 5e->37
+{0x19, 0x5d},// Double_AG 5e->36
+{0x1a, 0x0e},
+{0x1b, 0x01},
+{0x1c, 0xdc},
+{0x1d, 0xfe},
+
+//GMA Default
+{0x30, 0x00},
+{0x31, 0x0a},
+{0x32, 0x1f},
+{0x33, 0x33},
+{0x34, 0x53},
+{0x35, 0x6c},
+{0x36, 0x81},
+{0x37, 0x94},
+{0x38, 0xa4},
+{0x39, 0xb3},
+{0x3a, 0xc0},
+{0x3b, 0xcb},
+{0x3c, 0xd5},
+{0x3d, 0xde},
+{0x3e, 0xe6},
+{0x3f, 0xee},
+{0x40, 0xf5},
+{0x41, 0xfc},
+{0x42, 0xff},
+
+{0x50, 0x00},
+{0x51, 0x09},
+{0x52, 0x1f},
+{0x53, 0x37},
+{0x54, 0x5b},
+{0x55, 0x76},
+{0x56, 0x8d},
+{0x57, 0xa1},
+{0x58, 0xb2},
+{0x59, 0xbe},
+{0x5a, 0xc9},
+{0x5b, 0xd2},
+{0x5c, 0xdb},
+{0x5d, 0xe3},
+{0x5e, 0xeb},
+{0x5f, 0xf0},
+{0x60, 0xf5},
+{0x61, 0xf7},
+{0x62, 0xf8},
+
+{0x70, 0x00},
+{0x71, 0x08},
+{0x72, 0x17},
+{0x73, 0x2f},
+{0x74, 0x53},
+{0x75, 0x6c},
+{0x76, 0x81},
+{0x77, 0x94},
+{0x78, 0xa4},
+{0x79, 0xb3},
+{0x7a, 0xc0},
+{0x7b, 0xcb},
+{0x7c, 0xd5},
+{0x7d, 0xde},
+{0x7e, 0xe6},
+{0x7f, 0xee},
+{0x80, 0xf4},
+{0x81, 0xfa},
+{0x82, 0xff},
+
+/////// PAGE 17 START ///////
+{0x03, 0x17},
+{0x10, 0xf7},
+
+/////// PAGE 20 START ///////
+//AE Start
+{0x03, 0x20},
+{0x11, 0x1c},
+{0x18, 0x30},
+{0x1a, 0x08},
+{0x20, 0x01}, //05_lowtemp Y Mean off
+{0x21, 0x30},
+{0x22, 0x10},
+{0x23, 0x00},
+{0x24, 0x00}, //Uniform Scene Off
+
+{0x28, 0xe7},
+{0x29, 0x0d}, //20100305 ad->0d
+
+// MTK set up 		anti banding --> 1/100 s
+{0x2a, 0xff},
+{0x2b, 0x04}, //f4->Adaptive off
+
+{0x2c, 0xc2},
+{0x2d, 0xcf},  //ff->AE Speed option
+{0x2e, 0x33},
+{0x30, 0x78}, //f8
+{0x32, 0x03},
+{0x33, 0x2e},
+{0x34, 0x30},
+{0x35, 0xd4},
+{0x36, 0xfe},
+{0x37, 0x32},
+{0x38, 0x04},
+
+{0x39, 0x22}, //AE_escapeC10
+{0x3a, 0xde}, //AE_escapeC11
+
+{0x3b, 0x22}, //AE_escapeC1
+{0x3c, 0xde}, //AE_escapeC2
+//Y_Frame TH
+{0x50, 0x45},
+{0x51, 0x88},
+
+{0x56, 0x03},
+{0x57, 0xf7},
+{0x58, 0x14},
+{0x59, 0x88},
+{0x5a, 0x04},
+
+//New Weight For Samsung
+//{0x60, 0xaa},
+//{0x61, 0xaa},
+//{0x62, 0xaa},
+//{0x63, 0xaa},
+//{0x64, 0xaa},
+//{0x65, 0xaa},
+//{0x66, 0xab},
+//{0x67, 0xEa},
+//{0x68, 0xab},
+//{0x69, 0xEa},
+//{0x6a, 0xaa},
+//{0x6b, 0xaa},
+//{0x6c, 0xaa},
+//{0x6d, 0xaa},
+//{0x6e, 0xaa},
+//{0x6f, 0xaa},
+
+{0x60, 0x55}, // AEWGT1
+{0x61, 0x55}, // AEWGT2
+{0x62, 0x6a}, // AEWGT3
+{0x63, 0xa9}, // AEWGT4
+{0x64, 0x6a}, // AEWGT5
+{0x65, 0xa9}, // AEWGT6
+{0x66, 0x6a}, // AEWGT7
+{0x67, 0xa9}, // AEWGT8
+{0x68, 0x6b}, // AEWGT9
+{0x69, 0xe9}, // AEWGT10
+{0x6a, 0x6a}, // AEWGT11
+{0x6b, 0xa9}, // AEWGT12
+{0x6c, 0x6a}, // AEWGT13
+{0x6d, 0xa9}, // AEWGT14
+{0x6e, 0x55}, // AEWGT15
+{0x6f, 0x55}, // AEWGT16
+
+{0x70, 0x76}, //6e
+{0x71, 0x00}, //82(+8)->+0
+
+// haunting control
+{0x76, 0x43},
+{0x77, 0xe2}, //04
+{0x78, 0x23}, //Yth1
+{0x79, 0x42}, //Yth2
+{0x7a, 0x23}, //23
+{0x7b, 0x22}, //22
+{0x7d, 0x23},
+
+{0x83, 0x01}, //EXP Normal 33.33 fps 
+{0x84, 0x5f}, 
+{0x85, 0x00}, 
+
+{0x86, 0x02}, //EXPMin 5859.38 fps
+{0x87, 0x00}, 
+
+{0x88, 0x04}, //EXP Max 10.00 fps 
+{0x89, 0x92}, 
+{0x8a, 0x00}, 
+
+{0x8B, 0x75}, //EXP100 
+{0x8C, 0x00}, 
+{0x8D, 0x61}, //EXP120 
+{0x8E, 0x00}, 
+
+{0x9c, 0x18}, //EXP Limit 488.28 fps 
+{0x9d, 0x00}, 
+{0x9e, 0x02}, //EXP Unit 
+{0x9f, 0x00}, 
+
+//AE_Middle Time option
+//{0xa0, 0x03},
+//{0xa1, 0xa9},
+//{0xa2, 0x80},
+
+{0xb0, 0x18},
+{0xb1, 0x14}, //ADC 400->560
+{0xb2, 0xe0}, //d0
+{0xb3, 0x18},
+{0xb4, 0x1a},
+{0xb5, 0x44},
+{0xb6, 0x2f},
+{0xb7, 0x28},
+{0xb8, 0x25},
+{0xb9, 0x22},
+{0xba, 0x21},
+{0xbb, 0x20},
+{0xbc, 0x1f},
+{0xbd, 0x1f},
+
+//AE_Adaptive Time option
+//{0xc0, 0x10},
+//{0xc1, 0x2b},
+//{0xc2, 0x2b},
+//{0xc3, 0x2b},
+//{0xc4, 0x08},
+
+{0xc8, 0x80},
+{0xc9, 0x40},
+
+/////// PAGE 22 START ///////
+{0x03, 0x22},
+{0x10, 0xfd},
+{0x11, 0x2e},
+{0x19, 0x01}, // Low On //
+{0x20, 0x30},
+{0x21, 0x80},
+{0x24, 0x01},
+//{0x25, 0x00}, //7f New Lock Cond & New light stable
+
+{0x30, 0x80},
+{0x31, 0x80},
+{0x38, 0x11},
+{0x39, 0x34},
+
+{0x40, 0xf4},
+{0x41, 0x55}, //44
+{0x42, 0x33}, //43
+
+{0x43, 0xf6},
+{0x44, 0x55}, //44
+{0x45, 0x44}, //33
+{0x46, 0x00},
+
+//MTK set up 
+{0x47, 0x94},
+
+{0x50, 0xb2},
+{0x51, 0x81},
+{0x52, 0x98},
+
+{0x80, 0x40}, //3e
+{0x81, 0x20},
+{0x82, 0x3e},
+
+{0x83, 0x5e}, //5e
+{0x84, 0x1e}, //24
+{0x85, 0x5e}, //54 //56 //5a
+{0x86, 0x22}, //24 //22
+
+{0x87, 0x49},
+{0x88, 0x39},
+{0x89, 0x37}, //38
+{0x8a, 0x28}, //2a
+
+{0x8b, 0x41}, //47
+{0x8c, 0x39}, 
+{0x8d, 0x34}, 
+{0x8e, 0x28}, //2c
+
+{0x8f, 0x53}, //4e
+{0x90, 0x52}, //4d
+{0x91, 0x51}, //4c
+{0x92, 0x4e}, //4a
+{0x93, 0x4a}, //46
+{0x94, 0x45},
+{0x95, 0x3d},
+{0x96, 0x31},
+{0x97, 0x28},
+{0x98, 0x24},
+{0x99, 0x20},
+{0x9a, 0x20},
+
+{0x9b, 0x77},
+{0x9c, 0x77},
+{0x9d, 0x48},
+{0x9e, 0x38},
+{0x9f, 0x30},
+
+{0xa0, 0x60},
+{0xa1, 0x34},
+{0xa2, 0x6f},
+{0xa3, 0xff},
+
+{0xa4, 0x14}, //1500fps
+{0xa5, 0x2c}, // 700fps
+{0xa6, 0xcf},
+
+{0xad, 0x40},
+{0xae, 0x4a},
+
+{0xaf, 0x28},  // low temp Rgain
+{0xb0, 0x26},  // low temp Rgain
+
+{0xb1, 0x00}, //0x20 -> 0x00 0405 modify
+{0xb4, 0xea},
+{0xb8, 0xa0}, //a2: b-2, R+2  //b4 B-3, R+4 lowtemp
+{0xb9, 0x00},
+
+/////// PAGE 20 ///////
+{0x03, 0x20},
+{0x10, 0x8c},
+
+// PAGE 20
+{0x03, 0x20}, //page 20
+{0x10, 0x9c}, //ae off
+
+// PAGE 22
+{0x03, 0x22}, //page 22
+{0x10, 0xe9}, //awb off
+
+// PAGE 0
+{0x03, 0x00},
+{0x0e, 0x03}, //PLL On
+{0x0e, 0x73}, //PLLx2
+
+{0x03, 0x00}, // Dummy 750us
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+{0x03, 0x00},
+
+{0x03, 0x00}, // Page 0
+{0x01, 0x60}, // Sleep Off
+
+{0x03, 0x18},
+{0x10, 0x07},
+{0x11, 0x00},
+{0x12, 0x20},
+{0x20, 0x02},
+{0x21, 0x84}, //80},
+{0x22, 0x01},
+{0x23, 0xe0},
+{0x24, 0x00},
+{0x25, 0x04}, //00},
+{0x26, 0x00},
+{0x27, 0x00},
+{0x28, 0x02},
+{0x29, 0x84}, //80},
+{0x2a, 0x01},
+{0x2b, 0xe0},
+{0x2c, 0x14},
+{0x2d, 0x00},
+{0x2e, 0x14},
+{0x2f, 0x00},
+{0x30, 0x66},
+
+{0x03, 0x22},	//CAM_WB_AUTO		
+{0x11, 0x2e},				
+{0x83, 0x5e},
+{0x84, 0x1e},
+{0x85, 0x5e},
+{0x86, 0x22},
+
+
+{0xff, 0xff},
+//{HI253_WRITE_DELAY,1}
+};
+
+const struct regval_list HI253_wb_tab[6][9]=
+{
+{
+{0x03, 0x22},	//CAM_WB_AUTO		
+{0x11, 0x2e},				
+{0x83, 0x5e},
+{0x84, 0x1e},
+{0x85, 0x5e},
+{0x86, 0x22},
+{0xff, 0xff},
+{0xff, 0xff},
+{0xff, 0xff}
+},
+	
+{
+{0x03, 0x22}, //CAM_WB_CLOUD
+{0x11, 0x28},
+{0x80, 0x71},
+{0x82, 0x2b},
+{0x83, 0x72},
+{0x84, 0x70},
+{0x85, 0x2b},
+{0x86, 0x28},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x22}, //CAM_WB_DAYLIGHT
+{0x11, 0x28},		  
+{0x80, 0x59},
+{0x82, 0x29},
+{0x83, 0x60},
+{0x84, 0x50},
+{0x85, 0x2f},
+{0x86, 0x23},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x22}, //CAM_WB_INCANDESCENCE
+{0x11, 0x28},		  
+{0x80, 0x29},
+{0x82, 0x54},
+{0x83, 0x2e},
+{0x84, 0x23},
+{0x85, 0x58},
+{0x86, 0x4f},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x22}, //CAM_WB_TUNGSTEN
+{0x80, 0x24},
+{0x81, 0x20},
+{0x82, 0x58},
+{0x83, 0x27},
+{0x84, 0x22},
+{0x85, 0x58},
+{0x86, 0x52},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x22}, //CAM_WB_FLUORESCENT
+{0x11, 0x28},
+{0x80, 0x41},
+{0x82, 0x42},
+{0x83, 0x44},
+{0x84, 0x34},
+{0x85, 0x46},
+{0x86, 0x3a},
+{0xff, 0xff}
+}
+};
+
+/* for effect */
+const struct regval_list HI253_effect_tab[6][8]=
+{
+{
+{0x03, 0x10}, //CAM_EFFECT_ENC_NORMAL:
+{0x11, 0x03},
+{0x12, 0x30},
+{0x13, 0x02},
+{0x44, 0x80},
+{0x45, 0x80},
+{0xff, 0xff},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x10}, //C  AM_EFFECT_ENC_SEPIA
+{0x11, 0x03},
+{0x12, 0x33},
+{0x13, 0x02},
+{0x44, 0x70},
+{0x45, 0x98},
+{0xff, 0xff},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x10}, //CAM_EFFECT_ENC_SEPIAGREEN
+{0x11, 0x03},
+{0x12, 0x03},
+{0x13, 0x02},
+{0x40, 0x00},
+{0x44, 0x30},
+{0x45, 0x50},
+{0xff, 0xff}
+},
+
+
+{
+{0x03, 0x10}, //CAM_EFFECT_ENC_GRAYSCALE
+{0x11, 0x03},
+{0x12, 0x03},
+{0x13, 0x02},
+{0x40, 0x00},
+{0x44, 0x80},
+{0x45, 0x80},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x10}, //CAM_EFFECT_ENC_COLORINV
+{0x11, 0x03},
+{0x12, 0x08},
+{0x13, 0x02},
+{0x14, 0x00},
+{0xff, 0xff},
+{0xff, 0xff},
+{0xff, 0xff}
+},
+
+{
+{0x03, 0x10}, //CAM_EFFECT_ENC_SEPIABLUE
+{0x11, 0x03},
+{0x12, 0x03},
+{0x40, 0x00},
+{0x13, 0x02},
+{0x44, 0xb0},
+{0x45, 0x40},
+{0xff, 0xff}
+},
+
+};
+
+
+/*
+ * register setting for window size
+ */
+	
+static const struct regval_list hi253_uxga_regs[] = {
+	{ 0x03, 0x00 },
+	{ 0x20, 0x00 },
+	{ 0x21, 0x0a },
+	{ 0x22, 0x00 },
+	{ 0x23, 0x0a },
+		
+	{ 0x40, 0x01 },
+	{ 0x41, 0x68 },
+	{ 0x42, 0x00 },
+	{ 0x43, 0x14 },
+	
+	{ 0x03, 0x10 }, 	//page10
+	{ 0x3f, 0x00 },
+	{ 0x03, 0x12 },
+	{ 0x20, 0x0f },
+	{ 0x21, 0x0f }, 			
+	{ 0x90, 0x5d },
+		
+	{ 0x03, 0x13 },
+	{ 0x80, 0xfd }, 	
+		
+	{ 0x03, 0x00 }, //select uxga
+	{ 0x10, 0x00 },
+	ENDMARKER,
+};
+
+static const struct regval_list hi253_sxga_regs[] = {
+	{ 0x03, 0x00 },
+	{ 0x20, 0x00 },
+	{ 0x21, 0x04 },  //uxga 0x0a
+	{ 0x22, 0x00 },
+	{ 0x23, 0x07 },  //uxga 0x0a
+	
+	{ 0x40, 0x01 },
+	{ 0x41, 0x98 },  //uxga 0x68
+	{ 0x42, 0x00 },
+	{ 0x43, 0x14 },
+//page10
+	{ 0x03, 0x10 },  	
+	{ 0x3f, 0x00 },
+//page12	
+	{ 0x03, 0x12 },
+	{ 0x20, 0x0f },
+	{ 0x21, 0x0f },				
+	{ 0x90, 0x5d },
+//page123	
+	{ 0x03, 0x13 },  
+	{ 0x80, 0xfd },		
+	
+	{ 0x03, 0x00 },	
+	{ 0x10, 0x11 }, //select svga
+	ENDMARKER,
+};
+
+static const struct regval_list hi253_vga_regs[] = {
+	ENDMARKER,
+};
+
+//static const struct regval_list * const hi253_vga_regs = &hi253_sensor_yuv640X480;
+
+
+
+
+
+
+
+
+/*
+ * supported format list
+ */
+
+#define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
+static const struct soc_camera_data_format hi253_fmt_lists[] = {
+	{
+		SETFOURCC(YUYV),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_JPEG,
+	},
+	{
+		SETFOURCC(YVYU),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_JPEG,
+	},
+	{
+		SETFOURCC(UYVY),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_JPEG,
+	},
+	{
+		SETFOURCC(RGB555),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+	},
+	{
+		SETFOURCC(RGB555X),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+	},
+	{
+		SETFOURCC(RGB565),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+	},
+	{
+		SETFOURCC(RGB565X),
+		.depth      = 16,
+		.colorspace = V4L2_COLORSPACE_SRGB,
+	},
+};
+
+/*
+ * color format list
+ */
+static const struct hi253_color_format hi253_cfmts[] = {
+	{
+		.format = &hi253_fmt_lists[0],
+	},
+	{
+		.format = &hi253_fmt_lists[1],
+	},
+	{
+		.format = &hi253_fmt_lists[2],
+	},
+	{
+		.format = &hi253_fmt_lists[3],
+	},
+	{
+		.format = &hi253_fmt_lists[4],
+	},
+	{
+		.format = &hi253_fmt_lists[5],
+	},
+	{
+		.format = &hi253_fmt_lists[6],
+	},
+};
+
+
+/*
+ * window size list
+ */
+ #define UXGA_WIDTH	1600
+ #define UXGA_HEIGHT	1200
+#define SVGA_WIDTH   800
+#define SVGA_HEIGHT  600
+#define VGA_WIDTH   640
+#define VGA_HEIGHT  480
+#define GP_WIDTH		352
+#define GP_HEIGHT		288
+#define SXGA_WIDTH  1280
+#define SXGA_HEIGHT 960
+#define MAX_WIDTH   1600
+#define MAX_HEIGHT  1200
+
+static const struct hi253_win_size hi253_win_uxga = {
+	.name     = "UXGA",
+	.width    = UXGA_WIDTH,
+	.height   = UXGA_HEIGHT,
+	.regs     = hi253_sensor_yuv1600X1200,
+};
+
+static const struct hi253_win_size hi253_win_sxga = {
+	.name     = "SXGA",
+	.width    = SXGA_WIDTH,
+	.height   = SXGA_HEIGHT,
+	.regs     = hi253_sensor_yuv1280X960,
+};
+
+static const struct hi253_win_size hi253_win_svga = {
+	.name     = "SVGA",
+	.width    = SVGA_WIDTH,
+	.height   = SVGA_HEIGHT,
+	.regs     = hi253_sensor_yuv800X600,
+};
+
+static const struct hi253_win_size hi253_win_vga = {
+	.name     = "VGA",
+	.width    = VGA_WIDTH,
+	.height   = VGA_HEIGHT,
+	.regs     = hi253_sensor_yuv640X480,
+};
+
+static const struct hi253_win_size hi253_win_3gp = {
+	.name     = "3GP",
+	.width    = GP_WIDTH,
+	.height   = GP_HEIGHT,
+	.regs     = hi253_sensor_yuv352X288,
+};
+
+static const struct v4l2_queryctrl hi253_controls[] = {
+	{
+		.id		= V4L2_CID_VFLIP,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "Flip Vertically",
+		.minimum	= 0,
+		.maximum	= 1,
+		.step		= 1,
+		.default_value	= 0,
+	},
+	{
+		.id		= V4L2_CID_HFLIP,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "Flip Horizontally",
+		.minimum	= 0,
+		.maximum	= 1,
+		.step		= 1,
+		.default_value	= 0,
+	},
+	{
+		.id		= V4L2_CID_BAND_STOP_FILTER,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Band-stop filter",
+		.minimum	= 0,
+		.maximum	= 256,
+		.step		= 1,
+		.default_value	= 0,
+	},
+};
+static int  hi253_mask_set(struct i2c_client *client,
+					  u8  command,
+					  u8  mask,
+					  u8  set)
+{
+	s32 val = i2c_smbus_read_byte_data(client, command);
+	if (val < 0)
+		return val;
+
+ 	val &= ~mask;
+	val |= set & mask;
+
+	return i2c_smbus_write_byte_data(client, command, val);
+}
+
+static int hi253_write_array(struct i2c_client *client,
+			      const struct regval_list *vals)
+{
+	while (vals->reg_num != 0xff) {
+		int ret = i2c_smbus_write_byte_data(client,
+						    vals->reg_num,
+						    vals->value);
+		if (ret < 0)
+			return ret;
+		vals++;
+	}
+	return 0;
+}
+
+
+/********************* MTK mt6253 ********************/
+
+void hi253_sensor_setting_init(struct i2c_client *client)
+{
+	u32 iEcount;
+	unsigned char temp = 0;
+
+	SENDBG("entry %s\n", __func__);
+	for(iEcount=0;(!((0xff==(hi253_sensor_yuv640X480[iEcount].reg_num))&&(0xff==(hi253_sensor_yuv640X480[iEcount].value))));iEcount++)
+	{	
+		i2c_smbus_write_byte_data(client, hi253_sensor_yuv640X480[iEcount].reg_num, hi253_sensor_yuv640X480[iEcount].value);
+	}
+	
+	i2c_smbus_write_byte_data(client, 0x03, 0x00);
+	temp = i2c_smbus_read_byte_data(client, 0x11);
+	temp |= 0x03;
+	i2c_smbus_write_byte_data(client, 0x03, 0x00);
+	i2c_smbus_write_byte_data(client, 0x11, temp);
+	SENDBG("leave %s\n", __func__);
+	
+}
+
+
+/*
+ * general function
+ */
+
+static struct hi253_priv *to_hi253(const struct i2c_client *client)
+{
+	return container_of(i2c_get_clientdata(client), struct hi253_priv, subdev);
+}
+
+static int hi253_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+
+	switch (ctrl->id) {
+	case V4L2_CID_VFLIP:
+//		ctrl->value = priv->flag_vflip;
+		break;
+	case V4L2_CID_HFLIP:
+//		ctrl->value = priv->flag_hflip;
+		break;
+	case V4L2_CID_BAND_STOP_FILTER:
+//		ctrl->value = priv->band_filter;
+		break;
+	}
+	return 0;
+}
+
+static int hi253_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+	int ret = 0;
+	u8 val;
+
+	printk(KERN_INFO "Entry hi253_s_ctrl:\n");
+	switch (ctrl->id) {
+		case V4L2_CID_DO_WHITE_BALANCE:
+			printk(KERN_INFO "V4L2_CID_DO_WHITE_BALANCE=0x%08x", V4L2_CID_DO_WHITE_BALANCE);
+			printk(KERN_INFO "value = %d\n", ctrl->value);
+			if (ctrl->value < 7) {
+				hi253_write_array(client, &HI253_wb_tab[ctrl->value -1][0]);
+			}
+			break;
+			
+		case V4L2_CID_COLORFX:
+			printk(KERN_INFO "V4L2_CID_COLORFX=0x%08x", V4L2_CID_COLORFX);
+			printk(KERN_INFO "value = %d\n", ctrl->value);
+			if (ctrl->value < 7) {
+				hi253_write_array(client, &HI253_effect_tab[ctrl->value -1][0]);
+			}
+
+			break;
+		default:
+			break;
+	}
+
+	printk(KERN_INFO "Leave hi253_s_ctrl\n");
+
+	return ret;
+}
+
+
+static int hi253_g_chip_ident(struct v4l2_subdev *sd,
+			       struct v4l2_dbg_chip_ident *id)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+
+	id->ident    = priv->model;
+	id->revision = 0;
+
+	return 0;
+}
+
+static const struct hi253_win_size *hi253_select_win(u32 width, u32 height)
+{
+	const struct hi253_win_size *win;
+
+	SENDBG("entry %s\n", __func__);
+
+	win = &hi253_win_vga;	
+	/* default is UXVGA */
+	if (width == 1600 && height == 1200) {
+		win = &hi253_win_uxga;	
+		SENDBG("mach %s: width = %d, height = %d\n", 
+		win->name, win->width, win->height);
+	}
+	
+	if (width == 1280 && height == 960) {
+		SENDBG("mach %s: width = %d, height = %d\n", 
+		win->name, win->width, win->height);		
+		win = &hi253_win_sxga;	
+	}
+	if (width == 640 && height == 480) {
+		win = &hi253_win_vga;
+		SENDBG("mach %s: width = %d, height = %d\n", 
+		win->name, win->width, win->height);		
+	}	
+	if (width == 800 && height == 600) {
+		win = &hi253_win_sxga;	
+		SENDBG("mach %s: width = %d, height = %d\n", 
+		win->name, win->width, win->height);		
+	}
+
+	if (width == 352 && height == 288) {
+		printk(KERN_DEBUG"width = %d && height = %d\n", width, height);
+		win = &hi253_win_3gp;			
+		SENDBG("mach %s: width = %d, height = %d\n", 
+		win->name, win->width, win->height);		
+	}
+
+	SENDBG("leave %s\n", __func__);
+	
+	return win;
+}
+
+static int hi253_set_params(struct i2c_client *client,
+			     u32 *width, u32 *height, u32 pixfmt)
+{
+	struct hi253_priv *priv = to_hi253(client);
+	int ret = -EINVAL;
+	int i;
+
+	SENDBG("entry %s\n", __func__);
+	
+	/*
+	 * select format for priv->fmt
+	 */
+	priv->fmt = NULL;
+	for (i = 0; i < ARRAY_SIZE(hi253_cfmts); i++) {
+		if (pixfmt == hi253_cfmts[i].format->fourcc) {
+			priv->fmt = hi253_cfmts + i;
+			break;
+		}
+	}
+	if (!priv->fmt)
+		goto hi253_set_fmt_error;
+ 
+	/*
+	 * select win for priv->win
+	 */
+	priv->win = hi253_select_win(*width, *height);
+	
+	/*
+	 * set size format
+	 */
+	SENDBG("select %s\n", priv->win->name);
+	 
+	ret = hi253_write_array(client, priv->win->regs);
+
+	if (ret < 0)
+		goto hi253_set_fmt_error;
+
+	*width = priv->win->width;
+	*height = priv->win->height;
+
+	SENDBG("leave %s succeedded!\n", __func__);
+	return 0;
+
+hi253_set_fmt_error:
+	priv->win = NULL;
+	priv->fmt = NULL;
+	
+	SENDBG("leave %s failed!\n", __func__);
+	
+	return ret;
+}
+
+/* first called by soc_camera_prove to initialize lcd->user_width... */
+static int hi253_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+
+	SENDBG("entry %s\n", __func__);
+
+	if (!priv->win || !priv->fmt) {
+//		SENDBG("select UXGA for first time\n");
+		u32 width = GP_WIDTH; 
+		u32 height = GP_HEIGHT;
+		int ret = hi253_set_params(client, &width, &height,
+					    V4L2_PIX_FMT_YUYV);
+		if (ret < 0)
+			return ret;
+	}
+
+	f->type			= V4L2_BUF_TYPE_VIDEO_CAPTURE;
+
+	pix->width		= priv->win->width;
+	pix->height		= priv->win->height;
+	pix->pixelformat	= priv->fmt->format->fourcc;
+	pix->colorspace		= priv->fmt->format->colorspace;
+	pix->field		= V4L2_FIELD_NONE;
+
+	SENDBG("leave %s\n", __func__);
+
+	return 0;
+}
+
+
+static int hi253_try_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_format *f)
+{
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+	const struct hi253_win_size *win;
+
+	SENDBG("entry %s\n", __func__);
+
+	/*
+	 * select suitable win
+	 */
+	win = hi253_select_win(pix->width, pix->height);
+
+	pix->width  = win->width;
+	pix->height = win->height;
+	pix->field  = V4L2_FIELD_NONE;
+	
+	SENDBG("entry %s\n", __func__);
+
+	return 0;
+}
+
+static int hi253_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
+{
+	struct i2c_client *client = sd->priv;
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+
+	SENDBG("entry %s\n", __func__);
+
+	return hi253_set_params(client, &pix->width, &pix->height,
+				 pix->pixelformat);
+}
+
+static unsigned long hi253_query_bus_param(struct soc_camera_device *icd)
+{
+	struct i2c_client *client = to_i2c_client(to_soc_camera_control(icd));
+	struct hi253_priv *priv = i2c_get_clientdata(client);
+	struct soc_camera_link *icl = to_soc_camera_link(icd);
+	unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
+		SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
+		SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
+
+	SENDBG("entry %s\n", __func__);
+
+	return soc_camera_apply_sensor_flags(icl, flags);
+}
+
+static int hi253_set_bus_param(struct soc_camera_device *icd,
+				unsigned long		  flags)
+{
+	SENDBG("entry %s\n", __func__);
+
+	return 0;
+} 
+
+static int hi253_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
+{
+	struct i2c_client *client = sd->priv;
+
+	SENDBG("entry %s\n", __func__);
+
+	a->bounds.left			= 0;
+	a->bounds.top			= 0;
+	a->bounds.width			= MAX_WIDTH;
+	a->bounds.height		= MAX_HEIGHT;
+	a->defrect.width		= VGA_WIDTH;
+	a->defrect.height		= VGA_HEIGHT;
+	a->type				= V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	a->pixelaspect.numerator	= 1;
+	a->pixelaspect.denominator	= 1;
+
+	/* fix me */
+	hi253_write_array(client, HI253_YUV_640X480);
+	hi253_mask_set(client, PWRCTL, SOFT_SLEEP_MODE, SOFT_SLEEP_ON);
+
+	
+	SENDBG("leave %s\n", __func__);
+	
+	return 0;
+}
+
+static int hi253_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+
+	SENDBG("entry %s\n", __func__);
+
+	a->c.left	= 0;
+	a->c.top	= 0;
+	a->c.width	= priv->win->width;
+	a->c.height	= priv->win->height;
+	a->type		= V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	
+	SENDBG("leave %s\n", __func__);
+
+	return 1;
+}
+
+
+
+static int hi253_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+	struct hi253_win_size *win;
+
+	SENDBG("leave %s\n", __func__);
+
+	/* select suitable windows */
+	win = hi253_select_win(a->c.width, a->c.height);
+
+	/* set sensor register */
+	hi253_write_array(client, priv->win->regs);	
+	
+	SENDBG("leave %s\n", __func__);
+	
+	return 0;
+}
+
+/*
+ * soc_camera_ops function
+ */
+
+static int hi253_s_stream(struct v4l2_subdev *sd, int enable)
+{
+	struct i2c_client *client = sd->priv;
+	struct hi253_priv *priv = to_hi253(client);
+	unsigned char temp = 0;
+
+	SENDBG("entry %s\n", __func__);
+
+	if (!enable) {
+		// sleep on
+		hi253_mask_set(client, PWRCTL, SOFT_SLEEP_MODE, SOFT_SLEEP_ON);
+		return 0;
+	}
+	
+	// sleep on
+//	hi253_mask_set(client, PWRCTL, SOFT_SLEEP_MODE, SOFT_SLEEP_ON);
+
+	/* init the sensor with mt6253 setting */
+//	hi253_sensor_setting_init(client);
+
+//	SENDBG("select %s\n", priv->win->name);
+//	hi253_write_array(client, 	priv->win->regs);
+//	hi253_write_array(client, HI253_YUV_640X480);
+
+	// sleep off
+	hi253_mask_set(client, PWRCTL, SOFT_SLEEP_MODE, SOFT_SLEEP_OFF);
+
+	SENDBG("leave %s\n", __func__);
+	
+	return 0;
+}
+
+static int hi253_video_probe(struct soc_camera_device *icd,
+			      struct i2c_client *client)
+{
+	struct hi253_priv *priv = to_hi253(client);
+	u8				pid;
+	const char         *devname;
+
+	SENDBG("entry %s\n", __func__);
+
+	/*
+	 * We must have a parent by now. And it cannot be a wrong one.
+	 * So this entire test is completely redundant.
+	 */
+	if (!icd->dev.parent ||
+	    to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
+		return -ENODEV;
+
+	/*
+	 * hi253 only use 8 or 10 bit bus width
+	 */
+	if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
+	    SOCAM_DATAWIDTH_8  != priv->info->buswidth) {
+		dev_err(&client->dev, "bus width error\n");
+		return -ENODEV;
+	}
+
+	icd->formats     = hi253_fmt_lists;
+	icd->num_formats = ARRAY_SIZE(hi253_fmt_lists);
+
+	/*
+	 * check and show product ID and manufacturer ID
+	 */
+	pid = i2c_smbus_read_byte_data(client, DEVID);
+
+	if (pid != HI253_PID) {
+		dev_err(&client->dev,  "Product ID error %x\n", pid);
+		return -ENODEV;	
+	}
+	
+	devname 	= "hi253";
+	priv->model = pid;
+
+	dev_info(&client->dev,
+		 "Probing %s Product ID %0x\n",
+		 devname, pid);
+
+	SENDBG("leave %s\n", __func__);
+
+	return 0;
+}
+
+static struct soc_camera_ops hi253_ops = {
+	.set_bus_param		= hi253_set_bus_param,
+	.query_bus_param	= hi253_query_bus_param,
+	.controls		= hi253_controls,
+	.num_controls		= ARRAY_SIZE(hi253_controls),
+};
+
+static struct v4l2_subdev_core_ops hi253_subdev_core_ops = {
+	.g_ctrl		= hi253_g_ctrl,
+	.s_ctrl		= hi253_s_ctrl,
+	.g_chip_ident	= hi253_g_chip_ident,
+};
+
+static struct v4l2_subdev_video_ops hi253_subdev_video_ops = {
+	.s_stream	= hi253_s_stream,
+	.g_fmt		= hi253_g_fmt,
+	.s_fmt		= hi253_s_fmt,
+	.try_fmt	= hi253_try_fmt,
+	.cropcap	= hi253_cropcap,
+	.g_crop		= hi253_g_crop,
+	.s_crop		= hi253_s_crop,
+};
+
+static struct v4l2_subdev_ops hi253_subdev_ops = {
+	.core	= &hi253_subdev_core_ops,
+	.video	= &hi253_subdev_video_ops,
+};
+
+/*
+ * i2c_driver function
+ */
+
+static int hi253_probe(struct i2c_client *client,
+			const struct i2c_device_id *did)
+{
+	struct hi253_priv        *priv;
+	struct hi253_camera_info *info;
+	struct soc_camera_device  *icd = client->dev.platform_data;
+	struct i2c_adapter        *adapter = to_i2c_adapter(client->dev.parent);
+	struct soc_camera_link    *icl;
+	int                        ret;
+
+	SENDBG("entry %s\n", __func__);
+
+	if (!icd) {
+		dev_err(&client->dev, "HI253: missing soc-camera data!\n");
+		return -EINVAL;
+	}
+
+	icl = to_soc_camera_link(icd);
+	if (!icl)
+		return -EINVAL;
+	
+	info = container_of(icl, struct hi253_camera_info, link);
+
+	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+		dev_err(&adapter->dev,
+			"I2C-Adapter doesn't support "
+			"I2C_FUNC_SMBUS_BYTE_DATA\n");
+		return -EIO;
+	}
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		return -ENOMEM;
+	}	
+
+	priv->info = info;
+
+	v4l2_i2c_subdev_init(&priv->subdev, client, &hi253_subdev_ops);
+
+	icd->ops		= &hi253_ops;
+
+	ret = hi253_video_probe(icd, client);
+	
+	if (ret) {
+		icd->ops = NULL;
+		i2c_set_clientdata(client, NULL);
+		kfree(priv);
+	}
+
+	SENDBG("leave %s\n", __func__);
+
+	return ret;
+}
+
+static int hi253_remove(struct i2c_client *client)
+{
+	struct hi253_priv *priv = to_hi253(client);
+	struct soc_camera_device *icd = client->dev.platform_data;
+
+	icd->ops = NULL;
+	i2c_set_clientdata(client, NULL);
+	kfree(priv);
+	return 0;
+}
+
+static const struct i2c_device_id hi253_id[] = {
+	{ "hi253", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, hi253);
+
+static struct i2c_driver hi253_i2c_driver = {
+	.driver = {
+		.name = "hi253",
+	},
+	.probe    = hi253_probe,
+	.remove   = hi253_remove,
+	.id_table = hi253_id,
+};
+
+/*
+ * module function
+ */
+
+static int __init hi253_module_init(void)
+{
+	
+	SENDBG("entry %s\n", __func__);
+
+	return i2c_add_driver(&hi253_i2c_driver);
+}
+
+static void __exit hi253_module_exit(void)
+{
+	SENDBG("entry %s\n", __func__);
+
+	i2c_del_driver(&hi253_i2c_driver);
+}
+
+module_init(hi253_module_init);
+module_exit(hi253_module_exit);
+
+MODULE_DESCRIPTION("SoC Camera driver for hi253");
+MODULE_AUTHOR("wu_daochao@anyka.oa");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov772x.c b/drivers/media/video/ov772x.c
index eccb40ab7fe..130397e842e 100644
--- a/drivers/media/video/ov772x.c
+++ b/drivers/media/video/ov772x.c
@@ -21,11 +21,13 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/videodev2.h>
+#include <mach/gpio.h>
 #include <media/v4l2-chip-ident.h>
 #include <media/v4l2-subdev.h>
 #include <media/soc_camera.h>
-#include <media/ov772x.h>
+//#include <media/ov772x.h>
 
+#include "ov772x.h"
 /*
  * register offset
  */
@@ -373,14 +375,12 @@
 #define OV7725  0x7721
 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
 
-/*
- * struct
- */
 struct regval_list {
 	unsigned char reg_num;
 	unsigned char value;
 };
 
+
 struct ov772x_color_format {
 	const struct soc_camera_data_format *format;
 	u8 dsp3;
@@ -581,6 +581,66 @@ static const struct v4l2_queryctrl ov772x_controls[] = {
 	},
 };
 
+/* function to setup the initialize parameter */
+static int ov772x_set_param(struct i2c_client *client, const unsigned char tabParameter[])
+{ 
+	int i = 0;
+	unsigned char temp_value;
+
+	while (1)
+	{
+		if ((END_FLAG == tabParameter[i]) && (END_FLAG == tabParameter[i + 1])) 
+		{
+			break;
+		}
+		else if (DELAY_FLAG == tabParameter[i])
+		{
+			mdelay(tabParameter[i + 1]);
+		}
+		else
+		{
+//			sccb_write_data(CAMERA_SCCB_ADDR, tabParameter[i], (T_U8 *)(&tabParameter[i + 1]), 1);
+			i2c_smbus_write_byte_data(client, tabParameter[i], tabParameter[i + 1]);
+
+
+
+            if (!((tabParameter[i] == 0x12) && (tabParameter[i + 1] & 0x80))
+                && !((tabParameter[i] == 0xc9) && (tabParameter[i + 1] & 0x60)))
+            {                
+//                temp_value = sccb_read_data(CAMERA_SCCB_ADDR, tabParameter[i]);
+			temp_value = i2c_smbus_read_byte_data(client, tabParameter[i]);
+
+                if (temp_value != tabParameter[i + 1])
+                {
+                    printk(KERN_INFO "set parameter error!\n");
+                    printk(KERN_INFO "reg 0x%x write data is 0x%x, read data is 0x%x!\n", tabParameter[i], tabParameter[i + 1], temp_value);
+
+                    return 1;
+                }
+            }
+        }
+        i += 2;
+    }
+
+    return 0;
+}
+
+
+static int ov772x_camera_init(struct i2c_client *client)
+{
+    if (ov772x_set_param(client, INIT_TAB))
+    {
+        return 1;
+    }
+    else
+    {        
+//        night_mode = CAMERA_DAY_MODE;
+        return 0;
+    }        
+}
+
+
+struct ______________________________________{};
 
 /*
  * general function
@@ -651,6 +711,12 @@ static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
 
 	dev_dbg(&client->dev, "format %s, win %s\n",
 		priv->fmt->format->name, priv->win->name);
+	
+	if (ov772x_camera_init(client)) {
+		printk(KERN_INFO "initialize the sensor failed!\n");
+	} else {
+		printk(KERN_INFO "initialize the sensor succeedded!\n");
+	}
 
 	return 0;
 }
@@ -658,6 +724,8 @@ static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
 static int ov772x_set_bus_param(struct soc_camera_device *icd,
 				unsigned long		  flags)
 {
+	printk(KERN_DEBUG "Entry ov772x_set_bus_param:\n");
+	printk(KERN_DEBUG "Leave ov772x_set_bus_param!\n");
 	return 0;
 }
 
@@ -669,7 +737,7 @@ static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
 	unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
 		SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
 		SOCAM_DATA_ACTIVE_HIGH | priv->info->buswidth;
-
+	
 	return soc_camera_apply_sensor_flags(icl, flags);
 }
 
@@ -792,6 +860,8 @@ static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
 	__u32 diff;
 	const struct ov772x_win_size *win;
 
+	printk(KERN_DEBUG "Entry ov772x_select_win:\n");
+
 	/* default is QVGA */
 	diff = abs(width - ov772x_win_qvga.width) +
 		abs(height - ov772x_win_qvga.height);
@@ -802,7 +872,8 @@ static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
 	    abs(width  - ov772x_win_vga.width) +
 	    abs(height - ov772x_win_vga.height))
 		win = &ov772x_win_vga;
-
+	
+	printk(KERN_DEBUG "Leave ov772x_select_win:\n");
 	return win;
 }
 
@@ -827,11 +898,13 @@ static int ov772x_set_params(struct i2c_client *client,
 	if (!priv->fmt)
 		goto ov772x_set_fmt_error;
 
+
+
 	/*
 	 * select win
 	 */
 	priv->win = ov772x_select_win(*width, *height);
-
+	
 	/*
 	 * reset hardware
 	 */
@@ -969,6 +1042,8 @@ static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
 
 static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
 {
+	printk(KERN_DEBUG "Entry ov772x_cropcap:\n");
+	
 	a->bounds.left			= 0;
 	a->bounds.top			= 0;
 	a->bounds.width			= VGA_WIDTH;
@@ -977,6 +1052,8 @@ static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
 	a->type				= V4L2_BUF_TYPE_VIDEO_CAPTURE;
 	a->pixelaspect.numerator	= 1;
 	a->pixelaspect.denominator	= 1;
+	
+	printk(KERN_DEBUG "Leave ov772x_cropcap!\n");
 
 	return 0;
 }
@@ -987,8 +1064,11 @@ static int ov772x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
 	struct ov772x_priv *priv = to_ov772x(client);
 	struct v4l2_pix_format *pix = &f->fmt.pix;
 
+	printk(KERN_DEBUG " Entry ov772x_g_fmt:\n");
+
 	if (!priv->win || !priv->fmt) {
-		u32 width = VGA_WIDTH, height = VGA_HEIGHT;
+		u32 width = VGA_WIDTH; 
+		u32 height = VGA_HEIGHT;
 		int ret = ov772x_set_params(client, &width, &height,
 					    V4L2_PIX_FMT_YUYV);
 		if (ret < 0)
@@ -1003,6 +1083,8 @@ static int ov772x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
 	pix->colorspace		= priv->fmt->format->colorspace;
 	pix->field		= V4L2_FIELD_NONE;
 
+	printk(KERN_DEBUG " Leave ov772x_g_fmt!\n");
+
 	return 0;
 }
 
@@ -1011,8 +1093,11 @@ static int ov772x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *f)
 	struct i2c_client *client = sd->priv;
 	struct v4l2_pix_format *pix = &f->fmt.pix;
 
+	printk(KERN_INFO "Entry ov772x_s_fmt:\n");
+	printk(KERN_INFO "Leave ov772x_s_fmt:\n");
 	return ov772x_set_params(client, &pix->width, &pix->height,
 				 pix->pixelformat);
+	return 0;
 }
 
 static int ov772x_try_fmt(struct v4l2_subdev *sd,
@@ -1021,6 +1106,7 @@ static int ov772x_try_fmt(struct v4l2_subdev *sd,
 	struct v4l2_pix_format *pix = &f->fmt.pix;
 	const struct ov772x_win_size *win;
 
+	printk(KERN_INFO "Entry ov772x_try_fmt:\n");
 	/*
 	 * select suitable win
 	 */
@@ -1029,7 +1115,8 @@ static int ov772x_try_fmt(struct v4l2_subdev *sd,
 	pix->width  = win->width;
 	pix->height = win->height;
 	pix->field  = V4L2_FIELD_NONE;
-
+	
+	printk(KERN_INFO "Leave ov772x_try_fmt:\n");
 	return 0;
 }
 
@@ -1066,6 +1153,13 @@ static int ov772x_video_probe(struct soc_camera_device *icd,
 	pid = i2c_smbus_read_byte_data(client, PID);
 	ver = i2c_smbus_read_byte_data(client, VER);
 
+	/* setup the sensor register */
+	if (ov772x_camera_init(client)) {
+		printk(KERN_INFO "initialize the sensor failed!\n");
+	} else {
+		printk(KERN_INFO "initialize the sensor succeedded!\n");
+	}
+
 	switch (VERSION(pid, ver)) {
 	case OV7720:
 		devname     = "ov7720";
@@ -1145,7 +1239,7 @@ static int ov772x_probe(struct i2c_client *client,
 	icl = to_soc_camera_link(icd);
 	if (!icl)
 		return -EINVAL;
-
+	
 	info = container_of(icl, struct ov772x_camera_info, link);
 
 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
@@ -1156,8 +1250,9 @@ static int ov772x_probe(struct i2c_client *client,
 	}
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
-	if (!priv)
+	if (!priv) {
 		return -ENOMEM;
+	}	
 
 	priv->info = info;
 
@@ -1166,12 +1261,13 @@ static int ov772x_probe(struct i2c_client *client,
 	icd->ops		= &ov772x_ops;
 
 	ret = ov772x_video_probe(icd, client);
+	
 	if (ret) {
 		icd->ops = NULL;
 		i2c_set_clientdata(client, NULL);
 		kfree(priv);
 	}
-
+	
 	return ret;
 }
 
@@ -1207,7 +1303,12 @@ static struct i2c_driver ov772x_i2c_driver = {
 
 static int __init ov772x_module_init(void)
 {
-	return i2c_add_driver(&ov772x_i2c_driver);
+	int ret;
+	printk(KERN_NOTICE "Entry ov772x_module_init:\n");
+	ret = i2c_add_driver(&ov772x_i2c_driver);
+	printk(KERN_NOTICE "Leave ov772x_module_init!\n");
+
+	return ret;
 }
 
 static void __exit ov772x_module_exit(void)
diff --git a/drivers/media/video/ov772x.h b/drivers/media/video/ov772x.h
new file mode 100644
index 00000000000..0eb83f46801
--- /dev/null
+++ b/drivers/media/video/ov772x.h
@@ -0,0 +1,163 @@
+

+

+

+/* ov772x Camera

+ *

+ * Copyright (C) 2008 Renesas Solutions Corp.

+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ */

+

+#ifndef __OV772X_H__

+#define __OV772X_H__

+

+#include <media/soc_camera.h>

+

+/* for flags */

+#define OV772X_FLAG_VFLIP     0x00000001 /* Vertical flip image */

+#define OV772X_FLAG_HFLIP     0x00000002 /* Horizontal flip image */

+

+/*

+ * for Edge ctrl

+ *

+ * strength also control Auto or Manual Edge Control Mode

+ * see also OV772X_MANUAL_EDGE_CTRL

+ */

+struct ov772x_edge_ctrl {

+	unsigned char strength;

+	unsigned char threshold;

+	unsigned char upper;

+	unsigned char lower;

+};

+

+#define OV772X_MANUAL_EDGE_CTRL	0x80 /* un-used bit of strength */

+#define EDGE_STRENGTH_MASK	0x1F

+#define EDGE_THRESHOLD_MASK	0x0F

+#define EDGE_UPPER_MASK		0xFF

+#define EDGE_LOWER_MASK		0xFF

+

+#define OV772X_AUTO_EDGECTRL(u, l)	\

+{					\

+	.upper = (u & EDGE_UPPER_MASK),	\

+	.lower = (l & EDGE_LOWER_MASK),	\

+}

+

+#define OV772X_MANUAL_EDGECTRL(s, t)					\

+{									\

+	.strength  = (s & EDGE_STRENGTH_MASK) | OV772X_MANUAL_EDGE_CTRL,\

+	.threshold = (t & EDGE_THRESHOLD_MASK),				\

+}

+

+/*

+ * ov772x camera info

+ */

+struct ov772x_camera_info {

+	unsigned long          buswidth;

+	unsigned long          flags;

+	struct soc_camera_link link;

+	struct ov772x_edge_ctrl edgectrl;

+};

+

+

+#define DELAY_FLAG        0xFE   // first parameter is 0xfe, then 2nd parameter is delay time count

+#define END_FLAG          0xFF   // first parameter is 0xff, then parameter table is over 

+/*

+ * struct

+ */

+

+

+

+static const unsigned char INIT_TAB[] = 

+{

+0x12, 0x80,

+0x3d, 0x03,

+

+0x17, 0x22,

+0x18, 0xa4, 

+0x32, 0x00,

+0x19, 0x07,

+0x1a, 0xf0,

+0x03, 0x00,

+

+0x29, 0xa0,

+0x2c, 0xf0,

+0x2a, 0x00,

+0x11, 0x01,//0x01,//0x01,//==0x03,frame

+0x33, 0x66,//==frame

+0x42, 0x7f,

+0x4d, 0x09,

+0x63, 0xe0,

+0x64, 0xff,

+0x65, 0x20,

+0x66, 0x00,

+0x67, 0x48,

+0x13, 0xff,//

+0x0d, 0x41,

+0x0f, 0xc5,

+0x14, 0x31,

+

+0x22, 0x3f,

+0x23, 0x07,

+0x24, 0x40,

+0x25, 0x30,

+0x26, 0xa1,

+

+

+0x2b, 0x00,

+0x6b, 0xaa,

+0x90, 0x05,

+0x91, 0x01,

+0x92, 0x03,

+0x93, 0x00,

+0x94, 0xb0,

+0x95, 0x9d,

+0x96, 0x13,

+0x97, 0x16,

+0x98, 0x7b,

+0x99, 0x91,

+0x9a, 0x1e,

+0x9b, 0x08,

+0x9c, 0x20,//0x20

+0x9e, 0x81,

+0xa6, 0x04,

+0x7e, 0x0c,

+0x7f, 0x16,

+0x80, 0x2a,

+0x81, 0x4e,

+0x82, 0x61,

+0x83, 0x6f,

+0x84, 0x7b,

+0x85, 0x86,

+0x86, 0x8e,

+0x87, 0x97,

+0x88, 0xa4,

+0x89, 0xaf,

+0x8a, 0xc5,

+0x8b, 0xd7,

+0x8c, 0xe8,

+0x8d, 0x20,

+0x0c, 0x00,//0x80,

+0x6b, 0x90,

+//0xac, 0x20,//==add

+//0x8e, 0x10,

+0xa7,0x70,

+0xa8,0x70,

+//0x0e,0x35,

+

+//¾µÍ·Ð£Õý

+

+0x47, 0x90,

+0x48, 0x14,

+0x4a, 0x00,

+0x49, 0x07,

+0x4b, 0x07,

+0x4c, 0x0a,

+0x46, 0x05,

+	END_FLAG, END_FLAG

+};

+

+#endif /* __OV772X_H__ */

+

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index df1f86b5c83..99538ab4cfb 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -13,6 +13,10 @@ menuconfig MISC_DEVICES
 
 if MISC_DEVICES
 
+config ANDROID_PMEM
+	bool "Android pmem allocator"
+	default y
+
 config ATMEL_PWM
 	tristate "Atmel AT32/AT91 PWM support"
 	depends on AVR32 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9
@@ -159,6 +163,13 @@ config ENCLOSURE_SERVICES
 	  driver (SCSI/ATA) which supports enclosures
 	  or a SCSI enclosure device (SES) to use these services.
 
+config KERNEL_DEBUGGER_CORE
+	bool "Kernel Debugger Core"
+	default n
+	---help---
+	  Generic kernel debugging command processor used by low level
+	  (interrupt context) platform-specific debuggers.
+
 config SGI_XP
 	tristate "Support communication between SGI SSIs"
 	depends on NET
@@ -246,6 +257,39 @@ config EP93XX_PWM
 	  To compile this driver as a module, choose M here: the module will
 	  be called ep93xx_pwm.
 
+config UID_STAT
+	bool "UID based statistics tracking exported to /proc/uid_stat"
+	default n
+
+config WL127X_RFKILL
+	tristate "Bluetooth power control driver for TI wl127x"
+	depends on RFKILL
+	default n
+	---help---
+	 Creates an rfkill entry in sysfs for power control of Bluetooth
+	 TI wl127x chips.
+
+config APANIC
+	bool "Android kernel panic diagnostics driver"
+	default n
+	---help---
+	 Driver which handles kernel panics and attempts to write
+	 critical debugging data to flash.
+
+config APANIC_PLABEL
+	string "Android panic dump flash partition label"
+	depends on APANIC
+	default "kpanic"
+	---help---
+	 If your platform uses a different flash partition label for storing
+ 	 crashdumps, enter it here.
+
+config AK_SENSOR
+	tristate "Anyka Sensor Info Get"
+	depends on ARCH_AK98
+	---help---
+	 If you say yes here you get the ak98 sensor info
+	 
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f982d2ecfde..d3dc10e5054 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -12,14 +12,20 @@ obj-$(CONFIG_LKDTM)		+= lkdtm.o
 obj-$(CONFIG_TIFM_CORE)       	+= tifm_core.o
 obj-$(CONFIG_TIFM_7XX1)       	+= tifm_7xx1.o
 obj-$(CONFIG_PHANTOM)		+= phantom.o
+obj-$(CONFIG_ANDROID_PMEM)	+= pmem.o
 obj-$(CONFIG_SGI_IOC4)		+= ioc4.o
 obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
+obj-$(CONFIG_KERNEL_DEBUGGER_CORE)	+= kernel_debugger.o
 obj-$(CONFIG_KGDB_TESTS)	+= kgdbts.o
 obj-$(CONFIG_SGI_XP)		+= sgi-xp/
 obj-$(CONFIG_SGI_GRU)		+= sgi-gru/
 obj-$(CONFIG_HP_ILO)		+= hpilo.o
 obj-$(CONFIG_ISL29003)		+= isl29003.o
 obj-$(CONFIG_EP93XX_PWM)	+= ep93xx_pwm.o
+obj-$(CONFIG_UID_STAT)		+= uid_stat.o
 obj-$(CONFIG_C2PORT)		+= c2port/
 obj-y				+= eeprom/
 obj-y				+= cb710/
+obj-$(CONFIG_WL127X_RFKILL)	+= wl127x-rfkill.o
+obj-$(CONFIG_APANIC)		+= apanic.o
+obj-$(CONFIG_AK_SENSOR)		+= ak_sensor.o
diff --git a/drivers/misc/ak_sensor.c b/drivers/misc/ak_sensor.c
new file mode 100755
index 00000000000..1b3008b2941
--- /dev/null
+++ b/drivers/misc/ak_sensor.c
@@ -0,0 +1,260 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+#include <mach/ak_sensor.h>
+
+struct sensor_kobj {
+	struct kobject kobj;
+	struct sensor_t *sensor;
+};
+
+struct sensor_attribute {
+	struct attribute attr;
+	ssize_t (*show)(struct sensor_kobj *kobj, struct sensor_attribute *attr,
+			char *buf);
+	ssize_t (*store)(struct sensor_kobj *kobj, struct sensor_attribute *attr,
+			 const char *buf, size_t count);
+};
+
+static struct kset *sensor_kset =NULL;
+static struct sensor_kobj *gsensor_kobj = NULL;
+static struct sensor_kobj *msensor_kobj = NULL;
+static struct sensor_kobj *osensor_kobj = NULL;
+
+#define SENSOR_ATTR(_type, _name, _mode, _show, _store) 				\
+struct sensor_attribute attr_##_type##_##_name = __ATTR(_name, _mode, _show, _store)
+
+#define SENSOR_SYSFS(type, name)										\
+static ssize_t show_##type##_##name(struct sensor_kobj *kobj,			\
+				struct sensor_attribute *attr, char *buf)				\
+{																		\
+	ssize_t ret = 0;													\
+																		\
+	sprintf(buf, "%s", kobj->sensor->name); 							\
+	ret = strlen(buf) + 1;												\
+																		\
+	return ret;															\
+}																		\
+static SENSOR_ATTR(type, name, S_IRUGO, show_##type##_##name, NULL);	
+
+SENSOR_SYSFS(gsensor, name);
+SENSOR_SYSFS(gsensor, vendor);
+SENSOR_SYSFS(gsensor, type);
+SENSOR_SYSFS(gsensor, maxRange);
+SENSOR_SYSFS(gsensor, resolution);
+SENSOR_SYSFS(gsensor, power);
+SENSOR_SYSFS(gsensor, dir);
+
+SENSOR_SYSFS(msensor, name);
+SENSOR_SYSFS(msensor, vendor);
+SENSOR_SYSFS(msensor, type);
+SENSOR_SYSFS(msensor, maxRange);
+SENSOR_SYSFS(msensor, resolution);
+SENSOR_SYSFS(msensor, power);
+SENSOR_SYSFS(msensor, dir);
+
+SENSOR_SYSFS(osensor, name);
+SENSOR_SYSFS(osensor, vendor);
+SENSOR_SYSFS(osensor, type);
+SENSOR_SYSFS(osensor, maxRange);
+SENSOR_SYSFS(osensor, resolution);
+SENSOR_SYSFS(osensor, power);
+
+static struct attribute *gsensor_attributes[] = {
+	&attr_gsensor_name.attr,
+	&attr_gsensor_vendor.attr,
+	&attr_gsensor_type.attr,
+	&attr_gsensor_maxRange.attr,
+	&attr_gsensor_resolution.attr,
+	&attr_gsensor_power.attr,
+	&attr_gsensor_dir.attr,
+	NULL
+};
+
+static struct attribute *msensor_attributes[] = {
+	&attr_msensor_name.attr,
+	&attr_msensor_vendor.attr,
+	&attr_msensor_type.attr,
+	&attr_msensor_maxRange.attr,
+	&attr_msensor_resolution.attr,
+	&attr_msensor_power.attr,
+	&attr_msensor_dir.attr,
+	NULL
+};
+
+static struct attribute *osensor_attributes[] = {
+	&attr_osensor_name.attr,
+	&attr_osensor_vendor.attr,
+	&attr_osensor_type.attr,
+	&attr_osensor_maxRange.attr,
+	&attr_osensor_resolution.attr,
+	&attr_osensor_power.attr,
+	NULL
+};
+
+static ssize_t sensor_attr_show(struct kobject *kobj, 
+						struct attribute *attr,
+						char *buf)
+{
+	struct sensor_attribute *attribute;
+	struct sensor_kobj *sensor;
+
+	attribute = container_of(attr, struct sensor_attribute, attr);
+	sensor = container_of(kobj, struct sensor_kobj, kobj);
+
+	if (!attribute->show)
+		return -EIO;
+
+	return attribute->show(sensor, attribute, buf);
+}					
+											
+static struct sysfs_ops sensor_sysfs_ops = {
+	.show = sensor_attr_show,
+	.store = NULL,
+};
+
+static void sensor_release(struct kobject *kobj)
+{
+	struct sensor_kobj *sensor;
+
+	sensor = container_of(kobj, struct sensor_kobj, kobj);
+	kfree(sensor);
+}
+
+static struct kobj_type gsensor_ktype = {
+	.sysfs_ops		= &sensor_sysfs_ops,
+	.release		= sensor_release,
+	.default_attrs	= gsensor_attributes,
+}; 
+
+static struct kobj_type msensor_ktype = {
+	.sysfs_ops		= &sensor_sysfs_ops,
+	.release		= sensor_release,
+	.default_attrs	= msensor_attributes,
+}; 
+
+static struct kobj_type osensor_ktype = {
+	.sysfs_ops		= &sensor_sysfs_ops,
+	.release		= sensor_release,
+	.default_attrs	= osensor_attributes,
+}; 
+
+
+static struct sensor_kobj *create_sensor_kobj(const char *name, struct kobj_type *ktype)
+{
+	struct sensor_kobj *sensor;
+	int ret;
+
+	sensor = kzalloc(sizeof(*sensor), GFP_KERNEL);
+	if (!sensor)
+		return NULL;
+
+	sensor->kobj.kset = sensor_kset;
+
+	ret = kobject_init_and_add(&sensor->kobj, ktype, NULL, "%s", name);
+	if (ret) {
+		kobject_put(&sensor->kobj);
+		kfree(sensor);
+		return NULL;
+	}
+
+	kobject_uevent(&sensor->kobj, KOBJ_ADD);
+
+	return sensor;
+}
+
+static int __init ak_sensor_probe(struct platform_device *pdev)
+{
+	int i;
+	struct sensor_platform_data *pdata = NULL;
+	struct sensor_t *sensor = NULL; 
+
+	pdata = pdev->dev.platform_data;
+	sensor = pdata->sensors;
+
+	sensor_kset = kset_create_and_add("sensor_list", NULL, &pdev->dev.kobj);
+	if (!sensor_kset) {
+		printk("failed to create sensor kset\n");
+		return -ENOMEM;
+	}
+
+	for(i = 0; ; i++) {
+		if (sensor[i].name == NULL) 
+			break;
+
+		if (sensor[i].exist == 0) 
+			continue;
+
+		if (!strcmp(sensor[i].type, SENSOR_ACCELEROMETER)) 
+		{
+			gsensor_kobj = create_sensor_kobj("gsensor", &gsensor_ktype);
+			if (!gsensor_kobj) 
+				printk("failed to create gsensor kobject\n");
+			else  
+				gsensor_kobj->sensor = sensor + i;
+		} 
+		else if (!strcmp(sensor[i].type, SENSOR_MAGNETIC_FIELD)) 
+		{
+			msensor_kobj = create_sensor_kobj("msensor", &msensor_ktype);
+			if (!msensor_kobj) 
+				printk("failed to create msensor kobject\n");
+			else 
+				msensor_kobj->sensor = sensor + i;
+		} 
+		else if (!strcmp(sensor[i].type, SENSOR_ORIENTATION)) 
+		{
+			if (gsensor_kobj && msensor_kobj) {
+				osensor_kobj = create_sensor_kobj("osensor", &osensor_ktype);
+				if (!osensor_kobj)
+					printk("failed to create osensor kobject\n");
+				else 
+					osensor_kobj->sensor = sensor + i;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int ak_sensor_remove(struct platform_device *pdev)
+{
+	if (gsensor_kobj)
+		kobject_put(&gsensor_kobj->kobj);
+	if (msensor_kobj)
+		kobject_put(&msensor_kobj->kobj);
+	if (osensor_kobj)
+		kobject_put(&osensor_kobj->kobj);
+	kset_unregister(sensor_kset);
+
+	return 0;
+}
+
+static struct platform_driver ak_sensor_driver = {
+	.driver	= {
+		.owner	= THIS_MODULE,
+		.name	= "ak_sensor",
+	},
+	.probe		= ak_sensor_probe,
+	.remove		= ak_sensor_remove,
+};
+
+static int __init ak_sensor_init(void)
+{
+	return platform_driver_register(&ak_sensor_driver);
+}
+
+static void __exit ak_sensor_exit(void)
+{
+	platform_driver_unregister(&ak_sensor_driver);
+}
+
+module_init(ak_sensor_init);	
+module_exit(ak_sensor_exit);	
+
+MODULE_DESCRIPTION("Anyka Sensor Driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/apanic.c b/drivers/misc/apanic.c
new file mode 100644
index 00000000000..ca875f89da7
--- /dev/null
+++ b/drivers/misc/apanic.c
@@ -0,0 +1,606 @@
+/* drivers/misc/apanic.c
+ *
+ * Copyright (C) 2009 Google, Inc.
+ * Author: San Mehat <san@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/wakelock.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/mtd/mtd.h>
+#include <linux/notifier.h>
+#include <linux/mtd/mtd.h>
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/mutex.h>
+#include <linux/workqueue.h>
+#include <linux/preempt.h>
+
+extern void ram_console_enable_console(int);
+
+struct panic_header {
+	u32 magic;
+#define PANIC_MAGIC 0xdeadf00d
+
+	u32 version;
+#define PHDR_VERSION   0x01
+
+	u32 console_offset;
+	u32 console_length;
+
+	u32 threads_offset;
+	u32 threads_length;
+};
+
+struct apanic_data {
+	struct mtd_info		*mtd;
+	struct panic_header	curr;
+	void			*bounce;
+	struct proc_dir_entry	*apanic_console;
+	struct proc_dir_entry	*apanic_threads;
+};
+
+static struct apanic_data drv_ctx;
+static struct work_struct proc_removal_work;
+static DEFINE_MUTEX(drv_mutex);
+
+static unsigned int *apanic_bbt;
+static unsigned int apanic_erase_blocks;
+static unsigned int apanic_good_blocks;
+
+static void set_bb(unsigned int block, unsigned int *bbt)
+{
+	unsigned int flag = 1;
+
+	BUG_ON(block >= apanic_erase_blocks);
+
+	flag = flag << (block%32);
+	apanic_bbt[block/32] |= flag;
+	apanic_good_blocks--;
+}
+
+static unsigned int get_bb(unsigned int block, unsigned int *bbt)
+{
+	unsigned int flag;
+
+	BUG_ON(block >= apanic_erase_blocks);
+
+	flag = 1 << (block%32);
+	return apanic_bbt[block/32] & flag;
+}
+
+static void alloc_bbt(struct mtd_info *mtd, unsigned int *bbt)
+{
+	int bbt_size;
+	apanic_erase_blocks = (mtd->size)>>(mtd->erasesize_shift);
+	bbt_size = (apanic_erase_blocks+32)/32;
+
+	apanic_bbt = kmalloc(bbt_size*4, GFP_KERNEL);
+	memset(apanic_bbt, 0, bbt_size*4);
+	apanic_good_blocks = apanic_erase_blocks;
+}
+static void scan_bbt(struct mtd_info *mtd, unsigned int *bbt)
+{
+	int i;
+
+	for (i = 0; i < apanic_erase_blocks; i++) {
+		if (mtd->block_isbad(mtd, i*mtd->erasesize))
+			set_bb(i, apanic_bbt);
+	}
+}
+
+#define APANIC_INVALID_OFFSET 0xFFFFFFFF
+
+static unsigned int phy_offset(struct mtd_info *mtd, unsigned int offset)
+{
+	unsigned int logic_block = offset>>(mtd->erasesize_shift);
+	unsigned int phy_block;
+	unsigned good_block = 0;
+
+	for (phy_block = 0; phy_block < apanic_erase_blocks; phy_block++) {
+		if (!get_bb(phy_block, apanic_bbt))
+			good_block++;
+		if (good_block == (logic_block + 1))
+			break;
+	}
+
+	if (good_block != (logic_block + 1))
+		return APANIC_INVALID_OFFSET;
+
+	return offset + ((phy_block-logic_block)<<mtd->erasesize_shift);
+}
+
+static void apanic_erase_callback(struct erase_info *done)
+{
+	wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
+	wake_up(wait_q);
+}
+
+static int apanic_proc_read(char *buffer, char **start, off_t offset,
+			       int count, int *peof, void *dat)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	size_t file_length;
+	off_t file_offset;
+	unsigned int page_no;
+	off_t page_offset;
+	int rc;
+	size_t len;
+
+	if (!count)
+		return 0;
+
+	mutex_lock(&drv_mutex);
+
+	switch ((int) dat) {
+	case 1:	/* apanic_console */
+		file_length = ctx->curr.console_length;
+		file_offset = ctx->curr.console_offset;
+		break;
+	case 2:	/* apanic_threads */
+		file_length = ctx->curr.threads_length;
+		file_offset = ctx->curr.threads_offset;
+		break;
+	default:
+		pr_err("Bad dat (%d)\n", (int) dat);
+		mutex_unlock(&drv_mutex);
+		return -EINVAL;
+	}
+
+	if ((offset + count) > file_length) {
+		mutex_unlock(&drv_mutex);
+		return 0;
+	}
+
+	/* We only support reading a maximum of a flash page */
+	if (count > ctx->mtd->writesize)
+		count = ctx->mtd->writesize;
+
+	page_no = (file_offset + offset) / ctx->mtd->writesize;
+	page_offset = (file_offset + offset) % ctx->mtd->writesize;
+
+
+	if (phy_offset(ctx->mtd, (page_no * ctx->mtd->writesize))
+		== APANIC_INVALID_OFFSET) {
+		pr_err("apanic: reading an invalid address\n");
+		mutex_unlock(&drv_mutex);
+		return -EINVAL;
+	}
+	rc = ctx->mtd->read(ctx->mtd,
+		phy_offset(ctx->mtd, (page_no * ctx->mtd->writesize)),
+		ctx->mtd->writesize,
+		&len, ctx->bounce);
+
+	if (page_offset)
+		count -= page_offset;
+	memcpy(buffer, ctx->bounce + page_offset, count);
+
+	*start = count;
+
+	if ((offset + count) == file_length)
+		*peof = 1;
+
+	mutex_unlock(&drv_mutex);
+	return count;
+}
+
+static void mtd_panic_erase(void)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	struct erase_info erase;
+	DECLARE_WAITQUEUE(wait, current);
+	wait_queue_head_t wait_q;
+	int rc, i;
+
+	init_waitqueue_head(&wait_q);
+	erase.mtd = ctx->mtd;
+	erase.callback = apanic_erase_callback;
+	erase.len = ctx->mtd->erasesize;
+	erase.priv = (u_long)&wait_q;
+	for (i = 0; i < ctx->mtd->size; i += ctx->mtd->erasesize) {
+		erase.addr = i;
+		set_current_state(TASK_INTERRUPTIBLE);
+		add_wait_queue(&wait_q, &wait);
+
+		if (get_bb(erase.addr>>ctx->mtd->erasesize_shift, apanic_bbt)) {
+			printk(KERN_WARNING
+			       "apanic: Skipping erase of bad "
+			       "block @%llx\n", erase.addr);
+			set_current_state(TASK_RUNNING);
+			remove_wait_queue(&wait_q, &wait);
+			continue;
+		}
+
+		rc = ctx->mtd->erase(ctx->mtd, &erase);
+		if (rc) {
+			set_current_state(TASK_RUNNING);
+			remove_wait_queue(&wait_q, &wait);
+			printk(KERN_ERR
+			       "apanic: Erase of 0x%llx, 0x%llx failed\n",
+			       (unsigned long long) erase.addr,
+			       (unsigned long long) erase.len);
+			if (rc == -EIO) {
+				if (ctx->mtd->block_markbad(ctx->mtd,
+							    erase.addr)) {
+					printk(KERN_ERR
+					       "apanic: Err marking blk bad\n");
+					goto out;
+				}
+				printk(KERN_INFO
+				       "apanic: Marked a bad block"
+				       " @%llx\n", erase.addr);
+				set_bb(erase.addr>>ctx->mtd->erasesize_shift,
+					apanic_bbt);
+				continue;
+			}
+			goto out;
+		}
+		schedule();
+		remove_wait_queue(&wait_q, &wait);
+	}
+	printk(KERN_DEBUG "apanic: %s partition erased\n",
+	       CONFIG_APANIC_PLABEL);
+out:
+	return;
+}
+
+static void apanic_remove_proc_work(struct work_struct *work)
+{
+	struct apanic_data *ctx = &drv_ctx;
+
+	mutex_lock(&drv_mutex);
+	mtd_panic_erase();
+	memset(&ctx->curr, 0, sizeof(struct panic_header));
+	if (ctx->apanic_console) {
+		remove_proc_entry("apanic_console", NULL);
+		ctx->apanic_console = NULL;
+	}
+	if (ctx->apanic_threads) {
+		remove_proc_entry("apanic_threads", NULL);
+		ctx->apanic_threads = NULL;
+	}
+	mutex_unlock(&drv_mutex);
+}
+
+static int apanic_proc_write(struct file *file, const char __user *buffer,
+				unsigned long count, void *data)
+{
+	schedule_work(&proc_removal_work);
+	return count;
+}
+
+static void mtd_panic_notify_add(struct mtd_info *mtd)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	struct panic_header *hdr = ctx->bounce;
+	size_t len;
+	int rc;
+	int    proc_entry_created = 0;
+
+	if (strcmp(mtd->name, CONFIG_APANIC_PLABEL))
+		return;
+
+	ctx->mtd = mtd;
+
+	alloc_bbt(mtd, apanic_bbt);
+	scan_bbt(mtd, apanic_bbt);
+
+	if (apanic_good_blocks == 0) {
+		printk(KERN_ERR "apanic: no any good blocks?!\n");
+		goto out_err;
+	}
+
+	rc = mtd->read(mtd, phy_offset(mtd, 0), mtd->writesize,
+			&len, ctx->bounce);
+	if (rc && rc == -EBADMSG) {
+		printk(KERN_WARNING
+		       "apanic: Bad ECC on block 0 (ignored)\n");
+	} else if (rc && rc != -EUCLEAN) {
+		printk(KERN_ERR "apanic: Error reading block 0 (%d)\n", rc);
+		goto out_err;
+	}
+
+	if (len != mtd->writesize) {
+		printk(KERN_ERR "apanic: Bad read size (%d)\n", rc);
+		goto out_err;
+	}
+
+	printk(KERN_INFO "apanic: Bound to mtd partition '%s'\n", mtd->name);
+
+	if (hdr->magic != PANIC_MAGIC) {
+		printk(KERN_INFO "apanic: No panic data available\n");
+		mtd_panic_erase();
+		return;
+	}
+
+	if (hdr->version != PHDR_VERSION) {
+		printk(KERN_INFO "apanic: Version mismatch (%d != %d)\n",
+		       hdr->version, PHDR_VERSION);
+		mtd_panic_erase();
+		return;
+	}
+
+	memcpy(&ctx->curr, hdr, sizeof(struct panic_header));
+
+	printk(KERN_INFO "apanic: c(%u, %u) t(%u, %u)\n",
+	       hdr->console_offset, hdr->console_length,
+	       hdr->threads_offset, hdr->threads_length);
+
+	if (hdr->console_length) {
+		ctx->apanic_console = create_proc_entry("apanic_console",
+						      S_IFREG | S_IRUGO, NULL);
+		if (!ctx->apanic_console)
+			printk(KERN_ERR "%s: failed creating procfile\n",
+			       __func__);
+		else {
+			ctx->apanic_console->read_proc = apanic_proc_read;
+			ctx->apanic_console->write_proc = apanic_proc_write;
+			ctx->apanic_console->size = hdr->console_length;
+			ctx->apanic_console->data = (void *) 1;
+			proc_entry_created = 1;
+		}
+	}
+
+	if (hdr->threads_length) {
+		ctx->apanic_threads = create_proc_entry("apanic_threads",
+						       S_IFREG | S_IRUGO, NULL);
+		if (!ctx->apanic_threads)
+			printk(KERN_ERR "%s: failed creating procfile\n",
+			       __func__);
+		else {
+			ctx->apanic_threads->read_proc = apanic_proc_read;
+			ctx->apanic_threads->write_proc = apanic_proc_write;
+			ctx->apanic_threads->size = hdr->threads_length;
+			ctx->apanic_threads->data = (void *) 2;
+			proc_entry_created = 1;
+		}
+	}
+
+	if (!proc_entry_created)
+		mtd_panic_erase();
+
+	return;
+out_err:
+	ctx->mtd = NULL;
+}
+
+static void mtd_panic_notify_remove(struct mtd_info *mtd)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	if (mtd == ctx->mtd) {
+		ctx->mtd = NULL;
+		printk(KERN_INFO "apanic: Unbound from %s\n", mtd->name);
+	}
+}
+
+static struct mtd_notifier mtd_panic_notifier = {
+	.add	= mtd_panic_notify_add,
+	.remove	= mtd_panic_notify_remove,
+};
+
+static int in_panic = 0;
+
+static int apanic_writeflashpage(struct mtd_info *mtd, loff_t to,
+				 const u_char *buf)
+{
+	int rc;
+	size_t wlen;
+	int panic = in_interrupt() | in_atomic();
+
+	if (panic && !mtd->panic_write) {
+		printk(KERN_EMERG "%s: No panic_write available\n", __func__);
+		return 0;
+	} else if (!panic && !mtd->write) {
+		printk(KERN_EMERG "%s: No write available\n", __func__);
+		return 0;
+	}
+
+	to = phy_offset(mtd, to);
+	if (to == APANIC_INVALID_OFFSET) {
+		printk(KERN_EMERG "apanic: write to invalid address\n");
+		return 0;
+	}
+
+	if (panic)
+		rc = mtd->panic_write(mtd, to, mtd->writesize, &wlen, buf);
+	else
+		rc = mtd->write(mtd, to, mtd->writesize, &wlen, buf);
+
+	if (rc) {
+		printk(KERN_EMERG
+		       "%s: Error writing data to flash (%d)\n",
+		       __func__, rc);
+		return rc;
+	}
+
+	return wlen;
+}
+
+extern int log_buf_copy(char *dest, int idx, int len);
+extern void log_buf_clear(void);
+
+/*
+ * Writes the contents of the console to the specified offset in flash.
+ * Returns number of bytes written
+ */
+static int apanic_write_console(struct mtd_info *mtd, unsigned int off)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	int saved_oip;
+	int idx = 0;
+	int rc, rc2;
+	unsigned int last_chunk = 0;
+
+	while (!last_chunk) {
+		saved_oip = oops_in_progress;
+		oops_in_progress = 1;
+		rc = log_buf_copy(ctx->bounce, idx, mtd->writesize);
+		if (rc < 0)
+			break;
+
+		if (rc != mtd->writesize)
+			last_chunk = rc;
+
+		oops_in_progress = saved_oip;
+		if (rc <= 0)
+			break;
+		if (rc != mtd->writesize)
+			memset(ctx->bounce + rc, 0, mtd->writesize - rc);
+
+		rc2 = apanic_writeflashpage(mtd, off, ctx->bounce);
+		if (rc2 <= 0) {
+			printk(KERN_EMERG
+			       "apanic: Flash write failed (%d)\n", rc2);
+			return idx;
+		}
+		if (!last_chunk)
+			idx += rc2;
+		else
+			idx += last_chunk;
+		off += rc2;
+	}
+	return idx;
+}
+
+static int apanic(struct notifier_block *this, unsigned long event,
+			void *ptr)
+{
+	struct apanic_data *ctx = &drv_ctx;
+	struct panic_header *hdr = (struct panic_header *) ctx->bounce;
+	int console_offset = 0;
+	int console_len = 0;
+	int threads_offset = 0;
+	int threads_len = 0;
+	int rc;
+
+	if (in_panic)
+		return NOTIFY_DONE;
+	in_panic = 1;
+#ifdef CONFIG_PREEMPT
+	/* Ensure that cond_resched() won't try to preempt anybody */
+	add_preempt_count(PREEMPT_ACTIVE);
+#endif
+	touch_softlockup_watchdog();
+
+	if (!ctx->mtd)
+		goto out;
+
+	if (ctx->curr.magic) {
+		printk(KERN_EMERG "Crash partition in use!\n");
+		goto out;
+	}
+	console_offset = ctx->mtd->writesize;
+
+	/*
+	 * Write out the console
+	 */
+	console_len = apanic_write_console(ctx->mtd, console_offset);
+	if (console_len < 0) {
+		printk(KERN_EMERG "Error writing console to panic log! (%d)\n",
+		       console_len);
+		console_len = 0;
+	}
+
+	/*
+	 * Write out all threads
+	 */
+	threads_offset = ALIGN(console_offset + console_len,
+			       ctx->mtd->writesize);
+	if (!threads_offset)
+		threads_offset = ctx->mtd->writesize;
+
+	ram_console_enable_console(0);
+
+	log_buf_clear();
+	show_state_filter(0);
+	threads_len = apanic_write_console(ctx->mtd, threads_offset);
+	if (threads_len < 0) {
+		printk(KERN_EMERG "Error writing threads to panic log! (%d)\n",
+		       threads_len);
+		threads_len = 0;
+	}
+
+	/*
+	 * Finally write the panic header
+	 */
+	memset(ctx->bounce, 0, PAGE_SIZE);
+	hdr->magic = PANIC_MAGIC;
+	hdr->version = PHDR_VERSION;
+
+	hdr->console_offset = console_offset;
+	hdr->console_length = console_len;
+
+	hdr->threads_offset = threads_offset;
+	hdr->threads_length = threads_len;
+
+	rc = apanic_writeflashpage(ctx->mtd, 0, ctx->bounce);
+	if (rc <= 0) {
+		printk(KERN_EMERG "apanic: Header write failed (%d)\n",
+		       rc);
+		goto out;
+	}
+
+	printk(KERN_EMERG "apanic: Panic dump sucessfully written to flash\n");
+
+ out:
+#ifdef CONFIG_PREEMPT
+	sub_preempt_count(PREEMPT_ACTIVE);
+#endif
+	in_panic = 0;
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block panic_blk = {
+	.notifier_call	= apanic,
+};
+
+static int panic_dbg_get(void *data, u64 *val)
+{
+	apanic(NULL, 0, NULL);
+	return 0;
+}
+
+static int panic_dbg_set(void *data, u64 val)
+{
+	BUG();
+	return -1;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(panic_dbg_fops, panic_dbg_get, panic_dbg_set, "%llu\n");
+
+int __init apanic_init(void)
+{
+	register_mtd_user(&mtd_panic_notifier);
+	atomic_notifier_chain_register(&panic_notifier_list, &panic_blk);
+	debugfs_create_file("apanic", 0644, NULL, NULL, &panic_dbg_fops);
+	memset(&drv_ctx, 0, sizeof(drv_ctx));
+	drv_ctx.bounce = (void *) __get_free_page(GFP_KERNEL);
+	INIT_WORK(&proc_removal_work, apanic_remove_proc_work);
+	printk(KERN_INFO "Android kernel panic handler initialized (bind=%s)\n",
+	       CONFIG_APANIC_PLABEL);
+	return 0;
+}
+
+module_init(apanic_init);
diff --git a/drivers/misc/kernel_debugger.c b/drivers/misc/kernel_debugger.c
new file mode 100644
index 00000000000..f10eaa4dfc4
--- /dev/null
+++ b/drivers/misc/kernel_debugger.c
@@ -0,0 +1,79 @@
+/* drivers/android/kernel_debugger.c
+ *
+ * Guts of the kernel debugger.
+ * Needs something to actually push commands to it.
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/ctype.h>
+#include <linux/device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/sysrq.h>
+#include <linux/kernel_debugger.h>
+
+#define dprintf(fmt...) (ctxt->printf(ctxt->cookie, fmt))
+
+static void do_ps(struct kdbg_ctxt *ctxt)
+{
+	struct task_struct *g, *p;
+	unsigned state;
+	static const char stat_nam[] = "RSDTtZX";
+
+	dprintf("pid   ppid  prio task            pc\n");
+	read_lock(&tasklist_lock);
+	do_each_thread(g, p) {
+		state = p->state ? __ffs(p->state) + 1 : 0;
+		dprintf("%5d %5d %4d ", p->pid, p->parent->pid, p->prio);
+		dprintf("%-13.13s %c", p->comm,
+			state >= sizeof(stat_nam) ? '?' : stat_nam[state]);
+		if (state == TASK_RUNNING)
+			dprintf(" running\n");
+		else
+			dprintf(" %08lx\n", thread_saved_pc(p));
+	} while_each_thread(g, p);
+	read_unlock(&tasklist_lock);
+}
+
+int log_buf_copy(char *dest, int idx, int len);
+extern int do_syslog(int type, char __user *bug, int count);
+static void do_sysrq(struct kdbg_ctxt *ctxt, char rq)
+{
+	char buf[128];
+	int ret;
+	int idx = 0;
+	do_syslog(5 /* clear */, NULL, 0);
+	__handle_sysrq(rq, NULL, 0);
+	while (1) {
+		ret = log_buf_copy(buf, idx, sizeof(buf) - 1);
+		if (ret <= 0)
+			break;
+		buf[ret] = 0;
+		dprintf("%s", buf);
+		idx += ret;
+	}
+}
+
+int kernel_debugger(struct kdbg_ctxt *ctxt, char *cmd)
+{
+	if (!strcmp(cmd, "ps"))
+		do_ps(ctxt);
+	if (!strcmp(cmd, "sysrq"))
+		do_sysrq(ctxt, 'h');
+	if (!strncmp(cmd, "sysrq ", 6))
+		do_sysrq(ctxt, cmd[6]);
+
+	return 0;
+}
+
diff --git a/drivers/misc/pmem.c b/drivers/misc/pmem.c
new file mode 100644
index 00000000000..7f3b5321756
--- /dev/null
+++ b/drivers/misc/pmem.c
@@ -0,0 +1,1345 @@
+/* drivers/android/pmem.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/fs.h>
+#include <linux/file.h>
+#include <linux/mm.h>
+#include <linux/list.h>
+#include <linux/debugfs.h>
+#include <linux/android_pmem.h>
+#include <linux/mempolicy.h>
+#include <linux/sched.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/cacheflush.h>
+
+#define PMEM_MAX_DEVICES 10
+#define PMEM_MAX_ORDER 128
+#define PMEM_MIN_ALLOC PAGE_SIZE
+
+#define PMEM_DEBUG 1
+
+/* indicates that a refernce to this file has been taken via get_pmem_file,
+ * the file should not be released until put_pmem_file is called */
+#define PMEM_FLAGS_BUSY 0x1
+/* indicates that this is a suballocation of a larger master range */
+#define PMEM_FLAGS_CONNECTED 0x1 << 1
+/* indicates this is a master and not a sub allocation and that it is mmaped */
+#define PMEM_FLAGS_MASTERMAP 0x1 << 2
+/* submap and unsubmap flags indicate:
+ * 00: subregion has never been mmaped
+ * 10: subregion has been mmaped, reference to the mm was taken
+ * 11: subretion has ben released, refernece to the mm still held
+ * 01: subretion has been released, reference to the mm has been released
+ */
+#define PMEM_FLAGS_SUBMAP 0x1 << 3
+#define PMEM_FLAGS_UNSUBMAP 0x1 << 4
+
+
+struct pmem_data {
+	/* in alloc mode: an index into the bitmap
+	 * in no_alloc mode: the size of the allocation */
+	int index;
+	/* see flags above for descriptions */
+	unsigned int flags;
+	/* protects this data field, if the mm_mmap sem will be held at the
+	 * same time as this sem, the mm sem must be taken first (as this is
+	 * the order for vma_open and vma_close ops */
+	struct rw_semaphore sem;
+	/* info about the mmaping process */
+	struct vm_area_struct *vma;
+	/* task struct of the mapping process */
+	struct task_struct *task;
+	/* process id of teh mapping process */
+	pid_t pid;
+	/* file descriptor of the master */
+	int master_fd;
+	/* file struct of the master */
+	struct file *master_file;
+	/* a list of currently available regions if this is a suballocation */
+	struct list_head region_list;
+	/* a linked list of data so we can access them for debugging */
+	struct list_head list;
+#if PMEM_DEBUG
+	int ref;
+#endif
+};
+
+struct pmem_bits {
+	unsigned allocated:1;		/* 1 if allocated, 0 if free */
+	unsigned order:7;		/* size of the region in pmem space */
+};
+
+struct pmem_region_node {
+	struct pmem_region region;
+	struct list_head list;
+};
+
+#define PMEM_DEBUG_MSGS 0
+#if PMEM_DEBUG_MSGS
+#define DLOG(fmt,args...) \
+	do { printk(KERN_INFO "[%s:%s:%d] "fmt, __FILE__, __func__, __LINE__, \
+		    ##args); } \
+	while (0)
+#else
+#define DLOG(x...) do {} while (0)
+#endif
+
+struct pmem_info {
+	struct miscdevice dev;
+	/* physical start address of the remaped pmem space */
+	unsigned long base;
+	/* vitual start address of the remaped pmem space */
+	unsigned char __iomem *vbase;
+	/* total size of the pmem space */
+	unsigned long size;
+	/* number of entries in the pmem space */
+	unsigned long num_entries;
+	/* pfn of the garbage page in memory */
+	unsigned long garbage_pfn;
+	/* index of the garbage page in the pmem space */
+	int garbage_index;
+	/* the bitmap for the region indicating which entries are allocated
+	 * and which are free */
+	struct pmem_bits *bitmap;
+	/* indicates the region should not be managed with an allocator */
+	unsigned no_allocator;
+	/* indicates maps of this region should be cached, if a mix of
+	 * cached and uncached is desired, set this and open the device with
+	 * O_SYNC to get an uncached region */
+	unsigned cached;
+	unsigned buffered;
+	/* in no_allocator mode the first mapper gets the whole space and sets
+	 * this flag */
+	unsigned allocated;
+	/* for debugging, creates a list of pmem file structs, the
+	 * data_list_sem should be taken before pmem_data->sem if both are
+	 * needed */
+	struct semaphore data_list_sem;
+	struct list_head data_list;
+	/* pmem_sem protects the bitmap array
+	 * a write lock should be held when modifying entries in bitmap
+	 * a read lock should be held when reading data from bits or
+	 * dereferencing a pointer into bitmap
+	 *
+	 * pmem_data->sem protects the pmem data of a particular file
+	 * Many of the function that require the pmem_data->sem have a non-
+	 * locking version for when the caller is already holding that sem.
+	 *
+	 * IF YOU TAKE BOTH LOCKS TAKE THEM IN THIS ORDER:
+	 * down(pmem_data->sem) => down(bitmap_sem)
+	 */
+	struct rw_semaphore bitmap_sem;
+
+	long (*ioctl)(struct file *, unsigned int, unsigned long);
+	int (*release)(struct inode *, struct file *);
+};
+
+static struct pmem_info pmem[PMEM_MAX_DEVICES];
+static int id_count;
+
+#define PMEM_IS_FREE(id, index) !(pmem[id].bitmap[index].allocated)
+#define PMEM_ORDER(id, index) pmem[id].bitmap[index].order
+#define PMEM_BUDDY_INDEX(id, index) (index ^ (1 << PMEM_ORDER(id, index)))
+#define PMEM_NEXT_INDEX(id, index) (index + (1 << PMEM_ORDER(id, index)))
+#define PMEM_OFFSET(index) (index * PMEM_MIN_ALLOC)
+#define PMEM_START_ADDR(id, index) (PMEM_OFFSET(index) + pmem[id].base)
+#define PMEM_LEN(id, index) ((1 << PMEM_ORDER(id, index)) * PMEM_MIN_ALLOC)
+#define PMEM_END_ADDR(id, index) (PMEM_START_ADDR(id, index) + \
+	PMEM_LEN(id, index))
+#define PMEM_START_VADDR(id, index) (PMEM_OFFSET(id, index) + pmem[id].vbase)
+#define PMEM_END_VADDR(id, index) (PMEM_START_VADDR(id, index) + \
+	PMEM_LEN(id, index))
+#define PMEM_REVOKED(data) (data->flags & PMEM_FLAGS_REVOKED)
+#define PMEM_IS_PAGE_ALIGNED(addr) (!((addr) & (~PAGE_MASK)))
+#define PMEM_IS_SUBMAP(data) ((data->flags & PMEM_FLAGS_SUBMAP) && \
+	(!(data->flags & PMEM_FLAGS_UNSUBMAP)))
+
+static int pmem_release(struct inode *, struct file *);
+static int pmem_mmap(struct file *, struct vm_area_struct *);
+static int pmem_open(struct inode *, struct file *);
+static long pmem_ioctl(struct file *, unsigned int, unsigned long);
+
+struct file_operations pmem_fops = {
+	.release = pmem_release,
+	.mmap = pmem_mmap,
+	.open = pmem_open,
+	.unlocked_ioctl = pmem_ioctl,
+};
+
+static int get_id(struct file *file)
+{
+	return MINOR(file->f_dentry->d_inode->i_rdev);
+}
+
+int is_pmem_file(struct file *file)
+{
+	int id;
+
+	if (unlikely(!file || !file->f_dentry || !file->f_dentry->d_inode))
+		return 0;
+	id = get_id(file);
+	if (unlikely(id >= PMEM_MAX_DEVICES))
+		return 0;
+	if (unlikely(file->f_dentry->d_inode->i_rdev !=
+	     MKDEV(MISC_MAJOR, pmem[id].dev.minor)))
+		return 0;
+	return 1;
+}
+
+static int has_allocation(struct file *file)
+{
+	struct pmem_data *data;
+	/* check is_pmem_file first if not accessed via pmem_file_ops */
+
+	if (unlikely(!file->private_data))
+		return 0;
+	data = (struct pmem_data *)file->private_data;
+	if (unlikely(data->index < 0))
+		return 0;
+	return 1;
+}
+
+static int is_master_owner(struct file *file)
+{
+	struct file *master_file;
+	struct pmem_data *data;
+	int put_needed, ret = 0;
+
+	if (!is_pmem_file(file) || !has_allocation(file))
+		return 0;
+	data = (struct pmem_data *)file->private_data;
+	if (PMEM_FLAGS_MASTERMAP & data->flags)
+		return 1;
+	master_file = fget_light(data->master_fd, &put_needed);
+	if (master_file && data->master_file == master_file)
+		ret = 1;
+	fput_light(master_file, put_needed);
+	return ret;
+}
+
+static int pmem_free(int id, int index)
+{
+	/* caller should hold the write lock on pmem_sem! */
+	int buddy, curr = index;
+	DLOG("index %d\n", index);
+
+	if (pmem[id].no_allocator) {
+		pmem[id].allocated = 0;
+		return 0;
+	}
+	/* clean up the bitmap, merging any buddies */
+	pmem[id].bitmap[curr].allocated = 0;
+	/* find a slots buddy Buddy# = Slot# ^ (1 << order)
+	 * if the buddy is also free merge them
+	 * repeat until the buddy is not free or end of the bitmap is reached
+	 */
+	do {
+		buddy = PMEM_BUDDY_INDEX(id, curr);
+		if (PMEM_IS_FREE(id, buddy) &&
+				PMEM_ORDER(id, buddy) == PMEM_ORDER(id, curr)) {
+			PMEM_ORDER(id, buddy)++;
+			PMEM_ORDER(id, curr)++;
+			curr = min(buddy, curr);
+		} else {
+			break;
+		}
+	} while (curr < pmem[id].num_entries);
+
+	return 0;
+}
+
+static void pmem_revoke(struct file *file, struct pmem_data *data);
+
+static int pmem_release(struct inode *inode, struct file *file)
+{
+	struct pmem_data *data = (struct pmem_data *)file->private_data;
+	struct pmem_region_node *region_node;
+	struct list_head *elt, *elt2;
+	int id = get_id(file), ret = 0;
+
+
+	down(&pmem[id].data_list_sem);
+	/* if this file is a master, revoke all the memory in the connected
+	 *  files */
+	if (PMEM_FLAGS_MASTERMAP & data->flags) {
+		struct pmem_data *sub_data;
+		list_for_each(elt, &pmem[id].data_list) {
+			sub_data = list_entry(elt, struct pmem_data, list);
+			down_read(&sub_data->sem);
+			if (PMEM_IS_SUBMAP(sub_data) &&
+			    file == sub_data->master_file) {
+				up_read(&sub_data->sem);
+				pmem_revoke(file, sub_data);
+			}  else
+				up_read(&sub_data->sem);
+		}
+	}
+	list_del(&data->list);
+	up(&pmem[id].data_list_sem);
+
+
+	down_write(&data->sem);
+
+	/* if its not a conencted file and it has an allocation, free it */
+	if (!(PMEM_FLAGS_CONNECTED & data->flags) && has_allocation(file)) {
+		down_write(&pmem[id].bitmap_sem);
+		ret = pmem_free(id, data->index);
+		up_write(&pmem[id].bitmap_sem);
+	}
+
+	/* if this file is a submap (mapped, connected file), downref the
+	 * task struct */
+	if (PMEM_FLAGS_SUBMAP & data->flags)
+		if (data->task) {
+			put_task_struct(data->task);
+			data->task = NULL;
+		}
+
+	file->private_data = NULL;
+
+	list_for_each_safe(elt, elt2, &data->region_list) {
+		region_node = list_entry(elt, struct pmem_region_node, list);
+		list_del(elt);
+		kfree(region_node);
+	}
+	BUG_ON(!list_empty(&data->region_list));
+
+	up_write(&data->sem);
+	kfree(data);
+	if (pmem[id].release)
+		ret = pmem[id].release(inode, file);
+
+	return ret;
+}
+
+static int pmem_open(struct inode *inode, struct file *file)
+{
+	struct pmem_data *data;
+	int id = get_id(file);
+	int ret = 0;
+
+	DLOG("current %u file %p(%d)\n", current->pid, file, file_count(file));
+	/* setup file->private_data to indicate its unmapped */
+	/*  you can only open a pmem device one time */
+	if (file->private_data != NULL)
+		return -1;
+	data = kmalloc(sizeof(struct pmem_data), GFP_KERNEL);
+	if (!data) {
+		printk("pmem: unable to allocate memory for pmem metadata.");
+		return -1;
+	}
+	data->flags = 0;
+	data->index = -1;
+	data->task = NULL;
+	data->vma = NULL;
+	data->pid = 0;
+	data->master_file = NULL;
+#if PMEM_DEBUG
+	data->ref = 0;
+#endif
+	INIT_LIST_HEAD(&data->region_list);
+	init_rwsem(&data->sem);
+
+	file->private_data = data;
+	INIT_LIST_HEAD(&data->list);
+
+	down(&pmem[id].data_list_sem);
+	list_add(&data->list, &pmem[id].data_list);
+	up(&pmem[id].data_list_sem);
+	return ret;
+}
+
+static unsigned long pmem_order(unsigned long len)
+{
+	int i;
+
+	len = (len + PMEM_MIN_ALLOC - 1)/PMEM_MIN_ALLOC;
+	len--;
+	for (i = 0; i < sizeof(len)*8; i++)
+		if (len >> i == 0)
+			break;
+	return i;
+}
+
+static int pmem_allocate(int id, unsigned long len)
+{
+	/* caller should hold the write lock on pmem_sem! */
+	/* return the corresponding pdata[] entry */
+	int curr = 0;
+	int end = pmem[id].num_entries;
+	int best_fit = -1;
+	unsigned long order = pmem_order(len);
+
+	if (pmem[id].no_allocator) {
+		DLOG("no allocator");
+		if ((len > pmem[id].size) || pmem[id].allocated)
+			return -1;
+		pmem[id].allocated = 1;
+		return len;
+	}
+
+	if (order > PMEM_MAX_ORDER)
+		return -1;
+	DLOG("order %lx\n", order);
+
+	/* look through the bitmap:
+	 * 	if you find a free slot of the correct order use it
+	 * 	otherwise, use the best fit (smallest with size > order) slot
+	 */
+	while (curr < end) {
+		if (PMEM_IS_FREE(id, curr)) {
+			if (PMEM_ORDER(id, curr) == (unsigned char)order) {
+				/* set the not free bit and clear others */
+				best_fit = curr;
+				break;
+			}
+			if (PMEM_ORDER(id, curr) > (unsigned char)order &&
+			    (best_fit < 0 ||
+			     PMEM_ORDER(id, curr) < PMEM_ORDER(id, best_fit)))
+				best_fit = curr;
+		}
+		curr = PMEM_NEXT_INDEX(id, curr);
+	}
+
+	/* if best_fit < 0, there are no suitable slots,
+	 * return an error
+	 */
+	if (best_fit < 0) {
+		printk("pmem: no space left to allocate!\n");
+		return -1;
+	}
+
+	/* now partition the best fit:
+	 * 	split the slot into 2 buddies of order - 1
+	 * 	repeat until the slot is of the correct order
+	 */
+	while (PMEM_ORDER(id, best_fit) > (unsigned char)order) {
+		int buddy;
+		PMEM_ORDER(id, best_fit) -= 1;
+		buddy = PMEM_BUDDY_INDEX(id, best_fit);
+		PMEM_ORDER(id, buddy) = PMEM_ORDER(id, best_fit);
+	}
+	pmem[id].bitmap[best_fit].allocated = 1;
+	return best_fit;
+}
+
+static pgprot_t phys_mem_access_prot(struct file *file, pgprot_t vma_prot)
+{
+	int id = get_id(file);
+#ifdef pgprot_noncached
+	if (pmem[id].cached == 0 || file->f_flags & O_SYNC)
+		return pgprot_noncached(vma_prot);
+#endif
+#ifdef pgprot_ext_buffered
+	else if (pmem[id].buffered)
+		return pgprot_ext_buffered(vma_prot);
+#endif
+	return vma_prot;
+}
+
+static unsigned long pmem_start_addr(int id, struct pmem_data *data)
+{
+	if (pmem[id].no_allocator)
+		return PMEM_START_ADDR(id, 0);
+	else
+		return PMEM_START_ADDR(id, data->index);
+
+}
+
+static void *pmem_start_vaddr(int id, struct pmem_data *data)
+{
+	return pmem_start_addr(id, data) - pmem[id].base + pmem[id].vbase;
+}
+
+static unsigned long pmem_len(int id, struct pmem_data *data)
+{
+	if (pmem[id].no_allocator)
+		return data->index;
+	else
+		return PMEM_LEN(id, data->index);
+}
+
+static int pmem_map_garbage(int id, struct vm_area_struct *vma,
+			    struct pmem_data *data, unsigned long offset,
+			    unsigned long len)
+{
+	int i, garbage_pages = len >> PAGE_SHIFT;
+
+	vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP | VM_SHARED | VM_WRITE;
+	for (i = 0; i < garbage_pages; i++) {
+		if (vm_insert_pfn(vma, vma->vm_start + offset + (i * PAGE_SIZE),
+		    pmem[id].garbage_pfn))
+			return -EAGAIN;
+	}
+	return 0;
+}
+
+static int pmem_unmap_pfn_range(int id, struct vm_area_struct *vma,
+				struct pmem_data *data, unsigned long offset,
+				unsigned long len)
+{
+	int garbage_pages;
+	DLOG("unmap offset %lx len %lx\n", offset, len);
+
+	BUG_ON(!PMEM_IS_PAGE_ALIGNED(len));
+
+	garbage_pages = len >> PAGE_SHIFT;
+	zap_page_range(vma, vma->vm_start + offset, len, NULL);
+	pmem_map_garbage(id, vma, data, offset, len);
+	return 0;
+}
+
+static int pmem_map_pfn_range(int id, struct vm_area_struct *vma,
+			      struct pmem_data *data, unsigned long offset,
+			      unsigned long len)
+{
+	DLOG("map offset %lx len %lx\n", offset, len);
+	BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_start));
+	BUG_ON(!PMEM_IS_PAGE_ALIGNED(vma->vm_end));
+	BUG_ON(!PMEM_IS_PAGE_ALIGNED(len));
+	BUG_ON(!PMEM_IS_PAGE_ALIGNED(offset));
+
+	if (io_remap_pfn_range(vma, vma->vm_start + offset,
+		(pmem_start_addr(id, data) + offset) >> PAGE_SHIFT,
+		len, vma->vm_page_prot)) {
+		return -EAGAIN;
+	}
+	return 0;
+}
+
+static int pmem_remap_pfn_range(int id, struct vm_area_struct *vma,
+			      struct pmem_data *data, unsigned long offset,
+			      unsigned long len)
+{
+	/* hold the mm semp for the vma you are modifying when you call this */
+	BUG_ON(!vma);
+	zap_page_range(vma, vma->vm_start + offset, len, NULL);
+	return pmem_map_pfn_range(id, vma, data, offset, len);
+}
+
+static void pmem_vma_open(struct vm_area_struct *vma)
+{
+	struct file *file = vma->vm_file;
+	struct pmem_data *data = file->private_data;
+	int id = get_id(file);
+	/* this should never be called as we don't support copying pmem
+	 * ranges via fork */
+	BUG_ON(!has_allocation(file));
+	down_write(&data->sem);
+	/* remap the garbage pages, forkers don't get access to the data */
+	pmem_unmap_pfn_range(id, vma, data, 0, vma->vm_start - vma->vm_end);
+	up_write(&data->sem);
+}
+
+static void pmem_vma_close(struct vm_area_struct *vma)
+{
+	struct file *file = vma->vm_file;
+	struct pmem_data *data = file->private_data;
+
+	DLOG("current %u ppid %u file %p count %d\n", current->pid,
+	     current->parent->pid, file, file_count(file));
+	if (unlikely(!is_pmem_file(file) || !has_allocation(file))) {
+		printk(KERN_WARNING "pmem: something is very wrong, you are "
+		       "closing a vm backing an allocation that doesn't "
+		       "exist!\n");
+		return;
+	}
+	down_write(&data->sem);
+	if (data->vma == vma) {
+		data->vma = NULL;
+		if ((data->flags & PMEM_FLAGS_CONNECTED) &&
+		    (data->flags & PMEM_FLAGS_SUBMAP))
+			data->flags |= PMEM_FLAGS_UNSUBMAP;
+	}
+	/* the kernel is going to free this vma now anyway */
+	up_write(&data->sem);
+}
+
+static struct vm_operations_struct vm_ops = {
+	.open = pmem_vma_open,
+	.close = pmem_vma_close,
+};
+
+static int pmem_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct pmem_data *data;
+	int index;
+	unsigned long vma_size =  vma->vm_end - vma->vm_start;
+	int ret = 0, id = get_id(file);
+
+	if (vma->vm_pgoff || !PMEM_IS_PAGE_ALIGNED(vma_size)) {
+#if PMEM_DEBUG
+		printk(KERN_ERR "pmem: mmaps must be at offset zero, aligned"
+				" and a multiple of pages_size.\n");
+#endif
+		return -EINVAL;
+	}
+
+	data = (struct pmem_data *)file->private_data;
+	down_write(&data->sem);
+	/* check this file isn't already mmaped, for submaps check this file
+	 * has never been mmaped */
+	if ((data->flags & PMEM_FLAGS_MASTERMAP) ||
+	    (data->flags & PMEM_FLAGS_SUBMAP) ||
+	    (data->flags & PMEM_FLAGS_UNSUBMAP)) {
+#if PMEM_DEBUG
+		printk(KERN_ERR "pmem: you can only mmap a pmem file once, "
+		       "this file is already mmaped. %x\n", data->flags);
+#endif
+		ret = -EINVAL;
+		goto error;
+	}
+	/* if file->private_data == unalloced, alloc*/
+	if (data && data->index == -1) {
+		down_write(&pmem[id].bitmap_sem);
+		index = pmem_allocate(id, vma->vm_end - vma->vm_start);
+		up_write(&pmem[id].bitmap_sem);
+		data->index = index;
+	}
+	/* either no space was available or an error occured */
+	if (!has_allocation(file)) {
+		ret = -EINVAL;
+		printk("pmem: could not find allocation for map.\n");
+		goto error;
+	}
+
+	if (pmem_len(id, data) < vma_size) {
+#if PMEM_DEBUG
+		printk(KERN_WARNING "pmem: mmap size [%lu] does not match"
+		       "size of backing region [%lu].\n", vma_size,
+		       pmem_len(id, data));
+#endif
+		ret = -EINVAL;
+		goto error;
+	}
+
+	vma->vm_pgoff = pmem_start_addr(id, data) >> PAGE_SHIFT;
+	vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_page_prot);
+
+	if (data->flags & PMEM_FLAGS_CONNECTED) {
+		struct pmem_region_node *region_node;
+		struct list_head *elt;
+		if (pmem_map_garbage(id, vma, data, 0, vma_size)) {
+			printk("pmem: mmap failed in kernel!\n");
+			ret = -EAGAIN;
+			goto error;
+		}
+		list_for_each(elt, &data->region_list) {
+			region_node = list_entry(elt, struct pmem_region_node,
+						 list);
+			DLOG("remapping file: %p %lx %lx\n", file,
+				region_node->region.offset,
+				region_node->region.len);
+			if (pmem_remap_pfn_range(id, vma, data,
+						 region_node->region.offset,
+						 region_node->region.len)) {
+				ret = -EAGAIN;
+				goto error;
+			}
+		}
+		data->flags |= PMEM_FLAGS_SUBMAP;
+		get_task_struct(current->group_leader);
+		data->task = current->group_leader;
+		data->vma = vma;
+#if PMEM_DEBUG
+		data->pid = current->pid;
+#endif
+		DLOG("submmapped file %p vma %p pid %u\n", file, vma,
+		     current->pid);
+	} else {
+		if (pmem_map_pfn_range(id, vma, data, 0, vma_size)) {
+			printk(KERN_INFO "pmem: mmap failed in kernel!\n");
+			ret = -EAGAIN;
+			goto error;
+		}
+		data->flags |= PMEM_FLAGS_MASTERMAP;
+		data->pid = current->pid;
+	}
+	vma->vm_ops = &vm_ops;
+error:
+	up_write(&data->sem);
+	return ret;
+}
+
+/* the following are the api for accessing pmem regions by other drivers
+ * from inside the kernel */
+int get_pmem_user_addr(struct file *file, unsigned long *start,
+		   unsigned long *len)
+{
+	struct pmem_data *data;
+	if (!is_pmem_file(file) || !has_allocation(file)) {
+#if PMEM_DEBUG
+		printk(KERN_INFO "pmem: requested pmem data from invalid"
+				  "file.\n");
+#endif
+		return -1;
+	}
+	data = (struct pmem_data *)file->private_data;
+	down_read(&data->sem);
+	if (data->vma) {
+		*start = data->vma->vm_start;
+		*len = data->vma->vm_end - data->vma->vm_start;
+	} else {
+		*start = 0;
+		*len = 0;
+	}
+	up_read(&data->sem);
+	return 0;
+}
+
+int get_pmem_addr(struct file *file, unsigned long *start,
+		  unsigned long *vstart, unsigned long *len)
+{
+	struct pmem_data *data;
+	int id;
+
+	if (!is_pmem_file(file) || !has_allocation(file)) {
+		return -1;
+	}
+
+	data = (struct pmem_data *)file->private_data;
+	if (data->index == -1) {
+#if PMEM_DEBUG
+		printk(KERN_INFO "pmem: requested pmem data from file with no "
+		       "allocation.\n");
+		return -1;
+#endif
+	}
+	id = get_id(file);
+
+	down_read(&data->sem);
+	*start = pmem_start_addr(id, data);
+	*len = pmem_len(id, data);
+	*vstart = (unsigned long)pmem_start_vaddr(id, data);
+	up_read(&data->sem);
+#if PMEM_DEBUG
+	down_write(&data->sem);
+	data->ref++;
+	up_write(&data->sem);
+#endif
+	return 0;
+}
+
+int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart,
+		  unsigned long *len, struct file **filp)
+{
+	struct file *file;
+
+	file = fget(fd);
+	if (unlikely(file == NULL)) {
+		printk(KERN_INFO "pmem: requested data from file descriptor "
+		       "that doesn't exist.");
+		return -1;
+	}
+
+	if (get_pmem_addr(file, start, vstart, len))
+		goto end;
+
+	if (filp)
+		*filp = file;
+	return 0;
+end:
+	fput(file);
+	return -1;
+}
+
+void put_pmem_file(struct file *file)
+{
+	struct pmem_data *data;
+	int id;
+
+	if (!is_pmem_file(file))
+		return;
+	id = get_id(file);
+	data = (struct pmem_data *)file->private_data;
+#if PMEM_DEBUG
+	down_write(&data->sem);
+	if (data->ref == 0) {
+		printk("pmem: pmem_put > pmem_get %s (pid %d)\n",
+		       pmem[id].dev.name, data->pid);
+		BUG();
+	}
+	data->ref--;
+	up_write(&data->sem);
+#endif
+	fput(file);
+}
+
+void flush_pmem_file(struct file *file, unsigned long offset, unsigned long len)
+{
+	struct pmem_data *data;
+	int id;
+	void *vaddr;
+	struct pmem_region_node *region_node;
+	struct list_head *elt;
+	void *flush_start, *flush_end;
+
+	if (!is_pmem_file(file) || !has_allocation(file)) {
+		return;
+	}
+
+	id = get_id(file);
+	data = (struct pmem_data *)file->private_data;
+	if (!pmem[id].cached || file->f_flags & O_SYNC)
+		return;
+
+	down_read(&data->sem);
+	vaddr = pmem_start_vaddr(id, data);
+	/* if this isn't a submmapped file, flush the whole thing */
+	if (unlikely(!(data->flags & PMEM_FLAGS_CONNECTED))) {
+		dmac_flush_range(vaddr, vaddr + pmem_len(id, data));
+		goto end;
+	}
+	/* otherwise, flush the region of the file we are drawing */
+	list_for_each(elt, &data->region_list) {
+		region_node = list_entry(elt, struct pmem_region_node, list);
+		if ((offset >= region_node->region.offset) &&
+		    ((offset + len) <= (region_node->region.offset +
+			region_node->region.len))) {
+			flush_start = vaddr + region_node->region.offset;
+			flush_end = flush_start + region_node->region.len;
+			dmac_flush_range(flush_start, flush_end);
+			break;
+		}
+	}
+end:
+	up_read(&data->sem);
+}
+
+static int pmem_connect(unsigned long connect, struct file *file)
+{
+	struct pmem_data *data = (struct pmem_data *)file->private_data;
+	struct pmem_data *src_data;
+	struct file *src_file;
+	int ret = 0, put_needed;
+
+	down_write(&data->sem);
+	/* retrieve the src file and check it is a pmem file with an alloc */
+	src_file = fget_light(connect, &put_needed);
+	DLOG("connect %p to %p\n", file, src_file);
+	if (!src_file) {
+		printk("pmem: src file not found!\n");
+		ret = -EINVAL;
+		goto err_no_file;
+	}
+	if (unlikely(!is_pmem_file(src_file) || !has_allocation(src_file))) {
+		printk(KERN_INFO "pmem: src file is not a pmem file or has no "
+		       "alloc!\n");
+		ret = -EINVAL;
+		goto err_bad_file;
+	}
+	src_data = (struct pmem_data *)src_file->private_data;
+
+	if (has_allocation(file) && (data->index != src_data->index)) {
+		printk("pmem: file is already mapped but doesn't match this"
+		       " src_file!\n");
+		ret = -EINVAL;
+		goto err_bad_file;
+	}
+	data->index = src_data->index;
+	data->flags |= PMEM_FLAGS_CONNECTED;
+	data->master_fd = connect;
+	data->master_file = src_file;
+
+err_bad_file:
+	fput_light(src_file, put_needed);
+err_no_file:
+	up_write(&data->sem);
+	return ret;
+}
+
+static void pmem_unlock_data_and_mm(struct pmem_data *data,
+				    struct mm_struct *mm)
+{
+	up_write(&data->sem);
+	if (mm != NULL) {
+		up_write(&mm->mmap_sem);
+		mmput(mm);
+	}
+}
+
+static int pmem_lock_data_and_mm(struct file *file, struct pmem_data *data,
+				 struct mm_struct **locked_mm)
+{
+	int ret = 0;
+	struct mm_struct *mm = NULL;
+	*locked_mm = NULL;
+lock_mm:
+	down_read(&data->sem);
+	if (PMEM_IS_SUBMAP(data)) {
+		mm = get_task_mm(data->task);
+		if (!mm) {
+#if PMEM_DEBUG
+			printk("pmem: can't remap task is gone!\n");
+#endif
+			up_read(&data->sem);
+			return -1;
+		}
+	}
+	up_read(&data->sem);
+
+	if (mm)
+		down_write(&mm->mmap_sem);
+
+	down_write(&data->sem);
+	/* check that the file didn't get mmaped before we could take the
+	 * data sem, this should be safe b/c you can only submap each file
+	 * once */
+	if (PMEM_IS_SUBMAP(data) && !mm) {
+		pmem_unlock_data_and_mm(data, mm);
+		up_write(&data->sem);
+		goto lock_mm;
+	}
+	/* now check that vma.mm is still there, it could have been
+	 * deleted by vma_close before we could get the data->sem */
+	if ((data->flags & PMEM_FLAGS_UNSUBMAP) && (mm != NULL)) {
+		/* might as well release this */
+		if (data->flags & PMEM_FLAGS_SUBMAP) {
+			put_task_struct(data->task);
+			data->task = NULL;
+			/* lower the submap flag to show the mm is gone */
+			data->flags &= ~(PMEM_FLAGS_SUBMAP);
+		}
+		pmem_unlock_data_and_mm(data, mm);
+		return -1;
+	}
+	*locked_mm = mm;
+	return ret;
+}
+
+int pmem_remap(struct pmem_region *region, struct file *file,
+		      unsigned operation)
+{
+	int ret;
+	struct pmem_region_node *region_node;
+	struct mm_struct *mm = NULL;
+	struct list_head *elt, *elt2;
+	int id = get_id(file);
+	struct pmem_data *data = (struct pmem_data *)file->private_data;
+
+	/* pmem region must be aligned on a page boundry */
+	if (unlikely(!PMEM_IS_PAGE_ALIGNED(region->offset) ||
+		 !PMEM_IS_PAGE_ALIGNED(region->len))) {
+#if PMEM_DEBUG
+		printk("pmem: request for unaligned pmem suballocation "
+		       "%lx %lx\n", region->offset, region->len);
+#endif
+		return -EINVAL;
+	}
+
+	/* if userspace requests a region of len 0, there's nothing to do */
+	if (region->len == 0)
+		return 0;
+
+	/* lock the mm and data */
+	ret = pmem_lock_data_and_mm(file, data, &mm);
+	if (ret)
+		return 0;
+
+	/* only the owner of the master file can remap the client fds
+	 * that back in it */
+	if (!is_master_owner(file)) {
+#if PMEM_DEBUG
+		printk("pmem: remap requested from non-master process\n");
+#endif
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* check that the requested range is within the src allocation */
+	if (unlikely((region->offset > pmem_len(id, data)) ||
+		     (region->len > pmem_len(id, data)) ||
+		     (region->offset + region->len > pmem_len(id, data)))) {
+#if PMEM_DEBUG
+		printk(KERN_INFO "pmem: suballoc doesn't fit in src_file!\n");
+#endif
+		ret = -EINVAL;
+		goto err;
+	}
+
+	if (operation == PMEM_MAP) {
+		region_node = kmalloc(sizeof(struct pmem_region_node),
+			      GFP_KERNEL);
+		if (!region_node) {
+			ret = -ENOMEM;
+#if PMEM_DEBUG
+			printk(KERN_INFO "No space to allocate metadata!");
+#endif
+			goto err;
+		}
+		region_node->region = *region;
+		list_add(&region_node->list, &data->region_list);
+	} else if (operation == PMEM_UNMAP) {
+		int found = 0;
+		list_for_each_safe(elt, elt2, &data->region_list) {
+			region_node = list_entry(elt, struct pmem_region_node,
+				      list);
+			if (region->len == 0 ||
+			    (region_node->region.offset == region->offset &&
+			    region_node->region.len == region->len)) {
+				list_del(elt);
+				kfree(region_node);
+				found = 1;
+			}
+		}
+		if (!found) {
+#if PMEM_DEBUG
+			printk("pmem: Unmap region does not map any mapped "
+				"region!");
+#endif
+			ret = -EINVAL;
+			goto err;
+		}
+	}
+
+	if (data->vma && PMEM_IS_SUBMAP(data)) {
+		if (operation == PMEM_MAP)
+			ret = pmem_remap_pfn_range(id, data->vma, data,
+						   region->offset, region->len);
+		else if (operation == PMEM_UNMAP)
+			ret = pmem_unmap_pfn_range(id, data->vma, data,
+						   region->offset, region->len);
+	}
+
+err:
+	pmem_unlock_data_and_mm(data, mm);
+	return ret;
+}
+
+static void pmem_revoke(struct file *file, struct pmem_data *data)
+{
+	struct pmem_region_node *region_node;
+	struct list_head *elt, *elt2;
+	struct mm_struct *mm = NULL;
+	int id = get_id(file);
+	int ret = 0;
+
+	data->master_file = NULL;
+	ret = pmem_lock_data_and_mm(file, data, &mm);
+	/* if lock_data_and_mm fails either the task that mapped the fd, or
+	 * the vma that mapped it have already gone away, nothing more
+	 * needs to be done */
+	if (ret)
+		return;
+	/* unmap everything */
+	/* delete the regions and region list nothing is mapped any more */
+	if (data->vma)
+		list_for_each_safe(elt, elt2, &data->region_list) {
+			region_node = list_entry(elt, struct pmem_region_node,
+						 list);
+			pmem_unmap_pfn_range(id, data->vma, data,
+					     region_node->region.offset,
+					     region_node->region.len);
+			list_del(elt);
+			kfree(region_node);
+	}
+	/* delete the master file */
+	pmem_unlock_data_and_mm(data, mm);
+}
+
+static void pmem_get_size(struct pmem_region *region, struct file *file)
+{
+	struct pmem_data *data = (struct pmem_data *)file->private_data;
+	int id = get_id(file);
+
+	if (!has_allocation(file)) {
+		region->offset = 0;
+		region->len = 0;
+		return;
+	} else {
+		region->offset = pmem_start_addr(id, data);
+		region->len = pmem_len(id, data);
+	}
+	DLOG("offset %lx len %lx\n", region->offset, region->len);
+}
+
+
+static long pmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct pmem_data *data;
+	int id = get_id(file);
+
+	switch (cmd) {
+	case PMEM_GET_PHYS:
+		{
+			struct pmem_region region;
+			DLOG("get_phys\n");
+			if (!has_allocation(file)) {
+				region.offset = 0;
+				region.len = 0;
+			} else {
+				data = (struct pmem_data *)file->private_data;
+				region.offset = pmem_start_addr(id, data);
+				region.len = pmem_len(id, data);
+			}
+			printk(KERN_INFO "pmem: request for physical address of pmem region "
+					"from process %d.\n", current->pid);
+			if (copy_to_user((void __user *)arg, &region,
+						sizeof(struct pmem_region)))
+				return -EFAULT;
+			break;
+		}
+	case PMEM_MAP:
+		{
+			struct pmem_region region;
+			if (copy_from_user(&region, (void __user *)arg,
+						sizeof(struct pmem_region)))
+				return -EFAULT;
+			data = (struct pmem_data *)file->private_data;
+			return pmem_remap(&region, file, PMEM_MAP);
+		}
+		break;
+	case PMEM_UNMAP:
+		{
+			struct pmem_region region;
+			if (copy_from_user(&region, (void __user *)arg,
+						sizeof(struct pmem_region)))
+				return -EFAULT;
+			data = (struct pmem_data *)file->private_data;
+			return pmem_remap(&region, file, PMEM_UNMAP);
+			break;
+		}
+	case PMEM_GET_SIZE:
+		{
+			struct pmem_region region;
+			DLOG("get_size\n");
+			pmem_get_size(&region, file);
+			if (copy_to_user((void __user *)arg, &region,
+						sizeof(struct pmem_region)))
+				return -EFAULT;
+			break;
+		}
+	case PMEM_GET_TOTAL_SIZE:
+		{
+			struct pmem_region region;
+			DLOG("get total size\n");
+			region.offset = 0;
+			get_id(file);
+			region.len = pmem[id].size;
+			if (copy_to_user((void __user *)arg, &region,
+						sizeof(struct pmem_region)))
+				return -EFAULT;
+			break;
+		}
+	case PMEM_ALLOCATE:
+		{
+			if (has_allocation(file))
+				return -EINVAL;
+			data = (struct pmem_data *)file->private_data;
+			data->index = pmem_allocate(id, arg);
+			break;
+		}
+	case PMEM_CONNECT:
+		DLOG("connect\n");
+		return pmem_connect(arg, file);
+		break;
+	case PMEM_CACHE_FLUSH:
+		{
+			struct pmem_region region;
+			DLOG("flush\n");
+			if (copy_from_user(&region, (void __user *)arg,
+					   sizeof(struct pmem_region)))
+				return -EFAULT;
+			flush_pmem_file(file, region.offset, region.len);
+			break;
+		}
+	default:
+		if (pmem[id].ioctl)
+			return pmem[id].ioctl(file, cmd, arg);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+#if PMEM_DEBUG
+static ssize_t debug_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static ssize_t debug_read(struct file *file, char __user *buf, size_t count,
+			  loff_t *ppos)
+{
+	struct list_head *elt, *elt2;
+	struct pmem_data *data;
+	struct pmem_region_node *region_node;
+	int id = (int)file->private_data;
+	const int debug_bufmax = 4096;
+	static char buffer[4096];
+	int n = 0;
+
+	DLOG("debug open\n");
+	n = scnprintf(buffer, debug_bufmax,
+		      "pid #: mapped regions (offset, len) (offset,len)...\n");
+
+	down(&pmem[id].data_list_sem);
+	list_for_each(elt, &pmem[id].data_list) {
+		data = list_entry(elt, struct pmem_data, list);
+		down_read(&data->sem);
+		n += scnprintf(buffer + n, debug_bufmax - n, "pid %u:",
+				data->pid);
+		list_for_each(elt2, &data->region_list) {
+			region_node = list_entry(elt2, struct pmem_region_node,
+				      list);
+			n += scnprintf(buffer + n, debug_bufmax - n,
+					"(%lx,%lx) ",
+					region_node->region.offset,
+					region_node->region.len);
+		}
+		n += scnprintf(buffer + n, debug_bufmax - n, "\n");
+		up_read(&data->sem);
+	}
+	up(&pmem[id].data_list_sem);
+
+	n++;
+	buffer[n] = 0;
+	return simple_read_from_buffer(buf, count, ppos, buffer, n);
+}
+
+static struct file_operations debug_fops = {
+	.read = debug_read,
+	.open = debug_open,
+};
+#endif
+
+#if 0
+static struct miscdevice pmem_dev = {
+	.name = "pmem",
+	.fops = &pmem_fops,
+};
+#endif
+
+int pmem_setup(struct android_pmem_platform_data *pdata,
+	       long (*ioctl)(struct file *, unsigned int, unsigned long),
+	       int (*release)(struct inode *, struct file *))
+{
+	int err = 0;
+	int i, index = 0;
+	int id = id_count;
+	id_count++;
+
+	pmem[id].no_allocator = pdata->no_allocator;
+	pmem[id].cached = pdata->cached;
+	pmem[id].buffered = pdata->buffered;
+	pmem[id].base = pdata->start;
+	pmem[id].size = pdata->size;
+	pmem[id].ioctl = ioctl;
+	pmem[id].release = release;
+	init_rwsem(&pmem[id].bitmap_sem);
+	init_MUTEX(&pmem[id].data_list_sem);
+	INIT_LIST_HEAD(&pmem[id].data_list);
+	pmem[id].dev.name = pdata->name;
+	pmem[id].dev.minor = id;
+	pmem[id].dev.fops = &pmem_fops;
+	printk(KERN_INFO "%s: %d init\n", pdata->name, pdata->cached);
+
+	err = misc_register(&pmem[id].dev);
+	if (err) {
+		printk(KERN_ALERT "Unable to register pmem driver!\n");
+		goto err_cant_register_device;
+	}
+	pmem[id].num_entries = pmem[id].size / PMEM_MIN_ALLOC;
+
+	pmem[id].bitmap = kmalloc(pmem[id].num_entries *
+				  sizeof(struct pmem_bits), GFP_KERNEL);
+	if (!pmem[id].bitmap)
+		goto err_no_mem_for_metadata;
+
+	memset(pmem[id].bitmap, 0, sizeof(struct pmem_bits) *
+					  pmem[id].num_entries);
+
+	for (i = sizeof(pmem[id].num_entries) * 8 - 1; i >= 0; i--) {
+		if ((pmem[id].num_entries) &  1<<i) {
+			PMEM_ORDER(id, index) = i;
+			index = PMEM_NEXT_INDEX(id, index);
+		}
+	}
+
+	if (pmem[id].cached)
+		pmem[id].vbase = ioremap_cached(pmem[id].base,
+						pmem[id].size);
+#ifdef ioremap_ext_buffered
+	else if (pmem[id].buffered)
+		pmem[id].vbase = ioremap_ext_buffered(pmem[id].base,
+						      pmem[id].size);
+#endif
+	else
+		pmem[id].vbase = ioremap(pmem[id].base, pmem[id].size);
+
+	if (pmem[id].vbase == 0)
+		goto error_cant_remap;
+
+	pmem[id].garbage_pfn = page_to_pfn(alloc_page(GFP_KERNEL));
+	if (pmem[id].no_allocator)
+		pmem[id].allocated = 0;
+
+#if PMEM_DEBUG
+	debugfs_create_file(pdata->name, S_IFREG | S_IRUGO, NULL, (void *)id,
+			    &debug_fops);
+#endif
+	return 0;
+error_cant_remap:
+	kfree(pmem[id].bitmap);
+err_no_mem_for_metadata:
+	misc_deregister(&pmem[id].dev);
+err_cant_register_device:
+	return -1;
+}
+
+static int pmem_probe(struct platform_device *pdev)
+{
+	struct android_pmem_platform_data *pdata;
+
+	if (!pdev || !pdev->dev.platform_data) {
+		printk(KERN_ALERT "Unable to probe pmem!\n");
+		return -1;
+	}
+	pdata = pdev->dev.platform_data;
+	return pmem_setup(pdata, NULL, NULL);
+}
+
+
+static int pmem_remove(struct platform_device *pdev)
+{
+	int id = pdev->id;
+	__free_page(pfn_to_page(pmem[id].garbage_pfn));
+	misc_deregister(&pmem[id].dev);
+	return 0;
+}
+
+static struct platform_driver pmem_driver = {
+	.probe = pmem_probe,
+	.remove = pmem_remove,
+	.driver = { .name = "android_pmem" }
+};
+
+
+static int __init pmem_init(void)
+{
+	return platform_driver_register(&pmem_driver);
+}
+
+static void __exit pmem_exit(void)
+{
+	platform_driver_unregister(&pmem_driver);
+}
+
+module_init(pmem_init);
+module_exit(pmem_exit);
+
diff --git a/drivers/misc/uid_stat.c b/drivers/misc/uid_stat.c
new file mode 100644
index 00000000000..43a548bab7a
--- /dev/null
+++ b/drivers/misc/uid_stat.c
@@ -0,0 +1,153 @@
+/* drivers/misc/uid_stat.c
+ *
+ * Copyright (C) 2008 - 2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/atomic.h>
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/proc_fs.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/stat.h>
+#include <linux/uid_stat.h>
+
+static DEFINE_SPINLOCK(uid_lock);
+static LIST_HEAD(uid_list);
+static struct proc_dir_entry *parent;
+
+struct uid_stat {
+	struct list_head link;
+	uid_t uid;
+	atomic_t tcp_rcv;
+	atomic_t tcp_snd;
+};
+
+static struct uid_stat *find_uid_stat(uid_t uid) {
+	unsigned long flags;
+	struct uid_stat *entry;
+
+	spin_lock_irqsave(&uid_lock, flags);
+	list_for_each_entry(entry, &uid_list, link) {
+		if (entry->uid == uid) {
+			spin_unlock_irqrestore(&uid_lock, flags);
+			return entry;
+		}
+	}
+	spin_unlock_irqrestore(&uid_lock, flags);
+	return NULL;
+}
+
+static int tcp_snd_read_proc(char *page, char **start, off_t off,
+				int count, int *eof, void *data)
+{
+	int len;
+	unsigned int bytes;
+	char *p = page;
+	struct uid_stat *uid_entry = (struct uid_stat *) data;
+	if (!data)
+		return 0;
+
+	bytes = (unsigned int) (atomic_read(&uid_entry->tcp_snd) + INT_MIN);
+	p += sprintf(p, "%u\n", bytes);
+	len = (p - page) - off;
+	*eof = (len <= count) ? 1 : 0;
+	*start = page + off;
+	return len;
+}
+
+static int tcp_rcv_read_proc(char *page, char **start, off_t off,
+				int count, int *eof, void *data)
+{
+	int len;
+	unsigned int bytes;
+	char *p = page;
+	struct uid_stat *uid_entry = (struct uid_stat *) data;
+	if (!data)
+		return 0;
+
+	bytes = (unsigned int) (atomic_read(&uid_entry->tcp_rcv) + INT_MIN);
+	p += sprintf(p, "%u\n", bytes);
+	len = (p - page) - off;
+	*eof = (len <= count) ? 1 : 0;
+	*start = page + off;
+	return len;
+}
+
+/* Create a new entry for tracking the specified uid. */
+static struct uid_stat *create_stat(uid_t uid) {
+	unsigned long flags;
+	char uid_s[32];
+	struct uid_stat *new_uid;
+	struct proc_dir_entry *entry;
+
+	/* Create the uid stat struct and append it to the list. */
+	if ((new_uid = kmalloc(sizeof(struct uid_stat), GFP_KERNEL)) == NULL)
+		return NULL;
+
+	new_uid->uid = uid;
+	/* Counters start at INT_MIN, so we can track 4GB of network traffic. */
+	atomic_set(&new_uid->tcp_rcv, INT_MIN);
+	atomic_set(&new_uid->tcp_snd, INT_MIN);
+
+	spin_lock_irqsave(&uid_lock, flags);
+	list_add_tail(&new_uid->link, &uid_list);
+	spin_unlock_irqrestore(&uid_lock, flags);
+
+	sprintf(uid_s, "%d", uid);
+	entry = proc_mkdir(uid_s, parent);
+
+	/* Keep reference to uid_stat so we know what uid to read stats from. */
+	create_proc_read_entry("tcp_snd", S_IRUGO, entry , tcp_snd_read_proc,
+		(void *) new_uid);
+
+	create_proc_read_entry("tcp_rcv", S_IRUGO, entry, tcp_rcv_read_proc,
+		(void *) new_uid);
+
+	return new_uid;
+}
+
+int update_tcp_snd(uid_t uid, int size) {
+	struct uid_stat *entry;
+	if ((entry = find_uid_stat(uid)) == NULL &&
+		((entry = create_stat(uid)) == NULL)) {
+			return -1;
+	}
+	atomic_add(size, &entry->tcp_snd);
+	return 0;
+}
+
+int update_tcp_rcv(uid_t uid, int size) {
+	struct uid_stat *entry;
+	if ((entry = find_uid_stat(uid)) == NULL &&
+		((entry = create_stat(uid)) == NULL)) {
+			return -1;
+	}
+	atomic_add(size, &entry->tcp_rcv);
+	return 0;
+}
+
+static int __init uid_stat_init(void)
+{
+	parent = proc_mkdir("uid_stat", NULL);
+	if (!parent) {
+		pr_err("uid_stat: failed to create proc entry\n");
+		return -1;
+	}
+	return 0;
+}
+
+__initcall(uid_stat_init);
diff --git a/drivers/misc/wl127x-rfkill.c b/drivers/misc/wl127x-rfkill.c
new file mode 100644
index 00000000000..f5b95152948
--- /dev/null
+++ b/drivers/misc/wl127x-rfkill.c
@@ -0,0 +1,121 @@
+/*
+ * Bluetooth TI wl127x rfkill power control via GPIO
+ *
+ * Copyright (C) 2009 Motorola, Inc.
+ * Copyright (C) 2008 Texas Instruments
+ * Initial code: Pavan Savoy <pavan.savoy@gmail.com> (wl127x_power.c)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/rfkill.h>
+#include <linux/platform_device.h>
+#include <linux/wl127x-rfkill.h>
+
+static int wl127x_rfkill_set_power(void *data, enum rfkill_state state)
+{
+	int nshutdown_gpio = (int) data;
+
+	switch (state) {
+	case RFKILL_STATE_UNBLOCKED:
+		gpio_set_value(nshutdown_gpio, 1);
+		break;
+	case RFKILL_STATE_SOFT_BLOCKED:
+		gpio_set_value(nshutdown_gpio, 0);
+		break;
+	default:
+		printk(KERN_ERR "invalid bluetooth rfkill state %d\n", state);
+	}
+	return 0;
+}
+
+static int wl127x_rfkill_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct wl127x_rfkill_platform_data *pdata = pdev->dev.platform_data;
+	enum rfkill_state default_state = RFKILL_STATE_SOFT_BLOCKED;  /* off */
+
+	rc = gpio_request(pdata->nshutdown_gpio, "wl127x_nshutdown_gpio");
+	if (unlikely(rc))
+		return rc;
+
+	rc = gpio_direction_output(pdata->nshutdown_gpio, 0);
+	if (unlikely(rc))
+		return rc;
+
+	rfkill_set_default(RFKILL_TYPE_BLUETOOTH, default_state);
+	wl127x_rfkill_set_power(NULL, default_state);
+
+	pdata->rfkill = rfkill_allocate(&pdev->dev, RFKILL_TYPE_BLUETOOTH);
+	if (unlikely(!pdata->rfkill))
+		return -ENOMEM;
+
+	pdata->rfkill->name = "wl127x";
+	pdata->rfkill->state = default_state;
+	/* userspace cannot take exclusive control */
+	pdata->rfkill->user_claim_unsupported = 1;
+	pdata->rfkill->user_claim = 0;
+	pdata->rfkill->data = (void *) pdata->nshutdown_gpio;
+	pdata->rfkill->toggle_radio = wl127x_rfkill_set_power;
+
+	rc = rfkill_register(pdata->rfkill);
+
+	if (unlikely(rc))
+		rfkill_free(pdata->rfkill);
+
+	return 0;
+}
+
+static int wl127x_rfkill_remove(struct platform_device *pdev)
+{
+	struct wl127x_rfkill_platform_data *pdata = pdev->dev.platform_data;
+
+	rfkill_unregister(pdata->rfkill);
+	rfkill_free(pdata->rfkill);
+	gpio_free(pdata->nshutdown_gpio);
+
+	return 0;
+}
+
+static struct platform_driver wl127x_rfkill_platform_driver = {
+	.probe = wl127x_rfkill_probe,
+	.remove = wl127x_rfkill_remove,
+	.driver = {
+		   .name = "wl127x-rfkill",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init wl127x_rfkill_init(void)
+{
+	return platform_driver_register(&wl127x_rfkill_platform_driver);
+}
+
+static void __exit wl127x_rfkill_exit(void)
+{
+	platform_driver_unregister(&wl127x_rfkill_platform_driver);
+}
+
+module_init(wl127x_rfkill_init);
+module_exit(wl127x_rfkill_exit);
+
+MODULE_ALIAS("platform:wl127x");
+MODULE_DESCRIPTION("wl127x-rfkill");
+MODULE_AUTHOR("Motorola");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/card/Kconfig b/drivers/mmc/card/Kconfig
index 3f2a912659a..86948f90c3f 100644
--- a/drivers/mmc/card/Kconfig
+++ b/drivers/mmc/card/Kconfig
@@ -32,6 +32,15 @@ config MMC_BLOCK_BOUNCE
 
 	  If unsure, say Y here.
 
+config MMC_BLOCK_DEFERRED_RESUME
+	bool "Deferr MMC layer resume until I/O is requested"
+	depends on MMC_BLOCK
+	default n
+	help
+	  Say Y here to enable deferred MMC resume until I/O
+	  is requested. This will reduce overall resume latency and
+	  save power when theres an SD card inserted but not being used.
+
 config SDIO_UART
 	tristate "SDIO UART/GPS class support"
 	help
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 1f552c6e757..8d2bd242ac6 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -241,6 +241,33 @@ static u32 get_card_status(struct mmc_card *card, struct request *req)
 	return cmd.resp[0];
 }
 
+static int
+mmc_blk_set_blksize(struct mmc_blk_data *md, struct mmc_card *card)
+{
+	struct mmc_command cmd;
+	int err;
+
+	/* Block-addressed cards ignore MMC_SET_BLOCKLEN. */
+	if (mmc_card_blockaddr(card))
+		return 0;
+
+	mmc_claim_host(card->host);
+	cmd.opcode = MMC_SET_BLOCKLEN;
+	cmd.arg = 512;
+	cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
+	err = mmc_wait_for_cmd(card->host, &cmd, 5);
+	mmc_release_host(card->host);
+
+	if (err) {
+		printk(KERN_ERR "%s: unable to set block size to %d: %d\n",
+			md->disk->disk_name, cmd.arg, err);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+
 static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 {
 	struct mmc_blk_data *md = mq->data;
@@ -248,6 +275,13 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 	struct mmc_blk_request brq;
 	int ret = 1, disable_multi = 0;
 
+#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME
+	if (mmc_bus_needs_resume(card->host)) {
+		mmc_resume_bus(card->host);
+		mmc_blk_set_blksize(md, card);
+	}
+#endif
+
 	mmc_claim_host(card->host);
 
 	do {
@@ -351,6 +385,8 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
 				continue;
 			}
 			status = get_card_status(card, req);
+		} else if (disable_multi == 1) {
+			disable_multi = 0;
 		}
 
 		if (brq.cmd.error) {
@@ -562,32 +598,6 @@ static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
 	return ERR_PTR(ret);
 }
 
-static int
-mmc_blk_set_blksize(struct mmc_blk_data *md, struct mmc_card *card)
-{
-	struct mmc_command cmd;
-	int err;
-
-	/* Block-addressed cards ignore MMC_SET_BLOCKLEN. */
-	if (mmc_card_blockaddr(card))
-		return 0;
-
-	mmc_claim_host(card->host);
-	cmd.opcode = MMC_SET_BLOCKLEN;
-	cmd.arg = 512;
-	cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
-	err = mmc_wait_for_cmd(card->host, &cmd, 5);
-	mmc_release_host(card->host);
-
-	if (err) {
-		printk(KERN_ERR "%s: unable to set block size to %d: %d\n",
-			md->disk->disk_name, cmd.arg, err);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
 static int mmc_blk_probe(struct mmc_card *card)
 {
 	struct mmc_blk_data *md;
@@ -616,6 +626,9 @@ static int mmc_blk_probe(struct mmc_card *card)
 		cap_str, md->read_only ? "(ro)" : "");
 
 	mmc_set_drvdata(card, md);
+#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME
+	mmc_set_bus_resume_policy(card->host, 1);
+#endif
 	add_disk(md->disk);
 	return 0;
 
@@ -640,6 +653,9 @@ static void mmc_blk_remove(struct mmc_card *card)
 		mmc_blk_put(md);
 	}
 	mmc_set_drvdata(card, NULL);
+#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME
+	mmc_set_bus_resume_policy(card->host, 0);
+#endif
 }
 
 #ifdef CONFIG_PM
@@ -658,7 +674,9 @@ static int mmc_blk_resume(struct mmc_card *card)
 	struct mmc_blk_data *md = mmc_get_drvdata(card);
 
 	if (md) {
+#ifndef CONFIG_MMC_BLOCK_DEFERRED_RESUME
 		mmc_blk_set_blksize(md, card);
+#endif
 		mmc_queue_resume(&md->queue);
 	}
 	return 0;
diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
index ab37a6d9d32..09a8766223a 100644
--- a/drivers/mmc/core/Kconfig
+++ b/drivers/mmc/core/Kconfig
@@ -14,3 +14,19 @@ config MMC_UNSAFE_RESUME
 	  This option is usually just for embedded systems which use
 	  a MMC/SD card for rootfs. Most people should say N here.
 
+config MMC_EMBEDDED_SDIO
+	boolean "MMC embedded SDIO device support (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	help
+	  If you say Y here, support will be added for embedded SDIO
+	  devices which do not contain the necessary enumeration
+	  support in hardware to be properly detected.
+
+config MMC_PARANOID_SD_INIT
+	bool "Enable paranoid SD card initialization (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	help
+	  If you say Y here, the MMC layer will be extra paranoid
+	  about re-trying SD init requests. This can be a useful
+	  work-around for buggy controllers and hardware. Enable
+	  if you are experiencing issues with SD detection.
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 7dab2e5f4bc..fb25fd001f4 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -22,6 +22,7 @@
 #include <linux/scatterlist.h>
 #include <linux/log2.h>
 #include <linux/regulator/consumer.h>
+#include <linux/wakelock.h>
 
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
@@ -38,6 +39,7 @@
 #include "sdio_ops.h"
 
 static struct workqueue_struct *workqueue;
+static struct wake_lock mmc_delayed_work_wake_lock;
 
 /*
  * Enabling software CRCs on the data blocks can be a significant (30%)
@@ -53,6 +55,7 @@ module_param(use_spi_crc, bool, 0);
 static int mmc_schedule_delayed_work(struct delayed_work *work,
 				     unsigned long delay)
 {
+	wake_lock(&mmc_delayed_work_wake_lock);
 	return queue_delayed_work(workqueue, work, delay);
 }
 
@@ -529,9 +532,12 @@ void mmc_host_deeper_disable(struct work_struct *work)
 
 	/* If the host is claimed then we do not want to disable it anymore */
 	if (!mmc_try_claim_host(host))
-		return;
+		goto out;
 	mmc_host_do_disable(host, 1);
 	mmc_do_release_host(host);
+
+out:
+	wake_unlock(&mmc_delayed_work_wake_lock);
 }
 
 /**
@@ -891,12 +897,7 @@ static void mmc_power_up(struct mmc_host *host)
 	 */
 	mmc_delay(10);
 
-	if (host->f_min > 400000) {
-		pr_warning("%s: Minimum clock frequency too high for "
-				"identification mode\n", mmc_hostname(host));
-		host->ios.clock = host->f_min;
-	} else
-		host->ios.clock = 400000;
+	host->ios.clock = host->f_min;
 
 	host->ios.power_mode = MMC_POWER_ON;
 	mmc_set_ios(host);
@@ -961,6 +962,30 @@ static inline void mmc_bus_put(struct mmc_host *host)
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
+int mmc_resume_bus(struct mmc_host *host)
+{
+	if (!mmc_bus_needs_resume(host))
+		return -EINVAL;
+
+	printk("%s: Starting deferred resume\n", mmc_hostname(host));
+	host->bus_resume_flags &= ~MMC_BUSRESUME_NEEDS_RESUME;
+	mmc_bus_get(host);
+	if (host->bus_ops && !host->bus_dead) {
+		mmc_power_up(host);
+		BUG_ON(!host->bus_ops->resume);
+		host->bus_ops->resume(host);
+	}
+
+	if (host->bus_ops->detect && !host->bus_dead)
+		host->bus_ops->detect(host);
+
+	mmc_bus_put(host);
+	printk("%s: Deferred resume completed\n", mmc_hostname(host));
+	return 0;
+}
+
+EXPORT_SYMBOL(mmc_resume_bus);
+
 /*
  * Assign a mmc bus handler to a host. Only one bus handler may control a
  * host at any given time.
@@ -1041,6 +1066,7 @@ void mmc_rescan(struct work_struct *work)
 		container_of(work, struct mmc_host, detect.work);
 	u32 ocr;
 	int err;
+	int extend_wakelock = 0;
 
 	mmc_bus_get(host);
 
@@ -1048,6 +1074,12 @@ void mmc_rescan(struct work_struct *work)
 	if ((host->bus_ops != NULL) && host->bus_ops->detect && !host->bus_dead)
 		host->bus_ops->detect(host);
 
+	/* If the card was removed the bus will be marked
+	 * as dead - extend the wakelock so userspace
+	 * can respond */
+	if (host->bus_dead)
+		extend_wakelock = 1;
+
 	mmc_bus_put(host);
 
 
@@ -1084,6 +1116,7 @@ void mmc_rescan(struct work_struct *work)
 	if (!err) {
 		if (mmc_attach_sdio(host, ocr))
 			mmc_power_off(host);
+		extend_wakelock = 1;
 		goto out;
 	}
 
@@ -1094,6 +1127,7 @@ void mmc_rescan(struct work_struct *work)
 	if (!err) {
 		if (mmc_attach_sd(host, ocr))
 			mmc_power_off(host);
+		extend_wakelock = 1;
 		goto out;
 	}
 
@@ -1104,6 +1138,7 @@ void mmc_rescan(struct work_struct *work)
 	if (!err) {
 		if (mmc_attach_mmc(host, ocr))
 			mmc_power_off(host);
+		extend_wakelock = 1;
 		goto out;
 	}
 
@@ -1111,6 +1146,11 @@ void mmc_rescan(struct work_struct *work)
 	mmc_power_off(host);
 
 out:
+	if (extend_wakelock)
+		wake_lock_timeout(&mmc_delayed_work_wake_lock, HZ / 2);
+	else
+		wake_unlock(&mmc_delayed_work_wake_lock);
+
 	if (host->caps & MMC_CAP_NEEDS_POLL)
 		mmc_schedule_delayed_work(&host->detect, HZ);
 }
@@ -1238,6 +1278,9 @@ int mmc_suspend_host(struct mmc_host *host, pm_message_t state)
 {
 	int err = 0;
 
+	if (mmc_bus_needs_resume(host))
+		return 0;
+
 	if (host->caps & MMC_CAP_DISABLE)
 		cancel_delayed_work(&host->disable);
 	cancel_delayed_work(&host->detect);
@@ -1279,6 +1322,12 @@ int mmc_resume_host(struct mmc_host *host)
 	int err = 0;
 
 	mmc_bus_get(host);
+	if (host->bus_resume_flags & MMC_BUSRESUME_MANUAL_RESUME) {
+		host->bus_resume_flags |= MMC_BUSRESUME_NEEDS_RESUME;
+		mmc_bus_put(host);
+		return 0;
+	}
+
 	if (host->bus_ops && !host->bus_dead) {
 		mmc_power_up(host);
 		mmc_select_voltage(host, host->ocr);
@@ -1312,10 +1361,28 @@ EXPORT_SYMBOL(mmc_resume_host);
 
 #endif
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+void mmc_set_embedded_sdio_data(struct mmc_host *host,
+				struct sdio_cis *cis,
+				struct sdio_cccr *cccr,
+				struct sdio_embedded_func *funcs,
+				int num_funcs)
+{
+	host->embedded_sdio_data.cis = cis;
+	host->embedded_sdio_data.cccr = cccr;
+	host->embedded_sdio_data.funcs = funcs;
+	host->embedded_sdio_data.num_funcs = num_funcs;
+}
+
+EXPORT_SYMBOL(mmc_set_embedded_sdio_data);
+#endif
+
 static int __init mmc_init(void)
 {
 	int ret;
 
+	wake_lock_init(&mmc_delayed_work_wake_lock, WAKE_LOCK_SUSPEND, "mmc_delayed_work");
+
 	workqueue = create_singlethread_workqueue("kmmcd");
 	if (!workqueue)
 		return -ENOMEM;
@@ -1350,6 +1417,7 @@ static void __exit mmc_exit(void)
 	mmc_unregister_host_class();
 	mmc_unregister_bus();
 	destroy_workqueue(workqueue);
+	wake_lock_destroy(&mmc_delayed_work_wake_lock);
 }
 
 subsys_initcall(mmc_init);
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index bfefce365ae..32af45c419f 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -207,7 +207,7 @@ static int mmc_read_ext_csd(struct mmc_card *card)
 	}
 
 	card->ext_csd.rev = ext_csd[EXT_CSD_REV];
-	if (card->ext_csd.rev > 3) {
+	if (card->ext_csd.rev > 5) {
 		printk(KERN_ERR "%s: unrecognised EXT_CSD structure "
 			"version %d\n", mmc_hostname(card->host),
 			card->ext_csd.rev);
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 10b2a4d20f5..9d92ca9db42 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -22,6 +22,8 @@
 #include "mmc_ops.h"
 #include "sd_ops.h"
 
+//#define CONFIG_MMC_PARANOID_SD_INIT
+
 static const unsigned int tran_exp[] = {
 	10000,		100000,		1000000,	10000000,
 	0,		0,		0,		0
@@ -336,7 +338,9 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr,
 	int err;
 	u32 cid[4];
 	unsigned int max_dtr;
-
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	int retries;
+#endif
 	BUG_ON(!host);
 	WARN_ON(!host->claimed);
 
@@ -439,11 +443,29 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr,
 		err = mmc_decode_scr(card);
 		if (err < 0)
 			goto free_card;
-
 		/*
 		 * Fetch switch information from card.
 		 */
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+		for (retries = 1; retries <= 3; retries++) {
+			err = mmc_read_switch(card);
+			if (!err) {
+				if (retries > 1) {
+					printk(KERN_WARNING
+					       "%s: recovered\n", 
+					       mmc_hostname(host));
+				}
+				break;
+			} else {
+				printk(KERN_WARNING
+				       "%s: read switch failed (attempt %d)\n",
+				       mmc_hostname(host), retries);
+			}
+		}
+#else
 		err = mmc_read_switch(card);
+#endif
+
 		if (err)
 			goto free_card;
 	}
@@ -538,18 +560,36 @@ static void mmc_sd_remove(struct mmc_host *host)
  */
 static void mmc_sd_detect(struct mmc_host *host)
 {
-	int err;
+	int err = 0;
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+        int retries = 5;
+#endif
 
 	BUG_ON(!host);
 	BUG_ON(!host->card);
-
+       
 	mmc_claim_host(host);
 
 	/*
 	 * Just check if our card has been removed.
 	 */
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	while(retries) {
+		err = mmc_send_status(host->card, NULL);
+		if (err) {
+			retries--;
+			udelay(5);
+			continue;
+		}
+		break;
+	}
+	if (!retries) {
+		printk(KERN_ERR "%s(%s): Unable to re-detect card (%d)\n",
+		       __func__, mmc_hostname(host), err);
+	}
+#else
 	err = mmc_send_status(host->card, NULL);
-
+#endif
 	mmc_release_host(host);
 
 	if (err) {
@@ -587,12 +627,31 @@ static int mmc_sd_suspend(struct mmc_host *host)
 static int mmc_sd_resume(struct mmc_host *host)
 {
 	int err;
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	int retries;
+#endif
 
 	BUG_ON(!host);
 	BUG_ON(!host->card);
 
 	mmc_claim_host(host);
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	retries = 5;
+	while (retries) {
+		err = mmc_sd_init_card(host, host->ocr, host->card);
+
+		if (err) {
+			printk(KERN_ERR "%s: Re-init card rc = %d (retries = %d)\n",
+			       mmc_hostname(host), err, retries);
+			mdelay(5);
+			retries--;
+			continue;
+		}
+		break;
+	}
+#else
 	err = mmc_sd_init_card(host, host->ocr, host->card);
+#endif
 	mmc_release_host(host);
 
 	return err;
@@ -658,6 +717,9 @@ static void mmc_sd_attach_bus_ops(struct mmc_host *host)
 int mmc_attach_sd(struct mmc_host *host, u32 ocr)
 {
 	int err;
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	int retries;
+#endif
 
 	BUG_ON(!host);
 	WARN_ON(!host->claimed);
@@ -706,9 +768,27 @@ int mmc_attach_sd(struct mmc_host *host, u32 ocr)
 	/*
 	 * Detect and init the card.
 	 */
+#ifdef CONFIG_MMC_PARANOID_SD_INIT
+	retries = 5;
+	while (retries) {
+		err = mmc_sd_init_card(host, host->ocr, NULL);
+		if (err) {
+			retries--;
+			continue;
+		}
+		break;
+	}
+
+	if (!retries) {
+		printk(KERN_ERR "%s: mmc_sd_init_card() failure (err = %d)\n",
+		       mmc_hostname(host), err);
+		goto err;
+	}
+#else
 	err = mmc_sd_init_card(host, host->ocr, NULL);
 	if (err)
 		goto err;
+#endif
 
 	mmc_release_host(host);
 
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index cdb845b68ab..ac9102487e2 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -24,6 +24,10 @@
 #include "sdio_ops.h"
 #include "sdio_cis.h"
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+#include <linux/mmc/sdio_ids.h>
+#endif
+
 static int sdio_read_fbr(struct sdio_func *func)
 {
 	int ret;
@@ -279,19 +283,35 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr,
 			goto remove;
 	}
 
-	/*
-	 * Read the common registers.
-	 */
-	err = sdio_read_cccr(card);
-	if (err)
-		goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	if (host->embedded_sdio_data.cccr)
+		memcpy(&card->cccr, host->embedded_sdio_data.cccr, sizeof(struct sdio_cccr));
+	else {
+#endif
+		/*
+		 * Read the common registers.
+		 */
+		err = sdio_read_cccr(card);
+		if (err)
+			goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	}
+#endif
 
-	/*
-	 * Read the common CIS tuples.
-	 */
-	err = sdio_read_common_cis(card);
-	if (err)
-		goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	if (host->embedded_sdio_data.cis)
+		memcpy(&card->cis, host->embedded_sdio_data.cis, sizeof(struct sdio_cis));
+	else {
+#endif
+		/*
+		 * Read the common CIS tuples.
+		 */
+		err = sdio_read_common_cis(card);
+		if (err)
+			goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	}
+#endif
 
 	if (oldcard) {
 		int same = (card->cis.vendor == oldcard->cis.vendor &&
@@ -518,6 +538,11 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
 	 */
 	card->sdio_funcs = funcs = (ocr & 0x70000000) >> 28;
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	if (host->embedded_sdio_data.funcs)
+		card->sdio_funcs = funcs = host->embedded_sdio_data.num_funcs;
+#endif
+
 	/*
 	 * If needed, disconnect card detection pull-up resistor.
 	 */
@@ -529,9 +554,27 @@ int mmc_attach_sdio(struct mmc_host *host, u32 ocr)
 	 * Initialize (but don't add) all present functions.
 	 */
 	for (i = 0;i < funcs;i++) {
-		err = sdio_init_func(host->card, i + 1);
-		if (err)
-			goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+		if (host->embedded_sdio_data.funcs) {
+			struct sdio_func *tmp;
+
+			tmp = sdio_alloc_func(host->card);
+			if (IS_ERR(tmp))
+				goto remove;
+			tmp->num = (i + 1);
+			card->sdio_func[i] = tmp;
+			tmp->class = host->embedded_sdio_data.funcs[i].f_class;
+			tmp->max_blksize = host->embedded_sdio_data.funcs[i].f_maxblksize;
+			tmp->vendor = card->cis.vendor;
+			tmp->device = card->cis.device;
+		} else {
+#endif
+			err = sdio_init_func(host->card, i + 1);
+			if (err)
+				goto remove;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+		}
+#endif
 	}
 
 	mmc_release_host(host);
@@ -573,3 +616,82 @@ err:
 	return err;
 }
 
+int sdio_reset_comm(struct mmc_card *card)
+{
+	struct mmc_host *host = card->host;
+	u32 ocr;
+	int err;
+
+	printk("%s():\n", __func__);
+	mmc_claim_host(host);
+
+	mmc_go_idle(host);
+
+	mmc_set_clock(host, host->f_min);
+
+	err = mmc_send_io_op_cond(host, 0, &ocr);
+	if (err)
+		goto err;
+
+	host->ocr = mmc_select_voltage(host, ocr);
+	if (!host->ocr) {
+		err = -EINVAL;
+		goto err;
+	}
+
+	err = mmc_send_io_op_cond(host, host->ocr, &ocr);
+	if (err)
+		goto err;
+
+	if (mmc_host_is_spi(host)) {
+		err = mmc_spi_set_crc(host, use_spi_crc);
+		if (err)
+		goto err;
+	}
+
+	if (!mmc_host_is_spi(host)) {
+		err = mmc_send_relative_addr(host, &card->rca);
+		if (err)
+			goto err;
+		mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL);
+	}
+	if (!mmc_host_is_spi(host)) {
+		err = mmc_select_card(card);
+		if (err)
+			goto err;
+	}
+
+	/*
+	 * Switch to high-speed (if supported).
+	 */
+	err = sdio_enable_hs(card);
+	if (err)
+		goto err;
+
+	/*
+	 * Change to the card's maximum speed.
+	 */
+	if (mmc_card_highspeed(card)) {
+		/*
+		 * The SDIO specification doesn't mention how
+		 * the CIS transfer speed register relates to
+		 * high-speed, but it seems that 50 MHz is
+		 * mandatory.
+		 */
+		mmc_set_clock(host, 50000000);
+	} else {
+		mmc_set_clock(host, card->cis.max_dtr);
+	}
+
+	err = sdio_enable_wide(card);
+	if (err)
+		goto err;
+	mmc_release_host(host);
+	return 0;
+err:
+	printk("%s: Error resetting SDIO communications (%d)\n",
+	       mmc_hostname(host), err);
+	mmc_release_host(host);
+	return err;
+}
+EXPORT_SYMBOL(sdio_reset_comm);
diff --git a/drivers/mmc/core/sdio_bus.c b/drivers/mmc/core/sdio_bus.c
index d37464e296a..0b1d2143ed2 100644
--- a/drivers/mmc/core/sdio_bus.c
+++ b/drivers/mmc/core/sdio_bus.c
@@ -20,6 +20,10 @@
 #include "sdio_cis.h"
 #include "sdio_bus.h"
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+#include <linux/mmc/host.h>
+#endif
+
 /* show configuration fields */
 #define sdio_config_attr(field, format_string)				\
 static ssize_t								\
@@ -199,7 +203,14 @@ static void sdio_release_func(struct device *dev)
 {
 	struct sdio_func *func = dev_to_sdio_func(dev);
 
-	sdio_free_func_cis(func);
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	/*
+	 * If this device is embedded then we never allocated
+	 * cis tables for this func
+	 */
+	if (!func->card->host->embedded_sdio_data.funcs)
+#endif
+		sdio_free_func_cis(func);
 
 	if (func->info)
 		kfree(func->info);
diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c
index f9aa8a7deff..6bb0654a0d4 100644..100755
--- a/drivers/mmc/core/sdio_io.c
+++ b/drivers/mmc/core/sdio_io.c
@@ -378,6 +378,39 @@ u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret)
 EXPORT_SYMBOL_GPL(sdio_readb);
 
 /**
+ *	sdio_readb_ext - read a single byte from a SDIO function
+ *	@func: SDIO function to access
+ *	@addr: address to read
+ *	@err_ret: optional status value from transfer
+ *	@in: value to add to argument
+ *
+ *	Reads a single byte from the address space of a given SDIO
+ *	function. If there is a problem reading the address, 0xff
+ *	is returned and @err_ret will contain the error code.
+ */
+unsigned char sdio_readb_ext(struct sdio_func *func, unsigned int addr,
+	int *err_ret, unsigned in)
+{
+	int ret;
+	unsigned char val;
+
+	BUG_ON(!func);
+
+	if (err_ret)
+		*err_ret = 0;
+
+	ret = mmc_io_rw_direct(func->card, 0, func->num, addr, (u8)in, &val);
+	if (ret) {
+		if (err_ret)
+			*err_ret = ret;
+		return 0xFF;
+	}
+
+	return val;
+}
+EXPORT_SYMBOL_GPL(sdio_readb_ext);
+
+/**
  *	sdio_writeb - write a single byte to a SDIO function
  *	@func: SDIO function to access
  *	@b: byte to write
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 432ae8358c8..8ad495e1d3f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -357,3 +357,7 @@ config MMC_VIA_SDMMC
 	  If you have a controller with this interface, say Y or M here.
 
 	  If unsure, say N.
+
+source "drivers/mmc/host/ak88-mmc/Kconfig"
+source "drivers/mmc/host/ak98-mmc/Kconfig"
+
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index abcb0400e06..2e38f2ac65d 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -34,6 +34,8 @@ obj-$(CONFIG_MMC_SDRICOH_CS)	+= sdricoh_cs.o
 obj-$(CONFIG_MMC_TMIO)		+= tmio_mmc.o
 obj-$(CONFIG_MMC_CB710)	+= cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)	+= via-sdmmc.o
+obj-$(CONFIG_MMC_AK88)	+= ak88-mmc/
+obj-$(CONFIG_ARCH_AK98)	+= ak98-mmc/
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
diff --git a/drivers/mmc/host/ak88-mmc/Kconfig b/drivers/mmc/host/ak88-mmc/Kconfig
new file mode 100644
index 00000000000..3e201ebab31
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/Kconfig
@@ -0,0 +1,10 @@
+
+
+config MMC_AK88
+    tristate "AK88 AK7801 MMC/SD Card Interface support"
+    depends on ARCH_AK88
+    help
+      This selects the AK88 AK7801 MMC/SD card Interface.
+      say Y or M here.
+      If unsure, say N.
+
diff --git a/drivers/mmc/host/ak88-mmc/Makefile b/drivers/mmc/host/ak88-mmc/Makefile
new file mode 100644
index 00000000000..967779e4439
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_MMC_AK88)    += ak88_mci.o
+
diff --git a/drivers/mmc/host/ak88-mmc/ak880x_l2.c b/drivers/mmc/host/ak88-mmc/ak880x_l2.c
new file mode 100644
index 00000000000..51d448a44fa
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/ak880x_l2.c
@@ -0,0 +1,173 @@
+/*
+ * support l2 dma
+ * 09-09-10 16:46:47
+ */
+
+#include <mach/ak880x_addr.h>
+
+/* #define L2_BASE_ADDR	0x2002c000	//L2 PA*/
+#define L2_BASE_ADDR	AK88_VA_L2CTRL	//L2 VA
+#define L2_BUF_MEM_BASE_ADDR	    	0x48000000  //L2 Buffer start address
+#define	L2_DMA_ADDR	AK88_L2CTRL_REG(0x00)
+#define	L2_DMA_CNT	AK88_L2CTRL_REG(0x40)
+#define	L2_DMA_REQ	AK88_L2CTRL_REG(0x80)
+#define	L2_FRAC_ADDR	AK88_L2CTRL_REG(0x84)
+#define	L2_COMBUF_CFG	AK88_L2CTRL_REG(0x88)
+#define	L2_UARTBUF_CFG	AK88_L2CTRL_REG(0x8c)
+#define	L2_ASSIGN_REG1	AK88_L2CTRL_REG(0x90)
+#define	L2_ASSIGN_REG2	AK88_L2CTRL_REG(0x94)
+#define	L2_LDMA_CFG	AK88_L2CTRL_REG(0x98)
+#define	L2_INT_ENA	AK88_L2CTRL_REG(0x9c)
+#define	L2_STAT_REG1	AK88_L2CTRL_REG(0xa0)
+#define	L2_STAT_REG2	AK88_L2CTRL_REG(0xa8)
+
+#define L2_SD_BUFX	2 /* assign l2 buf2 to sd */ 
+
+#define L2_USING	1
+
+#define l2_write(reg, val) __raw_writel((val), (reg))
+#define l2_read(reg)	__raw_readl(reg)
+
+void l2_init(void)
+{
+	unsigned int regval;
+
+	/* l2_write(L2_INT_ENA, 0); */
+
+	regval = l2_read(L2_DMA_REQ);
+	regval |= 0x1;
+	l2_write(L2_DMA_REQ, regval);
+
+	regval = l2_read(L2_COMBUF_CFG);
+	regval |= 0x1<<(16+L2_SD_BUFX) | 0x1<<L2_SD_BUFX;
+	l2_write(L2_COMBUF_CFG, regval);
+}
+
+void l2_pre(int buf_id, int addr, int size, int dir)
+{
+	unsigned int regval;
+
+	l2_init();
+
+	/* l2_write(L2_COMBUF_CFG, 0xffff00ff); */
+	regval = l2_read(L2_COMBUF_CFG) | 0x1<<(24+buf_id);
+	l2_write(L2_COMBUF_CFG, regval);
+	/* dbg("L2_COMBUF_CFG(0x%x), regval(0x%x)", l2_read(L2_COMBUF_CFG), regval); */
+
+        /*
+	 * if (dir) [> write <]
+	 *         regval = l2_read(L2_COMBUF_CFG) | 0x1<<(8+buf_id);
+	 * else
+	 *         regval = l2_read(L2_COMBUF_CFG) & ~(0x1<<(8+buf_id));
+	 * l2_write(L2_COMBUF_CFG, regval);
+         */
+
+	regval = l2_read(L2_ASSIGN_REG1);
+	regval &= ~(0x7<<12); /* sd */ 
+	regval |= (buf_id & 0x7) << 12;
+	l2_write(L2_ASSIGN_REG1, regval);
+	/* dbg("L2_ASSIGN_REG1(0x%x), regval(0x%x)", l2_read(L2_ASSIGN_REG1), regval); */
+}
+
+#if 0
+void l2_write_pre(int buf_id, int addr, int size, int dir)
+{
+	unsigned int regval;
+
+	/* l2_write(L2_COMBUF_CFG, 0xffff00ff); */
+	regval = l2_read(L2_COMBUF_CFG) | 0x1<<(24+buf_id);
+	l2_write(L2_COMBUF_CFG, regval);
+	dbg("L2_COMBUF_CFG(0x%x), regval(0x%x)", l2_read(L2_COMBUF_CFG), regval);
+
+	regval = l2_read(L2_ASSIGN_REG1);
+	regval &= ~(0x7<<12); /* sd */ 
+	regval |= (buf_id & 0x7) << 12;
+	l2_write(L2_ASSIGN_REG1, regval);
+	dbg("L2_ASSIGN_REG1(0x%x), regval(0x%x)", l2_read(L2_ASSIGN_REG1), regval);
+
+	regval = addr & ~(0xf<<28); /* 28 bits */ 
+	l2_write(L2_DMA_ADDR + (buf_id<<2), regval);
+
+	regval = (size>>6) & 0xff;
+	l2_write(L2_DMA_CNT + (buf_id<<2), regval);
+
+	if (dir) /* write */
+		regval = l2_read(L2_COMBUF_CFG) | 0x1<<(8+buf_id);
+	else
+		regval = l2_read(L2_COMBUF_CFG) & ~(0x1<<(8+buf_id));
+	l2_write(L2_COMBUF_CFG, regval);
+	
+	regval = l2_read(L2_DMA_REQ);
+	regval &= ~((1<<9) | (0xffff<<16));
+	regval |= 1 << (24+buf_id);
+	l2_write(L2_DMA_REQ, regval);
+
+        /*
+	 * regval = l2_read(L2_ASSIGN_REG1);
+	 * regval &= ~(0x7<<12); [> sd <] 
+	 * regval |= (buf_id & 0x7) << 12;
+	 * l2_write(L2_ASSIGN_REG1, regval);
+	 * dbg("L2_ASSIGN_REG1(0x%x), regval(0x%x)", l2_read(L2_ASSIGN_REG1), regval);
+         */
+}
+
+void l2_write_pre_2(int buf_id)
+{
+	unsigned int regval;
+
+	while (l2_read(L2_DMA_REQ) & (1<<24+buf_id));
+	
+        /*
+	 * regval = l2_read(L2_ASSIGN_REG1);
+	 * regval &= ~(0x7<<12); [> sd <] 
+	 * regval |= (buf_id & 0x7) << 12;
+	 * l2_write(L2_ASSIGN_REG1, regval);
+	 * dbg("L2_ASSIGN_REG1(0x%x), regval(0x%x)", l2_read(L2_ASSIGN_REG1), regval);
+         */
+}
+
+
+void l2_write_dma(int buf_id, int addr, int size, int dir)
+{
+	int i = 0;
+	dbg("waiting %d", i);
+}
+#endif
+
+void l2_dma(int buf_id, int addr, int size, int dir)
+{
+	unsigned int regval;
+	int timeout;
+
+	regval = addr & ~(0xf<<28);
+	l2_write(L2_DMA_ADDR + (buf_id<<2), regval);
+	/* dbg("L2_DMA_ADDR(0x%x), regval(0x%x)", l2_read(L2_DMA_ADDR + (buf_id<<2)), regval); */
+
+	regval = size>>6 & 0xff;
+	l2_write(L2_DMA_CNT + (buf_id<<2), regval);
+	/* dbg("L2_DMA_CNT(0x%x), regval(0x%x)", l2_read(L2_DMA_CNT + (buf_id<<2)), regval); */
+
+	regval = l2_read(L2_COMBUF_CFG);
+	regval |= 0x1<<buf_id | 0x1<<(16+buf_id);
+	if (dir)
+		regval |= 0x1<<(8+buf_id);
+	else
+		regval &= ~(0x1<<(8+buf_id));
+	l2_write(L2_COMBUF_CFG, regval);
+	/* dbg("L2_COMBUF_CFG(0x%x), regval(0x%x)", l2_read(L2_COMBUF_CFG), regval); */
+
+	regval = l2_read(L2_DMA_REQ);
+	regval &= ~((1<<9) | 0xffff<<16);
+	regval |= 0x1<<(24+buf_id);
+	l2_write(L2_DMA_REQ, regval);
+
+	timeout = 50000;
+	while ((l2_read(L2_DMA_REQ) & (0x1<<(24+buf_id))) && timeout) {  /* poll */
+		timeout--;
+	}
+	dbg("waiting %d", timeout);
+}
+void l2_post(int buf_id)
+{
+	l2_write(L2_DMA_CNT + (buf_id<<2), 0);
+}
diff --git a/drivers/mmc/host/ak88-mmc/ak880x_mci.c b/drivers/mmc/host/ak88-mmc/ak880x_mci.c
new file mode 100644
index 00000000000..b36f9c380ed
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/ak880x_mci.c
@@ -0,0 +1,612 @@
+/*
+ *  linux/drivers/mmc/host/ak880x_mci.c
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/mmc.h>
+
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+
+#include <mach/gpio.h>
+
+#include "ak880x_mci.h"
+
+extern struct mutex nand_lock;
+
+#define DRIVER_NAME	"ak880x-mci"
+
+#if 0
+#define dbg(fmt, arg...) printk("%s(%d): " fmt "\n", __func__, __LINE__, ##arg)
+#else
+#define dbg(fmt, arg...)
+#endif
+
+#include "ak880x_l2.c"
+
+#define mci_read(host, reg)		__raw_readl((host)->baseaddr + (reg))
+#define mci_write(host, reg, val) 	__raw_writel((val), (host)->baseaddr + (reg))
+
+#define SD_PWRON	AK88_DGPIO_24
+
+struct ak880xmci_host {
+	struct mmc_host	*mmc;
+	struct clk	*clk;
+	unsigned int	irq;
+	unsigned long	clkrate;
+
+	void __iomem	*baseaddr;
+	int		bus_mode;
+	int		bus_width;
+	int		flags;
+	struct completion	completion;
+	struct mmc_request	*request;
+	struct mmc_command	*cmd;
+
+	/* for dma */
+	unsigned int	*buffer;
+	dma_addr_t	phy_addr;
+	unsigned int	total_len;
+	volatile unsigned int	xfer_index;
+	volatile unsigned int	blocks;
+};
+
+static void rcv_resp(struct ak880xmci_host *host, struct mmc_command *cmd)
+{
+	cmd->resp[0] = mci_read(host, MMC_RESP1);
+	cmd->resp[1] = mci_read(host, MMC_RESP2);
+	cmd->resp[2] = mci_read(host, MMC_RESP3);
+	cmd->resp[3] = mci_read(host, MMC_RESP4);
+	if (mmc_resp_type(cmd) & MMC_RSP_OPCODE) {
+		int rsp_opcode = mci_read(host, MMC_CMD_RESP);
+		/* dbg("rsp_opcode(%d)", rsp_opcode); */
+	}
+}
+
+static void mci_xfer(struct ak880xmci_host *host)
+{
+	int i = 0;
+	struct mmc_data *data = host->cmd->data;
+	unsigned int *sgbuffer;
+
+	if (!data)
+		return;
+
+	if (host->xfer_index<<2 >= host->total_len) {
+		dbg("xfer overflow");
+		return;
+	}
+	if (host->blocks >= data->blocks) {
+		dbg("xfer overflow");
+		return;
+	}
+
+	sgbuffer = sg_virt(data->sg);
+
+	if (data->flags & MMC_DATA_READ) {
+		unsigned long regval;
+#ifdef L2_USING
+		if (host->total_len >= 64) {
+			dma_addr_t phy_addr = sg_phys(data->sg) + host->blocks*data->blksz;
+			l2_dma(L2_SD_BUFX, phy_addr, data->blksz, 0);
+
+			host->blocks++;
+		} else  
+#endif
+		{
+			regval = mci_read(host, MMC_CPU_MODE);
+			if (regval) {
+				/* dbg("[%d] r,MMC_CPU_MODE(0x%x)", host->xfer_index, regval); */
+			}
+			sgbuffer[host->xfer_index++] = regval;
+		}
+	} else if (data->flags & MMC_DATA_WRITE) {
+#ifdef L2_USING
+		dma_addr_t phy_addr;
+
+		host->blocks++;
+		if (host->blocks < data->blocks) {
+			phy_addr = sg_phys(data->sg) + host->blocks*data->blksz;
+			l2_dma(L2_SD_BUFX, phy_addr, data->blksz, 1);
+		}
+#else
+		unsigned long val;
+		val = sgbuffer[host->xfer_index++];
+		mci_write(host, MMC_CPU_MODE, val);
+		if (val)
+			dbg("[%d], w,MMC_CPU_MODE(0x%x)", host->xfer_index, val);
+#endif /* L2_USING */
+	}
+}
+
+static void ak880xmci_setup_data(struct ak880xmci_host *host, struct mmc_data *data)
+{
+	unsigned int regval, timeout, length;
+	struct mmc_command *cmd = host->cmd;
+
+	if (data->blksz & 0x3) {
+		dbg("Unsopported block size");
+		cmd->error = -EINVAL;
+		mmc_request_done(host->mmc, host->request);
+		return;
+	}
+
+	length = data->blksz * data->blocks;
+	timeout = (data->timeout_ns / 1000000) * (host->clkrate / 1000); /* mci clocks */ 
+#ifdef L2_USING
+	if (length >= 64) {
+		regval = 0x1<<0 | 0x1<<16 | (data->blksz>>2)<<17;
+		/* regval = 0x1<<0 | (data->blksz>>2)<<17; */
+		mci_write(host, MMC_DMA_MODE, regval);
+		dbg("dmareg(0x%x)", regval);
+	} else
+#endif
+	{
+		regval = mci_read(host, MMC_INT_CTRL);
+		mci_write(host, MMC_INT_CTRL, regval | (0x1<<12));
+		mci_write(host, MMC_DMA_MODE, 0);
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+#ifdef L2_USING
+		if (length >= 64)
+			l2_pre(L2_SD_BUFX, 0, 0, 0);
+	} else if (data->flags & MMC_DATA_WRITE) {
+		dma_addr_t phy_addr;
+		phy_addr = sg_phys(data->sg);
+		l2_pre(L2_SD_BUFX, 0, 0, 0);
+		l2_dma(L2_SD_BUFX, phy_addr, data->blksz, 1);
+#endif
+	}
+
+	host->total_len = length;
+	host->xfer_index = 0;
+	host->blocks = 0;
+
+	mci_write(host, MMC_DATA_TIMER, timeout);
+	mci_write(host, MMC_DATA_LENGTH, length);
+
+	regval = (data->blksz & 0xfff) << 16;
+	if (host->bus_width == MMC_BUS_WIDTH_4)
+		regval |= 0x1<<3;
+	if (data->flags & MMC_DATA_STREAM)
+		regval |= 0x1<<2;
+	if (data->flags & MMC_DATA_READ) 
+		regval |= 0x1<<1;
+	regval |= 0x1<<0;
+	mci_write(host, MMC_DATA_CONTROL, regval);
+}
+
+/*
+ * #undef dbg(fmt, arg...)
+ * #define dbg(fmt, arg...)
+ */
+
+#define STATUS_ERROR (0x1<<0 | 0x1<<1 | 0x1<<2 | 0x1<<3 | 0x1<<8)
+static irqreturn_t ak880xmci_irq(int irq, void *dev)
+{
+	int status;
+	int completed;
+	struct ak880xmci_host *host = (struct ak880xmci_host*)dev;
+	struct mmc_command *cmd = host->cmd;
+	struct mmc_data *data = cmd->data;
+
+	status = mci_read(host, MMC_STATUS);
+	if (status != 0x1800)
+		dbg("status(0x%x)", status);
+
+	if (status & STATUS_ERROR) {
+		completed = 2;
+		if (status & 0x1<<0) {
+			cmd->error |= -EILSEQ;
+			printk("Cmd crc check FAILED\n");
+		}
+		if (status & 0x1<<1) {
+			data->error |= -EILSEQ;
+			printk("Data crc check FAILED");
+		}
+		if (status & 0x1<<2) {
+			cmd->error |= -ETIMEDOUT;
+			dbg("Cmd response is TIMEOUT\n");
+		}
+		if (status & 0x1<<3) {
+			data->error |= -ETIMEDOUT;
+			printk("Data is TIMEOUT\n");
+		}
+		if (status & 0x1<<8) {	
+			data->error |= -EILSEQ;
+			printk("Start bit ERR\n");
+		}
+	} else {
+		if (status & 0x1<<4) {
+			completed = 1;
+			rcv_resp(host, cmd);
+			dbg("Command response has been received");
+		}
+		if (status & 0x1<<5) {
+			completed = 1;
+			dbg("Cmd send successfully, no response");
+		}
+		if (status & 0x1<<7) { /* data block end */ 
+#ifdef L2_USING
+			if ((host->total_len >= 64) && data) {
+				mci_xfer(host);
+				completed = 0;
+			}
+#endif
+			dbg("Data block has been sent/received");
+		}
+		if (status & 0x1<<9) {
+			completed = 0;
+			dbg("Transferring command");
+		}
+		if (status & 0x1<<10) {
+			completed = 0;
+			/* dbg("Transmitting data"); */
+		}
+		if (status & 0x1<<11) {
+			completed = 0;
+		}
+		if (status & 0x1<<12) { /* Data buffer full */ 
+			if (!mci_read(host, MMC_DMA_MODE)) /* cpu mode */
+				if (data && (data->flags & MMC_DATA_READ)) {
+					mci_xfer(host);
+					completed = 0;
+				}
+			/* dbg("Data buffer full"); */
+		}
+		if (status & 0x1<<13) { /* Data buffer empty */ 
+#ifndef L2_USING
+			if (data && (data->flags & MMC_DATA_WRITE)) {
+				if (!(status & 0x1<<4))
+					mci_xfer(host);
+				completed = 0;
+			}
+#endif
+		}
+		if (status & 0x1<<15) { /* half empty */ 
+			if (data)
+				completed = 0;
+		}
+		if (status & 0x1<<6) {
+			completed = 2;
+			dbg("Data transfer ends");
+		}
+	}
+
+	switch (completed) {
+		case 1:
+			if (data) {
+				ak880xmci_setup_data(host, data);
+				break;
+			}
+		case 2:
+			complete(&host->completion);
+			break;
+		default:
+			/* do nothing */
+			break;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void ak880xmci_setup_cmd(struct ak880xmci_host *host,struct mmc_command *cmd)
+{
+	unsigned int regval;
+
+	regval = 0x1ff;
+	mci_write(host, MMC_INT_CTRL, regval); 
+
+	/* if (cmd->arg) */
+	mci_write(host, MMC_CMD_ARG, cmd->arg); /* Needed each time */ 
+
+	regval = 0;
+	if (mmc_resp_type(cmd) & MMC_RSP_CRC)
+		regval &= ~(0x1<<10);
+	else
+		regval |= 0x1<<10;
+	if (mmc_resp_type(cmd) & MMC_RSP_136)
+		regval |= 0x1<<8;
+	if (mmc_cmd_type(cmd) !=  MMC_CMD_BC) /* ac, bcr */ 
+		regval |= 0x1<<7;
+	regval |= (cmd->opcode&0x3f)<<1; /* 6 bits */ 
+	regval |= 0x1<<0;
+	mci_write(host, MMC_CMD_REG, regval);
+
+	wait_for_completion_interruptible(&host->completion);
+}
+
+
+static void ak880xmci_request_done(struct ak880xmci_host *host, struct mmc_request *mrq)
+{
+	struct mmc_data *data = mrq->data;
+
+	if (data) {
+		if (!data->error)
+			data->bytes_xfered = data->blocks * data->blksz;
+		else
+			data->bytes_xfered = 0;
+	}
+
+	mci_write(host, MMC_INT_CTRL, 0);  /* clear irq */ 
+	mci_write(host, MMC_DMA_MODE, 0); /* need */ 
+#ifdef L2_USING
+	l2_post(L2_SD_BUFX);
+#endif
+
+	mmc_request_done(host->mmc, mrq);
+	/* printk("         ********\n");  */
+}
+
+static void ak880xmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct ak880xmci_host *host = mmc_priv(mmc);
+
+	host->request = mrq;
+	host->cmd = host->request->cmd;
+
+	if (mutex_lock_interruptible(&nand_lock))
+		printk("lock error");
+
+	ak880xmci_setup_cmd(host, mrq->cmd);
+
+	mutex_unlock(&nand_lock);
+
+	if (mrq->stop) {
+		host->cmd = host->request->stop;
+		ak880xmci_setup_cmd(host, mrq->stop);
+	}
+
+	ak880xmci_request_done(host, mrq);
+}
+
+static void ak880xmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct ak880xmci_host *host = mmc_priv(mmc);
+	int regval;
+
+	host->bus_mode = ios->bus_mode;
+	host->bus_width = ios->bus_width;
+		
+	switch (ios->power_mode) {
+		case MMC_POWER_UP:
+			break;
+		case MMC_POWER_ON:
+		{	
+			/* pull up enable */
+			ak880x_gpio_pullup(AK88_GPIO_72, 1);
+			ak880x_gpio_pullup(AK88_GPIO_73, 1);
+			ak880x_gpio_pullup(AK88_GPIO_74, 1);
+			ak880x_gpio_pullup(AK88_GPIO_75, 1);
+			ak880x_gpio_pullup(AK88_GPIO_39, 1); /* MMC_MCD */ 
+			ak880x_gpio_pullup(AK88_GPIO_40, 1); /* MMC_MCK */ 
+			ak880x_gpio_cfgpin(SD_PWRON, AK88_GPIO_OUT_0);
+			ak880x_gpio_pullup(SD_PWRON, 1);
+			ak880x_gpio_setpin(SD_PWRON, 0);
+			AK88_GPIO_MDAT2(1);
+			AK88_MCI_ENABLE();
+
+			break;
+		}
+		case MMC_POWER_OFF:
+		default:
+		{
+			AK88_MCI_DISABLE();
+			AK88_GPIO_MDAT2(0);
+			ak880x_gpio_cfgpin(SD_PWRON, AK88_GPIO_OUT_0);
+			ak880x_gpio_pullup(SD_PWRON, 1);
+			ak880x_gpio_setpin(SD_PWRON, 1);
+			ak880x_gpio_pullup(AK88_GPIO_72, 1);
+			ak880x_gpio_pullup(AK88_GPIO_73, 1);
+			ak880x_gpio_pullup(AK88_GPIO_74, 1);
+			ak880x_gpio_pullup(AK88_GPIO_75, 1);
+			ak880x_gpio_pullup(AK88_GPIO_39, 1); /* MMC_MCD */ 
+			ak880x_gpio_pullup(AK88_GPIO_40, 1); /* MMC_MCK */ 
+			break;
+
+		}
+	}
+	
+	if (ios->clock == 0) {
+		/* Disable SD clock */
+                /*
+		 * regval = mci_read(host, MMC_CLK_CTRL);
+		 * regval &= ~(0x1<<20 | 0x1<<16);
+                 */
+		regval = 0;
+	} else {
+		/* Enable & setup SD clock */
+		clk_enable(host->clk);
+		clk_set_rate(host->clk, ios->clock);
+		regval = mci_read(host, MMC_CLK_CTRL);
+		regval |= 0x1<<20 | 0x1<<19 | 0x1<<17 | 0x1<<16;
+	}
+	mci_write(host, MMC_CLK_CTRL, regval);
+	host->clkrate = clk_get_rate(host->clk);
+	
+	/* printk("ios->clock(%d), host->clkrate(%d), MMC_CLK_CTRL(0x%x)\n", ios->clock, host->clkrate, mci_read(host, MMC_CLK_CTRL)); */
+}
+
+static int ak880xmci_get_ro(struct mmc_host *host)
+{
+	dbg("");
+	return 0;
+}
+
+static struct mmc_host_ops ak880xmci_ops = {
+	.request	= ak880xmci_request,
+  	.set_ios	= ak880xmci_set_ios,
+	.get_ro		= ak880xmci_get_ro,
+};
+
+static int ak880xmci_probe(struct platform_device *pdev)
+{
+	struct mmc_host *mmc;
+	struct ak880xmci_host *host;
+	struct resource *res;
+	int ret;
+
+#ifdef L2_USING
+	/* rCLK_CON &= (0x1<<15); [> lTo enable L2 controller/UART1 working clock <] */
+	/* l2_init(); */
+#endif
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dbg("");
+		return -ENXIO;
+	}
+	if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) {
+		dbg("");
+		return -EBUSY;
+	}
+
+	mmc = mmc_alloc_host(sizeof(struct ak880xmci_host), &pdev->dev);
+	if (!mmc) {
+		ret = -ENOMEM;
+		dbg("");
+		goto err1;
+	}
+
+	mmc->ops	= &ak880xmci_ops;
+	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_31_32;
+	mmc->caps	= MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED;
+	mmc->max_blk_size = 512;
+	mmc->max_blk_count = 8;
+	mmc->max_req_size = 512*8;
+	mmc->f_min	= 300*1000; /* <400MHz */ 
+	mmc->f_max	= 20*1000*1000;
+
+	host		= mmc_priv(mmc);
+	host->mmc	= mmc;
+	host->irq	= IRQ_MMC_SD;
+	host->clk	= clk_get(&pdev->dev, "mci_clk");
+	if (IS_ERR(host->clk)) {
+		ret = -ENODEV;
+		goto err2;
+	}
+
+	host->baseaddr = ioremap(res->start, res->end - res->start + 1);
+	if (!host->baseaddr) {
+		ret = -ENOMEM;
+		goto err3;
+	}
+
+	platform_set_drvdata(pdev, mmc);
+
+	init_completion(&host->completion);
+
+	if (request_irq(host->irq, ak880xmci_irq, 0, DRIVER_NAME, host)) {
+		ret = -EBUSY;
+		goto err4;
+	}
+	
+	if (mmc_add_host(mmc)) {
+		goto err5;
+	}
+
+	return 0;
+
+err5:
+	free_irq(host->irq, host);
+err4:
+	iounmap(host->baseaddr);
+err3:
+	clk_put(host->clk);
+err2:
+	mmc_free_host(mmc);
+err1:
+	release_mem_region(res->start, res->end - res->start + 1);
+
+	return ret;
+}
+
+static int ak880xmci_remove(struct platform_device *pdev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(pdev);
+	struct ak880xmci_host *host = mmc_priv(mmc);
+	struct resource *res;
+
+	mmc_remove_host(mmc);
+	free_irq(host->irq, host);
+	platform_set_drvdata(pdev, NULL);
+	iounmap(host->baseaddr);
+	clk_put(host->clk);
+	mmc_free_host(mmc);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res->end - res->start + 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ak880xmci_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+        /*
+	 * if (mmc)
+	 *         ret = mmc_suspend_host(mmc, state);
+         */
+
+	return ret;
+}
+
+static int ak880xmci_resume(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+        /*
+	 * if (mmc)
+	 *         ret = mmc_resume_host(mmc);
+         */
+
+	return ret;
+}
+#else
+#define ak880xmci_suspend	NULL
+#define ak880xmci_resume	NULL
+#endif
+
+static struct platform_driver ak880xmci_driver = {
+	.probe		= ak880xmci_probe,
+	.remove		= ak880xmci_remove,
+	.suspend	= ak880xmci_suspend,
+	.resume		= ak880xmci_resume,
+	.driver		= {
+		.name	= "ak880x-mci",
+	},
+};
+
+static int __init ak880xmci_init(void)
+{
+	dbg("Build at %s %s", __DATE__, __TIME__);
+	return platform_driver_register(&ak880xmci_driver);
+}
+
+static void __exit ak880xmci_exit(void)
+{
+	platform_driver_unregister(&ak880xmci_driver);
+}
+
+module_init(ak880xmci_init);
+module_exit(ak880xmci_exit);
+
+MODULE_DESCRIPTION("ANYKA AK88 MMC/SD Interface Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/ak88-mmc/ak880x_mci.h b/drivers/mmc/host/ak88-mmc/ak880x_mci.h
new file mode 100644
index 00000000000..b612741b95a
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/ak880x_mci.h
@@ -0,0 +1,21 @@
+#ifndef __AK88_MCI_H
+#define __AK88_MCI_H
+
+#define MMC_CLK_CTRL     (0x04)
+#define MMC_CMD_ARG      (0x08)
+#define MMC_CMD_REG      (0x0C)
+#define MMC_CMD_RESP     (0x10)
+#define MMC_RESP1        (0x14)
+#define MMC_RESP2        (0x18)
+#define MMC_RESP3        (0x1C)
+#define MMC_RESP4        (0x20)
+#define MMC_DATA_TIMER   (0x24)
+#define MMC_DATA_LENGTH  (0x28)
+#define MMC_DATA_CONTROL (0x2C)
+#define MMC_DATA_COUNTER (0x30)
+#define MMC_STATUS       (0x34)
+#define MMC_INT_CTRL     (0x38)
+#define MMC_DMA_MODE     (0x3C)
+#define MMC_CPU_MODE     (0x40)
+
+#endif /* __AK88_MCI_H */
diff --git a/drivers/mmc/host/ak88-mmc/ak88_mci.c b/drivers/mmc/host/ak88-mmc/ak88_mci.c
new file mode 100644
index 00000000000..456417b0dc5
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/ak88_mci.c
@@ -0,0 +1,1195 @@
+/*
+ *  linux/drivers/mmc/host/ak88_mci.c - AK88 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/highmem.h>
+#include <linux/log2.h>
+#include <linux/mmc/host.h>
+#include <linux/clk.h>
+#include <linux/scatterlist.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/cacheflush.h>
+#include <asm/div64.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+
+#include <mach/devices_ak880x.h>
+#include <mach/gpio.h>
+#include "ak88_mci.h"
+
+#define DRIVER_NAME "ak88_mci"
+
+//#define AKMCI_INNERFIFO_PIO /* only 4bytes inner fifo */
+#define AKMCI_L2FIFO_PIO
+//#define AKMCI_L2FIFO_DMA
+
+#define DBG(host,fmt,args...)	\
+	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
+
+#define PK1(fmt...) //printk(fmt)
+#define PK(fmt...) //printk(fmt)
+
+#define SRDPIN_USE_MUTEX
+
+#ifdef SRDPIN_USE_MUTEX
+extern struct mutex nand_lock;
+#else
+extern struct semaphore nand_lock;
+#endif
+
+#if defined AKMCI_L2FIFO_PIO || defined AKMCI_L2FIFO_DMA
+static unsigned int fmax = (20*1000*1000);
+#elif defined AKMCI_INNERFIFO_PIO
+static unsigned int fmax = (4*1000*1000);
+#else
+#error "Please select one FIFO translation mode!"
+#endif
+
+static void ak88_mci_dump_regs(void *base)
+{
+	int i;
+
+	for (i = 0; i <= 0x40; i+=4) {
+		PK("%02x - %08x\n", i, ioread32(base+i));
+	}
+}
+
+static void dump_data(struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	u8 *sg_dat, *sg_end;
+	unsigned int blks, blkdat;
+
+	printk("%s\n", __func__);
+
+	sg = data->sg;
+	sg_dat = sg_virt(sg);
+	sg_end = sg_dat + sg->length;
+
+	for (blks = 0; blks < data->blocks; blks++) {
+		for (blkdat = 0; blkdat < data->blksz; blkdat++) {
+			printk("%02X ", *sg_dat);
+			if ((blkdat % 16) == 15)
+				printk("\n");
+			sg_dat++;
+			if (sg_dat >= sg_end) {
+				sg = sg_next(sg);
+				if (sg == NULL)
+					break;
+				sg_dat = sg_virt(sg);
+				sg_end = sg_dat + sg->length;
+			}
+		}
+		printk("\n");
+	}
+}
+
+#ifdef AKMCI_L2FIFO_PIO
+static void
+mci_xfer(struct ak88_mci_host *host)
+{
+	int i, sg_remain;
+	u32 *src, *dst;
+
+	PK("%s\n", __func__);
+
+	if (host->data->flags & MMC_DATA_WRITE) {
+		src = sg_virt(host->sg_ptr) + host->sg_off;
+		dst = host->l2fifo;
+	} else {
+		src = host->l2fifo;
+		dst = sg_virt(host->sg_ptr) + host->sg_off;
+	}
+
+	/* 
+	   limit: blksz(512), host_remain, sg
+
+	   xfer_len = min(host->size, host->data->blksz);
+	   if (xfer_len <= 0)
+	   return 0;
+
+	   sg_remain = ;
+	   while (sg_remain <= 0) {
+	   next_sg();
+	   sg_remain = ;
+	   }
+
+	   if (sg_remain >= xfer_len)
+	   memcpy(dst, src, xfer_len);
+
+	   do {
+	   sg_remain = host->sg_ptr->length - host->sg_off;
+	   x_len = xfer_len;
+	   if (sg_remain < x_len)
+	   x_len = sg_remain;
+	   memcpy(dst, src, x_len);
+	   xfer_len -= x_len;
+	   sg_remain -= x_len;
+	   }while (xfer_len > 0 || sg == NULL);
+
+	   while (host->sg_ptr && offset < xfer_len) {
+	   sg_remain = host->sg_ptr->length - host->sg_off;
+	   x_len = min(sg_remain, xfer_len);
+
+	   memcpy(dst, src, x_len);
+	   if (read)
+	   memcpy(sg_virt(host->sg_ptr) + host->sg_off, buffer + offset, x_len);
+	   else
+	   memcpy(buffer + offset, sg_virt(host->sg_ptr)+host->sg_off, x_len);
+
+	   offset += x_len;
+	   }
+
+	   xfer_len -= x_len;
+	   if (xfer_len <= 0) {
+	   sg_remain -= x_len;
+	   break; // done
+	   }
+
+	   host->sg_ptr = sg_next();
+	   host->sg_off = 0;
+	   if (host->sg_ptr == NULL)
+	   break;
+
+	   if (read) {
+	   dst = sg_virt(host->sg_ptr);
+	   src += x_len;
+	   } else {
+	   src = sg_virt(host->sg_ptr);
+	   dst += x_len;
+	   }
+	   }
+	   host->sg_off = sg->length
+	*/
+
+	sg_remain = host->sg_ptr->length - host->sg_off;
+	for (i = 0; i < host->data->blksz; i+=4) {
+		*dst = *src;
+		src++;
+		dst++;
+
+		host->data_xfered += 4;
+		host->size -= 4;
+
+		sg_remain -= 4;
+		if (sg_remain <= 0) {
+			host->sg_ptr = sg_next(host->sg_ptr);
+			if (host->sg_ptr == NULL)
+				return;
+			host->sg_off = 0;
+			if (host->data->flags & MMC_DATA_WRITE)
+				src = sg_virt(host->sg_ptr) + host->sg_off;
+			else
+				dst = sg_virt(host->sg_ptr) + host->sg_off;
+			sg_remain = host->sg_ptr->length - host->sg_off;
+		}
+	}
+	PK("\n");
+
+	host->sg_off = host->sg_ptr->length - sg_remain;
+}
+#endif
+
+static void ak88_mci_stop_data(struct ak88_mci_host *host)
+{
+	u32 masks;
+
+	PK1("%s\n", __func__);
+
+	writel(0, host->base + AK88MCIDMACTRL);
+	writel(0, host->base + AK88MCIDATACTRL);
+	masks = readl(host->base + AK88MCIMASK);
+	masks &= ~(MCI_DATAIRQMASKS|MCI_FIFOFULLMASK|MCI_FIFOEMPTYMASK);
+	writel(masks, host->base + AK88MCIMASK);
+	PK("DISABLE DATA IRQ\n");
+
+#ifdef MCI_USE_L2FIFO_DMA
+	if (host->data->flags & MMC_DATA_WRITE) {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+	} else {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+	}
+#endif
+
+	host->data = NULL;
+}
+
+
+static void
+ak88_mci_request_end(struct ak88_mci_host *host, struct mmc_request *mrq)
+{
+	PK1("%s\n", __func__);
+
+	writel(0, host->base + AK88MCICOMMAND);
+
+	BUG_ON(host->data);
+
+	host->mrq = NULL;
+	host->cmd = NULL;
+
+	if (mrq->data)
+		mrq->data->bytes_xfered = host->data_xfered;
+
+	/* release shared data pins */
+#ifdef SRDPIN_USE_MUTEX
+	mutex_unlock(&nand_lock);
+#else
+	up(&nand_lock);
+#endif
+
+	/*
+	 * Need to drop the host lock here; mmc_request_done may call
+	 * back into the driver...
+	 */
+	spin_unlock(&host->lock);
+	mmc_request_done(host->mmc, mrq);
+	spin_lock(&host->lock);
+}
+
+static void ak88_mci_start_data(struct ak88_mci_host *host, struct mmc_data *data)
+{
+	unsigned int datactrl, timeout, irqmask;
+	unsigned long long clks;
+	void __iomem *base;
+	u32 regval;
+
+	PK1("%s: blksz %04x blks %04x flags %08x\n",
+	       __func__, data->blksz, data->blocks, data->flags);
+
+	host->data = data;
+	host->size = data->blksz * data->blocks;
+	host->data_xfered = 0;
+
+	ak88_mci_init_sg(host, data);
+
+	if (data->timeout_clks) {
+		timeout = data->timeout_clks;
+	} else {
+		clks = (unsigned long long)data->timeout_ns * host->bus_clkrate;
+		do_div(clks, 1000000000UL);
+		timeout = (unsigned int)clks;
+	}
+	PK("timeout: %uns / %uclks\n", data->timeout_ns, data->timeout_clks);
+
+	base = host->base;
+	writel(timeout, base + AK88MCIDATATIMER);
+	writel(host->size, base + AK88MCIDATALENGTH);
+
+#ifdef AKMCI_L2FIFO_PIO
+
+	/* get l2 fifo */
+	regval = readl(host->l2base + L2FIFO_ASSIGN1);
+	regval = (regval & (~(7<<12))) | (MCI_L2FIFO_NUM << 12);
+	writel(regval, host->l2base + L2FIFO_ASSIGN1);
+
+	regval = readl(host->l2base + L2FIFO_CONF1);
+	regval |= (1 << (16 + MCI_L2FIFO_NUM)) | (1 << (24 + MCI_L2FIFO_NUM));
+	writel(regval, host->l2base + L2FIFO_CONF1);
+
+	PK1("L2ASSIGN: 0x%08x, L2CONF: 0x%08x\n",
+	       readl(host->l2base + L2FIFO_ASSIGN1),
+	       readl(host->l2base + L2FIFO_CONF1));
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK88MCIDMACTRL);
+
+#elif defined AKMCI_L2FIFO_DMA
+
+	/* get l2 fifo */
+	regval = readl(host->l2base + L2FIFO_ASSIGN1);
+	regval = (regval & (~(3<<12))) | (MCI_L2FIFO_NUM << 12);
+	writel(regval, host->l2base + L2FIFO_ASSIGN1);
+
+	regval = readl(host->l2base + L2FIFO_CONF1);
+	regval |= (1 << (0 + MCI_L2FIFO_NUM))
+		| (1 << (16 + MCI_L2FIFO_NUM))
+		| (1 << (24 + MCI_L2FIFO_NUM));
+	if (data->flags & MMC_DATA_WRITE)
+		regval |= (1 << (8 + MCI_L2FIFO_NUM));
+	else
+		regval &= ~(1 << (8 + MCI_L2FIFO_NUM));
+	writel(regval, host->l2base + L2FIFO_CONF1);
+
+	/* set dma addr */
+	if (data->flags & MMC_DATA_WRITE)
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_TO_DEVICE);
+	else
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_FROM_DEVICE);
+	writel(sg_dma_address(data->sg), host->l2base + MCI_L2FIFO_NUM);
+
+	/* set dma size */
+	if (host->size > L2DMA_MAX_SIZE)
+		dma_size = L2DMA_MAX_SIZE;
+	dma_times = dma_size/64;
+	writel(dma_times, host->l2base + 0x40 + MCI_L2FIFO_NUM);
+
+	if (host->size > L2DMA_MAX_SIZE) {
+		/* need to handle dma int */
+		regval = readl(host->l2base + L2FIFO_INTEN);
+		regval |= (1 << (9 + MCI_L2FIFO_NUM));
+		writel(regval, host->l2base + L2FIFO_INTEN);
+
+		request_irq(AK88_L2MEM_IRQ(9+MCI_L2FIFO_NUM), ak88_mcil2_irq,
+			    IRQF_DISABLED, DRIVER_NAME "(dma)", host);
+	}
+
+	/* when to start dma? */
+	regval = readl(host->l2base + L2FIFO_DMACONF);
+	regval |= (1 | (1 << (24 + MCI_L2FIFO_NUM)));
+	writel(regval, host->l2base + L2FIFO_DMACONF);
+
+	if (dma_size % 64) {
+		/* fraction DMA */
+		(8 * MCI_L2FIFO_NUM)
+	}
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_EN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK88MCIDMACTRL);
+#endif
+
+	datactrl = MCI_DPSM_ENABLE;
+
+	switch (host->bus_width) {
+	case MMC_BUS_WIDTH_8:
+		datactrl |= MCI_DPSM_BUSMODE(2);
+		break;
+	case MMC_BUS_WIDTH_4:
+		datactrl |= MCI_DPSM_BUSMODE(1);
+		break;
+	case MMC_BUS_WIDTH_1:
+	default:
+		datactrl |= MCI_DPSM_BUSMODE(0);
+		break;
+	}
+
+	if (data->flags & MMC_DATA_STREAM) {
+		DBG(host, "%s", "STREAM Data\n");
+		datactrl |= MCI_DPSM_STREAM;
+	} else {
+		DBG(host, "BLOCK Data: %u x %u\n", data->blksz, data->blocks);
+		datactrl |= MCI_DPSM_BLOCKSIZE(data->blksz);
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		datactrl |= MCI_DPSM_DIRECTION;
+	}
+
+	writel(readl(base + AK88MCIMASK) | MCI_DATAIRQMASKS, base + AK88MCIMASK);
+	writel(datactrl, base + AK88MCIDATACTRL);
+
+	PK("ENABLE DATA IRQ, datactrl: 0x%08x, timeout: 0x%08x, len: %u\n",
+	       datactrl, readl(base+AK88MCIDATATIMER), host->size);
+
+#ifdef AKMCI_L2FIFO_PIO
+	if (data->flags & MMC_DATA_WRITE)
+		mci_xfer(host);
+#endif
+
+#ifdef AKMCI_INNERFIFO_PIO
+	irqmask = readl(base + AK88MCIMASK);
+	if (data->flags & MMC_DATA_READ) {
+		if (host->size > MCI_FIFOSIZE)
+			irqmask |= MCI_FIFOFULLMASK;
+		else
+			;	/* wait for DATAEND int */
+	} else {
+		irqmask |= MCI_FIFOEMPTYMASK;
+	}
+
+	writel(irqmask, base + AK88MCIMASK);
+#endif
+}
+
+static void
+ak88_mci_start_command(struct ak88_mci_host *host, struct mmc_command *cmd)
+{
+	unsigned int c;
+	void __iomem *base = host->base;
+
+	PK1("%s: op %02x arg %08x flags %08x\n",
+	       __func__, cmd->opcode, cmd->arg, cmd->flags);
+
+	if (readl(base + AK88MCICOMMAND) & MCI_CPSM_ENABLE) {
+		writel(0, base + AK88MCICOMMAND);
+		udelay(1);
+	}
+
+	c = MCI_CPSM_CMD(cmd->opcode) | MCI_CPSM_ENABLE;
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		c |= MCI_CPSM_RESPONSE;
+		if (cmd->flags & MMC_RSP_136)
+			c |= MCI_CPSM_LONGRSP;
+	}
+
+	if (cmd->data)
+		c |= MCI_CPSM_WITHDATA;
+
+	host->cmd = cmd;
+
+	writel(cmd->arg, base + AK88MCIARGUMENT);
+	writel(readl(base + AK88MCIMASK) | MCI_CMDIRQMASKS, base + AK88MCIMASK);
+	PK("ENABLE CMD IRQ\n");
+	PK("irqmask: 0x%08x\n", readl(base+AK88MCIMASK));
+	writel(c, base + AK88MCICOMMAND);
+#if 0
+	PK("%s: cmd:0x%08x; irq:0x%08x\n",
+	       __func__, c, readl(base+AK88MCIMASK));
+	ak88_mci_dump_regs(host->base);
+#endif
+}
+
+
+#ifdef AKMCI_INNERFIFO_PIO
+static void
+ak88_mci_pio_irq(struct ak88_mci_host *host, unsigned int status)
+{
+	u32 *p;
+
+	if (host->sg_ptr == NULL) {
+		printk("%s ERROR\n", __func__);
+		return;
+	}
+
+	p = sg_virt(host->sg_ptr) + host->sg_off;
+
+	if ((status & MCI_FIFOFULL) && (status & MCI_RXACTIVE)) {
+		*p = readl(host->base + AK88MCIFIFO);
+		PK("read: 0x%08x\n", *p);
+	} else if ((status & MCI_FIFOEMPTY) && (status & MCI_TXACTIVE)) {
+		writel(*p, host->base + AK88MCIFIFO);
+		PK("write: 0x%08x\n", *p);
+	} else {
+		return;
+	}
+
+	host->data_xfered += 4;
+	host->size -= 4;
+
+	host->sg_off += 4;
+	if (host->sg_off >= host->sg_ptr->length) {
+		ak88_mci_next_sg(host);
+	}
+}
+#endif
+
+static void
+ak88_mci_data_irq(struct ak88_mci_host *host, struct mmc_data *data,
+		  unsigned int status)
+{
+	if (status & MCI_DATABLOCKEND) {
+		PK("BLOCKEND\n");
+#ifdef AKMCI_L2FIFO_PIO
+		if (host->size > 0)
+			mci_xfer(host);
+#endif
+	}
+	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBIT_ERR)) {
+		PK1("DATA ERROR: 0x%08x\n", status);
+
+		if (status & MCI_DATACRCFAIL || status & MCI_STARTBIT_ERR)
+			data->error = -EILSEQ;
+		else if (status & MCI_DATATIMEOUT)
+			data->error = -ETIMEDOUT;
+		status |= MCI_DATAEND;
+		/*
+		 * We hit an error condition.  Ensure that any data
+		 * partially written to a page is properly coherent.
+		 */
+		if (host->sg_len && data->flags & MMC_DATA_READ)
+			flush_dcache_page(sg_page(host->sg_ptr));
+	}
+	if (status & MCI_DATAEND) {
+		ak88_mci_stop_data(host);
+
+		//dump_data(data);
+
+		if (!data->stop) {
+			ak88_mci_request_end(host, data->mrq);
+		} else {
+			ak88_mci_start_command(host, data->stop);
+		}
+	}
+}
+
+static void
+ak88_mci_cmd_irq(struct ak88_mci_host *host, struct mmc_command *cmd,
+		 unsigned int status)
+{
+	void __iomem *base = host->base;
+
+	PK("+%s\n", __func__);
+	host->cmd = NULL;
+
+	cmd->resp[0] = readl(base + AK88MCIRESPONSE0);
+	cmd->resp[1] = readl(base + AK88MCIRESPONSE1);
+	cmd->resp[2] = readl(base + AK88MCIRESPONSE2);
+	cmd->resp[3] = readl(base + AK88MCIRESPONSE3);
+
+	if (status & MCI_RESPTIMEOUT) {
+		cmd->error = -ETIMEDOUT;
+	} else if (status & MCI_RESPCRCFAIL && cmd->flags & MMC_RSP_CRC) {
+		cmd->error = -EILSEQ;
+	}
+
+	writel(readl(base + AK88MCIMASK) & ~MCI_CMDIRQMASKS, base + AK88MCIMASK);
+	PK("DISABLE CMD IRQ\n");
+
+	if (!cmd->data || cmd->error) {
+		if (host->data)
+			ak88_mci_stop_data(host);
+		ak88_mci_request_end(host, cmd->mrq);
+	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
+		ak88_mci_start_data(host, cmd->data);
+	}
+	PK("-%s\n", __func__);
+}
+
+/*
+ * Handle completion of command and data transfers.
+ */
+static irqreturn_t ak88_mci_irq(int irq, void *dev_id)
+{
+	struct ak88_mci_host *host = dev_id;
+	u32 status;
+	int ret = 0;
+
+	PK("+%s ", __func__);
+
+	spin_lock(&host->lock);
+
+	do {
+		struct mmc_command *cmd;
+		struct mmc_data *data;
+
+		status = readl(host->base + AK88MCISTATUS);
+
+		PK("irq0 %08x\n", status);
+/*
+		PK("irq: a: 0x%08x, b: 0x%08x\n", status,
+		       readl(host->base + AK88MCISTATUS));
+*/
+
+#ifdef AKMCI_INNERFIFO_PIO
+		if (host->data)
+			ak88_mci_pio_irq(host, status);
+#endif
+
+		cmd = host->cmd;
+		if (status & (MCI_RESPCRCFAIL|MCI_RESPTIMEOUT|MCI_CMDSENT|MCI_RESPEND)
+		    && cmd)
+			ak88_mci_cmd_irq(host, cmd, status);
+
+		data = host->data;
+		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_DATAEND|MCI_DATABLOCKEND|MCI_STARTBIT_ERR)
+		    && data)
+			ak88_mci_data_irq(host, data, status);
+
+#ifdef SDIO
+		if (status & MCI_SDIOINT) {
+			mmc_signal_sdio_irq(host->mmc);
+		}
+#endif
+
+		ret = 1;
+	} while (0);
+
+	spin_unlock(&host->lock);
+
+	PK("-%s, irqmask: 0x%08x\n", __func__, readl(host->base + AK88MCIMASK));
+
+	return IRQ_RETVAL(ret);
+}
+
+static void ak88_mci_detect_change(unsigned long data)
+{
+	struct ak88_mci_host *host = (struct ak88_mci_host *)data;
+
+	PK("%s\n", __func__);
+
+	mmc_detect_change(host->mmc, 0);
+
+	if (host->irq_cd_type == IRQ_TYPE_LEVEL_LOW) {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_LOW;
+	}
+	set_irq_type(host->irq_cd, host->irq_cd_type);
+	enable_irq(host->irq_cd);
+}
+
+static irqreturn_t ak88_mci_card_detect_irq(int irq, void *dev)
+{
+	struct ak88_mci_host *host = dev;
+
+	PK("%s\n", __func__);
+
+	disable_irq_nosync(irq);
+	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(400));
+
+	return IRQ_HANDLED;
+}
+
+static void ak88_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct ak88_mci_host *host = mmc_priv(mmc);
+	unsigned long flags;
+
+	WARN_ON(host->mrq != NULL);
+
+	PK1("%s: CMD%i\n", __func__, mrq->cmd->opcode);
+
+	if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
+		printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
+		       mmc_hostname(mmc), mrq->data->blksz);
+		mrq->cmd->error = -EINVAL;
+		mmc_request_done(mmc, mrq);
+		return;
+	}
+
+	spin_lock_irqsave(&host->lock, flags);
+
+	host->mrq = mrq;
+
+	/* grab shared pins */
+	PK("set shared pins\n");
+#if defined CONFIG_BOARD_AK8801EPC
+
+	/* soc pin mux bug */
+#ifdef SRDPIN_USE_MUTEX
+	mutex_lock_interruptible(&nand_lock);
+#else
+	down_interruptible(&nand_lock);
+#endif
+/*	ak880x_gpio_pullup(AK88_GPIO_39, AK88_GPIO_PUPD_DISABLE);
+	ak880x_gpio_pullup(AK88_GPIO_40, AK88_GPIO_PUPD_DISABLE);*/
+	AK88_GPIO_MDAT2(AK88_SHARE_FUNC);
+	AK88_MCI_ENABLE();
+
+#elif defined CONFIG_BOARD_AK8802EBOOK
+
+#ifdef SRDPIN_USE_MUTEX
+	mutex_lock_interruptible(&nand_lock);
+#else
+	down_interruptible(&nand_lock);
+#endif
+	AK88_GPIO_NFC_DATA4_7(AK88_SHARE_FUNC);
+	AK88_GPIO_NFC_DATA1_3(AK88_SHARE_FUNC);
+	AK88_GPIO_NFC_DATA0(AK88_SHARE_FUNC);
+	AK88_SD_ENABLE();
+
+#endif
+
+	if (mrq->data && (mrq->data->flags & MMC_DATA_READ))
+		ak88_mci_start_data(host, mrq->data);
+
+	ak88_mci_start_command(host, mrq->cmd);
+
+	spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void ak88_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct ak88_mci_host *host = mmc_priv(mmc);
+	unsigned int regval;
+	int div;
+
+	printk("%s ", __func__);
+
+	/* ak88 (and SD spec) don't support MMC_BUSMODE_OPENDRAIN */
+	host->bus_mode = ios->bus_mode;
+	host->bus_width = ios->bus_width;
+	printk("%ubits(%u); ", (unsigned)1 >> (host->bus_width), host->bus_width);
+
+	/* we can't control external power supply unit */
+	switch (ios->power_mode) {
+	case MMC_POWER_UP:
+		PK("MMC_POWER_UP; ");
+#if 0
+		regval = readl(host->base + AK88MCICLOCK);
+		regval |= MCI_ENABLE;
+		writel(regval, host->base + AK88MCICLOCK);
+#endif
+		break;
+	case MMC_POWER_ON:
+		PK("MMC_POWER_ON; ");
+		break;
+	case MMC_POWER_OFF:
+		PK("MMC_POWER_OFF; ");
+#if 0
+		regval = readl(host->base + AK88MCICLOCK);
+		regval &= ~MCI_ENABLE;
+		writel(regval, host->base + AK88MCICLOCK);
+#endif
+		break;
+	}
+	
+	if (ios->clock != host->bus_clkrate) {
+		regval = readl(host->base + AK88MCICLOCK);
+		if (ios->clock == 0) {
+			regval &= ~MCI_CLK_ENABLE;
+			host->bus_clkrate = 0;
+		} else {
+			regval |= MCI_CLK_ENABLE;
+			regval &= ~0xffff; /* clear clk div */
+			div = (host->asic_clkrate + ios->clock - 1) / ios->clock - 2;
+			printk("clk_div: %d\n", div);
+			if (div < 256) {
+				regval |= MMC_CLK_DIVL(div);
+			} else {
+				regval |= MMC_CLK_DIVL(255) | MMC_CLK_DIVH(div-255);
+			}
+			host->bus_clkrate = host->asic_clkrate / (div + 2);
+		}
+		writel(regval, host->base + AK88MCICLOCK);
+	}
+
+	/* no matter high-speed mode or not, ak88 mci use the same timing */
+
+	printk("ios->clock(%dkhz), host->bus_clkrate(%lukhz), host->asic_clkrate(%lumhz), MMC_CLK_CTRL(0x%08x)\n",
+	       ios->clock/1000, host->bus_clkrate/1000, host->asic_clkrate/1000000, readl(host->base + AK88MCICLOCK));
+}
+
+static int ak88_mci_get_ro(struct mmc_host *mmc)
+{
+	struct ak88_mci_host *host = mmc_priv(mmc);
+
+	if (host->gpio_wp == -ENOSYS)
+		return -ENOSYS;
+
+	printk("%s: %i\n", __func__, ak880x_gpio_getpin(host->gpio_wp));
+	return (ak880x_gpio_getpin(host->gpio_wp) != 0);
+}
+
+#if 0
+static int ak88_mci_get_cd(struct mmc_host *mmc)
+{
+	struct ak88_mci_host *host = mmc_priv(mmc);
+	unsigned int status;
+
+	if (host->gpio_cd == -ENOSYS)
+		status = host->plat->status(mmc_dev(host->mmc));
+	else
+		status = gpio_get_value(host->gpio_cd);
+
+	return !status;
+}
+#endif
+
+static const struct mmc_host_ops ak88_mci_ops = {
+	.request	= ak88_mci_request,
+	.set_ios	= ak88_mci_set_ios,
+	.get_ro		= ak88_mci_get_ro,
+#if 0
+	.get_cd		= ak88_mci_get_cd,
+#endif
+#ifdef SDIO
+	.enable_sdio_irq = ak88_mci_enable_sdio_irq,
+#endif
+};
+
+#if 0
+static void ak88_mci_check_status(unsigned long data)
+{
+	struct ak88_mci_host *host = (struct ak88_mci_host *)data;
+	unsigned int status = ak88_mci_get_cd(host->mmc);
+
+	if (status ^ host->oldstat)
+		mmc_detect_change(host->mmc, 0);
+
+	host->oldstat = status;
+	mod_timer(&host->timer, jiffies + HZ);
+}
+#endif
+
+static int __devinit ak88_mci_probe(struct platform_device *pdev)
+{
+	struct ak88_mci_platform_data *plat = pdev->dev.platform_data;
+	struct ak88_mci_host *host;
+	struct mmc_host *mmc;
+	struct resource *res;
+	int irq;
+	int ret;
+
+	/* must have platform data */
+	if (!plat) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	PK("%s\n", __func__);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+
+#if 0				/* can do in akmci_request() */
+	/* set shared data pins */
+	PK("set shared pins\n");
+#if defined CONFIG_BOARD_AK8801EPC
+	ak880x_gpio_pullup(AK88_GPIO_39, AK88_GPIO_PUPD_DISABLE);
+	ak880x_gpio_pullup(AK88_GPIO_40, AK88_GPIO_PUPD_DISABLE);
+	AK88_GPIO_MDAT2(AK88_SHARE_FUNC);
+	AK88_MCI_ENABLE();
+#elif defined CONFIG_BOARD_AK8802EBOOK
+	AK88_GPIO_NFC_DATA4_7(AK88_SHARE_FUNC);
+	AK88_GPIO_NFC_DATA1_3(AK88_SHARE_FUNC);
+	AK88_GPIO_NFC_DATA0(AK88_SHARE_FUNC);
+	AK88_SD_ENABLE();
+#endif
+#endif
+
+	PK("res: %x, %u", res->start, resource_size(res));
+	res = request_mem_region(res->start, resource_size(res), DRIVER_NAME);
+	if (!res) {
+		ret = -EBUSY;
+		goto out;
+	}
+	PK("res: %x, %u", res->start, resource_size(res));
+
+	mmc = mmc_alloc_host(sizeof(struct ak88_mci_host), &pdev->dev);
+	if (!mmc) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	host = mmc_priv(mmc);
+	host->mmc = mmc;
+
+	host->gpio_wp = -ENOSYS;
+	host->gpio_cd = -ENOSYS;
+
+	host->clk = clk_get(&pdev->dev, "mci_clk");
+	if (IS_ERR(host->clk)) {
+		ret = PTR_ERR(host->clk);
+		host->clk = NULL;
+		goto host_free;
+	}
+
+	ret = clk_enable(host->clk);
+	if (ret)
+		goto clk_free;
+
+	host->plat = plat;
+	host->asic_clkrate = clk_get_rate(host->clk);
+	PK("asic_clkrate: %uhz", host->asic_clkrate);
+
+	host->base = ioremap(res->start, resource_size(res));
+	if (!host->base) {
+		ret = -ENOMEM;
+		goto clk_disable;
+	}
+
+	mmc->ops = &ak88_mci_ops;
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->caps = MMC_CAP_4_BIT_DATA;
+#if 0
+	mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+#endif
+#ifdef SDIO
+	mmc->caps |= MMC_CAP_SDIO_IRQ;
+#endif
+//	mmc->caps |= MMC_CAP_NEEDS_POLL;
+	mmc->f_min = host->asic_clkrate / (255+1 + 255+1);
+	mmc->f_max = host->asic_clkrate / (0+1 + 0+1);
+	mmc->f_max = mmc->f_max < fmax ? mmc->f_max : fmax;
+
+	/*
+	 * We can do SGIO
+	 */
+	mmc->max_hw_segs = 16;
+	mmc->max_phys_segs = NR_SG;
+
+	/*
+	 * Since we only have a 16-bit data length register, we must
+	 * ensure that we don't exceed 2^16-1 bytes in a single request.
+	 */
+	mmc->max_req_size = 65535;
+
+	/*
+	 * Set the maximum segment size.  Since we aren't doing DMA
+	 * (yet) we are only limited by the data length register.
+	 */
+	mmc->max_seg_size = mmc->max_req_size;
+
+#if 0
+	/*
+	 * Block size can be up to 2048 bytes, but must be a power of two.
+	 */
+	mmc->max_blk_size = 2048;
+#else
+	/* as l2 fifo limit to 512 bytes */
+	mmc->max_blk_size = 512;
+#endif
+
+	/*
+	 * No limit on the number of blocks transferred.
+	 */
+	mmc->max_blk_count = mmc->max_req_size;
+
+	spin_lock_init(&host->lock);
+
+	writel(0, host->base + AK88MCICLOCK);
+	udelay(1000);
+
+	writel(MCI_ENABLE|MCI_FAIL_TRIGGER, host->base + AK88MCICLOCK);
+
+	writel(0, host->base + AK88MCIMASK);
+	PK("%s: MCICLOCK: 0x%08x\n", __func__, readl(host->base + AK88MCICLOCK));
+
+	PK("request irq %i\n", irq);
+	ret = request_irq(irq, ak88_mci_irq, IRQF_DISABLED, DRIVER_NAME " (cmd)", host);
+	if (ret)
+		goto unmap;
+	host->irq_mci = irq;
+
+#if 0
+	if (gpio_is_valid(plat->gpio_cd)) {
+		ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
+		if (ret == 0)
+			ret = gpio_direction_input(plat->gpio_cd);
+		if (ret == 0)
+			host->gpio_cd = plat->gpio_cd;
+		else if (ret != -ENOSYS)
+			goto err_gpio_cd;
+	}
+	if (gpio_is_valid(plat->gpio_wp)) {
+		ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
+		if (ret == 0)
+			ret = gpio_direction_input(plat->gpio_wp);
+		if (ret == 0)
+			host->gpio_wp = plat->gpio_wp;
+		else if (ret != -ENOSYS)
+			goto err_gpio_wp;
+	}
+
+	if (gpio_is_valid(plat->gpio_cd)) {
+		irq = ak880x_gpio_to_irq(host->gpio_cd);
+		PK("request card detect irq: %u - %u\n", AK88_DGPIO_12, irq);
+		ret = request_irq(irq, ak88_mci_card_detect_irq,
+				  IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
+				  DRIVER_NAME " cd", host);
+		if (ret)
+			goto irq_free;
+		host->irq_cd = irq;
+	}
+#else
+	host->gpio_cd = plat->gpio_cd;
+	host->gpio_wp = plat->gpio_wp;
+	ak880x_gpio_cfgpin(host->gpio_cd, AK88_GPIO_IN_0);
+	ak880x_gpio_pullup(host->gpio_wp, AK88_GPIO_PUPD_DISABLE);
+	ak880x_gpio_cfgpin(host->gpio_wp, AK88_GPIO_IN_0);
+
+	setup_timer(&host->detect_timer, ak88_mci_detect_change,
+		    (unsigned long)host);
+	irq = ak880x_gpio_to_irq(host->gpio_cd);
+	PK("request card detect irq: %u - %u\n", AK88_DGPIO_12, irq);
+	if (ak880x_gpio_getpin(host->gpio_cd))
+		set_irq_type (irq, IRQ_TYPE_LEVEL_LOW);
+	else
+		set_irq_type (irq, IRQ_TYPE_LEVEL_HIGH);
+	ret = request_irq(irq, ak88_mci_card_detect_irq,
+			  IRQF_DISABLED,
+			  DRIVER_NAME " cd", host);
+	if (ret)
+		goto irq_free;
+	host->irq_cd = irq;
+	host->irq_cd_type = IRQ_TYPE_LEVEL_LOW;
+#endif
+
+	platform_set_drvdata(pdev, mmc);
+
+	mmc_add_host(mmc);
+
+	PK(KERN_INFO "%s: AK88MCI at 0x%016llx irq %d\n",
+		mmc_hostname(mmc), (unsigned long long)res->start,
+		host->irq_mci);
+
+	/* ak88_mci_dump_regs(host->base); */
+	PK("srdpin conf1: 0x%08x, srdpin conf2: 0x%08x\n",
+	   readl(AK88_SHAREPIN_CON1), readl(AK88_SHAREPIN_CON2));
+
+#ifdef AKMCI_L2FIFO_PIO
+	res = request_mem_region(L2BASE, SZ_256, DRIVER_NAME);
+	if (!res) {
+		ret = -EBUSY;
+		goto irq_free;
+	}
+	host->l2base = ioremap(res->start, resource_size(res));
+	if (!host->l2base) {
+		ret = -ENOMEM;
+		goto irq_free;
+	}
+
+	res = request_mem_region(L2ADDR(MCI_L2FIFO_NUM), MCI_L2FIFO_SIZE, DRIVER_NAME);
+	if (!res) {
+		ret = -EBUSY;
+		goto irq_free;
+	}
+	host->l2fifo = ioremap(res->start, resource_size(res));
+	if (!host->l2fifo) {
+		ret = -ENOMEM;
+		goto irq_free;
+	}
+#endif
+
+	return 0;
+
+ irq_free:
+	PK("ERR irq_free\n");
+	free_irq(host->irq_mci, host);
+ unmap:
+	PK("ERR unmap\n");
+#if 0
+	if (host->gpio_wp != -ENOSYS)
+		gpio_free(host->gpio_wp);
+#endif
+ err_gpio_wp:
+	PK("ERR gpio_wp\n");
+#if 0
+	if (host->gpio_cd != -ENOSYS)
+		gpio_free(host->gpio_cd);
+#endif
+ err_gpio_cd:
+	PK("ERR gpio_cd\n");
+	iounmap(host->base);
+ clk_disable:
+	PK("ERR clk_disable\n");
+	clk_disable(host->clk);
+ clk_free:
+	PK("ERR clk_free\n");
+	clk_put(host->clk);
+ host_free:
+	PK("ERR host_free\n");
+	mmc_free_host(mmc);
+ out:
+	PK("ERR out\n");
+	return ret;
+}
+
+static int __devexit ak88_mci_remove(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+
+	platform_set_drvdata(dev, NULL);
+
+	if (mmc) {
+		struct ak88_mci_host *host = mmc_priv(mmc);
+
+#if 0
+		del_timer_sync(&host->timer);
+#endif
+
+		mmc_remove_host(mmc);
+
+		writel(0, host->base + AK88MCIMASK);
+
+		writel(0, host->base + AK88MCICOMMAND);
+		writel(0, host->base + AK88MCIDATACTRL);
+
+#if 0
+		if (gpio_is_valid(host->gpio_cd))
+			free_irq(host->irq_cd, host);
+		free_irq(host->irq_mci, host);
+
+		if (host->gpio_wp != -ENOSYS)
+			gpio_free(host->gpio_wp);
+		if (host->gpio_cd != -ENOSYS)
+			gpio_free(host->gpio_cd);
+#else
+		free_irq(host->irq_cd, host);
+		free_irq(host->irq_mci, host);
+#endif
+
+		iounmap(host->base);
+		clk_disable(host->clk);
+		clk_put(host->clk);
+
+		mmc_free_host(mmc);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ak88_mci_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak88_mci_host *host = mmc_priv(mmc);
+
+		ret = mmc_suspend_host(mmc, state);
+		if (ret == 0)
+			writel(0, host->base + AK88MCIMASK0);
+	}
+
+	return ret;
+}
+
+static int ak88_mci_resume(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak88_mci_host *host = mmc_priv(mmc);
+
+		writel(MCI_IRQENABLE, host->base + AK88MCIMASK0);
+
+		ret = mmc_resume_host(mmc);
+	}
+
+	return ret;
+}
+#else
+#define ak88_mci_suspend	NULL
+#define ak88_mci_resume	NULL
+#endif
+
+static struct platform_driver ak88_mci_driver = {
+	.driver		= {
+		.name	= DRIVER_NAME,
+	},
+	.probe		= ak88_mci_probe,
+	.remove		= __devexit_p(ak88_mci_remove),
+	.suspend	= ak88_mci_suspend,
+	.resume		= ak88_mci_resume,
+};
+
+static int __init ak88_mci_init(void)
+{
+	PK("%s\n", __func__);
+	return platform_driver_register(&ak88_mci_driver);
+}
+
+static void __exit ak88_mci_exit(void)
+{
+	platform_driver_unregister(&ak88_mci_driver);
+}
+
+module_init(ak88_mci_init);
+module_exit(ak88_mci_exit);
+
+MODULE_DESCRIPTION("Anyka AK88 MMC/SD/SDIO Interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/ak88-mmc/ak88_mci.h b/drivers/mmc/host/ak88-mmc/ak88_mci.h
new file mode 100644
index 00000000000..37f4448eddc
--- /dev/null
+++ b/drivers/mmc/host/ak88-mmc/ak88_mci.h
@@ -0,0 +1,209 @@
+/*
+ *  linux/drivers/mmc/host/ak88_mci.h - AK88 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define AK88MCICLOCK		0x004
+#define MMC_CLK_DIVL(x)		((x) & 0xff)
+#define MMC_CLK_DIVH(x)		(((x) & 0xff) << 8)
+#define MCI_CLK_ENABLE		(1 << 16)
+#define MCI_CLK_PWRSAVE		(1 << 17)
+#define MCI_FAIL_TRIGGER	(1 << 19)
+#define MCI_ENABLE		(1 << 20)
+
+#define AK88MCIARGUMENT		0x008
+#define AK88MCICOMMAND		0x00c
+#define MCI_CPSM_ENABLE		(1 << 0)
+#define MCI_CPSM_CMD(x)		(((x) & 0x3f) << 1)
+#define MCI_CPSM_RESPONSE	(1 << 7)
+#define MCI_CPSM_LONGRSP	(1 << 8)
+#define MCI_CPSM_PENDING	(1 << 9)
+#define MCI_CPSM_RSPCRC_NOCHK	(1 << 10)
+#define MCI_CPSM_WITHDATA	(1 << 11)
+
+#define AK88MCIRESPCMD		0x010
+#define AK88MCIRESPONSE0	0x014
+#define AK88MCIRESPONSE1	0x018
+#define AK88MCIRESPONSE2	0x01c
+#define AK88MCIRESPONSE3	0x020
+#define AK88MCIDATATIMER	0x024
+#define AK88MCIDATALENGTH	0x028
+#define AK88MCIDATACTRL		0x02c
+#define MCI_DPSM_ENABLE		(1 << 0)
+#define MCI_DPSM_DIRECTION	(1 << 1)
+#define MCI_DPSM_STREAM		(1 << 2)
+#define MCI_DPSM_BUSMODE(x)	(((x) & 0x3) << 3)
+#define MCI_DPSM_BLOCKSIZE(x)	(((x) & 0xfff) << 16)
+
+#define AK88MCIDATACNT		0x030
+#define AK88MCISTATUS		0x034
+#define MCI_RESPCRCFAIL		(1 << 0)
+#define MCI_DATACRCFAIL		(1 << 1)
+#define MCI_RESPTIMEOUT		(1 << 2)
+#define MCI_DATATIMEOUT		(1 << 3)
+#define MCI_RESPEND		(1 << 4)
+#define MCI_CMDSENT		(1 << 5)
+#define MCI_DATAEND		(1 << 6)
+#define MCI_DATABLOCKEND	(1 << 7)
+#define MCI_STARTBIT_ERR	(1 << 8)
+#define MCI_CMDACTIVE		(1 << 9)
+#define MCI_TXACTIVE		(1 << 10)
+#define MCI_RXACTIVE		(1 << 11)
+#define MCI_FIFOFULL		(1 << 12)
+#define MCI_FIFOEMPTY		(1 << 13)
+#define MCI_FIFOHALFFULL	(1 << 14)
+#define MCI_FIFOHALFEMPTY	(1 << 15)
+#define MCI_DATATRANS_FINISH	(1 << 16)
+#define MCI_SDIOINT		(1 << 17)
+
+#define AK88MCIMASK		0x038
+#define MCI_RESPCRCFAILMASK	(1 << 0)
+#define MCI_DATACRCFAILMASK	(1 << 1)
+#define MCI_RESPTIMEOUTMASK	(1 << 2)
+#define MCI_DATATIMEOUTMASK	(1 << 3)
+#define MCI_RESPENDMASK		(1 << 4)
+#define MCI_CMDSENTMASK		(1 << 5)
+#define MCI_DATAENDMASK		(1 << 6)
+#define MCI_DATABLOCKENDMASK	(1 << 7)
+#define MCI_STARTBIT_ERRMASK	(1 << 8)
+#define MCI_CMDACTIVEMASK	(1 << 9)
+#define MCI_TXACTIVEMASK	(1 << 10)
+#define MCI_RXACTIVEMASK	(1 << 11)
+#define MCI_FIFOFULLMASK	(1 << 12)
+#define MCI_FIFOEMPTYMASK	(1 << 13)
+#define MCI_FIFOHALFFULLMASK	(1 << 14)
+#define MCI_FIFOHALFEMPTYMASK	(1 << 15)
+#define MCI_DATATRANS_FINISHMASK	(1 << 16)
+#define MCI_SDIOINTMASK		(1 << 17)
+
+#define AK88MCIDMACTRL		0x03c
+#define MCI_DMA_BUFEN		(1 << 0)
+#define MCI_DMA_ADDR(x)		(((x) & 0x7fff) << 1)
+#define MCI_DMA_EN		(1 << 16)
+#define MCI_DMA_SIZE(x)		(((x) & 0x7fff) << 17)
+
+#define AK88MCIFIFO		0x040
+
+#define MCI_CMDIRQMASKS \
+	(MCI_CMDSENTMASK|MCI_RESPENDMASK|		\
+	 MCI_RESPCRCFAILMASK|MCI_RESPTIMEOUTMASK)
+
+#define MCI_DATAIRQMASKS \
+	(MCI_DATAEND|MCI_DATABLOCKENDMASK|		\
+	 MCI_DATACRCFAILMASK|MCI_DATATIMEOUTMASK|	\
+	 MCI_STARTBIT_ERRMASK)
+
+/*
+ * The size of the FIFO in bytes.
+ */
+#define MCI_FIFOSIZE	4
+#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
+
+#define NR_SG		16
+
+#define L2BASE		0x2002c000
+#define L2FIFO_DMACONF	0x80
+#define L2FIFO_CONF1	0x88
+#define L2FIFO_ASSIGN1	0x90
+#define L2FIFO_INTEN	0x9c
+
+#define L2FIFOBASE	0x48000000
+#define L2ADDR(n)	(L2FIFOBASE + 512 * (n))
+#define MCI_L2FIFO_NUM	2	/* #6 l2fifo */
+#define MCI_L2FIFO_SIZE	512
+
+#define L2DMA_MAX_SIZE	(64*255)
+
+struct clk;
+
+struct ak88_mci_host {
+	void __iomem		*base;
+	struct mmc_request	*mrq;
+	struct mmc_command	*cmd;
+	struct mmc_data		*data;
+	struct mmc_host		*mmc;
+	struct clk		*clk;
+	int			gpio_cd;
+	int			gpio_wp;
+	int			irq_mci;
+	int			irq_cd;
+	int			irq_cd_type;
+
+	unsigned int		data_xfered;
+
+	spinlock_t		lock;
+
+#if 0
+	unsigned int		mclk;
+	unsigned int		cclk;
+	u32			pwr;
+#else
+	unsigned char		bus_mode;
+	unsigned char		bus_width;
+	unsigned long		bus_clkrate;
+	unsigned long		asic_clkrate;
+	unsigned char		power_mode;
+#endif
+	struct ak88_mci_platform_data *plat;
+
+#if 0
+	u8			hw_designer;
+	u8			hw_revision:4;
+#endif
+
+#if 0
+	struct timer_list	timer;
+	unsigned int		oldstat;
+#endif
+
+	unsigned int		sg_len;
+
+	/* pio stuff */
+	struct scatterlist	*sg_ptr;
+	unsigned int		sg_off;
+	unsigned int		size;
+
+#if 0
+	struct regulator	*vcc;
+#endif
+
+	struct timer_list	detect_timer;
+
+	void __iomem		*l2base;
+	void __iomem		*l2fifo;
+};
+
+static inline void ak88_mci_init_sg(struct ak88_mci_host *host, struct mmc_data *data)
+{
+	/*
+	 * Ideally, we want the higher levels to pass us a scatter list.
+	 */
+	host->sg_len = data->sg_len;
+	host->sg_ptr = data->sg;
+	host->sg_off = 0;
+}
+
+static inline int ak88_mci_next_sg(struct ak88_mci_host *host)
+{
+	host->sg_ptr++;
+	host->sg_off = 0;
+	return --host->sg_len;
+}
+
+static inline char *ak88_mci_kmap_atomic(struct ak88_mci_host *host, unsigned long *flags)
+{
+	struct scatterlist *sg = host->sg_ptr;
+
+	local_irq_save(*flags);
+	return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
+}
+
+static inline void ak88_mci_kunmap_atomic(struct ak88_mci_host *host, void *buffer, unsigned long *flags)
+{
+	kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+	local_irq_restore(*flags);
+}
diff --git a/drivers/mmc/host/ak98-mmc/Kconfig b/drivers/mmc/host/ak98-mmc/Kconfig
new file mode 100644
index 00000000000..cd2cda3fb5d
--- /dev/null
+++ b/drivers/mmc/host/ak98-mmc/Kconfig
@@ -0,0 +1,31 @@
+
+
+config MMC_AK98
+    tristate "AK98  MMC/SD/SDIO Card Interface support"
+    depends on ARCH_AK98
+    help
+      This selects the AK98 MMC/SD card Interface.
+      say Y or M here.
+      If unsure, say N.
+
+choice 
+	prompt "MMC/SD Data line select"
+	depends on MMC_AK98
+	default FOUR_DATA_LINE
+
+config FOUR_DATA_LINE
+	bool "four data line mmc/sd slot"
+
+config EIGHT_DATA_LINE
+	bool "eight data line mmc/sd slot"
+endchoice
+
+config SDIO_DEVICE_SLOT
+    tristate "AK98 SDIO Card slot"
+	default N
+    help
+      This selects the AK98 sdio card Interface.
+      say Y or M here.
+      If unsure, say N.
+
+
diff --git a/drivers/mmc/host/ak98-mmc/Makefile b/drivers/mmc/host/ak98-mmc/Makefile
new file mode 100644
index 00000000000..c6e976c8398
--- /dev/null
+++ b/drivers/mmc/host/ak98-mmc/Makefile
@@ -0,0 +1,4 @@
+
+obj-$(CONFIG_MMC_AK98)    += ak98_mci.o
+obj-$(CONFIG_SDIO_DEVICE_SLOT)    += ak98_sdio.o
+
diff --git a/drivers/mmc/host/ak98-mmc/ak98_mci.c b/drivers/mmc/host/ak98-mmc/ak98_mci.c
new file mode 100755
index 00000000000..54fb856c05c
--- /dev/null
+++ b/drivers/mmc/host/ak98-mmc/ak98_mci.c
@@ -0,0 +1,1406 @@
+/*
+ *  linux/drivers/mmc/host/ak98_mci.c - ak98 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/highmem.h>
+#include <linux/log2.h>
+#include <linux/mmc/host.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/scatterlist.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/cacheflush.h>
+#include <asm/div64.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <mach/l2.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+#include <mach/regs-comm.h>
+#include <mach/ak98_mci.h>
+
+#define DRIVER_NAME "ak98_mci"
+
+//#define AKMCI_INNERFIFO_PIO /* only 4bytes inner fifo */
+#define AKMCI_L2FIFO_PIO
+//#define AKMCI_L2FIFO_DMA
+
+#define hydbg(fmt,args...) //printk("%s(%d):" fmt, __func__,__LINE__,##args)
+
+#define DBG(host,fmt,args...)	\
+	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
+
+#define PK1(fmt...) 	//printk(fmt)
+#define PK(fmt...)  	//printk(fmt)
+#define PKCLK(fmt...)   //printk(fmt)
+
+/*
+* because the sd card and the nand share the data pin,so the sd driver
+*and the nand driver must be sync with semaphore.
+*/
+#ifdef CONFIG_MTD_NAND_AK98
+extern struct semaphore nand_lock;
+#endif
+
+static u8   l2_mci_bufid = BUF_NULL;
+
+#if defined AKMCI_L2FIFO_PIO || defined AKMCI_L2FIFO_DMA
+static unsigned int fmax = (20*1000*1000);
+#elif defined AKMCI_INNERFIFO_PIO
+static unsigned int fmax = (4*1000*1000);
+#else
+#error "Please select one FIFO translation mode!"
+#endif
+
+#if 0
+static void ak98_mci_dump_regs(void *base)
+{
+	int i;
+
+	for (i = 0; i <= 0x40; i+=4) {
+		PK("%02x - %08x\n", i, ioread32(base+i));
+	}
+}
+
+static void dump_data(struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	u8 *sg_dat, *sg_end;
+	unsigned int blks, blkdat;
+
+	printk("%s\n", __func__);
+
+	sg = data->sg;
+	sg_dat = sg_virt(sg);
+	sg_end = sg_dat + sg->length;
+
+	for (blks = 0; blks < data->blocks; blks++) {
+		for (blkdat = 0; blkdat < data->blksz; blkdat++) {
+			printk("%02X ", *sg_dat);
+			if ((blkdat % 16) == 15)
+				printk("\n");
+			sg_dat++;
+			if (sg_dat >= sg_end) {
+				sg = sg_next(sg);
+				if (sg == NULL)
+					break;
+				sg_dat = sg_virt(sg);
+				sg_end = sg_dat + sg->length;
+			}
+		}
+		printk("\n");
+	}
+}
+#endif
+#ifdef AKMCI_L2FIFO_PIO
+/**
+ * @brief transmitting data.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of data transmitted, including data buf pointer, data len .
+ * @return void.
+ */
+static void mci_xfer(struct ak98_mci_host *host)
+{
+	int  sg_remain;
+	u32 *tempbuf,xferlen;
+	u8 dir;
+
+	PK("%s\n", __func__);
+
+	if (host->data->flags & MMC_DATA_WRITE) {		
+		dir = MEM2BUF;
+	} else {
+	    //ak98_l2_clr_status(l2_mci_bufid);
+		dir = BUF2MEM;
+	}	
+
+    tempbuf = sg_virt(host->sg_ptr) + host->sg_off;
+    sg_remain = host->sg_ptr->length - host->sg_off;
+    
+    if (sg_remain <= 0)
+    {        
+        host->sg_ptr = sg_next(host->sg_ptr);        
+        if (host->sg_ptr == NULL)
+				return;
+				
+		host->sg_off = 0;
+		tempbuf = sg_virt(host->sg_ptr) + host->sg_off;
+        sg_remain = host->sg_ptr->length - host->sg_off;
+    }
+  
+    xferlen = (sg_remain > host->data->blksz) ? host->data->blksz : sg_remain;    
+    ak98_l2_combuf_cpu((unsigned long)tempbuf, l2_mci_bufid, xferlen, dir); 
+    host->sg_off += xferlen;
+    host->data_xfered += xferlen;    
+		
+}
+#endif
+
+void ak98_mci_init_sg(struct ak98_mci_host *host, struct mmc_data *data)
+{
+	/*
+	 * Ideally, we want the higher levels to pass us a scatter list.
+	 */
+	host->sg_len = data->sg_len;
+	host->sg_ptr = data->sg;
+	host->sg_off = 0;
+}
+
+int ak98_mci_next_sg(struct ak98_mci_host *host)
+{
+	host->sg_ptr++;
+	host->sg_off = 0;
+	return --host->sg_len;
+}
+
+char *ak98_mci_kmap_atomic(struct ak98_mci_host *host, unsigned long *flags)
+{
+	struct scatterlist *sg = host->sg_ptr;
+
+	local_irq_save(*flags);
+	return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
+}
+
+void ak98_mci_kunmap_atomic(struct ak98_mci_host *host, void *buffer, unsigned long *flags)
+{
+	kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
+	local_irq_restore(*flags);
+}
+
+/**
+ * @brief config group pin according the sd slot.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] void.
+ * @return void.
+ */
+
+static void ak98_group_pin_config(void)
+{
+#ifdef CONFIG_EIGHT_DATA_LINE    
+    ak98_group_config(ePIN_AS_SDMMC1);
+#elif defined CONFIG_FOUR_DATA_LINE
+    ak98_group_config(ePIN_AS_SDMMC2);
+#endif
+
+}
+
+/**
+ * @brief stop data, close interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host get the base address of resgister.
+ * @return void.
+ */
+
+static void ak98_mci_stop_data(struct ak98_mci_host *host)
+{
+	u32 masks;
+
+	PK1("%s\n", __func__);
+
+	writel(0, host->base + AK98MCIDMACTRL);
+	writel(0, host->base + AK98MCIDATACTRL);
+	masks = readl(host->base + AK98MCIMASK);
+	masks &= ~(MCI_DATAIRQMASKS|MCI_FIFOFULLMASK|MCI_FIFOEMPTYMASK);
+	writel(masks, host->base + AK98MCIMASK);
+	PK("DISABLE DATA IRQ\n"); 
+     
+#ifdef MCI_USE_L2FIFO_DMA
+	if (host->data->flags & MMC_DATA_WRITE) {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+	} else {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+	}
+#endif
+
+	host->data = NULL; 
+	
+}
+
+/**
+ * @brief  finish a request,release resource.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *mrq information of request.
+ * @return void.
+ */
+
+static void ak98_mci_request_end(struct ak98_mci_host *host, struct mmc_request *mrq)
+{
+    int not_retry = 0;
+    PK1("%s\n", __func__);
+
+	writel(0, host->base + AK98MCICOMMAND);
+	   
+	BUG_ON(host->data);
+
+	host->mrq = NULL;
+	host->cmd = NULL;
+
+    if(l2_mci_bufid != BUF_NULL)
+    {
+        ak98_l2_free(ADDR_MMC_SD);
+        l2_mci_bufid = BUF_NULL;
+    }
+
+	if (mrq->data)
+		mrq->data->bytes_xfered = host->data_xfered;
+	
+	/*
+	 * Need to drop the host lock here; mmc_request_done may call
+	 * back into the driver...
+	 */
+	spin_unlock(&host->lock);
+	
+    not_retry = (!mrq->cmd->error) || ((mrq->cmd->error && (mrq->cmd->retries == 0)));
+    mmc_request_done(host->mmc, mrq);
+    
+#ifdef CONFIG_MTD_NAND_AK98
+
+    /*if request fail,then mmc_request_done send request again, 
+        * ak98_mci_send_request not down nand_lock in interrupt,so not to up nand_lock.
+        */
+    if (not_retry) 
+    {           
+        up(&nand_lock);
+    }
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+	 /*if request fail,then mmc_request_done send request again, 
+	   * ak98_mci_send_request not down freq_lock in interrupt,so not to unlock freq_lock.
+	   */
+
+	 if (not_retry) 
+	 {					   
+		 up(&host->freq_lock);
+	 }	  
+#endif
+
+	spin_lock(&host->lock);
+}
+
+/**
+ * @brief  config sd controller, start transmitting data.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *data information of data transmitted.
+ * @return void.
+ */
+
+static void ak98_mci_start_data(struct ak98_mci_host *host, struct mmc_data *data)
+{
+	unsigned int datactrl, timeout;
+	unsigned long long clks;
+	void __iomem *base;
+    
+	PK("%s: blksz %04x blks %04x flags %08x\n",
+	       __func__, data->blksz, data->blocks, data->flags);
+
+	host->data = data;
+	host->size = data->blksz * data->blocks;
+	host->data_xfered = 0;
+
+	ak98_mci_init_sg(host, data);  
+	
+	clks = (unsigned long long)data->timeout_ns * host->bus_clkrate;
+	do_div(clks, 1000000000UL);
+	timeout = data->timeout_clks + (unsigned int)clks;
+	
+	PK("timeout: %uns / %uclks, clks=%d\n", data->timeout_ns, data->timeout_clks,clks);
+
+	base = host->base;
+	writel(timeout, base + AK98MCIDATATIMER);
+	writel(host->size, base + AK98MCIDATALENGTH);
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK98MCIDMACTRL);
+
+#ifdef AKMCI_L2FIFO_DMA
+    u32    regval;	
+
+	/* get l2 fifo */
+	regval = readl(host->l2base + L2FIFO_ASSIGN1);
+	regval = (regval & (~(3<<12))) | (MCI_L2FIFO_NUM << 12);
+	writel(regval, host->l2base + L2FIFO_ASSIGN1);
+
+	regval = readl(host->l2base + L2FIFO_CONF1);
+	regval |= (1 << (0 + MCI_L2FIFO_NUM))
+		| (1 << (16 + MCI_L2FIFO_NUM))
+		| (1 << (24 + MCI_L2FIFO_NUM));
+	if (data->flags & MMC_DATA_WRITE)
+		regval |= (1 << (8 + MCI_L2FIFO_NUM));
+	else
+		regval &= ~(1 << (8 + MCI_L2FIFO_NUM));
+	writel(regval, host->l2base + L2FIFO_CONF1);
+
+	/* set dma addr */
+	if (data->flags & MMC_DATA_WRITE)
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_TO_DEVICE);
+	else
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_FROM_DEVICE);
+	writel(sg_dma_address(data->sg), host->l2base + MCI_L2FIFO_NUM);
+
+	/* set dma size */
+	if (host->size > L2DMA_MAX_SIZE)
+		dma_size = L2DMA_MAX_SIZE;
+	dma_times = dma_size/64;
+	writel(dma_times, host->l2base + 0x40 + MCI_L2FIFO_NUM);
+
+	if (host->size > L2DMA_MAX_SIZE) {
+		/* need to handle dma int */
+		regval = readl(host->l2base + L2FIFO_INTEN);
+		regval |= (1 << (9 + MCI_L2FIFO_NUM));
+		writel(regval, host->l2base + L2FIFO_INTEN);
+
+		request_irq(AK88_L2MEM_IRQ(x)(9+MCI_L2FIFO_NUM), ak98_mcil2_irq,
+			    IRQF_DISABLED, DRIVER_NAME "(dma)", host);
+	}
+
+	/* when to start dma? */
+	regval = readl(host->l2base + L2FIFO_DMACONF);
+	regval |= (1 | (1 << (24 + MCI_L2FIFO_NUM)));
+	writel(regval, host->l2base + L2FIFO_DMACONF);
+
+	if (dma_size % 64) {
+		/* fraction DMA */
+		(8 * MCI_L2FIFO_NUM)
+	}
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_EN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK98MCIDMACTRL);
+#endif
+
+	datactrl = MCI_DPSM_ENABLE;
+
+	switch (host->bus_width) {
+	case MMC_BUS_WIDTH_8:
+		datactrl |= MCI_DPSM_BUSMODE(2);
+		break;
+	case MMC_BUS_WIDTH_4:
+		datactrl |= MCI_DPSM_BUSMODE(1);
+		break;
+	case MMC_BUS_WIDTH_1:
+	default:
+		datactrl |= MCI_DPSM_BUSMODE(0);
+		break;
+	}
+
+	if (data->flags & MMC_DATA_STREAM) {
+		DBG(host, "%s", "STREAM Data\n");
+		datactrl |= MCI_DPSM_STREAM;
+	} else {
+		DBG(host, "BLOCK Data: %u x %u\n", data->blksz, data->blocks);
+		datactrl |= MCI_DPSM_BLOCKSIZE(data->blksz);
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		datactrl |= MCI_DPSM_DIRECTION;
+	}
+
+	writel(readl(base + AK98MCIMASK) | MCI_DATAIRQMASKS, base + AK98MCIMASK);
+	writel(datactrl, base + AK98MCIDATACTRL);
+
+	PK("ENABLE DATA IRQ, datactrl: 0x%08x, timeout: 0x%08x, len: %u\n",
+	       datactrl, readl(base+AK98MCIDATATIMER), host->size);
+
+#ifdef AKMCI_L2FIFO_PIO
+	if (data->flags & MMC_DATA_WRITE)
+		mci_xfer(host);
+#endif
+
+#ifdef AKMCI_INNERFIFO_PIO
+    unsigned int irqmask;
+    
+	irqmask = readl(base + AK98MCIMASK);
+	if (data->flags & MMC_DATA_READ) {
+		if (host->size > MCI_FIFOSIZE)
+			irqmask |= MCI_FIFOFULLMASK;
+		else
+			;	/* wait for DATAEND int */
+	} else {
+		irqmask |= MCI_FIFOEMPTYMASK;
+	}
+
+	writel(irqmask, base + AK98MCIMASK);
+#endif
+}
+
+/**
+ * @brief  config sd controller, start sending command.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *cmd information of cmd sended.
+ * @return void.
+ */
+
+static void ak98_mci_start_command(struct ak98_mci_host *host, struct mmc_command *cmd)
+{
+	unsigned int c;
+	void __iomem *base = host->base;
+
+	PK1("%s: op %i arg 0x%08x flags 0x%08x\n",
+	       __func__, cmd->opcode, cmd->arg, cmd->flags);
+
+	if (readl(base + AK98MCICOMMAND) & MCI_CPSM_ENABLE) {
+		writel(0, base + AK98MCICOMMAND);
+		udelay(1);
+	}
+
+	c = MCI_CPSM_CMD(cmd->opcode) | MCI_CPSM_ENABLE;
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		c |= MCI_CPSM_RESPONSE;
+		if (cmd->flags & MMC_RSP_136)
+			c |= MCI_CPSM_LONGRSP;
+	}
+
+	if (cmd->data)
+		c |= MCI_CPSM_WITHDATA;
+
+	host->cmd = cmd;
+
+	writel(cmd->arg, base + AK98MCIARGUMENT);
+	writel(readl(base + AK98MCIMASK) | MCI_CMDIRQMASKS, base + AK98MCIMASK);
+	PK("ENABLE CMD IRQ\n");
+	PK("irqmask: 0x%08x\n", readl(base+AK98MCIMASK));
+	writel(c, base + AK98MCICOMMAND);
+}
+
+
+#ifdef AKMCI_INNERFIFO_PIO
+static void ak98_mci_pio_irq(struct ak98_mci_host *host, unsigned int status)
+{
+	u32 *p;
+
+	if (host->sg_ptr == NULL) {
+		printk("%s ERROR\n", __func__);
+		return;
+	}
+
+	p = sg_virt(host->sg_ptr) + host->sg_off;
+
+	if ((status & MCI_FIFOFULL) && (status & MCI_RXACTIVE)) {
+		*p = readl(host->base + AK88MCIFIFO);
+		PK("read: 0x%08x\n", *p);
+	} else if ((status & MCI_FIFOEMPTY) && (status & MCI_TXACTIVE)) {
+		writel(*p, host->base + AK88MCIFIFO);
+		PK("write: 0x%08x\n", *p);
+	} else {
+		return;
+	}
+
+	host->data_xfered += 4;
+	host->size -= 4;
+
+	host->sg_off += 4;
+	if (host->sg_off >= host->sg_ptr->length) {
+		ak98_mci_next_sg(host);
+	}
+}
+#endif
+
+/**
+ * @brief  data handle in sd interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *data information of data transmitting.
+ * @return void.
+ */
+
+static void ak98_mci_data_irq(struct ak98_mci_host *host, struct mmc_data *data,
+		  unsigned int status)
+{
+	if (status & MCI_DATABLOCKEND) {
+		PK("BLOCKEND\n");
+#ifdef AKMCI_L2FIFO_PIO
+        if (data->flags & MMC_DATA_WRITE)
+        {
+            ak98_l2_clr_status(l2_mci_bufid);
+        }
+		if (host->size > 0)
+			mci_xfer(host);
+		
+#endif
+	}
+	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBIT_ERR)) {
+		PK1("DATA ERROR: 0x%08x\n", status);
+
+		if (status & MCI_DATACRCFAIL || status & MCI_STARTBIT_ERR)
+			data->error = -EILSEQ;
+		else if (status & MCI_DATATIMEOUT)
+			data->error = -ETIMEDOUT;
+		status |= MCI_DATAEND;
+		/*
+		 * We hit an error condition.  Ensure that any data
+		 * partially written to a page is properly coherent.
+		 */
+		if (host->sg_len && data->flags & MMC_DATA_READ)
+			flush_dcache_page(sg_page(host->sg_ptr));
+	}
+	if (status & MCI_DATAEND) {
+		ak98_mci_stop_data(host);
+
+		//dump_data(data);
+
+		if (!data->stop) {
+			ak98_mci_request_end(host, data->mrq);
+		} else {
+			ak98_mci_start_command(host, data->stop);
+		}
+	}
+}
+
+/**
+ * @brief  cmd handle in sd interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *cmd information of cmd sended.
+  *@param [in] *status the status of sd controller.
+ * @return void.
+ */
+
+static void ak98_mci_cmd_irq(struct ak98_mci_host *host, struct mmc_command *cmd,
+		 unsigned int status)
+{
+	void __iomem *base = host->base;
+
+	PK("+%s\n", __func__);
+	host->cmd = NULL;
+
+	cmd->resp[0] = readl(base + AK98MCIRESPONSE0);
+	cmd->resp[1] = readl(base + AK98MCIRESPONSE1);
+	cmd->resp[2] = readl(base + AK98MCIRESPONSE2);
+	cmd->resp[3] = readl(base + AK98MCIRESPONSE3);
+    PK("base=0x%x,resp[0]=0x%x, [1]=0x%x,resp[2]=0x%x, [3]=0x%x",base,cmd->resp[0],
+                    cmd->resp[1],cmd->resp[2],cmd->resp[3]);
+	if (status & MCI_RESPTIMEOUT) {
+		cmd->error = -ETIMEDOUT;
+	} else if (status & MCI_RESPCRCFAIL && cmd->flags & MMC_RSP_CRC) {
+		cmd->error = -EILSEQ;
+	}
+
+	writel(readl(base + AK98MCIMASK) & ~MCI_CMDIRQMASKS, base + AK98MCIMASK);
+	PK("DISABLE CMD IRQ\n");
+
+	if (!cmd->data || cmd->error) {
+		if (host->data)
+			ak98_mci_stop_data(host);
+		ak98_mci_request_end(host, cmd->mrq);
+	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
+		ak98_mci_start_data(host, cmd->data);
+	}
+	PK("-%s\n", __func__);
+}
+
+/*
+ * Handle completion of command and data transfers.
+ */
+static irqreturn_t ak98_mci_irq(int irq, void *dev_id)
+{
+	struct ak98_mci_host *host = dev_id;
+	u32 status;
+	int ret = 0;
+
+	PK("+%s ", __func__);
+
+	spin_lock(&host->lock);
+
+	do {
+		struct mmc_command *cmd;
+		struct mmc_data *data;
+
+		status = readl(host->base + AK98MCISTATUS);
+
+		PK(" status= 0x%08x\n", status);
+
+#ifdef AKMCI_INNERFIFO_PIO
+		if (host->data)
+			ak98_mci_pio_irq(host, status);
+#endif
+
+		cmd = host->cmd;
+		if (status & (MCI_RESPCRCFAIL|MCI_RESPTIMEOUT|MCI_CMDSENT|MCI_RESPEND)
+		    && cmd)
+			ak98_mci_cmd_irq(host, cmd, status);
+
+		data = host->data;
+		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_DATAEND|MCI_DATABLOCKEND|MCI_STARTBIT_ERR)
+		    && data)
+			ak98_mci_data_irq(host, data, status);
+
+#ifdef SDIO
+		if (status & MCI_SDIOINT) {
+			mmc_signal_sdio_irq(host->mmc);
+		}
+#endif
+
+		ret = 1;
+	} while (0);
+
+	spin_unlock(&host->lock);
+
+	PK("-%s, irqmask: 0x%08x\n", __func__, readl(host->base + AK98MCIMASK));
+
+	return IRQ_RETVAL(ret);
+}
+
+/**
+ * @brief  detect sd card's level type .
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] data  getting the information of sd host.
+ * @return void.
+ */
+
+static void ak98_mci_detect_change(unsigned long data)
+{
+	struct ak98_mci_host *host = (struct ak98_mci_host *)data;
+
+	PK("%s\n", __func__);
+
+	mmc_detect_change(host->mmc, 0);
+
+	if (host->irq_cd_type == IRQ_TYPE_LEVEL_LOW) {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_LOW;
+	}
+	set_irq_type(host->irq_cd, host->irq_cd_type);
+	enable_irq(host->irq_cd);
+}
+
+static irqreturn_t ak98_mci_card_detect_irq(int irq, void *dev)
+{
+	struct ak98_mci_host *host = dev;
+
+	PK("%s##################\n", __func__);
+
+	disable_irq_nosync(irq);
+	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(400));
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * @brief   detect the sd card whether or not is in.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host ,getting the sd detect gpio.
+ * @return int.
+ * @retal 1 sd card is in ;0 sd card is not in
+ */
+
+static int ak98_mci_get_cd(struct mmc_host *mmc)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);	
+
+	if (host->gpio_cd == -ENOSYS)
+		return -ENOSYS;	
+		
+	//printk("%s: %i\n", __func__, ak98_gpio_getpin(host->gpio_cd) == 0);
+	return (ak98_gpio_getpin(host->gpio_cd) == 0);
+}
+
+/**
+ * @brief   detect the sd card writing protection.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host ,getting the sd detect gpio.
+ * @return int.
+ * @retal 1 sd card writing protected ;0 sd card writing is not protected
+ */
+
+static int ak98_mci_get_ro(struct mmc_host *mmc) 
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);
+
+	if (host->gpio_wp == -ENOSYS)
+		return -ENOSYS;
+
+	//printk("%s: %i\n", __func__, ak98_gpio_getpin(host->gpio_wp));
+	return (ak98_gpio_getpin(host->gpio_wp) == 0);
+}
+
+static void ak98mci_set_clk(struct ak98_mci_host *host, struct mmc_ios *ios)
+{
+	unsigned int regval;
+	int div;
+
+	PKCLK("%s\n",__func__);	
+	
+	if (ios->clock == 0) 
+	{
+		regval = readl(host->base + AK98MCICLOCK);
+		regval &= ~MCI_CLK_ENABLE;
+		host->bus_clkrate = 0;
+		writel(regval, host->base + AK98MCICLOCK);		
+	} 
+	else 
+	{
+		regval = readl(host->base + AK98MCICLOCK);
+		regval |= MCI_CLK_ENABLE;
+		regval &= ~0xffff; /* clear clk div */
+		div = host->asic_clkrate/ios->clock - 2;
+		PKCLK("host->asic_clkrate = %ld\n",host->asic_clkrate); 
+		PKCLK("ios->clock = %d\n",ios->clock); 
+		printk("clk_div: %d\n", div);
+		
+		/*
+		*the high bytes and the lower bytes of the register must be equal
+		*/
+		regval |= MMC_CLK_DIVL(div/2) | MMC_CLK_DIVH(div/2);			
+		host->bus_clkrate = host->asic_clkrate / (div + 2);
+		writel(regval, host->base + AK98MCICLOCK);		
+	}
+
+}
+
+
+/**
+ * @brief   set sd bus mode,bus width,clock.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host .
+ * @param [in] *ios information of sd interface .
+ * @return void.
+ */
+static void ak98_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);
+
+	hydbg("bus_mode=%d,bus_width=%d\n", ios->bus_mode, ios->bus_width);
+	
+	/* ak98 (and SD spec) don't support MMC_BUSMODE_OPENDRAIN */
+	host->bus_mode = ios->bus_mode;
+	host->bus_width = ios->bus_width;
+	//printk("%ubits(%u); ", (unsigned)1 >> (host->bus_width), host->bus_width);
+
+	/* we can't control external power supply unit */
+	switch (ios->power_mode) {
+	case MMC_POWER_UP:
+		PK("MMC_POWER_UP; ");
+		break;
+	case MMC_POWER_ON:
+		PK("MMC_POWER_ON; ");
+		break;
+	case MMC_POWER_OFF:
+		PK("MMC_POWER_OFF; ");
+		break;
+	}
+
+#ifdef CONFIG_CPU_FREQ
+	down(&host->freq_lock);
+#endif
+	
+#ifdef CONFIG_MTD_NAND_AK98   
+	down(&nand_lock);
+#endif
+	ak98_group_pin_config();
+	
+	if (ios->clock != host->bus_clkrate) 
+	{
+		ak98mci_set_clk(host,ios);
+	}
+	
+#ifdef CONFIG_MTD_NAND_AK98
+	up(&nand_lock);
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+	 up(&host->freq_lock);
+#endif
+	
+	
+	/* no matter high-speed mode or not, ak88 mci use the same timing */   
+	
+	//printk("ios->clock(%dkhz), host->bus_clkrate(%lukhz), host->asic_clkrate(%lumhz), MMC_CLK_CTRL(0x%08x)\n",
+	//  ios->clock/1000, host->bus_clkrate/1000, host->asic_clkrate/1000000, readl(host->base + AK98MCICLOCK));
+}
+
+
+/**
+ * @brief   reset sd card clock.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] void .
+ * @return void.
+ */
+
+static void ak98_mci_reset(void)
+{
+    rCLK_CON2 |= (0x1 << 18);
+    rCLK_CON2 &= ~(0x1 << 18);
+}
+
+/**
+ * @brief   send a request, starting data or command.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host .
+ * @return void.
+ */
+
+static void ak98_mci_send_request(struct mmc_host *mmc)
+{
+    struct ak98_mci_host *host = mmc_priv(mmc); 
+    struct mmc_request *mrq = host->mrq;	
+    unsigned long flags; 
+
+
+#ifdef CONFIG_CPU_FREQ
+     /*
+        * need not to acquire the freq_lock in interrupt.
+        */
+     if (!in_interrupt()) 
+     {                     
+		 down(&host->freq_lock);
+         
+     }    
+#endif
+
+#ifdef CONFIG_MTD_NAND_AK98	
+     /*
+        * need not to acquire the nand_lock in interrupt.
+        */
+     if (!in_interrupt()) 
+     {                     
+         down(&nand_lock);           
+     }    
+#endif
+
+    ak98_group_pin_config();
+
+    /*
+        *when transmit data, alloc the L2 buffer Id.
+        */
+    if(mrq->data)
+    {
+        l2_mci_bufid = ak98_l2_alloc(ADDR_MMC_SD);
+        if (BUF_NULL == l2_mci_bufid)
+        {
+            printk("L2 buffer malloc fail!\n");
+            BUG();
+        }
+        ak98_l2_clr_status(l2_mci_bufid);
+    }    
+    
+    spin_lock_irqsave(&host->lock, flags);  
+    
+	if (mrq->data && (mrq->data->flags & MMC_DATA_READ))
+		ak98_mci_start_data(host, mrq->data);
+
+	ak98_mci_start_command(host, mrq->cmd);
+
+	spin_unlock_irqrestore(&host->lock, flags);    
+
+}
+
+static void ak98_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);	
+
+	PK1("%s: CMD%i\n", __func__, mrq->cmd->opcode);
+	
+	host->mrq = mrq;	
+
+    if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
+        printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
+               mmc_hostname(mmc), mrq->data->blksz);
+        mrq->cmd->error = -EINVAL;
+        mmc_request_done(mmc, mrq);
+        return;
+    }
+
+    if (ak98_mci_get_cd(mmc) == 0)
+    {
+        printk("%s: no medium present\n", __func__);
+		host->mrq->cmd->error = -ENOMEDIUM;
+		mmc_request_done(mmc, mrq);        
+    }
+    else
+    {
+        ak98_mci_send_request(mmc); 
+    }	
+	
+}
+
+/**
+ * register the function of sd driver.
+ * 
+ */
+
+static const struct mmc_host_ops ak98_mci_ops = {
+	.request	= ak98_mci_request,
+	.set_ios	= ak98_mci_set_ios,
+	.get_ro		= ak98_mci_get_ro,
+	.get_cd		= ak98_mci_get_cd,
+};
+
+
+// difine change cpu freq
+#ifdef CONFIG_CPU_FREQ
+
+static int ak98mci_cpufreq_transition(struct notifier_block *nb,
+				     unsigned long val, void *data)
+{
+	struct ak98_mci_host *host;
+	struct mmc_host *mmc;
+	unsigned long newclk;
+	unsigned long flags;
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+	host = container_of(nb, struct ak98_mci_host, freq_transition);
+	
+	PKCLK("%s\n",__func__);	
+	PKCLK("%s(): in_interrupt()=%ld\n", __func__, in_interrupt());
+	PKCLK("ak98_get_asic_clk = %ld\n",ak98_get_asic_clk());	
+	PKCLK("freqs->new_cpufreq.asic_clk = %d\n",
+		  freqs->new_cpufreq.asic_clk);	
+		  
+	mmc = host->mmc;
+	newclk = freqs->new_cpufreq.asic_clk;
+	if ((val == CPUFREQ_PRECHANGE && newclk > host->asic_clkrate) 
+		|| (val == CPUFREQ_POSTCHANGE && newclk < host->asic_clkrate)) 
+	{
+
+		if (mmc->ios.power_mode != MMC_POWER_OFF &&
+			mmc->ios.clock != 0)
+		{		
+			PKCLK("%s(): preempt_count()=%d\n",
+				__func__, preempt_count());
+			down(&host->freq_lock);
+		
+			spin_lock_irqsave(&mmc->lock, flags);
+		
+			host->asic_clkrate = newclk;
+			PKCLK("AK98MCICLOCK1 = %d\n",readl(host->base + AK98MCICLOCK));	
+			ak98mci_set_clk(host, &mmc->ios);
+			PKCLK("AK98MCICLOCK2 = %d\n",readl(host->base + AK98MCICLOCK));	
+			
+			spin_unlock_irqrestore(&mmc->lock, flags);
+			
+			up(&host->freq_lock);
+		}		
+
+	}
+
+	return NOTIFY_DONE;
+}
+
+static inline int ak98mci_cpufreq_register(struct ak98_mci_host *host)
+{
+	// use for requst and cpufreq
+	init_MUTEX(&host->freq_lock);
+	
+	host->freq_transition.notifier_call = ak98mci_cpufreq_transition;
+
+	return cpufreq_register_notifier(&host->freq_transition,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void ak98mci_cpufreq_deregister(struct ak98_mci_host *host)
+{
+	cpufreq_unregister_notifier(&host->freq_transition,
+				    CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int ak98mci_cpufreq_register(struct ak98_mci_host *host)
+{
+	return 0;
+}
+
+static inline void ak98mci_cpufreq_deregister(struct ak98_mci_host *host)
+{
+}
+#endif
+
+// difine change cpu freq end
+
+
+#if 0
+static void ak98_mci_check_status(unsigned long data)
+{
+	struct ak98_mci_host *host = (struct ak98_mci_host *)data;
+	unsigned int status = ak98_mci_get_cd(host->mmc);
+
+	if (status ^ host->oldstat)
+		mmc_detect_change(host->mmc, 0);
+
+	host->oldstat = status;
+	mod_timer(&host->timer, jiffies + HZ);
+}
+#endif
+
+/**
+ * @brief   sd driver probe and init.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *pdev information of platform device ,getting the sd driver resource .
+ * @return int.
+ * @retval -EINVAL no platform data , fail;
+ * @retval -EBUSY  requset mem  fail;
+ * @retval -ENOMEM  alloc mem fail;
+ */
+ 
+
+static int __devinit ak98_mci_probe(struct platform_device *pdev)
+{
+	struct ak98_mci_platform_data *plat = pdev->dev.platform_data;
+	struct ak98_mci_host *host;
+	struct mmc_host *mmc;
+	struct resource *res;
+	int irq;
+	int ret;
+
+	/* must have platform data */
+	if (!plat) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	PK("%s\n", __func__);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+
+	PK("res: %x, %u", res->start, resource_size(res));
+	res = request_mem_region(res->start, resource_size(res), DRIVER_NAME);
+	if (!res) {
+		ret = -EBUSY;
+		goto out;
+	}
+	PK("res: %x, %u\n", res->start, resource_size(res));
+
+	mmc = mmc_alloc_host(sizeof(struct ak98_mci_host), &pdev->dev);
+	if (!mmc) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	host = mmc_priv(mmc);
+	host->mmc = mmc;
+
+	host->gpio_wp = -ENOSYS;
+	host->gpio_cd = -ENOSYS;
+
+    ak98_mci_reset();
+	host->clk = clk_get(&pdev->dev, "mci_clk");
+
+    if (IS_ERR(host->clk)) {
+        ret = PTR_ERR(host->clk);
+        host->clk = NULL;
+        goto host_free;
+    }      
+
+	ret = clk_enable(host->clk);
+	if (ret)
+		goto clk_free;
+
+	host->plat = plat;
+	host->asic_clkrate = ak98_get_asic_clk();
+	
+
+	host->base = ioremap(res->start, resource_size(res));
+	if (!host->base) {
+		ret = -ENOMEM;
+		goto clk_disable;
+	} 
+    PK("asic_clkrate: %luhz,host->base=0x%x\n", host->asic_clkrate,host->base);
+	mmc->ops = &ak98_mci_ops;
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	/*
+	 * set the transmit mode to four data line mode, if not set, 
+	 * default is one data line mode.
+	 */
+	mmc->caps = MMC_CAP_4_BIT_DATA;
+#if 0
+	mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+#endif 
+
+//	mmc->caps |= MMC_CAP_NEEDS_POLL;
+	mmc->f_min = host->asic_clkrate / (255+1 + 255+1);
+	mmc->f_max = host->asic_clkrate / (0+1 + 0+1);
+	mmc->f_max = mmc->f_max < fmax ? mmc->f_max : fmax;
+
+	/*
+	 * We can do SGIO
+	 */
+	mmc->max_hw_segs = 16;
+	mmc->max_phys_segs = NR_SG;
+
+	/*
+	 * Since we only have a 16-bit data length register, we must
+	 * ensure that we don't exceed 2^16-1 bytes in a single request.
+	 */
+	mmc->max_req_size = 65536;
+
+	/*
+	 * Set the maximum segment size.  Since we aren't doing DMA
+	 * (yet) we are only limited by the data length register.
+	 */
+	mmc->max_seg_size = mmc->max_req_size;
+
+#if 0
+	/*
+	 * Block size can be up to 2048 bytes, but must be a power of two.
+	 */
+	mmc->max_blk_size = 2048;
+#else
+	/* as l2 fifo limit to 512 bytes */
+	mmc->max_blk_size = 512;
+#endif
+
+	/*
+	 * No limit on the number of blocks transferred.
+	 */
+	mmc->max_blk_count = mmc->max_req_size;
+
+	spin_lock_init(&host->lock);
+	
+#ifdef CONFIG_MTD_NAND_AK98
+    down(&nand_lock);
+#endif
+    ak98_group_pin_config();
+   // writel(SDIO_INTR_CTR_ENABLE, host->base + AK98SDIOINTRCTR);	
+	
+	writel(MCI_ENABLE|MCI_FAIL_TRIGGER, host->base + AK98MCICLOCK);	
+    PK("%s: MCICLOCK: 0x%08x\n", __func__, readl(host->base + AK98MCICLOCK));    
+
+#ifdef CONFIG_MTD_NAND_AK98
+    up(&nand_lock);
+#endif
+
+	writel(0, host->base + AK98MCIMASK);
+	
+	PK("request irq %i\n", irq);
+	ret = request_irq(irq, ak98_mci_irq, IRQF_DISABLED, DRIVER_NAME " (cmd)", host);
+	if (ret)
+		goto unmap;
+		
+	host->irq_mci = irq;
+
+	/*
+	* if card detected pin or write protect pin has  
+	* been config, then config the pins.
+	*/
+	if(plat->gpio_cd >= 0)
+	{
+    	host->gpio_cd = plat->gpio_cd;	
+    	ak98_gpio_cfgpin(host->gpio_cd, AK98_GPIO_DIR_INPUT);
+    	ak98_gpio_pulldown(host->gpio_cd,AK98_PULLDOWN_DISABLE);
+	}
+	if(plat->gpio_wp >= 0)
+	{
+    	host->gpio_wp = plat->gpio_wp;	
+    	ak98_gpio_cfgpin(host->gpio_wp, AK98_GPIO_DIR_INPUT);
+    	ak98_gpio_pullup(host->gpio_wp, AK98_PULLUP_ENABLE);
+    	ak98_gpio_pulldown(host->gpio_wp,AK98_PULLDOWN_DISABLE);
+    }
+	setup_timer(&host->detect_timer, ak98_mci_detect_change,
+		    (unsigned long)host);
+		    
+	irq = ak98_gpio_to_irq(host->gpio_cd);    
+	ret = request_irq(irq, ak98_mci_card_detect_irq,
+			  IRQF_DISABLED,
+			  DRIVER_NAME " cd", host);
+	printk("request gpio irq ret = %d, irq=%d", ret, irq);
+	if (ret)
+		goto irq_free;
+	host->irq_cd = irq;
+	host->irq_cd_type = IRQ_TYPE_LEVEL_LOW;	
+
+	platform_set_drvdata(pdev, mmc);
+
+	ret = ak98mci_cpufreq_register(host);
+	if (ret) {
+		goto irq_free;
+	}
+
+	ret = mmc_add_host(mmc);
+	if (ret) {
+		goto cpufreq_free;
+	}
+
+	PK(KERN_INFO "%s: ak98MCI at 0x%016llx irq %d\n",
+		mmc_hostname(mmc), (unsigned long long)res->start,
+		host->irq_mci);
+
+	return 0;
+
+ cpufreq_free:
+	 PK("ERR cpufreq_free\n");
+	 ak98mci_cpufreq_deregister(host);
+ irq_free:
+	PK("ERR irq_free\n");
+	free_irq(host->irq_mci, host);
+ unmap:
+	PK("ERR unmap\n");
+	iounmap(host->base);
+ clk_disable:
+	PK("ERR clk_disable\n");
+	clk_disable(host->clk);
+ clk_free:
+	PK("ERR clk_free\n");
+	clk_put(host->clk);
+ host_free:
+	PK("ERR host_free\n");
+	mmc_free_host(mmc);
+ out:
+	PK("ERR out\n");
+	return ret;
+}
+
+static int __devexit ak98_mci_remove(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+  
+	platform_set_drvdata(dev, NULL);
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+#if 0
+		del_timer_sync(&host->timer);
+#endif
+		
+		ak98mci_cpufreq_deregister(host);
+
+		mmc_remove_host(mmc);
+
+		writel(0, host->base + AK98MCIMASK);
+
+		writel(0, host->base + AK98MCICOMMAND);
+		writel(0, host->base + AK98MCIDATACTRL);
+
+#if 0
+		if (gpio_is_valid(host->gpio_cd))
+			free_irq(host->irq_cd, host);
+		free_irq(host->irq_mci, host);
+
+		if (host->gpio_wp != -ENOSYS)
+			gpio_free(host->gpio_wp);
+		if (host->gpio_cd != -ENOSYS)
+			gpio_free(host->gpio_cd);
+#else
+		free_irq(host->irq_cd, host);
+		free_irq(host->irq_mci, host);
+#endif
+
+		iounmap(host->base);
+		clk_disable(host->clk);
+		clk_put(host->clk);
+
+		mmc_free_host(mmc);
+	}
+
+	return 0;
+}
+
+//#ifdef CONFIG_PM
+#if 0
+static int ak98_mci_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+		ret = mmc_suspend_host(mmc, state);
+		if (ret == 0)
+			writel(0, host->base + AK98MCIMASK);
+	}
+
+	return ret;
+}
+
+static int ak98_mci_resume(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+		writel(MCI_CMDIRQMASKS | MCI_DATAIRQMASKS, host->base + AK98MCIMASK);
+
+		ret = mmc_resume_host(mmc);
+	}
+
+	return ret;
+}
+#else
+#define ak98_mci_suspend	NULL
+#define ak98_mci_resume	NULL
+#endif
+
+static struct platform_driver ak98_mci_driver = {
+	.driver		= {
+		.name	= DRIVER_NAME,
+	},
+	.probe		= ak98_mci_probe,
+	.remove		= __devexit_p(ak98_mci_remove),
+	.suspend	= ak98_mci_suspend,
+	.resume		= ak98_mci_resume,
+};
+
+static int __init ak98_mci_init(void)
+{
+	printk("%s\n", __func__);
+	return platform_driver_register(&ak98_mci_driver);
+}
+
+static void __exit ak98_mci_exit(void)
+{
+	platform_driver_unregister(&ak98_mci_driver);
+}
+
+module_init(ak98_mci_init);
+module_exit(ak98_mci_exit);
+
+MODULE_DESCRIPTION("Anyka AK98 MMC/SD/SDIO Interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/ak98-mmc/ak98_sdio.c b/drivers/mmc/host/ak98-mmc/ak98_sdio.c
new file mode 100755
index 00000000000..fa5337e37e2
--- /dev/null
+++ b/drivers/mmc/host/ak98-mmc/ak98_sdio.c
@@ -0,0 +1,1335 @@
+/*
+ *  linux/drivers/mmc/host/ak98_sdio.c - ak98 MMC/SD/SDIO driver
+ *
+ *  Copyright (C) 2010 Anyka, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/highmem.h>
+#include <linux/log2.h>
+#include <linux/mmc/host.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/scatterlist.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/cacheflush.h>
+#include <asm/div64.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <mach/l2.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+#include <mach/regs-comm.h>
+#include <mach/ak98_sdio.h>
+
+#define DRIVER_NAME "ak98_sdio"
+
+//#define AKMCI_INNERFIFO_PIO /* only 4bytes inner fifo */
+#define AKMCI_L2FIFO_PIO
+//#define AKMCI_L2FIFO_DMA
+
+#define hydbg(fmt,args...) //printk("%s(%d):" fmt, __func__,__LINE__,##args)
+
+#define DBG(host,fmt,args...)	\
+	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
+
+#define PK1(fmt...) 	//printk(fmt)
+#define PK(fmt...) 	 	//printk(fmt)
+#define PKCLK(fmt...) 	//printk(fmt)
+
+static u8    l2_sdio_bufid = BUF_NULL ;
+
+#if defined AKMCI_L2FIFO_PIO || defined AKMCI_L2FIFO_DMA
+static unsigned int fmax = (20*1000*1000);
+#elif defined AKMCI_INNERFIFO_PIO
+static unsigned int fmax = (4*1000*1000);
+#else
+#error "Please select one FIFO translation mode!"
+#endif
+
+#if 0
+static void ak98_sdio_dump_regs(void *base)
+{
+	int i;
+
+	for (i = 0; i <= 0x40; i+=4) {
+		PK("%02x - %08x\n", i, ioread32(base+i));
+	}
+}
+
+static void dump_data(struct mmc_data *data)
+{
+	struct scatterlist *sg;
+	u8 *sg_dat, *sg_end;
+	unsigned int blks, blkdat;
+
+	printk("%s\n", __func__);
+
+	sg = data->sg;
+	sg_dat = sg_virt(sg);
+	sg_end = sg_dat + sg->length;
+
+	for (blks = 0; blks < data->blocks; blks++) {
+		for (blkdat = 0; blkdat < data->blksz; blkdat++) {
+			printk("%02X ", *sg_dat);
+			if ((blkdat % 16) == 15)
+				printk("\n");
+			sg_dat++;
+			if (sg_dat >= sg_end) {
+				sg = sg_next(sg);
+				if (sg == NULL)
+					break;
+				sg_dat = sg_virt(sg);
+				sg_end = sg_dat + sg->length;
+			}
+		}
+		printk("\n");
+	}
+}
+#endif
+#ifdef AKMCI_L2FIFO_PIO
+/**
+ * @brief transmitting data.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of data transmitted, including data buf pointer, data len .
+ * @return void.
+ */
+
+static void mci_xfer(struct ak98_mci_host *host)
+{
+	int  sg_remain;
+	u32 *tempbuf,xferlen;
+	u8 dir;
+
+	PK("%s\n", __func__);
+
+	if (host->data->flags & MMC_DATA_WRITE) {		
+		dir = MEM2BUF;
+	} else {
+	    //ak98_l2_clr_status(l2_sdio_bufid);
+		dir = BUF2MEM;
+	}	
+
+    tempbuf = sg_virt(host->sg_ptr) + host->sg_off;
+    sg_remain = host->sg_ptr->length - host->sg_off;
+    
+    if (sg_remain <= 0)
+    {        
+        host->sg_ptr = sg_next(host->sg_ptr);        
+        if (host->sg_ptr == NULL)
+				return;
+				
+		host->sg_off = 0;
+		tempbuf = sg_virt(host->sg_ptr) + host->sg_off;
+        sg_remain = host->sg_ptr->length - host->sg_off;
+    }
+  
+    xferlen = (sg_remain > host->data->blksz) ? host->data->blksz : sg_remain;    
+    ak98_l2_combuf_cpu((unsigned long)tempbuf, l2_sdio_bufid, xferlen, dir); 
+    host->sg_off += xferlen;
+    host->data_xfered += xferlen;    
+		
+}
+#endif
+
+/**
+ * @brief stop data, close interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host get the base address of resgister.
+ * @return void.
+ */
+
+static void ak98_sdio_stop_data(struct ak98_mci_host *host)
+{
+	u32 masks;
+
+	PK1("%s\n", __func__);
+
+	writel(0, host->base + AK98MCIDMACTRL);
+	writel(0, host->base + AK98MCIDATACTRL);
+	masks = readl(host->base + AK98MCIMASK);
+	masks &= ~(MCI_DATAIRQMASKS|MCI_FIFOFULLMASK|MCI_FIFOEMPTYMASK);
+	writel(masks, host->base + AK98MCIMASK);
+	PK("DISABLE DATA IRQ\n"); 
+     
+#ifdef MCI_USE_L2FIFO_DMA
+	if (host->data->flags & MMC_DATA_WRITE) {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_TO_DEVICE);
+	} else {
+		dma_sync_sg_for_cpu(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+		dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->data->sg_len, DMA_FROM_DEVICE);
+	}
+#endif
+
+	host->data = NULL; 
+	
+}
+
+/**
+ * @brief  finish a request,release resource.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *mrq information of request.
+ * @return void.
+ */
+
+static void ak98_sdio_request_end(struct ak98_mci_host *host, struct mmc_request *mrq)
+{
+    int not_retry = 0;
+
+    PK1("%s\n", __func__);
+
+	writel(0, host->base + AK98MCICOMMAND); 
+	BUG_ON(host->data);
+
+	host->mrq = NULL;
+	host->cmd = NULL;
+
+    if(l2_sdio_bufid != BUF_NULL)
+    {
+        ak98_l2_free(ADDR_SDIO);
+        l2_sdio_bufid = BUF_NULL;
+    }
+    
+	if (mrq->data)
+		mrq->data->bytes_xfered = host->data_xfered;
+	
+	/*
+	 * Need to drop the host lock here; mmc_request_done may call
+	 * back into the driver...
+	 */
+	spin_unlock(&host->lock);    
+
+    not_retry = (!mrq->cmd->error) || ((mrq->cmd->error && (mrq->cmd->retries == 0)));
+	
+    mmc_request_done(host->mmc, mrq);
+
+#ifdef CONFIG_CPU_FREQ
+	 /*if request fail,then mmc_request_done send request again, 
+	   * ak98_mci_send_request not down freq_lock in interrupt,so not to unlock freq_lock.
+	   */
+
+	 if (not_retry) 
+	 {					   
+		 up(&host->freq_lock);
+	 }	  
+#endif
+
+    
+	spin_lock(&host->lock);
+}
+
+/**
+ * @brief  config sd controller, start transmitting data.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *data information of data transmitted.
+ * @return void.
+ */
+
+static void ak98_sdio_start_data(struct ak98_mci_host *host, struct mmc_data *data)
+{
+	unsigned int datactrl, timeout;
+	unsigned long long clks;
+	void __iomem *base;
+    
+	PK("%s: blksz %04x blks %04x flags %08x\n",
+	       __func__, data->blksz, data->blocks, data->flags);
+
+	host->data = data;
+	host->size = data->blksz * data->blocks;
+	host->data_xfered = 0;
+
+	ak98_mci_init_sg(host, data);  
+	
+	clks = (unsigned long long)data->timeout_ns * host->bus_clkrate;
+	do_div(clks, 1000000000UL);
+	timeout = data->timeout_clks + (unsigned int)clks;
+	
+	PK("timeout: %uns / %uclks, clks=%d\n", data->timeout_ns, data->timeout_clks,clks);
+
+	base = host->base;
+	writel(timeout, base + AK98MCIDATATIMER);
+	writel(host->size, base + AK98MCIDATALENGTH);
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK98MCIDMACTRL);
+
+#ifdef AKMCI_L2FIFO_DMA
+    u32    regval;	
+
+	/* get l2 fifo */
+	regval = readl(host->l2base + L2FIFO_ASSIGN1);
+	regval = (regval & (~(3<<12))) | (MCI_L2FIFO_NUM << 12);
+	writel(regval, host->l2base + L2FIFO_ASSIGN1);
+
+	regval = readl(host->l2base + L2FIFO_CONF1);
+	regval |= (1 << (0 + MCI_L2FIFO_NUM))
+		| (1 << (16 + MCI_L2FIFO_NUM))
+		| (1 << (24 + MCI_L2FIFO_NUM));
+	if (data->flags & MMC_DATA_WRITE)
+		regval |= (1 << (8 + MCI_L2FIFO_NUM));
+	else
+		regval &= ~(1 << (8 + MCI_L2FIFO_NUM));
+	writel(regval, host->l2base + L2FIFO_CONF1);
+
+	/* set dma addr */
+	if (data->flags & MMC_DATA_WRITE)
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_TO_DEVICE);
+	else
+		dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, DMA_FROM_DEVICE);
+	writel(sg_dma_address(data->sg), host->l2base + MCI_L2FIFO_NUM);
+
+	/* set dma size */
+	if (host->size > L2DMA_MAX_SIZE)
+		dma_size = L2DMA_MAX_SIZE;
+	dma_times = dma_size/64;
+	writel(dma_times, host->l2base + 0x40 + MCI_L2FIFO_NUM);
+
+	if (host->size > L2DMA_MAX_SIZE) {
+		/* need to handle dma int */
+		regval = readl(host->l2base + L2FIFO_INTEN);
+		regval |= (1 << (9 + MCI_L2FIFO_NUM));
+		writel(regval, host->l2base + L2FIFO_INTEN);
+
+		request_irq(AK88_L2MEM_IRQ(x)(9+MCI_L2FIFO_NUM), ak98_mcil2_irq,
+			    IRQF_DISABLED, DRIVER_NAME "(dma)", host);
+	}
+
+	/* when to start dma? */
+	regval = readl(host->l2base + L2FIFO_DMACONF);
+	regval |= (1 | (1 << (24 + MCI_L2FIFO_NUM)));
+	writel(regval, host->l2base + L2FIFO_DMACONF);
+
+	if (dma_size % 64) {
+		/* fraction DMA */
+		(8 * MCI_L2FIFO_NUM)
+	}
+
+	/* set l2 fifo info */
+	writel (MCI_DMA_BUFEN | MCI_DMA_EN | MCI_DMA_SIZE(MCI_L2FIFO_SIZE/4),
+		base + AK98MCIDMACTRL);
+#endif
+
+	datactrl = MCI_DPSM_ENABLE;
+
+	switch (host->bus_width) {
+	case MMC_BUS_WIDTH_8:
+		datactrl |= MCI_DPSM_BUSMODE(2);
+		break;
+	case MMC_BUS_WIDTH_4:
+		datactrl |= MCI_DPSM_BUSMODE(1);
+		break;
+	case MMC_BUS_WIDTH_1:
+	default:
+		datactrl |= MCI_DPSM_BUSMODE(0);
+		break;
+	}
+
+	if (data->flags & MMC_DATA_STREAM) {
+		DBG(host, "%s", "STREAM Data\n");
+		datactrl |= MCI_DPSM_STREAM;
+	} else {
+		DBG(host, "BLOCK Data: %u x %u\n", data->blksz, data->blocks);
+		datactrl |= MCI_DPSM_BLOCKSIZE(data->blksz);
+	}
+
+	if (data->flags & MMC_DATA_READ) {
+		datactrl |= MCI_DPSM_DIRECTION;
+	}
+
+	writel(readl(base + AK98MCIMASK) | MCI_DATAIRQMASKS, base + AK98MCIMASK);
+	writel(datactrl, base + AK98MCIDATACTRL);
+
+	PK("ENABLE DATA IRQ, datactrl: 0x%08x, timeout: 0x%08x, len: %u\n",
+	       datactrl, readl(base+AK98MCIDATATIMER), host->size);
+
+#ifdef AKMCI_L2FIFO_PIO
+	if (data->flags & MMC_DATA_WRITE)
+		mci_xfer(host);
+#endif
+
+#ifdef AKMCI_INNERFIFO_PIO
+    unsigned int irqmask;
+    
+	irqmask = readl(base + AK98MCIMASK);
+	if (data->flags & MMC_DATA_READ) {
+		if (host->size > MCI_FIFOSIZE)
+			irqmask |= MCI_FIFOFULLMASK;
+		else
+			;	/* wait for DATAEND int */
+	} else {
+		irqmask |= MCI_FIFOEMPTYMASK;
+	}
+
+	writel(irqmask, base + AK98MCIMASK);
+#endif
+}
+
+/**
+ * @brief  config sd controller, start sending command.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *cmd information of cmd sended.
+ * @return void.
+ */
+
+static void ak98_sdio_start_command(struct ak98_mci_host *host, struct mmc_command *cmd)
+{
+	unsigned int c;
+	void __iomem *base = host->base;
+
+	PK1("%s: op %i arg 0x%08x flags 0x%08x\n",
+	       __func__, cmd->opcode, cmd->arg, cmd->flags);
+
+	if (readl(base + AK98MCICOMMAND) & MCI_CPSM_ENABLE) {
+		writel(0, base + AK98MCICOMMAND);
+		udelay(1);
+	}
+
+	c = MCI_CPSM_CMD(cmd->opcode) | MCI_CPSM_ENABLE;
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		c |= MCI_CPSM_RESPONSE;
+		if (cmd->flags & MMC_RSP_136)
+			c |= MCI_CPSM_LONGRSP;
+	}
+
+	if (cmd->data)
+		c |= MCI_CPSM_WITHDATA;
+
+	host->cmd = cmd;
+
+	writel(cmd->arg, base + AK98MCIARGUMENT);
+	writel(readl(base + AK98MCIMASK) | MCI_CMDIRQMASKS, base + AK98MCIMASK);
+	PK("ENABLE CMD IRQ\n");
+	PK("irqmask: 0x%08x\n", readl(base+AK98MCIMASK));
+	writel(c, base + AK98MCICOMMAND);
+}
+
+
+#ifdef AKMCI_INNERFIFO_PIO
+static void ak98_sdio_pio_irq(struct ak98_mci_host *host, unsigned int status)
+{
+	u32 *p;
+
+	if (host->sg_ptr == NULL) {
+		printk("%s ERROR\n", __func__);
+		return;
+	}
+
+	p = sg_virt(host->sg_ptr) + host->sg_off;
+
+	if ((status & MCI_FIFOFULL) && (status & MCI_RXACTIVE)) {
+		*p = readl(host->base + AK88MCIFIFO);
+		PK("read: 0x%08x\n", *p);
+	} else if ((status & MCI_FIFOEMPTY) && (status & MCI_TXACTIVE)) {
+		writel(*p, host->base + AK88MCIFIFO);
+		PK("write: 0x%08x\n", *p);
+	} else {
+		return;
+	}
+
+	host->data_xfered += 4;
+	host->size -= 4;
+
+	host->sg_off += 4;
+	if (host->sg_off >= host->sg_ptr->length) {
+		ak98_mci_next_sg(host);
+	}
+}
+#endif
+
+/**
+ * @brief  enable or disable sdio interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of sd controller.
+ * @param [in] enable  1: enable; 0: disable.
+ * @return void.
+ */
+
+void ak98_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+    struct ak98_mci_host *host = mmc_priv(mmc);	
+    unsigned reg1,reg2;
+    unsigned long flags;
+    
+    spin_lock_irqsave(&host->lock, flags); 
+
+    reg1 = readl(host->base + AK98MCIMASK);
+    reg2 = readl(host->base + AK98SDIOINTRCTR);
+    
+    if (enable)
+    {
+        reg1 |= SDIO_INTR_ENABLE; 
+        reg2 |= SDIO_INTR_CTR_ENABLE;
+    }
+    else
+    {
+        reg1 &= ~SDIO_INTR_ENABLE;
+        reg2 &= ~SDIO_INTR_CTR_ENABLE;
+    }
+    
+    writel(reg2, host->base + AK98SDIOINTRCTR);    
+    writel(reg1, host->base + AK98MCIMASK);
+    spin_unlock_irqrestore(&host->lock, flags); 
+}
+
+/**
+ * @brief  data handle in sdio interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *data information of data transmitting.
+ * @return void.
+ */
+
+static void ak98_sdio_data_irq(struct ak98_mci_host *host, struct mmc_data *data,
+		  unsigned int status)
+{
+	if (status & MCI_DATABLOCKEND) {
+		PK("BLOCKEND\n");
+#ifdef AKMCI_L2FIFO_PIO
+        if (data->flags & MMC_DATA_WRITE)
+        {
+            ak98_l2_clr_status(l2_sdio_bufid);
+        }
+		if (host->size > 0)
+			mci_xfer(host);
+		
+#endif
+	}
+	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT)) {
+		PK1("DATA ERROR: 0x%08x\n", status);
+
+		if (status & MCI_DATACRCFAIL )
+			data->error = -EILSEQ;
+		else if (status & MCI_DATATIMEOUT)
+			data->error = -ETIMEDOUT;
+		status |= MCI_DATAEND;
+		/*
+		 * We hit an error condition.  Ensure that any data
+		 * partially written to a page is properly coherent.
+		 */
+		if (host->sg_len && data->flags & MMC_DATA_READ)
+			flush_dcache_page(sg_page(host->sg_ptr));
+	}
+	if (status & MCI_DATAEND) {
+		ak98_sdio_stop_data(host);
+
+		//dump_data(data);
+
+		if (!data->stop) {
+			ak98_sdio_request_end(host, data->mrq);
+		} else {
+			ak98_sdio_start_command(host, data->stop);
+		}
+	}
+}
+
+/**
+ * @brief  cmd handle in sd interrupt.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *host information of sd controller.
+ * @param [in] *cmd information of cmd sended.
+  *@param [in] *status the status of sd controller.
+ * @return void.
+ */
+
+static void ak98_sdio_cmd_irq(struct ak98_mci_host *host, struct mmc_command *cmd,
+		 unsigned int status)
+{
+	void __iomem *base = host->base;
+
+	PK("+%s\n", __func__);
+	host->cmd = NULL;
+
+	cmd->resp[0] = readl(base + AK98MCIRESPONSE0);
+	cmd->resp[1] = readl(base + AK98MCIRESPONSE1);
+	cmd->resp[2] = readl(base + AK98MCIRESPONSE2);
+	cmd->resp[3] = readl(base + AK98MCIRESPONSE3);
+    PK("base=0x%x,resp[0]=0x%x, [1]=0x%x,resp[2]=0x%x, [3]=0x%x",base,cmd->resp[0],
+                    cmd->resp[1],cmd->resp[2],cmd->resp[3]);
+	if (status & MCI_RESPTIMEOUT) {
+		cmd->error = -ETIMEDOUT;
+	} else if (status & MCI_RESPCRCFAIL && cmd->flags & MMC_RSP_CRC) {
+		cmd->error = -EILSEQ;
+	}
+
+	writel(readl(base + AK98MCIMASK) & ~MCI_CMDIRQMASKS, base + AK98MCIMASK);
+	PK("DISABLE CMD IRQ\n");
+
+	if (!cmd->data || cmd->error) {
+		if (host->data)
+			ak98_sdio_stop_data(host);
+		ak98_sdio_request_end(host, cmd->mrq);
+	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
+		ak98_sdio_start_data(host, cmd->data);
+	}
+	PK("-%s\n", __func__);
+}
+
+/*
+ * Handle completion of command and data transfers.
+ */
+static irqreturn_t ak98_sdio_irq(int irq, void *dev_id)
+{
+	struct ak98_mci_host *host = dev_id;
+	u32 status;
+	int ret = 0;
+
+	PK("+%s ", __func__);
+
+	spin_lock(&host->lock);
+
+	do {
+		struct mmc_command *cmd;
+		struct mmc_data *data;
+
+		status = readl(host->base + AK98MCISTATUS);
+
+		PK(" status= 0x%08x\n", status);
+
+#ifdef AKMCI_INNERFIFO_PIO
+		if (host->data)
+			ak98_sdio_pio_irq(host, status);
+#endif
+
+		cmd = host->cmd;
+		if (status & (MCI_RESPCRCFAIL|MCI_RESPTIMEOUT|MCI_CMDSENT|MCI_RESPEND)
+		    && cmd)
+			ak98_sdio_cmd_irq(host, cmd, status);
+
+		data = host->data;
+		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_DATAEND|MCI_DATABLOCKEND|MCI_STARTBIT_ERR)
+		    && data)
+			ak98_sdio_data_irq(host, data, status);
+
+		if (status & MCI_SDIOINT) {
+		    /*must disable sdio irq ,than read status to clear the sdio status,
+                        else sdio irq will come again.
+		       */
+		    ak98_enable_sdio_irq(host->mmc,0);
+		    readl(host->base + AK98MCISTATUS);		    
+			mmc_signal_sdio_irq(host->mmc);
+		}
+
+		ret = 1;
+	} while (0);
+
+	spin_unlock(&host->lock);
+
+	PK("-%s, irqmask: 0x%08x\n", __func__, readl(host->base + AK98MCIMASK));
+
+	return IRQ_RETVAL(ret);
+}
+
+/**
+ * @brief  detect sdio card's level type .
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] data  getting the information of sd host.
+ * @return void.
+ */
+
+static void ak98_sdio_detect_change(unsigned long data)
+{
+	struct ak98_mci_host *host = (struct ak98_mci_host *)data;
+
+	PK("%s\n", __func__);
+
+	mmc_detect_change(host->mmc, 0);
+
+	if (host->irq_cd_type == IRQ_TYPE_LEVEL_LOW) {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_HIGH;
+	} else {
+		host->irq_cd_type = IRQ_TYPE_LEVEL_LOW;
+	}
+	set_irq_type(host->irq_cd, host->irq_cd_type);
+	enable_irq(host->irq_cd);
+}
+
+static irqreturn_t ak98_sdio_card_detect_irq(int irq, void *dev)
+{
+	struct ak98_mci_host *host = dev;
+
+	PK("%s##################\n", __func__);
+
+	disable_irq_nosync(irq);
+	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(400));
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * @brief   detect the sdio card whether or not is in.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host ,getting the sdio detect gpio.
+ * @return int.
+ * @retal 1 sdio card is in ;0 sdio card is not in
+ */
+
+static int ak98_sdio_get_cd(struct mmc_host *mmc)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);	
+
+	if (host->gpio_cd == -ENOSYS)
+		return -ENOSYS;	
+		
+	//printk("%s: %i\n", __func__, ak98_gpio_getpin(host->gpio_cd) == 0);
+	return (ak98_gpio_getpin(host->gpio_cd) == 0);
+}
+
+/**
+ * @brief   detect the sdio card writing protection.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host ,getting the sdio detect gpio.
+ * @return int.
+ * @retal 1 sdio card writing protected ;0 sdio card writing is not protected
+ */
+
+static int ak98_sdio_get_ro(struct mmc_host *mmc) 
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);
+
+	if (host->gpio_wp == -ENOSYS)
+		return -ENOSYS;
+
+	//printk("%s: %i\n", __func__, ak98_gpio_getpin(host->gpio_wp));
+	return (ak98_gpio_getpin(host->gpio_wp) == 0);
+}
+
+static void ak98sdio_set_clk(struct ak98_mci_host *host, struct mmc_ios *ios)
+{
+	unsigned int regval;
+	int div;
+
+	PKCLK("%s\n",__func__); 
+	
+	if (ios->clock == 0) 
+	{
+		regval = readl(host->base + AK98MCICLOCK);
+		regval &= ~MCI_CLK_ENABLE;
+		host->bus_clkrate = 0;
+		writel(regval, host->base + AK98MCICLOCK);		
+	} 
+	else 
+	{
+		regval = readl(host->base + AK98MCICLOCK);
+		regval |= MCI_CLK_ENABLE;
+		regval &= ~0xffff; /* clear clk div */
+		div = host->asic_clkrate/ios->clock - 2;
+		PKCLK("host->asic_clkrate = %ld\n",host->asic_clkrate); 
+		PKCLK("ios->clock = %d\n",ios->clock); 
+		printk("clk_div: %d\n", div);
+		
+		regval |= MMC_CLK_DIVL(div/2) | MMC_CLK_DIVH(div/2);			
+		host->bus_clkrate = host->asic_clkrate / (div + 2);
+		writel(regval, host->base + AK98MCICLOCK);		
+	}
+}
+
+/**
+ * @brief   set sdio bus mode,bus width,clock.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host .
+ * @param [in] *ios information of sd interface .
+ * @return void.
+ */
+
+static void ak98_sdio_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);
+
+	hydbg("bus_mode=%d,bus_width=%d\n", ios->bus_mode, ios->bus_width);
+	
+	/* ak98 (and SD spec) don't support MMC_BUSMODE_OPENDRAIN */
+	host->bus_mode = ios->bus_mode;
+	host->bus_width = ios->bus_width;
+	//printk("%ubits(%u); ", (unsigned)1 >> (host->bus_width), host->bus_width);
+
+	/* we can't control external power supply unit */
+	switch (ios->power_mode) {
+	case MMC_POWER_UP:
+		PK("MMC_POWER_UP; ");
+		break;
+	case MMC_POWER_ON:
+		PK("MMC_POWER_ON; ");
+		break;
+	case MMC_POWER_OFF:
+		PK("MMC_POWER_OFF; ");
+		break;
+	}
+	
+    ak98_group_config(ePIN_AS_SDIO); 
+    
+	if (ios->clock != host->bus_clkrate) 
+	{
+	#ifdef CONFIG_CPU_FREQ
+		down(&host->freq_lock);
+	#endif
+		
+		ak98sdio_set_clk(host, &mmc->ios);
+
+	#ifdef CONFIG_CPU_FREQ
+		 up(&host->freq_lock);
+	#endif
+		
+	}
+	
+	/* no matter high-speed mode or not, ak88 mci use the same timing */   
+
+	//printk("ios->clock(%dkhz), host->bus_clkrate(%lukhz), host->asic_clkrate(%lumhz), MMC_CLK_CTRL(0x%08x)\n",
+	     //  ios->clock/1000, host->bus_clkrate/1000, host->asic_clkrate/1000000, readl(host->base + AK98MCICLOCK));
+}
+
+/**
+ * @brief   reset sdio card clock.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] void .
+ * @return void.
+ */
+
+static void ak98_sdio_reset(void)
+{
+    rCLK_CON2 |= (0x1 << 19);
+    rCLK_CON2 &= ~(0x1 << 19);
+}
+
+/**
+ * @brief   send a request, starting data or command.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *mmc information of host .
+ * @return void.
+ */
+
+static void ak98_sdio_send_request(struct mmc_host *mmc)
+{
+    struct ak98_mci_host *host = mmc_priv(mmc); 
+    struct mmc_request *mrq = host->mrq;	
+    unsigned long flags;    
+
+#ifdef CONFIG_CPU_FREQ
+	 /*
+		* need not to acquire the freq_lock in interrupt.
+	*/
+	 if (!in_interrupt()) 
+	 {					   
+		 down(&host->freq_lock);
+		 
+	 }	  
+#endif
+    
+
+    if(mrq->data || mrq->cmd->data)
+    {
+        l2_sdio_bufid = ak98_l2_alloc(ADDR_SDIO);
+        if (BUF_NULL == l2_sdio_bufid)
+        {
+            printk("L2 buffer malloc fail!\n");
+            BUG();
+        }
+        ak98_l2_clr_status(l2_sdio_bufid);
+    }
+    
+    spin_lock_irqsave(&host->lock, flags);  
+    
+	if (mrq->data && (mrq->data->flags & MMC_DATA_READ))
+		ak98_sdio_start_data(host, mrq->data);
+
+	ak98_sdio_start_command(host, mrq->cmd);
+
+	spin_unlock_irqrestore(&host->lock, flags);    
+
+}
+
+static void ak98_sdio_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+	struct ak98_mci_host *host = mmc_priv(mmc);	
+
+	PK1("%s: CMD%i\n", __func__, mrq->cmd->opcode);
+	
+	host->mrq = mrq;	
+
+    if (ak98_sdio_get_cd(mmc) == 0)
+    {
+        printk("%s: no medium present\n", __func__);
+		host->mrq->cmd->error = -ENOMEDIUM;
+		mmc_request_done(mmc, mrq);        
+    }
+    else
+    {
+        ak98_sdio_send_request(mmc); 
+    }	
+	
+}
+
+/**
+ * register the function of sd driver.
+ * 
+ */
+
+static const struct mmc_host_ops ak98_mci_ops = {
+	.request	= ak98_sdio_request,
+	.set_ios	= ak98_sdio_set_ios,
+	.get_ro		= ak98_sdio_get_ro,
+	.get_cd		= ak98_sdio_get_cd,
+	.enable_sdio_irq = ak98_enable_sdio_irq,
+
+};
+
+// difine change cpu freq
+#ifdef CONFIG_CPU_FREQ
+
+static int ak98sdio_cpufreq_transition(struct notifier_block *nb,
+				     unsigned long val, void *data)
+{
+	struct ak98_mci_host *host;
+	struct mmc_host *mmc;
+	unsigned long newclk;
+	unsigned long flags;
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+	host = container_of(nb, struct ak98_mci_host, freq_transition);
+	
+	PKCLK("%s\n",__func__);	
+	PKCLK("%s(): in_interrupt()=%ld\n", __func__, in_interrupt());
+	PKCLK("ak98_get_asic_clk = %ld\n",ak98_get_asic_clk());	
+	PKCLK("freqs->new_cpufreq.asic_clk = %d\n",
+		  freqs->new_cpufreq.asic_clk);	
+		  
+	mmc = host->mmc;
+	newclk = freqs->new_cpufreq.asic_clk;
+	if ((val == CPUFREQ_PRECHANGE && newclk > host->asic_clkrate) 
+		|| (val == CPUFREQ_POSTCHANGE && newclk < host->asic_clkrate)) 
+	{
+
+		if (mmc->ios.power_mode != MMC_POWER_OFF &&
+			mmc->ios.clock != 0)
+		{		
+			PKCLK("%s(): preempt_count()=%d\n",
+				__func__, preempt_count());
+				
+			down(&host->freq_lock);
+			
+			spin_lock_irqsave(&mmc->lock, flags);
+		
+			host->asic_clkrate = newclk;
+			PKCLK("AK98MCICLOCK1 = %d\n",readl(host->base + AK98MCICLOCK));	
+			ak98sdio_set_clk(host, &mmc->ios);
+			PKCLK("AK98MCICLOCK2 = %d\n",readl(host->base + AK98MCICLOCK));	
+			
+			spin_unlock_irqrestore(&mmc->lock, flags);
+
+			up(&host->freq_lock);
+		}		
+
+	}
+
+	return NOTIFY_DONE;
+}
+
+static inline int ak98sdio_cpufreq_register(struct ak98_mci_host *host)
+{
+	// use for requst and cpufreq
+	init_MUTEX(&host->freq_lock);
+	
+	host->freq_transition.notifier_call = ak98sdio_cpufreq_transition;
+
+	return cpufreq_register_notifier(&host->freq_transition,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void ak98sdio_cpufreq_deregister(struct ak98_mci_host *host)
+{
+	cpufreq_unregister_notifier(&host->freq_transition,
+				    CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int ak98sdio_cpufreq_register(struct ak98_mci_host *host)
+{
+	return 0;
+}
+
+static inline void ak98sdio_cpufreq_deregister(struct ak98_mci_host *host)
+{
+}
+#endif
+
+// difine change cpu freq end
+
+
+
+#if 0
+static void ak98_mci_check_status(unsigned long data)
+{
+	struct ak98_mci_host *host = (struct ak98_mci_host *)data;
+	unsigned int status = ak98_mci_get_cd(host->mmc);
+
+	if (status ^ host->oldstat)
+		mmc_detect_change(host->mmc, 0);
+
+	host->oldstat = status;
+	mod_timer(&host->timer, jiffies + HZ);
+}
+#endif
+
+/**
+ * @brief   sdio driver probe and init.
+ * 
+ * @author Hanyang
+ * @date 2011-05-10
+ * @param [in] *pdev information of platform device ,getting the sd driver resource .
+ * @return int.
+ * @retval -EINVAL no platform data , fail;
+ * @retval -EBUSY  requset mem  fail;
+ * @retval -ENOMEM  alloc mem fail;
+ */
+
+static int __devinit ak98_sdio_probe(struct platform_device *pdev)
+{
+	struct ak98_mci_platform_data *plat = pdev->dev.platform_data;
+	struct ak98_mci_host *host;
+	struct mmc_host *mmc;
+	struct resource *res;
+	int irq;
+	int ret;
+
+	/* must have platform data */
+	if (!plat) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	PK("%s\n", __func__);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq = platform_get_irq(pdev, 0);
+
+	PK("res: %x, %u", res->start, resource_size(res));
+	res = request_mem_region(res->start, resource_size(res), DRIVER_NAME);
+	if (!res) {
+		ret = -EBUSY;
+		goto out;
+	}
+	PK("res: %x, %u\n", res->start, resource_size(res));
+
+	mmc = mmc_alloc_host(sizeof(struct ak98_mci_host), &pdev->dev);
+	if (!mmc) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	host = mmc_priv(mmc);
+	host->mmc = mmc;
+
+	host->gpio_wp = -ENOSYS;
+	host->gpio_cd = -ENOSYS;
+
+    ak98_sdio_reset();
+    host->clk = clk_get(&pdev->dev, "sdio_clk");
+    if (IS_ERR(host->clk)) {
+        ret = PTR_ERR(host->clk);
+        host->clk = NULL;
+        goto host_free;
+    }      
+
+	ret = clk_enable(host->clk);
+	if (ret)
+		goto clk_free;
+
+	host->plat = plat;
+	host->asic_clkrate = ak98_get_asic_clk();
+	
+
+	host->base = ioremap(res->start, resource_size(res));
+	if (!host->base) {
+		ret = -ENOMEM;
+		goto clk_disable;
+	} 
+    PK("asic_clkrate: %luhz,host->base=0x%x\n", host->asic_clkrate,host->base);
+	mmc->ops = &ak98_mci_ops;
+	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+	mmc->caps = MMC_CAP_4_BIT_DATA;
+#if 0
+	mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+#endif 
+	mmc->caps |= MMC_CAP_SDIO_IRQ;
+
+//	mmc->caps |= MMC_CAP_NEEDS_POLL;
+	mmc->f_min = host->asic_clkrate / (255+1 + 255+1);
+	mmc->f_max = host->asic_clkrate / (0+1 + 0+1);
+	mmc->f_max = mmc->f_max < fmax ? mmc->f_max : fmax;
+
+	/*
+	 * We can do SGIO
+	 */
+	mmc->max_hw_segs = 16;
+	mmc->max_phys_segs = NR_SG;
+
+	/*
+	 * Since we only have a 16-bit data length register, we must
+	 * ensure that we don't exceed 2^16-1 bytes in a single request.
+	 */
+	mmc->max_req_size = 65535;
+
+	/*
+	 * Set the maximum segment size.  Since we aren't doing DMA
+	 * (yet) we are only limited by the data length register.
+	 */
+	mmc->max_seg_size = mmc->max_req_size;
+
+#if 0
+	/*
+	 * Block size can be up to 2048 bytes, but must be a power of two.
+	 */
+	mmc->max_blk_size = 2048;
+#else
+	/* as l2 fifo limit to 512 bytes */
+	mmc->max_blk_size = 512;
+#endif
+
+	/*
+	 * No limit on the number of blocks transferred.
+	 */
+	mmc->max_blk_count = mmc->max_req_size;
+
+	spin_lock_init(&host->lock);
+	
+    ak98_group_config(ePIN_AS_SDIO); 
+	writel(MCI_ENABLE|MCI_FAIL_TRIGGER, host->base + AK98MCICLOCK);	
+    PK("%s: MCICLOCK: 0x%08x\n", __func__, readl(host->base + AK98MCICLOCK));
+    
+	writel(0, host->base + AK98MCIMASK);
+	
+	PK("request irq %i\n", irq);
+	ret = request_irq(irq, ak98_sdio_irq, IRQF_DISABLED, DRIVER_NAME " (cmd)", host);
+	if (ret)
+		goto unmap;
+		
+	host->irq_mci = irq;
+	if(plat->gpio_cd >= 0)
+	{
+    	host->gpio_cd = plat->gpio_cd;	
+    	ak98_gpio_cfgpin(host->gpio_cd, AK98_GPIO_DIR_INPUT);
+    	ak98_gpio_pulldown(host->gpio_cd,AK98_PULLDOWN_DISABLE);
+        ak98_gpio_pullup(host->gpio_cd, AK98_PULLUP_ENABLE);  
+        
+        setup_timer(&host->detect_timer, ak98_sdio_detect_change,
+                    (unsigned long)host);
+                    
+        irq = ak98_gpio_to_irq(host->gpio_cd);    
+        ret = request_irq(irq, ak98_sdio_card_detect_irq,
+                  IRQF_DISABLED,
+                  DRIVER_NAME " cd", host);
+        printk("request gpio irq ret = %d, irq=%d", ret, irq);
+        if (ret)
+            goto irq_free;
+        host->irq_cd = irq;
+        host->irq_cd_type = IRQ_TYPE_LEVEL_LOW; 
+    }
+    
+    if(plat->gpio_wp >= 0)
+    {
+        host->gpio_wp = plat->gpio_wp;	
+    	ak98_gpio_cfgpin(host->gpio_wp, AK98_GPIO_DIR_INPUT);
+    	ak98_gpio_pullup(host->gpio_wp, AK98_PULLUP_ENABLE);
+    	ak98_gpio_pulldown(host->gpio_wp,AK98_PULLDOWN_DISABLE);
+    }
+	
+	platform_set_drvdata(pdev, mmc);
+
+	ret = ak98sdio_cpufreq_register(host);
+	if (ret) {
+		goto irq_free;
+	}
+
+	ret = mmc_add_host(mmc);
+	if (ret) {
+		goto cpufreq_free;
+	}
+
+	PK(KERN_INFO "%s: ak98MCI at 0x%016llx irq %d\n",
+		mmc_hostname(mmc), (unsigned long long)res->start,
+		host->irq_mci);
+
+	return 0;
+
+ cpufreq_free:
+	 PK("ERR cpufreq_free\n");
+	 ak98sdio_cpufreq_deregister(host);
+
+ irq_free:
+	PK("ERR irq_free\n");
+	free_irq(host->irq_mci, host);
+ unmap:
+	PK("ERR unmap\n");
+	iounmap(host->base);
+ clk_disable:
+	PK("ERR clk_disable\n");
+	clk_disable(host->clk);
+ clk_free:
+	PK("ERR clk_free\n");
+	clk_put(host->clk);
+ host_free:
+	PK("ERR host_free\n");
+	mmc_free_host(mmc);
+ out:
+	PK("ERR out\n");
+	return ret;
+}
+
+static int __devexit ak98_sdio_remove(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+  
+	platform_set_drvdata(dev, NULL);
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+#if 0
+		del_timer_sync(&host->timer);
+#endif
+
+		ak98sdio_cpufreq_deregister(host);
+
+		mmc_remove_host(mmc);
+
+		writel(0, host->base + AK98MCIMASK);
+
+		writel(0, host->base + AK98MCICOMMAND);
+		writel(0, host->base + AK98MCIDATACTRL);
+
+#if 0
+		if (gpio_is_valid(host->gpio_cd))
+			free_irq(host->irq_cd, host);
+		free_irq(host->irq_mci, host);
+
+		if (host->gpio_wp != -ENOSYS)
+			gpio_free(host->gpio_wp);
+		if (host->gpio_cd != -ENOSYS)
+			gpio_free(host->gpio_cd);
+#else
+        if (host->irq_cd > 0)
+        {
+		    free_irq(host->irq_cd, host);
+		}
+		free_irq(host->irq_mci, host);
+#endif
+
+		iounmap(host->base);
+		clk_disable(host->clk);
+		clk_put(host->clk);
+
+		mmc_free_host(mmc);
+	}
+
+	return 0;
+}
+
+//#ifdef CONFIG_PM
+#if 0
+static int ak98_sdio_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+		ret = mmc_suspend_host(mmc, state);
+		if (ret == 0)
+			writel(0, host->base + AK88MCIMASK0);
+	}
+
+	return ret;
+}
+
+static int ak98_sdio_resume(struct platform_device *dev)
+{
+	struct mmc_host *mmc = platform_get_drvdata(dev);
+	int ret = 0;
+
+	if (mmc) {
+		struct ak98_mci_host *host = mmc_priv(mmc);
+
+		writel(MCI_IRQENABLE, host->base + AK88MCIMASK0);
+
+		ret = mmc_resume_host(mmc);
+	}
+
+	return ret;
+}
+#else
+#define ak98_sdio_suspend	NULL
+#define ak98_sdio_resume	NULL
+#endif
+
+static struct platform_driver ak98_sdio_driver = {
+	.driver		= {
+		.name	= DRIVER_NAME,
+	},
+	.probe		= ak98_sdio_probe,
+	.remove		= __devexit_p(ak98_sdio_remove),
+	.suspend	= ak98_sdio_suspend,
+	.resume		= ak98_sdio_resume,
+};
+
+static int __init ak98_sdio_init(void)
+{
+	printk("%s\n", __func__);
+	return platform_driver_register(&ak98_sdio_driver);
+}
+
+static void __exit ak98_sdio_exit(void)
+{
+	platform_driver_unregister(&ak98_sdio_driver);
+}
+
+module_init(ak98_sdio_init);
+module_exit(ak98_sdio_exit);
+
+MODULE_DESCRIPTION("Anyka AK98 MMC/SD/SDIO Interface driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 2fda0b61524..d3630339d47 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -1,5 +1,12 @@
 # drivers/mtd/nand/Kconfig
 
+config MTD_NAND_IDS
+	tristate "Include chip ids for known NAND devices."
+	depends on MTD
+	help
+	  Useful for NAND drivers that do not use the NAND subsystem but
+	  still like to take advantage of the known chip information.
+
 menuconfig MTD_NAND
 	tristate "NAND Device Support"
 	depends on MTD
@@ -103,9 +110,6 @@ config MTD_NAND_TS7250
 	help
 	  Support for NAND flash on Technologic Systems TS-7250 platform.
 
-config MTD_NAND_IDS
-	tristate
-
 config MTD_NAND_AU1550
 	tristate "Au1550/1200 NAND support"
 	depends on SOC_AU1200 || SOC_AU1550
@@ -482,4 +486,48 @@ config MTD_NAND_W90P910
 	  This enables the driver for the NAND Flash on evaluation board based
 	  on w90p910.
 
+config MTD_NAND_AK88
+	tristate "NAND Flash support for AK88 SoC"
+	depends on ARCH_AK88 && MTD_NAND
+	help
+	  This enables the NAND flash controller on the AK88 SoCs.
+
+	  No board specific support is done by this driver, each board
+	  must advertise a platform_device for the driver to attach.
+	  
+config MTD_NAND_AK98
+	tristate "NAND Flash support for AK98 SoC"
+	depends on ARCH_AK98 && MTD_NAND
+	help
+	  This enables the NAND flash controller on the AK98 SoCs.
+
+	  No board specific support is done by this driver, each board
+	  must advertise a platform_device for the driver to attach.
+
+config MTD_NAND_DMA_MODE
+	tristate "ANYKA Nand Flash DMA mode"
+	depends on MTD_NAND_AK88 || MTD_NAND_AK98
+	default y
+	help
+          This enable dma mode for AK880x nandflash driver.
+          
+
+config MTD_DOWNLOAD_MODE
+	tristate "ANYKA Nand MTD Download Mode"
+	depends on MTD_NAND_AK88 || MTD_NAND_AK98
+	help 
+	   This enables download mode, don't mount mtd partitions.
+
+config MTD_NAND_AK88_DEBUG
+	tristate "AK880x debug support"
+	depends on MTD_NAND_AK88
+	help
+	  This enables debug support for AK880x nandflash driver.
+
+config MTD_NAND_TEST
+	tristate "NAND Test support"
+	depends on MTD_NAND_AK98
+	default n
+	help
+	  This enables support for nand erase test and lost power test.
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6950d3dabf1..cb4b7e3eb85 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -42,5 +42,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
 obj-$(CONFIG_MTD_NAND_W90P910)		+= w90p910_nand.o
 obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
+obj-$(CONFIG_MTD_NAND_AK88)		+= ak88-nand/
+obj-$(CONFIG_MTD_NAND_AK98)		+= ak98-nand/
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/ak88-nand/Makefile b/drivers/mtd/nand/ak88-nand/Makefile
new file mode 100644
index 00000000000..52694c403e4
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_MTD_NAND_AK88) += ak880x-nand.o
+	ak880x-nand-objs := ak880x.o wrap_nand.o nand_control.o communicate.o ak880x-nfc.o
+
+obj-$(CONFIG_MTD_DOWNLOAD_MODE) += nand_char.o
diff --git a/drivers/mtd/nand/ak88-nand/ak880x-nand.h b/drivers/mtd/nand/ak88-nand/ak880x-nand.h
new file mode 100644
index 00000000000..3ae314e5ec8
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/ak880x-nand.h
@@ -0,0 +1,168 @@
+/*----------------------------------------------------------------
+ *Copyright (c) 2004,Anyka(GuangZhou) Software Technology Co.,Ltd.                            
+ *All rights reserved.                            
+ *                             
+ *File name:                            
+ *        ak3221m-nand.h
+ *Brief:                            
+ *        nandflash driver.
+ *author:                            
+ *        liang_dongcai
+ *version:                            
+ *        0.0.1
+ *history:    
+ -----------------------------------------------------------------*/
+
+#ifndef _AK7801_NAND_H
+#define _AK7801_NAND_H
+
+//#include <asm/sizes.h>
+
+#define NANDDRV_SPEED_LOW		0
+#define NANDDRV_SPEED_MIDDLE		1
+#define NANDDRV_SPEED_HIGH		2
+#define NANDDRV_SPEED_SPEC		3
+
+#define COPYBACK_NONE			0
+#define COPYBACK_SUPPORT		1
+//*******************************************
+//this is define of our chip nandflash driver information
+// AK3223 NFC's FIFO size is 512 bytes
+//this is 3221 chip controller
+#define CHIP_NFC_7801
+//#define CHIP_NFC_3229
+//#define CHIP_NFC_3310
+
+//**************************************************************
+//all  of this define is for 3221 nandflash controller
+//**************************************************************
+#ifdef CHIP_NFC_7801
+
+#define  PHY_ERR_FLAG           0
+//basic save information
+#define NFC_FIFO_SIZE           512
+#define NFC_LOG_PAGE_SIZE       512
+#define NFC_LOG_SPARE_SIZE      16
+//#define NFC_FS_INFO_OFFSET    522
+#define NFC_FS_INFO_OFFSET      520	//must be 4 multiple
+#define NFC_FS_INFO_SIZE        6
+#define NFC_SUPPORT_CHIPNUM     4
+
+#define BASIC_DLYCNT               0x30
+
+//#######enddefine of ecc encode and decode ################
+
+#endif				//CHIP_NFC_3221
+
+//********************************************************************************//
+//nandflash information of one chip
+//********************************************************************************//
+//physic information
+#define NFLASH_PAGE_SIZE            (Nand_SysInfo.phy_page_size)
+#define NFLASH_BLOCK_NUM            (Nand_SysInfo.total_blk_num)
+
+//log information
+#define NFLASH_LOGPAGE_NUM          (Nand_SysInfo.total_logpage_num)
+
+#ifdef POP_NF_HARDWARE
+
+#define NFLASH_LOGPAGE_SIZE          512
+#define NFLASH_LOGSPARE_SIZE         16
+#define NFLASH_PHYPAGES_PER_BLOCK    64
+#define NFLASH_LOG_PER_PHY           4
+#else
+
+#define NFLASH_LOGPAGE_SIZE          (Nand_SysInfo.log_page_size)
+#define NFLASH_LOGSPARE_SIZE         (Nand_SysInfo.log_spare_size)
+#define NFLASH_PHYPAGES_PER_BLOCK    chipInfo.phy_page_per_blk
+#define NFLASH_LOG_PER_PHY           Nand_SysInfo.Nand_LogPerPhy
+#endif				/* POP_NF_HARDWARE */
+
+// CRC begin at second bit
+#define CRC_TYPE_START_BIT    2
+
+// ECC flag bit
+#define RS1_NO_ERR_BIT                (1 << 11)
+#define RS2_NO_ERR_BIT                (1 << 12)
+#define BCH_NO_ERR_BIT                (1 << 13)
+
+#define RS1_CANT_CORRECT_BIT          (1 << 5)
+#define RS2_CANT_CORRECT_BIT          (1 << 7)
+#define BCH_CANT_CORRECT_BIT          (1 << 9)
+
+#define RS1_CORRECT_END_BIT           (1 << 6)
+#define RS2_CORRECT_END_BIT           (1 << 8)
+#define BCH_CORRECT_END_BIT           (1 << 10)
+
+// ECC error code( reservd 16 error code)
+/*
+ * function do_ECC_coerr() setting has two valve: 16 or 2
+ *    when do_ECC_coerr() return value >= ECC_CANT_CORRECT, 
+ *        mean error can't correct, don't need execute CRC;
+ *    when do_ECC_coerr() 
+ *        return value < ECC_CANT_CORRECT and >= ECC_NEED_CRC_CHECK,
+ *        mean error has too much, maybe correct, then execute verify.
+ *    when do_ECC_coerr return value == 0, 
+ *        mean no error or had correct already.
+ */
+#define ECC_NEED_CRC_CHECK          (2)
+#define ECC_CANT_CORRECT            (1 << 4)
+#define RS1_CANT_CORRECT            (1 << 4)
+#define RS2_CANT_CORRECT            (1 << 5)
+#define BCH_CANT_CORRECT            (1 << 6)
+
+#define RS1_COERR                    1
+#define RS2_COERR                    2
+
+// AK3220 support CRC type list
+typedef enum {
+	CRC_TYPE_CRC8 = 0,
+	CRC_TYPE_CRC12,
+	CRC_TYPE_CRC16,
+	CRC_TYPE_CRC24,
+	CRC_TYPE_CRC32
+} T_AK3220_CRC_TYPE;
+
+#define ERROR_CHIP_ID			0x00000000
+#define NFLASH_READ_ID			0x90
+
+//custom nandflash bit information
+//this byte is just for expand out driver
+//bit 0,if nandflash no cache, set this bit,driver would avoid cache control
+//bit 1,if nandflash command set is other,set this bit dirver would try to find this chips command set
+//bit 2,if nandflash use 16 bit connect,set this bit
+//bit 3,if pin R/B not connect,set this bit
+//bit 4,bit 5,bit 6,bit 7,reserved for other status
+
+#define  UNMAP_BLK_PER_GROUP		16
+
+//status register bit
+#define NFLASH_PROGRAM_SUCCESS		0x01	//bit 0
+#define NFLASH_HANDLE_READY		0x40	//bit 6
+
+/** @{@name Error Code of nandflash
+ *  define the error code of nandflash
+ */
+#define NF_TIMEOUT			(16)
+#define NF_SUCCESS			(1)
+#define NF_FAIL				(0)
+#define NF_ERR_ECC			(0)
+#define NF_ERR_PROGRAM			(-2)
+#define NF_ERR_ERASE			(-3)
+#define NF_ERR_INIT			(-4)
+#define NF_ERR_DEV			(-5)
+#define NF_ERR_LAST			(-6)
+#define NFLASH_RESET			0xff
+
+#define NFLASH_FRAME_PROGRAM0		0x80
+#define NFLASH_FRAME_PROGRAM1		0x10
+
+#define NAND_SELCHIP_NONE		0x0
+#define NAND_SELCHIP_NEED		0x1
+#define NAND_SELCHIP_RESCALE		0x2
+
+#define NAND_READBBT_TIMEOUT_MAX 	3
+
+#define ERROR_NAND_ID			0
+
+#endif
diff --git a/drivers/mtd/nand/ak88-nand/ak880x-nfc.c b/drivers/mtd/nand/ak88-nand/ak880x-nfc.c
new file mode 100644
index 00000000000..9c422f40174
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/ak880x-nfc.c
@@ -0,0 +1,1344 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+
+#include <mach/nand.h>
+#include <mach/map.h>
+
+//#include "ak880x-nand.h"
+#include "nand_flash_drv.h"
+#include "communicate.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define WRITE_BUF	GLOBE_BUF5
+#define READ_BUF	GLOBE_BUF4
+
+/* NF controller */
+#define FLASH_CTRL_REG0     (AK88_VA_NFCTRL+0x100)
+
+#define FLASH_CTRL_REG20    (FLASH_CTRL_REG0 + 0x50)
+#define FLASH_CTRL_REG21    (FLASH_CTRL_REG0 + 0x54)
+#define FLASH_CTRL_REG22    (FLASH_CTRL_REG0 + 0x58)
+#define FLASH_CTRL_REG23    (FLASH_CTRL_REG0 + 0x5c)
+#define FLASH_CTRL_REG24    (FLASH_CTRL_REG0 + 0x60)
+
+/* ECC sub-module */
+#define FLASH_ECC_REG0      (AK88_VA_ECCCTRL)
+
+#define ECC_CTL_DEC_RDY_EN      (1<<30)
+#define ECC_CTL_ENC_RDY_EN      (1<<29)
+#define ECC_CTL_END_EN          (1<<28)
+#define ECC_CTL_RESULT_NO_OK    (1<<27)
+#define ECC_CTL_NO_ERR          (1<<26)
+#define ECC_CTL_DEC_RDY         (1<<24)
+#define ECC_CTL_ENC_RDY         (1<<23)
+#define ECC_CTL_MODE0           (0<<22)
+#define ECC_CTL_MODE1           (1<<22)
+#define ECC_CTL_NFC_EN          (1<<20)
+#define ECC_CTL_BYTE_CFG(m)     ((m)<<7)	// bit [19:7]
+#define ECC_CTL_END             (1<<6)
+#define ECC_CTL_LITTLE_ENDIAN       (0<<5)
+#define ECC_CTL_BIG_ENDIAN      (1<<5)
+#define ECC_CTL_ADDR_CLR        (1<<4)
+#define ECC_CTL_START           (1<<3)
+#define ECC_CTL_DIR_READ        (0<<2)
+#define ECC_CTL_DIR_WRITE       (1<<2)
+#define ECC_CTL_DEC_EN          (1<<1)
+#define ECC_CTL_ENC_EN          (1<<0)
+
+/* *************** command sequece configuration define ************* */
+
+/* command cycle's configure:
+ *       CMD_END=X, ALE=0, CLE=1, CNT_EN=0,  (BIT[0:3])
+ *       REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define COMMAND_CYCLES_CONF     0x64
+
+/* address cycle's:
+ *       CMD_END=X, ALE=1, CLE=0, CNT_EN=0,  (BIT[0:3])
+ *       REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define ADDRESS_CYCLES_CONF     0x62
+
+/*  read data cycle's:
+ *       CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])
+ *       REN=1, WEN=0, CMD_EN=0, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define READ_DATA_CONF          0x118
+
+/*  write data cycle's:
+ *       CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])
+ *       REN=0, WEN=1, CMD_EN=0, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define WRITE_DATA_CONF         0x128
+
+/* read command status's:(example: read ID, status, 隙暺�æ�…擂掀隤•æ’…曇…”è��ç’‡¢‡¬?)
+ *       CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])
+ *       REN=1, WEN=0, CMD_EN=1, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define READ_CMD_CONF           0x58
+#define READ_INFO_CONF          0x58
+
+/* wait the rising edge of R/B line:
+ *       CMD_END=X, ALE=0, CLE=0, CNT_EN=0,  (BIT[0:3])
+ *       REN=0, WEN=0, CMD_EN=0, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=0, RBN_EN=1, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define WAIT_JUMP_CONF          (1 << 9)
+
+/* wait time (1024 ASIC cycles):
+ *       CMD_END=X, ALE=0, CLE=0, CNT_EN=0,  (BIT[0:3])
+ *       REN=0, WEN=0, CMD_EN=0, STAFF_EN=0, (BIT[4:7])
+ *       DAT_EN=0, RBN_EN=1, CMD_WAIT=0,     (BIT[8:10])
+ */
+#define DELAY_CNT_CONF          (1 << 10)
+
+/* last command's bit0 set to 1 */
+#define LAST_CMD_FLAG           (1 << 0)
+
+/* ************** end command sequece configuration define ************/
+
+/* æ��æ’–�FLASH1~FLASH4(è�–�憭”銵„ç�å…蜈‡æ’œˆ1):
+ *       0: CE1 active;
+ *       1: CE2 active;
+ *       2: CE3 active;
+ *       3: CE4 active;
+ */
+#define FLASH_CE_VALID      0	// (æ“–œè�å–ç•¥…ã„�è�–‰éŠçš�”€¥��æ’–�èŸâˆæ‹‡æ’“‚圄LASH)
+#define SELECT_FLASH_CE     (1 << FLASH_CE_VALID)
+
+/* æ��æ’–�FLASH_WP1~FLASH_WP4(éŠçš�”€Žœ•å—è�â…¡ˆË‰‡æ’œˆ1):
+ *   BIT0~BIT3:
+ *       BIT0: WP1 active;
+ *       BIT1: WP2 active;
+ *       BIT2: WP3 active;
+ *       BIT3: WP4 active;
+ */
+#define SELECT_FLASH_WP     0x0
+
+#define comb_ctrl_reg(ps, staff, ce_keep, ce, wp, go) (ps | (staff << 1) | (ce_keep << 9) \
+		| (ce << 10) | (wp << 15) | (go << 30))
+
+#define ECC_CHECK_NO_ERROR              (0x1<<26)
+#define ECC_ERROR_REPAIR_CAN_NOT_TRUST  (0x1<<27)
+
+#define DATA_ECC_CHECK_OK                           1
+#define DATA_ECC_CHECK_ERROR                        0
+#define DATA_ECC_ERROR_REPAIR_CAN_TRUST             2
+#define DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST         3
+
+#define REG32(_reg)	(*(volatile unsigned long *)(_reg))
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned char akecc[128*2];
+static unsigned char tmp_fs_buf[16*16];
+static unsigned char tmp_data_buf[DATA_SIZE*2];
+ 
+static void MMU_FlashDCache(void)  //flash dcache
+{
+	asm("AK_FlashDCache:\n" "mrc  p15,0,r15,c7,c10,3\n" "bne AK_FlashDCache");
+}
+
+static void MMU_InvalidateDCache(void)  //Invalidate dcache
+{
+	asm("AK_InvalidateDCache:\n" "mrc  p15,0,r15,c7,c14,3\n" "bne AK_InvalidateDCache");
+}
+
+static void ak880x_nand_lock_sharepin(void)
+{
+	/* set the share pin for nandflash */
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x74) &= (~(3 << 3));
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x74) |= (1 << 3);	//set 01 to enable the NFC
+
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x78) |=
+	    ((1 << 22) | (0xf << 16));
+
+#if	defined(CONFIG_MACH_AK7801EVB) || defined(CONFIG_MACH_TA8)
+	/* FIXME: use configurable nWP pin */
+	/* set DGPIO 36 high, disable flash write protection */
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x94) &= (~(1 << 5));
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x98) |= (1 << 5);
+#endif
+
+}
+
+/* NFC & HW port setup
+ *
+ * setting NFC, AC
+ *
+ * NFC share pin set
+ *	Enable nandflash function pin		: 0x08000074 [4:3] = 0x01
+ *	Share pin use nandflash :
+ *	CE0,RE,WE,CLE,ALE,data0 -- data7	: 0x08000078 [16]=1 [17]=1 [18]=1
+ *	R/B					: 0x08000078 [22]=1
+ *	pull up and pull down			: use the defalut value
+ */
+void ak880x_nand_inithw(void)
+{
+	/* open the nand flash clk */
+    printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_inithw() line 218\n");
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x0c) &= (~(1 << 13));
+	ak880x_nand_lock_sharepin();
+
+	/* FIXME: use configurable timing parameter */
+	*(volatile unsigned int *)(AK88_VA_NFCTRL + 0x15C) = 0xF5BD1;
+}
+
+/* check cmd_done bit */
+static int check_cmd_done(void)
+{
+	volatile unsigned long status;
+    
+	status = *(volatile unsigned long *)(FLASH_CTRL_REG22);
+
+	if (status & 0x80000000)
+		return 1;
+	else
+		return 0;
+}
+
+//col =1(for 512) or 2(for >512)
+//row_cycle =3
+
+static unsigned long *nf_send_addr(unsigned long *reg, unsigned int col,
+				   unsigned int row, unsigned char col_cycle,
+				   unsigned char row_cycle)
+{
+	unsigned char cycle, value;
+    printk(KERN_INFO "zz ak880x-nfc.c nf_send_addr() line 246\n");
+	ak880x_nand_lock_sharepin();
+
+	// send column address 
+	for (cycle = 0; cycle < col_cycle; cycle++) {
+		value = (col >> (8 * cycle)) & 0xFF;
+		REG32(reg++) = (value << 11) | ADDRESS_CYCLES_CONF;
+	}
+
+	// send row address 
+	for (cycle = 0; cycle < row_cycle; cycle++) {
+		value = (row >> (8 * cycle)) & 0xFF;
+		REG32(reg++) = (value << 11) | ADDRESS_CYCLES_CONF;
+	}
+
+	return reg;
+}
+
+/* get nandflash chip id */
+unsigned long ak880x_nand_get_chipid(unsigned char chip)
+{
+	unsigned long id = 0;
+    printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_get_chipid() line 269\n");
+	ak880x_nand_lock_sharepin();
+
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) = 0x00;
+
+	/* send cmd */
+	*(volatile unsigned long *)(FLASH_CTRL_REG0) =
+	    (NFLASH_READ_ID << 11) | COMMAND_CYCLES_CONF;
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x04) =
+	    (0x00 << 11) | ADDRESS_CYCLES_CONF;
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x08) = DELAY_CNT_CONF;	//wait > 10 ns < 30????(84M, 1 clock =12ns)
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x0C) =
+	    (0x04 << 11) | READ_INFO_CONF | LAST_CMD_FLAG;
+
+	/* excute operation, , enable power saving, CE# keep LOW wait R/B */
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) =
+	    NCHIP_SELECT(chip) | DEFAULT_GO;
+
+	while (!check_cmd_done()) ;
+
+	/* read status */
+	id = *(volatile unsigned long *)(FLASH_CTRL_REG20);
+
+	printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_get_chipid line 292 nandid = 0x%lx\n", id); 
+
+	return id;
+}
+
+/* software reset flash */
+void ak880x_nand_reset(unsigned char chip, unsigned short wait_time)
+{
+	unsigned long *reg_addr = (unsigned long *)FLASH_CTRL_REG0;
+    //printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_reset() line 297\n");
+	ak880x_nand_lock_sharepin();
+
+	// sta_clr = 0
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) = 0x00;
+
+	*(volatile unsigned long *)(reg_addr++) =
+	    ((0xFF << 11) | COMMAND_CYCLES_CONF);
+
+	/* NOTE:
+	 * when command is NOT right, the R/B rising never generate
+	 * so can't wait R/B rising to judge data is ready
+	 *
+	 */
+	wait_time &= 0xFFF;	// only low 12 bit is valid
+
+	if (wait_time) {
+		*(volatile unsigned long *)(reg_addr) =
+		    ((wait_time << 11) | NCHIP_SELECT(chip) | LAST_CMD_FLAG);
+	} else {
+		*(volatile unsigned long *)(reg_addr) =
+		    ((NAND_FLASH_DEFAULT_DELAY << 11) | NCHIP_SELECT(chip) |
+		     LAST_CMD_FLAG);
+	}
+
+	/* excute operation, CE1, disable power saving, CE# keep LOW wait R/B */
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) =
+	    (comb_ctrl_reg(0, 0, 1, SELECT_FLASH_CE, SELECT_FLASH_WP, 1));
+
+	while (!check_cmd_done()) ;
+}
+
+/* set timing */
+void ak880x_nand_settiming(unsigned long cmd_timing, unsigned long data_timing)
+{
+    //printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_settiming() line 335\n");
+	ak880x_nand_lock_sharepin();
+	if (cmd_timing)
+		*(volatile unsigned long *)(FLASH_CTRL_REG23) = cmd_timing;
+
+	if (data_timing)
+		*(volatile unsigned long *)(FLASH_CTRL_REG24) = data_timing;
+}
+
+/* get nandflash chip status */
+unsigned char ak880x_nand_get_status(unsigned char chip)
+{
+	unsigned long nand_status;
+	unsigned long *reg_addr;
+    //printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_get_status() line 349\n");
+	ak880x_nand_lock_sharepin();
+
+	do {
+		nand_status = 0;
+		reg_addr = (unsigned long *)FLASH_CTRL_REG0;
+
+		*(volatile unsigned long *)(FLASH_CTRL_REG22) = 0x00;
+
+		/* send cmd */
+		*(volatile unsigned long *)(reg_addr++) =
+		    ((NFLASH_READ_STATUS << 11) | COMMAND_CYCLES_CONF);
+		*(volatile unsigned long *)(reg_addr++) = DELAY_CNT_CONF;
+		*(volatile unsigned long *)(reg_addr++) = DELAY_CNT_CONF;
+		*(volatile unsigned long *)(reg_addr) =
+		    ((0x1 << 11) | READ_INFO_CONF | LAST_CMD_FLAG);
+
+		/* excute operation, , enable power saving, CE# keep LOW wait R/B */
+		*(volatile unsigned long *)(FLASH_CTRL_REG22) =
+		    NCHIP_SELECT(chip) | DEFAULT_GO;
+
+		while (!check_cmd_done()) ;
+
+		/* read status */
+		nand_status = *(volatile unsigned long *)(FLASH_CTRL_REG20);
+		if ((nand_status & AK_NAND_STATUS_READY) !=
+		    AK_NAND_STATUS_READY)
+			mdelay(2);
+		else
+			break;
+	} while (1);
+
+	if ((nand_status & AK_NAND_STATUS_ERROR) == AK_NAND_STATUS_ERROR)
+		printk("status error!\n");
+
+	return nand_status & 0xFF;
+}
+
+/* erase nandflash block */
+void ak880x_nand_eraseblock(unsigned char chip, unsigned int phypage)
+{
+    //printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_eraseblock() line 390\n");
+	ak880x_nand_lock_sharepin();
+
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) = 0x00;
+
+	/* send cmd */
+	*(volatile unsigned long *)(FLASH_CTRL_REG0) =
+	    (NFLASH_BLOCK_ERASE0 << 11) | COMMAND_CYCLES_CONF;
+
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x04) =
+	    ((phypage & 0xff) << 11) | ADDRESS_CYCLES_CONF;
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x08) =
+	    (((phypage & 0xff00) >> 8) << 11) | ADDRESS_CYCLES_CONF;
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x0c) =
+	    (((phypage & 0xff0000) >> 16) << 11) | ADDRESS_CYCLES_CONF;
+	*(volatile unsigned long *)(FLASH_CTRL_REG0 + 0x10) =
+	    (NFLASH_BLOCK_ERASE1 << 11) | COMMAND_CYCLES_CONF | LAST_CMD_FLAG;
+
+	/* excute operation, , enable power saving, CE# keep LOW wait R/B */
+	*(volatile unsigned long *)(FLASH_CTRL_REG22) =
+	    NCHIP_SELECT(chip) | DEFAULT_GO;
+
+	while (!check_cmd_done()) ;
+}
+
+void ak880x_nand_read_page(unsigned char chip, unsigned int rowAddr,
+			   unsigned int columnAddr, unsigned char *buf,
+			   unsigned int len, unsigned char large_page)
+{
+	unsigned long *reg_addr;
+	unsigned long tmp;
+	int read_times = len / 512 ? len / 512 : 1;
+	int step;
+	int i;
+
+    printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_read_page() line 425\n");
+
+	if (len >= 512)
+		step = 512;
+	else
+		step = len;
+
+	ak880x_nand_lock_sharepin();
+
+	/*************** set program command *******************************/
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);	//clear the go stat reg
+	reg_addr = (T_U32 *) FLASH_CTRL_REG0;
+
+	//nandflash send command
+	if (large_page) {
+		REG32(reg_addr++) = (NFLASH_READ0 << 11) | COMMAND_CYCLES_CONF;
+	} else {
+		if (columnAddr < 256) {
+			REG32(reg_addr++) =
+			    (NFLASH_READ0 << 11) | COMMAND_CYCLES_CONF;
+		} else if (columnAddr >= 512) {
+			REG32(reg_addr++) =
+			    (NFLASH_READ12 << 11) | COMMAND_CYCLES_CONF;
+		} else {
+			columnAddr -= 256;
+			REG32(reg_addr++) =
+			    (NFLASH_READ0_HALF << 11) | COMMAND_CYCLES_CONF;
+		}
+	}
+
+	if (large_page)
+		reg_addr = nf_send_addr(reg_addr, columnAddr, rowAddr, 2, 3);
+	else {
+		reg_addr = nf_send_addr(reg_addr, columnAddr, rowAddr, 1, 3);
+	}
+
+	if (large_page) {
+		HAL_WRITE_UINT32((T_U32) (reg_addr++),
+				 (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF);
+	}
+
+	HAL_WRITE_UINT32((T_U32) (reg_addr++), WAIT_JUMP_CONF | LAST_CMD_FLAG);	// wait R/B rising edge
+	//HAL_WRITE_UINT32((T_U32)(reg_addr++), (0x1<<11) | DELAY_CNT_CONF | LAST_CMD_FLAG);  //DELAY
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, NCHIP_SELECT(chip) | DEFAULT_GO);
+	while (!check_cmd_done()) ;
+	
+
+	// *******************************************************************
+#if 0
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+	MMU_InvalidateDCache();
+#else  // in here
+	MMU_CleanDCache();
+	//printk("nand_read_page()/MMU_CleanDCache();\n");
+#endif
+ 
+//invalidate_dcache_range((unsigned int)buf,(unsigned int)(buf+len));
+	MMU_InvalidateDCache();
+#endif 
+
+	for (i = 0; i < read_times; i++) {
+
+		communicate_conf(NAND_FLASH, READ_BUF);
+
+		//config ECC
+		tmp = (0 | ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR
+		       | ECC_CTL_BYTE_CFG(step) | ECC_CTL_NFC_EN |
+		       ECC_CTL_MODE);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp | ECC_CTL_START);
+
+		// config NAND interface
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);	//clear the go stat reg
+		reg_addr = (T_U32 *) FLASH_CTRL_REG0;
+		HAL_WRITE_UINT32((T_U32) reg_addr,
+				 ((step -
+				   1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG);
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22,
+				 NCHIP_SELECT(chip) | DEFAULT_GO);
+
+		while (!check_cmd_done()) ;	// wait till all data is received
+
+		// copy page data from L2 buffer
+		rece_dat_cpu(buf + i * step, step, NAND_FLASH);
+
+		// wait for ECC completion
+		do {
+			HAL_READ_UINT32(FLASH_ECC_REG0, tmp);
+		} while (((tmp & ECC_CTL_END) == 0)
+			 || !(tmp & ECC_CTL_DEC_RDY));
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));
+	}
+}
+
+void ak880x_nand_write_page(unsigned char chip, unsigned int rowAddr,
+			    unsigned int columnAddr, const unsigned char *buf,
+			    unsigned int len, unsigned char large_page)
+{
+	unsigned long *reg_addr;
+	unsigned long tmp;
+	int write_times = len / 512 ? len / 512 : 1;
+	int step;
+	int i;
+    printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_write_page() line 528\n");
+	if (len >= 512)
+		step = 512;
+	else
+		step = len;
+
+	ak880x_nand_lock_sharepin();
+
+	/*set program command */
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);	//clear the go stat reg
+	reg_addr = (T_U32 *) FLASH_CTRL_REG0;
+
+	if (!large_page) {
+		if (columnAddr < 256) {
+			REG32(reg_addr++) =
+			    (NFLASH_READ0 << 11) | COMMAND_CYCLES_CONF;
+		} else if (columnAddr >= 512) {
+			REG32(reg_addr++) =
+			    (NFLASH_READ12 << 11) | COMMAND_CYCLES_CONF;
+		} else {
+			columnAddr -= 256;
+			REG32(reg_addr++) =
+			    (NFLASH_READ0_HALF << 11) | COMMAND_CYCLES_CONF;
+		}
+	}
+
+	HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+			 (NFLASH_PAGE_PROGRAM0 << 11) | COMMAND_CYCLES_CONF);
+
+	if (large_page) {
+#if 1
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 ((columnAddr & 0xff) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 (((columnAddr & 0xff00) >> 8) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 ((rowAddr & 0xff) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 (((rowAddr & 0xff00) >> 8) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 (((rowAddr & 0xff0000) >> 16) << 11) |
+				 ADDRESS_CYCLES_CONF | LAST_CMD_FLAG);
+#else
+		reg_addr = nf_send_addr(reg_addr, columnAddr, rowAddr, 2, 2);
+#endif
+	} else {
+#if 1
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 ((columnAddr & 0xff) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 ((rowAddr & 0xff) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 (((rowAddr & 0xff00) >> 8) << 11) |
+				 ADDRESS_CYCLES_CONF);
+		HAL_WRITE_UINT32((unsigned long)(reg_addr++),
+				 (((rowAddr & 0xff0000) >> 16) << 11) |
+				 ADDRESS_CYCLES_CONF | LAST_CMD_FLAG);
+#else
+		reg_addr = nf_send_addr(reg_addr, columnAddr, rowAddr, 1, 3);
+#endif
+	}
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22,
+			 (SELECT_FLASH_CE << 10) | DEFAULT_GO);
+
+	while (!check_cmd_done()) ;
+
+#if 0
+	//flash_dcache_range((unsigned int)buf,(unsigned int)(buf+len));
+	MMU_FlashDCache();
+#endif
+
+	//printk("write_page()/MMU_FlashDCache();\n");
+
+	for (i = 0; i < write_times; i++) {
+
+		// init L2 buffer
+		communicate_conf(NAND_FLASH, WRITE_BUF);
+
+		// config ECC module
+		tmp = (0 | ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR
+		       | ECC_CTL_BYTE_CFG(step) | ECC_CTL_NFC_EN |
+		       ECC_CTL_MODE);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);
+		/* start */
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp | ECC_CTL_START);
+
+		// config NAND interface
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);	//clear the go stat reg
+		HAL_WRITE_UINT32(FLASH_CTRL_REG0,
+				 ((step -
+				   1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG);
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22,
+				 NCHIP_SELECT(chip) | DEFAULT_GO);
+
+		// copy page data to L2 buffer
+#ifdef CONFIG_MTD_NAND_DMA_MODE
+		prepare_dat_send_dma((T_U8 *) buf, step, NAND_FLASH);
+#else
+		prepare_dat_send_cpu(buf + i * step, step, NAND_FLASH);
+#endif
+		while (!check_cmd_done()) ;
+
+		// wait for ECC complete        
+		do {
+			HAL_READ_UINT32(FLASH_ECC_REG0, tmp);
+		} while (((tmp & ECC_CTL_END) == 0)
+			 || !(tmp & ECC_CTL_ENC_RDY));
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));
+
+	}
+
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);	//clear the go stat reg
+	HAL_WRITE_UINT32(FLASH_CTRL_REG0,
+			 (NFLASH_PAGE_PROGRAM1 << 11) | COMMAND_CYCLES_CONF);
+	HAL_WRITE_UINT32(FLASH_CTRL_REG0 + 0x4, WAIT_JUMP_CONF | LAST_CMD_FLAG);	// wait R/B rising edge
+	//HAL_WRITE_UINT32(FLASH_CTRL_REG0+0x4,  (0x100<< 11) | DELAY_CNT_CONF | LAST_CMD_FLAG);
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, NCHIP_SELECT(chip) | DEFAULT_GO);
+
+	//printk("wait cmd done...\n");
+	while (!check_cmd_done()) ;
+}
+
+unsigned char ak880x_nand_ecc_stat(unsigned long stat)
+{
+    printk(KERN_INFO "zz ak880x-nfc.c ak880x_nand_ecc_stat() line 658\n");
+	ak880x_nand_lock_sharepin();
+
+	if ((stat & ECC_CHECK_NO_ERROR) == ECC_CHECK_NO_ERROR) {
+
+		*(volatile unsigned long *)(FLASH_ECC_REG0) =
+		    (stat | ECC_CHECK_NO_ERROR);
+		stat = *(volatile unsigned long *)(FLASH_ECC_REG0);
+
+		return DATA_ECC_CHECK_OK;
+
+	} else if ((stat & ECC_ERROR_REPAIR_CAN_NOT_TRUST) ==
+		   ECC_ERROR_REPAIR_CAN_NOT_TRUST) {
+
+		*(volatile unsigned long *)(FLASH_ECC_REG0) =
+		    stat | ECC_ERROR_REPAIR_CAN_NOT_TRUST;
+		stat = *(volatile unsigned long *)(FLASH_ECC_REG0);
+
+		return DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST;
+	} else
+		return DATA_ECC_ERROR_REPAIR_CAN_TRUST;
+}
+
+
+/******************************************************************************
+	nand read/write with ecc    
+	add at 08/05/2010 
+	by Lynn Liu
+******************************************************************************/
+
+//mach/map.h
+//#define AK880X_VA_SUBCTRL       AK880X_ADDR(0x00200000)
+//#define AK880X_PA_SUBCTRL       (0x20000000)
+//#define AK880X_VA_ECCCTRL       (AK880X_VA_SUBCTRL + 0x2B000)
+
+//#define FLASH_ECC_POSITION_REG0     (0X2002B004)
+//#define FLASH_ECC_POSITION_REG1     (0X2002B004+4)
+//#define FLASH_ECC_POSITION_REG2     (0X2002B004+8)
+//#define FLASH_ECC_POSITION_REG3     (0X2002B004+12)
+//#define FLASH_ECC_POSITION_REG4     (0X2002B004+16)
+//#define FLASH_ECC_POSITION_REG5     (0X2002B004+20)
+//#define FLASH_ECC_POSITION_REG6     (0X2002B004+24)
+//#define FLASH_ECC_POSITION_REG7     (0X2002B004+28)
+//#define FLASH_ECC_POSITION_REG8     (0X2002B004+32)
+
+//#define DATA_SIZE 4096
+
+//#define FLASH_ECC_POSITION_REG0     (AK880X_VA_ECCCTRL + 0X04)
+
+/*********************************************************************
+Function:       NAND_Read_ChipStatus
+Description:    read the Nand flash chip's status.
+Input:
+Output:
+Return:         chip status
+Author:       Zou Tianxiang
+Date:         2007.7.6
+**********************************************************************/
+
+extern int print_32(unsigned char *buf);
+
+unsigned char NAND_Read_ChipStatus(void)
+{
+	unsigned int nand_status;
+	unsigned int *reg_addr;
+    printk(KERN_INFO "zz ak880x-nfc.c NAND_Read_ChipStatus() line 723\n");
+	nand_status = 0;
+	reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+
+	ak880x_nand_lock_sharepin();
+
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0x00);
+
+	/* send cmd */
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (NFLASH_READ_STATUS << 11) | COMMAND_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), DELAY_CNT_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), DELAY_CNT_CONF);
+	HAL_WRITE_UINT32((unsigned int)reg_addr, (0x1 << 11) | READ_INFO_CONF | LAST_CMD_FLAG);
+
+	// excute operation, , enable power saving, CE# keep LOW wait R/B
+	HAL_WRITE_UINT32( FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO );
+	// wait end & read data (data at where)
+	while(!check_cmd_done());
+
+	// read status
+	HAL_READ_UINT32(FLASH_CTRL_REG20, nand_status);
+	return (unsigned char)(nand_status & 0xff);
+
+}
+
+/*********************************************************************
+Function:       TNAND_ECC_POS_HIGHT
+Description:    NAND ECC DATA REPAIR
+Input:
+Output:
+Return:         1: Repair ok   0: Repair failed
+Author:             Zou Tianxiang
+Date:               2007.7.6
+ **********************************************************************/
+static unsigned int TNAND_ECC_POS_HIGHT(unsigned int position_info, unsigned char *buf, unsigned char *fs_buf)
+{
+	unsigned int position = (position_info>>9) & 0x3ff;
+	unsigned int offset;
+	//unsigned int bit_index;
+	unsigned int byte_index;
+	unsigned char  correct;
+	unsigned int shift;
+    printk(KERN_INFO "zz ak880x-nfc.c TNAND_ECC_POS_HIGHT() line 765\n");
+	ak880x_nand_lock_sharepin();
+
+	if (position)
+	{// error occurs
+		//        printk("ECC error position reg = 0x%x\n",  position_info);
+
+		// There are chances that two errors fall into contiguous bits. Then position will have two bits set.
+		// For each bit of position
+		for (shift=0; shift<10; shift++)
+		{
+			if (0 == (position & (1<<shift)))
+			{
+				// no error in this block
+				continue;
+			}
+
+			switch (position & (1<<shift))
+			{
+				case (1<<0):
+				case (1<<1):
+					// block1
+					byte_index = NAND_SPARE_SIZE - 128;
+					break;
+
+				case (1<<2):
+				case (1<<3):
+					// block2
+					byte_index = NAND_SPARE_SIZE;
+					break;
+
+				case (1<<4):
+				case (1<<5):
+					// block3
+					byte_index = NAND_SPARE_SIZE + 128;
+					break;
+
+				case (1<<6):
+				case (1<<7):
+					// block4
+					byte_index = NAND_SPARE_SIZE + 128*2;
+					break;
+
+				case (1<<8):
+				case (1<<9):
+					// block5
+					byte_index = NAND_SPARE_SIZE + 128*3;
+					break;
+				default:
+					printk("wrong position = 0x%x\n", position);
+					while(1);
+					break;
+			}
+
+			offset = 2 * (position_info & 0x1ff) + (((1<<shift)&0x2aa)? 1:0);
+#ifndef ECC_MODE1
+			offset -= 4;
+			if (offset & 0x8000)
+			{
+				byte_index -= 1;
+				offset += 8;
+			}
+#endif
+
+			byte_index += offset>>3;
+			correct = 1 << (7 - (offset&0x7));
+			//print("byte index = %d, correct factor = 0x%x\n", byte_index, correct);
+
+			if (byte_index < NAND_DATA_SIZE)
+			{// error occurs in data
+				buf[byte_index] ^= correct;
+			}
+			else if (byte_index < NAND_EFFECTIVE_SIZE)
+			{// error occurs in file system info
+				fs_buf[byte_index-NAND_DATA_SIZE] ^= correct;
+			}
+			else
+			{// error occurs in parity data
+				// nothing to do            
+			}
+		}
+	}
+
+	return 1;
+}
+
+
+/*********************************************************************
+Function:       NAND_ECC_Repair
+Description:    NAND ECC REPAIR
+Input:        PERIPHERAL_TYPE dev_type
+Output:
+Return:         ecc check:  data  ok            return      1
+ecc check:  data  error can't repair            return      0
+ecc check,  data will repair, can trust         return      2
+ecc check,  data will repair, can't trust       return      3
+
+Author:       Zou Tianxiang
+Date:         2007.7.6
+**********************************************************************/
+
+static unsigned char NAND_ECC_Data_Check(unsigned int stat)
+{
+	//unsigned int position_star;
+	//unsigned int position_end;
+    printk(KERN_INFO "zz ak880x-nfc.c NAND_ECC_Data_Check() line 869\n");
+	ak880x_nand_lock_sharepin();
+
+	if( (stat & ECC_CHECK_NO_ERROR) == ECC_CHECK_NO_ERROR )
+	{
+		stat |= ECC_CHECK_NO_ERROR;
+		HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);
+		HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);
+		return DATA_ECC_CHECK_OK;
+	}
+	else if( (stat & ECC_ERROR_REPAIR_CAN_NOT_TRUST) == ECC_ERROR_REPAIR_CAN_NOT_TRUST)
+	{
+		stat |= ECC_ERROR_REPAIR_CAN_NOT_TRUST;
+		HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);
+		HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);
+		return DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST;
+	}
+	else
+	{
+		return DATA_ECC_ERROR_REPAIR_CAN_TRUST;
+	}
+}
+
+
+/*********************************************************************
+Function:       NAND_ECC_Data_Repair
+Description:    NAND ECC DATA REPAIR
+Input:
+Output:
+Return:         1: Repair ok   0: Repair failed
+Author:       Zou Tianxiang
+Date:         2007.7.6
+ **********************************************************************/
+void NAND_ECC_Data_Repair(unsigned char *buf, unsigned char *fs_buf)
+{
+	unsigned int position_info;
+	//unsigned int wrong_info;
+	unsigned int error_count;
+    printk(KERN_INFO "zz ak880x-nfc.c NAND_ECC_Data_Repair() line 907\n");
+	ak880x_nand_lock_sharepin();
+
+	for (error_count=0; error_count<MAX_ERROR_CNT; error_count++)
+	{
+		HAL_READ_UINT32(FLASH_ECC_POSITION_REG0 + error_count*4 ,position_info);
+
+		TNAND_ECC_POS_HIGHT(position_info, buf, fs_buf);
+	}
+}
+
+void Nand_WritePhyPage_ECC_2K(unsigned int PhyPage,const unsigned char *buf, const unsigned char *fs_buf)
+{
+	unsigned int *reg_addr;
+	unsigned int status;
+	unsigned int tmp;
+	unsigned int i;
+	unsigned int max_read_count = 512 ;
+	//unsigned int read_loop = nand_flash_info_tab[cur_flash_info].data_size/max_read_count ;
+	//unsigned int read_loop = DATA_SIZE/max_read_count ;
+	unsigned int read_loop = NAND_MAX_PAGESIZE/max_read_count ;  //4096/512
+    printk(KERN_INFO "zz ak880x-nfc.c Nand_WritePhyPage_ECC_2K() line 929\n");
+//MMU_Clean_All_DCache();
+MMU_FlashDCache();
+
+	ak880x_nand_lock_sharepin();
+
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+	reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (NFLASH_PAGE_PROGRAM0 << 11) | COMMAND_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), ((0 & 0xff) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((0 & 0xff00)>>8) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), ((PhyPage & 0xff) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((PhyPage & 0xff00)>>8) << 11) | ADDRESS_CYCLES_CONF);
+
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((PhyPage & 0xff0000)>>16) << 11) | ADDRESS_CYCLES_CONF|LAST_CMD_FLAG);
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+	while(!check_cmd_done());
+
+	// write 4*page bytes
+	for( i = 0; i < read_loop; i++ )
+	{
+		// init l2 buffer
+		communicate_conf(NAND_FLASH, WRITE_BUF);
+
+ 		//==========================
+		// config ECC module
+		tmp = ( ECC_CTL_ENC_EN | ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR
+				| ECC_CTL_BYTE_CFG(NAND_EFFECTIVE_SIZE) | ECC_CTL_NFC_EN | ECC_CTL_MODE);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp|ECC_CTL_START); 
+		
+ 		//=============================
+		// config NAND interface
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+		HAL_WRITE_UINT32(FLASH_CTRL_REG0, ((NAND_PAGE_SIZE-1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG);
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+
+		//==========================
+		// copy page data to L2 buffer
+#ifdef L2_DMA_MODE
+		prepare_dat_send_dma(buf+i*NAND_DATA_SIZE, NAND_DATA_SIZE, NAND_FLASH);
+		prepare_dat_send_dma(fs_buf+i*NAND_FS_SIZE, NAND_FS_SIZE, NAND_FLASH);
+#else
+		prepare_dat_send_cpu(buf+i*NAND_DATA_SIZE, NAND_DATA_SIZE, NAND_FLASH);
+		prepare_dat_send_cpu(fs_buf+i*NAND_FS_SIZE, NAND_FS_SIZE, NAND_FLASH);
+#endif
+		//=============================
+
+ 		// wait for ECC complete
+		do
+		{
+			HAL_READ_UINT32(FLASH_ECC_REG0,tmp);
+		} while((tmp  & ECC_CTL_END) != ECC_CTL_END);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));
+
+ 		//while(!check_cmd_done());
+	}
+
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+	HAL_WRITE_UINT32(FLASH_CTRL_REG0, (NFLASH_PAGE_PROGRAM1 << 11) | COMMAND_CYCLES_CONF);
+	//HAL_WRITE_UINT32(FLASH_CTRL_REG0+0x4,  (0x1<< 11) | DELAY_CNT_CONF | LAST_CMD_FLAG);
+	//by ljh, wait rb ready
+	HAL_WRITE_UINT32(FLASH_CTRL_REG0+0x4,  WAIT_JUMP_CONF|LAST_CMD_FLAG);
+
+
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+	while(!check_cmd_done());
+
+	do
+	{
+		status = NAND_Read_ChipStatus();
+	}   while((status & NAND_STATUS_READY) != NAND_STATUS_READY);
+
+	if( (status & AK_NAND_STATUS_ERROR) == AK_NAND_STATUS_ERROR)
+	{
+		printk("Program 2K ecc error!\n");
+	}
+}
+
+
+unsigned char Nand_ReadPhyPage_ECC_2K(unsigned int PhyPage, unsigned char *buf, unsigned char *fs_buf)
+{
+
+	unsigned int *reg_addr;
+	unsigned int tmp;
+	unsigned char  ecc_stat;
+	unsigned int i;
+	unsigned int max_read_count = 512 ;
+	//unsigned int read_loop = nand_flash_info_tab[cur_flash_info].data_size/max_read_count ;
+ 	unsigned int read_loop = NAND_MAX_PAGESIZE/max_read_count ;  //4096/512
+	int ecc_all_ff=1;
+	int j=0,j0=0;
+    printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() line 1017\n");
+MMU_InvalidateDCache();
+	
+	ak880x_nand_lock_sharepin();
+
+	memset(akecc,0x00,sizeof(akecc));
+  
+	//set program command 
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+	reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (NFLASH_READ0 << 11) | COMMAND_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), ((0 & 0xff) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((0 & 0xff00)>>8) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), ((PhyPage & 0xff) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((PhyPage & 0xff00)>>8) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (((PhyPage & 0xff0000)>>16) << 11) | ADDRESS_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF);
+	HAL_WRITE_UINT32((unsigned int)(reg_addr++), WAIT_JUMP_CONF | LAST_CMD_FLAG);  //DELAY
+	HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+	while(!check_cmd_done()) ;
+
+	for ( i = 0; i < read_loop; i++ )
+	{
+ 
+		// init L2 buffer
+		communicate_conf(NAND_FLASH, READ_BUF);
+ 
+		//==========================
+		//config ECC
+		tmp = ECC_CTL_DEC_EN | ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR
+			| ECC_CTL_BYTE_CFG(NAND_EFFECTIVE_SIZE) | ECC_CTL_NFC_EN | ECC_CTL_MODE
+			| ECC_CTL_NO_ERR | ECC_CTL_RESULT_NO_OK;    // reset ecc result status bits
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp|ECC_CTL_START);  
+ 
+		//==========================
+		// config NAND interface
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+		reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+		HAL_WRITE_UINT32((unsigned int)reg_addr, ((NAND_PAGE_SIZE-1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG);
+		HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+ 
+		//==========================
+		// copy page data from L2 buffer
+#ifdef L2_DMA_MODE
+        //printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() 1061 L2_DMA_MODE\n");
+		rece_data_dma(buf+i*NAND_DATA_SIZE, NAND_DATA_SIZE, NAND_FLASH);
+		while(!check_cmd_done()); // wait till all data is received
+		rece_data_dma(fs_buf+i*NAND_FS_SIZE, NAND_FS_SIZE, NAND_FLASH);
+		rece_dat_dma(akecc+i*NAND_PARITY_SIZE, NAND_PARITY_SIZE, NAND_FLASH);
+#else
+        printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() 1067 L2_CPU_MODE\n");
+		rece_dat_cpu(buf+i*NAND_DATA_SIZE, NAND_DATA_SIZE, NAND_FLASH);
+		while(!check_cmd_done()); // wait till all data is received
+		/*
+	    for (j=0; j<32; j++)
+        {
+            printk(KERN_INFO "data[%d] = 0x%x", j, buf[i*NAND_DATA_SIZE+j]);
+        }
+        */
+		rece_dat_cpu(fs_buf+i*NAND_FS_SIZE, NAND_FS_SIZE, NAND_FLASH);
+        /*
+        printk(KERN_INFO "oob[] 0x%x 0x%x 0x%x 0x%x\n", 
+               fs_buf[i*NAND_FS_SIZE],
+               fs_buf[i*NAND_FS_SIZE+1],
+               fs_buf[i*NAND_FS_SIZE+2],
+               fs_buf[i*NAND_FS_SIZE+3]);
+               */
+        printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() 1086 NAND_PARITY_SIZE=%d\n",
+               NAND_PARITY_SIZE);
+		rece_dat_cpu(akecc+i*NAND_PARITY_SIZE, NAND_PARITY_SIZE, NAND_FLASH);
+
+#endif
+
+		//if read ecc result is all 0xff,it isn't a valid ecc,
+		//it only means this page has beed erased, no written any words,or not written with ecc
+	
+		ecc_all_ff=1;
+		j0=i*NAND_PARITY_SIZE;
+		for(j=0;j<NAND_PARITY_SIZE;j++)	{
+ 			if(akecc[j0+j]!=0xff) {
+ 				ecc_all_ff=0;	//isn't all 0xff, it is a valid ecc
+				break;
+                        }
+		}
+		
+		//invalid ecc, means this page is empty,it is an erased page, or not written with ecc
+		if(ecc_all_ff==1) {	
+			//printk("erased page,akecc=");
+			//print_32(akecc);
+			continue;
+		}
+		else{
+			//printk("valid ecc,akecc=");
+			//print_32(akecc);
+		}
+
+	
+		//==========================
+
+		// wait for ECC complete
+		do
+		{
+			HAL_READ_UINT32(FLASH_ECC_REG0,tmp);
+		}   while((tmp  & ECC_CTL_END) == 0);
+		HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));
+        
+        //buf[i*NAND_DATA_SIZE] = (buf[i*NAND_DATA_SIZE])^0b00001111;
+
+ 		ecc_stat = NAND_ECC_Data_Check(tmp);
+ 
+		switch(ecc_stat)
+		{
+			case DATA_ECC_CHECK_OK:
+				break;
+
+			case DATA_ECC_ERROR_REPAIR_CAN_TRUST:
+				printk("page %d: ecc error occurs and can be corrected\n", PhyPage);
+				NAND_ECC_Data_Repair(buf+i*NAND_DATA_SIZE, (fs_buf+i*NAND_FS_SIZE));
+				break;
+
+			case DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST:
+ 				printk("page %d: ecc error occurs and cannot be corrected\n", PhyPage);
+				printk("akecc=");
+				print_32(akecc);
+
+				return 0;
+ 
+			default :
+				printk("No ECC State!\n");
+				break;
+		}
+	}
+  
+	return 1;
+}
+
+/*
+
+    static T_VOID cmd_go(T_U32 Chip)
+    {
+        volatile T_U32 status;
+    
+        status = REG32(FLASH_CTRL_REG22);
+        status &= ~( 1<<31 | 1<<10 | 1<<11); //remove CE flag
+        status |= NCHIP_SELECT(Chip) | ((1 << 30)|(1<<9));
+        REG32(FLASH_CTRL_REG22) = status;
+    }
+
+unsigned char Nand_ReadPhyPage_ECC_2K(unsigned int PhyPage, unsigned char *buf, unsigned char *fs_buf)
+{
+    
+        unsigned int *reg_addr;
+        unsigned int tmp;
+        unsigned int i;
+        unsigned int max_read_count = 512 ;
+        //unsigned int read_loop = nand_flash_info_tab[cur_flash_info].data_size/max_read_count ;
+        unsigned int read_loop = NAND_MAX_PAGESIZE/max_read_count ;  //4096/512
+        printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() line 1152\n");
+        MMU_InvalidateDCache();
+        
+        ak880x_nand_lock_sharepin();
+        
+        memset(akecc,0x00,sizeof(akecc));
+      
+        REG32(FLASH_CTRL_REG22) &= ~(1<<14);
+        reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+         //nandflash send command
+        REG32(reg_addr++) = (0x00 << 11) | COMMAND_CYCLES_CONF;
+        reg_addr = nf_send_addr(reg_addr, 0, PhyPage, 2, 3);
+        //nandflash read2 command,this is a wait command
+        if (0 != 2)
+        {
+            REG32(reg_addr++) = (0x30 << 11) | COMMAND_CYCLES_CONF |(1 << 10);
+        }
+    
+        REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge
+
+        cmd_go(0);
+        while (!check_cmd_done());
+
+        for ( i = 0; i < read_loop; i++ )
+        {
+     
+            // init L2 buffer
+            communicate_conf(NAND_FLASH, READ_BUF);
+     
+            //==========================
+            //config ECC
+            tmp = (ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR  \
+                      | ECC_CTL_BYTE_CFG(516) | ECC_CTL_NFC_EN | ECC_CTL_MODE);
+            HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);
+            HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp|ECC_CTL_START);
+            REG32(FLASH_CTRL_REG0) = ((516 - 1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG;
+            cmd_go(0);
+    
+            //==========================
+            // config NAND interface
+            HAL_WRITE_UINT32(FLASH_CTRL_REG22, 0);      //clear the go stat reg
+            reg_addr = (unsigned int *) FLASH_CTRL_REG0;
+            HAL_WRITE_UINT32((unsigned int)reg_addr, ((NAND_PAGE_SIZE-1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG);
+            HAL_WRITE_UINT32(FLASH_CTRL_REG22, (SELECT_FLASH_CE<<10)|DEFAULT_GO);
+     
+            //==========================
+            // copy page data from L2 buffer
+            printk(KERN_INFO "zz ak880x-nfc.c Nand_ReadPhyPage_ECC_2K() 1232 L2_CPU_MODE\n");
+            rece_dat_cpu(buf+i*NAND_DATA_SIZE, NAND_DATA_SIZE, NAND_FLASH);
+            while(!check_cmd_done()); // wait till all data is received
+         
+            rece_dat_cpu(fs_buf+i*NAND_FS_SIZE, NAND_FS_SIZE, NAND_FLASH);
+            rece_dat_cpu(akecc+i*NAND_PARITY_SIZE, NAND_PARITY_SIZE, NAND_FLASH);
+        }
+        return 1;
+}
+*/
+#define AK880X_OOB_OFFSET      (2)
+//#define AK880X_OOB_OFFSET      (0)
+#define AK880X_FS_LEN          (3*8)
+
+static unsigned char data_buf[DATA_SIZE+OOB_SIZE];
+static unsigned char fs_buf[AK880X_FS_LEN] ;
+
+void nand_write_page_ecc( int page, const unsigned char *buf,const unsigned char *oobbuf)
+{
+/**
+	yaffs tags len = { 28, //with tags ECC
+			   16, //no tags ECC	
+			 }
+**/
+
+    printk(KERN_INFO "zz ak880x-nfc.c nand_write_page_ecc() line 1290\n");
+	if(oobbuf==NULL)
+	{
+		memset(tmp_fs_buf,0xff,sizeof(tmp_fs_buf));
+		oobbuf=&tmp_fs_buf[0];
+	}
+
+	Nand_WritePhyPage_ECC_2K( page, buf, oobbuf+AK880X_OOB_OFFSET);
+
+	return;
+}
+
+ 
+void nand_read_page_ecc( int page, unsigned char * buf,unsigned char *oobbuf)
+{
+    printk(KERN_INFO "zz ak880x-nfc.c nand_read_page_ecc() line 1305\n");
+	if(oobbuf==NULL)
+	{
+		memset(tmp_fs_buf,0xff,sizeof(tmp_fs_buf));
+		oobbuf=&tmp_fs_buf[0];
+	}
+
+	Nand_ReadPhyPage_ECC_2K( page, buf, oobbuf+AK880X_OOB_OFFSET);
+ 
+	return;
+}
+
+//read data, does'n transfer oob
+void nand_read_page_data( int page, unsigned char * data_buf)
+{
+    printk(KERN_INFO "zz ak880x-nfc.c nand_read_page_data() line 1320\n");
+ 	memset(tmp_fs_buf,0xff,sizeof(tmp_fs_buf));
+  
+	Nand_ReadPhyPage_ECC_2K( page, data_buf, tmp_fs_buf+AK880X_OOB_OFFSET);
+
+	return;
+}
+
+//read oob,doesn't transfer data
+void nand_read_page_oob( int page, unsigned char * oob_buf)
+{
+    printk(KERN_INFO "zz ak880x-nfc.c nand_read_page_oob() line 1331\n");
+ 	memset(tmp_data_buf,0xff,sizeof(tmp_data_buf));
+  
+	Nand_ReadPhyPage_ECC_2K( page, tmp_data_buf, oob_buf+AK880X_OOB_OFFSET);
+
+	return;
+}
+
+
+void nand_read_oob_ecc( int page, unsigned char *oobbuf)
+{  	
+    printk(KERN_INFO "zz ak880x-nfc.c nand_read_oob_ecc() line 1342\n");
+ 	memset(data_buf,0xff,sizeof(data_buf));
+ 	Nand_ReadPhyPage_ECC_2K( page, data_buf, oobbuf + AK880X_OOB_OFFSET);
+    return;
+}
+
+
+ 
+//only write some bytes
+void nand_write_page_ecc_part( int page,const unsigned char *buf,int len )
+{
+    printk(KERN_INFO "zz ak880x-nfc.c nand_write_page_ecc_part() line 1353\n");
+	memset(data_buf,0xff,sizeof(data_buf));
+	memset(fs_buf,0xff,sizeof(fs_buf));
+  
+	len = len<DATA_SIZE? len:DATA_SIZE;
+
+	memcpy(data_buf,buf,len);
+
+	Nand_WritePhyPage_ECC_2K( page,data_buf, fs_buf) ;
+	
+	return ;
+}
+ 
+
+//only read some bytes
+void nand_read_page_ecc_part( int page, unsigned char * buf,int len )
+{ 
+    printk(KERN_INFO "zz ak880x-nfc.c nand_read_page_ecc_part() line 1370\n");
+	memset(data_buf,0xff,sizeof(data_buf));
+	memset(fs_buf,0xff,sizeof(fs_buf));
+ 
+	Nand_ReadPhyPage_ECC_2K( page, data_buf, fs_buf) ;
+
+	len = len<DATA_SIZE? len:DATA_SIZE;
+
+	memcpy(buf,data_buf,len);
+  
+	return ;
+}
+
diff --git a/drivers/mtd/nand/ak88-nand/ak880x.c b/drivers/mtd/nand/ak88-nand/ak880x.c
new file mode 100644
index 00000000000..d65a00bf19e
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/ak880x.c
@@ -0,0 +1,565 @@
+/* linux/drivers/mtd/nand/ak880x.c
+ *
+ * Anyka ak880x NAND driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifdef CONFIG_MTD_NAND_AK880X_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/dma-mapping.h>
+#include <mach-anyka/anyka_types.h>
+
+#include <asm/io.h>
+#include <mach/nand.h>
+#include <mach/map.h>
+#include "nand_flash_drv.h"
+#include "arch_nand.h"
+#include "wrap_nand.h"
+
+#define ZZ_DEBUG                 0
+
+//receive mtd command
+static unsigned int m_nCommand = 0;
+int page_shift;
+static unsigned long nandid = 0xFFFFFFFF;
+#define SRDPIN_USE_MUTEX
+
+/* struct semaphore m_sem_lock; */
+#ifdef SRDPIN_USE_MUTEX
+DEFINE_MUTEX(nand_lock);
+#else
+DECLARE_MUTEX(nand_lock);
+#endif
+EXPORT_SYMBOL(nand_lock);
+unsigned char m_status = 0;
+
+/* controller and mtd information */
+
+struct ak880x_nand_info {
+	/* mtd info */
+	struct nand_hw_control controller;
+	struct ak880x_nand_mtd *mtds;
+	struct ak880x_platform_nand *platform;
+
+	/* device info */
+	struct device *device;
+	struct clk *clk;
+	int mtd_count;
+};
+
+struct ak880x_nand_mtd {
+	struct mtd_info mtd;
+	struct nand_chip chip;
+	struct ak880x_nand_set *set;
+	struct ak880x_nand_info *info;
+	int scan_res;
+};
+
+extern T_PNandflash_Add g_pNF;
+
+int print_32(unsigned char *buf)
+{	
+	int i,j;
+	unsigned char *p0;
+	p0=buf;
+	printk("print_32,buf=0x%x: ",(int)p0);
+ 
+	for(i=0;i<1;i++){
+		for(j=0;j<32;j++){
+			printk("%02x,",*(p0+j+i*32));
+		}
+	printk("\n");
+	}
+
+return i*j;	
+}
+
+static struct ak880x_nand_info *to_nand_info(struct platform_device *dev)
+{
+	return platform_get_drvdata(dev);
+}
+
+static struct ak880x_platform_nand *to_nand_plat(struct platform_device *dev)
+{
+	return dev->dev.platform_data;
+}
+/* select chip */
+static void ak880x_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct ak880x_nand_mtd *nmtd;
+	struct nand_chip *this = mtd->priv;
+	nmtd = this->priv;
+	ak880x_nand_settiming(nmtd->set->cmd_len, nmtd->set->data_len);
+}
+
+/* device management functions */
+
+static int ak880x_nand_remove(struct platform_device *pdev)
+{
+	struct ak880x_nand_info *info = to_nand_info(pdev);
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz ak880x.c ak880x_nand_remove() line 132\n");
+	#endif
+	platform_set_drvdata(pdev, NULL);
+
+	if (info == NULL)
+		return 0;
+
+	/* first thing we need to do is release all our mtds
+	 * and their partitions, then go through freeing the
+	 * resources used
+	 */
+
+	if (info->mtds != NULL) {
+		struct ak880x_nand_mtd *ptr = info->mtds;
+		int mtdno;
+
+		for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
+		    pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
+			nand_release(&ptr->mtd);
+		}
+
+		kfree(info->mtds);
+	}
+
+	/* close flash contoller clock */
+	*(volatile unsigned int *)(AK88_VA_SYSCTRL + 0x0c) |= (1 << 13);
+
+	kfree(info);
+
+	return 0;
+}
+
+static unsigned int index = 0;
+static u_char ak880x_nand_read_byte(struct mtd_info *mtd)
+{
+	u_char ret_byte = 0;
+    
+    if (m_nCommand == NAND_CMD_STATUS) 
+    {
+		index = 0;
+		return m_status;
+	}
+
+	if (m_nCommand == NAND_CMD_READID) 
+    {
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak880x.c ak880x_nand_read_byte() 178 index=%d nandid=0x%lx\n", 
+               index, nandid);
+		#endif
+		ret_byte = ((nandid >> index) & 0xFF);
+		if (index == 24)
+			index = 0;
+		else
+			index += 8;
+	}
+
+	if (m_nCommand == NAND_CMD_READOOB)
+    {
+		//printk("%s: No implement yet for READOOB\n", __FUNCTION__);
+		//printk("%s: please create BBT first\n", __FUNCTION__);
+ 	}
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_read_byte() 194 ret_byte=%d\n",
+           ret_byte);
+	#endif
+	return ret_byte;
+}
+
+static void ak880x_nand_command(struct mtd_info *mtd,
+				unsigned command, int column, int page_addr)
+{
+    int block_index = 0;
+	m_nCommand = command;
+	page_shift = page_addr;
+
+	//printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 304 page=%d\n",page_addr);
+	switch (command) {
+	case NAND_CMD_RESET:
+		//printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 307 CMD:NAND_CMD_RESET\n");
+		ak880x_nand_reset(0, 0);
+		break;
+
+	case NAND_CMD_STATUS:
+		//printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 312 CMD:NAND_CMD_STATUS\n");
+		m_status = ak880x_nand_get_status(0);
+		break;
+
+	case NAND_CMD_READID:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 317 CMD:NAND_CMD_READID\n");
+		index = 0;
+		nandid = ak880x_nand_get_chipid(0);	/* only support 1st flash */
+ 		break;
+	case NAND_CMD_ERASE1:
+		if(g_pNF == NULL)
+		{
+			printk(KERN_INFO "zz ak880x.c ak880x_nand_command() 227 g_pNF==NULL error!!!\n");
+			break;
+		}
+		block_index = page_addr/128;
+        nand_eraseblock(0, block_index*128, g_pNF);
+		break;
+
+	case NAND_CMD_ERASE2:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 327 CMD:NAND_CMD_ERASE2\n");
+		break;
+        
+	case NAND_CMD_READOOB:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 331 CMD:NAND_CMD_READOOB\n");
+		break;
+        
+	case NAND_CMD_READ0:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 335 CMD:NAND_CMD_READ0\n");
+		break;
+        
+	case NAND_CMD_PAGEPROG:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 339 CMD:NAND_CMD_PAGEPROG\n");
+		break;
+        
+	case NAND_CMD_SEQIN:
+        //printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 343 CMD:NAND_CMD_SEQIN\n");
+		break;
+
+	default:
+		//printk(KERN_INFO "zz ak880x.c ak880x_nand_command() line 347 Unkown CMD:0x%x\n", command);
+		return;
+	}
+
+}
+#if 0
+#if CONFIG_MTD_PARTITIONS
+static int ak880x_nand_add_partition(struct ak880x_nand_info *info,
+				     struct ak880x_nand_mtd *mtd,
+				     struct ak880x_nand_set *set)
+{
+	if (set == NULL)
+    {   
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak880x.c ak880x_nand_add_partition() 269\n");
+		#endif
+		return add_mtd_device(&mtd->mtd);
+    }
+	if (set->nr_partitions > 0 && set->partitions != NULL) 
+    {
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak880x.c ak880x_nand_add_partition() 276\n");
+		#endif
+		return add_mtd_partitions(&mtd->mtd, set->partitions,
+					  set->nr_partitions);
+	}
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_add_partition() 282\n");
+	#endif
+	return add_mtd_device(&mtd->mtd);
+}
+#else
+static int ak880x_nand_add_partition(struct ak880x_nand_info *info,
+				     struct ak880x_nand_mtd *mtd,
+				     struct ak880x_nand_set *set)
+{
+	return add_mtd_device(&mtd->mtd);
+}
+#endif
+#endif
+static uint8_t ak880x_bbt_pattern[] = { 'b', 'b', 't' };
+
+static struct nand_bbt_descr ak880x_nand_bbt_descr = {
+	//.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	//    | NAND_BBT_1BIT,
+	.options = NAND_BBT_ABSPAGE|NAND_BBT_VERSION | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_1BIT,
+	.pages[0] = 127,
+	.offs = 13,
+	.len = 3,
+	.maxblocks = 4,
+	//.reserved_block_code = 1,
+	.pattern = ak880x_bbt_pattern
+};
+
+/* ak880x_nand_init_chip
+ *
+ * init a single instance of an chip
+*/
+
+static void ak880x_nand_init_chip(struct ak880x_nand_info *info,
+				  struct ak880x_nand_mtd *nmtd,
+				  struct ak880x_nand_set *set)
+{
+	struct nand_chip *chip = &nmtd->chip;
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_init_chip() 321\n");
+	#endif
+	chip->write_buf = ak_nand_write_buf;     //ak880x_nand_write_buf;
+	chip->read_buf =  ak_nand_read_buf;      //ak880x_nand_read_buf;   
+	chip->select_chip = ak880x_nand_select_chip;//ak_nand_select_chip; 
+	chip->chip_delay = 50;
+	chip->priv = nmtd;
+	chip->options = 0;
+	chip->options = NAND_NO_PADDING | NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;	// | NAND_SKIP_BBTSCAN;
+	chip->controller = &info->controller;
+	chip->dev_ready = NULL;
+	chip->cmdfunc = ak880x_nand_command;
+	chip->read_byte = ak880x_nand_read_byte;
+	chip->bbt_td = &ak880x_nand_bbt_descr;
+
+    chip->ecc.mode = NAND_ECC_HW;      //NAND_ECC_HW;
+	chip->ecc.read_page = ak_nand_read_page_hwecc; 
+	chip->ecc.write_page = ak_nand_write_page_hwecc; 
+	chip->ecc.read_page_raw = ak_nand_read_page_raw;
+	chip->ecc.write_page_raw = ak_nand_write_page_raw;
+	chip->ecc.read_oob = ak_nand_read_oob;  
+	chip->ecc.write_oob = ak_nand_write_oob;
+    
+	nmtd->info = info;
+	nmtd->mtd.priv = chip;
+	nmtd->mtd.owner = THIS_MODULE;
+	nmtd->set = set;
+	#if ZZ_DEBUG
+	printk("ak880x_nand_init_chip/cmd_timing=0x%x,data_timing=0x%x\n",nmtd->set->cmd_len,nmtd->set->data_len);
+	#endif
+	#if defined(L2_DMA_MODE)
+		printk("NAND driver:L2_DMA_MODE\n");
+    #else
+		printk("NAND driver:L2_CPU_MODE\n");
+	#endif
+
+}
+
+struct mtd_info *g_master = NULL; //zhangzheng add for nand char dev mount mtd partitions
+
+static int __init ak880x_nand_probe(struct platform_device *pdev)
+{
+	struct ak880x_platform_nand *plat = to_nand_plat(pdev);
+	struct ak880x_nand_info *info;
+	struct ak880x_nand_mtd *nmtd;
+	struct ak880x_nand_set *sets;
+	int err = 0;
+	int size;
+	int nr_sets;
+	int setno;
+	
+	printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 371\n");
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (info == NULL) {
+		printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 381 no memory for flash info\n");
+		err = -ENOMEM;
+		goto exit_error;
+	}
+	platform_set_drvdata(pdev, info);
+
+	spin_lock_init(&info->controller.lock);
+	init_waitqueue_head(&info->controller.wq);
+
+	ak880x_nand_inithw();
+
+	#ifndef CONFIG_MTD_DOWNLOAD_MODE
+	if(FHA_FAIL == init_fha_lib())
+	{
+		printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 375 init fha lib error return!!!\n");
+		return -ENOMEM;
+	}
+	
+	if(AK_FALSE == init_globe_para())
+	{
+		printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 380 init globe para error return!!!\n");
+		return -ENOMEM;
+	}
+	#endif
+
+	info->device = &pdev->dev;
+	info->platform = plat;
+	sets = (plat != NULL) ? plat->sets : NULL;
+	nr_sets = (plat != NULL) ? plat->nr_sets : 1;
+
+	info->mtd_count = nr_sets;
+
+	/* allocate our information */
+
+	size = nr_sets * sizeof(*info->mtds);
+	info->mtds = kzalloc(size, GFP_KERNEL);
+	if (info->mtds == NULL) {
+		printk("failed to allocate mtd storage\n");
+		err = -ENOMEM;
+		goto exit_error;
+	}
+
+	/* initialise all possible chips */
+	nmtd = info->mtds;
+    g_master = &nmtd->mtd;//zhangzheng add for nand char dev mount mtd partitions
+    #if ZZ_DEBUG
+	printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 413 nr_sets=%d\n", nr_sets);
+	#endif
+	for (setno = 0; setno < nr_sets; setno++, nmtd++)   //nr_sets==1
+	{
+		pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd,
+			 info);
+
+		ak880x_nand_init_chip(info, nmtd, sets);
+
+		nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
+        
+        #ifndef CONFIG_MTD_DOWNLOAD_MODE
+		ak_mount_partitions();
+        #endif
+        
+		if (sets != NULL)
+			sets++;
+	}
+    #if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 437 Initialize Successed!\n");
+	#endif
+	
+	#if 0
+    zz_test_nand();
+   	erase_all_flash();
+	#endif
+	
+	return 0;
+
+ exit_error:
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_probe() 444 Error Exit!\n");
+    ak880x_nand_remove(pdev);
+	return err;
+}
+
+/* PM Support */
+//#ifdef CONFIG_PM
+
+static int ak880x_nand_suspend(struct platform_device *dev, pm_message_t pm)
+{
+    //struct ak880x_nand_info *info = platform_get_drvdata(dev);
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_suspend() 456\n");
+	#endif
+	return 0;
+}
+
+static int ak880x_nand_resume(struct platform_device *dev)
+{
+	struct ak880x_nand_info *info = platform_get_drvdata(dev);
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_resume() 465\n");
+	#endif
+	if (info) 
+	{
+		ak880x_nand_inithw();
+	}
+	return 0;
+}
+/*
+#else
+#define ak880x_nand_suspend NULL
+#define ak880x_nand_resume NULL
+#endif
+*/
+/* driver device registration */
+
+static struct platform_driver ak880x_nand_driver = {
+	.probe = ak880x_nand_probe,
+	.remove = ak880x_nand_remove,
+	.suspend = ak880x_nand_suspend,
+	.resume = ak880x_nand_resume,
+	.driver = {
+		   .name = "ak880x-nand",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init ak880x_nand_init(void)
+{
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz ak880x.c ak880x_nand_init() line 495\n");
+	#endif
+	/* init_MUTEX(&m_sem_lock); */
+	/* mutex_init(&nand_lock); */
+   
+	return platform_driver_register(&ak880x_nand_driver);
+}
+
+static void __exit ak880x_nand_exit(void)
+{
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak880x.c ak880x_nand_exit() 506\n");
+	#endif
+	platform_driver_unregister(&ak880x_nand_driver);
+}
+//--------------------------------zhangzheng add start---------------------------------
+void zz_print_struct_mtd_info(struct mtd_info *mtd)
+{
+    printk(KERN_INFO "---------------------zz print struct mtd_info start-------------------------------\n");
+    printk(KERN_INFO "erasesize=%d\nerasesize_mask=%d\nwritesize=%d\noobsize=%d\n",           
+           mtd->erasesize,
+           mtd->erasesize_mask,
+           mtd->writesize, 
+           mtd->oobsize);
+    printk(KERN_INFO "oobavail=%d\nerasesize_shift=%d\nwritesize_shift=%d\n",
+           mtd->oobavail,
+           mtd->erasesize_shift,
+           mtd->writesize_shift);
+    printk(KERN_INFO "erasesize_mask=%d\nwritesize_mask=%d\n",
+           mtd->erasesize_mask,
+           mtd->writesize_mask);
+    printk(KERN_INFO "---------------------zz print struct mtd_info end---------------------------------\n");
+}
+
+void zz_print_struct_nand_chip(struct nand_chip *chip)
+{
+    printk(KERN_INFO "---------------------zz print struct nand_chip start-------------------------------\n");
+    printk(KERN_INFO "chip_delay=%d\noptions=%d\npage_shift=%d\nphys_erase_shift=%d\n",           
+           chip->chip_delay,
+           chip->options,
+           chip->page_shift,
+           chip->phys_erase_shift);
+    printk(KERN_INFO "bbt_erase_shift=%d\nchip_shift=%d\nnumchips=%d\npagemask=%d\n",           
+           chip->bbt_erase_shift,
+           chip->chip_shift,
+           chip->numchips,
+           chip->pagemask);
+    printk(KERN_INFO "pagebuf=%d\nsubpagesize=%d\ncellinfo=%d\nbadblockpos=%d\nstate=%d\n",           
+           chip->pagebuf,
+           chip->subpagesize,
+           chip->cellinfo,
+           chip->badblockpos,
+           chip->state);
+    printk(KERN_INFO "--------------------zz print struct nand_chip end---------------------------------\n");
+}
+
+//-----------------------------------zhangzheng add end-------------------------------------------------
+module_init(ak880x_nand_init);
+module_exit(ak880x_nand_exit);
+
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("AK880X MTD NAND driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/mtd/nand/ak88-nand/anyka_cpu.h b/drivers/mtd/nand/ak88-nand/anyka_cpu.h
new file mode 100644
index 00000000000..28952ba5f15
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/anyka_cpu.h
@@ -0,0 +1,642 @@
+/** @file

+ * @brief Define the register of ANYKA CPU

+ *

+ * Define the register address and bit map for system.

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author xuchang

+ * @date 2008-01-05

+ * @version 1.0

+ * @note

+ * ¸ÃÎļþ¶¨ÒåËùÓÐÇý¶¯Ä£¿éµÄ¼Ä´æÆ÷£¬²»µÃÔÚÆäËûµØ·½×ö¼Ä´æÆ÷¶¨Òå!!

+ * ¼Ä´æÆ÷µÄ붨ÒåÔ­ÔòÉÏ·ÅÔÚ¸÷¸öÇý¶¯Ä£¿éµÄÍ·ÎļþÖж¨Ò壬Èç¹û¶ÔÓ¦µÄÇý¶¯Ä£¿é̫СûÓÐÍ·Îļþ£¬

+ * Ôò¿É·ÅÔÚ´Ë´¦¶¨Òå

+ */

+#ifndef _ANYKA_CPU_H_

+#define _ANYKA_CPU_H_

+#include <mach-anyka/anyka_types.h>

+

+/** @defgroup ANYKA_CPU  

+ *      @ingroup Drv_Lib

+ */

+/*@{*/

+

+

+/** @{@name Base Address Define

+ *      The base address of system memory space is define here. 

+ *      Include memory assignment and module base address define.

+ */

+ /**Memory assignment*/

+#define CHIP_CONF_BASE_ADDR                             0x08000000      // chip configurations

+#define USB_BASE_ADDR                                   0x70000000      // USB

+#define L2_BUF_MEM_BASE_ADDR                            0x48000000      //L2 Buffer start address

+/** @} */

+

+

+/** @{@name CPU working mode

+ */

+#define ANYKA_CPU_Mode_USR                              0x10

+#define ANYKA_CPU_Mode_FIQ                              0x11

+#define ANYKA_CPU_Mode_IRQ                              0x12

+#define ANYKA_CPU_Mode_SVC                              0x13

+#define ANYKA_CPU_Mode_ABT                              0x17

+#define ANYKA_CPU_Mode_UNDEF                            0x1B

+#define ANYKA_CPU_Mode_SYS                              0x1F            

+#define ANYKA_CPU_I_Bit                                 0x80

+#define ANYKA_CPU_F_Bit                                 0x40

+/** @} */

+

+/** @{@name System Control Register

+ *      Define system control register here, include CLOCK/INT/RESET

+ */

+#define CLOCK_CTRL_REG                                  (CHIP_CONF_BASE_ADDR + 0x0000000C)      // module clock control(switch)

+#define CLOCK_CTRL2_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000008)      // module clock control(switch)

+#define RESET_CTRL_REG                                  (CHIP_CONF_BASE_ADDR + 0x0000000C)      // module software reset control register

+#define STANDBY_REG                                     (CHIP_CONF_BASE_ADDR + 0x00000004)      // module standby register

+#define IRQINT_MASK_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000034)      // module IRQ interrupt mask register, 1: mask; 0:unmask(default);

+#define FRQINT_MASK_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000038)      // module FRQ interrupt mask register, 1: mask; 0:unmask(default);

+#define INT_STATUS_REG                                  (CHIP_CONF_BASE_ADDR + 0x000000CC)      // module interrupt status register

+#define INT_SYS_MODULE_REG                              (CHIP_CONF_BASE_ADDR + 0x0000004C)      // system module interrupt control register

+#define CLOCK_DIV_REG                                   (CHIP_CONF_BASE_ADDR + 0x00000004)      // clock divider register 1

+#define CLOCK2X_CTRL_REG                                (CHIP_CONF_BASE_ADDR + 0x00000004)      // clock2x control register,1: 2*ASIC clock; 0: ASIC clock

+#define CLOCK3X_CTRL_REG                                (CHIP_CONF_BASE_ADDR + 0x00000064)      //bit28 => 1: asic = pll1_clock /3, 0: refresh to bit[6..8] of 0x08000004 register 

+#define PLL_NPARAM_REG                                  (CHIP_CONF_BASE_ADDR + 0x000000dc)      // n configuration register,PLL_Clk = 4*M/N

+/** @} */

+

+/** @{@name Interrupt bit map define

+ */ 

+/** interrupt status register bit map*/

+#define INT_STATUS_LCD_BIT                              (1 << 1)

+#define INT_STATUS_CAMERA_BIT                           (1 << 2)

+#define INT_STATUS_AUDIO_BIT                            (1 << 5)

+#define INT_STATUS_L2_BIT                               (1 << 10)

+#define INT_STATUS_UART4_BIT                            (1 << 13)

+#define INT_STATUS_UART3_BIT                            (1 << 14)

+#define INT_STATUS_UART2_BIT                            (1 << 15)

+#define INT_STATUS_UART1_BIT                            (1 << 16)

+#define INT_STATUS_SPI2_BIT                             (1 << 17)

+#define INT_STATUS_SPI1_BIT                             (1 << 18)

+#define INT_STATUS_SDIO_BIT                             (1 << 21)

+#define INT_STATUS_MMCSD_BIT                            (1 << 22)

+#define INT_STATUS_USB_BIT                              (1 << 25)

+#define INT_STATUS_SYS_MODULE_BIT                       (1 << 27)

+                                        

+//level 2 interrupt status bit map      

+#define INT_STATUS_TS_BIT                               (1 << 16)

+#define INT_STATUS_TIMER5_BIT                           (1 << 17)

+#define INT_STATUS_TIMER4_BIT                           (1 << 18)

+#define INT_STATUS_TIMER3_BIT                           (1 << 19)

+#define INT_STATUS_TIMER2_BIT                           (1 << 20)

+#define INT_STATUS_TIMER1_BIT                           (1 << 21)

+#define INT_STATUS_ASICCLK_BIT                          (1 << 22)

+#define INT_STATUS_WGPIO_BIT                            (1 << 23)

+#define INT_STATUS_RTC_READY_BIT                        (1 << 24)

+#define INT_STATUS_RTC_ALARM_BIT                        (1 << 25)

+#define INT_STATUS_GPIO_BIT                             (1 << 26)

+

+/* define the level1 interrupt valid bits */

+#define INT_STATUS_NBITS                                27

+

+/** IRQ interrupt mask register bit map*/

+#define IRQ_MASK_LCD_BIT                                (1 << 1)

+#define IRQ_MASK_CAMERA_BIT                             (1 << 2)

+#define IRQ_MASK_AUDIO_BIT                              (1 << 5)

+#define IRQ_MASK_L2_BIT                                 (1 << 10)

+#define IRQ_MASK_UART4_BIT                              (1 << 13)

+#define IRQ_MASK_UART3_BIT                              (1 << 14)

+#define IRQ_MASK_UART2_BIT                              (1 << 15)

+#define IRQ_MASK_UART1_BIT                              (1 << 16)

+#define IRQ_MASK_SPI2_BIT                               (1 << 17)

+#define IRQ_MASK_SPI1_BIT                               (1 << 18)

+#define IRQ_MASK_SDIO_BIT                               (1 << 21)

+#define IRQ_MASK_MMCSD_BIT                              (1 << 22)

+#define IRQ_MASK_USB_BIT                                (1 << 25)

+#define IRQ_MASK_SYS_MODULE_BIT                         (1 << 27)

+#define IRQ_MASK_USB_FS_BIT                             (1 << 23)

+

+//level 2 interrupt mask bit map

+#define IRQ_MASK_TS_BIT                                 1

+#define IRQ_MASK_TIMER5_BIT                             (1 << 1)

+#define IRQ_MASK_TIMER4_BIT                             (1 << 2)

+#define IRQ_MASK_TIMER3_BIT                             (1 << 3)

+#define IRQ_MASK_TIMER2_BIT                             (1 << 4)

+#define IRQ_MASK_TIMER1_BIT                             (1 << 5)

+#define IRQ_MASK_ASICCLK_BIT                            (1 << 6)

+#define IRQ_MASK_WGPIO_BIT                              (1 << 7)

+#define IRQ_MASK_RTC_READY_BIT                          (1 << 8)

+#define IRQ_MASK_RTC_ALARM_BIT                          (1 << 9)

+#define IRQ_MASK_GPIO_BIT                               (1 << 10)

+/** @} */

+

+

+/** @{@name SDRAM&DMA register and bit map define

+ */ 

+#define DMA_CTRL_BASE_ADDR                              (0x2002d000)

+#define DMA_PRIORITY_CTRL_REG1                          (DMA_CTRL_BASE_ADDR + 0x0000000c)

+#define DMA_PRIORITY_CTRL_REG2                          (DMA_CTRL_BASE_ADDR + 0x00000010)

+#define AHB_PRIORITY_CTRL_REG                           (DMA_CTRL_BASE_ADDR + 0x00000014)

+#define SDRAM_CFG_REG1                                  (DMA_CTRL_BASE_ADDR + 0x0)

+#define SDRAM_CFG_REG2                                  (DMA_CTRL_BASE_ADDR + 0x4)

+#define SDRAM_CFG_REG3                                  (DMA_CTRL_BASE_ADDR + 0x8)

+/** @} */

+

+

+/** @{@name L2 memory register and bit map define

+ */ 

+#define L2_BASE_ADDR                                    (0xf022c000)       //(0x2002c000)

+#define L2_DMA_ADDR                                     (L2_BASE_ADDR+0x00)

+#define L2_DMA_CNT                                      (L2_BASE_ADDR+0x40)

+#define L2_DMA_REQ                                      (L2_BASE_ADDR+0x80)

+#define L2_FRAC_ADDR                                    (L2_BASE_ADDR+0x84)

+#define L2_COMBUF_CFG                                   (L2_BASE_ADDR+0x88)

+#define L2_UARTBUF_CFG                                  (L2_BASE_ADDR+0x8c)

+#define L2_ASSIGN_REG1                                  (L2_BASE_ADDR+0x90)

+#define L2_ASSIGN_REG2                                  (L2_BASE_ADDR+0x94)

+#define L2_LDMA_CFG                                     (L2_BASE_ADDR+0x98)

+#define L2_INT_ENA                                      (L2_BASE_ADDR+0x9c)

+#define L2_STAT_REG1                                    (L2_BASE_ADDR+0xa0)

+#define L2_STAT_REG2                                    (L2_BASE_ADDR+0xa8)

+/** @} */

+

+

+/** @{@name Nandflash ECC Controller Define 

+ *      Define the register and bit map of nandflash controller

+ */

+// ECC

+#define FLASH_ECC_REG0                                  (0xf022b000)           //0x2002b000

+#define FLASH_ECC_REPAIR_REG0                           (FLASH_ECC_REG0+0x4)

+// NF controller

+#define FLASH_CTRL_REG0                                 (0xf022a100)           //(0x2002a100)

+#define FLASH_CTRL_REG20                                (FLASH_CTRL_REG0+0x50)

+#define FLASH_CTRL_REG21                                (FLASH_CTRL_REG0+0x54)

+#define FLASH_CTRL_REG22                                (FLASH_CTRL_REG0+0x58)

+#define FLASH_CTRL_REG23                                (FLASH_CTRL_REG0+0x5c)

+#define FLASH_CTRL_REG24                                (FLASH_CTRL_REG0+0x60)

+/** @} */

+

+

+/** @{@name RTC module register and bit map define

+ */

+#define RTC_MODULE_BASE_ADDR                            0x08000000      // RTC

+#define RTC_CONFIG_REG                                  (RTC_MODULE_BASE_ADDR + 0x50)   // rtc confgiuration

+#define RTC_BACK_DAT_REG                                (RTC_MODULE_BASE_ADDR + 0x54)   // rtc read back data

+#define RTC_CLOCK_DIV_REG                               (RTC_MODULE_BASE_ADDR + 0x04)   // enable/disable wakeup function

+#define RTC_WAKEUP_GPIO_P_REG                           (RTC_MODULE_BASE_ADDR + 0x3C)   // wakeup GPIO polarity

+#define RTC_WAKEUP_GPIO_C_REG                           (RTC_MODULE_BASE_ADDR + 0x40)   // clear wakeup GPIO status

+#define RTC_WAKEUP_GPIO_E_REG                           (RTC_MODULE_BASE_ADDR + 0x44)   // enable wake-up GPIO wakeup function

+#define RTC_WAKEUP_GPIO_S_REG                           (RTC_MODULE_BASE_ADDR + 0x48)   // wakeup GPIO status

+/** @} */

+

+

+/** @{@name LCD module register and bit map define

+ */ 

+#define LCD_MODULE_BASE_ADDR                            0x20010000

+#define LCD_TOP_CONFIGURE_REG                           (LCD_MODULE_BASE_ADDR | 0x0000)

+#define LCD_MPU_CTL_REG                                 (LCD_MODULE_BASE_ADDR | 0x0004)

+#define LCD_RST_PIN_REG                                 (LCD_MODULE_BASE_ADDR | 0x0008)

+#define LCD_MPU_READ_REG                                (LCD_MODULE_BASE_ADDR | 0x000C)

+#define LCD_RGB_CTL_REG1                                (LCD_MODULE_BASE_ADDR | 0x0010)

+#define LCD_RGB_CTL_REG2                                (LCD_MODULE_BASE_ADDR | 0x0014)

+#define LCD_RGB_VIRTUAL_SIZE_REG                        (LCD_MODULE_BASE_ADDR | 0x0018)

+#define LCD_RGB_VIRTUAL_OFFSET_REG                      (LCD_MODULE_BASE_ADDR | 0x001C)

+

+#define LCD_OSD_ADDR_REG                                (LCD_MODULE_BASE_ADDR | 0x20)

+#define LCD_OSD_OFFSET_REG                              (LCD_MODULE_BASE_ADDR | 0x24)

+#define LCD_OSD_F_COLOR1_REG                            (LCD_MODULE_BASE_ADDR | 0x28)

+#define LCD_OSD_F_COLOR2_REG                            (LCD_MODULE_BASE_ADDR | 0x2C)

+#define LCD_OSD_F_COLOR3_REG                            (LCD_MODULE_BASE_ADDR | 0x30)

+#define LCD_OSD_F_COLOR4_REG                            (LCD_MODULE_BASE_ADDR | 0x34)

+#define LCD_OSD_F_COLOR5_REG                            (LCD_MODULE_BASE_ADDR | 0xd0)

+#define LCD_OSD_F_COLOR6_REG                            (LCD_MODULE_BASE_ADDR | 0xd4)

+#define LCD_OSD_F_COLOR7_REG                            (LCD_MODULE_BASE_ADDR | 0xd8)

+#define LCD_OSD_F_COLOR8_REG                            (LCD_MODULE_BASE_ADDR | 0xdc)

+#define LCD_OSD_SIZE_ALPHA_REG                          (LCD_MODULE_BASE_ADDR | 0x38)

+

+#define LCD_GRB_BACKGROUND_REG                          (LCD_MODULE_BASE_ADDR | 0x003c)

+#define LCD_RGB_CTL_REG3                                (LCD_MODULE_BASE_ADDR | 0x0040)

+#define LCD_RGB_CTL_REG4                                (LCD_MODULE_BASE_ADDR | 0x0044)

+#define LCD_RGB_CTL_REG5                                (LCD_MODULE_BASE_ADDR | 0x0048)

+#define LCD_RGB_CTL_REG6                                (LCD_MODULE_BASE_ADDR | 0x004C)

+#define LCD_RGB_CTL_REG7                                (LCD_MODULE_BASE_ADDR | 0x0050)

+#define LCD_RGB_CTL_REG8                                (LCD_MODULE_BASE_ADDR | 0x0054)

+#define LCD_RGB_CTL_REG9                                (LCD_MODULE_BASE_ADDR | 0x0058)

+

+#define LCD_Y1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x005c)

+#define LCD_U1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0060) 

+#define LCD_V1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0064) 

+#define LCD_YUV1_H_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x0068) 

+#define LCD_YUV1_V_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x006c) 

+#define LCD_YUV1_VIR_SIZE_REG                           (LCD_MODULE_BASE_ADDR | 0x0078) 

+#define LCD_YUV1_VIR_OFFSET_REG                         (LCD_MODULE_BASE_ADDR | 0x007c) 

+#define LCD_YUV1_SCALER_INFO_REG                        (LCD_MODULE_BASE_ADDR | 0x0070) 

+#define LCD_YUV1_DISPLAY_INFO_REG                       (LCD_MODULE_BASE_ADDR | 0x0074)

+

+#define LCD_Y2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0080)

+#define LCD_U2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0084) 

+#define LCD_V2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0088) 

+#define LCD_YUV2_H_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x008c) 

+#define LCD_YUV2_V_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x0090) 

+#define LCD_YUV2_SCALER_INFO_REG                        (LCD_MODULE_BASE_ADDR | 0x0094) 

+#define LCD_YUV2_DISPLAY_INFO_REG                       (LCD_MODULE_BASE_ADDR | 0x0098)

+

+#define LCD_RGB_OFFSET_REG                              (LCD_MODULE_BASE_ADDR | 0x00A8)

+#define LCD_RGB_SIZE_REG                                (LCD_MODULE_BASE_ADDR | 0x00AC)

+#define LCD_PANEL_SIZE_REG                              (LCD_MODULE_BASE_ADDR | 0x00B0)

+#define LCD_REG_CONFIG_REG                              (LCD_MODULE_BASE_ADDR | 0x00B4)

+#define LCD_LCD_GO_REG                                  (LCD_MODULE_BASE_ADDR | 0x00B8)

+#define LCD_LCD_STATUS                                  (LCD_MODULE_BASE_ADDR | 0x00BC)

+#define LCD_LCD_INTERRUPT_MASK                          (LCD_MODULE_BASE_ADDR | 0x00C0)

+#define LCD_SOFTWARE_CTL_REG                            (LCD_MODULE_BASE_ADDR | 0x00C8)

+#define LCD_TVOUT_CTL_REG                               (LCD_MODULE_BASE_ADDR | 0x00CC)

+#define LCD_CLK_CTL_REG                                 (LCD_MODULE_BASE_ADDR | 0x00E8)

+/** @} */

+

+

+/** @{@name GUI module register and bit map define

+ */

+#define GUI_BASE_ADDR                                   0x20022000

+#define GUI_SCALSRCADDR1_ADDR                           (GUI_BASE_ADDR+0x108)   // Input image start address 1

+#define GUI_SCALSRCADDR2_ADDR                           (GUI_BASE_ADDR+0x10c) // Input image start address 2

+#define GUI_SCALSRCADDR3_ADDR                           (GUI_BASE_ADDR+0x110) // Input image start address 3

+#define GUI_SCALSRCSTRD_ADDR                            (GUI_BASE_ADDR+0x118)   // Input image line stride

+#define GUI_SCALDSTADDR_ADDR                            (GUI_BASE_ADDR+0x11c)   // Output image start address

+#define GUI_SCALSRCRECT_ADDR                            (GUI_BASE_ADDR+0x114)   // Input image rectangle dimensions

+#define GUI_SCALDSTRECT_ADDR                            (GUI_BASE_ADDR+0x120)   // Output image rectangle dimensions

+#define GUI_SCALDSTSTRD_ADDR                            (GUI_BASE_ADDR+0x124)   // Output image line stride

+#define GUI_SCALRATIO_ADDR                              (GUI_BASE_ADDR+0x104)   // Scaling parameters, scale=8192/ILX[8:0]

+#define GUI_POINT1_ADDR                                 (GUI_BASE_ADDR+0x0c)    // Destination Offset

+#define GUI_CMD_ADDR                                    (GUI_BASE_ADDR+0x04)    // Command

+#define GUI_SCALCTRL_ADDR                               (GUI_BASE_ADDR+0x100)   // Color Space conversion and scaling control

+#define GUI_SCALOFFSET_ADDR                             (GUI_BASE_ADDR+0x128)   // Output image line stride

+/** @} */

+

+/** @{@name IMAGE sensor module register and bit map define

+ */

+#define IMAGE_MODULE_BASE_ADDR                          0x20030000      // image sensor

+#define IMG_CMD_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0000)

+#define IMG_HINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0004)

+#define IMG_HINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0008)

+#define IMG_VINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x000C)

+#define IMG_VINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0010)

+                                                        

+#define IMG_YADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0018)

+#define IMG_UADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x001c)

+#define IMG_VADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0020)

+#define IMG_RGBADDR_ODD                                 (IMAGE_MODULE_BASE_ADDR | 0x0024)

+#define IMG_YADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0028)

+#define IMG_UADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x002c)

+#define IMG_VADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0030)

+#define IMG_RGBADDR_EVE                                 (IMAGE_MODULE_BASE_ADDR | 0x0034)

+#define IMG_CONFIG_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0040)

+#define IMG_STATUS_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0060)

+#define IMG_NUM_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0080)

+

+#define MUL_FUN_CTL_REG                                 (CHIP_CONF_BASE_ADDR | 0x0058)

+/** @} */

+

+

+/** @{@name UART module register and bit map define

+ */

+#define UART_MODULE_BASE_ADDR                           0x20026000      // UART

+#define UART0_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00000000)

+#define UART1_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00001000)

+#define UART2_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00002000)

+#define UART3_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00003000)

+                                                        

+#define UART_CFG_REG1                                   (0x00)

+#define UART_CFG_REG2                                   (0x04)

+#define UART_DATA_CFG                                   (0x08)

+#define UART_RX_THREINT                                 (0x0c)

+/** @} */

+

+/** @{@name SPI module register and bit map define

+ */

+#define SPI_MODULE_BASE_ADDR                            0x20020000      // SPI

+#define SPI0_BASE_ADDR                                  (SPI_MODULE_BASE_ADDR + 0x00004000)

+#define SPI1_BASE_ADDR                                  (SPI_MODULE_BASE_ADDR + 0x00005000)

+                                                        

+#define ASPEN_SPI_CTRL                                  (0x00)

+#define ASPEN_SPI_STA                                   (0x04)

+#define ASPEN_SPI_INTENA                                (0x08)

+#define ASPEN_SPI_NBR                                   (0x0c)

+#define ASPEN_SPI_TX_EXBUF                              (0x10)

+#define ASPEN_SPI_RX_EXBUF                              (0x14)

+#define ASPEN_SPI_TX_INBUF                              (0x18)

+#define ASPEN_SPI_RX_INBUF                              (0x1c)

+#define ASPEN_SPI_RTIM                                  (0x20)

+/** @} */

+

+/** @{@name USB register and bit map define

+ *  Define register to control USB port and the bit map of the register

+ */

+#define USB_CONTROL_REG                                 (0x08000058)

+#define USB_FIFO_EP0                                    (USB_BASE_ADDR + 0x0020)

+#define USB_REG_FADDR                                   (USB_BASE_ADDR + 0x0000)

+#define USB_REG_POWER                                   (USB_BASE_ADDR + 0x0001)

+#define USB_REG_INTRTX1                                 (USB_BASE_ADDR + 0x0002)

+#define USB_REG_INTRTX2                                 (USB_BASE_ADDR + 0x0003)

+#define USB_REG_INTRRX1                                 (USB_BASE_ADDR + 0x0004)

+#define USB_REG_INTRRX2                                 (USB_BASE_ADDR + 0x0005)

+#define USB_REG_INTRTX1E                                (USB_BASE_ADDR + 0x0006)

+#define USB_REG_INTRTX2E                                (USB_BASE_ADDR + 0x0007)

+#define USB_REG_INTRRX1E                                (USB_BASE_ADDR + 0x0008)

+#define USB_REG_INTRRX2E                                (USB_BASE_ADDR + 0x0009)

+#define USB_REG_INTRUSB                                 (USB_BASE_ADDR + 0x000A)

+#define USB_REG_INTRUSBE                                (USB_BASE_ADDR + 0x000B)

+#define USB_REG_FRAME1                                  (USB_BASE_ADDR + 0x000C)

+#define USB_REG_FRAME2                                  (USB_BASE_ADDR + 0x000D)

+#define USB_REG_INDEX                                   (USB_BASE_ADDR + 0x000E)

+#define USB_REG_TESEMODE                                (USB_BASE_ADDR + 0x000F)

+#define USB_REG_DEVCTL                                  (USB_BASE_ADDR + 0x0060)

+#define USB_REG_TXMAXP0                                 (USB_BASE_ADDR + 0x0010)

+#define USB_REG_TXMAXP1                                 (USB_BASE_ADDR + 0x0010)

+#define USB_REG_CSR0                                    (USB_BASE_ADDR + 0x0012)

+#define USB_REG_TXCSR1                                  (USB_BASE_ADDR + 0x0012)

+#define USB_REG_CSR02                                   (USB_BASE_ADDR + 0x0013)

+#define USB_REG_TXCSR2                                  (USB_BASE_ADDR + 0x0013)

+#define USB_REG_RXMAXP1                                 (USB_BASE_ADDR + 0x0014)

+#define USB_REG_RXMAXP2                                 (USB_BASE_ADDR + 0x0015)

+#define USB_REG_RXCSR1                                  (USB_BASE_ADDR + 0x0016)

+#define USB_REG_RXCSR2                                  (USB_BASE_ADDR + 0x0017)

+#define USB_REG_COUNT0                                  (USB_BASE_ADDR + 0x0018)

+#define USB_REG_RXCOUNT1                                (USB_BASE_ADDR + 0x0018)

+#define USB_REG_RXCOUNT2                                (USB_BASE_ADDR + 0x0019)

+#define USB_REG_TXTYPE                                  (USB_BASE_ADDR + 0x001A)

+#define USB_REG_RXTYPE                                  (USB_BASE_ADDR + 0x001C)

+#define USB_REG_RXINTERVAL                              (USB_BASE_ADDR + 0x001D)

+#define USB_REG_NAKLIMIT0                               (USB_BASE_ADDR + 0x001B)

+                                                        

+#define USB_EP0_TX_COUNT                                (USB_BASE_ADDR + 0x0330)

+#define USB_EP2_TX_COUNT                                (USB_BASE_ADDR + 0x0334)

+                                                        

+#define USB_FORBID_WRITE_REG                            (USB_BASE_ADDR + 0x0338)

+                                                        

+#define USB_START_PRE_READ_REG                          (USB_BASE_ADDR + 0x033C)

+#define USB_FS_SPEED_REG                                (USB_BASE_ADDR + 0x0344)

+

+#define USB_FS_HOST_BASE_ADDR                           0x70000800

+#define USB_FS_HOST_REG_FADDR                           (USB_FS_HOST_BASE_ADDR + 0x0000)

+#define USB_FS_HOST_REG_POWER                           (USB_FS_HOST_BASE_ADDR + 0x0001)

+#define USB_FS_HOST_REG_INTRTX1                         (USB_FS_HOST_BASE_ADDR + 0x0002)

+#define USB_FS_HOST_REG_INTRTX2                         (USB_FS_HOST_BASE_ADDR + 0x0003)

+#define USB_FS_HOST_REG_INTRRX1                         (USB_FS_HOST_BASE_ADDR + 0x0004)

+#define USB_FS_HOST_REG_INTRRX2                         (USB_FS_HOST_BASE_ADDR + 0x0005)

+#define USB_FS_HOST_REG_INTRTX1E                        (USB_FS_HOST_BASE_ADDR + 0x0006)

+#define USB_FS_HOST_REG_INTRTX2E                        (USB_FS_HOST_BASE_ADDR + 0x0007)

+#define USB_FS_HOST_REG_INTRRX1E                        (USB_FS_HOST_BASE_ADDR + 0x0008)

+#define USB_FS_HOST_REG_INTRRX2E                        (USB_FS_HOST_BASE_ADDR + 0x0009)

+#define USB_FS_HOST_REG_INTRUSB                         (USB_FS_HOST_BASE_ADDR + 0x000A)

+#define USB_FS_HOST_REG_INTRUSBE                        (USB_FS_HOST_BASE_ADDR + 0x000B)

+#define USB_FS_HOST_REG_FRAME1                          (USB_FS_HOST_BASE_ADDR + 0x000C)

+#define USB_FS_HOST_REG_FRAME2                          (USB_FS_HOST_BASE_ADDR + 0x000D)

+#define USB_FS_HOST_REG_INDEX                           (USB_FS_HOST_BASE_ADDR + 0x000E)

+#define USB_FS_HOST_REG_TESEMODE                        (USB_FS_HOST_BASE_ADDR + 0x000F)

+#define USB_FS_HOST_REG_DEVCTL                          (USB_FS_HOST_BASE_ADDR + 0x0060)

+#define USB_FS_HOST_REG_TXMAXP0                         (USB_FS_HOST_BASE_ADDR + 0x0010)

+#define USB_FS_HOST_REG_TXMAXP1                         (USB_FS_HOST_BASE_ADDR + 0x0010)

+#define USB_FS_HOST_REG_CSR0                            (USB_FS_HOST_BASE_ADDR + 0x0012)

+#define USB_FS_HOST_REG_TXCSR1                          (USB_FS_HOST_BASE_ADDR + 0x0012)

+#define USB_FS_HOST_REG_CSR02                           (USB_FS_HOST_BASE_ADDR + 0x0013)

+#define USB_FS_HOST_REG_TXCSR2                          (USB_FS_HOST_BASE_ADDR + 0x0013)

+#define USB_FS_HOST_REG_RXMAXP1                         (USB_FS_HOST_BASE_ADDR + 0x0014)

+#define USB_FS_HOST_REG_RXMAXP2                         (USB_FS_HOST_BASE_ADDR + 0x0015)

+#define USB_FS_HOST_REG_RXCSR1                          (USB_FS_HOST_BASE_ADDR + 0x0016)

+#define USB_FS_HOST_REG_RXCSR2                          (USB_FS_HOST_BASE_ADDR + 0x0017)

+#define USB_FS_HOST_REG_COUNT0                          (USB_FS_HOST_BASE_ADDR + 0x0018)

+#define USB_FS_HOST_REG_RXCOUNT1                        (USB_FS_HOST_BASE_ADDR + 0x0018)

+#define USB_FS_HOST_REG_RXCOUNT2                        (USB_FS_HOST_BASE_ADDR + 0x0019)

+#define USB_FS_HOST_REG_TXTYPE                          (USB_FS_HOST_BASE_ADDR + 0x001A)

+#define USB_FS_HOST_REG_RXTYPE                          (USB_FS_HOST_BASE_ADDR + 0x001C)

+#define USB_FS_HOST_REG_RXINTERVAL                      (USB_FS_HOST_BASE_ADDR + 0x001D)

+#define USB_FS_HOST_REG_NAKLIMIT0                       (USB_FS_HOST_BASE_ADDR + 0x001B)

+#define USB_FS_HOST_REG_FIFOSIZE                        (USB_FS_HOST_BASE_ADDR + 0x001F)

+

+#define USB_L2_CONTROL_FIFO                             (0x48001500)

+                                                        

+#define USB_FS_FIFO_EP0                                 0x70000820

+#define USB_FS_FIFO_EP1                                 0x70000824

+#define USB_FS_FIFO_EP2                                 0x70000828

+#define USB_FS_FIFO_EP3                                 0x7000082c 

+                                                        

+/**  USB DMA */                         

+#define USB_FS_HOST_DMA_INTR                            (USB_FS_HOST_BASE_ADDR + 0x0200)

+#define USB_FS_HOST_DMA_CNTL_1                          (USB_FS_HOST_BASE_ADDR + 0x0204)

+#define USB_FS_HOST_DMA_ADDR_1                          (USB_FS_HOST_BASE_ADDR + 0x0208)

+#define USB_FS_HOST_DMA_COUNT_1                         (USB_FS_HOST_BASE_ADDR + 0x020c)

+#define USB_FS_HOST_DMA_CNTL_2                          (USB_FS_HOST_BASE_ADDR + 0x0214)

+#define USB_FS_HOST_DMA_ADDR_2                          (USB_FS_HOST_BASE_ADDR + 0x0218)

+#define USB_FS_HOST_DMA_COUNT_2                         (USB_FS_HOST_BASE_ADDR + 0x021c)

+

+/**Dynamic FIFO sizing   JUST FOR HOST  */

+#define USB_REG_TXFIFO1                                 (USB_BASE_ADDR + 0x001C)

+#define USB_REG_TXFIFO2                                 (USB_BASE_ADDR + 0x001D)

+#define USB_REG_RXFIFO1                                 (USB_BASE_ADDR + 0x001E)

+#define USB_REG_RXFIFO2                                 (USB_BASE_ADDR + 0x001F)

+                                                        

+#define USB_REG_FIFOSIZE                                (USB_BASE_ADDR + 0x001F)

+                                                        

+/**  USB DMA */                                         

+#define USB_DMA_INTR                                    (USB_BASE_ADDR + 0x0200)

+#define USB_DMA_CNTL_1                                  (USB_BASE_ADDR + 0x0204)

+#define USB_DMA_ADDR_1                                  (USB_BASE_ADDR + 0x0208)

+#define USB_DMA_COUNT_1                                 (USB_BASE_ADDR + 0x020c)

+#define USB_DMA_CNTL_2                                  (USB_BASE_ADDR + 0x0214)

+#define USB_DMA_ADDR_2                                  (USB_BASE_ADDR + 0x0218)

+#define USB_DMA_COUNT_2                                 (USB_BASE_ADDR + 0x021c)                                 

+#define USB_FS_SPEED_REG                                (USB_BASE_ADDR + 0x0344)

+/** @} */

+

+

+/** @{@name SDMMC/SDIO module register and bit map define

+ */

+#define SD_MMC_BASE_ADDR                                0x20020000       /*mmc_sd interface*/

+#define SDIO_BASE_ADDR                                  0x20021000       /*sdio interface*/

+#define SD_CLK_CTRL_REG                                 ( SD_MMC_BASE_ADDR + 0x04  )

+#define SD_ARGUMENT_REG                                 ( SD_MMC_BASE_ADDR + 0x08  )

+#define SD_CMD_REG                                      ( SD_MMC_BASE_ADDR + 0x0C  )

+#define SD_RESP_CMD_REG                                 ( SD_MMC_BASE_ADDR + 0x10  )

+#define SD_RESP_REG0                                    ( SD_MMC_BASE_ADDR + 0x14  )

+#define SD_RESP_REG1                                    ( SD_MMC_BASE_ADDR + 0x18  )

+#define SD_RESP_REG2                                    ( SD_MMC_BASE_ADDR + 0x1c  )

+#define SD_RESP_REG3                                    ( SD_MMC_BASE_ADDR + 0x20  )

+#define SD_DATA_TIM_REG                                 ( SD_MMC_BASE_ADDR + 0x24  )

+#define SD_DATA_LEN_REG                                 ( SD_MMC_BASE_ADDR + 0x28  )

+#define SD_DATA_CTRL_REG                                ( SD_MMC_BASE_ADDR + 0x2C  )

+#define SD_DATA_COUT_REG                                ( SD_MMC_BASE_ADDR + 0x30  )

+#define SD_INT_STAT_REG                                 ( SD_MMC_BASE_ADDR + 0x34  )

+#define SD_INT_ENABLE                                   ( SD_MMC_BASE_ADDR + 0x38  )

+#define SD_DMA_MODE_REG                                 ( SD_MMC_BASE_ADDR + 0x3C  )

+#define SD_CPU_MODE_REG                                 ( SD_MMC_BASE_ADDR + 0x40  )

+                                                        

+#define SDIO_CLK_CTRL_REG                               ( SDIO_BASE_ADDR + 0x04  )

+#define SDIO_ARGUMENT_REG                               ( SDIO_BASE_ADDR + 0x08  )

+#define SDIO_CMD_REG                                    ( SDIO_BASE_ADDR + 0x0C  )

+#define SDIO_RESP_CMD_REG                               ( SDIO_BASE_ADDR + 0x10  )

+#define SDIO_RESP_REG0                                  ( SDIO_BASE_ADDR + 0x14  )

+#define SDIO_RESP_REG1                                  ( SDIO_BASE_ADDR + 0x18  )

+#define SDIO_RESP_REG2                                  ( SDIO_BASE_ADDR + 0x1c  )

+#define SDIO_RESP_REG3                                  ( SDIO_BASE_ADDR + 0x20  )

+#define SDIO_DATA_TIM_REG                               ( SDIO_BASE_ADDR + 0x24  )

+#define SDIO_DATA_LEN_REG                               ( SDIO_BASE_ADDR + 0x28  )

+#define SDIO_DATA_CTRL_REG                              ( SDIO_BASE_ADDR + 0x2C  )

+#define SDIO_DATA_COUT_REG                              ( SDIO_BASE_ADDR + 0x30  )

+#define SDIO_INT_STAT_REG                               ( SDIO_BASE_ADDR + 0x34  )

+#define SDIO_INT_ENABLE                                 ( SDIO_BASE_ADDR + 0x38  )

+#define SDIO_DMA_MODE_REG                               ( SDIO_BASE_ADDR + 0x3C  )

+#define SDIO_CPU_MODE_REG                               ( SDIO_BASE_ADDR + 0x40  )

+/** @} */

+

+

+/** @{@name ANALOG module register and bit map define

+ */

+#define ADC_MODULE_BASE_ADDR                            0x08000000      // Analog 

+#define ADC_CONTROL1                                    (ADC_MODULE_BASE_ADDR + 0x60)

+#define ADC_CLK_DIV                                     (ADC_MODULE_BASE_ADDR + 0x08)

+#define ADC_CLK_DIV1                                    (ADC_MODULE_BASE_ADDR + 0x04)

+#define ANLSOFT_CONTROL                                 (ADC_MODULE_BASE_ADDR + 0x34)

+#define USB_CONTROL                                     (ADC_MODULE_BASE_ADDR + 0x44)

+#define X_COORDINATE_REG                                (ADC_MODULE_BASE_ADDR + 0x68)

+#define Y_COORDINATE_REG                                (ADC_MODULE_BASE_ADDR + 0x6c)

+#define TS_CONTROL_REG2                                 (ADC_MODULE_BASE_ADDR + 0x64)

+#define ADC1_STAT_REG                                   (ADC_MODULE_BASE_ADDR + 0x70)

+#define TS_CONTROL_REG1                                 (ADC_MODULE_BASE_ADDR + 0x5c)

+#define ANALOG_CONTROL1                                 (ADC_MODULE_BASE_ADDR + 0x5c)

+#define ANALOG_CONTROL2                                 (ADC_MODULE_BASE_ADDR + 0x64)

+#define ADC2_MODE_CFG                                   (0x20072000)

+#define DAC_CONFIG_REG                                  (0x2002E000)        //DAC

+#define I2S_CONFIG_REG                                  (0x2002E004)        //I2S

+/** @} */

+

+

+/** @{@name PWM module register and bit map define

+ */

+#define PWM_MODULE_BASE_ADDR                            0x08000000

+#define PWM_CTRL_REG1                                   (PWM_MODULE_BASE_ADDR + 0x2c)

+#define PWM_CTRL_REG2                                   (PWM_MODULE_BASE_ADDR + 0x30)

+#define PWM_CTRL_REG3                                   (PWM_MODULE_BASE_ADDR + 0xb4)

+#define PWM_CTRL_REG4                                   (PWM_MODULE_BASE_ADDR + 0xb8)

+/** @} */

+

+

+/** @{@name TIMER module register and bit map define

+ */

+#define TIMER_MODULE_BASE_ADDR                          0x08000000      // timer registers

+#define TIMER1_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x18)

+#define TIMER2_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x1c)

+#define TIMER3_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x20)

+#define TIMER4_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x24)

+#define TIMER5_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x28) 

+#define TIMER1_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x100)

+#define TIMER2_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x104)

+#define TIMER3_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x108)

+#define TIMER4_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x10c)

+#define TIMER5_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x110)

+/** @} */

+

+

+/** @{@name GPIO module register and bit map define

+ */

+//gpio direction

+#define GPIO_MODULE_BASE_ADDR                           0x08000000      // GPIO registers

+#define GPIO_DIR_REG1                                   (GPIO_MODULE_BASE_ADDR + 0x7c)

+#define GPIO_DIR_REG2                                   (GPIO_MODULE_BASE_ADDR + 0x84)

+#define GPIO_DIR_REG3                                   (GPIO_MODULE_BASE_ADDR + 0x8c)

+#define GPIO_DIR_REG4                                   (GPIO_MODULE_BASE_ADDR + 0x94)

+                                                        

+//gpio output control                                   

+#define GPIO_OUT_REG1                                   (GPIO_MODULE_BASE_ADDR + 0x80)

+#define GPIO_OUT_REG2                                   (GPIO_MODULE_BASE_ADDR + 0x88)

+#define GPIO_OUT_REG3                                   (GPIO_MODULE_BASE_ADDR + 0x90)

+#define GPIO_OUT_REG4                                   (GPIO_MODULE_BASE_ADDR + 0x98)

+                                                        

+//gpio input control                                    

+#define GPIO_IN_REG1                                    (GPIO_MODULE_BASE_ADDR + 0xbc)

+#define GPIO_IN_REG2                                    (GPIO_MODULE_BASE_ADDR + 0xc0)

+#define GPIO_IN_REG3                                    (GPIO_MODULE_BASE_ADDR + 0xc4)

+#define GPIO_IN_REG4                                    (GPIO_MODULE_BASE_ADDR + 0xc8)

+                                                        

+//gpio interrupt enable/disable                         

+#define GPIO_INT_EN1                                    (GPIO_MODULE_BASE_ADDR + 0xe0)

+#define GPIO_INT_EN2                                    (GPIO_MODULE_BASE_ADDR + 0xe4)

+#define GPIO_INT_EN3                                    (GPIO_MODULE_BASE_ADDR + 0xe8)

+#define GPIO_INT_EN4                                    (GPIO_MODULE_BASE_ADDR + 0xec)

+                                                        

+//gpio interrupt sensitivity level                      

+#define GPIO_INT_LEVEL_REG1                             (GPIO_MODULE_BASE_ADDR + 0xf0)

+#define GPIO_INT_LEVEL_REG2                             (GPIO_MODULE_BASE_ADDR + 0xf4)

+#define GPIO_INT_LEVEL_REG3                             (GPIO_MODULE_BASE_ADDR + 0xf8)

+#define GPIO_INT_LEVEL_REG4                             (GPIO_MODULE_BASE_ADDR + 0xfc)

+                                                        

+//gpio pull/pulldown reg                                

+#define GPIO_PULLUPDOWN_REG1                            (GPIO_MODULE_BASE_ADDR + 0x9c)

+#define GPIO_PULLUPDOWN_REG2                            (GPIO_MODULE_BASE_ADDR + 0xa0)

+#define GPIO_PULLUPDOWN_REG3                            (GPIO_MODULE_BASE_ADDR + 0xa4)

+#define GPIO_PULLUPDOWN_REG4                            (GPIO_MODULE_BASE_ADDR + 0xa8)

+                                                        

+//io control reg                                        

+#define GPIO_IO_CONTROL_REG1                            (GPIO_MODULE_BASE_ADDR + 0xD4)

+#define GPIO_IO_CONTROL_REG2                            (GPIO_MODULE_BASE_ADDR + 0xD8)

+                                                        

+//share pin control reg                                 

+#define GPIO_SHAREPIN_CONTROL2                          (GPIO_MODULE_BASE_ADDR + 0x74)

+#define GPIO_SHAREPIN_CONTROL1                          (GPIO_MODULE_BASE_ADDR + 0x78)

+/** @} */

+

+

+/** @{@name Register Operation Define

+ *      Define the macro for read/write register and memory

+ */

+//#ifdef OS_ANYKA

+/* ------ Macro definition for reading/writing data from/to register ------ */

+#define HAL_READ_UINT32( _register_, _value_ )          ((_value_) = *((volatile T_U32 *)(_register_)))

+#define HAL_WRITE_UINT32( _register_, _value_ )         (*((volatile T_U32 *)(_register_)) = (_value_))

+

+#define REG32(_register_)                               (*(volatile T_U32 *)(_register_))

+#define REG16(_register_)                               (*(volatile T_U16 *)(_register_))

+#define REG8(_register_)                                (*(volatile T_U8 *)(_register_))

+

+#if 0

+//read and write register

+#define outb(v,p)                                       (*(volatile unsigned char *)(p) = (v))

+#define outw(v,p)                                       (*(volatile unsigned short *)(p) = (v))

+#define outl(v,p)                                       (*(volatile unsigned long  *)(p) = (v))

+                                                        

+#define inb(p)                                          (*(volatile unsigned char *)(p))

+#define inw(p)                                          (*(volatile unsigned short *)(p))

+#define inl(p)                                          (*(volatile unsigned long *)(p))

+#endif

+

+#define WriteBuf(v,p)                                   (*(volatile unsigned long  *)(p) = (v))

+#define ReadBuf(p)                                      (*(volatile unsigned long *)(p))

+                                                        

+#define WriteRamb(v,p)                                  (*(volatile unsigned char *)(p) = (v))

+#define WriteRamw(v,p)                                  (*(volatile unsigned short *)(p) = (v))

+#define WriteRaml(v,p)                                  (*(volatile unsigned long  *)(p) = (v))

+                                                        

+#define ReadRamb(p)                                     (*(volatile unsigned char *)(p))

+#define ReadRamw(p)                                     (*(volatile unsigned short *)(p))

+#define ReadRaml(p)                                     (*(volatile unsigned long *)(p))

+//#else

+/* ------ Macro definition for reading/writing data from/to register ------ */

+/*

+#define HAL_READ_UINT8( _register_, _value_ )        

+#define HAL_WRITE_UINT8( _register_, _value_ )       

+#define HAL_READ_UINT16( _register_, _value_ )      

+#define HAL_WRITE_UINT16( _register_, _value_ )     

+#define HAL_READ_UINT32( _register_, _value_ )      

+#define HAL_WRITE_UINT32( _register_, _value_ )     

+#define REG32(_register_)  

+#define REG16(_register_)  

+#define REG8(_register_) 

+*/

+//#endif

+

+//error type define

+#define UNDEF_ERROR             1

+#define ABT_ERROR               2

+#define PREF_ERROR              3

+/** @} */

+

+/*@}*/

+

+#endif  // _ANYKA_CPU_H_

+

diff --git a/drivers/mtd/nand/ak88-nand/arch_nand.h b/drivers/mtd/nand/ak88-nand/arch_nand.h
new file mode 100644
index 00000000000..afb17a44d7d
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/arch_nand.h
@@ -0,0 +1,316 @@
+/**@file arch_nand.h

+ * @brief AK880x nand controller

+ *

+ * This file describe how to control the AK880x nandflash driver.

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author yiruoxiang, jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ */

+#ifndef __ARCH_NAND_H__

+#define __ARCH_NAND_H__

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @defgroup NandFlash Nandflash group

+ *  @ingroup Drv_Lib

+ */

+/*@{*/

+#define NFC_FIFO_SIZE			512

+#define NFC_LOG_SPARE_SIZE		16

+

+#define NAND_512B_PAGE      0   // 512 bytes per page

+#define NAND_2K_PAGE        1

+#define NAND_4K_PAGE        2

+#define NAND_8K_PAGE        3

+

+#define NFC_SUPPORT_CHIPNUM    (4)

+#define MTD_PART_NAME_LEN      (4)

+

+struct partitions

+{

+	char name[MTD_PART_NAME_LEN]; 		   

+	unsigned long long size;			           

+	unsigned long long offset;         

+	unsigned int mask_flags;		       

+}__attribute__((packed));

+

+typedef enum

+{

+    ECC_4BIT_P512B  = 0,    /*4 bit ecc requirement per 512 bytes*/

+    ECC_8BIT_P512B  = 1,    //8 bit ecc requirement per 512 bytes

+    ECC_12BIT_P512B = 2,    //12 bit ecc requirement per 512 bytes

+    ECC_16BIT_P512B = 3,    //16 bit ecc requirement per 512 bytes

+    ECC_24BIT_P1KB  = 4,    //24 bit ecc requirement per 1024 bytes

+    ECC_32BIT_P1KB  = 5     //32 bit ecc requirement per 1024 bytes

+}ECC_TYPE;

+

+

+typedef struct SNandEccStru

+{

+    T_U8 *buf;                         //data buffer, e.g. common data buffer or spare buffer

+    T_U32 buf_len;                     //data total length, e.g. 4096 or 8192

+    T_U32 ecc_section_len;             //ecc section length, e.g. 512, 512+4, or 1024, 1024+4

+    ECC_TYPE ecc_type;                 //ecc type, e.g. ECC_4BIT or ECC_8BIT

+}T_NAND_ECC_STRU, *T_PNAND_ECC_STRU;

+

+

+struct SNandflash_Add

+{

+    T_U8    ChipPos[NFC_SUPPORT_CHIPNUM];

+    T_U8    RowCycle;

+    T_U8    ColCycle;

+    T_U8    ChipType;

+    T_U8    EccType;

+    T_U32   PageSize;

+    T_U32   PagesPerBlock;

+};

+

+typedef struct SNandflash_Add* T_PNandflash_Add;

+typedef struct SNandflash_Add T_Nandflash_Add;

+//**********************************************************************

+

+/**

+ * @brief initialization of nandflash hardware.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @return  T_VOID

+ */

+T_VOID nand_HWinit(T_VOID);

+

+/**

+ * @brief config nand command and data cycle

+ *

+ * @author xuchang

+ * @date 2007-12-27

+ * @param[in] CmdCycle the command cycle to config

+ * @param[in] DataCycle the data cycle to config

+ * @return T_VOID

+ */

+T_VOID nand_config_timeseq(T_U32 cmd_cycle, T_U32 data_cycle);

+

+/**

+ * @brief calculate each nand's timing under 62MHz & 124MHz

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] DefDataLen default data lenght

+ * @return  T_VOID

+ */

+T_VOID nand_calctiming(T_U32 DefDataLen);

+

+/**

+ * @brief change nand timing when Freq has changed

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] Freq frequency

+ * @return  T_VOID

+ */

+T_VOID nand_changetiming(T_U32 Freq);

+

+/**

+ * @brief read nand flash chip ID.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @return  T_U32

+ * @retval  current nandflash ID

+ */

+T_U32 nand_read_chipID(T_U32 Chip);

+

+/**

+ * @brief reset nand flash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be reset.

+ * @return  T_VOID

+ */

+T_VOID nand_reset(T_U32 chip);

+

+/**

+ * @brief read data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in/out] pDataCtrl control reading data section: buffer, data lenght, ECC.

+ * @param[in/out] pSpareCtrl control reading spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readpage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl);

+

+/**

+ * @brief read one page(page size>=2048) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be large than or equal to 2048 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 *Spare);

+

+/**

+ * @brief read one page(page size=512) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be 512 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare);

+

+/**

+ * @brief read file system info.

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readspare(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 *Spare);

+

+/**

+ * @brief read data from nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data.

+ * @param[in] Len how many bytes read from nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readbytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Len);

+

+/**

+ * @brief write data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] pDataCtrl control writting data section: buffer, data lenght, ECC.

+ * @param[in] pSpareCtrl control writting spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writepage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl);

+

+/**

+ * @brief write one page(page size>=2048) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be large than or equal to 2048 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Spare);

+

+/**

+ * @brief write one page(page size=512) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be 512 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare);

+

+/**

+ * @brief write data to nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data.

+ * @param[in] Len how many bytes write to nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writebytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, const T_U8 Data[], T_U32 Len);

+

+/**

+ * @brief erase one block of nandflash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] BlkStartPage first page of the block.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return T_U32

+ * @retval 0 means write successfully

+ * @retval 1 means write unsuccessfully

+ * @retval 2 means time out

+ */

+T_U32 nand_eraseblock(T_U32 Chip, T_U32 BlkStartPage, T_PNandflash_Add pNF_Add);

+

+/**

+ * @brief copy one physical page to another one.

+ *

+ * hardware copyback mode, there should be caches in nandflash, source and destation page should be in the same plane

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] SouPhyPage the source page to read.

+ * @param[in] DesPhyPage the destination page to write.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return  T_U32

+ * @retval  0 means write successfully

+ * @retval  1 means write unsuccessfully

+ * @retval  2 means time out

+ */

+T_U32 nand_copyback(T_U32 Chip, T_U32 SrcPhyPage, T_U32 DestPhyPage, T_PNandflash_Add pNF_Add);

+

+/*@}*/

+#ifdef __cplusplus

+}

+#endif

+

+#endif //__ARCH_NAND_H__

diff --git a/drivers/mtd/nand/ak88-nand/communicate.c b/drivers/mtd/nand/ak88-nand/communicate.c
new file mode 100644
index 00000000000..ef7955148c8
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/communicate.c
@@ -0,0 +1,500 @@
+/*******************************************************************************
+ * #BRIEF communicate for AK3226 use the L2 Inter Globe Fifo.
+ * Copyright (C) 2007 Anyka (Guangzhou) Software Technology Co., LTD
+ * #AUTHOR Zou TianXiang
+ * #DATE 2007-7-1
+ ********************************************************************************/
+#include <linux/kernel.h>
+#include <mach/map.h>
+
+#include "communicate.h"
+
+#define L2_BASE_ADDR		AK88_VA_L2CTRL
+#define L2_DMA_BLOCK_ADDR_CONF	AK88_VA_L2CTRL
+
+#define L2_DMA_BLOCK_COUNT_CONF	AK88_VA_L2CTRL+0x40
+
+#define L2_DMA_CRTL		(L2_BASE_ADDR+0x80)
+#define L2_FRACTIOIN_DMA_CONF	(L2_BASE_ADDR+0x84)
+#define L2_BLOCK_DMA_CONF	(L2_BASE_ADDR+0x88)
+#define L2_FLAG_CONF		(L2_BASE_ADDR+0x8C)
+#define L2_BUF_ID_CONF		(L2_BASE_ADDR+0x90)
+#define L2_BUF2_ID_CONF		(L2_BASE_ADDR+0x94)
+#define L2_LDMA_CONF		(L2_BASE_ADDR+0x98)
+#define L2_INTR_EN		(L2_BASE_ADDR+0x9C)
+#define L2_STATUS1		(L2_BASE_ADDR+0xA0)
+#define L2_STATUS2		(L2_BASE_ADDR+0xA8)
+
+#define FRAC_DMA_DIRECT_WRITE	(1<<8)
+#define FRAC_DMA_DIRECT_READ	(0<<8)
+#define FRAC_DMA_START_REQ	(1<<9)
+#define	L2_DMA_ENABLE		(1)
+
+#define L2_BUF_MEM_BASE_ADDR	AK88_VA_L2MEM
+
+static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type);
+
+/*********************************************************************
+Function:       communate_conf
+Description:    Set the BUF ID Correspond to the peripheral
+Input:    	  PERIPHERAL_TYPE dev_type
+GLOBE_BUF_ID buf_id
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id)
+{
+	T_U32 buf_ena_val;
+	T_U32 buf_id_val;
+	//    T_U32 buf_status;
+	T_U32 dam_ctrl_val;
+	T_U32 current_buf_id;
+    //printk(KERN_INFO "zz communicate.c communicate_conf() line 51\n");
+	// Enable the flag effect.
+	HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, dam_ctrl_val);
+	dam_ctrl_val |= (0x3 << 28);
+	HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, dam_ctrl_val);
+
+	// Disable the current buf (if exist) and enable the new buf 
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, buf_ena_val);
+	current_buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c communicate_conf() 60 current_buf_id=0x%08x\n",
+    //         current_buf_id);
+	if (INVALID_BUF_ID != current_buf_id) {
+		// current buf shall be empty
+		/*
+		   HAL_READ_UINT32(L2_STATUS1, buf_status);
+		   if ((buf_status & (0xf<<(4*current_buf_id))) != 0)
+		   printk("warning: L2 buf%d not empty when switch to another\n", current_buf_id);
+		 */
+		//printk(KERN_INFO "zz communicate.c communicate_conf() 69\n");
+		set_buf_stat_empty(current_buf_id);
+		buf_ena_val &= ~(1 << (16 + current_buf_id));
+	}
+	buf_ena_val |= (1 << (16 + buf_id));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, buf_ena_val);
+    //printk(KERN_INFO "zz communicate.c communicate_conf() 75 L2_BLOCK_DMA_CONF:0x%8x=0x%08x\n",
+     //              L2_BLOCK_DMA_CONF, buf_ena_val);
+
+	if (dev_type <= DAC) {
+		// set the Buf Id for the peripheral dev
+		HAL_READ_UINT32(L2_BUF_ID_CONF, buf_id_val);
+		buf_id_val &= (~(0x7 << (dev_type * 3)));
+		buf_id_val |= (buf_id << (dev_type * 3));
+		HAL_WRITE_UINT32(L2_BUF_ID_CONF, buf_id_val);
+        //printk(KERN_INFO "zz communicate.c communicate_conf() 84 L2_BUF_ID_CONF:0x%8x=0x%08x\n",
+        //         L2_BUF_ID_CONF, buf_id_val);
+	} else {
+		// set the BUF ID for SPI2 or gps
+		HAL_READ_UINT32(L2_BUF2_ID_CONF, buf_id_val);
+		buf_id_val &= (~(0x7 << ((dev_type - SPI2_RECE) * 3)));
+		buf_id_val |= (buf_id << ((dev_type - SPI2_RECE) * 3));
+		HAL_WRITE_UINT32(L2_BUF2_ID_CONF, buf_id_val);
+	}
+
+	// clear the buf
+	set_buf_stat_empty(buf_id);
+
+	return AK_TRUE;
+}
+
+/*********************************************************************
+Function:       prepare_dat_send_cpu
+Description:    use CPU MODE to prepare the data to be sent
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_status;
+	T_U32 align_4_len, len_remian_4;
+	T_U32 buf_addr;
+	T_U32 *p_buf_int;
+	T_U32 i;
+	T_U32 tmp;
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 117\n");
+	if (len > 512) {
+		return 0;
+	}
+
+	align_4_len = (len & (~0x3));
+	len_remian_4 = (len % 4);
+
+	buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 126 buf_id=%d\n", buf_id);;
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+	//set_buf_stat_empty((GLOBE_BUF_ID)buf_id);
+
+	// wait till buffer empty
+	do {
+		HAL_READ_UINT32(L2_STATUS1, buf_status);
+        //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 133 L2_STATUS1:0x%08x=0x%08x\n",
+         //      L2_STATUS1, buf_status);
+	} while ((buf_status & (0xf << (4 * buf_id))) != 0);
+
+	if (((T_U32) buf % 4) == 0)	// if the buf is the even then it can 4 bytes write.
+	{
+		p_buf_int = (T_U32 *) buf;
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//tmp = *(p_buf_int++);
+			//WriteBuf(buf_addr+i, tmp);
+			*(volatile T_U32 *)(buf_addr + i) = *(p_buf_int++);
+		}
+		if (len_remian_4 != 0) {
+			tmp = 0;
+			for (i = 0; i < len_remian_4; i++) {
+				tmp = tmp + (buf[align_4_len + i] << (i * 8));
+			}
+			//WriteBuf(buf_addr+align_4_len, tmp);
+			*(volatile T_U32 *)(buf_addr + align_4_len) = tmp;
+		}
+	}
+
+	else			// if the buf is the odd then it can't 4 bytes write.
+	{
+		for (i = 0; i < align_4_len; i = i + 4) {
+			tmp =
+			    (buf[i] | (buf[i + 1] << 8) | (buf[i + 2] << 16) |
+			     (buf[i + 3] << 24));
+			//WriteBuf(buf_addr+i, tmp);
+			*(volatile T_U32 *)(buf_addr + i) = tmp;
+		}
+		tmp = 0;
+		if (len_remian_4 != 0) {
+			for (i = 0; i < len_remian_4; i++) {
+				tmp = tmp + (buf[align_4_len + i] << (i * 8));
+			}
+			//WriteBuf(buf_addr+align_4_len, tmp);
+			*(volatile T_U32 *)(buf_addr + align_4_len) = tmp;
+		}
+	}
+
+	//increase buf status
+	if ((len % 64) && ((len % 64) <= 60)) {
+		*(volatile T_U32 *)(buf_addr + (len & (~0x3f)) + 0x3c) = 0;
+	}
+
+	return 1;
+}
+
+/*********************************************************************
+Function:       rece_dat_cpu
+Description:    use CPU MODE to receive the data from L2 buf
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_status;	//, buf_config;
+	T_U32 align_4_len, len_remian_4;
+	T_U32 buf_addr;
+	T_U32 *p_buf_int;
+	T_U32 i;
+	T_U32 tmp;
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 190\n");
+	if (len > 512) {
+		//printk("error: L2 read too long\n");
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 197 buf_id=%d\n", buf_id);
+	buf_addr = (T_U32)(L2_BUF_MEM_BASE_ADDR + buf_id * 512);
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 205 buf_addr=0x%08x\n", buf_addr);
+	align_4_len = (len & (~0x3));
+	len_remian_4 = (len % 4);
+
+	// wait till 64-byte-aligned data have all been received
+	do {
+		HAL_READ_UINT32(L2_STATUS1, buf_status);
+        //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 206 L2_STATUS1=0x%8x buf_status=0x%8x\n",
+         //     L2_STATUS1, buf_status);
+	} while (((buf_status >> (4 * buf_id)) & 0xf) < (len >> 6));
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 209\n");
+	if (((T_U32) buf % 4) == 0)	// if the buf is the even then it can 4 bytes write.
+	{
+		p_buf_int = (T_U32 *) buf;
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//*(p_buf_int++)  = ReadBuf(buf_addr+i);
+			*(p_buf_int++) = *(volatile T_U32 *)(buf_addr + i);
+		}
+		if (len_remian_4 != 0) {
+			//tmp = ReadBuf(buf_addr+align_4_len);
+			tmp = *(volatile T_U32 *)(buf_addr + align_4_len);
+			for (i = 0; i < len_remian_4; i++) {
+				buf[align_4_len + i] = (tmp >> (8 * i)) & 0xff;
+			}
+		}
+	}
+
+	else			// if the buf is the odd then it can't 4 bytes write.
+	{
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//tmp = ReadBuf(buf_addr+i);
+			tmp = *(volatile T_U32 *)(buf_addr + i);
+
+			buf[i] = (tmp & 0xff);
+			buf[i + 1] = ((tmp >> 8) & 0xff);
+			buf[i + 2] = ((tmp >> 16) & 0xff);
+			buf[i + 3] = ((tmp >> 24) & 0xff);
+		}
+
+		if (len_remian_4 != 0) {
+			//tmp = ReadBuf(buf_addr + align_4_len);
+			tmp = *(volatile T_U32 *)(buf_addr + align_4_len);
+			for (i = 0; i < len_remian_4; i++) {
+				buf[align_4_len + i] = (tmp >> (8 * i)) & 0xff;
+			}
+		}
+	}
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 243\n");
+	return 1;
+}
+
+/*********************************************************************
+Function:       prepare_dat_send_dma
+Description:    use DMA MODE to prepare the data to be sent
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 prepare_dat_send_dma(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 dma_conf, frac_dma_conf, buf_status;
+	T_U32 align_64_len, len_remian_64;
+	T_U32 buf_addr;
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_dma() line 261\n");
+	if ((len > 2048) || (len == 0)) {
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+	if (INVALID_BUF_ID == buf_id) {
+		//printk("ERROR: L2 buf not assigned, dev_type = %d\n", dev_type);
+		return 0;
+	}
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+
+	//set_buf_stat_empty((GLOBE_BUF_ID)buf_id);
+
+	align_64_len = (len >> 6);	//        len / 64
+	len_remian_64 = (len % 64);	//                len % 64
+
+	// enable buf, enable buf dma function, set DMA direction
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+	dma_conf |=
+	    ((1 << buf_id) | (1 << (16 + buf_id)) | (1 << (8 + buf_id)));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+
+	//Config the L2 DMA to transfer the data of 64 align
+	if (align_64_len) {
+		// config the dma addr and count
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_ADDR_CONF + buf_id * 4,
+				 ((T_U32) buf & 0xfffffff));
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_COUNT_CONF + buf_id * 4,
+				 align_64_len);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | (1 << (24 + buf_id)));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while (dma_conf & (1 << (24 + buf_id)));
+	}
+	// Config the L2 DMA to transfer the data of fraction data
+	if (len_remian_64) {
+		const T_U8 *fdma_buf = buf + align_64_len * 64;	// RAM address
+		T_U32 fdma_len = len_remian_64;	// data length
+
+		// chip bug
+		if (fdma_len & 1)	// len is odd
+		{
+			fdma_len++;
+		}
+		// Config the direction, fraction data base addr , fdma len
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf &= (~0xffff);
+		dma_conf |=
+		    (((buf_id * 512 / 64 +
+		       (align_64_len %
+			(512 /
+			 64))) << 1) | FRAC_DMA_DIRECT_WRITE | ((fdma_len -
+								 1) << 10));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		// Config the fraction dma addr
+		HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+		frac_dma_conf &= ~0xfffffff;
+		frac_dma_conf |= ((T_U32) fdma_buf) & 0xfffffff;
+		HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+
+		// wait till buffer is not full
+		do {
+			HAL_READ_UINT32(L2_STATUS1, buf_status);
+		} while (((buf_status >> (4 * buf_id)) & 0xf) == 8);
+
+		//start the fdma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | FRAC_DMA_START_REQ);
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & FRAC_DMA_START_REQ) == FRAC_DMA_START_REQ);
+
+		//increase buf status
+		if (len_remian_64 <= 64 - 4) {
+			*(volatile T_U32 *)(buf_addr +
+					    ((align_64_len * 64) % 512) +
+					    0x3c) = 0;
+		}
+	}
+
+	return 1;
+}
+
+T_U8 rece_data_dma(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 align_64_len, len_remian_64;
+	T_U32 dma_conf, frac_dma_conf;	//, buf_status;
+	T_U32 buf_addr;
+    //printk(KERN_INFO "zz communicate.c rece_data_dma() line 358\n");
+	if ((len > 2048) || (len == 0)) {
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+	if (INVALID_BUF_ID == buf_id) {
+		//printk("ERROR: L2 buf not assigned, dev_type = %d\n", dev_type);
+		return 0;
+	}
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+
+	align_64_len = (len >> 6);	//        len / 64
+	len_remian_64 = (len % 64);	//                len % 64
+
+	// enable buf, enable buf dma function, set DMA direction
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+	dma_conf &= (~(1 << (8 + buf_id)));
+	dma_conf |= ((1 << buf_id) | (1 << (16 + buf_id)));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+
+	//Config the L2 DMA to transfer the data of 64 align
+	if (align_64_len) {
+		// config the dma addr and count
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_ADDR_CONF + buf_id * 4,
+				 ((T_U32) buf & 0xfffffff));
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_COUNT_CONF + buf_id * 4,
+				 align_64_len);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | (1 << (24 + buf_id)));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & (1 << (24 + buf_id))) ==
+			 (1 << (24 + buf_id)));
+	}
+	// *******************         NOTE:              *****************************
+	// **** L2 alone do NOT know whether the rest of data have all been received from peripheral.
+	// **** It is the peripheral driver that should make sure.
+
+	// Config the L2 Fraction DMA to transfer the rest of data
+	if (len_remian_64) {
+		// Config the direct and fraction data base addr
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf &= (~0xffff);
+		dma_conf |=
+		    (((buf_id * 512 / 64 +
+		       (align_64_len %
+			(512 /
+			 64))) << 1) | FRAC_DMA_DIRECT_READ | ((len_remian_64 -
+								1) << 10));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		// Config the fraction dma addr and count
+		HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+		frac_dma_conf &= ~0xfffffff;
+		frac_dma_conf |=
+		    ((T_U32) (buf + align_64_len * 64) & 0xfffffff);
+		HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | FRAC_DMA_START_REQ);
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & FRAC_DMA_START_REQ) == FRAC_DMA_START_REQ);
+	}
+
+	return 1;
+}
+
+/*********************************************************************
+Function:       get_buf_id
+Description:    get the perpheral's correspond buf ID.
+Input:    	  dev_type :	the peripheral type
+Return:         BUF ID
+**********************************************************************/
+static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_en;
+    //printk(KERN_INFO "zz communicate.c get_buf_id() line 443\n");
+	//get the buf id
+	if (dev_type <= DAC) {
+		HAL_READ_UINT32(L2_BUF_ID_CONF, buf_id);
+		buf_id = ((buf_id >> (dev_type * 3)) & 0x7);
+		// to see if the buf is enabled
+		HAL_READ_UINT32(L2_BLOCK_DMA_CONF, buf_en);
+        //printk(KERN_INFO "zz communicate.c get_buf_id() 460 L2_BLOCK_DMA_CONF:0x%08x=0x%08x\n", 
+         //      L2_BLOCK_DMA_CONF,buf_en);
+		if ((buf_en & (1 << (buf_id + 16))) == 0) {
+			buf_id = INVALID_BUF_ID;
+		}
+	} else {
+		HAL_READ_UINT32(L2_BUF2_ID_CONF, buf_id);
+		buf_id = ((buf_id >> ((dev_type - SPI2_RECE) * 3)) & 0x7);
+	}
+    //printk(KERN_INFO "zz communicate.c get_buf_id() 468 return buf_id=%d\n", buf_id);
+	return buf_id;
+}
+
+/*********************************************************************
+Function:       set_buf_stat_empty
+Description:    set the buf to empty stat
+Input:    	  dev_id :	the peripheral type
+ *********************************************************************/
+void set_buf_stat_empty(GLOBE_BUF_ID buf_id)
+{
+	T_U32 flag_conf;
+    //printk(KERN_INFO "zz communicate.c set_buf_stat_empty() line 469\n");
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, flag_conf);
+	flag_conf |= (1 << (buf_id + 24));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, flag_conf);
+}
+
+/*********************************************************************
+Function:       set_buf_empty
+Description:    set the buf to empty stat
+Input:    	  PERIPHERAL_TYPE dev_type
+ **********************************************************************/
+void set_buf_empty(PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c set_buf_empty() line 483\n");
+	set_buf_stat_empty((GLOBE_BUF_ID) buf_id);
+}
+
diff --git a/drivers/mtd/nand/ak88-nand/communicate.h b/drivers/mtd/nand/ak88-nand/communicate.h
new file mode 100644
index 00000000000..5531b4a4e8a
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/communicate.h
@@ -0,0 +1,64 @@
+#ifndef _COMMUNICATE_H_
+#define _COMMUNICATE_H_
+
+//#include "AK3220_types.h"
+#ifndef _AK3220_TYPES_H_
+#define _AK3220_TYPES_H_
+
+/* preliminary type definition for global area */
+typedef unsigned char T_U8;	/* unsigned 8 bit integer */
+typedef unsigned short T_U16;	/* unsigned 16 bit integer */
+typedef unsigned long T_U32;	/* unsigned 32 bit integer */
+typedef signed char T_S8;	/* signed 8 bit integer */
+typedef signed short T_S16;	/* signed 16 bit integer */
+typedef signed long T_S32;	/* signed 32 bit integer */
+typedef void T_VOID;		/* void */
+
+#define HAL_READ_UINT32(reg, val)      ((val) = *((volatile unsigned long *)(reg)))
+#define HAL_WRITE_UINT32(reg, val)     (*((volatile  unsigned long *)(reg)) = (val))
+
+#define AK_FALSE                                0
+#define AK_TRUE                                 1
+//#define AK_NULL                                 ((T_VOID*)0)
+#endif
+
+typedef enum {
+	GLOBE_BUF0 = 0,
+	GLOBE_BUF1,
+	GLOBE_BUF2,
+	GLOBE_BUF3,
+	GLOBE_BUF4,
+	GLOBE_BUF5,
+	GLOBE_BUF6,
+	GLOBE_BUF7
+} GLOBE_BUF_ID;
+
+typedef enum {
+	USB_BULK_SEND,
+	USB_BULK_RECE,
+	USB_ISO,
+	NAND_FLASH,
+	MMC_SD1,
+	MMC_SD2,
+	MMC_SD3,
+	SPI1_RECE,
+	SPI1_SEND,
+	DAC,
+	SPI2_RECE,
+	SPI2_SEND,
+	GPS
+} PERIPHERAL_TYPE;
+
+//static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type);
+#define INVALID_BUF_ID 0xFFFFFFFF
+
+T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id);
+T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len,
+			  PERIPHERAL_TYPE dev_type);
+T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+T_U8 prepare_dat_send_dma(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+T_U8 rece_data_dma(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+void set_buf_stat_empty(GLOBE_BUF_ID buf_id);
+void set_buf_empty(PERIPHERAL_TYPE dev_type);
+
+#endif
diff --git a/drivers/mtd/nand/ak88-nand/nand_char.c b/drivers/mtd/nand/ak88-nand/nand_char.c
new file mode 100644
index 00000000000..fb4d29fcc75
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/nand_char.c
@@ -0,0 +1,545 @@
+/**

+ * @filename nand_char.c

+ * @brief AK880x nandflash char device driver

+ * Copyright (C) 2010 Anyka (Guangzhou) Software Technology Co., LTD

+ * @author zhangzheng

+ * @modify 

+ * @date 2010-10-20

+ * @version 1.0

+ * @ref Please refer to¡­

+ */

+#include <linux/module.h>

+#include <linux/types.h>

+#include <linux/fs.h>

+#include <linux/errno.h>

+#include <linux/mm.h>

+#include <linux/sched.h>

+#include <linux/init.h>

+#include <linux/kernel.h>

+#include <linux/cdev.h>

+#include <linux/string.h>

+#include <asm/uaccess.h>

+#include <linux/mtd/partitions.h>

+#include <mtd/mtd-abi.h>

+#include <mach-anyka/nand_list.h>

+#include <mach-anyka/fha.h>

+#include "arch_nand.h"

+#include "nand_control.h"

+#include "wrap_nand.h"

+

+#define NAND_CHAR_MAJOR                 168

+#define AK_NAND_PHY_ERASE               0xa0

+#define AK_NAND_PHY_READ                0xa1

+#define AK_NAND_PHY_WRITE               0xa2

+#define AK_NAND_GET_CHIP_ID             0xa3

+#define AK_MOUNT_MTD_PART               0xa4

+#define AK_NAND_READ_BYTES              0xa5

+#define AK_GET_NAND_PARA                0xa6

+

+#define ZZ_DEBUG                        0

+

+extern T_NAND_PHY_INFO *g_pNand_Phy_Info;

+extern T_PNandflash_Add g_pNF;

+extern T_PFHA_INIT_INFO g_pinit_info;

+extern T_PFHA_LIB_CALLBACK g_pCallback;

+

+static int nand_char_open(struct inode *inode, struct file *filp);

+static int nand_char_close(struct inode *inode, struct file *filp);

+static int nand_char_ioctl(struct inode *inode, struct file *filp,

+		     unsigned int cmd, unsigned long arg);

+

+struct erase_para

+{

+    uint32_t chip_num;

+    uint32_t startpage;

+};

+

+struct rw_para

+{

+    T_U32 chip_num;

+    T_U32 page_num;

+    T_U8 *data;

+    T_U32 data_len;

+    T_U8 *oob;

+    T_U32 oob_len;

+	T_U32 eDataType;

+};

+

+struct rbytes_para

+{

+	T_U32 chip_num; 

+	T_U32 row_addr; 

+	T_U32 clm_addr; 

+	T_U8 *data;

+	T_U32 data_len;

+};

+

+struct get_id_para

+{

+    uint32_t chip_num;

+    uint32_t *nand_id;

+};

+

+static struct nand_char_dev

+{

+    struct cdev c_dev;

+}nand_c_dev;

+

+extern struct mtd_info *g_master;

+

+static int nand_c_major = NAND_CHAR_MAJOR;

+

+static const struct file_operations nand_char_fops =

+{

+    .owner   = THIS_MODULE,

+    .open    = nand_char_open,

+    .release = nand_char_close,

+    .ioctl   = nand_char_ioctl

+};

+

+static int nand_char_open(struct inode *inode, struct file *filp)

+{

+    filp->private_data = &nand_c_dev;

+	#if ZZ_DEBUG

+    printk(KERN_NOTICE "zz nand_char.c nand_char_open() 104\n");

+	#endif

+    return 0;

+}

+

+static int nand_char_close(struct inode *inode, struct file *filp)

+{

+	#if ZZ_DEBUG

+    printk(KERN_NOTICE "zz nand_char.c nand_char_close() 112\n");

+	#endif

+    return 0;

+}

+

+static int nand_char_ioctl(struct inode *inode, struct file *filp,

+		                     unsigned int cmd, unsigned long arg)

+{

+	#if ZZ_DEBUG

+    printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 121 cmd=0x%x\n", cmd);   

+	#endif

+    switch(cmd)

+    {

+        case AK_NAND_PHY_ERASE:

+        {

+            struct erase_para ep;

+			if(g_pNF == NULL)

+			{

+				#if ZZ_DEBUG

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 131 g_pNF==NULL\n");

+				#endif

+				break;

+			}

+            copy_from_user(&ep, (struct erase_para *)arg, sizeof(struct erase_para));

+			#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 137 AK_NAND_PHY_ERASE\n");

+            printk(KERN_INFO "erase chip_num = %d startpage = %d\n",

+                   ep.chip_num,

+                   ep.startpage);

+			#endif

+            nand_eraseblock(ep.chip_num, ep.startpage, g_pNF);

+            break;

+        }

+        case AK_NAND_PHY_READ:

+        {

+            struct rw_para r_para;

+            T_NAND_ECC_STRU data_ctrl;

+            T_NAND_ECC_STRU spare_ctrl;

+            T_U8 oob_buf[32];

+

+			if(g_pNF == NULL)

+			{

+				#if ZZ_DEBUG

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 155 g_pNF==NULL\n");

+				#endif

+				break;

+			}

+            copy_from_user(&r_para, (struct rw_para*)arg, sizeof(struct rw_para));

+			#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 161 AK_NAND_PHY_READ\n");

+            printk(KERN_INFO "Read chip_num=%d page_num=%d data_len=%d oob_len=%d eDataType=%d\n",

+                   r_para.chip_num,

+                   r_para.page_num,

+                   r_para.data_len,

+                   r_para.oob_len,

+                   r_para.eDataType);

+			#endif

+	

+            if(r_para.eDataType == FHA_DATA_BOOT)

+    		{

+    			data_ctrl.buf = kmalloc(r_para.data_len, GFP_KERNEL);

+    			data_ctrl.buf_len = r_para.data_len;

+    			data_ctrl.ecc_section_len = NAND_DATA_SIZE + r_para.oob_len;

+    			data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    			spare_ctrl.buf = oob_buf;

+    			spare_ctrl.buf_len = r_para.oob_len;

+    			spare_ctrl.ecc_section_len = NAND_DATA_SIZE + r_para.oob_len;

+    			spare_ctrl.ecc_type = ECC_8BIT_P512B;

+    		}

+			else if (r_para.eDataType == FHA_DATA_ASA || r_para.eDataType == FHA_DATA_BIN)

+			{

+				data_ctrl.buf = kmalloc(r_para.data_len, GFP_KERNEL);

+    			data_ctrl.buf_len = r_para.data_len;

+    			data_ctrl.ecc_section_len = NAND_DATA_SIZE + r_para.oob_len;

+    			data_ctrl.ecc_type = g_pNF->EccType;

+

+    			spare_ctrl.buf = oob_buf;

+    			spare_ctrl.buf_len = r_para.oob_len;

+    			spare_ctrl.ecc_section_len = NAND_DATA_SIZE + r_para.oob_len;

+    			spare_ctrl.ecc_type = g_pNF->EccType;

+			}

+			else

+			{

+    			Nand_Config_Data(&data_ctrl,

+					             kmalloc(r_para.data_len, GFP_KERNEL),

+					             r_para.data_len, 

+					             g_pNF->EccType

+					             );

+				Nand_Config_Spare(&spare_ctrl, oob_buf, r_para.oob_len, g_pNF->EccType);

+			}      

+            nand_readpage_ecc(r_para.chip_num, r_para.page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);

+
+            copy_to_user(((struct rw_para *)arg)->data, data_ctrl.buf, r_para.data_len);

+            copy_to_user(((struct rw_para *)arg)->oob, spare_ctrl.buf, r_para.oob_len);

+
+            kfree(data_ctrl.buf);

+            break;

+        }

+        case AK_NAND_PHY_WRITE:

+        {

+            struct rw_para w_para;

+            T_NAND_ECC_STRU data_ctrl;

+            T_NAND_ECC_STRU spare_ctrl;

+            unsigned char oob_buf[32];

+			if(g_pNF == NULL)

+			{

+				#if ZZ_DEBUG

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 220 g_pNF==NULL\n");

+				#endif

+				break;

+			}

+            copy_from_user(&w_para, (struct rw_para *)arg, sizeof(struct rw_para));

+			#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 226 AK_NAND_PHY_WRITE\n");

+            printk(KERN_INFO "Write chip_num=%d page_num=%d data_len=%d oob_len=%d eDataType=%d\n",

+                   w_para.chip_num,

+                   w_para.page_num,

+                   w_para.data_len,

+                   w_para.oob_len,

+                   w_para.eDataType);

+    		#endif

+

+			if(w_para.eDataType == FHA_DATA_BOOT)

+    		{

+    			data_ctrl.buf = kmalloc(w_para.data_len, GFP_KERNEL);

+    			data_ctrl.buf_len = w_para.data_len;

+    			data_ctrl.ecc_section_len = NAND_DATA_SIZE + w_para.oob_len;

+    			data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    			spare_ctrl.buf = oob_buf;

+    			spare_ctrl.buf_len = w_para.oob_len;

+    			spare_ctrl.ecc_section_len = NAND_DATA_SIZE + w_para.oob_len;

+    			spare_ctrl.ecc_type = ECC_8BIT_P512B;

+    		}

+			else if (w_para.eDataType == FHA_DATA_ASA || w_para.eDataType == FHA_DATA_BIN)

+			{

+				data_ctrl.buf = kmalloc(w_para.data_len, GFP_KERNEL);

+    			data_ctrl.buf_len = w_para.data_len;

+    			data_ctrl.ecc_section_len = NAND_DATA_SIZE + w_para.oob_len;

+    			data_ctrl.ecc_type = g_pNF->EccType;

+

+    			spare_ctrl.buf = oob_buf;

+    			spare_ctrl.buf_len = w_para.oob_len;

+    			spare_ctrl.ecc_section_len = NAND_DATA_SIZE + w_para.oob_len;

+    			spare_ctrl.ecc_type = g_pNF->EccType;

+			}

+			else

+			{

+				Nand_Config_Data(&data_ctrl, 

+					             kmalloc(w_para.data_len, GFP_KERNEL), 

+					             w_para.data_len, 

+					             g_pNF->EccType

+					             );

+				Nand_Config_Spare(&spare_ctrl, oob_buf, w_para.oob_len, g_pNF->EccType);

+			}	

+			

+			if(data_ctrl.buf != NULL)

+			{

+				copy_from_user(data_ctrl.buf, ((struct rw_para *)arg)->data, data_ctrl.buf_len);

+				copy_from_user(spare_ctrl.buf, ((struct rw_para *)arg)->oob, spare_ctrl.buf_len);

+			}

+			else

+			{

+				printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 276 data_ctrl.buf == NULL error!!!\n");

+				break;

+			}

+			

+            nand_writepage_ecc(w_para.chip_num, w_para.page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);

+
+            kfree(data_ctrl.buf);

+            break;

+        }

+        case AK_NAND_GET_CHIP_ID:

+        {

+            uint32_t nand_id = 0;

+            struct get_id_para gip;

+            copy_from_user(&gip, (struct get_id_para *)arg, sizeof(struct get_id_para));

+            nand_id = nand_read_chipID(gip.chip_num);

+			#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 292 AK_NAND_GET_CHIP_ID\n");

+            printk(KERN_INFO "mtd_ioctl() chip_num=%d nand_id=0x%x\n", 

+                   gip.chip_num,

+                   nand_id);

+			#endif

+            copy_to_user(((struct get_id_para *)arg)->nand_id, &nand_id, 

+                           sizeof(nand_id));

+            break;

+        }

+        case AK_MOUNT_MTD_PART:

+		{

+			int retval = 0;

+			T_U32 part_cnt = 0;

+			int i = 0;

+			T_U8 *fs_info = NULL;

+			struct partitions *parts = NULL;

+			struct mtd_partition *pmtd_part = NULL;

+			

+			retval = init_fha_lib();        //initialize fha lib

+			

+			if(retval == FHA_SUCCESS)

+			{

+				if(g_pNF == NULL)

+				{

+					printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 316 g_pNF == NULL error!!!\n");

+					break;

+				}

+				fs_info = kmalloc(g_pNF->PageSize, GFP_KERNEL);

+				retval = FHA_get_fs_part(fs_info, g_pNF->PageSize);

+				

+				#if ZZ_DEBUG

+				printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 323 FHA_get_fs_part() return %d\n", retval);

+				printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 324 test recieve data start------------------\n");

+				for(i=0; i<80; i++)

+				{	

+					if(i%10 == 0)

+					{

+						printk(KERN_INFO "\n");

+					}

+					printk(KERN_INFO "0x%02x\n", fs_info[i]);

+				}

+				printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 333 test recieve data end---------------------\n");

+				#endif

+				

+				part_cnt = *((int *)fs_info);  //calculate how many partitions

+				

+				if(part_cnt == 0)

+				{

+					printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 340 part_cnt==0 error!!!\n");

+					break;

+				}

+				

+				pmtd_part = kmalloc(sizeof(struct mtd_partition) * part_cnt, GFP_KERNEL);

+				

+				if(pmtd_part == NULL)

+				{

+					printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 348 pmtd_part==NULL error!!!\n");

+					break;

+				}

+				#if ZZ_DEBUG

+				printk(KERN_INFO "---------------zz nand_char.c nand_char_ioctl() 352 AK_MOUNT_MTD_PART mtd parts info start-------------\n");

+				#endif

+				

+				parts = (struct partitions *)(&fs_info[4]);

+				

+				for(i=0; i<part_cnt; i++)

+				{	

+					pmtd_part[i].name = kmalloc(MTD_PART_NAME_LEN, GFP_KERNEL);

+					memcpy(pmtd_part[i].name, (parts+i)->name, MTD_PART_NAME_LEN);

+					pmtd_part[i].size = parts[i].size;

+					pmtd_part[i].offset =  parts[i].offset;

+					pmtd_part[i].mask_flags = parts[i].mask_flags;

+					

+					#if ZZ_DEBUG

+					printk(KERN_INFO "pmtd_part[%d]:\nname = %s\nsize = 0x%llx\noffset = 0x%llx\nmask_flags = 0x%x\n\n", 

+					       i, 

+					       pmtd_part[i].name, 

+					       pmtd_part[i].size,

+					       pmtd_part[i].offset,

+					       pmtd_part[i].mask_flags);

+					#endif

+				}

+				

+				#if ZZ_DEBUG

+				printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 376 AK_MOUNT_MTD_PART mtd part info end-----------------\n");

+				#endif

+				

+				add_mtd_partitions(g_master, (const struct mtd_partition *)pmtd_part, part_cnt);

+				

+				kfree(pmtd_part);

+				kfree(fs_info);

+			}

+			else

+			{

+				printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 386 AK_MOUNT_MTD_PART init fha lib failed!!!\n");

+			}

+			

+		    break;

+        }

+		case AK_NAND_READ_BYTES:            

+		{

+			struct rbytes_para rbp;

+			if(g_pNF == NULL)

+			{

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 396 g_pNF==NULL Error!!!\n");

+				break;

+			}

+			copy_from_user(&rbp, (struct rbytes_para *)arg, sizeof(struct rbytes_para));

+			rbp.data = kmalloc(rbp.data_len, GFP_KERNEL);

+			nand_readbytes(rbp.chip_num, rbp.row_addr, rbp.clm_addr, g_pNF, rbp.data, rbp.data_len);

+			copy_to_user(((struct rbytes_para *)arg)->data, rbp.data, rbp.data_len);

+			break;

+		}

+		case AK_GET_NAND_PARA:

+		{

+			g_pNand_Phy_Info = kmalloc(sizeof(T_NAND_PHY_INFO), GFP_KERNEL);

+			if(g_pNand_Phy_Info == NULL)

+			{

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 410 g_pNand_Phy_Info==NULL Error!!!\n");

+				break;

+			}

+			copy_from_user(g_pNand_Phy_Info, (T_NAND_PHY_INFO *)arg, sizeof(T_NAND_PHY_INFO));

+			g_pNF = kmalloc(sizeof(T_Nandflash_Add), GFP_KERNEL);

+			if(g_pNF == NULL)

+			{

+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 417 g_pNF==NULL Error!!!\n");

+				break;

+			}

+			

+			g_pNF->RowCycle      = g_pNand_Phy_Info->row_cycle;

+			g_pNF->ColCycle      = g_pNand_Phy_Info->col_cycle;

+			g_pNF->PageSize      = g_pNand_Phy_Info->page_size;

+			g_pNF->PagesPerBlock = g_pNand_Phy_Info->page_per_blk;

+			g_pNF->EccType       = (T_U8)((g_pNand_Phy_Info->flag & 0xf0) >> 4);  //4-7 bit is ecc type

+			

+			switch(g_pNand_Phy_Info->page_size)

+			{

+				case 512:

+				{

+					g_pNF->ChipType = NAND_512B_PAGE;

+					break;

+				}

+				case 2048:

+				{

+					g_pNF->ChipType = NAND_2K_PAGE;

+					break;

+				}

+				case 4096:

+				{

+					g_pNF->ChipType = NAND_4K_PAGE;

+					break;

+				}	

+				case 8192:

+				{

+					g_pNF->ChipType = NAND_8K_PAGE;

+					break;

+				}

+				default:

+				{

+					printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 451 globle g_pNF->ChipType is error!!!\n");

+				}

+			}

+			

+			#if 1  //ZZ_DEBUG

+			printk(KERN_INFO "----------------------zz nand_char.c nand_char_ioctl() 456-----------------------\n");

+			printk(KERN_INFO "----------------------------Nand Physical Parameter------------------------------\n");

+			printk(KERN_INFO "chip_id = 0x%x\n", g_pNand_Phy_Info->chip_id);

+			printk(KERN_INFO "page_size = %d\n", g_pNand_Phy_Info->page_size);

+			printk(KERN_INFO "page_per_blk = %d\n", g_pNand_Phy_Info->page_per_blk);

+			printk(KERN_INFO "blk_num = %d\n", g_pNand_Phy_Info->blk_num);

+			printk(KERN_INFO "group_blk_num = %d\n", g_pNand_Phy_Info->group_blk_num);

+			printk(KERN_INFO "plane_blk_num = %d\n", g_pNand_Phy_Info->plane_blk_num);

+			printk(KERN_INFO "spare_size = %d\n", g_pNand_Phy_Info->spare_size);

+			printk(KERN_INFO "col_cycle = %d\n", g_pNand_Phy_Info->col_cycle);

+			printk(KERN_INFO "lst_col_mask = %d\n", g_pNand_Phy_Info->lst_col_mask);

+			printk(KERN_INFO "row_cycle = %d\n", g_pNand_Phy_Info->row_cycle);

+			printk(KERN_INFO "delay_cnt = %d\n", g_pNand_Phy_Info->delay_cnt);

+			printk(KERN_INFO "custom_nd = %d\n", g_pNand_Phy_Info->custom_nd);

+			printk(KERN_INFO "flag = 0x%x\n", g_pNand_Phy_Info->flag);

+			printk(KERN_INFO "cmd_len = 0x%x\n", g_pNand_Phy_Info->cmd_len);

+			printk(KERN_INFO "data_len = 0x%x\n", g_pNand_Phy_Info->data_len);

+			printk(KERN_INFO "---------------------------------------------------------------------------------\n");

+			#endif

+			break;

+		}

+	    default:

+        {   

+            return -EINVAL;

+        }

+    }

+    return 0;

+}

+

+static struct class *nand_class;

+

+static void nand_setup_cdev(void)

+{

+    int err = 0;

+    dev_t devno = MKDEV(nand_c_major, 0);

+

+    cdev_init(&(nand_c_dev.c_dev), &nand_char_fops);

+    nand_c_dev.c_dev.owner = THIS_MODULE;

+    nand_c_dev.c_dev.ops = &nand_char_fops;

+    err = cdev_add(&(nand_c_dev.c_dev), devno, 1);

+    if(err)

+    {

+        printk(KERN_NOTICE "Error %d adding anyka nand char dev\n", err);

+    }

+	

+	//automatic mknod device node

+	nand_class = class_create(THIS_MODULE, "nand_class");

+	device_create(nand_class, NULL, devno, &nand_c_dev, "nand_char");

+}

+

+static int __init nand_char_init(void)

+{

+    int result = 0;

+    dev_t devno = MKDEV(nand_c_major, 0);

+    if(nand_c_major)

+    {

+        result = register_chrdev_region(devno, 1, "anyka nand char dev");

+    }

+    else

+    {

+        result = alloc_chrdev_region(&devno, 0, 1, "anyka nand char dev");

+    }

+    if(result<0)

+    {

+        return result;

+    }

+    nand_setup_cdev();

+	printk(KERN_INFO "Nand Char Device Initialize Successed!\n");
+    return 0;

+}

+                      

+static void __exit nand_char_exit(void)

+{

+	dev_t devno = MKDEV(nand_c_major, 0);

+	

+	//destroy device node

+	device_destroy(nand_class, devno);

+	class_destroy(nand_class); 

+	

+	//delete char device

+    cdev_del(&(nand_c_dev.c_dev));

+    unregister_chrdev_region(devno, 1);

+}

+                      

+module_init(nand_char_init);

+module_exit(nand_char_exit);            

+MODULE_LICENSE("GPL");

+MODULE_AUTHOR("ZhangZheng");

+MODULE_DESCRIPTION("Direct character-device access to Nand devices");

+

diff --git a/drivers/mtd/nand/ak88-nand/nand_control.c b/drivers/mtd/nand/ak88-nand/nand_control.c
new file mode 100644
index 00000000000..1c24b8d495c
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/nand_control.c
@@ -0,0 +1,1809 @@
+/**

+ * @filename nandflash.c

+ * @brief AK880x nandflash driver

+ * Copyright (C) 2006 Anyka (Guangzhou) Software Technology Co., LTD

+ * @author yiruoxiang

+ * @modify jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ * @ref Please refer to¡­

+ */

+#include <linux/kernel.h>

+#include <asm/delay.h>

+#include <mach-anyka/anyka_types.h>

+#include <asm/delay.h>

+#include <linux/slab.h>

+#include <linux/string.h>

+#include <linux/dma-mapping.h>

+#include <mach/l2.h>

+#include "anyka_cpu.h"

+#include "arch_nand.h"

+#include "nand_control.h"

+#include "sysctl.h"

+

+#define READ_BUF	GLOBE_BUF4

+#define WRITE_BUF	GLOBE_BUF5

+

+#define NAND_L2_ENABLE	1	/* Define NAND_L2_ENABLE to use new L2 API(ak88_l2_*), undefine it to use old communicate.c API */

+//#undef NAND_L2_ENABLE

+

+#define ZZ_DEBUG        0

+

+//*****************************************************************************************

+static T_BOOL   nf_check_data_spare_separate(T_PNAND_ECC_STRU pDataCtrl, T_PNAND_ECC_STRU pSpareCtrl, T_U32 *cycle, T_U32 *effective_size, T_U32 *ecc_type);

+static T_U32    nf_get_ecccode_len(T_U32 ecc_type);

+static T_U8     nf_read_chipstatus(T_U32 Chip);

+static T_U32*   nf_send_addr(T_U32 *reg_addr, T_U32 columnAddr,T_U32 rowAddr, T_U32 col_cycle, T_U32 row_cycle);

+//static T_VOID   nf_controller_reset(T_VOID);

+static T_BOOL   check_cmd_done(T_VOID);

+static T_VOID   cmd_go(T_U32 Chip);

+static T_U8     nf_check_ecc_status(T_U32 stat);

+static T_U32    calc_new(T_U8 data_opt_len, T_U8 data_we_fe, T_U8 data_we_re, T_U8 data_re_fe, T_U8 data_re_re);

+static T_U32    ecc_repair(T_U32 wrong_info, T_U8 *main_buf, T_U8 *add_buf, T_U32 main_size, T_U32 add_size, T_U32 ecc_type);

+static T_U32    nf_check_repair_ecc(T_U8 *pMain_buf, T_U8 *pAdd_buf, T_U32 section_size, T_U32 add_len, T_U32 ecc_type, T_BOOL  bSeparate_spare);

+

+//*****************************************************************************************

+typedef enum {

+	USB_BULK_SEND,

+	USB_BULK_RECE,

+	USB_ISO,

+	NAND_FLASH,

+	MMC_SD1,

+	MMC_SD2,

+	MMC_SD3,

+	SPI1_RECE,

+	SPI1_SEND,

+	DAC,

+	SPI2_RECE,

+	SPI2_SEND,

+	GPS

+} PERIPHERAL_TYPE;

+

+typedef enum {

+	GLOBE_BUF0 = 0,

+	GLOBE_BUF1,

+	GLOBE_BUF2,

+	GLOBE_BUF3,

+	GLOBE_BUF4,

+	GLOBE_BUF5,

+	GLOBE_BUF6,

+	GLOBE_BUF7

+} GLOBE_BUF_ID;

+

+extern T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id);

+extern T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);

+extern T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);

+

+//***************************************************************************************    

+#define MAX_LOOP_CNT       T_U32_MAX

+

+#define CAL_40M(n)   ((((n) - 1) >> 1) + 1)     //¼´Ê¹n£½0£¬Ò²»áËã³ö-1+1=0

+#define CAL_62M(n)   (((((n) * 3) - 1 ) >> 2) + 1)  // a >= (3*a_84 - 1)/4

+#define CAL_124M(n)  ((((n) * 3) >> 1) + 1)

+#define CAL_168M(n)  (((n) * 2) + 1)

+

+

+/** @name frequency define

+         define frequency by numbers

+ */

+/*@{*/

+#define FREQ_168M       (168 * 1000000)

+#define FREQ_124M       (124 * 1000000)

+#define FREQ_84M        (84 * 1000000)

+#define FREQ_62M        (62 * 1000000)

+#define FREQ_31M        (31 * 1000000)

+/*@} */

+

+static T_U32 s_datalen_40M  = 0x82627;

+static T_U32 s_datalen_62M  = 0x82627;

+static T_U32 s_cmdlen_84M   = 0x82671;

+static T_U32 s_datalen_84M  = 0x82627;

+static T_U32 s_datalen_124M = 0xf5c5c;

+static T_U32 s_datalen_168M = 0xf5c5c;

+

+/**

+ * @brief initialization of nandflash hardware.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @return  T_VOID

+ */

+ 

+static void ak880x_nand_lock_sharepin(void)

+{

+	/* set the share pin for nandflash */ 

+	*(volatile unsigned int *)(0xF0100000 + 0x74) &= (~(3 << 3));

+	*(volatile unsigned int *)(0xF0100000 + 0x74) |= (1 << 3);	//set 01 to enable the NFC

+

+	*(volatile unsigned int *)(0xF0100000 + 0x78) |=

+	    ((1 << 22) | (0xf << 16));

+

+#if	defined(CONFIG_MACH_AK7801EVB) || defined(CONFIG_MACH_TA8)

+	//FIXME: use configurable nWP pin 

+	// set DGPIO 36 high, disable flash write protection 

+	*(volatile unsigned int *)(0xF0100000 + 0x94) &= (~(1 << 5));

+	*(volatile unsigned int *)(0xF0100000 + 0x98) |= (1 << 5);

+    

+#endif

+

+}

+

+T_VOID nand_HWinit(T_VOID)

+{

+  

+    T_U8 chip;

+    //T_U32 pin;

+

+    //DRV_PROTECT

+

+    //set cmd&data cycle\len

+    REG32(FLASH_CTRL_REG23) = 0xf5ad1;//0x41230//0x52341//0x82671//0xC3671

+    REG32(FLASH_CTRL_REG24) = 0xf5c5c;//0x30102//0x41213//0x82627//0xF3637

+

+    //set share pin as nandflash data pin

+    //gpio_pin_group_cfg(ePIN_AS_NANDFLASH);//zhangzheng mask

+    *(volatile unsigned int *)(0xF0100000 + 0x74) &= (~(3 << 3));

+	*(volatile unsigned int *)(0xF0100000 + 0x74) |= (1 << 3);	//set 01 to enable the NFC

+	*(volatile unsigned int *)(0xF0100000 + 0x78) |= ((1 << 22) | (0xf << 16));

+    //DRV_UNPROTECT

+    

+    for (chip = 0; chip < 4; chip++)

+    {

+        nand_reset(chip);

+    }

+}

+

+/**

+ * @brief config nand command and data cycle

+ *

+ * @author xuchang

+ * @date 2007-12-27

+ * @param[in] CmdCycle the command cycle to config

+ * @param[in] DataCycle the data cycle to config

+ * @return T_VOID

+ */

+T_VOID nand_config_timeseq(T_U32 CmdCycle, T_U32 DataCycle)

+{

+    //open nand controller clock so that register can be read!!

+    //DRV_PROTECT

+    //set cmd&data cycle\len

+    REG32(FLASH_CTRL_REG23) = CmdCycle;

+    REG32(FLASH_CTRL_REG24) = DataCycle;

+    //DRV_UNPROTECT

+}

+

+/**

+ * @brief calculate each nand's timing under 62MHz & 124MHz

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] DefDataLen default data lenght

+ * @return  T_VOID

+ */

+T_VOID nand_calctiming(T_U32 DefDataLen)

+{

+    T_U8 data_opt_len, data_we_fe, data_we_re, data_re_fe, data_re_re;

+    T_U8 data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new;

+

+    //open nand controller clock so that register can be read!!

+    //record the original data_len under 84MHz

+    s_cmdlen_84M = REG32(FLASH_CTRL_REG23);

+    s_datalen_84M = DefDataLen;

+    

+    if (DefDataLen > 0x80000)

+    {

+        data_opt_len = 7;

+        data_we_fe = 1;

+        data_we_re = 5;

+        data_re_fe = 1;

+        data_re_re = 5;

+    }

+    else

+    {

+        data_opt_len = (DefDataLen >> 16) & 0xF;

+        data_we_fe = (DefDataLen >> 12) & 0xF;

+        data_we_re = (DefDataLen >> 8) & 0xF;

+        data_re_fe = (DefDataLen >> 4) & 0xF;

+        data_re_re = (DefDataLen >> 0) & 0xF;

+    }

+

+    data_opt_len_new = CAL_40M(data_opt_len);

+    data_we_fe_new   = CAL_40M(data_we_fe);

+    data_we_re_new   = CAL_40M(data_we_re);

+    data_re_fe_new   = CAL_40M(data_re_fe);

+    data_re_re_new   = CAL_40M(data_re_re);

+

+

+    s_datalen_40M = calc_new(data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new);

+

+    data_opt_len_new = CAL_62M(data_opt_len);

+    data_we_fe_new   = CAL_62M(data_we_fe);

+    data_we_re_new   = CAL_62M(data_we_re);

+    data_re_fe_new   = CAL_62M(data_re_fe);

+    data_re_re_new   = CAL_62M(data_re_re);

+

+    s_datalen_62M = calc_new(data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new);

+    

+    data_opt_len_new = CAL_124M(data_opt_len);

+    data_we_fe_new   = CAL_124M(data_we_fe);

+    data_we_re_new   = CAL_124M(data_we_re);

+    data_re_fe_new   = CAL_124M(data_re_fe);

+    data_re_re_new   = CAL_124M(data_re_re);

+

+    s_datalen_124M = calc_new(data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new);

+

+    data_opt_len_new = CAL_168M(data_opt_len);

+    data_we_fe_new   = CAL_168M(data_we_fe);

+    data_we_re_new   = CAL_168M(data_we_re);

+    data_re_fe_new   = CAL_168M(data_re_fe);

+    data_re_re_new   = CAL_168M(data_re_re);

+

+    s_datalen_168M = calc_new(data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new);

+}

+

+/**

+ * @brief change nand timing when Freq has changed

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] Freq frequency

+ * @return  T_VOID

+ */

+T_VOID nand_changetiming(T_U32 Freq)

+{

+    T_U32 cmd_len, dat_len;

+

+    if (Freq > FREQ_168M)

+    {

+        cmd_len = 0xf5ad1;

+        dat_len = 0xf5c5c;

+    }

+    else if (Freq > FREQ_124M)

+    {

+        cmd_len = 0xf5ad1;

+        dat_len = s_datalen_168M;

+    }

+    else if (Freq > FREQ_84M)

+    {

+        cmd_len = 0xf5ad1;

+        dat_len = s_datalen_124M;

+    }

+    else if (Freq > FREQ_62M)

+    {

+        cmd_len = s_cmdlen_84M;

+        dat_len = s_datalen_84M;

+    }

+    else if (Freq > FREQ_31M)

+    {

+        cmd_len = 0x82671;

+        dat_len = s_datalen_62M;

+    }

+    else

+    {

+        cmd_len = 0x82671;

+        dat_len = s_datalen_40M;

+    }

+

+    nand_config_timeseq(cmd_len, dat_len);

+}

+

+/**

+ * @brief read nand flash chip ID.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @return  T_U32

+ * @retval  current nandflash ID

+ */

+T_U32 nand_read_chipID(T_U32 Chip)

+{

+    T_U32 nand_id = 0;

+

+    ak880x_nand_lock_sharepin();

+    //clear internal status

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //config command

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_READ_ID << 11) | COMMAND_CYCLES_CONF;

+

+    //config address

+    REG32(FLASH_CTRL_REG0 + 0x04) = (0x00 << 11) | ADDRESS_CYCLES_CONF;

+

+    //ID information is 4 byte,read it to register 22

+    REG32(FLASH_CTRL_REG0 + 0x08) = (3 << 11) | READ_INFO_CONF | LAST_CMD_FLAG;

+

+    //excute operation

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );

+

+    // read status

+    nand_id = REG32(FLASH_CTRL_REG20);

+

+    return nand_id;

+}

+

+/**

+ * @brief reset nand flash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be reset.

+ * @return  T_VOID

+ */

+T_VOID nand_reset(T_U32 Chip)

+{

+    //clear internal status

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //config command

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_RESET << 11) | COMMAND_CYCLES_CONF;

+

+    //config wait time, the chip may not exist

+    REG32(FLASH_CTRL_REG0 + 0x04) = ((84 * 1000 / 1024) << 11) | DELAY_CNT_CONF | LAST_CMD_FLAG; // wait R/B rising

+

+    //excute operation

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+}

+

+/**

+ * @brief read data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in/out] pDataCtrl control reading data section: buffer, data lenght, ECC.

+ * @param[in/out] pSpareCtrl control reading spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success, 1 fail

+ */

+T_U32 nand_readpage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl)

+{

+    T_U32   i, regvalue, loopCnt, ret;

+    T_U32   ecc_type;

+    T_U32   effective_size, total_len, section_size =0, add_len;

+    T_U8    *pMain_buf, *pAdd_buf;

+    T_U32   *reg_addr;

+    T_U16   fail_cnt = 0;

+    T_BOOL  bSeparate_spare, bSpare_read;

+    T_U8    l2_buf_id;

+    T_BOOL  bIsFinalRead = AK_FALSE;     //final read, not care previous read_fail

+    

+    //-------------------zhangzheng add start-----------------------------

+	#ifndef NAND_L2_ENABLE

+    asm("AK_InvalidateDCache_z:\n" "mrc  p15,0,r15,c7,c14,3\n" "bne AK_InvalidateDCache_z"); 

+	#endif

+	ak880x_nand_lock_sharepin();

+    //-------------------zhangzheng add end-----------------------------

+RETRY_RP:

+    ret = 0;

+    bSpare_read = AK_FALSE;

+    pMain_buf = AK_NULL;

+    pAdd_buf = AK_NULL;

+    add_len = 0;

+    l2_buf_id = BUF_NULL;

+

+    /*check whether is data and spare separate, get the length and ECC type of the first data seciton or spare,

+           and get the times to read data*/ 

+    bSeparate_spare = nf_check_data_spare_separate(pDataCtrl, pSpareCtrl, &loopCnt, &effective_size, &ecc_type);

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 398 phy page=%d\n", RowAddr);

+    printk(KERN_INFO "bSeparate_spare=%d loopCnt=%d effective_size=%d ecc_type=%d\n",

+    bSeparate_spare,loopCnt,effective_size,ecc_type);

+	#endif

+

+    if(0 == loopCnt)

+    {

+        ret = 1;

+        goto RETURN2;

+    }    

+    //clear status

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash read1 command

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;      

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+    }

+    else

+    {

+        if(ColumnAddr < 256)

+        {

+            REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else if(ColumnAddr >= 512)

+        {

+            REG32(reg_addr++) = (NFLASH_READ22 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else

+        {

+            REG32(reg_addr++) = (NFLASH_READ1_HALF << 11) | COMMAND_CYCLES_CONF;

+        }

+    }

+

+    //nandflash send address   

+    reg_addr = nf_send_addr(reg_addr, 0, RowAddr, pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash read2 command if nand is large page

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ2 << 11) | COMMAND_CYCLES_CONF;

+    }

+    //config waiting R/B rising edge

+    REG32(reg_addr++) = WAIT_JUMP_CONF | LAST_CMD_FLAG;

+

+    //run command, wait cmd done 

+    cmd_go(Chip);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 447 before while(cmd)\n");

+	#endif

+	

+    while (!check_cmd_done());

+	

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 453 before while(cmd)\n");

+	#endif

+	

+#ifdef NAND_L2_ENABLE

+    l2_buf_id = ak88_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == l2_buf_id)

+    {

+        ret = 1;

+        goto RETURN2;

+    }    

+#else

+    communicate_conf(NAND_FLASH, READ_BUF);

+#endif

+    for (i = 0; i < loopCnt; i++)

+    {

+        T_U32 ecc_ret;

+        /*set data size and ecc type to read when reading spare section 

+              if data and spare is separate */

+        if(bSeparate_spare  && (( loopCnt - 1) == i) && (AK_NULL != pSpareCtrl))

+        {

+            bSpare_read = AK_TRUE;

+            effective_size = pSpareCtrl->buf_len;

+            ecc_type = pSpareCtrl->ecc_type;     

+        }

+

+        //config ECC module

+        regvalue = ECC_CTL_DEC_EN | ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR      \

+                        | ECC_CTL_BYTE_CFG(effective_size) | ECC_CTL_NFC_EN | ECC_CTL_MODE(pSpareCtrl->ecc_type)    \

+                        | ECC_CTL_NO_ERR | ECC_CTL_RESULT_NO_OK;    // reset ecc result status bits

+        HAL_WRITE_UINT32(FLASH_ECC_REG0, regvalue);

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  regvalue|ECC_CTL_START);

+

+        //clear status

+        REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+        //config the whole length of a section including ecc part

+        total_len = effective_size + nf_get_ecccode_len(pSpareCtrl->ecc_type);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 491 total_len=%d\n",

+               total_len);

+		#endif

+        REG32(FLASH_CTRL_REG0) = ((total_len - 1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG;

+#ifdef NAND_L2_ENABLE

+        //clear l2 status, must before cmd_go

+        ak88_l2_clr_status(l2_buf_id);

+#endif

+        

+        //start to transfer data from nand to l2

+        cmd_go(Chip);

+

+        //need to read data part if pDataCtrl is not NULL

+        if ((AK_NULL != pDataCtrl) && (!bSpare_read))

+        {            

+            if(!bSeparate_spare)

+            {

+                section_size = pDataCtrl->ecc_section_len - pSpareCtrl->buf_len;

+            }

+            else

+            {

+                section_size = pDataCtrl->ecc_section_len;

+            }    

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 515 section_size=%d\n", section_size);

+			#endif

+            pMain_buf = pDataCtrl->buf + (i * section_size);

+#ifdef NAND_L2_ENABLE

+            if(((T_U32)pMain_buf & 0x3) != 0)

+            {

+                ak88_l2_combuf_cpu((T_U32)pMain_buf, l2_buf_id, section_size, BUF2MEM); 

+            }

+            else

+            {

+				dma_addr_t dmahandle;

+				void *bufaddr = NULL;

+		    

+				bufaddr = dma_alloc_coherent(NULL, NAND_DATA_SIZE, &dmahandle, GFP_KERNEL);

+				ak88_l2_combuf_dma((T_U32)dmahandle, l2_buf_id, NAND_DATA_SIZE, BUF2MEM, AK_FALSE);

+				ak88_l2_combuf_wait_dma_finish(l2_buf_id);

+				memcpy(pMain_buf, bufaddr, NAND_DATA_SIZE);

+				dma_free_coherent(NULL, NAND_DATA_SIZE, bufaddr, dmahandle);

+            }    

+#else	// ! NAND_L2_ENABLE

+        	rece_dat_cpu(pMain_buf, NAND_DATA_SIZE, NAND_FLASH);

+#endif

+        } 

+        //wait data transfered

+        while(!check_cmd_done());

+

+        //copy spare from l2 to memory 

+        if ((AK_NULL != pSpareCtrl) && (!bSeparate_spare || bSpare_read))

+        {  

+            if(!bSeparate_spare)

+            {

+                //need to read spare while reading a section of data if data and spare is not separate

+                pAdd_buf = pSpareCtrl->buf;

+                add_len = pSpareCtrl->buf_len;

+            }  

+            else

+            {

+                //read spare for the last time(bSpare_read is true) if data and spare is separate

+                pMain_buf = pSpareCtrl->buf;

+                section_size = effective_size;

+            }

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 557 spare len=%d\n",

+				   pSpareCtrl->buf_len);

+			#endif

+			

+			#ifdef NAND_L2_ENABLE

+			ak88_l2_combuf_cpu((T_U32)pSpareCtrl->buf, l2_buf_id, pSpareCtrl->buf_len, BUF2MEM);

+			

+			#else

+			rece_dat_cpu(pSpareCtrl->buf, pSpareCtrl->buf_len, NAND_FLASH);

+			#endif

+

+        }

+

+        ecc_ret = nf_check_repair_ecc(pMain_buf, pAdd_buf, section_size, add_len, ecc_type, bSeparate_spare);

+      

+        if (DATA_ECC_CHECK_ERROR == ecc_ret)

+        {   

+            if (AK_FALSE == bIsFinalRead)

+            {

+                fail_cnt++;                

+                if ((fail_cnt & 0x40) != 0) //max retry read cnt = 64

+                {

+                    bIsFinalRead = AK_TRUE;

+                }

+#ifdef NAND_L2_ENABLE

+                ak88_l2_free(ADDR_NFC);

+#endif

+                goto RETRY_RP;

+            }

+            else

+            {

+                ret = 1;

+            }

+        }

+        else if (DATA_ECC_ERROR_REPAIR_CAN_TRUST == ecc_ret)

+        {

+        } 

+    }

+	

+RETURN2:    

+#ifdef NAND_L2_ENABLE

+    ak88_l2_free(ADDR_NFC);

+#endif

+    return ret;

+}   

+

+/**

+ * @brief read one page(page size>=2048) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be large than or equal to 2048 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 *Spare)

+{

+    return nand_readsector(Chip, RowAddr, ColumnAddr, pNF_Add, Data, Spare);

+}

+

+/**

+ * @brief read one page(page size=512) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be 512 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    data_ctrl.buf = Data;

+    data_ctrl.buf_len = pNF_Add->PageSize;

+    data_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = Spare + 2;

+    spare_ctrl.buf_len = NAND_FS_SIZE;

+    spare_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+     

+    return nand_readpage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+/**

+ * @brief read file system info.

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readspare(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    T_U8 data[NAND_DATA_SIZE];

+

+    data_ctrl.buf = data;

+    data_ctrl.buf_len = NAND_DATA_SIZE;

+    data_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = Spare+2;//zhangzheng add 2 offset

+    spare_ctrl.buf_len = 128;

+    spare_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readspare() 683\n");

+	#endif

+    return nand_readpage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+/**

+ * @brief read data from nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data.

+ * @param[in] Len how many bytes read from nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readbytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Len)

+{

+    T_U32 *reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+    T_U32 tmp   = 0;

+	T_U8 l2_buf_id = BUF_NULL;

+    T_U8  i     = 0;

+    T_U32 ret   = 0;

+

+	//-------------------zhangzheng add start-----------------------------

+	#ifdef NAND_L2_ENABLE

+	dma_addr_t dmahandle;

+	void *bufaddr = NULL;

+	#endif

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readbytes() 716 Len=%d\n", Len);

+	#endif

+	#ifndef NAND_L2_ENABLE	

+    asm("AK_InvalidateDCache_rb:\n" "mrc  p15,0,r15,c7,c14,3\n" "bne AK_InvalidateDCache_rb"); 

+	#endif

+	ak880x_nand_lock_sharepin();

+	//-------------------zhangzheng add end------------------------------

+

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash send command

+    REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash read2 command,this is a wait command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ2 << 11) | COMMAND_CYCLES_CONF |(1 << 10);

+    }

+	

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+	cmd_go(Chip);

+	while (!check_cmd_done());

+

+	#ifdef NAND_L2_ENABLE

+	l2_buf_id = ak88_l2_alloc(ADDR_NFC);

+	if (BUF_NULL == l2_buf_id)

+	{

+		ret = 1;

+		goto RETURN1;

+	}

+	#else

+	communicate_conf(NAND_FLASH, READ_BUF);

+	#endif

+	

+    //config ECC

+    tmp = (ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR  \

+            | ECC_CTL_BYTE_CFG(Len) | ECC_CTL_NFC_EN | ECC_CTL_MODE(pNF_Add->EccType));

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp|ECC_CTL_START);

+    REG32(FLASH_CTRL_REG0) = ((Len - 1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG;

+    cmd_go(Chip);

+

+    for(i = 0; i < (Len / NAND_DATA_SIZE); i++)

+    {

+		#ifdef NAND_L2_ENABLE

+		bufaddr = dma_alloc_coherent(NULL, NAND_DATA_SIZE, &dmahandle, GFP_KERNEL);

+		ak88_l2_combuf_dma((T_U32)dmahandle, l2_buf_id, NAND_DATA_SIZE, BUF2MEM, AK_FALSE);

+		ak88_l2_combuf_wait_dma_finish(l2_buf_id);

+		memcpy(Data+(i*NAND_DATA_SIZE), bufaddr, NAND_DATA_SIZE);

+		dma_free_coherent(NULL, NAND_DATA_SIZE, bufaddr, dmahandle);

+		#else

+		rece_dat_cpu(Data+(i*NAND_DATA_SIZE), NAND_DATA_SIZE, NAND_FLASH);

+		#endif   

+    }

+	

+    tmp = Len & 511;

+    if (tmp != 0)

+    {

+    	#ifdef NAND_L2_ENABLE

+		ak88_l2_combuf_cpu((T_U32)(Data + i * NAND_DATA_SIZE), l2_buf_id, tmp, BUF2MEM);

+		#else

+		rece_dat_cpu(Data+(i*NAND_DATA_SIZE), tmp, NAND_FLASH);

+		#endif

+    }

+    while (!check_cmd_done());

+

+

+	ret = 0;

+	

+RETURN1:

+	#ifdef NAND_L2_ENABLE 

+	ak88_l2_free(ADDR_NFC);

+	#endif

+	

+	return ret;

+}

+

+/**

+ * @brief write data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] pDataCtrl control writting data section: buffer, data lenght, ECC.

+ * @param[in] pSpareCtrl control writting spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writepage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl)

+{

+    T_U32   i, loopCnt;

+    T_BOOL  bSeparate_spare;

+    T_U32   effective_size;

+    T_U32   ecc_type;

+    T_U32   total_len;

+    T_U8    tmp_rowcycle = pNF_Add->RowCycle - 1;

+    T_U32   ret;

+    T_U32   status;

+    T_U32   tmp = 0;

+    T_U32   section_data_size;

+    T_U32   *reg_addr;

+    T_U8    l2_buf_id;

+    T_U16   fail_cnt = 0;

+    T_BOOL  bSpare_write;

+	#ifndef NAND_L2_ENABLE

+    asm("AK_FlashDCache_zz:\n" "mrc  p15,0,r15,c7,c10,3\n" "bne AK_FlashDCache_zz");

+	#endif

+	ak880x_nand_lock_sharepin();

+    

+ RETRY_WR: 

+    ret = 0;

+    bSpare_write = AK_FALSE;

+    l2_buf_id = BUF_NULL;

+    

+    /*check whether is data and spare separate, get the length and ECC type of the first data seciton,

+       and get the times to write data*/   

+    bSeparate_spare = nf_check_data_spare_separate(pDataCtrl, pSpareCtrl, &loopCnt, &effective_size, &ecc_type);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 840 phy page=%d\n", RowAddr);

+    printk(KERN_INFO "bSeparate_spare=%d loopCnt=%d effective_size=%d ecc_type=%d\n",

+           bSeparate_spare,loopCnt,effective_size,ecc_type);

+    #endif

+    if (0 == loopCnt)

+    {

+        ret = 1;

+        goto RETURN2;

+    }    

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0; 

+

+    if (NAND_512B_PAGE == pNF_Add->ChipType)

+    {

+        //... ÐèÒªµ÷ÕûÖ¸Õë

+        if(ColumnAddr < 256)

+        {

+            REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else if(ColumnAddr >= 512)

+        {

+            REG32(reg_addr++) = (NFLASH_READ22 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else

+        {

+            REG32(reg_addr++) = (NFLASH_READ1_HALF << 11) | COMMAND_CYCLES_CONF;

+        }

+    }

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR; 

+   

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM0)

+    REG32(reg_addr++) = (NFLASH_FRAME_PROGRAM0 << 11) | COMMAND_CYCLES_CONF; 

+

+    //nandflash send address

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, tmp_rowcycle);

+    REG32(reg_addr) = ((RowAddr >> (tmp_rowcycle * 8)) << 11) | ADDRESS_CYCLES_CONF | LAST_CMD_FLAG;

+

+    //execute cmd and wait command send done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 883 after while\n");

+	#endif

+	

+#ifdef NAND_L2_ENABLE

+    l2_buf_id = ak88_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == l2_buf_id)

+    {

+        ret = 1;

+        goto RETURN2;

+    } 

+#else

+    communicate_conf(NAND_FLASH, WRITE_BUF);

+#endif

+

+    for (i = 0; i < loopCnt; i++)

+    {

+        /*set data size and ecc type to write when writing spare section 

+        if data and spare is separate */

+        if (bSeparate_spare  && (( loopCnt - 1) == i) && (AK_NULL != pSpareCtrl))

+        {

+            bSpare_write = AK_TRUE;

+            effective_size = pSpareCtrl->buf_len;

+            ecc_type = pSpareCtrl->ecc_type;

+        }

+

+        //config ECC module

+		

+		tmp = ( ECC_CTL_ENC_EN | ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR	\

+                | ECC_CTL_BYTE_CFG(effective_size) | ECC_CTL_NFC_EN | ECC_CTL_MODE(ecc_type));

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp);

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp|ECC_CTL_START);

+        //sta_clr = 0,

+        REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+        //config the whole length of a section including ecc part

+        total_len = effective_size + nf_get_ecccode_len(ecc_type);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 920 total_len=%d\n",

+              total_len);

+		#endif

+        REG32(FLASH_CTRL_REG0) = ((total_len - 1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG;

+

+        //start to transfer data from memory to nand

+        cmd_go(Chip);

+		

+        //copy page data to L2 buffer

+        if(!bSpare_write)

+        {

+            //the length of a ecc data section

+            if(!bSeparate_spare)

+            {

+                section_data_size = pDataCtrl->ecc_section_len - pSpareCtrl->buf_len;

+            }

+            else

+            {

+                section_data_size = pDataCtrl->ecc_section_len;

+            }    

+			

+#ifdef NAND_L2_ENABLE

+            if (((T_U32)(pDataCtrl->buf) & 0x3) != 0)

+            {

+                ak88_l2_combuf_cpu((T_U32)(pDataCtrl->buf + (i * section_data_size)), l2_buf_id, section_data_size, MEM2BUF); 

+            }

+            else

+            {

+				dma_addr_t dmahandle;

+				void *bufaddr = NULL;

+

+				bufaddr = dma_alloc_coherent(NULL, NAND_DATA_SIZE, &dmahandle, GFP_KERNEL);

+				memcpy(bufaddr, pDataCtrl->buf + (i * NAND_DATA_SIZE), NAND_DATA_SIZE);

+				ak88_l2_combuf_dma((T_U32)dmahandle, l2_buf_id, NAND_DATA_SIZE, MEM2BUF, false);

+				ak88_l2_combuf_wait_dma_finish(l2_buf_id);

+				dma_free_coherent(NULL, NAND_DATA_SIZE, bufaddr, dmahandle);

+            }

+            //wait nand controler transfer data

+            while(0 != ak88_l2_get_status(l2_buf_id)); 

+			

+#else	// ! NAND_L2_ENABLE

+            prepare_dat_send_cpu(pDataCtrl->buf+(i*NAND_DATA_SIZE), NAND_DATA_SIZE, NAND_FLASH);

+#endif

+        }

+

+        //send spare data

+        if ((AK_NULL != pSpareCtrl) && (!bSeparate_spare || bSpare_write))

+        {

+#ifdef NAND_L2_ENABLE

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 970 spare len=%d\n",pSpareCtrl->buf_len);

+			#endif

+            ak88_l2_combuf_cpu((T_U32)pSpareCtrl->buf, l2_buf_id, pSpareCtrl->buf_len, MEM2BUF);

+#else

+            prepare_dat_send_cpu(pSpareCtrl->buf + (i*NAND_FS_SIZE), NAND_FS_SIZE, NAND_FLASH);

+#endif

+        } 

+        while (!check_cmd_done());

+		

+#ifdef NAND_L2_ENABLE

+	    ak88_l2_clr_status(l2_buf_id);

+#else

+        //clear l2 status, because l2_combuf_cpu will set l2 status 

+        ak88_l2_clr_status(WRITE_BUF);

+#endif

+        // wait for ECC complete

+        do 

+        {

+            HAL_READ_UINT32(FLASH_ECC_REG0, tmp);

+        }while ((tmp  & ECC_CTL_END) != ECC_CTL_END);

+

+        HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+    }

+	

+#ifdef NAND_L2_ENABLE

+    ak88_l2_free(ADDR_NFC);

+#endif

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM1)

+    REG32(reg_addr++)= ((NFLASH_FRAME_PROGRAM1 << 11) | COMMAND_CYCLES_CONF | LAST_CMD_FLAG);

+

+    //run command, wait cmd done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+

+    for ( i = 0; i < MAX_LOOP_CNT; i++ )

+    {

+        status = nf_read_chipstatus(Chip);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 1014 status=0x%lx\n",

+               status);

+		#endif

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_WR;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN2;

+            }

+            else 

+            {

+                ret = 0;

+                goto RETURN2;

+            }

+        }

+        udelay(100);

+    }

+    ret = 2;

+    

+RETURN2:

+    return ret;

+}

+

+/**

+ * @brief write one page(page size>=2048) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be large than or equal to 2048 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Spare)

+{

+     return nand_writesector(Chip, RowAddr, ColumnAddr, pNF_Add, Data, Spare);

+}

+

+/**

+ * @brief write one page(page size=512) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be 512 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+

+    data_ctrl.buf = Data;

+    data_ctrl.buf_len = pNF_Add->PageSize;

+    data_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = Spare + 2;

+    spare_ctrl.buf_len = NAND_FS_SIZE;

+    spare_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+

+    return nand_writepage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+/**

+ * @brief write data to nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data.

+ * @param[in] Len how many bytes write to nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writebytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, const T_U8 Data[], T_U32 Len)

+{

+    T_U32 *reg_addr;

+    T_U32 ret = 0, LoopCnt = 0, tmp, i, status;

+    T_U8  tmp_rowcycle = pNF_Add->RowCycle - 1, buf_id = BUF_NULL;

+    T_U16 fail_cnt = 0;

+

+RETRY_WR:

+    i = 0;

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+    

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM0)

+    REG32(reg_addr++)=((NFLASH_FRAME_PROGRAM0 << 11) | COMMAND_CYCLES_CONF); 

+

+    //nandflash send address

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, tmp_rowcycle);

+    REG32(reg_addr)=(((RowAddr >> (tmp_rowcycle * 8)) << 11) | ADDRESS_CYCLES_CONF | LAST_CMD_FLAG);

+

+    //run cmd, wait fifo command send done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+

+    buf_id = ak88_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == buf_id)

+    {

+        ret = 1;

+        goto RETURN4;

+    }

+        

+    //config ECC module

+    tmp = ( ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR    \

+           | ECC_CTL_BYTE_CFG(Len) | ECC_CTL_NFC_EN);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp|ECC_CTL_START);

+

+    REG32(FLASH_CTRL_REG0)=(((Len -  1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG);

+

+    cmd_go(Chip);

+

+    //copy data to l2

+    for(i = 0; i < (Len / NAND_DATA_SIZE); i++)

+    {

+        ak88_l2_combuf_dma((T_U32)(Data + (i * NAND_DATA_SIZE)), buf_id, NAND_DATA_SIZE, MEM2BUF, AK_FALSE);

+        ak88_l2_combuf_wait_dma_finish(buf_id);

+        

+        //wait nand controler transfer data

+        while(0 != ak88_l2_get_status(buf_id));

+    }

+    

+    tmp = Len & 511;

+    if (tmp != 0)

+    {

+        ak88_l2_combuf_cpu((T_U32)(Data + i * NAND_DATA_SIZE), buf_id, tmp, MEM2BUF);

+    }

+

+    while ( !check_cmd_done());

+

+    ak88_l2_clr_status(buf_id);

+   

+    //wait for ECC complete        

+    do 

+    {

+        HAL_READ_UINT32(FLASH_ECC_REG0, tmp);

+    }while ((tmp  & ECC_CTL_END) != ECC_CTL_END);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+    REG32(reg_addr++)= ((NFLASH_FRAME_PROGRAM1 << 11) | COMMAND_CYCLES_CONF);

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+ 

+    for ( LoopCnt = 0; LoopCnt < MAX_LOOP_CNT; LoopCnt++)

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_WR;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN4;

+            }

+            else 

+            {

+                ret = 0;

+                goto RETURN4;

+            }

+        } 

+        udelay(100);

+    }

+    ret = 2;

+

+RETURN4:

+    ak88_l2_free(ADDR_NFC);

+    return ret;

+}

+

+/**

+ * @brief erase one block of nandflash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] BlkStartPage first page of the block.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return T_U32

+ * @retval 0 means write successfully

+ * @retval 1 means write unsuccessfully

+ * @retval 2 means time out

+ */

+T_U32 nand_eraseblock(T_U32 Chip, T_U32 BlkStartPage, T_PNandflash_Add pNF_Add)

+{

+    T_U32 status;

+    T_U32 *reg_addr;

+    T_U32 ret = 0;

+    T_U32 LoopCnt  = 0;

+    T_U16 fail_cnt = 0;

+

+//    printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1301 startpage=%d\n", 

+//           BlkStartPage);

+    ak880x_nand_lock_sharepin();//zhangzheng add temp for debug

+RETRY_EB:

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0, need?

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash erase command

+    REG32(reg_addr++) = (NFLASH_BLOCK_ERASE0 << 11) | COMMAND_CYCLES_CONF;

+

+    //nandflash physic page address

+    reg_addr = nf_send_addr(reg_addr, 0, BlkStartPage, 0, pNF_Add->RowCycle);

+

+    //nandflash erase command

+    REG32(reg_addr++) = (NFLASH_BLOCK_ERASE1 << 11) | COMMAND_CYCLES_CONF;

+

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+    // excute operation, CE1, enable power saving, CE# keep LOW wait R/B

+    cmd_go(Chip);

+    // wait end & read data (data at where)

+//    printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1322\n");

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+//    printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1324\n");

+    for ( LoopCnt = 0; LoopCnt <MAX_LOOP_CNT; LoopCnt ++ )

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+        	#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1275\n");

+			#endif

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 2)

+                {

+                    goto RETRY_EB;

+                }

+                ret = 1;

+                goto RETURN5;

+            }

+            else

+            {

+                ret = 0;

+                goto RETURN5;

+            }

+        }

+        udelay(100);

+    }

+    ret = 2;

+RETURN5:

+    return ret;

+}

+

+/**

+ * @brief copy one physical page to another one.

+ *

+ * hardware copyback mode, there should be caches in nandflash, source and destation page should be in the same plane

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] SouPhyPage the source page to read.

+ * @param[in] DesPhyPage the destination page to write.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return  T_U32

+ * @retval  0 means write successfully

+ * @retval  1 means write unsuccessfully

+ * @retval  2 means time out

+ */

+T_U32 nand_copyback(T_U32 Chip, T_U32 SrcPhyPage, T_U32 DestPhyPage, T_PNandflash_Add pNF_Add)

+{

+    T_U32 status;

+    T_U32 *reg_addr;

+    T_U32 ret = 0;

+    T_U16 fail_cnt = 0;

+    T_U32 i;

+

+RETRY_CP:

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+    //nandflash read1 command

+    REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+

+    reg_addr = nf_send_addr(reg_addr, 0, SrcPhyPage,  pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash copyback read command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_READ << 11) | COMMAND_CYCLES_CONF;

+    }    

+

+    REG32(reg_addr++) = WAIT_JUMP_CONF;// wait R/B rising edge

+

+    //nandflash copyback write command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_WRITE << 11) | COMMAND_CYCLES_CONF;

+    }

+    else

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_WRITE1 << 11) | COMMAND_CYCLES_CONF;

+    }

+

+    reg_addr = nf_send_addr(reg_addr, 0, DestPhyPage,  pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash copyback confirm command

+    //if (NFLASH_SMALL_PAGE != pNF_Add->ChipType)

+    //small page slc also need to send '10H' command, resumed on 20070615

+    REG32(reg_addr++) = (NFLASH_COPY_BACK_CONFIRM << 11) | COMMAND_CYCLES_CONF;

+    

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+    

+    cmd_go(Chip);

+

+    // wait reg22 fifo command send done

+    while ( !check_cmd_done() );

+

+    for ( i = 0; i < MAX_LOOP_CNT; i++ )

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_CP;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN6;

+            }

+            else

+            {

+                ret = 0;

+                goto RETURN6;

+            }

+        }

+        udelay(100);//delay or handle other task

+    }

+    ret = 2;

+RETURN6:

+    return ret;

+}

+

+//***********************************************************************************

+/*

+static T_VOID nf_controller_reset(T_VOID)

+{

+    T_U32 cmd_len = 0xf5ad1;

+    T_U32 dat_len = 0xf5c5c;

+    

+    //akprintf(C3, M_DRVSYS, "reset nand controller\r\n");  

+    

+    cmd_len = REG32(FLASH_CTRL_REG23);

+    dat_len = REG32(FLASH_CTRL_REG24);

+    

+    sysctl_reset(RESET_NANDFLASH);

+

+    REG32(FLASH_CTRL_REG23) = cmd_len;

+    REG32(FLASH_CTRL_REG24) = dat_len;

+}

+*/

+//***********************************************************************************

+static T_U8 nf_read_chipstatus(T_U32 Chip)

+{

+    T_U32 status;

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_STATUS_READ << 11) | COMMAND_CYCLES_CONF;

+

+    //read status,1byte

+    REG32(FLASH_CTRL_REG0 + 0x04) = (0 << 11) | READ_INFO_CONF | LAST_CMD_FLAG;

+

+    // excute operation, CE1, enable power saving, CE# keep LOW wait R/B

+    //must open write protect

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+

+    // read status

+    status = REG32(FLASH_CTRL_REG20);

+

+    return((T_U8)(status & 0xFF));

+}

+

+//***********************************************************************************

+static T_U32 *nf_send_addr(T_U32 *reg_addr, T_U32 ColumnAddr,T_U32 rowAddr, T_U32 col_cycle, T_U32 row_cycle)

+{

+    T_U8 cycle,value;

+

+    //send column address

+    for (cycle = 0; cycle < col_cycle; cycle++)

+    {

+        value = (ColumnAddr >> (8 * cycle)) & 0xFF;

+        REG32(reg_addr++) = (value << 11) | ADDRESS_CYCLES_CONF;

+    }

+

+    //send row address

+    for (cycle = 0; cycle < row_cycle; cycle++)

+    {

+        value = (rowAddr >> (8 * cycle)) & 0xFF;

+        REG32(reg_addr++) = (value << 11) | ADDRESS_CYCLES_CONF;

+    }

+

+    return reg_addr;

+}

+//***********************************************************************************

+static T_BOOL nf_check_data_spare_separate(T_PNAND_ECC_STRU pDataCtrl, T_PNAND_ECC_STRU pSpareCtrl, T_U32 *cycle, T_U32 *effective_size, T_U32 *ecc_type)

+{

+    T_BOOL ret = AK_TRUE;

+

+    if(AK_NULL == pDataCtrl)

+    {

+        *cycle = 1;

+        *effective_size = pSpareCtrl->buf_len;

+        *ecc_type = pSpareCtrl->ecc_type;

+    }

+    else

+    {

+        T_U32 section_len = pDataCtrl->ecc_section_len;

+

+        if(0 != (pDataCtrl->buf_len % section_len)) //spare and data is not separate

+        {

+            section_len -= pSpareCtrl->buf_len;

+

+            if(0 != (pDataCtrl->buf_len % section_len))  //param err

+            {

+                *cycle = 0;

+            }    

+            else

+            {

+                *cycle = pDataCtrl->buf_len / section_len;

+            }

+

+            ret = AK_FALSE;

+        }

+        else

+        {

+            *cycle = pDataCtrl->buf_len / section_len;

+

+            if(AK_NULL != pSpareCtrl)

+            {

+                (*cycle)++;

+            }

+        }

+

+        *effective_size = pDataCtrl->ecc_section_len;

+        *ecc_type = pDataCtrl->ecc_type;

+    }

+

+    return ret;

+}    

+//***********************************************************************************

+static T_U32 nf_get_ecccode_len(T_U32 ecc_type)

+{

+    T_U32 ecc_len = NAND_PARITY_SIZE_MODE0;

+    

+    switch(ecc_type)

+    {

+        case ECC_4BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE0;

+            break;

+        case ECC_8BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE1;

+            break;

+        default:

+            break; 

+    } 

+

+    return ecc_len;

+} 

+

+//***********************************************************************************

+static T_U8 nf_check_ecc_status(T_U32 stat)

+{

+    if ( (stat & ECC_CHECK_NO_ERROR) == ECC_CHECK_NO_ERROR )

+    {

+        stat |= ECC_CHECK_NO_ERROR;

+        HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);

+        HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);

+        return DATA_ECC_CHECK_OK;

+    }

+    else if ( (stat & ECC_ERROR_REPAIR_CAN_NOT_TRUST) == ECC_ERROR_REPAIR_CAN_NOT_TRUST)

+    {

+        stat |= ECC_ERROR_REPAIR_CAN_NOT_TRUST;

+        HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);

+        HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);

+        return DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST;

+    }

+    else

+    {

+        return DATA_ECC_ERROR_REPAIR_CAN_TRUST;

+    }

+}

+

+//***********************************************************************************

+static T_U32 nf_check_repair_ecc(T_U8 *pMain_buf, T_U8 *pAdd_buf, 

+                    T_U32 section_size, T_U32 add_len, T_U32 ecc_type, T_BOOL  bSeparate_spare)

+{

+    T_U32   tmp,m,j;

+    T_U32   position_info;

+    T_U32   error_count;

+    T_U32   bit_errs;

+    T_U8    max_errcnt;

+    T_U8    ecc_stat; 

+

+    //wait for ECC complete

+    do

+    {

+        HAL_READ_UINT32(FLASH_ECC_REG0,tmp);

+    }while ((tmp  & ECC_CTL_DEC_RDY) == 0);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+

+    ecc_stat = nf_check_ecc_status(tmp);

+

+    switch(ecc_stat)

+    {

+        case DATA_ECC_CHECK_OK:

+            break;

+

+        case DATA_ECC_ERROR_REPAIR_CAN_TRUST:

+            if(ecc_type >= ECC_24BIT_P1KB)

+            {

+                max_errcnt = (ecc_type - 1) * 8;

+            } 

+            else

+            {

+                max_errcnt = (ecc_type + 1) * 4;

+            }

+

+            //ecc correct

+            for (error_count = 0; error_count < max_errcnt; error_count++)

+            {  

+                HAL_READ_UINT32(FLASH_ECC_REPAIR_REG0 + error_count * 4 ,position_info);

+                ecc_repair(position_info, pMain_buf, pAdd_buf, section_size, add_len, ecc_type);

+            }

+            break;

+

+        case DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST:

+            bit_errs = 0;

+            if (!bSeparate_spare)

+            {

+                for(j = 0; j < add_len; j++)

+                {

+                    if (0xff != *(pAdd_buf+ j))

+                    {

+                        for(m = 0; m < 8; m++)

+                        {

+                            if(0 == ((*(pAdd_buf + j)) & (1 << m)))

+                            {

+                                bit_errs++;

+                            }    

+                        }

+

+                        if(bit_errs > 3)

+                        {

+                            goto RETURN1;

+                        }

+                    }

+                } 

+

+                if(0 != bit_errs)

+                {

+                    memset(pAdd_buf, 0xFF, add_len);

+				}

+           }

+           else

+           {

+                for(j = 0; j < section_size; j++)

+                {

+                    if (0xff != *(pMain_buf + j))

+                    {

+                        for(m = 0; m < 8; m++)

+                        {

+                            if(0 == ((*(pMain_buf + j)) & (1 << m)))

+                            {

+                                bit_errs++;

+                            }    

+                        }

+

+                        if(bit_errs > 3)

+                        {

+                            goto RETURN1;

+                        }

+                    }

+                }

+

+                if(0 != bit_errs)

+                {

+                    memset(pMain_buf, 0xFF, section_size);

+                }    

+           }

+   

+           break;

+    }

+    

+    return ecc_stat;

+    

+RETURN1:

+    return DATA_ECC_CHECK_ERROR;  

+}

+

+

+static T_U32 ecc_repair(T_U32 wrong_info, T_U8 *main_buf, T_U8 *add_buf, T_U32 main_size, T_U32 add_size, T_U32 ecc_type)

+{

+    T_U32 position = (wrong_info>>9) & 0x3ff;

+    T_U32 offset;

+    T_U32 byte_index;

+    T_U8  correct;

+    T_U32 shift;

+    T_U32 ecccode_len = nf_get_ecccode_len(ecc_type);

+    T_U32 data_whole_len = main_size + add_size;

+

+    data_whole_len += ecccode_len;

+

+    if (position)

+    {

+        // There are chances that two errors fall into contiguous bits. Then position will have two bits set.

+        // For each bit of position

+        for (shift=0; shift<10; shift++)

+        {

+            if (0 == (position & (1<<shift)))

+            {

+                // no error in this block

+                continue;

+            }

+            

+            switch (position & (1<<shift))

+            {

+            case (1<<0):

+            case (1<<1):

+                // block1

+                byte_index = data_whole_len - 128 * 5;

+                break;

+                

+            case (1<<2):

+            case (1<<3):

+                // block2

+                byte_index = data_whole_len - 128 * 4;

+                break;

+                

+            case (1<<4):

+            case (1<<5):

+                // block3

+                byte_index = data_whole_len - 128 * 3;

+                break;

+                

+            case (1<<6):

+            case (1<<7):

+                // block4

+                byte_index = data_whole_len - 128 * 2;

+                break;

+                

+            case (1<<8):

+            case (1<<9):

+                // block5

+                byte_index = data_whole_len - 128 * 1;

+                break;

+            default:

+                while (1);

+                break;

+            }

+            

+            offset = 2 * (wrong_info & 0x1ff) + (((1<<shift)&0x2aa)? 1:0);

+            if (ECC_4BIT_P512B == ecc_type)

+            {

+                offset -= 4;

+                if (offset & 0x8000)

+                {

+                    byte_index -= 1;

+                    offset += 8;

+                }

+            }

+

+            byte_index += offset>>3;

+            correct = 1 << (7 - (offset&0x7));

+

+            if (byte_index < main_size)

+            {

+				// error occurs in data

+                main_buf[byte_index] ^= correct;

+            }

+            else if (byte_index < (main_size+add_size))

+            {

+				// error occurs in file system info

+                add_buf[byte_index - main_size] ^= correct;

+            }

+            else

+            {// error occurs in parity data

+                // nothing to do            

+            }

+        }

+    }

+    return 1;

+}

+

+//************************************************************************************

+/**

+* @BRIEF    check cmd_done bit

+* @AUTHOR   lgj

+* @MODIFY   yiruoxiang

+* @DATE     2006-7-17

+* @PARAM    T_VOID

+* @RETURN

+* @RETVAL

+*/

+static T_BOOL check_cmd_done(T_VOID)

+{

+    if ( 0 != (REG32(FLASH_CTRL_REG22) & BIT_DMA_CMD_DONE) )

+        return AK_TRUE;

+    else

+        return AK_FALSE;

+}

+

+//*****************************************************************************************

+/**

+ * @brief: start command sequence

+ */

+static T_VOID cmd_go(T_U32 Chip)

+{

+    volatile T_U32 status;

+

+    status = REG32(FLASH_CTRL_REG22);

+    status &= ~( NF_REG_CTRL_STA_CMD_DONE | NF_REG_CTRL_STA_CE0_SEL | NF_REG_CTRL_STA_CE1_SEL); //remove CE flag

+    status |= NCHIP_SELECT(Chip) | DEFAULT_GO;

+    REG32(FLASH_CTRL_REG22) = status;

+}

+

+//*****************************************************************************************

+static T_U32 calc_new(T_U8 data_opt_len, T_U8 data_we_fe, T_U8 data_we_re, T_U8 data_re_fe, T_U8 data_re_re)

+{

+    T_U32 dat_len;

+    

+    if (data_opt_len < 3)

+    {

+        data_opt_len = 3;

+    }

+    

+    if (data_opt_len == data_we_re)

+    {

+        data_we_re--;

+    }

+    

+    if (data_opt_len == data_re_re)

+    {

+        data_re_re--;

+    }

+

+    dat_len = (data_opt_len << 16) | (data_we_fe << 12) | (data_we_re << 8)

+              | (data_re_fe << 4) | (data_re_re << 0);

+

+    return dat_len;

+}

+

diff --git a/drivers/mtd/nand/ak88-nand/nand_control.h b/drivers/mtd/nand/ak88-nand/nand_control.h
new file mode 100644
index 00000000000..d8eb25694a6
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/nand_control.h
@@ -0,0 +1,194 @@
+/**

+ * @filename nand_control.h

+ * @brief AK880x nandflash driver

+ *

+ * This file describe how to control the AK880x nandflash driver.

+ * Copyright (C) 2008 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author yiruoxiang

+ * @modify jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ * @ref

+ */

+#ifndef __NAND_CONTORL_H__

+#define __NAND_CONTORL_H__

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @defgroup NandFlash Architecture NandFlash Interface

+ *  @ingroup Architecture

+ */

+/*@{*/

+

+/* contorl/status register */

+#define NF_REG_CTRL_STA_CMD_DONE  (1UL << 31)

+#define NF_REG_CTRL_STA_CE0_SEL   (1 << 10)

+#define NF_REG_CTRL_STA_CE1_SEL   (1 << 11)

+#define NF_REG_CTRL_STA_STA_CLR   (1 << 14)

+

+/* dma cpu control register */

+#define BIT_DMA_CMD_DONE          0x80000000

+

+/* ECC control bit */

+#define ECC_CTL_DIR_READ        (0<<2)

+#define ECC_CTL_ADDR_CLR        (1<<4)

+#define ECC_CTL_NFC_EN          (1<<20)

+#define ECC_CTL_BYTE_CFG(m)     ((m)<<7)  

+#define ECC_CTL_MODE(n)         ((n)<<22)

+#define ECC_CTL_START           (1<<3)

+#define ECC_CTL_DEC_EN          (1<<1)

+#define ECC_CTL_RESULT_NO_OK    (1<<27)

+#define ECC_CTL_END             (1<<6)

+#define ECC_CTL_NO_ERR          (1<<26)

+#define ECC_CTL_DIR_WRITE       (1<<2)

+#define ECC_CTL_ENC_EN          (1<<0)

+#define ECC_CTL_DEC_RDY         (1<<24)

+#define ECC_CTL_ENC_RDY         (1<<23)

+

+#define ECC_CHECK_NO_ERROR                              (0x1<<26)

+#define ECC_ERROR_REPAIR_CAN_NOT_TRUST                  (0x1<<27)

+

+#define DATA_ECC_CHECK_OK                               1

+#define DATA_ECC_CHECK_ERROR                            0

+#define DATA_ECC_ERROR_REPAIR_CAN_TRUST                 2

+#define DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST             3

+

+//  |               page               |

+//  | data | fs(file system) | parity  |

+//  | data |          spare            |

+#define NAND_DATA_SIZE            512  

+#define NAND_FS_SIZE              4

+#define NAND_PARITY_SIZE_MODE1    13

+#define NAND_PARITY_SIZE_MODE0    7

+

+/// @cond NANDFLASH_DRV

+//******************************************************************************************//

+//ͨ¹ýCTRL reg0½øÐÐÃüÁîѹջµÄ˵Ã÷ÈçÏ¡££¨¹²7¸öconfiuration£¬1¸öflag£©

+//*************reg0~reg19ÃüÁîµÄÀàÐÍÈçÏÂ***********

+/*

+1,nandflash±¾ÉíÊý¾Ý×ÜÏßÉÏ´«ÊäÊý¾ÝµÄÀàÐÍ

+a,COMMAND_CYCLES_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄÊÇNandflashÃüÁ

+b,ADDRESS_CYCLES_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄÊÇNandflashµØÖ·ÐÅÏ¢

+c,WRITE_DATA_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄFIFOÖеÄÊý¾ÝÐÅÏ¢£¬

+ÓÉÓÚ¶Á³öÊý¾Ý¿ÉÄÜ·ÅÔÚ²»Í¬Î»Öã¬ËùÒÔÕâÀïÓÐÁ½ÖÖ¶ÁÊý¾ÝÃüÁî

+d£¬READ_DATA_CONF£º±íʾÊý¾ÝÖÐ×ÜÏ߶ÁÊý¾Ý£¬¶Á³öÊý¾Ý·ÅÔÚFIFOÖÐ

+e£¬READ_CMD_CONFÕâÃüÃûºÃÏñ²»Ì«ºÃ£¬ÎÒ°ÑËü¸ÄΪREAD_INFO_CONF

+  ±íʾÊý¾Ý×ÜÏßÉ϶ÁµÄÊÇ״̬»òÊÇIDÐÅÏ¢Ö¸Áî,(Ò²¿ÉÓÃÓÚ¶ÁȡСÓÚ

+  8 byteµÄÊý¾ÝÁ½£©¶Á³öÊý¾Ý·ÅÔÚreg20

+

+  ÁíÍ⣬Èç¹û´øÉÏECCµÄ¶Á£¬Ð¾Æ¬»á×Ô¶¯°ÑdataÐÅÏ¢ºÍÎļþϵͳÐÅÏ¢·Åµ½Ïà

+  Ó¦µÄFIFOºÍ¼Ä´æÆ÷¡£

+

+2,ÓënandflashÎ޹أ¬ÎªÁËÒýÈëÑÓʱºÍÈ·¶¨¶ÁдԤ´¦ÀíµÈ´ýÍê³ÉʱÒýÈëµÄÃüÁî

+f,DELAY_CNT_CONF ÓÉÓÚnandflash²»»áÂíÉÏÏàÓ¦ÃüÁ´óÔ¼ÓÐ3usµ½50usµÄÑÓʱ£¬

+  Êý¾Ý²Å»á×¼±¸ºÃ£¬ËùÒÔÒýÈë¸ÃÃüÁî¡£ÑÓʱʱ¼äÔÚbit11~bit22ÖÐдÈë

+g.WAIT_JUMP_CONF ÔÚNandflash²Ù×÷ÖУ¬³ýÁË¿ÉÒÔ¶Ástatus Èí¼þ²éѯ״̬Í⣬

+»¹ÓÐÒ»¸öR/BÒý½ÅÓÃÀ´¸¨Öú¿ìËÙÈ·¶¨¶Áд²Ù×÷ÊÇ·ñÍê³É¡£¸ÃÃüÁîµÈ´ýÉÏÌøÑÓ´¥·¢¡£

+

+ÉÏÃæÃüÁîÿ´ÎÈÎÑ¡ÇÒÖ»ÄÜÑ¡Ò»Ìõ£¬²»¶Ïͨ¹ýreg0µØַѹµ½ÃüÁîÕ»ÖУ¬¼´¿ÉʵÏÖ¶Ô

+nandflashµÄËùÓвÙ×÷

+Èç¹ûÊÇ×îºóÒ»ÌõÖ¸Á±ØÐë´òÉÏLAST_CMD_FLAG±êÖ¾

+*/

+

+//////// command sequece configuration define ////////////

+

+/* command cycle's configure:

+ *      CMD_END=X, ALE=0, CLE=1, CNT_EN=0,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define COMMAND_CYCLES_CONF     0x64

+/* address cycle's:

+ *      CMD_END=X, ALE=1, CLE=0, CNT_EN=0,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define ADDRESS_CYCLES_CONF     0x62

+

+/*  read data cycle's:

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=1, WEN=0, CMD_EN=0, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define READ_DATA_CONF          0x118

+

+/*  write data cycle's:

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=0, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define WRITE_DATA_CONF         0x128

+

+/* read command status's:(example: read ID(pass), status(pass), »Ø¶ÁÊý¾Ý±È½ÏÉٵIJÙ×÷?

+//¸æËßоƬÏÖÔÚ¶ÁÈ¡status IDÐÅÏ¢£¬Ð¾Æ¬°Ñ¸ÃÐÅÏ¢°áµ½ÏàÓ¦¼Ä´æÆ÷(8 byte)£¬¶ø²»ÊÇFIFO¡£·½±ã²éѯNandflash״̬¡£

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=1, WEN=0, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define READ_INFO_CONF          0x58

+

+//wait delay time enable bit

+#define DELAY_CNT_CONF          (1<<10)

+

+//wait R/b enable bit

+#define WAIT_JUMP_CONF          (1<<9)

+

+// last command's bit0 set to 1

+#define LAST_CMD_FLAG           (1<<0)

+

+

+//#######excute comamnd,ctrl reg22 command configuration define ################

+//ËùÓеÄÅäÖö¨ÒåÕë¶Ô·¢ËÍÃüÁîµÄ·½Ê½¡£

+//±ØÐë½øÐÐƬѡ»òƬ±£»¤¡¢²Ù×÷ģʽ¡¢ÒÔ¼°ÊÇ·ñʹÄܵÄÊ¡µçģʽflag

+//ƬѡʹÓúêNCHIP_SELECT(x)

+#define NCHIP_SELECT(x)         ((0x01 << (x)) << 10)

+

+/*

+bit0(save mode) = 0;

+bit1-bit8(staff_cont)=0

+bit9(watit save mode jump) = 0

+bit10-bit13(chip select)=0

+bit14(sta_clr)=0

+bit15-bit18(write protect)=0

+bit19-bit29 reserved =0;

+bit30(start control) = 1;

+bit31(check statu) = 0;

+*/

+#define DEFAULT_GO                  ((1 << 30)|(1<<9))

+

+

+/** @{@name Command List and Status define

+ *  Define command set and status of nandflash

+ */

+#define NFLASH_READ1                0x00

+#define NFLASH_READ2                0x30

+#define NFLASH_READ1_HALF           0x01

+#define NFLASH_READ22               0x50

+

+#define NFLASH_COPY_BACK_READ       0x35

+#define NFLASH_COPY_BACK_WRITE      0x85

+#define NFLASH_COPY_BACK_WRITE1     0x8A

+#define NFLASH_COPY_BACK_CONFIRM    0x10

+#define NFLASH_RESET                0xff

+

+#define NFLASH_FRAME_PROGRAM0       0x80

+#define NFLASH_FRAME_PROGRAM1       0x10

+

+#define NFLASH_BLOCK_ERASE0         0x60

+#define NFLASH_BLOCK_ERASE1         0xD0

+#define NFLASH_STATUS_READ          0x70

+#define NFLASH_READ_ID              0x90

+

+//status register bit

+#define NFLASH_PROGRAM_SUCCESS      0x01 //bit 0

+#define NFLASH_HANDLE_READY         0x40 //bit 6

+#define NFLASH_WRITE_PROTECT        0x80 //bit 7

+

+/*@}*/

+#ifdef __cplusplus

+}

+#endif

+

+#endif //__NAND_CONTORL_H__

diff --git a/drivers/mtd/nand/ak88-nand/nand_flash_drv.h b/drivers/mtd/nand/ak88-nand/nand_flash_drv.h
new file mode 100644
index 00000000000..cbfcb98d0cc
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/nand_flash_drv.h
@@ -0,0 +1,121 @@
+/*
+ *	driver for nand flash
+ */
+
+#ifndef _NAND_FLASH_DRV_H_
+#define _NAND_FLASH_DRV_H_
+
+//#include "AK3220_types.h"
+
+#define ECC_MODE1		// ECC mode 0 if not defined
+//#define L2_DMA_MODE   // CPU mode if not defined
+
+#define TEST_FAULT_NUM		8	// # of error bits to simulate
+#define NAND_PAGE_PER_PHYPAGE	4
+
+#define NAND_MAX_PAGE_SIZE	640
+
+//  |               page               |
+//  | data | fs(file system) | parity  |
+//  | data |          spare            |
+#ifdef  ECC_MODE1
+#define ECC_CTL_MODE		ECC_CTL_MODE1
+#define NAND_PARITY_SIZE	13
+#define MAX_ERROR_CNT		8
+#define NAND_PAGE_SIZE		528
+#else
+#define ECC_CTL_MODE		ECC_CTL_MODE0
+#define NAND_PARITY_SIZE	7
+#define MAX_ERROR_CNT		4
+#define NAND_PAGE_SIZE		528
+#endif
+
+#define NAND_DATA_SIZE		512
+#define NAND_SPARE_SIZE		(NAND_PAGE_SIZE-NAND_DATA_SIZE)
+#define NAND_FS_SIZE		(NAND_SPARE_SIZE-NAND_PARITY_SIZE)
+#define NAND_EFFECTIVE_SIZE	(NAND_DATA_SIZE+NAND_FS_SIZE)
+
+#define FAULT_NUM		(TEST_FAULT_NUM>MAX_ERROR_CNT? MAX_ERROR_CNT:TEST_FAULT_NUM)
+
+////// flash macro define ////////////////////////////////////
+
+#define COMMAND_SEQUENCE_TOTAL	8
+#define LARGE_PAGE_LEN		2048	// 2KB
+#define SMALL_PAGE_LEN		512	// 512B
+#define NFC_FIFO_LEN		512	// AK3223 nand flash controller's FIFO length
+#define NAND_FLASH_MAX_DELAY	0xFFF	// 50 mS #84MHz
+
+#define NAND_FLASH_DEFAULT_DELAY	0xa	// change this parameter all spec is descript 5us for reset
+
+#define MAX_NAND_SECOND_BOOT_SIZE	0x40001A88	// 6792 bytes LIMIT
+////// end flash macro define ////////////////////////////////////
+
+#define NFLASH_READ_ID		0x90
+#define NFLASH_READ_STATUS	0x70
+#define NFLASH_RESET		0xff
+
+#define NFLASH_BLOCK_ERASE0	0x60
+#define NFLASH_BLOCK_ERASE1	0xd0
+
+#define NFLASH_PAGE_PROGRAM0	0x80
+#define NFLASH_PAGE_PROGRAM1	0x10
+
+#define NFLASH_CACHE_PROGRAM0	0x80
+#define NFLASH_CACHE_PROGRAM1	0x15
+
+#define NFLASH_CB_PROGRAM0	0x85
+#define NFLASH_CB_PROGRAM1	0x10
+
+#define NFLASH_RAN_PROGRAM	0x85
+
+#define NFLASH_READ0		0x00
+#define NFLASH_READ0_HALF	0x01
+#define NFLASH_READ1		0x30
+#define NFLASH_READ12		0x50
+
+#define NFLASH_CB_READ0		0x00
+#define NFLASH_CB_READ1		0x35
+
+#define NFLASH_RAN_READ0	0x05
+#define NFLASH_RAN_READ1	0xe0
+#define DEFAULT_GO		(1 << 30)
+
+#define AK_NAND_STATUS_READY 	(1 << 6)
+#define AK_NAND_STATUS_ERROR 	(1 << 0)
+
+#define NCHIP_SELECT(x)		((0x01 << (x)) << 10)
+
+
+#define FLASH_ECC_POSITION_REG0     (AK88_VA_ECCCTRL + 0X04)
+
+/**  very important!!! **/
+#define DATA_SIZE 4096      /**/
+#define OOB_SIZE  128
+
+//#define PAGE_SIZE 4224
+
+
+extern unsigned long ak880x_nand_get_chipid(unsigned char chip);
+extern void ak880x_nand_settiming(unsigned long cmd_timing,
+				  unsigned long data_timing);
+extern unsigned char ak880x_nand_get_status(unsigned char chip);
+extern void ak880x_nand_eraseblock(unsigned char chip, unsigned int phypage);
+extern void ak880x_nand_reset(unsigned char chip, unsigned short wait_time);
+extern void ak880x_nand_inithw(void);
+extern void ak880x_nand_read_page(unsigned char chip, unsigned int row,
+				  unsigned int col, unsigned char *buf,
+				  unsigned int len, unsigned char large_page);
+extern void ak880x_nand_write_page(unsigned char chip, unsigned int row,
+				   unsigned int col, const unsigned char *buf,
+				   unsigned int len, unsigned char large_page);
+
+void nand_write_page_ecc( int page, const unsigned char *buf,const unsigned char *oobbuf);
+void nand_read_page_ecc( int page, unsigned char * buf,unsigned char *oobbuf);
+void nand_read_page_data( int page, unsigned char * data_buf);
+void nand_read_page_oob( int page, unsigned char * oob_buf);
+
+void nand_read_oob_ecc( int page, unsigned char *oobbuf);
+void nand_write_page_ecc_part( int page, const unsigned char *buf,int len );
+void nand_read_page_ecc_part( int page, unsigned char * buf,int len );
+
+#endif				// _NAND_FLASH_DRV_H_
diff --git a/drivers/mtd/nand/ak88-nand/sysctl.h b/drivers/mtd/nand/ak88-nand/sysctl.h
new file mode 100644
index 00000000000..852230d3b5f
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/sysctl.h
@@ -0,0 +1,91 @@
+/**

+* @FILENAME sysctl.h

+*

+* Copyright (C) 2006 Anyka (Guangzhou) Software Technology Co., LTD

+* @DATE  2006-04-19

+* @VERSION 1.0

+* @REF 

+*/

+

+#ifndef __SYSCTL_H__

+#define __SYSCTL_H__

+

+/*ÒÔ϶¨ÒåµÄclock Ä£¿é±ØÐë¶ÀÁ¢£¬²»ÄÜÒ»¸öÄ£¿é°üº¬¶à¸ö¿É¿ØÖÆclockµÄ×ÓÄ£¿é*/

+#define CLOCK_DEFAULT_ENABLE                        (0)

+#define CLOCK_CAMERA_ENABLE                         (1<<0)

+#define CLOCK_LCD_ENABLE                            (1<<1)

+#define CLOCK_USB_ENABLE                            (1<<2)

+#define CLOCK_MMCSD_ENABLE                          (1<<3)

+#define CLOCK_UART0_ENABLE                          (1<<4)

+#define CLOCK_UART1_ENABLE                          (1<<5)

+#define CLOCK_UART2_ENABLE                          (1<<6)

+#define CLOCK_UART3_ENABLE                          (1<<7)

+#define CLOCK_SDIO_ENABLE                           (1<<8)

+#define CLOCK_SPI_ENABLE                            (1<<9)

+#define CLOCK_NAND_ENABLE                           (1<<10)

+#define CLOCK_NBITS                                 (11)

+#define CLOCK_ENABLE_MAX                            (1<<CLOCK_NBITS)

+

+/** CLOCK control register bit map*/

+#define CLOCK_CTRL_IMAGE_H263_MPEG4                 (0x1)

+#define CLOCK_CTRL_CAMERA                           (1 << 1)

+#define CLOCK_CTRL_SPI12_MMC_UART2                  (1 << 2)

+#define CLOCK_CTRL_LCD                              (1 << 3)

+#define CLOCK_CTRL_AUDIO                            (1 << 4)

+#define CLOCK_CTRL_USBOTG                           (1 << 5)

+#define CLOCK_CTRL_H264                             (1 << 6)

+#define CLOCK_CTRL_USBFS                            (1 << 7)

+#define CLOCK_CTRL_SDIO_UART34                      (1 << 8)

+#define CLOCK_CTRL_SDRAM_DDR                        (1 << 10)

+#define CLOCK_CTRL_MOTION_MODULE                    (1 << 11)

+#define CLOCK_CTRL_2D_ACCELERATOR                   (1 << 12)

+#define CLOCK_CTRL_NANDFLASH                        (1 << 13)

+#define CLOCK_CTRL_L2_UART1                         (1 << 15)

+

+#define RESET_IMAGE_PROCESS                         (1<<16)

+#define RESET_CAMERA                                (1<<17)

+#define RESET_SPI                                   (1<<18)

+#define RESET_SDMMC                                 (1<<18)

+#define RESET_PCM                                   (1<<18)

+#define RESET_UART2                                 (1<<18)

+#define RESET_LCD                                   (1<<19)

+#define RESET_GPS                                   (1<<20)

+#define RESET_USB_OTG                               (1<<21)

+#define RESET_H264_DECODER                          (1<<22)

+#define RESET_USB_FS                                (1<<23)

+#define RESET_SDIO                                  (1<<24)

+#define RESET_UART3                                 (1<<24)

+#define RESET_UART4                                 (1<<24)

+#define RESET_RAM                                   (1<<26)

+#define RESET_MOTION_ESTIMATE                       (1<<27)

+#define RESET_GRAPHICS                              (1<<28)

+#define RESET_NANDFLASH                             (1<<29)

+#define RESET_L2                                    (1<<31)

+#define RESET_UART1                                 (1<<31)

+

+

+/**

+ * @BRIEF Set SleepMode

+ * @AUTHOR guoshaofeng

+ * @DATE 2007-04-23

+ * @PARAM[in] T_U32 module

+ * @RETURN T_VOID

+ * @RETVAL

+ * attention: if you close some parts such as LCD 

+            you must init it again when you reopen 

+            it 

+            some settings may cause serious result

+            better not to use it if not familar

+ */

+T_VOID sysctl_clock(T_U32 module);

+

+/**

+ * @brief reset module 

+ * @author guoshaofeng

+ * @date 2010-07-20

+ * @param module [in]: module to be reset

+ * @return T_VOID

+ */

+T_VOID sysctl_reset(T_U32 module);

+

+#endif //__SYSCTL_H__
\ No newline at end of file
diff --git a/drivers/mtd/nand/ak88-nand/wrap_nand.c b/drivers/mtd/nand/ak88-nand/wrap_nand.c
new file mode 100644
index 00000000000..0a852d8d9f8
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/wrap_nand.c
@@ -0,0 +1,840 @@
+/**

+ * @filename wrap_nand.c

+ * @brief AK880x nandflash driver

+ *

+ * This file wrap the nand flash driver in nand_control.c file.

+ * Copyright (C) 2010 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author zhangzheng

+ * @modify 

+ * @date 2010-10-10

+ * @version 1.0

+ * @ref

+ */

+

+#include <linux/list.h>

+#include <linux/init.h>

+#include <linux/mtd/partitions.h>

+#include <linux/math64.h>

+#include <mtd/mtd-abi.h>

+#include "anyka_cpu.h"

+#include "nand_control.h"

+#include "wrap_nand.h"

+

+#define NAND_DATA_SIZE_P1KB         1024

+#define NAND_DATA_SIZE_P512B        512

+#define YAFFS_OOB_SIZE              28

+

+#define PASSWORD_ADDR_OFFSET	    (4)

+#define PASSWORD_STR			    "ANYKA782"                 

+#define PASSWORD_LENGTH			    (sizeof(PASSWORD_STR) - 1) 

+

+#define ZZ_DEBUG                    0

+

+extern int page_shift;

+extern struct mtd_info *g_master;

+

+T_Nandflash_Add g_sNF = {

+							{0,0,0,0}, 

+							3, 

+							2, 

+							NAND_4K_PAGE, 

+							ECC_4BIT_P512B, 

+							4096, 

+							128

+					    };

+

+T_NAND_PHY_INFO *g_pNand_Phy_Info = NULL;

+

+#if 1

+T_PNandflash_Add g_pNF = NULL;

+#else

+T_PNandflash_Add g_pNF = &g_sNF;

+#endif 

+

+T_PFHA_INIT_INFO g_pinit_info = NULL;

+T_PFHA_LIB_CALLBACK g_pCallback = NULL;

+

+T_Nandflash_Add try_nf_add[] = 

+{

+	{{0,0,0,0}, 3, 2, NAND_4K_PAGE, ECC_8BIT_P512B, 4096, 128},

+	{{0,0,0,0}, 2, 1, NAND_512B_PAGE, ECC_8BIT_P512B, 512, 128},

+	{{0,0,0,0}, 2, 1, NAND_512B_PAGE, ECC_8BIT_P512B, 512, 128}

+};

+

+int init_fha_lib(void)

+{

+	int retval = 0;

+	

+	g_pinit_info = kmalloc(sizeof(T_FHA_INIT_INFO), GFP_KERNEL);

+	if(g_pinit_info == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c init_fha_lib() 71 g_pinit_info==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+

+	g_pinit_info->nChipCnt = 1;

+	g_pinit_info->nBlockStep = 1;

+	g_pinit_info->eAKChip = CHIP_880X;

+	g_pinit_info->ePlatform = PLAT_LINUX;

+	g_pinit_info->eMedium = MEDIUM_NAND;

+	g_pinit_info->eMode = 0;

+			

+	g_pCallback = kmalloc(sizeof(T_FHA_LIB_CALLBACK), GFP_KERNEL);

+	if(g_pCallback == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c init_fha_lib() 85 g_pCallback==NULL\n");

+		return FHA_FAIL;

+	}

+	g_pCallback->Erase = nand_erase_callback;

+	g_pCallback->Write = (FHA_Write)nand_write_callback;

+	g_pCallback->Read = (FHA_Read)nand_read_callback;

+	g_pCallback->RamAlloc = ram_alloc;

+	g_pCallback->RamFree = ram_free;

+	g_pCallback->MemCmp = (FHA_MemCmp)memcmp;

+	g_pCallback->MemSet = (FHA_MemSet)memset;

+	g_pCallback->MemCpy = (FHA_MemCpy)memcpy;

+	g_pCallback->Printf = (FHA_Printf)printk; //print_callback;

+	g_pCallback->ReadNandBytes = nand_read_bytes_callback;

+

+	#ifndef CONFIG_MTD_DOWNLOAD_MODE

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 101 before FHA_mount()\n");

+	#endif

+	retval = FHA_mount(g_pinit_info, g_pCallback);

+

+	if (retval)

+	{

+		init_globe_para();

+	}

+	else

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() FHA_mount return:%d error!!!\n", retval);

+		return FHA_FAIL;

+	}

+	

+	FHA_asa_scan(AK_TRUE);

+	#else

+	if(g_pNand_Phy_Info == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c init_fha_lib() 120 g_pNand_Phy_Info==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+	

+	retval =  FHA_burn_init(g_pinit_info, g_pCallback, g_pNand_Phy_Info);

+	FHA_asa_scan(AK_TRUE);

+	#endif

+

+	if(retval == FHA_FAIL)

+	{

+		kfree(g_pinit_info);

+		kfree(g_pCallback);

+		g_pinit_info = NULL;

+		g_pCallback = NULL;

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 134 failed!!!\n");

+	}

+	return retval;

+}

+

+void Nand_Config_Data(T_PNAND_ECC_STRU data_ctrl, T_U8* data, T_U32 data_len, ECC_TYPE ecc_type)

+{

+

+    data_ctrl->buf = data;   

+

+    data_ctrl->buf_len = data_len;

+

+    data_ctrl->ecc_section_len = (ecc_type > ECC_12BIT_P512B) ? NAND_DATA_SIZE_P1KB : NAND_DATA_SIZE_P512B;

+

+    data_ctrl->ecc_type = (ecc_type > ECC_12BIT_P512B) ? ECC_12BIT_P512B : ecc_type;

+

+} 

+

+void Nand_Config_Spare(T_PNAND_ECC_STRU spare_ctrl, T_U8* spare, T_U32 spare_len, ECC_TYPE ecc_type)

+{

+

+    spare_ctrl->buf = spare;

+

+    spare_ctrl->buf_len= spare_len;

+

+    spare_ctrl->ecc_section_len = spare_len;

+

+    spare_ctrl->ecc_type = (ecc_type > ECC_12BIT_P512B) ? ECC_12BIT_P512B : ecc_type;

+

+}

+

+void ak_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    struct nand_chip *chip = mtd->priv;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_write_buf() 176 g_pNF==NULL error!!!\n");

+		return;

+	}

+    Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+    nand_writepage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);  

+}

+

+void ak_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    struct nand_chip *chip = mtd->priv;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_buf() 195 g_pNF==NULL error!!!\n");

+		return;

+	}

+    Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+    nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);   

+}

+

+void ak_nand_select_chip(struct mtd_info *mtd, int chip)

+{

+

+}

+

+u_char ak_nand_read_byte(struct mtd_info *mtd)

+{

+    T_U32 retval = 0;

+    return (u_char)retval;

+}

+

+int ak_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                   uint8_t *buf, int page)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_page_hwecc() 224 g_pNF==NULL error!!!\n");

+		return 1;

+	} 

+ 	Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+    return nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);

+}

+

+void ak_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                     const uint8_t *buf)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_write_page_hwecc() 242 g_pNF==NULL error\n");

+		return;

+	}

+	Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+    nand_writepage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);

+}

+

+int ak_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+			                    uint8_t *buf, int pag)

+{

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_read_page_raw() 254\n");

+	#endif

+    return 0;

+}

+

+void ak_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+				                  const uint8_t *buf)

+{

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_write_page_raw() 263\n");

+	#endif

+}

+

+static T_U8 zz_buf[4096];

+

+int ak_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page, int sndcmd)

+{      

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_oob() 280 g_pNF==NULL error!!!\n");

+		return 1;

+	}

+    if (sndcmd) 

+    {

+		chip->cmdfunc(mtd, 0x50, 0, page); //0x50 read oob cmd

+		sndcmd = 0;
+	}

+	Nand_Config_Data(&data_ctrl, zz_buf, g_pNF->PageSize, g_pNF->EccType);

+	Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+    nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);   

+	return sndcmd;

+}

+

+int ak_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page)

+{

+    return 0;

+}

+

+T_U32 nand_erase_callback(T_U32 chip_num,  T_U32 startpage)

+{

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_erase_callback() 304 g_pNF==NULL error\n");

+		return 1;

+	}

+    return nand_eraseblock(chip_num, startpage, g_pNF);

+}

+

+T_U32 nand_read_callback(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	int i = 0;

+	int try_count = sizeof(try_nf_add)/sizeof(try_nf_add[0]);

+	

+	if(eDataType == FHA_GET_NAND_PARAM)

+	{

+		#if 1

+		printk(KERN_INFO "zz wrap_nand.c nand_read_callback() 321 eDataType == FHA_GET_NAND_PARAM\n");

+		#endif

+		for(i=0; i<try_count; i++)

+		{	

+			#if 1

+			printk(KERN_INFO "i=%d row_cycle=%d col_cycle=%d chip_type=%d ecc_type=%d page_size=%d PagesPerBlock=%d\n",

+			       i, try_nf_add[i].RowCycle, try_nf_add[i].ColCycle, try_nf_add[i].ChipType, try_nf_add[i].EccType,

+			       try_nf_add[i].PageSize, try_nf_add[i].PagesPerBlock);

+			#endif

+			if(AK_TRUE== try_nand_para(chip_num, page_num, data, data_len, oob, oob_len, &try_nf_add[i]))

+			{

+				#if 1

+				printk(KERN_INFO "zz wrap_nand.c nand_read_callback() 333 try nand para successed i=%d\n", i);

+				#endif

+				return FHA_SUCCESS;

+			}

+		}

+		return FHA_FAIL;

+		#if 0

+		data_ctrl.buf = data;

+    	data_ctrl.buf_len = data_len;

+    	data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    	spare_ctrl.buf = oob;

+    	spare_ctrl.buf_len = oob_len;

+    	spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	spare_ctrl.ecc_type = ECC_8BIT_P512B;

+

+		nand_readpage_ecc(chip_num, page_num, 0, &try_nf_add[i], &data_ctrl, &spare_ctrl);

+		#endif

+		

+	}

+	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_read_callback() 357 g_pNF==NULL error\n");

+		return FHA_FAIL;

+	}

+	

+    if(eDataType == FHA_DATA_BOOT)

+    {

+    	data_ctrl.buf = data;

+    	data_ctrl.buf_len = data_len;

+    	data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    	spare_ctrl.buf = oob;

+    	spare_ctrl.buf_len = oob_len;

+    	spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	spare_ctrl.ecc_type = ECC_8BIT_P512B;

+    }

+	else if (eDataType == FHA_DATA_ASA || eDataType == FHA_DATA_BIN)

+	{

+		data_ctrl.buf = data;

+    	data_ctrl.buf_len = data_len;

+    	data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	data_ctrl.ecc_type = g_pNF->EccType;

+

+    	spare_ctrl.buf = oob;

+    	spare_ctrl.buf_len = oob_len;

+    	spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	spare_ctrl.ecc_type = g_pNF->EccType;

+	} 

+	else

+	{

+    	Nand_Config_Data(&data_ctrl, data, data_len, g_pNF->EccType);

+		Nand_Config_Spare(&spare_ctrl, oob, oob_len, g_pNF->EccType);

+	}

+	

+    nand_readpage_ecc(chip_num, page_num, 0, g_pNF, &data_ctrl, &spare_ctrl); 

+	

+	return FHA_SUCCESS;

+}

+

+T_U32 nand_write_callback(T_U32 chip_num, T_U32 page_num, const T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType)

+{ 

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_write_callback() 404 g_pNF==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+

+    if(eDataType == FHA_DATA_BOOT)

+    {

+    	data_ctrl.buf = data;

+    	data_ctrl.buf_len = data_len;

+    	data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    	spare_ctrl.buf = oob;

+    	spare_ctrl.buf_len = oob_len;

+    	spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	spare_ctrl.ecc_type = ECC_8BIT_P512B;

+    }

+	else if (eDataType == FHA_DATA_ASA || eDataType == FHA_DATA_BIN)

+	{

+		data_ctrl.buf = data;

+    	data_ctrl.buf_len = data_len;

+    	data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	data_ctrl.ecc_type = g_pNF->EccType;

+

+    	spare_ctrl.buf = oob;

+    	spare_ctrl.buf_len = oob_len;

+    	spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    	spare_ctrl.ecc_type = g_pNF->EccType;

+	}

+	else

+	{

+    	Nand_Config_Data(&data_ctrl, data, data_len, g_pNF->EccType);

+		Nand_Config_Spare(&spare_ctrl, oob, oob_len, g_pNF->EccType);

+	}

+	

+    nand_writepage_ecc(chip_num, page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);

+	return FHA_SUCCESS;

+}

+

+T_U32 nand_read_bytes_callback(T_U32 nChip, T_U32 rowAddr, T_U32 columnAddr, T_U8 *pData, T_U32 nDataLen)

+{

+	return nand_readbytes(nChip, rowAddr, columnAddr, g_pNF, pData, nDataLen);

+}

+

+void *ram_alloc(T_U32 size)

+{

+	return kmalloc(size, GFP_KERNEL);

+}

+

+void *ram_free(void *point)

+{

+	kfree(point);

+	return NULL;

+}

+

+T_S32 print_callback(T_pCSTR s, ...)

+{

+	printk(KERN_INFO "%s", s);

+	return AK_TRUE;

+}

+

+T_U32 init_globe_para(void)

+{

+	int ret = AK_FALSE;

+	printk(KERN_NOTICE "zz wrap_nand.c init_globe_para() 429\n");

+

+	if(g_pNand_Phy_Info != NULL && g_pNF != NULL)

+	{

+		return AK_TRUE;

+	}

+	g_pNand_Phy_Info = kmalloc(sizeof(T_NAND_PHY_INFO), GFP_KERNEL);

+	if(g_pNand_Phy_Info == NULL)

+	{

+		printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 471 g_pNand_Phy_Info=NULL error!!!\n");

+		return AK_FALSE;

+	}

+	

+	if(g_pinit_info!=NULL && g_pCallback!=NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c init_globe_para() 477 before FHA_get_nand_para()\n");

+		ret = FHA_get_nand_para(g_pNand_Phy_Info);

+		printk(KERN_NOTICE "zz wrap_nand.c init_globe_para() 479 after FHA_get_nand_para() return %d\n", ret);

+		if(ret == AK_FALSE)

+		{

+			printk(KERN_INFO "zz wrap_nand.c init_globe_para() 482 get nand para with fha lib error!!!\n");

+			return AK_FALSE;

+		}

+	}

+	else

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_globe_para() 488 init fha lib fail!!!\n");

+		return AK_FALSE;

+	}

+	

+

+	g_pNF = kmalloc(sizeof(T_Nandflash_Add), GFP_KERNEL);

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 496 g_pNF==NULL error!!!\n");

+		return AK_FALSE;

+	}

+	g_pNF->RowCycle      = g_pNand_Phy_Info->row_cycle;

+	g_pNF->ColCycle      = g_pNand_Phy_Info->col_cycle;

+	g_pNF->PageSize      = g_pNand_Phy_Info->page_size;

+	g_pNF->PagesPerBlock = g_pNand_Phy_Info->page_per_blk;

+	g_pNF->EccType       = (T_U8)((g_pNand_Phy_Info->flag & 0xf0) >> 4);  //4-7 bit is ecc type

+

+	switch(g_pNand_Phy_Info->page_size)

+	{

+		case 512:

+		{

+			g_pNF->ChipType = NAND_512B_PAGE;

+			break;

+		}

+		case 2048:

+		{

+			g_pNF->ChipType = NAND_2K_PAGE;

+			break;

+		}

+		case 4096:

+		{

+			g_pNF->ChipType = NAND_4K_PAGE;

+			break;

+		}	

+		case 8192:

+		{

+			g_pNF->ChipType = NAND_8K_PAGE;

+			break;

+		}

+		default:

+		{

+			printk(KERN_INFO "zz wrap_nand.c init_globe_para() 529 g_pNand_Phy_Info->page_size=%d Error!!!\n",

+				   g_pNand_Phy_Info->page_size);

+		}

+	}

+	

+	#if 1 //ZZ_DEBUG

+	printk(KERN_INFO "---------------------zz wrap_nand.c init_globe_para() 535------------------------\n");

+	printk(KERN_INFO "----------------------------Nand Physical Parameter------------------------------\n");

+	printk(KERN_INFO "chip_id = 0x%x\n", g_pNand_Phy_Info->chip_id);

+	printk(KERN_INFO "page_size = %d\n", g_pNand_Phy_Info->page_size);

+	printk(KERN_INFO "page_per_blk = %d\n", g_pNand_Phy_Info->page_per_blk);

+	printk(KERN_INFO "blk_num = %d\n", g_pNand_Phy_Info->blk_num);

+	printk(KERN_INFO "group_blk_num = %d\n", g_pNand_Phy_Info->group_blk_num);

+	printk(KERN_INFO "plane_blk_num = %d\n", g_pNand_Phy_Info->plane_blk_num);

+	printk(KERN_INFO "spare_size = %d\n", g_pNand_Phy_Info->spare_size);

+	printk(KERN_INFO "col_cycle = %d\n", g_pNand_Phy_Info->col_cycle);

+	printk(KERN_INFO "lst_col_mask = %d\n", g_pNand_Phy_Info->lst_col_mask);

+	printk(KERN_INFO "row_cycle = %d\n", g_pNand_Phy_Info->row_cycle);

+	printk(KERN_INFO "delay_cnt = %d\n", g_pNand_Phy_Info->delay_cnt);

+	printk(KERN_INFO "custom_nd = %d\n", g_pNand_Phy_Info->custom_nd);

+	printk(KERN_INFO "flag = 0x%x\n", g_pNand_Phy_Info->flag);

+	printk(KERN_INFO "cmd_len = 0x%x\n", g_pNand_Phy_Info->cmd_len);

+	printk(KERN_INFO "data_len = 0x%x\n", g_pNand_Phy_Info->data_len);

+	printk(KERN_INFO "---------------------------------------------------------------------------------\n");

+	#endif

+	

+	return AK_TRUE;

+}

+

+T_U32 ak_mount_partitions(void)

+{

+	int i = 0;

+	T_U8 *fs_info = NULL;

+	int part_cnt = 0;

+	struct partitions *parts = NULL;

+	struct mtd_partition *pmtd_part = NULL;

+	

+	#if 1

+	if(g_pinit_info!=NULL && g_pCallback!=NULL)

+	{

+		fs_info = kmalloc(g_pNF->PageSize, GFP_KERNEL);

+		FHA_get_fs_part(fs_info, g_pNF->PageSize);

+		part_cnt = *((int *)fs_info);  //calculate how many partitions

+		#if ZZ_DEBUG

+		printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 573 part_cnt=%d\n", part_cnt);

+		#endif

+		if(part_cnt == 0)

+		{

+			printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 577 part_cnt==0 error!!!\n");

+			return AK_FALSE;

+		}

+		

+		pmtd_part = kmalloc(sizeof(struct mtd_partition) * part_cnt, GFP_KERNEL);

+		if(pmtd_part == NULL)

+		{

+			printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 584 pmtd_part==NULL error!!!\n");

+			return AK_FALSE;

+		}

+		

+		#if ZZ_DEBUG

+		printk(KERN_INFO "-----------------zz wrap_nand.c ak_mount_partitions() 589 mtd part info start---------------\n");

+		#endif

+

+		parts = (struct partitions *)(&fs_info[4]);

+		

+		for(i=0; i<part_cnt; i++)

+		{	

+			pmtd_part[i].name= kmalloc(MTD_PART_NAME_LEN, GFP_KERNEL);

+			memcpy(pmtd_part[i].name, parts[i].name, MTD_PART_NAME_LEN);

+			pmtd_part[i].size = parts[i].size;

+			pmtd_part[i].offset = parts[i].offset;

+			pmtd_part[i].mask_flags = parts[i].mask_flags;

+			#if 1 //ZZ_DEBUG

+			printk(KERN_INFO "pmtd_part[%d]:\nname = %s\nsize = 0x%llx\noffset = 0x%llx\nmask_flags = 0x%x\n\n", 

+					i, 

+					pmtd_part[i].name, 

+					pmtd_part[i].size,

+					pmtd_part[i].offset,

+					pmtd_part[i].mask_flags

+				  );

+			#endif

+		}

+		

+		#if ZZ_DEBUG

+		printk(KERN_INFO "-----------------zz wrap_nand.c ak_mount_partitions() 613 mtd part info end----------------\n");

+		#endif

+		add_mtd_partitions(g_master, (const struct mtd_partition *)pmtd_part, part_cnt);

+		

+		kfree(pmtd_part);

+		kfree(fs_info);

+	}

+	else

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 622 init fha lib failed!!!\n");

+	}

+

+	return AK_TRUE;

+	#endif

+	

+	#if 0

+	part_cnt = 3;

+	pmtd_part = kmalloc(sizeof(struct mtd_partition) * part_cnt, GFP_KERNEL);

+	pmtd_part[0].name   = "A";

+	pmtd_part[0].size   = 0x00b80000;

+	pmtd_part[0].offset = 0x02000000;

+	pmtd_part[0].mask_flags = 0x0;

+

+	pmtd_part[1].name   = "B";

+	pmtd_part[1].size   = 0x02380000;

+	pmtd_part[1].offset = 0x02b80000;

+	pmtd_part[1].mask_flags = 0x0;

+

+	pmtd_part[2].name   = "C";

+	pmtd_part[2].size   = 0x02600000;

+	pmtd_part[2].offset = 0x04f00000;

+	pmtd_part[2].mask_flags = 0x0;

+	add_mtd_partitions(g_master, (const struct mtd_partition *)pmtd_part, part_cnt);

+	kfree(pmtd_part);

+	return AK_TRUE;

+	#endif

+}

+

+int ak_nand_block_isbad(struct mtd_info *mtd, loff_t offs)

+{

+	T_U32 blk_no = 0;

+	T_U32 ret = 0;

+

+	if (offs > mtd->size)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 658 offs=0x%llx Error!!!\n", offs);

+		return -EINVAL;

+	}

+	if(g_pinit_info==NULL || g_pCallback==NULL || g_pNF==NULL)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 663 point is NULL Error!!!\n");

+		return 0;          //default good block

+	}

+	if(g_pNF->PageSize == 0 || g_pNF->PagesPerBlock == 0)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 668 divisor=0  Error!!!\n");

+		return 0;          //default good block

+	}

+	blk_no = div_u64(offs, (g_pNF->PageSize * g_pNF->PagesPerBlock));

+	ret = FHA_check_bad_block(blk_no);     //divisor is 0 error!!!!!!

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 674 blk_no=%d return %d\n", 

+	       blk_no, ret);

+	#endif

+	

+	return ret;

+}

+

+int ak_nand_block_markbad(struct mtd_info *mtd, loff_t offs)

+{

+	T_U32 blk_no = 0;

+	T_U32 ret = 0;

+

+	if (offs > mtd->size)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 688 offs=0x%llx Error!!!\n", offs);

+		return -EINVAL;

+	}

+	if(g_pinit_info==NULL || g_pCallback==NULL || g_pNF==NULL)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 693 point is NULL Error!!!\n");

+		return 0;  //default mark successed

+	}

+	if(g_pNF->PageSize == 0 || g_pNF->PagesPerBlock == 0)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 698 divisor=0  Error!!!\n");

+		return 0;          //default good block

+	}	

+	blk_no = div_u64(offs, (g_pNF->PageSize * g_pNF->PagesPerBlock));

+	ret = FHA_set_bad_block(blk_no);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 704 blk_no=%d FHA_set_bad_block() return %d\n", 

+	       blk_no, ret);

+	#endif

+	if(ret == FHA_SUCCESS)

+	{

+		return 0;  //mark successed

+	}

+	else

+	{

+		return 1;  //mark failed

+	}

+}

+

+T_U32 try_nand_para(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_Nandflash_Add *p_add)

+{

+	T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	T_U8 pw[PASSWORD_LENGTH +1];

+	int j= 0;

+	

+	data_ctrl.buf = data;

+    data_ctrl.buf_len = data_len;

+    data_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    data_ctrl.ecc_type = ECC_8BIT_P512B;

+

+    spare_ctrl.buf = oob;

+    spare_ctrl.buf_len = oob_len;

+    spare_ctrl.ecc_section_len = NAND_DATA_SIZE + oob_len;

+    spare_ctrl.ecc_type = ECC_8BIT_P512B;

+

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c try_nand_para() 736 data_len=%d oob_len=%d\n",

+	       data_len, oob_len);

+	#endif 

+	

+	nand_readpage_ecc(chip_num, page_num, 0, p_add, &data_ctrl, &spare_ctrl);

+

+	memcpy(pw, data+PASSWORD_ADDR_OFFSET, PASSWORD_LENGTH);

+	pw[PASSWORD_LENGTH] = '\0';

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c try_nand_para() 745 password string=%s", pw);

+	#endif 

+	if(!strcmp(pw, PASSWORD_STR))

+	{

+		#if ZZ_DEBUG

+		printk(KERN_INFO "zz wrap_nand.c try_nand_para() 750 password match succussed!\n");

+		for(j=50;j<500;j++)

+		{

+			if(j%10==0)

+			{

+				printk("\n");

+			}

+			printk(KERN_INFO "0x%02x\t", data[j]);

+		}

+		#endif 

+		return  AK_TRUE;

+	}

+	return AK_FALSE;

+}

+

+#if 0

+unsigned char buf_r_data[4096];

+unsigned char buf_w_data[4096];

+

+void zz_test_nand(void)

+{

+    unsigned char oob_buf[32];

+    int i = 0;

+    int j = 0;

+    int retval = 0;

+    T_U32 chip = 0;

+    int pagenum = 0;

+	

+	T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    for(i=10; i<15; i++)

+    {

+        retval = nand_eraseblock(chip, i*128, g_pNF);

+        memset(buf_w_data, 0x9b, 4096);

+        memset(oob_buf, i, 32);

+        pagenum = i*128+10;

+		

+		Nand_Config_Data(&data_ctrl, buf_w_data, g_sNF.PageSize, g_sNF.EccType);

+		Nand_Config_Spare(&spare_ctrl, oob_buf, YAFFS_OOB_SIZE, g_sNF.EccType); 

+		

+		retval = nand_writepage_ecc(chip, pagenum, 0, &g_sNF, &data_ctrl, &spare_ctrl);

+

+        memset(buf_r_data,0xff, 4096);

+        memset(oob_buf, 0xff, 32);

+

+		Nand_Config_Data(&data_ctrl, buf_r_data, g_sNF.PageSize, g_sNF.EccType);

+		Nand_Config_Spare(&spare_ctrl, oob_buf, YAFFS_OOB_SIZE, g_sNF.EccType); 

+

+        retval = nand_readpage_ecc(chip, pagenum, 0, &g_sNF, &data_ctrl, &spare_ctrl);

+        //retval = nand_readbytes(chip, pagenum, 0, &g_sNF, buf_r_data, 2048);

+		

+		for(j=0; j<50; j++)

+		{

+			if(j%10 == 0)

+			{

+				printk(KERN_INFO "\n");

+			}

+			printk(KERN_INFO "0x%x ", buf_r_data[j]);

+		}

+		printk(KERN_INFO "\n");

+		#if 1

+		for(j=0; j<10; j++)

+		{

+			printk(KERN_INFO "oob_buf[%d] = %d ", j,oob_buf[j]);

+		}

+		printk(KERN_INFO "\n");

+		#endif

+    }

+}

+

+void erase_all_flash(void)

+{

+	int i = 0;

+	if((g_pNF == NULL) || (g_pNand_Phy_Info == NULL))

+	{

+		printk(KERN_INFO "zz wrap_nand.c erase_all_flash() 638 g_pNF == NULL || g_pNand_Phy_Info == NULL error!!!\n");

+		return;

+	}

+	for(i=0; i<(g_pNand_Phy_Info->blk_num); i++)

+	{

+		nand_eraseblock(0, i*128, g_pNF);

+	}

+}

+

+#endif

+

diff --git a/drivers/mtd/nand/ak88-nand/wrap_nand.h b/drivers/mtd/nand/ak88-nand/wrap_nand.h
new file mode 100644
index 00000000000..79617b04f28
--- /dev/null
+++ b/drivers/mtd/nand/ak88-nand/wrap_nand.h
@@ -0,0 +1,103 @@
+/**

+ * @filename wrap_nand.h

+ * @brief AK880x nandflash driver

+ *

+ * This file wrap the nand flash driver in nand_control.c file.

+ * Copyright (C) 2010 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author zhangzheng

+ * @modify 

+ * @date 2010-10-10

+ * @version 1.0

+ * @ref

+ */

+

+

+#ifndef _AK_NAND_WRAP_H_

+#define _AK_NAND_WRAP_H_

+

+#include <linux/types.h>

+#include <linux/mtd/mtd.h>

+#include <linux/mtd/nand.h>

+#include <mach-anyka/anyka_types.h>

+#include <mach-anyka/nand_list.h>

+#include <mach-anyka/fha.h>

+#include <mach-anyka/fha_asa.h>

+#include "arch_nand.h"

+

+int init_fha_lib(void);

+#if 0

+void release_fha_lib(void);

+#endif

+void Nand_Config_Data(T_PNAND_ECC_STRU data_ctrl, T_U8* data, T_U32 data_len, ECC_TYPE ecc_type);

+

+void Nand_Config_Spare(T_PNAND_ECC_STRU spare_ctrl, T_U8* spare, T_U32 spare_len, ECC_TYPE ecc_type);

+

+void ak_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len);

+

+

+void ak_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);

+

+

+void ak_nand_select_chip(struct mtd_info *mtd, int chip);

+

+

+u_char ak_nand_read_byte(struct mtd_info *mtd);

+

+

+int ak_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                   uint8_t *buf, int page);

+

+

+void ak_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                     const uint8_t *buf);

+

+

+int ak_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+			                    uint8_t *buf, int pag);

+

+

+void ak_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+				                  const uint8_t *buf);

+

+

+int ak_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page, int sndcmd);

+

+

+int ak_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page);

+

+T_U32 nand_erase_callback(T_U32 chip_num, T_U32 startpage);

+

+T_U32 nand_read_callback(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType);

+

+T_U32 nand_write_callback(T_U32 chip_num, T_U32 page_num, const T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType);

+

+T_U32 nand_read_bytes_callback(T_U32 nChip, T_U32 rowAddr, T_U32 columnAddr, T_U8 *pData, T_U32 nDataLen);

+

+void *ram_alloc(T_U32 size);

+

+void *ram_free(void *point);

+

+T_S32 print_callback(T_pCSTR s, ...);

+

+T_U32 init_globe_para(void);

+

+T_U32 ak_mount_partitions(void);

+

+int ak_nand_block_isbad(struct mtd_info *mtd, loff_t offs);

+

+int ak_nand_block_markbad(struct mtd_info *mtd, loff_t offs);

+

+T_U32 try_nand_para(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_Nandflash_Add *p_add);

+

+

+#if 0

+void zz_test_nand(void);

+void erase_all_flash(void);

+#endif

+

+#endif

diff --git a/drivers/mtd/nand/ak98-nand/Makefile b/drivers/mtd/nand/ak98-nand/Makefile
new file mode 100644
index 00000000000..7b49c114107
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/Makefile
@@ -0,0 +1,5 @@
+obj-$(CONFIG_MTD_NAND_AK98) += ak98-nandflash.o
+	ak98-nandflash-objs := ak98_nand.o wrap_nand.o nand_control.o communicate.o  
+
+obj-$(CONFIG_MTD_NAND_TEST) += nand_char.o
+obj-$(CONFIG_MTD_DOWNLOAD_MODE) += nand_char.o
diff --git a/drivers/mtd/nand/ak98-nand/ak98_nand.c b/drivers/mtd/nand/ak98-nand/ak98_nand.c
new file mode 100755
index 00000000000..2f57598a659
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/ak98_nand.c
@@ -0,0 +1,677 @@
+/* linux/drivers/mtd/nand/ak98.c
+ *
+ * Anyka ak98 NAND driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifdef CONFIG_MTD_NAND_ak98_DEBUG
+#define DEBUG
+#endif
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/notifier.h>
+#include <linux/cpufreq.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/dma-mapping.h>
+#include <mach-anyka/anyka_types.h>
+
+#include <asm/io.h>
+#include <mach/nand.h>
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+#include "arch_nand.h"
+#include "wrap_nand.h"
+#include "anyka_cpu.h"
+
+#define ZZ_DEBUG                 0
+
+//receive mtd command
+static unsigned int m_nCommand = 0;
+int page_shift;
+static unsigned long nandid = 0xFFFFFFFF;
+
+/* struct semaphore m_sem_lock; */
+DECLARE_MUTEX(nand_lock);
+EXPORT_SYMBOL(nand_lock);
+
+unsigned char m_status = 0;
+dma_addr_t dmahandle;
+void *bufaddr = NULL;
+extern T_NAND_PHY_INFO *g_pNand_Phy_Info;
+
+
+/* controller and mtd information */
+
+struct ak98_nand_info {
+	/* mtd info */
+	struct nand_hw_control controller;
+	struct ak98_nand_mtd *mtds;
+	struct ak98_platform_nand *platform;
+
+	/* device info */
+	struct device *device;
+#ifdef CONFIG_CPU_FREQ
+	struct notifier_block freq_transition;
+#endif
+	unsigned int cmd_len;
+	unsigned int data_len;
+	int mtd_count;
+};
+
+struct ak98_nand_mtd {
+	struct mtd_info mtd;
+	struct nand_chip chip;
+	struct ak98_nand_set *set;
+	struct ak98_nand_info *info;
+	int scan_res;
+};
+
+extern T_PNandflash_Add g_pNF;
+struct mtd_info *g_master = NULL; //zhangzheng add for nand char dev mount mtd partitions
+
+int print_32(unsigned char *buf)
+{	
+	int i,j;
+	unsigned char *p0;
+	p0=buf;
+	printk("print_32,buf=0x%x: ",(int)p0);
+ 
+	for(i=0;i<1;i++){
+		for(j=0;j<32;j++){
+			printk("%02x,",*(p0+j+i*32));
+		}
+	printk("\n");
+	}
+
+return i*j;	
+}
+
+static struct ak98_nand_info *to_nand_info(struct platform_device *dev)
+{
+	return platform_get_drvdata(dev);
+}
+
+static struct ak98_platform_nand *to_nand_plat(struct platform_device *dev)
+{
+	return dev->dev.platform_data;
+}
+
+/* NFC & HW port setup
+ *
+ * setting NFC, AC
+ *
+ * NFC share pin set
+ *	Enable nandflash function pin		: 0x08000074 [4:3] = 0x01
+ *	Share pin use nandflash :
+ *	CE0,RE,WE,CLE,ALE,data0 -- data7	: 0x08000078 [16]=1 [17]=1 [18]=1
+ *	R/B					: 0x08000078 [22]=1
+ *	pull up and pull down			: use the defalut value
+ */
+void ak98_nand_inithw(void)
+{
+	/* open the nand flash clk */
+    printk(KERN_INFO "%s: line %d\n",__func__,__LINE__);
+	*(volatile unsigned int *)(AK98_VA_SYSCTRL + 0x0c) &= (~(1 << 14));
+
+	nand_HWinit();
+   
+	/* FIXME: use configurable timing parameter */
+	//*(volatile unsigned int *)(AK98_VA_NFCTRL + 0x15C) = 0xF5AD1;
+}
+
+static unsigned int index = 0;
+static u_char ak98_nand_read_byte(struct mtd_info *mtd)
+{
+	u_char ret_byte = 0;
+    
+    if (m_nCommand == NAND_CMD_STATUS) 
+    {
+		index = 0;
+		return m_status;
+	}
+
+	if (m_nCommand == NAND_CMD_READID) 
+    {
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak98.c ak98_nand_read_byte() 178 index=%d nandid=0x%lx\n", 
+               index, nandid);
+		#endif
+		ret_byte = ((nandid >> index) & 0xFF);
+		if (index == 24)
+			index = 0;
+		else
+			index += 8;
+	}
+
+	if (m_nCommand == NAND_CMD_READOOB)
+    {
+		//printk("%s: No implement yet for READOOB\n", __FUNCTION__);
+		//printk("%s: please create BBT first\n", __FUNCTION__);
+ 	}
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_read_byte() 194 ret_byte=%d\n",
+           ret_byte);
+	#endif
+	return ret_byte;
+}
+
+static void ak98_nand_command(struct mtd_info *mtd,
+				unsigned command, int column, int page_addr)
+{
+    int block_index = 0;
+	m_nCommand = command;
+	page_shift = page_addr;
+
+	//printk(KERN_INFO "zz ak98.c ak98_nand_command() line 304 page=%d\n",page_addr);
+	switch (command) {
+	case NAND_CMD_RESET:
+		//printk(KERN_INFO "zz ak98.c ak98_nand_command() line 307 CMD:NAND_CMD_RESET\n");
+		nand_reset(0);
+		break;
+
+	case NAND_CMD_STATUS:
+		//printk(KERN_INFO "zz ak98.c ak98_nand_command() line 312 CMD:NAND_CMD_STATUS\n");
+		m_status = nand_get_status(0);
+		break;
+
+	case NAND_CMD_READID:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 317 CMD:NAND_CMD_READID\n");
+		index = 0;
+		nandid = nand_read_chipID(0);	/* only support 1st flash */
+ 		break;
+	case NAND_CMD_ERASE1:
+		if(g_pNF == NULL)
+		{
+			printk(KERN_INFO "zz ak98.c ak98_nand_command() 227 g_pNF==NULL error!!!\n");
+			break;
+		}
+		block_index = page_addr/128;
+        nand_eraseblock(0, block_index*128, g_pNF);
+		break;
+
+	case NAND_CMD_ERASE2:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 327 CMD:NAND_CMD_ERASE2\n");
+		break;
+        
+	case NAND_CMD_READOOB:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 331 CMD:NAND_CMD_READOOB\n");
+		break;
+        
+	case NAND_CMD_READ0:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 335 CMD:NAND_CMD_READ0\n");
+		break;
+        
+	case NAND_CMD_PAGEPROG:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 339 CMD:NAND_CMD_PAGEPROG\n");
+		break;
+        
+	case NAND_CMD_SEQIN:
+        //printk(KERN_INFO "zz ak98.c ak98_nand_command() line 343 CMD:NAND_CMD_SEQIN\n");
+		break;
+
+	default:
+		//printk(KERN_INFO "zz ak98.c ak98_nand_command() line 347 Unkown CMD:0x%x\n", command);
+		return;
+	}
+
+}
+#if 0
+#if CONFIG_MTD_PARTITIONS
+static int ak98_nand_add_partition(struct ak98_nand_info *info,
+				     struct ak98_nand_mtd *mtd,
+				     struct ak98_nand_set *set)
+{
+	if (set == NULL)
+    {   
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak98.c ak98_nand_add_partition() 269\n");
+		#endif
+		return add_mtd_device(&mtd->mtd);
+    }
+	if (set->nr_partitions > 0 && set->partitions != NULL) 
+    {
+    	#if ZZ_DEBUG
+        printk(KERN_INFO "zz ak98.c ak98_nand_add_partition() 276\n");
+		#endif
+		return add_mtd_partitions(&mtd->mtd, set->partitions,
+					  set->nr_partitions);
+	}
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_add_partition() 282\n");
+	#endif
+	return add_mtd_device(&mtd->mtd);
+}
+#else
+static int ak98_nand_add_partition(struct ak98_nand_info *info,
+				     struct ak98_nand_mtd *mtd,
+				     struct ak98_nand_set *set)
+{
+	return add_mtd_device(&mtd->mtd);
+}
+#endif
+#endif
+static uint8_t ak98_bbt_pattern[] = { 'b', 'b', 't' };
+
+static struct nand_bbt_descr ak98_nand_bbt_descr = {
+	//.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	//    | NAND_BBT_1BIT,
+	.options = NAND_BBT_ABSPAGE|NAND_BBT_VERSION | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_1BIT,
+	.pages[0] = 127,
+	.offs = 13,
+	.len = 3,
+	.maxblocks = 4,
+	//.reserved_block_code = 1,
+	.pattern = ak98_bbt_pattern
+};
+
+/* ak98_nand_init_chip
+ *
+ * init a single instance of an chip
+ */
+
+static void ak98_nand_init_chip(struct ak98_nand_info *info,
+				  struct ak98_nand_mtd *nmtd,
+				  struct ak98_nand_set *set)
+{
+	struct nand_chip *chip = &nmtd->chip;
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_init_chip() 321\n");
+	#endif
+	chip->write_buf = ak_nand_write_buf;     //ak98_nand_write_buf;
+	chip->read_buf =  ak_nand_read_buf;      //ak98_nand_read_buf;   
+	chip->select_chip = ak_nand_select_chip;//ak_nand_select_chip; 
+	chip->chip_delay = 50;
+	chip->priv = nmtd;
+	chip->options = 0;
+	chip->options = NAND_NO_PADDING | NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;	// | NAND_SKIP_BBTSCAN;
+	chip->controller = &info->controller;
+	chip->dev_ready = NULL;
+	chip->cmdfunc = ak98_nand_command;
+	chip->read_byte = ak98_nand_read_byte;
+	chip->bbt_td = &ak98_nand_bbt_descr;
+
+    chip->ecc.mode = NAND_ECC_HW;      //NAND_ECC_HW;
+	chip->ecc.read_page = ak_nand_read_page_hwecc; 
+	chip->ecc.write_page = ak_nand_write_page_hwecc; 
+	chip->ecc.read_page_raw = ak_nand_read_page_raw;
+	chip->ecc.write_page_raw = ak_nand_write_page_raw;
+	chip->ecc.read_oob = ak_nand_read_oob;  
+	chip->ecc.write_oob = ak_nand_write_oob;
+	chip->init_size = ak_nand_init_size;
+	chip->scan_bbt = ak_nand_scan_bbt;
+	chip->block_bad = ak_nand_block_isbad;
+	chip->block_markbad = ak_nand_block_markbad;
+    
+	nmtd->info = info;
+	nmtd->mtd.priv = chip;
+	nmtd->mtd.owner = THIS_MODULE;
+	nmtd->set = set;
+	#if ZZ_DEBUG
+	printk("ak98_nand_init_chip/cmd_timing=0x%x,data_timing=0x%x\n",nmtd->set->cmd_len,nmtd->set->data_len);
+	#endif
+	#if defined(L2_DMA_MODE)
+		printk("NAND driver:L2_DMA_MODE\n");
+    #else
+		printk("NAND driver:L2_CPU_MODE\n");
+	#endif
+
+}
+
+#ifdef CONFIG_CPU_FREQ
+static int ak98_nand_cpufreq_transition(struct notifier_block *nb, 
+						unsigned long val, void *data)
+{
+	struct cpufreq_freqs *freqs = (struct cpufreq_freqs *)data;
+	struct ak98_nand_info *info = container_of(nb, struct ak98_nand_info, freq_transition);	
+	unsigned int old_clk = freqs->old_cpufreq.asic_clk;
+	unsigned int new_clk = freqs->new_cpufreq.asic_clk;
+	unsigned long flags;
+
+	if ((val == CPUFREQ_PRECHANGE && new_clk > old_clk) ||
+		(val == CPUFREQ_POSTCHANGE && new_clk < old_clk)) {
+		down(&nand_lock);
+		local_irq_save(flags);
+
+		nand_calctiming(info->data_len);
+		nand_changetiming(new_clk);
+
+		local_irq_restore(flags);
+		up(&nand_lock);
+	}
+	return NOTIFY_DONE;
+}
+
+static int ak98_nand_cpufreq_register(struct ak98_nand_info *info)
+{
+	info->freq_transition.notifier_call = ak98_nand_cpufreq_transition;
+
+	return cpufreq_register_notifier(&info->freq_transition, 
+					CPUFREQ_TRANSITION_NOTIFIER); 
+}
+
+static void ak98_nand_cpufreq_unregister(struct ak98_nand_info *info)
+{
+	cpufreq_unregister_notifier(&info->freq_transition,
+					CPUFREQ_TRANSITION_NOTIFIER);
+}
+#else 
+static int ak98_nand_cpufreq_register(struct ak98_nand_info *info)
+{
+	return 0;
+}
+
+static void ak98_nand_cpufreq_unregister(struct ak98_nand_info *info)
+{
+}
+#endif
+
+static void ak98_nand_clock_set(struct ak98_nand_info *info)
+{
+	info->cmd_len = g_pNand_Phy_Info->cmd_len;
+	info->data_len = g_pNand_Phy_Info->data_len;
+	nand_calctiming(info->data_len);
+	nand_changetiming(ak98_get_asic_clk());
+}
+
+
+/* device management functions */
+
+static int ak98_nand_remove(struct platform_device *pdev)
+{
+	struct ak98_nand_info *info = to_nand_info(pdev);
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz ak98.c ak98_nand_remove() line 132\n");
+	#endif
+	platform_set_drvdata(pdev, NULL);
+
+	if (info == NULL)
+		return 0;
+
+	/* first thing we need to do is release all our mtds
+	 * and their partitions, then go through freeing the
+	 * resources used
+	 */
+
+	ak98_nand_cpufreq_unregister(info);
+
+	if (info->mtds != NULL) {
+		struct ak98_nand_mtd *ptr = info->mtds;
+		int mtdno;
+
+		for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
+		    pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
+			nand_release(&ptr->mtd);
+		}
+
+		kfree(info->mtds);
+	}
+
+	/* close flash contoller clock */
+	*(volatile unsigned int *)(AK98_VA_SYSCTRL + 0x0c) |= (1 << 14);
+
+	kfree(info);
+	free_globe_para();
+	
+#ifdef CONFIG_MTD_NAND_TEST 
+	nand_balance_test_exit();
+#endif
+
+	return 0;
+}
+
+static int __init ak98_nand_probe(struct platform_device *pdev)
+{
+	struct ak98_platform_nand *plat = to_nand_plat(pdev);
+	struct ak98_nand_info *info;
+	struct ak98_nand_mtd *nmtd;
+	struct ak98_nand_set *sets;
+	int err = 0;
+	int size;
+	int nr_sets;
+	int setno;
+	
+	printk(KERN_INFO "zz ak98.c ak98_nand_probe() 371\n");
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (info == NULL) {
+		printk(KERN_INFO "zz ak98.c ak98_nand_probe() 381 no memory for flash info\n");
+		err = -ENOMEM;
+		goto exit_error1;
+	}
+	
+	platform_set_drvdata(pdev, info);
+	spin_lock_init(&info->controller.lock);
+	init_waitqueue_head(&info->controller.wq);
+
+	info->device = &pdev->dev;
+	info->platform = plat;
+	sets = (plat != NULL) ? plat->sets : NULL;
+	nr_sets = (plat != NULL) ? plat->nr_sets : 1;
+
+	info->mtd_count = nr_sets;
+
+	/* allocate our information */
+
+	size = nr_sets * sizeof(*info->mtds);
+	info->mtds = kzalloc(size, GFP_KERNEL);
+	if (info->mtds == NULL) {
+		printk("failed to allocate mtd storage\n");
+		err = -ENOMEM;
+		goto exit_error2;
+	}
+
+	ak98_nand_inithw();	
+
+	#ifndef CONFIG_MTD_DOWNLOAD_MODE
+	if(FHA_FAIL == init_fha_lib())
+	{
+		printk(KERN_INFO "zz ak98.c ak98_nand_probe() 375 init fha lib error return!!!\n");
+		return -ENOMEM;
+	}	
+	ak98_nand_clock_set(info);
+	#endif
+
+	#ifdef CONFIG_MTD_NAND_TEST   
+    nand_balance_test_init();
+	#endif	
+
+	/* initialise all possible chips */
+	nmtd = info->mtds;
+    g_master = &nmtd->mtd;//zhangzheng add for nand char dev mount mtd partitions
+    #if ZZ_DEBUG
+	printk(KERN_INFO "zz ak98.c ak98_nand_probe() 413 nr_sets=%d\n", nr_sets);
+	#endif
+	for (setno = 0; setno < nr_sets; setno++, nmtd++)   //nr_sets==1
+	{
+		pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd,
+			 info);
+
+		ak98_nand_init_chip(info, nmtd, sets);
+
+        #ifndef CONFIG_MTD_DOWNLOAD_MODE
+		nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);            
+		ak_mount_partitions();
+        #endif
+        
+		if (sets != NULL)
+			sets++;
+	}
+
+    #if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_probe() 437 Initialize Successed!\n");
+	#endif
+
+	err = ak98_nand_cpufreq_register(info);
+	if (err) {
+		printk(KERN_INFO "ak98 nand cpu freq register fail\n");
+		err = -EINVAL;
+		goto exit_error3;
+	}
+		
+	#if 0
+    zz_test_nand();
+   	erase_all_flash();
+	#endif
+	
+	
+	return 0;
+
+
+exit_error3:
+	kfree(info->mtds);
+exit_error2:
+    kfree(info);
+exit_error1:
+    printk(KERN_INFO "zz ak98.c ak98_nand_probe() 444 Error Exit!\n");
+    ak98_nand_remove(pdev);
+	return err;
+}
+
+/* PM Support */
+#ifdef CONFIG_PM
+
+static int ak98_nand_suspend(struct platform_device *dev, pm_message_t pm)
+{
+    //struct ak98_nand_info *info = platform_get_drvdata(dev);
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_suspend() 456\n");    
+	#endif	
+    *(volatile unsigned int *)(AK98_VA_SYSCTRL + 0x0c) |= (1 << 14);
+	return 0;
+}
+
+static int ak98_nand_resume(struct platform_device *dev)
+{
+	struct ak98_nand_info *info = platform_get_drvdata(dev);
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_resume() 465\n");
+	#endif
+	if (info) 
+	{
+		ak98_nand_inithw();
+	}
+	return 0;
+}
+
+#else
+#define ak98_nand_suspend NULL
+#define ak98_nand_resume NULL
+#endif
+
+/* driver device registration */
+
+static struct platform_driver ak98_nand_driver = {
+	.probe = ak98_nand_probe,
+	.remove = ak98_nand_remove,
+	.suspend = ak98_nand_suspend,
+	.resume = ak98_nand_resume,
+	.driver = {
+		   .name = "ak98-nand",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init ak98_nand_init(void)
+{
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz ak98.c ak98_nand_init() line 495\n");
+	#endif
+
+	bufaddr = dma_alloc_coherent(NULL, NAND_DATA_SIZE_P1KB, &dmahandle, GFP_KERNEL);
+	if (bufaddr == NULL) {
+		printk(KERN_INFO "dma alloc coherent fail!\n");
+		WARN_ON(1);
+	}
+	
+	return platform_driver_register(&ak98_nand_driver);
+}
+
+static void __exit ak98_nand_exit(void)
+{
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz ak98.c ak98_nand_exit() 506\n");
+	#endif
+	if (bufaddr != NULL)
+	{
+	    dma_free_coherent(NULL, NAND_DATA_SIZE_P1KB, bufaddr, dmahandle);
+	}
+	
+	platform_driver_unregister(&ak98_nand_driver);
+}
+//--------------------------------print info---------------------------------
+void print_struct_mtd_info(struct mtd_info *mtd)
+{
+    printk(KERN_INFO "---------------------zz print struct mtd_info start-------------------------------\n");
+    printk(KERN_INFO "erasesize=%d\nerasesize_mask=%d\nwritesize=%d\noobsize=%d\n",           
+           mtd->erasesize,
+           mtd->erasesize_mask,
+           mtd->writesize, 
+           mtd->oobsize);
+    printk(KERN_INFO "oobavail=%d\nerasesize_shift=%d\nwritesize_shift=%d\n",
+           mtd->oobavail,
+           mtd->erasesize_shift,
+           mtd->writesize_shift);
+    printk(KERN_INFO "erasesize_mask=%d\nwritesize_mask=%d\n",
+           mtd->erasesize_mask,
+           mtd->writesize_mask);
+    printk(KERN_INFO "---------------------zz print struct mtd_info end---------------------------------\n");
+}
+
+void print_struct_nand_chip(struct nand_chip *chip)
+{
+    printk(KERN_INFO "---------------------zz print struct nand_chip start-------------------------------\n");
+    printk(KERN_INFO "chip_delay=%d\noptions=%d\npage_shift=%d\nphys_erase_shift=%d\n",           
+           chip->chip_delay,
+           chip->options,
+           chip->page_shift,
+           chip->phys_erase_shift);
+    printk(KERN_INFO "bbt_erase_shift=%d\nchip_shift=%d\nnumchips=%d\npagemask=%d\n",           
+           chip->bbt_erase_shift,
+           chip->chip_shift,
+           chip->numchips,
+           chip->pagemask);
+    printk(KERN_INFO "pagebuf=%d\nsubpagesize=%d\ncellinfo=%d\nbadblockpos=%d\nstate=%d\n",           
+           chip->pagebuf,
+           chip->subpagesize,
+           chip->cellinfo,
+           chip->badblockpos,
+           chip->state);
+    printk(KERN_INFO "--------------------zz print struct nand_chip end---------------------------------\n");
+}
+
+//-----------------------------------zhangzheng add end-------------------------------------------------
+module_init(ak98_nand_init);
+module_exit(ak98_nand_exit);
+
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("ak98 MTD NAND driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/mtd/nand/ak98-nand/anyka_cpu.h b/drivers/mtd/nand/ak98-nand/anyka_cpu.h
new file mode 100644
index 00000000000..28952ba5f15
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/anyka_cpu.h
@@ -0,0 +1,642 @@
+/** @file

+ * @brief Define the register of ANYKA CPU

+ *

+ * Define the register address and bit map for system.

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author xuchang

+ * @date 2008-01-05

+ * @version 1.0

+ * @note

+ * ¸ÃÎļþ¶¨ÒåËùÓÐÇý¶¯Ä£¿éµÄ¼Ä´æÆ÷£¬²»µÃÔÚÆäËûµØ·½×ö¼Ä´æÆ÷¶¨Òå!!

+ * ¼Ä´æÆ÷µÄ붨ÒåÔ­ÔòÉÏ·ÅÔÚ¸÷¸öÇý¶¯Ä£¿éµÄÍ·ÎļþÖж¨Ò壬Èç¹û¶ÔÓ¦µÄÇý¶¯Ä£¿é̫СûÓÐÍ·Îļþ£¬

+ * Ôò¿É·ÅÔÚ´Ë´¦¶¨Òå

+ */

+#ifndef _ANYKA_CPU_H_

+#define _ANYKA_CPU_H_

+#include <mach-anyka/anyka_types.h>

+

+/** @defgroup ANYKA_CPU  

+ *      @ingroup Drv_Lib

+ */

+/*@{*/

+

+

+/** @{@name Base Address Define

+ *      The base address of system memory space is define here. 

+ *      Include memory assignment and module base address define.

+ */

+ /**Memory assignment*/

+#define CHIP_CONF_BASE_ADDR                             0x08000000      // chip configurations

+#define USB_BASE_ADDR                                   0x70000000      // USB

+#define L2_BUF_MEM_BASE_ADDR                            0x48000000      //L2 Buffer start address

+/** @} */

+

+

+/** @{@name CPU working mode

+ */

+#define ANYKA_CPU_Mode_USR                              0x10

+#define ANYKA_CPU_Mode_FIQ                              0x11

+#define ANYKA_CPU_Mode_IRQ                              0x12

+#define ANYKA_CPU_Mode_SVC                              0x13

+#define ANYKA_CPU_Mode_ABT                              0x17

+#define ANYKA_CPU_Mode_UNDEF                            0x1B

+#define ANYKA_CPU_Mode_SYS                              0x1F            

+#define ANYKA_CPU_I_Bit                                 0x80

+#define ANYKA_CPU_F_Bit                                 0x40

+/** @} */

+

+/** @{@name System Control Register

+ *      Define system control register here, include CLOCK/INT/RESET

+ */

+#define CLOCK_CTRL_REG                                  (CHIP_CONF_BASE_ADDR + 0x0000000C)      // module clock control(switch)

+#define CLOCK_CTRL2_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000008)      // module clock control(switch)

+#define RESET_CTRL_REG                                  (CHIP_CONF_BASE_ADDR + 0x0000000C)      // module software reset control register

+#define STANDBY_REG                                     (CHIP_CONF_BASE_ADDR + 0x00000004)      // module standby register

+#define IRQINT_MASK_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000034)      // module IRQ interrupt mask register, 1: mask; 0:unmask(default);

+#define FRQINT_MASK_REG                                 (CHIP_CONF_BASE_ADDR + 0x00000038)      // module FRQ interrupt mask register, 1: mask; 0:unmask(default);

+#define INT_STATUS_REG                                  (CHIP_CONF_BASE_ADDR + 0x000000CC)      // module interrupt status register

+#define INT_SYS_MODULE_REG                              (CHIP_CONF_BASE_ADDR + 0x0000004C)      // system module interrupt control register

+#define CLOCK_DIV_REG                                   (CHIP_CONF_BASE_ADDR + 0x00000004)      // clock divider register 1

+#define CLOCK2X_CTRL_REG                                (CHIP_CONF_BASE_ADDR + 0x00000004)      // clock2x control register,1: 2*ASIC clock; 0: ASIC clock

+#define CLOCK3X_CTRL_REG                                (CHIP_CONF_BASE_ADDR + 0x00000064)      //bit28 => 1: asic = pll1_clock /3, 0: refresh to bit[6..8] of 0x08000004 register 

+#define PLL_NPARAM_REG                                  (CHIP_CONF_BASE_ADDR + 0x000000dc)      // n configuration register,PLL_Clk = 4*M/N

+/** @} */

+

+/** @{@name Interrupt bit map define

+ */ 

+/** interrupt status register bit map*/

+#define INT_STATUS_LCD_BIT                              (1 << 1)

+#define INT_STATUS_CAMERA_BIT                           (1 << 2)

+#define INT_STATUS_AUDIO_BIT                            (1 << 5)

+#define INT_STATUS_L2_BIT                               (1 << 10)

+#define INT_STATUS_UART4_BIT                            (1 << 13)

+#define INT_STATUS_UART3_BIT                            (1 << 14)

+#define INT_STATUS_UART2_BIT                            (1 << 15)

+#define INT_STATUS_UART1_BIT                            (1 << 16)

+#define INT_STATUS_SPI2_BIT                             (1 << 17)

+#define INT_STATUS_SPI1_BIT                             (1 << 18)

+#define INT_STATUS_SDIO_BIT                             (1 << 21)

+#define INT_STATUS_MMCSD_BIT                            (1 << 22)

+#define INT_STATUS_USB_BIT                              (1 << 25)

+#define INT_STATUS_SYS_MODULE_BIT                       (1 << 27)

+                                        

+//level 2 interrupt status bit map      

+#define INT_STATUS_TS_BIT                               (1 << 16)

+#define INT_STATUS_TIMER5_BIT                           (1 << 17)

+#define INT_STATUS_TIMER4_BIT                           (1 << 18)

+#define INT_STATUS_TIMER3_BIT                           (1 << 19)

+#define INT_STATUS_TIMER2_BIT                           (1 << 20)

+#define INT_STATUS_TIMER1_BIT                           (1 << 21)

+#define INT_STATUS_ASICCLK_BIT                          (1 << 22)

+#define INT_STATUS_WGPIO_BIT                            (1 << 23)

+#define INT_STATUS_RTC_READY_BIT                        (1 << 24)

+#define INT_STATUS_RTC_ALARM_BIT                        (1 << 25)

+#define INT_STATUS_GPIO_BIT                             (1 << 26)

+

+/* define the level1 interrupt valid bits */

+#define INT_STATUS_NBITS                                27

+

+/** IRQ interrupt mask register bit map*/

+#define IRQ_MASK_LCD_BIT                                (1 << 1)

+#define IRQ_MASK_CAMERA_BIT                             (1 << 2)

+#define IRQ_MASK_AUDIO_BIT                              (1 << 5)

+#define IRQ_MASK_L2_BIT                                 (1 << 10)

+#define IRQ_MASK_UART4_BIT                              (1 << 13)

+#define IRQ_MASK_UART3_BIT                              (1 << 14)

+#define IRQ_MASK_UART2_BIT                              (1 << 15)

+#define IRQ_MASK_UART1_BIT                              (1 << 16)

+#define IRQ_MASK_SPI2_BIT                               (1 << 17)

+#define IRQ_MASK_SPI1_BIT                               (1 << 18)

+#define IRQ_MASK_SDIO_BIT                               (1 << 21)

+#define IRQ_MASK_MMCSD_BIT                              (1 << 22)

+#define IRQ_MASK_USB_BIT                                (1 << 25)

+#define IRQ_MASK_SYS_MODULE_BIT                         (1 << 27)

+#define IRQ_MASK_USB_FS_BIT                             (1 << 23)

+

+//level 2 interrupt mask bit map

+#define IRQ_MASK_TS_BIT                                 1

+#define IRQ_MASK_TIMER5_BIT                             (1 << 1)

+#define IRQ_MASK_TIMER4_BIT                             (1 << 2)

+#define IRQ_MASK_TIMER3_BIT                             (1 << 3)

+#define IRQ_MASK_TIMER2_BIT                             (1 << 4)

+#define IRQ_MASK_TIMER1_BIT                             (1 << 5)

+#define IRQ_MASK_ASICCLK_BIT                            (1 << 6)

+#define IRQ_MASK_WGPIO_BIT                              (1 << 7)

+#define IRQ_MASK_RTC_READY_BIT                          (1 << 8)

+#define IRQ_MASK_RTC_ALARM_BIT                          (1 << 9)

+#define IRQ_MASK_GPIO_BIT                               (1 << 10)

+/** @} */

+

+

+/** @{@name SDRAM&DMA register and bit map define

+ */ 

+#define DMA_CTRL_BASE_ADDR                              (0x2002d000)

+#define DMA_PRIORITY_CTRL_REG1                          (DMA_CTRL_BASE_ADDR + 0x0000000c)

+#define DMA_PRIORITY_CTRL_REG2                          (DMA_CTRL_BASE_ADDR + 0x00000010)

+#define AHB_PRIORITY_CTRL_REG                           (DMA_CTRL_BASE_ADDR + 0x00000014)

+#define SDRAM_CFG_REG1                                  (DMA_CTRL_BASE_ADDR + 0x0)

+#define SDRAM_CFG_REG2                                  (DMA_CTRL_BASE_ADDR + 0x4)

+#define SDRAM_CFG_REG3                                  (DMA_CTRL_BASE_ADDR + 0x8)

+/** @} */

+

+

+/** @{@name L2 memory register and bit map define

+ */ 

+#define L2_BASE_ADDR                                    (0xf022c000)       //(0x2002c000)

+#define L2_DMA_ADDR                                     (L2_BASE_ADDR+0x00)

+#define L2_DMA_CNT                                      (L2_BASE_ADDR+0x40)

+#define L2_DMA_REQ                                      (L2_BASE_ADDR+0x80)

+#define L2_FRAC_ADDR                                    (L2_BASE_ADDR+0x84)

+#define L2_COMBUF_CFG                                   (L2_BASE_ADDR+0x88)

+#define L2_UARTBUF_CFG                                  (L2_BASE_ADDR+0x8c)

+#define L2_ASSIGN_REG1                                  (L2_BASE_ADDR+0x90)

+#define L2_ASSIGN_REG2                                  (L2_BASE_ADDR+0x94)

+#define L2_LDMA_CFG                                     (L2_BASE_ADDR+0x98)

+#define L2_INT_ENA                                      (L2_BASE_ADDR+0x9c)

+#define L2_STAT_REG1                                    (L2_BASE_ADDR+0xa0)

+#define L2_STAT_REG2                                    (L2_BASE_ADDR+0xa8)

+/** @} */

+

+

+/** @{@name Nandflash ECC Controller Define 

+ *      Define the register and bit map of nandflash controller

+ */

+// ECC

+#define FLASH_ECC_REG0                                  (0xf022b000)           //0x2002b000

+#define FLASH_ECC_REPAIR_REG0                           (FLASH_ECC_REG0+0x4)

+// NF controller

+#define FLASH_CTRL_REG0                                 (0xf022a100)           //(0x2002a100)

+#define FLASH_CTRL_REG20                                (FLASH_CTRL_REG0+0x50)

+#define FLASH_CTRL_REG21                                (FLASH_CTRL_REG0+0x54)

+#define FLASH_CTRL_REG22                                (FLASH_CTRL_REG0+0x58)

+#define FLASH_CTRL_REG23                                (FLASH_CTRL_REG0+0x5c)

+#define FLASH_CTRL_REG24                                (FLASH_CTRL_REG0+0x60)

+/** @} */

+

+

+/** @{@name RTC module register and bit map define

+ */

+#define RTC_MODULE_BASE_ADDR                            0x08000000      // RTC

+#define RTC_CONFIG_REG                                  (RTC_MODULE_BASE_ADDR + 0x50)   // rtc confgiuration

+#define RTC_BACK_DAT_REG                                (RTC_MODULE_BASE_ADDR + 0x54)   // rtc read back data

+#define RTC_CLOCK_DIV_REG                               (RTC_MODULE_BASE_ADDR + 0x04)   // enable/disable wakeup function

+#define RTC_WAKEUP_GPIO_P_REG                           (RTC_MODULE_BASE_ADDR + 0x3C)   // wakeup GPIO polarity

+#define RTC_WAKEUP_GPIO_C_REG                           (RTC_MODULE_BASE_ADDR + 0x40)   // clear wakeup GPIO status

+#define RTC_WAKEUP_GPIO_E_REG                           (RTC_MODULE_BASE_ADDR + 0x44)   // enable wake-up GPIO wakeup function

+#define RTC_WAKEUP_GPIO_S_REG                           (RTC_MODULE_BASE_ADDR + 0x48)   // wakeup GPIO status

+/** @} */

+

+

+/** @{@name LCD module register and bit map define

+ */ 

+#define LCD_MODULE_BASE_ADDR                            0x20010000

+#define LCD_TOP_CONFIGURE_REG                           (LCD_MODULE_BASE_ADDR | 0x0000)

+#define LCD_MPU_CTL_REG                                 (LCD_MODULE_BASE_ADDR | 0x0004)

+#define LCD_RST_PIN_REG                                 (LCD_MODULE_BASE_ADDR | 0x0008)

+#define LCD_MPU_READ_REG                                (LCD_MODULE_BASE_ADDR | 0x000C)

+#define LCD_RGB_CTL_REG1                                (LCD_MODULE_BASE_ADDR | 0x0010)

+#define LCD_RGB_CTL_REG2                                (LCD_MODULE_BASE_ADDR | 0x0014)

+#define LCD_RGB_VIRTUAL_SIZE_REG                        (LCD_MODULE_BASE_ADDR | 0x0018)

+#define LCD_RGB_VIRTUAL_OFFSET_REG                      (LCD_MODULE_BASE_ADDR | 0x001C)

+

+#define LCD_OSD_ADDR_REG                                (LCD_MODULE_BASE_ADDR | 0x20)

+#define LCD_OSD_OFFSET_REG                              (LCD_MODULE_BASE_ADDR | 0x24)

+#define LCD_OSD_F_COLOR1_REG                            (LCD_MODULE_BASE_ADDR | 0x28)

+#define LCD_OSD_F_COLOR2_REG                            (LCD_MODULE_BASE_ADDR | 0x2C)

+#define LCD_OSD_F_COLOR3_REG                            (LCD_MODULE_BASE_ADDR | 0x30)

+#define LCD_OSD_F_COLOR4_REG                            (LCD_MODULE_BASE_ADDR | 0x34)

+#define LCD_OSD_F_COLOR5_REG                            (LCD_MODULE_BASE_ADDR | 0xd0)

+#define LCD_OSD_F_COLOR6_REG                            (LCD_MODULE_BASE_ADDR | 0xd4)

+#define LCD_OSD_F_COLOR7_REG                            (LCD_MODULE_BASE_ADDR | 0xd8)

+#define LCD_OSD_F_COLOR8_REG                            (LCD_MODULE_BASE_ADDR | 0xdc)

+#define LCD_OSD_SIZE_ALPHA_REG                          (LCD_MODULE_BASE_ADDR | 0x38)

+

+#define LCD_GRB_BACKGROUND_REG                          (LCD_MODULE_BASE_ADDR | 0x003c)

+#define LCD_RGB_CTL_REG3                                (LCD_MODULE_BASE_ADDR | 0x0040)

+#define LCD_RGB_CTL_REG4                                (LCD_MODULE_BASE_ADDR | 0x0044)

+#define LCD_RGB_CTL_REG5                                (LCD_MODULE_BASE_ADDR | 0x0048)

+#define LCD_RGB_CTL_REG6                                (LCD_MODULE_BASE_ADDR | 0x004C)

+#define LCD_RGB_CTL_REG7                                (LCD_MODULE_BASE_ADDR | 0x0050)

+#define LCD_RGB_CTL_REG8                                (LCD_MODULE_BASE_ADDR | 0x0054)

+#define LCD_RGB_CTL_REG9                                (LCD_MODULE_BASE_ADDR | 0x0058)

+

+#define LCD_Y1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x005c)

+#define LCD_U1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0060) 

+#define LCD_V1_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0064) 

+#define LCD_YUV1_H_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x0068) 

+#define LCD_YUV1_V_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x006c) 

+#define LCD_YUV1_VIR_SIZE_REG                           (LCD_MODULE_BASE_ADDR | 0x0078) 

+#define LCD_YUV1_VIR_OFFSET_REG                         (LCD_MODULE_BASE_ADDR | 0x007c) 

+#define LCD_YUV1_SCALER_INFO_REG                        (LCD_MODULE_BASE_ADDR | 0x0070) 

+#define LCD_YUV1_DISPLAY_INFO_REG                       (LCD_MODULE_BASE_ADDR | 0x0074)

+

+#define LCD_Y2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0080)

+#define LCD_U2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0084) 

+#define LCD_V2_ADDR_REG                                 (LCD_MODULE_BASE_ADDR | 0x0088) 

+#define LCD_YUV2_H_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x008c) 

+#define LCD_YUV2_V_INFO_REG                             (LCD_MODULE_BASE_ADDR | 0x0090) 

+#define LCD_YUV2_SCALER_INFO_REG                        (LCD_MODULE_BASE_ADDR | 0x0094) 

+#define LCD_YUV2_DISPLAY_INFO_REG                       (LCD_MODULE_BASE_ADDR | 0x0098)

+

+#define LCD_RGB_OFFSET_REG                              (LCD_MODULE_BASE_ADDR | 0x00A8)

+#define LCD_RGB_SIZE_REG                                (LCD_MODULE_BASE_ADDR | 0x00AC)

+#define LCD_PANEL_SIZE_REG                              (LCD_MODULE_BASE_ADDR | 0x00B0)

+#define LCD_REG_CONFIG_REG                              (LCD_MODULE_BASE_ADDR | 0x00B4)

+#define LCD_LCD_GO_REG                                  (LCD_MODULE_BASE_ADDR | 0x00B8)

+#define LCD_LCD_STATUS                                  (LCD_MODULE_BASE_ADDR | 0x00BC)

+#define LCD_LCD_INTERRUPT_MASK                          (LCD_MODULE_BASE_ADDR | 0x00C0)

+#define LCD_SOFTWARE_CTL_REG                            (LCD_MODULE_BASE_ADDR | 0x00C8)

+#define LCD_TVOUT_CTL_REG                               (LCD_MODULE_BASE_ADDR | 0x00CC)

+#define LCD_CLK_CTL_REG                                 (LCD_MODULE_BASE_ADDR | 0x00E8)

+/** @} */

+

+

+/** @{@name GUI module register and bit map define

+ */

+#define GUI_BASE_ADDR                                   0x20022000

+#define GUI_SCALSRCADDR1_ADDR                           (GUI_BASE_ADDR+0x108)   // Input image start address 1

+#define GUI_SCALSRCADDR2_ADDR                           (GUI_BASE_ADDR+0x10c) // Input image start address 2

+#define GUI_SCALSRCADDR3_ADDR                           (GUI_BASE_ADDR+0x110) // Input image start address 3

+#define GUI_SCALSRCSTRD_ADDR                            (GUI_BASE_ADDR+0x118)   // Input image line stride

+#define GUI_SCALDSTADDR_ADDR                            (GUI_BASE_ADDR+0x11c)   // Output image start address

+#define GUI_SCALSRCRECT_ADDR                            (GUI_BASE_ADDR+0x114)   // Input image rectangle dimensions

+#define GUI_SCALDSTRECT_ADDR                            (GUI_BASE_ADDR+0x120)   // Output image rectangle dimensions

+#define GUI_SCALDSTSTRD_ADDR                            (GUI_BASE_ADDR+0x124)   // Output image line stride

+#define GUI_SCALRATIO_ADDR                              (GUI_BASE_ADDR+0x104)   // Scaling parameters, scale=8192/ILX[8:0]

+#define GUI_POINT1_ADDR                                 (GUI_BASE_ADDR+0x0c)    // Destination Offset

+#define GUI_CMD_ADDR                                    (GUI_BASE_ADDR+0x04)    // Command

+#define GUI_SCALCTRL_ADDR                               (GUI_BASE_ADDR+0x100)   // Color Space conversion and scaling control

+#define GUI_SCALOFFSET_ADDR                             (GUI_BASE_ADDR+0x128)   // Output image line stride

+/** @} */

+

+/** @{@name IMAGE sensor module register and bit map define

+ */

+#define IMAGE_MODULE_BASE_ADDR                          0x20030000      // image sensor

+#define IMG_CMD_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0000)

+#define IMG_HINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0004)

+#define IMG_HINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0008)

+#define IMG_VINFO1_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x000C)

+#define IMG_VINFO2_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0010)

+                                                        

+#define IMG_YADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0018)

+#define IMG_UADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x001c)

+#define IMG_VADDR_ODD                                   (IMAGE_MODULE_BASE_ADDR | 0x0020)

+#define IMG_RGBADDR_ODD                                 (IMAGE_MODULE_BASE_ADDR | 0x0024)

+#define IMG_YADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0028)

+#define IMG_UADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x002c)

+#define IMG_VADDR_EVE                                   (IMAGE_MODULE_BASE_ADDR | 0x0030)

+#define IMG_RGBADDR_EVE                                 (IMAGE_MODULE_BASE_ADDR | 0x0034)

+#define IMG_CONFIG_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0040)

+#define IMG_STATUS_ADDR                                 (IMAGE_MODULE_BASE_ADDR | 0x0060)

+#define IMG_NUM_ADDR                                    (IMAGE_MODULE_BASE_ADDR | 0x0080)

+

+#define MUL_FUN_CTL_REG                                 (CHIP_CONF_BASE_ADDR | 0x0058)

+/** @} */

+

+

+/** @{@name UART module register and bit map define

+ */

+#define UART_MODULE_BASE_ADDR                           0x20026000      // UART

+#define UART0_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00000000)

+#define UART1_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00001000)

+#define UART2_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00002000)

+#define UART3_BASE_ADDR                                 (UART_MODULE_BASE_ADDR + 0x00003000)

+                                                        

+#define UART_CFG_REG1                                   (0x00)

+#define UART_CFG_REG2                                   (0x04)

+#define UART_DATA_CFG                                   (0x08)

+#define UART_RX_THREINT                                 (0x0c)

+/** @} */

+

+/** @{@name SPI module register and bit map define

+ */

+#define SPI_MODULE_BASE_ADDR                            0x20020000      // SPI

+#define SPI0_BASE_ADDR                                  (SPI_MODULE_BASE_ADDR + 0x00004000)

+#define SPI1_BASE_ADDR                                  (SPI_MODULE_BASE_ADDR + 0x00005000)

+                                                        

+#define ASPEN_SPI_CTRL                                  (0x00)

+#define ASPEN_SPI_STA                                   (0x04)

+#define ASPEN_SPI_INTENA                                (0x08)

+#define ASPEN_SPI_NBR                                   (0x0c)

+#define ASPEN_SPI_TX_EXBUF                              (0x10)

+#define ASPEN_SPI_RX_EXBUF                              (0x14)

+#define ASPEN_SPI_TX_INBUF                              (0x18)

+#define ASPEN_SPI_RX_INBUF                              (0x1c)

+#define ASPEN_SPI_RTIM                                  (0x20)

+/** @} */

+

+/** @{@name USB register and bit map define

+ *  Define register to control USB port and the bit map of the register

+ */

+#define USB_CONTROL_REG                                 (0x08000058)

+#define USB_FIFO_EP0                                    (USB_BASE_ADDR + 0x0020)

+#define USB_REG_FADDR                                   (USB_BASE_ADDR + 0x0000)

+#define USB_REG_POWER                                   (USB_BASE_ADDR + 0x0001)

+#define USB_REG_INTRTX1                                 (USB_BASE_ADDR + 0x0002)

+#define USB_REG_INTRTX2                                 (USB_BASE_ADDR + 0x0003)

+#define USB_REG_INTRRX1                                 (USB_BASE_ADDR + 0x0004)

+#define USB_REG_INTRRX2                                 (USB_BASE_ADDR + 0x0005)

+#define USB_REG_INTRTX1E                                (USB_BASE_ADDR + 0x0006)

+#define USB_REG_INTRTX2E                                (USB_BASE_ADDR + 0x0007)

+#define USB_REG_INTRRX1E                                (USB_BASE_ADDR + 0x0008)

+#define USB_REG_INTRRX2E                                (USB_BASE_ADDR + 0x0009)

+#define USB_REG_INTRUSB                                 (USB_BASE_ADDR + 0x000A)

+#define USB_REG_INTRUSBE                                (USB_BASE_ADDR + 0x000B)

+#define USB_REG_FRAME1                                  (USB_BASE_ADDR + 0x000C)

+#define USB_REG_FRAME2                                  (USB_BASE_ADDR + 0x000D)

+#define USB_REG_INDEX                                   (USB_BASE_ADDR + 0x000E)

+#define USB_REG_TESEMODE                                (USB_BASE_ADDR + 0x000F)

+#define USB_REG_DEVCTL                                  (USB_BASE_ADDR + 0x0060)

+#define USB_REG_TXMAXP0                                 (USB_BASE_ADDR + 0x0010)

+#define USB_REG_TXMAXP1                                 (USB_BASE_ADDR + 0x0010)

+#define USB_REG_CSR0                                    (USB_BASE_ADDR + 0x0012)

+#define USB_REG_TXCSR1                                  (USB_BASE_ADDR + 0x0012)

+#define USB_REG_CSR02                                   (USB_BASE_ADDR + 0x0013)

+#define USB_REG_TXCSR2                                  (USB_BASE_ADDR + 0x0013)

+#define USB_REG_RXMAXP1                                 (USB_BASE_ADDR + 0x0014)

+#define USB_REG_RXMAXP2                                 (USB_BASE_ADDR + 0x0015)

+#define USB_REG_RXCSR1                                  (USB_BASE_ADDR + 0x0016)

+#define USB_REG_RXCSR2                                  (USB_BASE_ADDR + 0x0017)

+#define USB_REG_COUNT0                                  (USB_BASE_ADDR + 0x0018)

+#define USB_REG_RXCOUNT1                                (USB_BASE_ADDR + 0x0018)

+#define USB_REG_RXCOUNT2                                (USB_BASE_ADDR + 0x0019)

+#define USB_REG_TXTYPE                                  (USB_BASE_ADDR + 0x001A)

+#define USB_REG_RXTYPE                                  (USB_BASE_ADDR + 0x001C)

+#define USB_REG_RXINTERVAL                              (USB_BASE_ADDR + 0x001D)

+#define USB_REG_NAKLIMIT0                               (USB_BASE_ADDR + 0x001B)

+                                                        

+#define USB_EP0_TX_COUNT                                (USB_BASE_ADDR + 0x0330)

+#define USB_EP2_TX_COUNT                                (USB_BASE_ADDR + 0x0334)

+                                                        

+#define USB_FORBID_WRITE_REG                            (USB_BASE_ADDR + 0x0338)

+                                                        

+#define USB_START_PRE_READ_REG                          (USB_BASE_ADDR + 0x033C)

+#define USB_FS_SPEED_REG                                (USB_BASE_ADDR + 0x0344)

+

+#define USB_FS_HOST_BASE_ADDR                           0x70000800

+#define USB_FS_HOST_REG_FADDR                           (USB_FS_HOST_BASE_ADDR + 0x0000)

+#define USB_FS_HOST_REG_POWER                           (USB_FS_HOST_BASE_ADDR + 0x0001)

+#define USB_FS_HOST_REG_INTRTX1                         (USB_FS_HOST_BASE_ADDR + 0x0002)

+#define USB_FS_HOST_REG_INTRTX2                         (USB_FS_HOST_BASE_ADDR + 0x0003)

+#define USB_FS_HOST_REG_INTRRX1                         (USB_FS_HOST_BASE_ADDR + 0x0004)

+#define USB_FS_HOST_REG_INTRRX2                         (USB_FS_HOST_BASE_ADDR + 0x0005)

+#define USB_FS_HOST_REG_INTRTX1E                        (USB_FS_HOST_BASE_ADDR + 0x0006)

+#define USB_FS_HOST_REG_INTRTX2E                        (USB_FS_HOST_BASE_ADDR + 0x0007)

+#define USB_FS_HOST_REG_INTRRX1E                        (USB_FS_HOST_BASE_ADDR + 0x0008)

+#define USB_FS_HOST_REG_INTRRX2E                        (USB_FS_HOST_BASE_ADDR + 0x0009)

+#define USB_FS_HOST_REG_INTRUSB                         (USB_FS_HOST_BASE_ADDR + 0x000A)

+#define USB_FS_HOST_REG_INTRUSBE                        (USB_FS_HOST_BASE_ADDR + 0x000B)

+#define USB_FS_HOST_REG_FRAME1                          (USB_FS_HOST_BASE_ADDR + 0x000C)

+#define USB_FS_HOST_REG_FRAME2                          (USB_FS_HOST_BASE_ADDR + 0x000D)

+#define USB_FS_HOST_REG_INDEX                           (USB_FS_HOST_BASE_ADDR + 0x000E)

+#define USB_FS_HOST_REG_TESEMODE                        (USB_FS_HOST_BASE_ADDR + 0x000F)

+#define USB_FS_HOST_REG_DEVCTL                          (USB_FS_HOST_BASE_ADDR + 0x0060)

+#define USB_FS_HOST_REG_TXMAXP0                         (USB_FS_HOST_BASE_ADDR + 0x0010)

+#define USB_FS_HOST_REG_TXMAXP1                         (USB_FS_HOST_BASE_ADDR + 0x0010)

+#define USB_FS_HOST_REG_CSR0                            (USB_FS_HOST_BASE_ADDR + 0x0012)

+#define USB_FS_HOST_REG_TXCSR1                          (USB_FS_HOST_BASE_ADDR + 0x0012)

+#define USB_FS_HOST_REG_CSR02                           (USB_FS_HOST_BASE_ADDR + 0x0013)

+#define USB_FS_HOST_REG_TXCSR2                          (USB_FS_HOST_BASE_ADDR + 0x0013)

+#define USB_FS_HOST_REG_RXMAXP1                         (USB_FS_HOST_BASE_ADDR + 0x0014)

+#define USB_FS_HOST_REG_RXMAXP2                         (USB_FS_HOST_BASE_ADDR + 0x0015)

+#define USB_FS_HOST_REG_RXCSR1                          (USB_FS_HOST_BASE_ADDR + 0x0016)

+#define USB_FS_HOST_REG_RXCSR2                          (USB_FS_HOST_BASE_ADDR + 0x0017)

+#define USB_FS_HOST_REG_COUNT0                          (USB_FS_HOST_BASE_ADDR + 0x0018)

+#define USB_FS_HOST_REG_RXCOUNT1                        (USB_FS_HOST_BASE_ADDR + 0x0018)

+#define USB_FS_HOST_REG_RXCOUNT2                        (USB_FS_HOST_BASE_ADDR + 0x0019)

+#define USB_FS_HOST_REG_TXTYPE                          (USB_FS_HOST_BASE_ADDR + 0x001A)

+#define USB_FS_HOST_REG_RXTYPE                          (USB_FS_HOST_BASE_ADDR + 0x001C)

+#define USB_FS_HOST_REG_RXINTERVAL                      (USB_FS_HOST_BASE_ADDR + 0x001D)

+#define USB_FS_HOST_REG_NAKLIMIT0                       (USB_FS_HOST_BASE_ADDR + 0x001B)

+#define USB_FS_HOST_REG_FIFOSIZE                        (USB_FS_HOST_BASE_ADDR + 0x001F)

+

+#define USB_L2_CONTROL_FIFO                             (0x48001500)

+                                                        

+#define USB_FS_FIFO_EP0                                 0x70000820

+#define USB_FS_FIFO_EP1                                 0x70000824

+#define USB_FS_FIFO_EP2                                 0x70000828

+#define USB_FS_FIFO_EP3                                 0x7000082c 

+                                                        

+/**  USB DMA */                         

+#define USB_FS_HOST_DMA_INTR                            (USB_FS_HOST_BASE_ADDR + 0x0200)

+#define USB_FS_HOST_DMA_CNTL_1                          (USB_FS_HOST_BASE_ADDR + 0x0204)

+#define USB_FS_HOST_DMA_ADDR_1                          (USB_FS_HOST_BASE_ADDR + 0x0208)

+#define USB_FS_HOST_DMA_COUNT_1                         (USB_FS_HOST_BASE_ADDR + 0x020c)

+#define USB_FS_HOST_DMA_CNTL_2                          (USB_FS_HOST_BASE_ADDR + 0x0214)

+#define USB_FS_HOST_DMA_ADDR_2                          (USB_FS_HOST_BASE_ADDR + 0x0218)

+#define USB_FS_HOST_DMA_COUNT_2                         (USB_FS_HOST_BASE_ADDR + 0x021c)

+

+/**Dynamic FIFO sizing   JUST FOR HOST  */

+#define USB_REG_TXFIFO1                                 (USB_BASE_ADDR + 0x001C)

+#define USB_REG_TXFIFO2                                 (USB_BASE_ADDR + 0x001D)

+#define USB_REG_RXFIFO1                                 (USB_BASE_ADDR + 0x001E)

+#define USB_REG_RXFIFO2                                 (USB_BASE_ADDR + 0x001F)

+                                                        

+#define USB_REG_FIFOSIZE                                (USB_BASE_ADDR + 0x001F)

+                                                        

+/**  USB DMA */                                         

+#define USB_DMA_INTR                                    (USB_BASE_ADDR + 0x0200)

+#define USB_DMA_CNTL_1                                  (USB_BASE_ADDR + 0x0204)

+#define USB_DMA_ADDR_1                                  (USB_BASE_ADDR + 0x0208)

+#define USB_DMA_COUNT_1                                 (USB_BASE_ADDR + 0x020c)

+#define USB_DMA_CNTL_2                                  (USB_BASE_ADDR + 0x0214)

+#define USB_DMA_ADDR_2                                  (USB_BASE_ADDR + 0x0218)

+#define USB_DMA_COUNT_2                                 (USB_BASE_ADDR + 0x021c)                                 

+#define USB_FS_SPEED_REG                                (USB_BASE_ADDR + 0x0344)

+/** @} */

+

+

+/** @{@name SDMMC/SDIO module register and bit map define

+ */

+#define SD_MMC_BASE_ADDR                                0x20020000       /*mmc_sd interface*/

+#define SDIO_BASE_ADDR                                  0x20021000       /*sdio interface*/

+#define SD_CLK_CTRL_REG                                 ( SD_MMC_BASE_ADDR + 0x04  )

+#define SD_ARGUMENT_REG                                 ( SD_MMC_BASE_ADDR + 0x08  )

+#define SD_CMD_REG                                      ( SD_MMC_BASE_ADDR + 0x0C  )

+#define SD_RESP_CMD_REG                                 ( SD_MMC_BASE_ADDR + 0x10  )

+#define SD_RESP_REG0                                    ( SD_MMC_BASE_ADDR + 0x14  )

+#define SD_RESP_REG1                                    ( SD_MMC_BASE_ADDR + 0x18  )

+#define SD_RESP_REG2                                    ( SD_MMC_BASE_ADDR + 0x1c  )

+#define SD_RESP_REG3                                    ( SD_MMC_BASE_ADDR + 0x20  )

+#define SD_DATA_TIM_REG                                 ( SD_MMC_BASE_ADDR + 0x24  )

+#define SD_DATA_LEN_REG                                 ( SD_MMC_BASE_ADDR + 0x28  )

+#define SD_DATA_CTRL_REG                                ( SD_MMC_BASE_ADDR + 0x2C  )

+#define SD_DATA_COUT_REG                                ( SD_MMC_BASE_ADDR + 0x30  )

+#define SD_INT_STAT_REG                                 ( SD_MMC_BASE_ADDR + 0x34  )

+#define SD_INT_ENABLE                                   ( SD_MMC_BASE_ADDR + 0x38  )

+#define SD_DMA_MODE_REG                                 ( SD_MMC_BASE_ADDR + 0x3C  )

+#define SD_CPU_MODE_REG                                 ( SD_MMC_BASE_ADDR + 0x40  )

+                                                        

+#define SDIO_CLK_CTRL_REG                               ( SDIO_BASE_ADDR + 0x04  )

+#define SDIO_ARGUMENT_REG                               ( SDIO_BASE_ADDR + 0x08  )

+#define SDIO_CMD_REG                                    ( SDIO_BASE_ADDR + 0x0C  )

+#define SDIO_RESP_CMD_REG                               ( SDIO_BASE_ADDR + 0x10  )

+#define SDIO_RESP_REG0                                  ( SDIO_BASE_ADDR + 0x14  )

+#define SDIO_RESP_REG1                                  ( SDIO_BASE_ADDR + 0x18  )

+#define SDIO_RESP_REG2                                  ( SDIO_BASE_ADDR + 0x1c  )

+#define SDIO_RESP_REG3                                  ( SDIO_BASE_ADDR + 0x20  )

+#define SDIO_DATA_TIM_REG                               ( SDIO_BASE_ADDR + 0x24  )

+#define SDIO_DATA_LEN_REG                               ( SDIO_BASE_ADDR + 0x28  )

+#define SDIO_DATA_CTRL_REG                              ( SDIO_BASE_ADDR + 0x2C  )

+#define SDIO_DATA_COUT_REG                              ( SDIO_BASE_ADDR + 0x30  )

+#define SDIO_INT_STAT_REG                               ( SDIO_BASE_ADDR + 0x34  )

+#define SDIO_INT_ENABLE                                 ( SDIO_BASE_ADDR + 0x38  )

+#define SDIO_DMA_MODE_REG                               ( SDIO_BASE_ADDR + 0x3C  )

+#define SDIO_CPU_MODE_REG                               ( SDIO_BASE_ADDR + 0x40  )

+/** @} */

+

+

+/** @{@name ANALOG module register and bit map define

+ */

+#define ADC_MODULE_BASE_ADDR                            0x08000000      // Analog 

+#define ADC_CONTROL1                                    (ADC_MODULE_BASE_ADDR + 0x60)

+#define ADC_CLK_DIV                                     (ADC_MODULE_BASE_ADDR + 0x08)

+#define ADC_CLK_DIV1                                    (ADC_MODULE_BASE_ADDR + 0x04)

+#define ANLSOFT_CONTROL                                 (ADC_MODULE_BASE_ADDR + 0x34)

+#define USB_CONTROL                                     (ADC_MODULE_BASE_ADDR + 0x44)

+#define X_COORDINATE_REG                                (ADC_MODULE_BASE_ADDR + 0x68)

+#define Y_COORDINATE_REG                                (ADC_MODULE_BASE_ADDR + 0x6c)

+#define TS_CONTROL_REG2                                 (ADC_MODULE_BASE_ADDR + 0x64)

+#define ADC1_STAT_REG                                   (ADC_MODULE_BASE_ADDR + 0x70)

+#define TS_CONTROL_REG1                                 (ADC_MODULE_BASE_ADDR + 0x5c)

+#define ANALOG_CONTROL1                                 (ADC_MODULE_BASE_ADDR + 0x5c)

+#define ANALOG_CONTROL2                                 (ADC_MODULE_BASE_ADDR + 0x64)

+#define ADC2_MODE_CFG                                   (0x20072000)

+#define DAC_CONFIG_REG                                  (0x2002E000)        //DAC

+#define I2S_CONFIG_REG                                  (0x2002E004)        //I2S

+/** @} */

+

+

+/** @{@name PWM module register and bit map define

+ */

+#define PWM_MODULE_BASE_ADDR                            0x08000000

+#define PWM_CTRL_REG1                                   (PWM_MODULE_BASE_ADDR + 0x2c)

+#define PWM_CTRL_REG2                                   (PWM_MODULE_BASE_ADDR + 0x30)

+#define PWM_CTRL_REG3                                   (PWM_MODULE_BASE_ADDR + 0xb4)

+#define PWM_CTRL_REG4                                   (PWM_MODULE_BASE_ADDR + 0xb8)

+/** @} */

+

+

+/** @{@name TIMER module register and bit map define

+ */

+#define TIMER_MODULE_BASE_ADDR                          0x08000000      // timer registers

+#define TIMER1_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x18)

+#define TIMER2_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x1c)

+#define TIMER3_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x20)

+#define TIMER4_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x24)

+#define TIMER5_CTRL_REG                                 (TIMER_MODULE_BASE_ADDR + 0x28) 

+#define TIMER1_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x100)

+#define TIMER2_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x104)

+#define TIMER3_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x108)

+#define TIMER4_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x10c)

+#define TIMER5_READ_BACK_REG                            (TIMER_MODULE_BASE_ADDR + 0x110)

+/** @} */

+

+

+/** @{@name GPIO module register and bit map define

+ */

+//gpio direction

+#define GPIO_MODULE_BASE_ADDR                           0x08000000      // GPIO registers

+#define GPIO_DIR_REG1                                   (GPIO_MODULE_BASE_ADDR + 0x7c)

+#define GPIO_DIR_REG2                                   (GPIO_MODULE_BASE_ADDR + 0x84)

+#define GPIO_DIR_REG3                                   (GPIO_MODULE_BASE_ADDR + 0x8c)

+#define GPIO_DIR_REG4                                   (GPIO_MODULE_BASE_ADDR + 0x94)

+                                                        

+//gpio output control                                   

+#define GPIO_OUT_REG1                                   (GPIO_MODULE_BASE_ADDR + 0x80)

+#define GPIO_OUT_REG2                                   (GPIO_MODULE_BASE_ADDR + 0x88)

+#define GPIO_OUT_REG3                                   (GPIO_MODULE_BASE_ADDR + 0x90)

+#define GPIO_OUT_REG4                                   (GPIO_MODULE_BASE_ADDR + 0x98)

+                                                        

+//gpio input control                                    

+#define GPIO_IN_REG1                                    (GPIO_MODULE_BASE_ADDR + 0xbc)

+#define GPIO_IN_REG2                                    (GPIO_MODULE_BASE_ADDR + 0xc0)

+#define GPIO_IN_REG3                                    (GPIO_MODULE_BASE_ADDR + 0xc4)

+#define GPIO_IN_REG4                                    (GPIO_MODULE_BASE_ADDR + 0xc8)

+                                                        

+//gpio interrupt enable/disable                         

+#define GPIO_INT_EN1                                    (GPIO_MODULE_BASE_ADDR + 0xe0)

+#define GPIO_INT_EN2                                    (GPIO_MODULE_BASE_ADDR + 0xe4)

+#define GPIO_INT_EN3                                    (GPIO_MODULE_BASE_ADDR + 0xe8)

+#define GPIO_INT_EN4                                    (GPIO_MODULE_BASE_ADDR + 0xec)

+                                                        

+//gpio interrupt sensitivity level                      

+#define GPIO_INT_LEVEL_REG1                             (GPIO_MODULE_BASE_ADDR + 0xf0)

+#define GPIO_INT_LEVEL_REG2                             (GPIO_MODULE_BASE_ADDR + 0xf4)

+#define GPIO_INT_LEVEL_REG3                             (GPIO_MODULE_BASE_ADDR + 0xf8)

+#define GPIO_INT_LEVEL_REG4                             (GPIO_MODULE_BASE_ADDR + 0xfc)

+                                                        

+//gpio pull/pulldown reg                                

+#define GPIO_PULLUPDOWN_REG1                            (GPIO_MODULE_BASE_ADDR + 0x9c)

+#define GPIO_PULLUPDOWN_REG2                            (GPIO_MODULE_BASE_ADDR + 0xa0)

+#define GPIO_PULLUPDOWN_REG3                            (GPIO_MODULE_BASE_ADDR + 0xa4)

+#define GPIO_PULLUPDOWN_REG4                            (GPIO_MODULE_BASE_ADDR + 0xa8)

+                                                        

+//io control reg                                        

+#define GPIO_IO_CONTROL_REG1                            (GPIO_MODULE_BASE_ADDR + 0xD4)

+#define GPIO_IO_CONTROL_REG2                            (GPIO_MODULE_BASE_ADDR + 0xD8)

+                                                        

+//share pin control reg                                 

+#define GPIO_SHAREPIN_CONTROL2                          (GPIO_MODULE_BASE_ADDR + 0x74)

+#define GPIO_SHAREPIN_CONTROL1                          (GPIO_MODULE_BASE_ADDR + 0x78)

+/** @} */

+

+

+/** @{@name Register Operation Define

+ *      Define the macro for read/write register and memory

+ */

+//#ifdef OS_ANYKA

+/* ------ Macro definition for reading/writing data from/to register ------ */

+#define HAL_READ_UINT32( _register_, _value_ )          ((_value_) = *((volatile T_U32 *)(_register_)))

+#define HAL_WRITE_UINT32( _register_, _value_ )         (*((volatile T_U32 *)(_register_)) = (_value_))

+

+#define REG32(_register_)                               (*(volatile T_U32 *)(_register_))

+#define REG16(_register_)                               (*(volatile T_U16 *)(_register_))

+#define REG8(_register_)                                (*(volatile T_U8 *)(_register_))

+

+#if 0

+//read and write register

+#define outb(v,p)                                       (*(volatile unsigned char *)(p) = (v))

+#define outw(v,p)                                       (*(volatile unsigned short *)(p) = (v))

+#define outl(v,p)                                       (*(volatile unsigned long  *)(p) = (v))

+                                                        

+#define inb(p)                                          (*(volatile unsigned char *)(p))

+#define inw(p)                                          (*(volatile unsigned short *)(p))

+#define inl(p)                                          (*(volatile unsigned long *)(p))

+#endif

+

+#define WriteBuf(v,p)                                   (*(volatile unsigned long  *)(p) = (v))

+#define ReadBuf(p)                                      (*(volatile unsigned long *)(p))

+                                                        

+#define WriteRamb(v,p)                                  (*(volatile unsigned char *)(p) = (v))

+#define WriteRamw(v,p)                                  (*(volatile unsigned short *)(p) = (v))

+#define WriteRaml(v,p)                                  (*(volatile unsigned long  *)(p) = (v))

+                                                        

+#define ReadRamb(p)                                     (*(volatile unsigned char *)(p))

+#define ReadRamw(p)                                     (*(volatile unsigned short *)(p))

+#define ReadRaml(p)                                     (*(volatile unsigned long *)(p))

+//#else

+/* ------ Macro definition for reading/writing data from/to register ------ */

+/*

+#define HAL_READ_UINT8( _register_, _value_ )        

+#define HAL_WRITE_UINT8( _register_, _value_ )       

+#define HAL_READ_UINT16( _register_, _value_ )      

+#define HAL_WRITE_UINT16( _register_, _value_ )     

+#define HAL_READ_UINT32( _register_, _value_ )      

+#define HAL_WRITE_UINT32( _register_, _value_ )     

+#define REG32(_register_)  

+#define REG16(_register_)  

+#define REG8(_register_) 

+*/

+//#endif

+

+//error type define

+#define UNDEF_ERROR             1

+#define ABT_ERROR               2

+#define PREF_ERROR              3

+/** @} */

+

+/*@}*/

+

+#endif  // _ANYKA_CPU_H_

+

diff --git a/drivers/mtd/nand/ak98-nand/arch_nand.h b/drivers/mtd/nand/ak98-nand/arch_nand.h
new file mode 100644
index 00000000000..973a3fb5005
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/arch_nand.h
@@ -0,0 +1,337 @@
+/**@file arch_nand.h

+ * @brief AK880x nand controller

+ *

+ * This file describe how to control the AK880x nandflash driver.

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author yiruoxiang, jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ */

+#ifndef __ARCH_NAND_H__

+#define __ARCH_NAND_H__

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @defgroup NandFlash Nandflash group

+ *  @ingroup Drv_Lib

+ */

+/*@{*/

+#define NFC_FIFO_SIZE			512

+#define NFC_LOG_SPARE_SIZE		16

+

+/* add for page size branches by lgh*/

+#define NAND_PAGE_SIZE_2KB		2048

+

+#define NAND_512B_PAGE      0   // 512 bytes per page

+#define NAND_2K_PAGE        1

+#define NAND_4K_PAGE        2

+#define NAND_8K_PAGE        3

+

+#define NFC_SUPPORT_CHIPNUM    (4)

+#define MTD_PART_NAME_LEN      (4)

+

+#define NAND_DATA_SIZE_P512B      512

+#define NAND_DATA_SIZE_P1KB       1024

+

+#define NFLASH_READ_STATUS	0x70

+#define AK_NAND_STATUS_READY 	(1 << 6)

+#define AK_NAND_STATUS_ERROR 	(1 << 0)

+

+

+struct partitions

+{

+	char name[MTD_PART_NAME_LEN]; 		   

+	unsigned long long size;			           

+	unsigned long long offset;         

+	unsigned int mask_flags;		       

+}__attribute__((packed));

+

+typedef enum

+{

+    ECC_4BIT_P512B  = 0,    /*4 bit ecc requirement per 512 bytes*/

+    ECC_8BIT_P512B  = 1,    //8 bit ecc requirement per 512 bytes

+    ECC_12BIT_P512B = 2,    //12 bit ecc requirement per 512 bytes

+    ECC_16BIT_P512B = 3,    //16 bit ecc requirement per 512 bytes

+    ECC_24BIT_P1KB  = 4,    //24 bit ecc requirement per 1024 bytes

+    ECC_32BIT_P1KB  = 5     //32 bit ecc requirement per 1024 bytes

+}ECC_TYPE;

+

+

+typedef struct SNandEccStru

+{

+    T_U8 *buf;                         //data buffer, e.g. common data buffer or spare buffer

+    T_U32 buf_len;                     //data total length, e.g. 4096 or 8192

+    T_U32 ecc_section_len;             //ecc section length, e.g. 512, 512+4, or 1024, 1024+4

+    ECC_TYPE ecc_type;                 //ecc type, e.g. ECC_4BIT or ECC_8BIT

+}T_NAND_ECC_STRU, *T_PNAND_ECC_STRU;

+

+

+struct SNandflash_Add

+{

+    T_U8    ChipPos[NFC_SUPPORT_CHIPNUM];

+    T_U8    RowCycle;

+    T_U8    ColCycle;

+    T_U8    ChipType;

+    T_U8    EccType;

+    T_U32   PageSize;

+    T_U32   PagesPerBlock;

+};

+

+typedef struct SNandflash_Add* T_PNandflash_Add;

+typedef struct SNandflash_Add T_Nandflash_Add;

+//**********************************************************************

+

+/**

+ * @brief initialization of nandflash hardware.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @return  T_VOID

+ */

+T_VOID nand_HWinit(T_VOID);

+

+/**

+ * @brief config nand command and data cycle

+ *

+ * @author xuchang

+ * @date 2007-12-27

+ * @param[in] CmdCycle the command cycle to config

+ * @param[in] DataCycle the data cycle to config

+ * @return T_VOID

+ */

+T_VOID nand_config_timeseq(T_U32 cmd_cycle, T_U32 data_cycle);

+

+/**

+ * @brief calculate each nand's timing under 62MHz & 124MHz

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] DefDataLen default data lenght

+ * @return  T_VOID

+ */

+T_VOID nand_calctiming(T_U32 DefDataLen);

+

+/**

+ * @brief change nand timing when Freq has changed

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] Freq frequency

+ * @return  T_VOID

+ */

+T_VOID nand_changetiming(T_U32 Freq);

+

+/**

+ * @brief read nand flash chip ID.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @return  T_U32

+ * @retval  current nandflash ID

+ */

+T_U32 nand_read_chipID(T_U32 Chip);

+

+void nand_settiming(unsigned long cmd_timing, unsigned long data_timing);

+

+unsigned char nand_get_status(unsigned char chip);

+

+/**

+ * @brief reset nand flash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be reset.

+ * @return  T_VOID

+ */

+T_VOID nand_reset(T_U32 chip);

+

+/**

+ * @brief read data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in/out] pDataCtrl control reading data section: buffer, data lenght, ECC.

+ * @param[in/out] pSpareCtrl control reading spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readpage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl);

+

+#if 0

+/**

+ * @brief read one page(page size>=2048) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be large than or equal to 2048 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 *Spare);

+

+/**

+ * @brief read one page(page size=512) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be 512 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare);

+#endif

+/**

+ * @brief read file system info.

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readspare(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 *Spare);

+

+/**

+ * @brief read data from nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data.

+ * @param[in] Len how many bytes read from nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readbytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Len);

+

+/**

+ * @brief write data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] pDataCtrl control writting data section: buffer, data lenght, ECC.

+ * @param[in] pSpareCtrl control writting spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writepage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl);

+

+#if 0

+/**

+ * @brief write one page(page size>=2048) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be large than or equal to 2048 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Spare);

+

+/**

+ * @brief write one page(page size=512) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be 512 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare);

+#endif 

+/**

+ * @brief write data to nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data.

+ * @param[in] Len how many bytes write to nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writebytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, const T_U8 Data[], T_U32 Len);

+

+/**

+ * @brief erase one block of nandflash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] BlkStartPage first page of the block.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return T_U32

+ * @retval 0 means write successfully

+ * @retval 1 means write unsuccessfully

+ * @retval 2 means time out

+ */

+T_U32 nand_eraseblock(T_U32 Chip, T_U32 BlkStartPage, T_PNandflash_Add pNF_Add);

+

+#ifdef CONFIG_MTD_NAND_TEST  

+T_U32 nand_get_erase_block_count(T_U32 blocknum);

+#endif

+

+/**

+ * @brief copy one physical page to another one.

+ *

+ * hardware copyback mode, there should be caches in nandflash, source and destation page should be in the same plane

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] SouPhyPage the source page to read.

+ * @param[in] DesPhyPage the destination page to write.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return  T_U32

+ * @retval  0 means write successfully

+ * @retval  1 means write unsuccessfully

+ * @retval  2 means time out

+ */

+T_U32 nand_copyback(T_U32 Chip, T_U32 SrcPhyPage, T_U32 DestPhyPage, T_PNandflash_Add pNF_Add);

+

+/*@}*/

+#ifdef __cplusplus

+}

+#endif

+

+#endif //__ARCH_NAND_H__

diff --git a/drivers/mtd/nand/ak98-nand/communicate.c b/drivers/mtd/nand/ak98-nand/communicate.c
new file mode 100755
index 00000000000..4d6c5757065
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/communicate.c
@@ -0,0 +1,500 @@
+/*******************************************************************************
+ * #BRIEF communicate for AK3226 use the L2 Inter Globe Fifo.
+ * Copyright (C) 2007 Anyka (Guangzhou) Software Technology Co., LTD
+ * #AUTHOR Zou TianXiang
+ * #DATE 2007-7-1
+ ********************************************************************************/
+#include <linux/kernel.h>
+#include <mach/map.h>
+
+#include "communicate.h"
+
+#define L2_BASE_ADDR		AK98_VA_L2CTRL
+#define L2_DMA_BLOCK_ADDR_CONF	AK98_VA_L2CTRL
+
+#define L2_DMA_BLOCK_COUNT_CONF	AK98_VA_L2CTRL+0x40
+
+#define L2_DMA_CRTL		(L2_BASE_ADDR+0x80)
+#define L2_FRACTIOIN_DMA_CONF	(L2_BASE_ADDR+0x84)
+#define L2_BLOCK_DMA_CONF	(L2_BASE_ADDR+0x88)
+#define L2_FLAG_CONF		(L2_BASE_ADDR+0x8C)
+#define L2_BUF_ID_CONF		(L2_BASE_ADDR+0x90)
+#define L2_BUF2_ID_CONF		(L2_BASE_ADDR+0x94)
+#define L2_LDMA_CONF		(L2_BASE_ADDR+0x98)
+#define L2_INTR_EN		(L2_BASE_ADDR+0x9C)
+#define L2_STATUS1		(L2_BASE_ADDR+0xA0)
+#define L2_STATUS2		(L2_BASE_ADDR+0xA8)
+
+#define FRAC_DMA_DIRECT_WRITE	(1<<8)
+#define FRAC_DMA_DIRECT_READ	(0<<8)
+#define FRAC_DMA_START_REQ	(1<<9)
+#define	L2_DMA_ENABLE		(1)
+
+#define L2_BUF_MEM_BASE_ADDR	AK98_VA_L2MEM
+
+static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type);
+
+/*********************************************************************
+Function:       communate_conf
+Description:    Set the BUF ID Correspond to the peripheral
+Input:    	  PERIPHERAL_TYPE dev_type
+GLOBE_BUF_ID buf_id
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id)
+{
+	T_U32 buf_ena_val;
+	T_U32 buf_id_val;
+	//    T_U32 buf_status;
+	T_U32 dam_ctrl_val;
+	T_U32 current_buf_id;
+    //printk(KERN_INFO "zz communicate.c communicate_conf() line 51\n");
+	// Enable the flag effect.
+	HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, dam_ctrl_val);
+	dam_ctrl_val |= (0x3 << 28);
+	HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, dam_ctrl_val);
+
+	// Disable the current buf (if exist) and enable the new buf 
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, buf_ena_val);
+	current_buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c communicate_conf() 60 current_buf_id=0x%08x\n",
+    //         current_buf_id);
+	if (INVALID_BUF_ID != current_buf_id) {
+		// current buf shall be empty
+		/*
+		   HAL_READ_UINT32(L2_STATUS1, buf_status);
+		   if ((buf_status & (0xf<<(4*current_buf_id))) != 0)
+		   printk("warning: L2 buf%d not empty when switch to another\n", current_buf_id);
+		 */
+		//printk(KERN_INFO "zz communicate.c communicate_conf() 69\n");
+		set_buf_stat_empty(current_buf_id);
+		buf_ena_val &= ~(1 << (16 + current_buf_id));
+	}
+	buf_ena_val |= (1 << (16 + buf_id));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, buf_ena_val);
+    //printk(KERN_INFO "zz communicate.c communicate_conf() 75 L2_BLOCK_DMA_CONF:0x%8x=0x%08x\n",
+     //              L2_BLOCK_DMA_CONF, buf_ena_val);
+
+	if (dev_type <= DAC) {
+		// set the Buf Id for the peripheral dev
+		HAL_READ_UINT32(L2_BUF_ID_CONF, buf_id_val);
+		buf_id_val &= (~(0x7 << (dev_type * 3)));
+		buf_id_val |= (buf_id << (dev_type * 3));
+		HAL_WRITE_UINT32(L2_BUF_ID_CONF, buf_id_val);
+        //printk(KERN_INFO "zz communicate.c communicate_conf() 84 L2_BUF_ID_CONF:0x%8x=0x%08x\n",
+        //         L2_BUF_ID_CONF, buf_id_val);
+	} else {
+		// set the BUF ID for SPI2 or gps
+		HAL_READ_UINT32(L2_BUF2_ID_CONF, buf_id_val);
+		buf_id_val &= (~(0x7 << ((dev_type - SPI2_RECE) * 3)));
+		buf_id_val |= (buf_id << ((dev_type - SPI2_RECE) * 3));
+		HAL_WRITE_UINT32(L2_BUF2_ID_CONF, buf_id_val);
+	}
+
+	// clear the buf
+	set_buf_stat_empty(buf_id);
+
+	return AK_TRUE;
+}
+
+/*********************************************************************
+Function:       prepare_dat_send_cpu
+Description:    use CPU MODE to prepare the data to be sent
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_status;
+	T_U32 align_4_len, len_remian_4;
+	T_U32 buf_addr;
+	T_U32 *p_buf_int;
+	T_U32 i;
+	T_U32 tmp;
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 117\n");
+	if (len > 512) {
+		return 0;
+	}
+
+	align_4_len = (len & (~0x3));
+	len_remian_4 = (len % 4);
+
+	buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 126 buf_id=%d\n", buf_id);;
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+	//set_buf_stat_empty((GLOBE_BUF_ID)buf_id);
+
+	// wait till buffer empty
+	do {
+		HAL_READ_UINT32(L2_STATUS1, buf_status);
+        //printk(KERN_INFO "zz communicate.c prepare_dat_send_cpu() 133 L2_STATUS1:0x%08x=0x%08x\n",
+         //      L2_STATUS1, buf_status);
+	} while ((buf_status & (0xf << (4 * buf_id))) != 0);
+
+	if (((T_U32) buf % 4) == 0)	// if the buf is the even then it can 4 bytes write.
+	{
+		p_buf_int = (T_U32 *) buf;
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//tmp = *(p_buf_int++);
+			//WriteBuf(buf_addr+i, tmp);
+			*(volatile T_U32 *)(buf_addr + i) = *(p_buf_int++);
+		}
+		if (len_remian_4 != 0) {
+			tmp = 0;
+			for (i = 0; i < len_remian_4; i++) {
+				tmp = tmp + (buf[align_4_len + i] << (i * 8));
+			}
+			//WriteBuf(buf_addr+align_4_len, tmp);
+			*(volatile T_U32 *)(buf_addr + align_4_len) = tmp;
+		}
+	}
+
+	else			// if the buf is the odd then it can't 4 bytes write.
+	{
+		for (i = 0; i < align_4_len; i = i + 4) {
+			tmp =
+			    (buf[i] | (buf[i + 1] << 8) | (buf[i + 2] << 16) |
+			     (buf[i + 3] << 24));
+			//WriteBuf(buf_addr+i, tmp);
+			*(volatile T_U32 *)(buf_addr + i) = tmp;
+		}
+		tmp = 0;
+		if (len_remian_4 != 0) {
+			for (i = 0; i < len_remian_4; i++) {
+				tmp = tmp + (buf[align_4_len + i] << (i * 8));
+			}
+			//WriteBuf(buf_addr+align_4_len, tmp);
+			*(volatile T_U32 *)(buf_addr + align_4_len) = tmp;
+		}
+	}
+
+	//increase buf status
+	if ((len % 64) && ((len % 64) <= 60)) {
+		*(volatile T_U32 *)(buf_addr + (len & (~0x3f)) + 0x3c) = 0;
+	}
+
+	return 1;
+}
+
+/*********************************************************************
+Function:       rece_dat_cpu
+Description:    use CPU MODE to receive the data from L2 buf
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_status;	//, buf_config;
+	T_U32 align_4_len, len_remian_4;
+	T_U32 buf_addr;
+	T_U32 *p_buf_int;
+	T_U32 i;
+	T_U32 tmp;
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 190\n");
+	if (len > 512) {
+		//printk("error: L2 read too long\n");
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 197 buf_id=%d\n", buf_id);
+	buf_addr = (T_U32)(L2_BUF_MEM_BASE_ADDR + buf_id * 512);
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 205 buf_addr=0x%08x\n", buf_addr);
+	align_4_len = (len & (~0x3));
+	len_remian_4 = (len % 4);
+
+	// wait till 64-byte-aligned data have all been received
+	do {
+		HAL_READ_UINT32(L2_STATUS1, buf_status);
+        //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 206 L2_STATUS1=0x%8x buf_status=0x%8x\n",
+         //     L2_STATUS1, buf_status);
+	} while (((buf_status >> (4 * buf_id)) & 0xf) < (len >> 6));
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 209\n");
+	if (((T_U32) buf % 4) == 0)	// if the buf is the even then it can 4 bytes write.
+	{
+		p_buf_int = (T_U32 *) buf;
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//*(p_buf_int++)  = ReadBuf(buf_addr+i);
+			*(p_buf_int++) = *(volatile T_U32 *)(buf_addr + i);
+		}
+		if (len_remian_4 != 0) {
+			//tmp = ReadBuf(buf_addr+align_4_len);
+			tmp = *(volatile T_U32 *)(buf_addr + align_4_len);
+			for (i = 0; i < len_remian_4; i++) {
+				buf[align_4_len + i] = (tmp >> (8 * i)) & 0xff;
+			}
+		}
+	}
+
+	else			// if the buf is the odd then it can't 4 bytes write.
+	{
+		for (i = 0; i < align_4_len; i = i + 4) {
+			//tmp = ReadBuf(buf_addr+i);
+			tmp = *(volatile T_U32 *)(buf_addr + i);
+
+			buf[i] = (tmp & 0xff);
+			buf[i + 1] = ((tmp >> 8) & 0xff);
+			buf[i + 2] = ((tmp >> 16) & 0xff);
+			buf[i + 3] = ((tmp >> 24) & 0xff);
+		}
+
+		if (len_remian_4 != 0) {
+			//tmp = ReadBuf(buf_addr + align_4_len);
+			tmp = *(volatile T_U32 *)(buf_addr + align_4_len);
+			for (i = 0; i < len_remian_4; i++) {
+				buf[align_4_len + i] = (tmp >> (8 * i)) & 0xff;
+			}
+		}
+	}
+    //printk(KERN_INFO "zz communicate.c rece_dat_cpu() line 243\n");
+	return 1;
+}
+
+/*********************************************************************
+Function:       prepare_dat_send_dma
+Description:    use DMA MODE to prepare the data to be sent
+Input:    	  buf :			data buffer
+len :			len < 512
+dev_type :	the peripheral type
+Return:         0 : failed  1:  ok
+ **********************************************************************/
+T_U8 prepare_dat_send_dma(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 dma_conf, frac_dma_conf, buf_status;
+	T_U32 align_64_len, len_remian_64;
+	T_U32 buf_addr;
+    //printk(KERN_INFO "zz communicate.c prepare_dat_send_dma() line 261\n");
+	if ((len > 2048) || (len == 0)) {
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+	if (INVALID_BUF_ID == buf_id) {
+		//printk("ERROR: L2 buf not assigned, dev_type = %d\n", dev_type);
+		return 0;
+	}
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+
+	//set_buf_stat_empty((GLOBE_BUF_ID)buf_id);
+
+	align_64_len = (len >> 6);	//        len / 64
+	len_remian_64 = (len % 64);	//                len % 64
+
+	// enable buf, enable buf dma function, set DMA direction
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+	dma_conf |=
+	    ((1 << buf_id) | (1 << (16 + buf_id)) | (1 << (8 + buf_id)));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+
+	//Config the L2 DMA to transfer the data of 64 align
+	if (align_64_len) {
+		// config the dma addr and count
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_ADDR_CONF + buf_id * 4,
+				 ((T_U32) buf & 0xfffffff));
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_COUNT_CONF + buf_id * 4,
+				 align_64_len);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | (1 << (24 + buf_id)));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while (dma_conf & (1 << (24 + buf_id)));
+	}
+	// Config the L2 DMA to transfer the data of fraction data
+	if (len_remian_64) {
+		const T_U8 *fdma_buf = buf + align_64_len * 64;	// RAM address
+		T_U32 fdma_len = len_remian_64;	// data length
+
+		// chip bug
+		if (fdma_len & 1)	// len is odd
+		{
+			fdma_len++;
+		}
+		// Config the direction, fraction data base addr , fdma len
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf &= (~0xffff);
+		dma_conf |=
+		    (((buf_id * 512 / 64 +
+		       (align_64_len %
+			(512 /
+			 64))) << 1) | FRAC_DMA_DIRECT_WRITE | ((fdma_len -
+								 1) << 10));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		// Config the fraction dma addr
+		HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+		frac_dma_conf &= ~0xfffffff;
+		frac_dma_conf |= ((T_U32) fdma_buf) & 0xfffffff;
+		HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+
+		// wait till buffer is not full
+		do {
+			HAL_READ_UINT32(L2_STATUS1, buf_status);
+		} while (((buf_status >> (4 * buf_id)) & 0xf) == 8);
+
+		//start the fdma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | FRAC_DMA_START_REQ);
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & FRAC_DMA_START_REQ) == FRAC_DMA_START_REQ);
+
+		//increase buf status
+		if (len_remian_64 <= 64 - 4) {
+			*(volatile T_U32 *)(buf_addr +
+					    ((align_64_len * 64) % 512) +
+					    0x3c) = 0;
+		}
+	}
+
+	return 1;
+}
+
+T_U8 rece_data_dma(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 align_64_len, len_remian_64;
+	T_U32 dma_conf, frac_dma_conf;	//, buf_status;
+	T_U32 buf_addr;
+    //printk(KERN_INFO "zz communicate.c rece_data_dma() line 358\n");
+	if ((len > 2048) || (len == 0)) {
+		return 0;
+	}
+
+	buf_id = get_buf_id(dev_type);
+	if (INVALID_BUF_ID == buf_id) {
+		//printk("ERROR: L2 buf not assigned, dev_type = %d\n", dev_type);
+		return 0;
+	}
+	buf_addr = (T_U32) L2_BUF_MEM_BASE_ADDR + buf_id * 512;
+
+	align_64_len = (len >> 6);	//        len / 64
+	len_remian_64 = (len % 64);	//                len % 64
+
+	// enable buf, enable buf dma function, set DMA direction
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+	dma_conf &= (~(1 << (8 + buf_id)));
+	dma_conf |= ((1 << buf_id) | (1 << (16 + buf_id)));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, dma_conf);
+
+	//Config the L2 DMA to transfer the data of 64 align
+	if (align_64_len) {
+		// config the dma addr and count
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_ADDR_CONF + buf_id * 4,
+				 ((T_U32) buf & 0xfffffff));
+		HAL_WRITE_UINT32(L2_DMA_BLOCK_COUNT_CONF + buf_id * 4,
+				 align_64_len);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | (1 << (24 + buf_id)));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & (1 << (24 + buf_id))) ==
+			 (1 << (24 + buf_id)));
+	}
+	// *******************         NOTE:              *****************************
+	// **** L2 alone do NOT know whether the rest of data have all been received from peripheral.
+	// **** It is the peripheral driver that should make sure.
+
+	// Config the L2 Fraction DMA to transfer the rest of data
+	if (len_remian_64) {
+		// Config the direct and fraction data base addr
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf &= (~0xffff);
+		dma_conf |=
+		    (((buf_id * 512 / 64 +
+		       (align_64_len %
+			(512 /
+			 64))) << 1) | FRAC_DMA_DIRECT_READ | ((len_remian_64 -
+								1) << 10));
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		// Config the fraction dma addr and count
+		HAL_READ_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+		frac_dma_conf &= ~0xfffffff;
+		frac_dma_conf |=
+		    ((T_U32) (buf + align_64_len * 64) & 0xfffffff);
+		HAL_WRITE_UINT32(L2_FRACTIOIN_DMA_CONF, frac_dma_conf);
+
+		//start the dma
+		HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		dma_conf |= (L2_DMA_ENABLE | FRAC_DMA_START_REQ);
+		HAL_WRITE_UINT32(L2_DMA_CRTL, dma_conf);
+
+		do {
+			HAL_READ_UINT32(L2_DMA_CRTL, dma_conf);
+		} while ((dma_conf & FRAC_DMA_START_REQ) == FRAC_DMA_START_REQ);
+	}
+
+	return 1;
+}
+
+/*********************************************************************
+Function:       get_buf_id
+Description:    get the perpheral's correspond buf ID.
+Input:    	  dev_type :	the peripheral type
+Return:         BUF ID
+**********************************************************************/
+static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id;
+	T_U32 buf_en;
+    //printk(KERN_INFO "zz communicate.c get_buf_id() line 443\n");
+	//get the buf id
+	if (dev_type <= DAC) {
+		HAL_READ_UINT32(L2_BUF_ID_CONF, buf_id);
+		buf_id = ((buf_id >> (dev_type * 3)) & 0x7);
+		// to see if the buf is enabled
+		HAL_READ_UINT32(L2_BLOCK_DMA_CONF, buf_en);
+        //printk(KERN_INFO "zz communicate.c get_buf_id() 460 L2_BLOCK_DMA_CONF:0x%08x=0x%08x\n", 
+         //      L2_BLOCK_DMA_CONF,buf_en);
+		if ((buf_en & (1 << (buf_id + 16))) == 0) {
+			buf_id = INVALID_BUF_ID;
+		}
+	} else {
+		HAL_READ_UINT32(L2_BUF2_ID_CONF, buf_id);
+		buf_id = ((buf_id >> ((dev_type - SPI2_RECE) * 3)) & 0x7);
+	}
+    //printk(KERN_INFO "zz communicate.c get_buf_id() 468 return buf_id=%d\n", buf_id);
+	return buf_id;
+}
+
+/*********************************************************************
+Function:       set_buf_stat_empty
+Description:    set the buf to empty stat
+Input:    	  dev_id :	the peripheral type
+ *********************************************************************/
+void set_buf_stat_empty(GLOBE_BUF_ID buf_id)
+{
+	T_U32 flag_conf;
+    //printk(KERN_INFO "zz communicate.c set_buf_stat_empty() line 469\n");
+	HAL_READ_UINT32(L2_BLOCK_DMA_CONF, flag_conf);
+	flag_conf |= (1 << (buf_id + 24));
+	HAL_WRITE_UINT32(L2_BLOCK_DMA_CONF, flag_conf);
+}
+
+/*********************************************************************
+Function:       set_buf_empty
+Description:    set the buf to empty stat
+Input:    	  PERIPHERAL_TYPE dev_type
+ **********************************************************************/
+void set_buf_empty(PERIPHERAL_TYPE dev_type)
+{
+	T_U32 buf_id = get_buf_id(dev_type);
+    //printk(KERN_INFO "zz communicate.c set_buf_empty() line 483\n");
+	set_buf_stat_empty((GLOBE_BUF_ID) buf_id);
+}
+
diff --git a/drivers/mtd/nand/ak98-nand/communicate.h b/drivers/mtd/nand/ak98-nand/communicate.h
new file mode 100644
index 00000000000..5531b4a4e8a
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/communicate.h
@@ -0,0 +1,64 @@
+#ifndef _COMMUNICATE_H_
+#define _COMMUNICATE_H_
+
+//#include "AK3220_types.h"
+#ifndef _AK3220_TYPES_H_
+#define _AK3220_TYPES_H_
+
+/* preliminary type definition for global area */
+typedef unsigned char T_U8;	/* unsigned 8 bit integer */
+typedef unsigned short T_U16;	/* unsigned 16 bit integer */
+typedef unsigned long T_U32;	/* unsigned 32 bit integer */
+typedef signed char T_S8;	/* signed 8 bit integer */
+typedef signed short T_S16;	/* signed 16 bit integer */
+typedef signed long T_S32;	/* signed 32 bit integer */
+typedef void T_VOID;		/* void */
+
+#define HAL_READ_UINT32(reg, val)      ((val) = *((volatile unsigned long *)(reg)))
+#define HAL_WRITE_UINT32(reg, val)     (*((volatile  unsigned long *)(reg)) = (val))
+
+#define AK_FALSE                                0
+#define AK_TRUE                                 1
+//#define AK_NULL                                 ((T_VOID*)0)
+#endif
+
+typedef enum {
+	GLOBE_BUF0 = 0,
+	GLOBE_BUF1,
+	GLOBE_BUF2,
+	GLOBE_BUF3,
+	GLOBE_BUF4,
+	GLOBE_BUF5,
+	GLOBE_BUF6,
+	GLOBE_BUF7
+} GLOBE_BUF_ID;
+
+typedef enum {
+	USB_BULK_SEND,
+	USB_BULK_RECE,
+	USB_ISO,
+	NAND_FLASH,
+	MMC_SD1,
+	MMC_SD2,
+	MMC_SD3,
+	SPI1_RECE,
+	SPI1_SEND,
+	DAC,
+	SPI2_RECE,
+	SPI2_SEND,
+	GPS
+} PERIPHERAL_TYPE;
+
+//static T_U32 get_buf_id(PERIPHERAL_TYPE dev_type);
+#define INVALID_BUF_ID 0xFFFFFFFF
+
+T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id);
+T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len,
+			  PERIPHERAL_TYPE dev_type);
+T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+T_U8 prepare_dat_send_dma(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+T_U8 rece_data_dma(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);
+void set_buf_stat_empty(GLOBE_BUF_ID buf_id);
+void set_buf_empty(PERIPHERAL_TYPE dev_type);
+
+#endif
diff --git a/drivers/mtd/nand/ak98-nand/nand_char.c b/drivers/mtd/nand/ak98-nand/nand_char.c
new file mode 100755
index 00000000000..bb069874ee7
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/nand_char.c
@@ -0,0 +1,742 @@
+/**
+ * @filename nand_char.c
+ * @brief AK880x nandflash char device driver
+ * Copyright (C) 2010 Anyka (Guangzhou) Software Technology Co., LTD
+ * @author zhangzheng
+ * @modify 
+ * @date 2010-10-20
+ * @version 1.0
+ * @ref Please refer to
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/cdev.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <asm/uaccess.h>
+#include <linux/mtd/partitions.h>
+#include <mtd/mtd-abi.h>
+#include <mach-anyka/nand_list.h>
+#include <mach-anyka/fha.h>
+#include "arch_nand.h"
+#include "nand_control.h"
+#include "wrap_nand.h"
+#include <linux/gpio.h>
+#include <mach/clock.h>
+#include "anyka_cpu.h"
+
+#define NAND_CHAR_MAJOR                 168
+#define AK_NAND_PHY_ERASE               0xa0
+#define AK_NAND_PHY_READ                0xa1
+#define AK_NAND_PHY_WRITE               0xa2
+#define AK_NAND_GET_CHIP_ID             0xa3
+#define AK_MOUNT_MTD_PART               0xa4
+#define AK_NAND_READ_BYTES              0xa5
+#define AK_GET_NAND_PARA                0xa6
+
+#ifdef CONFIG_MTD_NAND_TEST
+#define AK_GET_ERASE_BLOCK_NUM          0xa7
+#define AK_SET_POWER_STAT               0xa8
+#define AK_GET_POWER_STAT               0xa9
+#define AK_SET_POWER_ONOFF              0xaa
+#define AK_MMC_INSERT                   0xab
+#define AK_MMC_PULLOUT                  0xac
+#endif
+
+
+
+#define NAND_BOOT0_DATA_SIZE            472
+
+
+#define ZZ_DEBUG                        0
+
+extern T_NAND_PHY_INFO *g_pNand_Phy_Info;
+extern T_PNandflash_Add g_pNF;
+extern T_PFHA_INIT_INFO g_pinit_info;
+extern T_PFHA_LIB_CALLBACK g_pCallback;
+
+static int nand_char_open(struct inode *inode, struct file *filp);
+static int nand_char_close(struct inode *inode, struct file *filp);
+static int nand_char_ioctl(struct inode *inode, struct file *filp,
+		     unsigned int cmd, unsigned long arg);
+
+struct erase_para
+{
+    uint32_t chip_num;
+    uint32_t startpage;
+};
+
+struct rw_para
+{
+    T_U32 chip_num;
+    T_U32 page_num;
+    T_U8 *data;
+    T_U32 data_len;
+    T_U8 *oob;
+    T_U32 oob_len;
+	T_U32 eDataType;
+};
+
+struct rbytes_para
+{
+	T_U32 chip_num; 
+	T_U32 row_addr; 
+	T_U32 clm_addr; 
+	T_U8 *data;
+	T_U32 data_len;
+};
+
+struct get_id_para
+{
+    uint32_t chip_num;
+    uint32_t *nand_id;
+};
+
+static struct nand_char_dev
+{
+    struct cdev c_dev;
+}nand_c_dev;
+
+extern struct mtd_info *g_master;
+
+static int nand_c_major = NAND_CHAR_MAJOR;
+
+static const struct file_operations nand_char_fops =
+{
+    .owner   = THIS_MODULE,
+    .open    = nand_char_open,
+    .release = nand_char_close,
+    .ioctl   = nand_char_ioctl
+};
+
+static int nand_char_open(struct inode *inode, struct file *filp)
+{
+    filp->private_data = &nand_c_dev;
+	#if ZZ_DEBUG
+    printk(KERN_NOTICE "hy nand_char.c nand_char_open() ######\n");
+	#endif
+    return 0;
+}
+
+static int nand_char_close(struct inode *inode, struct file *filp)
+{
+	#if ZZ_DEBUG
+    printk(KERN_NOTICE "zz nand_char.c nand_char_close() 112\n");
+	#endif
+    return 0;
+}
+
+/**
+ * @brief Get Nand parameter.
+ * 
+ * @author Hanyang
+ * @date 2011-04-29
+ * @param arg[in]  struct T_NAND_PHY_INFO pointer including nand info from the userspace.
+ * @return int
+ * @retval  1: fail   0: success
+ */
+static int nand_GetNandPara_Handle(unsigned long arg)
+{
+    g_pNand_Phy_Info = kmalloc(sizeof(T_NAND_PHY_INFO), GFP_KERNEL);
+    if(g_pNand_Phy_Info == NULL)
+    {
+        printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 410 g_pNand_Phy_Info==NULL Error!!!\n");
+        return 1;
+    }
+    copy_from_user(g_pNand_Phy_Info, (T_NAND_PHY_INFO *)arg, sizeof(T_NAND_PHY_INFO));
+    g_pNF = kmalloc(sizeof(T_Nandflash_Add), GFP_KERNEL);
+    if(g_pNF == NULL)
+    {
+        printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 417 g_pNF==NULL Error!!!\n");
+        return 1;
+    }
+    
+    g_pNF->RowCycle      = g_pNand_Phy_Info->row_cycle;
+    g_pNF->ColCycle      = g_pNand_Phy_Info->col_cycle;
+    g_pNF->PageSize      = g_pNand_Phy_Info->page_size;
+    g_pNF->PagesPerBlock = g_pNand_Phy_Info->page_per_blk;
+    g_pNF->EccType       = (T_U8)((g_pNand_Phy_Info->flag & 0xf0) >> 4);  //4-7 bit is ecc type
+    
+    switch(g_pNand_Phy_Info->page_size)
+    {
+        case 512:
+        {
+            g_pNF->ChipType = NAND_512B_PAGE;
+            break;
+        }
+        case 2048:
+        {
+            g_pNF->ChipType = NAND_2K_PAGE;
+            break;
+        }
+        case 4096:
+        {
+            g_pNF->ChipType = NAND_4K_PAGE;
+            break;
+        }   
+        case 8192:
+        {
+            g_pNF->ChipType = NAND_8K_PAGE;
+            break;
+        }
+        default:
+        {
+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 451 globle g_pNF->ChipType is error!!!\n");
+        }
+    }
+
+	/* Set Clock From 84MHz To Currently ASIC Freq */
+	nand_calctiming(g_pNand_Phy_Info->data_len);
+	nand_changetiming(ak98_get_asic_clk());
+
+    printk(KERN_INFO "----------------------zz nand_char.c nand_char_ioctl() 456-----------------------\n");
+    printk(KERN_INFO "----------------------------Nand Physical Parameter------------------------------\n");
+    printk(KERN_INFO "chip_id = 0x%08lx\n", g_pNand_Phy_Info->chip_id);
+    printk(KERN_INFO "page_size = %d\n", g_pNand_Phy_Info->page_size);
+    printk(KERN_INFO "page_per_blk = %d\n", g_pNand_Phy_Info->page_per_blk);
+    printk(KERN_INFO "blk_num = %d\n", g_pNand_Phy_Info->blk_num);
+    printk(KERN_INFO "group_blk_num = %d\n", g_pNand_Phy_Info->group_blk_num);
+    printk(KERN_INFO "plane_blk_num = %d\n", g_pNand_Phy_Info->plane_blk_num);
+    printk(KERN_INFO "spare_size = %d\n", g_pNand_Phy_Info->spare_size);
+    printk(KERN_INFO "col_cycle = %d\n", g_pNand_Phy_Info->col_cycle);
+    printk(KERN_INFO "lst_col_mask = %d\n", g_pNand_Phy_Info->lst_col_mask);
+    printk(KERN_INFO "row_cycle = %d\n", g_pNand_Phy_Info->row_cycle);
+    printk(KERN_INFO "delay_cnt = %d\n", g_pNand_Phy_Info->delay_cnt);
+    printk(KERN_INFO "custom_nd = %d\n", g_pNand_Phy_Info->custom_nd);
+    printk(KERN_INFO "flag = 0x%08lx\n", g_pNand_Phy_Info->flag);
+    printk(KERN_INFO "cmd_len = 0x%lx\n", g_pNand_Phy_Info->cmd_len);
+    printk(KERN_INFO "data_len = 0x%lx\n", g_pNand_Phy_Info->data_len);
+    printk(KERN_INFO "---------------------------------------------------------------------------------\n");
+
+    return 0;
+}
+
+/**
+ * @brief :Read from nand.
+ * 
+ * @author Hanyang
+ * @date 2011-04-29
+ * @param arg[in] struct rw_para pointer including nand para info from the userspace.
+ * @return int
+ * @retval  1: fail   0: success
+ */
+static int nand_PhyRead_Handle(unsigned long arg)
+{
+    struct rw_para r_para;
+    T_NAND_ECC_STRU data_ctrl;
+    T_NAND_ECC_STRU spare_ctrl;
+    T_U8 oob_buf[32];
+    T_U32 boot_page_size = 0;
+   
+    if(g_pNF == NULL)
+    {
+#if ZZ_DEBUG
+       printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 155 g_pNF==NULL\n");
+#endif
+       return 1;
+    }
+    copy_from_user(&r_para, (struct rw_para*)arg, sizeof(struct rw_para));
+#if ZZ_DEBUG
+    printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 161 AK_NAND_PHY_READ\n");
+    printk(KERN_INFO "Read chip_num=%lu page_num=%lu data_len=%lu oob_len=%lu eDataType=%d\n",
+          r_para.chip_num,
+          r_para.page_num,
+          r_para.data_len,
+          r_para.oob_len,
+          r_para.eDataType);
+#endif
+
+    if(r_para.eDataType == FHA_DATA_BOOT)
+    {               
+       boot_page_size = (r_para.data_len > 4096) ? 4096 : r_para.data_len;
+       
+       if (0 == r_para.page_num)
+       {
+           data_ctrl.buf = kmalloc(NAND_BOOT0_DATA_SIZE, GFP_KERNEL);
+           data_ctrl.buf_len = NAND_BOOT0_DATA_SIZE;
+           data_ctrl.ecc_section_len = NAND_BOOT0_DATA_SIZE;
+           data_ctrl.ecc_type = ECC_32BIT_P1KB;                 
+                                
+       }
+       else
+       {                    
+           data_ctrl.buf = kmalloc(boot_page_size, GFP_KERNEL);
+           data_ctrl.buf_len = boot_page_size;
+           data_ctrl.ecc_section_len = 512;
+           data_ctrl.ecc_type = g_pNF->EccType;           
+       }
+       
+       nand_readpage_ecc(0, r_para.page_num, 0, g_pNF, &data_ctrl, AK_NULL);
+       copy_to_user(((struct rw_para *)arg)->data, data_ctrl.buf, data_ctrl.buf_len);
+       kfree(data_ctrl.buf);
+       return 0;
+       
+    }
+    else
+    {
+      /*
+      Nand_Config_Data(&data_ctrl,
+                        kmalloc(r_para.data_len, GFP_KERNEL),
+                        r_para.data_len, 
+                        g_pNF->EccType
+                        );
+       Nand_Config_Spare(&spare_ctrl, oob_buf, r_para.oob_len, g_pNF->EccType);
+	*/       
+	Nand_Config_Data_Spare(&data_ctrl,
+          		kmalloc(r_para.data_len, GFP_KERNEL),
+               	r_para.data_len, 
+               	g_pNF->EccType,
+           		&spare_ctrl, 
+          		oob_buf, 
+               	r_para.oob_len
+                	);
+       nand_readpage_ecc(r_para.chip_num, r_para.page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);
+    }   
+
+    copy_to_user(((struct rw_para *)arg)->data, data_ctrl.buf, data_ctrl.buf_len);
+    copy_to_user(((struct rw_para *)arg)->oob, spare_ctrl.buf, r_para.oob_len);
+
+    kfree(data_ctrl.buf);
+    return 0;
+}
+
+static int nand_PhyWrite_Handle(unsigned long arg)
+{
+    struct rw_para w_para;
+    T_NAND_ECC_STRU data_ctrl;
+    T_NAND_ECC_STRU spare_ctrl;
+    unsigned char oob_buf[32];
+    T_U32 boot_page_size = 0;
+       
+    if(g_pNF == NULL)
+    {
+    #if ZZ_DEBUG
+        printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 220 g_pNF==NULL\n");
+    #endif
+        return 1;
+    }
+    copy_from_user(&w_para, (struct rw_para *)arg, sizeof(struct rw_para));
+#if ZZ_DEBUG
+    printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 226 AK_NAND_PHY_WRITE\n");
+    printk(KERN_INFO "Write chip_num=%d page_num=%d data_len=%d oob_len=%d eDataType=%d\n",
+           w_para.chip_num,
+           w_para.page_num,
+           w_para.data_len,
+           w_para.oob_len,
+           w_para.eDataType);
+#endif
+
+    if(w_para.eDataType == FHA_DATA_BOOT)
+    {
+        boot_page_size = (w_para.data_len > 4096) ? 4096 : w_para.data_len;
+        
+        if (0 == w_para.page_num)
+        {
+            data_ctrl.buf = kmalloc(NAND_BOOT0_DATA_SIZE, GFP_KERNEL);
+            data_ctrl.buf_len = NAND_BOOT0_DATA_SIZE;
+            data_ctrl.ecc_section_len = NAND_BOOT0_DATA_SIZE;
+            data_ctrl.ecc_type = ECC_32BIT_P1KB;
+        }
+        else
+        {                    
+            data_ctrl.buf = kmalloc(boot_page_size, GFP_KERNEL);
+            data_ctrl.buf_len = boot_page_size;
+            data_ctrl.ecc_section_len = 512;
+            data_ctrl.ecc_type = g_pNF->EccType;
+        }
+
+         if(data_ctrl.buf != NULL)
+         {
+             copy_from_user(data_ctrl.buf, ((struct rw_para *)arg)->data, data_ctrl.buf_len);        
+         }
+         else
+         {
+             printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 276 data_ctrl.buf == NULL error!!!\n");
+             return AK_FALSE;
+         }
+
+         nand_writepage_ecc(0, w_para.page_num, 0, g_pNF, &data_ctrl, AK_NULL); 
+		
+         kfree(data_ctrl.buf);     
+         return 0;			
+        
+    }
+    else
+    {
+    	/*
+        Nand_Config_Data(&data_ctrl, 
+                         kmalloc(w_para.data_len, GFP_KERNEL), 
+                         w_para.data_len, 
+                         g_pNF->EccType
+                         );
+        Nand_Config_Spare(&spare_ctrl, oob_buf, w_para.oob_len, g_pNF->EccType);
+	*/
+	Nand_Config_Data_Spare(&data_ctrl, 
+               	kmalloc(w_para.data_len, GFP_KERNEL), 
+                    	w_para.data_len, 
+                    	g_pNF->EccType,
+			&spare_ctrl, 
+			oob_buf, 
+			w_para.oob_len
+    			);
+    }   
+	
+    if(data_ctrl.buf != NULL)
+    {
+        copy_from_user(data_ctrl.buf, ((struct rw_para *)arg)->data, data_ctrl.buf_len);
+        copy_from_user(spare_ctrl.buf, ((struct rw_para *)arg)->oob, spare_ctrl.buf_len);
+    }
+    else
+    {
+        printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 276 data_ctrl.buf == NULL error!!!\n");
+        return 1;
+    }
+	
+    nand_writepage_ecc(w_para.chip_num, w_para.page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);    
+	
+    kfree(data_ctrl.buf);
+    return 0;
+}
+
+/**
+ * @brief :Mount nand partitions according to burntool's partition info .
+ * 
+ * @author Hanyang
+ * @date 2011-04-29
+ * @param  void.
+ * @return int
+ * @retval  1: fail   0: success
+ */
+static int nand_MountMtdPart_Handle(void)
+{
+    int retval = 0;
+	T_U32 part_cnt = 0;
+	int i = 0;
+	T_U8 *fs_info = NULL;
+	struct partitions *parts = NULL;
+	struct mtd_partition *pmtd_part = NULL;
+	
+	retval = init_fha_lib();        //initialize fha lib
+	
+    printk(KERN_INFO "555 wrap_nand.c init_fha_lib() g_pinit_info=%p,g_pCallback=%p \n",g_pinit_info,g_pCallback);
+	if(retval == FHA_SUCCESS)
+	{
+		if(g_pNF == NULL)
+		{
+			printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 316 g_pNF == NULL error!!!\n");
+			return 1;
+		}
+		fs_info = kmalloc(g_pNF->PageSize, GFP_KERNEL);
+		retval = FHA_get_fs_part(fs_info, g_pNF->PageSize);
+		
+		#if ZZ_DEBUG
+		printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 323 FHA_get_fs_part() return %d\n", retval);
+		printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 324 test recieve data start------------------\n");
+		for(i=0; i<80; i++)
+		{	
+			if(i%10 == 0)
+			{
+				printk(KERN_INFO "\n");
+			}
+			printk(KERN_INFO "0x%02x\n", fs_info[i]);
+		}
+		printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 333 test recieve data end---------------------\n");
+		#endif
+		
+		part_cnt = *((int *)fs_info);  //calculate how many partitions
+		
+		if(part_cnt == 0)
+		{
+			printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 340 part_cnt==0 error!!!\n");
+			return 1;
+		}
+		
+		pmtd_part = kmalloc(sizeof(struct mtd_partition) * part_cnt, GFP_KERNEL);
+		
+		if(pmtd_part == NULL)
+		{
+			printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 348 pmtd_part==NULL error!!!\n");
+			return 1;
+		}
+		#if ZZ_DEBUG
+		printk(KERN_INFO "---------------zz nand_char.c nand_char_ioctl() 352 AK_MOUNT_MTD_PART mtd parts info start-------------\n");
+		#endif
+		
+		parts = (struct partitions *)(&fs_info[4]);
+		
+		for(i=0; i<part_cnt; i++)
+		{	
+			pmtd_part[i].name = kmalloc(MTD_PART_NAME_LEN, GFP_KERNEL);
+			memcpy(pmtd_part[i].name, (parts+i)->name, MTD_PART_NAME_LEN);
+			pmtd_part[i].size = parts[i].size;
+			pmtd_part[i].offset =  parts[i].offset;
+			pmtd_part[i].mask_flags = parts[i].mask_flags;
+			
+			#if 1
+			printk(KERN_INFO "pmtd_part[%d]:\nname = %s\nsize = 0x%llx\noffset = 0x%llx\nmask_flags = 0x%x\n\n", 
+			       i, 
+			       pmtd_part[i].name, 
+			       pmtd_part[i].size,
+			       pmtd_part[i].offset,
+			       pmtd_part[i].mask_flags);
+			#endif
+		}
+		
+		#if ZZ_DEBUG
+		printk(KERN_INFO "----------------zz nand_char.c nand_char_ioctl() 376 AK_MOUNT_MTD_PART mtd part info end-----------------\n");
+		#endif
+		nand_scan(g_master, 1);
+        printk(KERN_INFO "777 wrap_nand.c init_fha_lib() g_pinit_info=%p,g_pCallback=%p \n",g_pinit_info,g_pCallback);
+		add_mtd_partitions(g_master, (const struct mtd_partition *)pmtd_part, part_cnt);
+		
+		kfree(pmtd_part);
+		kfree(fs_info);
+	}
+	else
+	{
+		printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 386 AK_MOUNT_MTD_PART init fha lib failed!!!\n");
+	}
+    printk(KERN_INFO "666 wrap_nand.c init_fha_lib() g_pinit_info=%p,g_pCallback=%p\n",g_pinit_info,g_pCallback);
+
+	return 0;
+}
+
+/**
+ * @brief :Command Control interface for burntool .
+ * 
+ * @author Hanyang
+ * @date 2011-04-29
+ * @param  inode[in] nand char device inode.
+ * @param  filp[in] nand char file id.
+ * @param  cmd[in] burntool command.
+ * @param  arg[in] parameter from user.
+ * @return int
+ * @retval  1: fail   0: success
+ */
+static int nand_char_ioctl(struct inode *inode, struct file *filp,
+		                     unsigned int cmd, unsigned long arg)
+{
+    int ret = 0;
+    
+	#if ZZ_DEBUG
+    printk(KERN_INFO "zz nand_char.c nand_char_ioctl() : line %d cmd=0x%x\n", __LINE__, cmd);   
+	#endif
+    switch(cmd)
+    {
+        case AK_NAND_PHY_ERASE:
+        {
+            struct erase_para ep;
+			if(g_pNF == NULL)
+			{
+				#if ZZ_DEBUG
+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 131 g_pNF==NULL\n");
+				#endif
+				break;
+			}
+            copy_from_user(&ep, (struct erase_para *)arg, sizeof(struct erase_para));
+			#if ZZ_DEBUG
+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 137 AK_NAND_PHY_ERASE\n");
+            printk(KERN_INFO "erase chip_num = %d startpage = %d\n",
+                   ep.chip_num,
+                   ep.startpage);
+			#endif
+            nand_eraseblock(ep.chip_num, ep.startpage, g_pNF);           
+            ret = 0;
+            break;
+        }
+        case AK_NAND_PHY_READ:
+        {
+            ret = nand_PhyRead_Handle(arg);
+            break;
+        }
+        case AK_NAND_PHY_WRITE:
+        {
+            ret = nand_PhyWrite_Handle(arg);
+            break;
+        }
+        case AK_NAND_GET_CHIP_ID:
+        {
+            uint32_t nand_id = 0;
+            struct get_id_para gip;
+            copy_from_user(&gip, (struct get_id_para *)arg, sizeof(struct get_id_para));
+            nand_id = nand_read_chipID(gip.chip_num);
+            if (0xffffffff == nand_id)
+            {
+                ret = 1;
+            }
+            else
+            {
+                ret = 0;
+            }   
+            
+			#if ZZ_DEBUG
+            printk(KERN_INFO "zz nand_char.c nand_char_ioctl() 292 AK_NAND_GET_CHIP_ID\n");
+            printk(KERN_INFO "mtd_ioctl() chip_num=%d nand_id=0x%x\n", 
+                   gip.chip_num,
+                   nand_id);
+			#endif
+            copy_to_user(((struct get_id_para *)arg)->nand_id, &nand_id, 
+                           sizeof(nand_id));
+            break;  
+        }
+        case AK_MOUNT_MTD_PART:        
+			ret = nand_MountMtdPart_Handle();			
+		    break;
+        
+		case AK_NAND_READ_BYTES:            
+		{
+			struct rbytes_para rbp;
+			if(g_pNF == NULL)
+			{
+				printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 396 g_pNF==NULL Error!!!\n");
+				break;
+			}
+			copy_from_user(&rbp, (struct rbytes_para *)arg, sizeof(struct rbytes_para));
+			rbp.data = kmalloc(rbp.data_len, GFP_KERNEL);
+
+			nand_readbytes(rbp.chip_num, rbp.row_addr, rbp.clm_addr, g_pNF, rbp.data, rbp.data_len);
+			copy_to_user(((struct rbytes_para *)arg)->data, rbp.data, rbp.data_len);
+			break;
+		}
+		case AK_GET_NAND_PARA:
+		{
+			ret = nand_GetNandPara_Handle(arg);
+			break;
+		}
+
+	#ifdef CONFIG_MTD_NAND_TEST
+		case AK_GET_ERASE_BLOCK_NUM:
+		{
+			uint32_t blocknum = 0;
+			uint32_t count = 0;
+			copy_from_user(&blocknum, (uint32_t *)arg, sizeof(uint32_t));
+			//printk(" blocknum = %d\n", blocknum);
+			count = nand_get_erase_block_count(blocknum);
+			//printk(" count = %d\n", count);
+			copy_to_user((uint32_t *)arg, &count, sizeof(uint32_t));
+			break;
+		}
+		case AK_SET_POWER_STAT:
+		{
+			unsigned char stat = 1;
+			copy_from_user(&stat, (unsigned char *)arg, 1);
+			ak98_setpin_as_gpio(AK98_GPIO_114);
+			ak98_gpio_cfgpin(AK98_GPIO_114, AK98_GPIO_DIR_OUTPUT);
+			ak98_gpio_pullup(AK98_GPIO_114, AK98_PULLUP_ENABLE);
+			ak98_gpio_setpin(AK98_GPIO_114, stat);
+			break;
+		}
+		case AK_GET_POWER_STAT:
+		{
+			unsigned char stat;            
+			ak98_setpin_as_gpio(AK98_GPIO_114);
+			ak98_gpio_cfgpin(AK98_GPIO_114, AK98_GPIO_DIR_INPUT);
+			ak98_gpio_pullup(AK98_GPIO_114, AK98_PULLUP_ENABLE);
+			stat = ak98_gpio_getpin(AK98_GPIO_114);
+			copy_to_user((unsigned char *)arg, &stat, 1);
+			break;
+		}
+		case AK_SET_POWER_ONOFF:
+		{
+			ak98_setpin_as_gpio(AK98_GPIO_107);
+			ak98_gpio_cfgpin(AK98_GPIO_107, AK98_GPIO_DIR_OUTPUT);
+			ak98_gpio_pulldown(AK98_GPIO_107, AK98_PULLDOWN_ENABLE);
+			ak98_gpio_setpin(AK98_GPIO_107, 0);
+			mdelay(250);
+			ak98_gpio_setpin(AK98_GPIO_107, 1);
+			break;
+		}
+		case AK_MMC_INSERT:
+		{
+			ak98_setpin_as_gpio(AK98_GPIO_107);
+			ak98_gpio_cfgpin(AK98_GPIO_107, AK98_GPIO_DIR_OUTPUT);
+			ak98_gpio_pulldown(AK98_GPIO_107, AK98_PULLDOWN_ENABLE);
+			ak98_gpio_setpin(AK98_GPIO_107, 0);
+			break;
+		}
+		case AK_MMC_PULLOUT:
+		{
+			ak98_setpin_as_gpio(AK98_GPIO_107);
+			ak98_gpio_cfgpin(AK98_GPIO_107, AK98_GPIO_DIR_OUTPUT);
+			ak98_gpio_pulldown(AK98_GPIO_107, AK98_PULLDOWN_ENABLE);
+			ak98_gpio_setpin(AK98_GPIO_107, 1);
+			break;
+		}
+	#endif
+		
+	    default:
+        {   
+            return -EINVAL;
+        }
+    }
+    return ret;
+}
+
+static struct class *nand_class;
+
+static void nand_setup_cdev(void)
+{
+    int err = 0;
+    dev_t devno = MKDEV(nand_c_major, 0);
+
+    cdev_init(&(nand_c_dev.c_dev), &nand_char_fops);
+    nand_c_dev.c_dev.owner = THIS_MODULE;
+    nand_c_dev.c_dev.ops = &nand_char_fops;
+    err = cdev_add(&(nand_c_dev.c_dev), devno, 1);
+    if(err)
+    {
+        printk(KERN_NOTICE "Error %d adding anyka nand char dev\n", err);
+    }
+	
+	//automatic mknod device node
+	nand_class = class_create(THIS_MODULE, "nand_class");
+	device_create(nand_class, NULL, devno, &nand_c_dev, "nand_char");
+}
+
+static int __init nand_char_init(void)
+{
+    int result = 0;
+    dev_t devno = MKDEV(nand_c_major, 0);
+    if(nand_c_major)
+    {
+        result = register_chrdev_region(devno, 1, "anyka nand char dev");
+    }
+    else
+    {
+        result = alloc_chrdev_region(&devno, 0, 1, "anyka nand char dev");
+    }
+    if(result<0)
+    {
+        return result;
+    }
+    nand_setup_cdev();
+    
+	printk(KERN_INFO "Nand Char Device Initialize Successed!\n");
+    return 0;
+}
+                      
+static void __exit nand_char_exit(void)
+{
+	dev_t devno = MKDEV(nand_c_major, 0);
+	
+	//destroy device node
+	device_destroy(nand_class, devno);
+	class_destroy(nand_class); 
+	
+	//delete char device
+    cdev_del(&(nand_c_dev.c_dev));
+    unregister_chrdev_region(devno, 1);
+}
+                      
+module_init(nand_char_init);
+module_exit(nand_char_exit);            
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("ZhangZheng");
+MODULE_DESCRIPTION("Direct character-device access to Nand devices");
+
diff --git a/drivers/mtd/nand/ak98-nand/nand_control.c b/drivers/mtd/nand/ak98-nand/nand_control.c
new file mode 100755
index 00000000000..5c9dac69d41
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/nand_control.c
@@ -0,0 +1,2024 @@
+/**

+ * @filename nandflash.c

+ * @brief ak980x nandflash driver

+ * Copyright (C) 2006 Anyka (Guangzhou) Software Technology Co., LTD

+ * @author yiruoxiang

+ * @modify jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ * @ref Please refer to¡­

+ */

+#include <linux/kernel.h>

+#include <asm/delay.h>

+#include <mach-anyka/anyka_types.h>

+#include <asm/delay.h>

+#include <linux/slab.h>

+#include <linux/string.h>

+#include <linux/delay.h>

+#include <linux/dma-mapping.h>

+#include <mach/l2.h>

+#include <mach/gpio.h>

+#include "anyka_cpu.h"

+#include "arch_nand.h"

+#include "nand_control.h"

+#include "sysctl.h"

+

+#define READ_BUF	GLOBE_BUF4

+#define WRITE_BUF	GLOBE_BUF5

+

+#define NAND_L2_ENABLE	1	/* Define NAND_L2_ENABLE to use new L2 API(ak98_l2_*), undefine it to use old communicate.c API */

+//#undef NAND_L2_ENABLE

+

+#define ZZ_DEBUG        0

+

+#ifdef CONFIG_MTD_NAND_TEST

+extern T_U32 *nand_erase_test;

+extern T_U32 nand_total_blknum;

+#endif

+

+extern dma_addr_t dmahandle;

+extern void *bufaddr;

+

+

+//*****************************************************************************************

+static T_BOOL   nf_check_data_spare_separate(T_PNAND_ECC_STRU pDataCtrl, T_PNAND_ECC_STRU pSpareCtrl, T_U32 *cycle, T_U32 *effective_size, T_U32 *ecc_type);

+static T_U32    nf_get_ecccode_len(T_U32 ecc_type);

+static T_U8     nf_read_chipstatus(T_U32 Chip);

+static T_U32*   nf_send_addr(T_U32 *reg_addr, T_U32 columnAddr,T_U32 rowAddr, T_U32 col_cycle, T_U32 row_cycle);

+//static T_VOID   nf_controller_reset(T_VOID);

+static T_BOOL   check_cmd_done(T_VOID);

+static T_VOID   cmd_go(T_U32 Chip);

+static T_U8     nf_check_ecc_status(T_U32 stat);

+static T_U32    calc_new(T_U8 data_opt_len, T_U8 data_we_fe, T_U8 data_we_re, T_U8 data_re_fe, T_U8 data_re_re);

+static T_U32    ecc_repair(T_U32 wrong_info, T_U8 *main_buf, T_U8 *add_buf, T_U32 main_size, T_U32 add_size, T_U32 ecc_type);

+static T_U32    nf_check_repair_ecc(T_U8 *pMain_buf, T_U8 *pAdd_buf, T_U32 section_size, T_U32 add_len, T_U32 ecc_type, T_BOOL  bSeparate_spare);

+

+//*****************************************************************************************

+typedef enum {

+	USB_BULK_SEND,

+	USB_BULK_RECE,

+	USB_ISO,

+	NAND_FLASH,

+	MMC_SD1,

+	MMC_SD2,

+	MMC_SD3,

+	SPI1_RECE,

+	SPI1_SEND,

+	DAC,

+	SPI2_RECE,

+	SPI2_SEND,

+	GPS

+} PERIPHERAL_TYPE;

+

+typedef enum {

+	GLOBE_BUF0 = 0,

+	GLOBE_BUF1,

+	GLOBE_BUF2,

+	GLOBE_BUF3,

+	GLOBE_BUF4,

+	GLOBE_BUF5,

+	GLOBE_BUF6,

+	GLOBE_BUF7

+} GLOBE_BUF_ID;

+

+extern struct semaphore  nand_lock;

+

+extern T_U8 communicate_conf(PERIPHERAL_TYPE dev_type, GLOBE_BUF_ID buf_id);

+extern T_U8 rece_dat_cpu(T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);

+extern T_U8 prepare_dat_send_cpu(const T_U8 * buf, T_U32 len, PERIPHERAL_TYPE dev_type);

+

+//***************************************************************************************    

+#define MAX_LOOP_CNT       T_U32_MAX

+

+#define CAL_40M(n)   ((((n) - 1) >> 1) + 1)     //¼´Ê¹n£½0£¬Ò²»áËã³ö-1+1=0

+#define CAL_62M(n)   (((((n) * 3) - 1 ) >> 2) + 1)  // a >= (3*a_84 - 1)/4

+#define CAL_124M(n)  ((((n) * 3) >> 1) + 1)

+#define CAL_168M(n)  (((n) * 2) + 1)

+

+#define DEF_FRQ                     84

+#define CAL_TIM_LOW(freq, val)      (((freq) * (val) + ((DEF_FRQ) - 1)) / (DEF_FRQ))

+#define CAL_TIM_HIGH(freq, val)     (((freq) * ((val) + 1) + ((DEF_FRQ) - 1)) / (DEF_FRQ) - 1)

+

+

+/** @name frequency define

+         define frequency by numbers

+ */

+/*@{*/

+#define FREQ_168M       (168 * 1000000)

+#define FREQ_124M       (124 * 1000000)

+#define FREQ_84M        (84 * 1000000)

+#define FREQ_62M        (62 * 1000000)

+#define FREQ_31M        (31 * 1000000)

+/*@} */

+

+static T_U32 s_datalen_40M  = 0x82627;

+static T_U32 s_datalen_62M  = 0x82627;

+static T_U32 s_cmdlen_84M   = 0x82671;

+static T_U32 s_datalen_84M  = 0x82627;

+static T_U32 s_datalen_124M = 0xf5c5c;

+static T_U32 s_datalen_168M = 0xf5c5c;

+

+static T_U8 s_flip_bits = 0;

+

+#define ONLY_WEAK_DANGER_PRINT  //only when ecc flip is too much enough to alert user, print error info

+

+#ifdef ONLY_WEAK_DANGER_PRINT

+#define MAX_ECC_FLIP_BIT_NUM 32

+

+#define DANGER_BIT_NUM_MODE0 2	  //	4 bit nand ecc's danger flip bit number among 512 Bytes

+#define DANGER_BIT_NUM_MODE1 6  //8 bit nand ecc's danger flip bit number among 512 Bytes

+#define DANGER_BIT_NUM_MODE2 8  //12 bit nand ecc's danger flip bit number among 512 Bytes

+#define DANGER_BIT_NUM_MODE3 12  //16 bit nand ecc's danger flip bit number among 512 Bytes

+#define DANGER_BIT_NUM_MODE4 18  //24 bit nand ecc's danger flip bit number among 1024 Bytes

+#define DANGER_BIT_NUM_MODE5 26  //32 bit nand ecc's danger flip bit number among 1024 Bytes

+

+typedef struct

+{

+    T_U16 err_loc[MAX_ECC_FLIP_BIT_NUM];

+    T_U8 bad_bytes[MAX_ECC_FLIP_BIT_NUM];

+    T_U8 good_bytes[MAX_ECC_FLIP_BIT_NUM];

+}T_ECC_INFO;

+

+static T_ECC_INFO s_ecc_info;

+#endif

+

+/**

+ * @brief initialization of nandflash hardware.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @return  T_VOID

+ */ 

+

+T_VOID nand_HWinit(T_VOID)

+{

+

+    //T_U8 chip;

+    

+    down(&nand_lock);

+    

+    //set share pin as nandflash data pin

+    ak98_group_config(ePIN_AS_NFC);

+

+    //set cmd&data cycle\len

+    REG32(FLASH_CTRL_REG23) = 0xf5ad1;//0x41230//0x52341//0x82671//0xC3671

+    REG32(FLASH_CTRL_REG24) = 0xf5c5c;//0x30102//0x41213//0x82627//0xF3637

+

+    #if 0 

+    for (chip = 0; chip < 4; chip++)

+    {

+        nand_reset(chip);

+    }

+    #endif

+    nand_reset(0);

+    up(&nand_lock);   

+	

+}

+

+/**

+ * @brief config nand command and data cycle

+ *

+ * @author xuchang

+ * @date 2007-12-27

+ * @param[in] CmdCycle the command cycle to config

+ * @param[in] DataCycle the data cycle to config

+ * @return T_VOID

+ */

+T_VOID nand_config_timeseq(T_U32 CmdCycle, T_U32 DataCycle)

+{

+    //open nand controller clock so that register can be read!!

+    //DRV_PROTECT

+    //set cmd&data cycle\len

+    REG32(FLASH_CTRL_REG23) = CmdCycle;

+    REG32(FLASH_CTRL_REG24) = DataCycle;

+    //DRV_UNPROTECT

+}

+

+static T_U32 calctiming(T_U32 freq)

+{

+    T_U32 data_len;

+    T_U8 data_opt_len, data_we_fe, data_we_re, data_re_fe, data_re_re;

+    T_U8 data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new;

+    T_U32 freq_tmp = freq / 1000000;

+

+    if (s_datalen_84M > 0x90000)

+    {

+        data_opt_len = 8;

+        data_we_fe = 2;

+        data_we_re = 6;

+        data_re_fe = 2;

+        data_re_re = 7;

+    }

+    else

+    {

+        data_opt_len = (s_datalen_84M >> 16) & 0xF;

+        data_we_fe = (s_datalen_84M >> 12) & 0xF;

+        data_we_re = (s_datalen_84M >> 8) & 0xF;

+        data_re_fe = (s_datalen_84M >> 4) & 0xF;

+        data_re_re = (s_datalen_84M >> 0) & 0xF;

+    }

+

+    if (freq <= FREQ_84M)

+    {

+        data_opt_len_new = CAL_TIM_LOW(freq_tmp, data_opt_len);

+        data_we_fe_new   = CAL_TIM_LOW(freq_tmp, data_we_fe);

+        data_we_re_new   = CAL_TIM_LOW(freq_tmp, data_we_re);

+        data_re_fe_new   = CAL_TIM_LOW(freq_tmp, data_re_fe);

+        data_re_re_new   = CAL_TIM_LOW(freq_tmp, data_re_re);

+    }

+    else

+    {

+        data_opt_len_new = CAL_TIM_HIGH(freq_tmp, data_opt_len);

+        data_we_fe_new   = CAL_TIM_HIGH(freq_tmp, data_we_fe);

+        data_we_re_new   = CAL_TIM_HIGH(freq_tmp, data_we_re);

+        data_re_fe_new   = CAL_TIM_HIGH(freq_tmp, data_re_fe);

+        data_re_re_new   = CAL_TIM_HIGH(freq_tmp, data_re_re);

+    }    

+

+    

+    data_len = calc_new(data_opt_len_new, data_we_fe_new, data_we_re_new, data_re_fe_new, data_re_re_new);

+

+    return data_len;

+}    

+

+/**

+ * @brief calculate each nand's timing under 62MHz & 124MHz

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] DefDataLen default data lenght

+ * @return  T_VOID

+ */

+T_VOID nand_calctiming(T_U32 DefDataLen)

+{

+     //open nand controller clock so that register can be read!!

+    //DRV_PROTECT

+    //record the original data_len under 84MHz

+    s_cmdlen_84M = REG32(FLASH_CTRL_REG23);

+    s_datalen_84M = DefDataLen;

+    //DRV_UNPROTECT

+}

+

+

+/**

+ * @brief change nand timing when Freq has changed

+ *

+ * @author yiruoxiang

+ * @date 2007-12-27

+ * @param[in] Freq frequency

+ * @return  T_VOID

+ */

+T_VOID nand_changetiming(T_U32 Freq)

+{

+    T_U32 cmd_len, dat_len;

+

+    if (Freq > FREQ_84M)

+    {

+        cmd_len = 0xf5ad1;

+    }

+    else 

+    {

+        cmd_len = 0x82671;

+    }

+

+    dat_len = calctiming(Freq);

+

+    nand_config_timeseq(cmd_len, dat_len);

+}

+

+/**

+ * @brief read nand flash chip ID.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @return  T_U32

+ * @retval  current nandflash ID

+ */

+T_U32 nand_read_chipID(T_U32 Chip)

+{

+    T_U32 nand_id = 0;

+

+    down(&nand_lock);

+    ak98_group_config(ePIN_AS_NFC);

+    

+    //clear internal status     

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+    

+    //config command

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_READ_ID << 11) | COMMAND_CYCLES_CONF;

+

+    //config address

+    REG32(FLASH_CTRL_REG0 + 0x04) = (0x00 << 11) | ADDRESS_CYCLES_CONF;

+

+    //ID information is 4 byte,read it to register 22

+    REG32(FLASH_CTRL_REG0 + 0x08) = (3 << 11) | READ_INFO_CONF | LAST_CMD_FLAG;

+

+    //excute operation

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );

+

+    // read status

+    nand_id = REG32(FLASH_CTRL_REG20);

+    up(&nand_lock);

+    return nand_id;

+}

+

+/**

+ * @brief reset nand flash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be reset.

+ * @return  T_VOID

+ */

+T_VOID nand_reset(T_U32 Chip)

+{    

+    //clear internal status

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //config command

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_RESET << 11) | COMMAND_CYCLES_CONF;

+

+    //config wait time, the chip may not exist

+    REG32(FLASH_CTRL_REG0 + 0x04) = ((84 * 1000 / 1024) << 11) | DELAY_CNT_CONF | LAST_CMD_FLAG; // wait R/B rising

+

+    //excute operation

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+   

+}

+

+/* set timing */ 

+void nand_settiming(unsigned long cmd_timing, unsigned long data_timing)

+{

+    //printk(KERN_INFO "zz ak98-nfc.c ak98_nand_settiming() line 335\n");

+    down(&nand_lock);

+    ak98_group_config(ePIN_AS_NFC);

+	if (cmd_timing)

+		*(volatile unsigned long *)(FLASH_CTRL_REG23) = cmd_timing;

+

+	if (data_timing)

+		*(volatile unsigned long *)(FLASH_CTRL_REG24) = data_timing;

+		

+	up(&nand_lock);

+}

+

+/* get nandflash chip status */

+unsigned char nand_get_status(unsigned char chip)

+{

+	unsigned long nand_status;

+	unsigned long *reg_addr;

+    //printk(KERN_INFO "zz ak98-nfc.c ak98_nand_get_status() line 349\n");

+    down(&nand_lock);

+    ak98_group_config(ePIN_AS_NFC);

+

+	do {

+		nand_status = 0;

+		reg_addr = (unsigned long *)FLASH_CTRL_REG0;

+

+		*(volatile unsigned long *)(FLASH_CTRL_REG22) = 0x00;

+

+		/* send cmd */

+		*(volatile unsigned long *)(reg_addr++) =

+		    ((NFLASH_READ_STATUS << 11) | COMMAND_CYCLES_CONF);

+		*(volatile unsigned long *)(reg_addr++) = DELAY_CNT_CONF;

+		*(volatile unsigned long *)(reg_addr++) = DELAY_CNT_CONF;

+		*(volatile unsigned long *)(reg_addr) =

+		    ((0x1 << 11) | READ_INFO_CONF | LAST_CMD_FLAG);

+

+		/* excute operation, , enable power saving, CE# keep LOW wait R/B */

+		*(volatile unsigned long *)(FLASH_CTRL_REG22) =

+		    NCHIP_SELECT(chip) | DEFAULT_GO;

+

+		while (!check_cmd_done()) ;

+

+		/* read status */

+		nand_status = *(volatile unsigned long *)(FLASH_CTRL_REG20);

+		if ((nand_status & AK_NAND_STATUS_READY) !=

+		    AK_NAND_STATUS_READY)

+			mdelay(2);

+		else

+			break;

+	} while (1);

+

+	if ((nand_status & AK_NAND_STATUS_ERROR) == AK_NAND_STATUS_ERROR)

+		printk("status error!\n");

+

+    up(&nand_lock);

+	return nand_status & 0xFF;

+}

+

+

+/**

+ * @brief read data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in/out] pDataCtrl control reading data section: buffer, data lenght, ECC.

+ * @param[in/out] pSpareCtrl control reading spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success, 1 fail

+ */

+T_U32 nand_readpage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl)

+{

+    T_U32   i, regvalue, loopCnt, ret;

+    T_U32   ecc_type;

+    T_U32   effective_size, total_len, section_size =0, add_len;

+    T_U8    *pMain_buf, *pAdd_buf;

+    T_U32   *reg_addr;

+    T_U16   fail_cnt = 0;

+    T_BOOL  bSeparate_spare, bSpare_read;

+    T_U8    l2_buf_id;    

+    T_U8    danger_bit_num;     //if ecc flip bit number is more than danger_bit_num, print all flip bytes info

+    T_BOOL  bIsFinalRead = AK_FALSE;     //final read, not care previous read_fail

+   

+    down(&nand_lock);

+    //-------------------zhangzheng add start-----------------------------

+	#ifndef NAND_L2_ENABLE

+    asm("AK_InvalidateDCache_z:\n" "mrc  p15,0,r15,c7,c14,3\n" "bne AK_InvalidateDCache_z"); 

+	#endif

+    ak98_group_config(ePIN_AS_NFC);

+        

+    //-------------------zhangzheng add end-----------------------------

+RETRY_RP:

+    ret = 0;

+    bSpare_read = AK_FALSE;

+    pMain_buf = AK_NULL;

+    pAdd_buf = AK_NULL;

+    add_len = 0;

+    l2_buf_id = BUF_NULL;

+

+    /*check whether is data and spare separate, get the length and ECC type of the first data seciton or spare,

+           and get the times to read data*/ 

+    bSeparate_spare = nf_check_data_spare_separate(pDataCtrl, pSpareCtrl, &loopCnt, &effective_size, &ecc_type);

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 398 Chip=%d,RowAddr=%d,ColumnAddr=%d\n",Chip, RowAddr,ColumnAddr);

+    printk(KERN_INFO "bSeparate_spare=%d loopCnt=%d effective_size=%d ecc_type=%d\n",

+    bSeparate_spare,loopCnt,effective_size,ecc_type);

+	#endif

+

+    if(0 == loopCnt)

+    {

+    	printk(KERN_INFO "%s:%d: loopCnt=%lu \n", __func__, __LINE__, loopCnt);

+        ret = 1;

+        goto RETURN2;

+    }   

+

+    

+#ifdef ONLY_WEAK_DANGER_PRINT

+    if (ECC_4BIT_P512B == pNF_Add->EccType)

+    {

+        danger_bit_num = DANGER_BIT_NUM_MODE0;

+    }

+    else if (ECC_8BIT_P512B == pNF_Add->EccType)

+    {

+        danger_bit_num = DANGER_BIT_NUM_MODE1;

+    }

+    else if (ECC_12BIT_P512B == pNF_Add->EccType)

+    {

+        danger_bit_num = DANGER_BIT_NUM_MODE2;

+    }

+    else if (ECC_24BIT_P1KB == pNF_Add->EccType)

+    {

+        danger_bit_num = DANGER_BIT_NUM_MODE4;

+    }

+    else //default (ECC_32BIT_P1KB == pNF_Add->EccType)

+    {

+        danger_bit_num = DANGER_BIT_NUM_MODE5;

+    }

+#endif

+

+    //clear status

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash read1 command

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;      

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+    }

+    else

+    {

+        if(ColumnAddr < 256)

+        {

+            REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else if(ColumnAddr >= 512)

+        {

+            REG32(reg_addr++) = (NFLASH_READ22 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else

+        {

+            REG32(reg_addr++) = (NFLASH_READ1_HALF << 11) | COMMAND_CYCLES_CONF;

+        }

+    }

+

+    //nandflash send address   

+    reg_addr = nf_send_addr(reg_addr, 0, RowAddr, pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash read2 command if nand is large page

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ2 << 11) | COMMAND_CYCLES_CONF;

+    }

+    //config waiting R/B rising edge

+    REG32(reg_addr++) = WAIT_JUMP_CONF | LAST_CMD_FLAG;

+

+    //run command, wait cmd done 

+    cmd_go(Chip);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 447 before while(cmd)\n");

+	#endif

+	

+    while (!check_cmd_done());

+	

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 453 before while(cmd)\n");

+	#endif

+	

+#ifdef NAND_L2_ENABLE

+    l2_buf_id = ak98_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == l2_buf_id)

+    {

+    	printk(KERN_INFO "%s:%d:I2_buf_id=BUF_NULL \n", __func__, __LINE__);

+        ret = 1;

+        goto RETURN2;

+    }    

+#else

+    communicate_conf(NAND_FLASH, READ_BUF);

+#endif

+    for (i = 0; i < loopCnt; i++)

+    {

+        T_U32 ecc_ret;

+        /*set data size and ecc type to read when reading spare section 

+              if data and spare is separate */

+        if(bSeparate_spare  && (( loopCnt - 1) == i) && (AK_NULL != pSpareCtrl))

+        {

+            bSpare_read = AK_TRUE;

+            effective_size = pSpareCtrl->buf_len;

+            ecc_type = pSpareCtrl->ecc_type;     

+        }

+

+        //config ECC module

+        regvalue = ECC_CTL_DEC_EN | ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR      \

+                        | ECC_CTL_BYTE_CFG(effective_size) | ECC_CTL_NFC_EN | ECC_CTL_MODE(ecc_type)    \

+                        | ECC_CTL_NO_ERR | ECC_CTL_RESULT_NO_OK;    // reset ecc result status bits

+        HAL_WRITE_UINT32(FLASH_ECC_REG0, regvalue);

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  regvalue|ECC_CTL_START);

+

+        //clear status

+        REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+        //config the whole length of a section including ecc part

+        total_len = effective_size + nf_get_ecccode_len(ecc_type);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 491 total_len=%d\n",

+               total_len);

+		#endif

+        REG32(FLASH_CTRL_REG0) = ((total_len - 1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG;

+#ifdef NAND_L2_ENABLE

+        //clear l2 status, must before cmd_go

+        ak98_l2_clr_status(l2_buf_id);

+#endif

+        

+        //start to transfer data from nand to l2

+        cmd_go(Chip);

+

+        //need to read data part if pDataCtrl is not NULL

+        if ((AK_NULL != pDataCtrl) && (!bSpare_read))

+        {            

+            if(!bSeparate_spare)

+            {

+                section_size = pDataCtrl->ecc_section_len - pSpareCtrl->buf_len;

+            }

+            else

+            {

+                section_size = pDataCtrl->ecc_section_len;

+            }    

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 515 section_size=%d\n", section_size);

+			#endif

+            pMain_buf = pDataCtrl->buf + (i * section_size);

+#ifdef NAND_L2_ENABLE

+            

+			ak98_l2_combuf_cpu((T_U32)pMain_buf, l2_buf_id, section_size, BUF2MEM); 

+#else	// ! NAND_L2_ENABLE

+        	rece_dat_cpu(pMain_buf, section_size, NAND_FLASH);

+#endif

+        } 

+//        printk(KERN_INFO "zz nand_control.c nand_readpage_ecc()592 reg22=0x%x \n",*(volatile unsigned long *)(FLASH_CTRL_REG22));

+        //wait data transfered        

+        while(!check_cmd_done());

+//        printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 595\n");

+        //copy spare from l2 to memory 

+        if ((AK_NULL != pSpareCtrl) && (!bSeparate_spare || bSpare_read))

+        {  

+            if(!bSeparate_spare)

+            {

+                //need to read spare while reading a section of data if data and spare is not separate

+                pAdd_buf = pSpareCtrl->buf;

+                add_len = pSpareCtrl->buf_len;

+            }  

+            else

+            {

+                //read spare for the last time(bSpare_read is true) if data and spare is separate

+                pMain_buf = pSpareCtrl->buf;

+                section_size = effective_size;

+            }

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_readpage_ecc() 557 spare len=%d\n",

+				   pSpareCtrl->buf_len);

+			#endif

+			

+			#ifdef NAND_L2_ENABLE

+			ak98_l2_combuf_cpu((T_U32)pSpareCtrl->buf, l2_buf_id, pSpareCtrl->buf_len, BUF2MEM);

+			

+			#else

+			rece_dat_cpu(pSpareCtrl->buf, pSpareCtrl->buf_len, NAND_FLASH);

+			#endif

+

+        }

+

+        ecc_ret = nf_check_repair_ecc(pMain_buf, pAdd_buf, section_size, add_len, ecc_type, bSeparate_spare);

+      

+        if (DATA_ECC_CHECK_ERROR == ecc_ret)

+        {   

+            if (AK_FALSE == bIsFinalRead)

+            {

+                fail_cnt++;                

+                if ((fail_cnt & 0x40) != 0) //max retry read cnt = 64

+                {

+                    bIsFinalRead = AK_TRUE;

+                }

+#ifdef NAND_L2_ENABLE

+                ak98_l2_free(ADDR_NFC);

+#endif

+                goto RETRY_RP;

+            }

+            else

+            {

+                ret = 1;

+            }

+        }

+        else if (DATA_ECC_ERROR_REPAIR_CAN_TRUST == ecc_ret)

+        {

+        

+#ifdef ONLY_WEAK_DANGER_PRINT

+            if (s_flip_bits > danger_bit_num)

+            {

+                T_U8 k;

+

+                for (k = 0; k < s_flip_bits; k++)

+                {

+                    printk(KERN_INFO" L%d", s_ecc_info.err_loc[k]);

+                    if (s_ecc_info.good_bytes[k] != s_ecc_info.bad_bytes[k])

+                    {

+                        printk(KERN_INFO "_0x%x->0x%x", s_ecc_info.bad_bytes[k], s_ecc_info.good_bytes[k]);

+                    }

+                }

+                printk(KERN_INFO "ECC:good,B=%d,P=%d,i=%lu,flip=%u\n", (int)(RowAddr / pNF_Add->PagesPerBlock), (int)(RowAddr % pNF_Add->PagesPerBlock), i, s_flip_bits);

+            }

+#else

+            printk(KERN_INFO "ECC:good,B=%d,P=%d,i=%d,flip=%u\n", (int)(RowAddr / pNF_Add->PagesPerBlock), (int)(RowAddr % pNF_Add->PagesPerBlock), i, s_flip_bits);

+#endif

+        } 

+    }

+	

+RETURN2:    

+#ifdef NAND_L2_ENABLE

+    ak98_l2_free(ADDR_NFC);

+#endif

+

+    up(&nand_lock);

+    return ret;

+}   

+

+#if 0

+/**

+ * @brief read one page(page size>=2048) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be large than or equal to 2048 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 *Spare)

+{

+    return nand_readsector(Chip, RowAddr, ColumnAddr, pNF_Add, Data, Spare);

+}

+

+/**

+ * @brief read one page(page size=512) of data from nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data, should be 512 bytes.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readsector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;    

+    T_U32 ecc_len = (pNF_Add->EccType > ECC_12BIT_P512B) ? NAND_DATA_SIZE_P1KB : NAND_DATA_SIZE_P512B;

+	

+    data_ctrl.buf = Data;

+    data_ctrl.buf_len = pNF_Add->PageSize;    

+    data_ctrl.ecc_section_len = ecc_len + NAND_FS_SIZE;    

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = Spare + 2;

+    spare_ctrl.buf_len = NAND_FS_SIZE;    

+    spare_ctrl.ecc_section_len = ecc_len + NAND_FS_SIZE;    

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+     

+    return nand_readpage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+#endif

+/**

+ * @brief read file system info.

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Spare buffer for file system info, should be 4 bytes.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readspare(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;    

+    T_U8 data[NAND_DATA_SIZE_P1KB];

+    T_U32 ecc_len = (pNF_Add->EccType > ECC_12BIT_P512B) ? NAND_DATA_SIZE_P1KB : NAND_DATA_SIZE_P512B;

+

+    data_ctrl.buf = data;

+    data_ctrl.buf_len = ecc_len;

+    data_ctrl.ecc_section_len = ecc_len + NAND_FS_SIZE;

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = (T_U8*)Spare;

+    spare_ctrl.buf_len = NAND_FS_SIZE;

+    spare_ctrl.ecc_section_len = ecc_len + NAND_FS_SIZE;

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+    

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readspare() 683\n");

+	#endif

+    return nand_readpage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+/**

+ * @brief read data from nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[out] Data buffer for read data.

+ * @param[in] Len how many bytes read from nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_readbytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Len)

+{

+    T_U32 *reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+    T_U32 tmp   = 0;

+	T_U8 l2_buf_id = BUF_NULL;

+    T_U8  i     = 0;

+    T_U32 ret   = 0;

+	

+	//-------------------zhangzheng add start-----------------------------

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_readbytes() 716 Len=%d \n", Len);

+	#endif

+	#ifndef NAND_L2_ENABLE	

+    asm("AK_InvalidateDCache_rb:\n" "mrc  p15,0,r15,c7,c14,3\n" "bne AK_InvalidateDCache_rb"); 

+	#endif

+    printk(KERN_INFO "nand_readbytes Chip=%lu,RowAddr=%lu,ColumnAddr=%lu \n",Chip, RowAddr,ColumnAddr);

+

+	down(&nand_lock);

+    ak98_group_config(ePIN_AS_NFC);

+	//-------------------zhangzheng add end------------------------------

+

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash send command

+    REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash read2 command,this is a wait command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_READ2 << 11) | COMMAND_CYCLES_CONF |(1 << 10);

+    }

+	

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+	cmd_go(Chip);

+	while (!check_cmd_done());

+

+	#ifdef NAND_L2_ENABLE

+	l2_buf_id = ak98_l2_alloc(ADDR_NFC);

+	if (BUF_NULL == l2_buf_id)

+	{

+		ret = 1;

+		goto RETURN1;

+	}

+	#else

+	communicate_conf(NAND_FLASH, READ_BUF);

+	#endif

+	

+    //config ECC

+    tmp = (ECC_CTL_DIR_READ | ECC_CTL_ADDR_CLR  \

+            | ECC_CTL_BYTE_CFG(Len) | ECC_CTL_NFC_EN | ECC_CTL_MODE(pNF_Add->EccType));

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, tmp|ECC_CTL_START);

+    REG32(FLASH_CTRL_REG0) = ((Len - 1) << 11) | READ_DATA_CONF | LAST_CMD_FLAG;

+    cmd_go(Chip);

+

+    for(i = 0; i < (Len / NAND_DATA_SIZE); i++)

+    {

+		#ifdef NAND_L2_ENABLE

+		ak98_l2_combuf_cpu((T_U32)(Data + (i * NAND_DATA_SIZE)), l2_buf_id, 

+															NAND_DATA_SIZE, BUF2MEM);

+		#else

+		rece_dat_cpu(Data+(i*NAND_DATA_SIZE), NAND_DATA_SIZE, NAND_FLASH);

+		#endif   

+    }

+	

+    tmp = Len & 511;

+    if (tmp != 0)

+    {

+    	#ifdef NAND_L2_ENABLE

+		ak98_l2_combuf_cpu((T_U32)(Data + i * NAND_DATA_SIZE), l2_buf_id, tmp, BUF2MEM);

+		#else

+		rece_dat_cpu(Data+(i*NAND_DATA_SIZE), tmp, NAND_FLASH);

+		#endif

+    }

+

+    while (!check_cmd_done());

+

+	ret = 0;

+	

+RETURN1:

+	#ifdef NAND_L2_ENABLE 

+	ak98_l2_free(ADDR_NFC);

+	#endif

+

+	up(&nand_lock);

+	return ret;

+}

+

+/**

+ * @brief write data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] pDataCtrl control writting data section: buffer, data lenght, ECC.

+ * @param[in] pSpareCtrl control writting spare section: buffer, data lenght, ECC.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writepage_ecc(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_PNAND_ECC_STRU  pDataCtrl,  T_PNAND_ECC_STRU pSpareCtrl)

+{

+    T_U32   i, loopCnt;

+    T_BOOL  bSeparate_spare;

+    T_U32   effective_size;

+    T_U32   ecc_type;

+    T_U32   total_len;

+    T_U8    tmp_rowcycle = pNF_Add->RowCycle - 1;

+    T_U32   ret;

+    T_U32   status;

+    T_U32   tmp = 0;

+    T_U32   section_data_size;

+    T_U32   *reg_addr;

+    T_U8    l2_buf_id;

+    T_U16   fail_cnt = 0;

+    T_BOOL  bSpare_write;

+    

+    down(&nand_lock);

+	#ifndef NAND_L2_ENABLE

+    asm("AK_FlashDCache_zz:\n" "mrc  p15,0,r15,c7,c10,3\n" "bne AK_FlashDCache_zz");

+	#endif	

+    ak98_group_config(ePIN_AS_NFC);

+    

+ RETRY_WR: 

+    ret = 0;

+    bSpare_write = AK_FALSE;

+    l2_buf_id = BUF_NULL;

+    

+    /*check whether is data and spare separate, get the length and ECC type of the first data seciton,

+       and get the times to write data*/   

+    bSeparate_spare = nf_check_data_spare_separate(pDataCtrl, pSpareCtrl, &loopCnt, &effective_size, &ecc_type);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz nand_control.c %s:line %d phy_page=%d\n", __func__, __LINE__, RowAddr);

+    printk(KERN_INFO "bSeparate_spare=%d loopCnt=%d effective_size=%d ecc_type=%d\n",

+           bSeparate_spare,loopCnt,effective_size,ecc_type);

+    #endif

+    if (0 == loopCnt)

+    {

+        ret = 1;

+        goto RETURN2;

+    }    

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0; 

+

+    if (NAND_512B_PAGE == pNF_Add->ChipType)

+    {

+        //... ÐèÒªµ÷ÕûÖ¸Õë

+        if(ColumnAddr < 256)

+        {

+            REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else if(ColumnAddr >= 512)

+        {

+            REG32(reg_addr++) = (NFLASH_READ22 << 11) | COMMAND_CYCLES_CONF;

+        }

+        else

+        {

+            REG32(reg_addr++) = (NFLASH_READ1_HALF << 11) | COMMAND_CYCLES_CONF;

+        }

+    }

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR; 

+   

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM0)

+    REG32(reg_addr++) = (NFLASH_FRAME_PROGRAM0 << 11) | COMMAND_CYCLES_CONF; 

+

+    //nandflash send address

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, tmp_rowcycle);

+    REG32(reg_addr) = ((RowAddr >> (tmp_rowcycle * 8)) << 11) | ADDRESS_CYCLES_CONF | LAST_CMD_FLAG;

+

+    //execute cmd and wait command send done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+	#if ZZ_DEBUG

+    printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 883 after while\n");

+	#endif

+	

+#ifdef NAND_L2_ENABLE

+    l2_buf_id = ak98_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == l2_buf_id)

+    {

+        ret = 1;

+        goto RETURN2;

+    } 

+   // ak98_l2_dump_registers();

+#else

+    communicate_conf(NAND_FLASH, WRITE_BUF);

+#endif

+

+    for (i = 0; i < loopCnt; i++)

+    {

+        /*set data size and ecc type to write when writing spare section 

+        if data and spare is separate */

+        if (bSeparate_spare  && (( loopCnt - 1) == i) && (AK_NULL != pSpareCtrl))

+        {

+            bSpare_write = AK_TRUE;

+            effective_size = pSpareCtrl->buf_len;

+            ecc_type = pSpareCtrl->ecc_type;

+        }

+

+        //config ECC module

+		

+		tmp = ( ECC_CTL_ENC_EN | ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR	\

+                | ECC_CTL_BYTE_CFG(effective_size) | ECC_CTL_NFC_EN | ECC_CTL_MODE(ecc_type));

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp);

+        HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp|ECC_CTL_START);

+        //sta_clr = 0,

+        REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+        //config the whole length of a section including ecc part

+        total_len = effective_size + nf_get_ecccode_len(ecc_type);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 920 total_len=%d\n",

+              total_len);

+		#endif

+        REG32(FLASH_CTRL_REG0) = ((total_len - 1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG;

+

+        //start to transfer data from memory to nand

+        cmd_go(Chip);

+		

+        //copy page data to L2 buffer

+        if(!bSpare_write)

+        {

+            //the length of a ecc data section

+            if(!bSeparate_spare)

+            {

+                section_data_size = pDataCtrl->ecc_section_len - pSpareCtrl->buf_len;

+            }

+            else

+            {

+                section_data_size = pDataCtrl->ecc_section_len;

+            }    

+			

+#ifdef NAND_L2_ENABLE            

+                

+                ak98_l2_combuf_cpu((T_U32)(pDataCtrl->buf + (i * section_data_size)), 

+												l2_buf_id, section_data_size, MEM2BUF); 

+            

+            if(0 == (section_data_size & 63))

+            {

+                //wait nand controler transfer data

+                while(0 != ak98_l2_get_status(l2_buf_id)); 

+            }

+           // ak98_l2_dump_registers();          

+			

+#else	// ! NAND_L2_ENABLE

+            prepare_dat_send_cpu(pDataCtrl->buf+(i*section_data_size), section_data_size, NAND_FLASH);

+#endif

+        }

+

+        //send spare data

+        if ((AK_NULL != pSpareCtrl) && (!bSeparate_spare || bSpare_write))

+        {

+#ifdef NAND_L2_ENABLE

+			#if ZZ_DEBUG

+			printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 970 spare len=%d\n",pSpareCtrl->buf_len);

+			#endif

+            ak98_l2_combuf_cpu((T_U32)pSpareCtrl->buf, l2_buf_id, pSpareCtrl->buf_len, MEM2BUF);

+#else

+            prepare_dat_send_cpu(pSpareCtrl->buf + (i*NAND_FS_SIZE), NAND_FS_SIZE, NAND_FLASH);

+#endif

+        } 

+       

+        while (!check_cmd_done());

+		

+#ifdef NAND_L2_ENABLE

+	    ak98_l2_clr_status(l2_buf_id);

+#else

+        //clear l2 status, because l2_combuf_cpu will set l2 status 

+        ak98_l2_clr_status(WRITE_BUF);

+#endif

+        // wait for ECC complete

+        do 

+        {

+            HAL_READ_UINT32(FLASH_ECC_REG0, tmp);       

+        }   while(0 == (tmp & ECC_CTL_END));

+

+        

+        do

+        {

+            HAL_READ_UINT32(FLASH_ECC_REG0,tmp);

+        }   while(0 == (tmp & ECC_CTL_ENC_RDY));

+       

+        HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+    }

+	

+#ifdef NAND_L2_ENABLE

+    ak98_l2_free(ADDR_NFC);

+#endif

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM1)

+    REG32(reg_addr++)= ((NFLASH_FRAME_PROGRAM1 << 11) | COMMAND_CYCLES_CONF | LAST_CMD_FLAG);

+

+    //run command, wait cmd done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+

+    for ( i = 0; i < MAX_LOOP_CNT; i++ )

+    {

+        status = nf_read_chipstatus(Chip);

+		#if ZZ_DEBUG

+        printk(KERN_INFO "zz nand_control.c nand_writepage_ecc() 1014 status=0x%lx\n",

+               status);

+		#endif

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_WR;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN2;

+            }

+            else 

+            {

+                ret = 0;

+                goto RETURN2;

+            }

+        }

+        udelay(100);

+    }

+    ret = 2;

+    

+RETURN2:

+

+    up(&nand_lock);

+    return ret;

+}

+

+#if 0

+/**

+ * @brief write one page(page size>=2048) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be large than or equal to 2048 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector_large(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U32 Spare)

+{

+     return nand_writesector(Chip, RowAddr, ColumnAddr, pNF_Add, Data, Spare);

+}

+

+/**

+ * @brief write one page(page size=512) of data to nand flash with ECC .

+ *

+ * @author jiangdihui

+ * @date 2010-07-23

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data, should be 512 bytes.

+ * @param[in] Spare file system info.

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writesector(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, T_U8 Data[], T_U8 *Spare)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+

+    data_ctrl.buf = Data;

+    data_ctrl.buf_len = pNF_Add->PageSize;

+    data_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    data_ctrl.ecc_type = pNF_Add->EccType;

+

+    spare_ctrl.buf = Spare + 2;

+    spare_ctrl.buf_len = NAND_FS_SIZE;

+    spare_ctrl.ecc_section_len = NAND_DATA_SIZE + NAND_FS_SIZE;

+    spare_ctrl.ecc_type = pNF_Add->EccType;

+

+    return nand_writepage_ecc(Chip, RowAddr, ColumnAddr, pNF_Add, &data_ctrl, &spare_ctrl);

+}

+

+#endif

+/**

+ * @brief write data to nandflash without ECC.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be read.

+ * @param[in] RowAddr the row address of nandflash.

+ * @param[in] ColumnAddr the column address of nandflash.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @param[in] Data buffer for write data.

+ * @param[in] Len how many bytes write to nandflash

+ * @return  T_U32

+ * @retval  0 success

+ */

+T_U32 nand_writebytes(T_U32 Chip, T_U32 RowAddr, T_U32 ColumnAddr, T_PNandflash_Add pNF_Add, const T_U8 Data[], T_U32 Len)

+{

+    T_U32 *reg_addr;

+    T_U32 ret = 0, LoopCnt = 0, tmp, i, status;

+    T_U8  tmp_rowcycle = pNF_Add->RowCycle - 1, buf_id = BUF_NULL;

+    T_U16 fail_cnt = 0;

+

+    down(&nand_lock);

+

+RETRY_WR:

+    i = 0;

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+    

+    //nandflash frame write command(NFLASH_FRAME_PROGRAM0)

+    REG32(reg_addr++)=((NFLASH_FRAME_PROGRAM0 << 11) | COMMAND_CYCLES_CONF); 

+

+    //nandflash send address

+    reg_addr = nf_send_addr(reg_addr, ColumnAddr, RowAddr, pNF_Add->ColCycle, tmp_rowcycle);

+    REG32(reg_addr)=(((RowAddr >> (tmp_rowcycle * 8)) << 11) | ADDRESS_CYCLES_CONF | LAST_CMD_FLAG);

+

+    //run cmd, wait fifo command send done

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+

+    buf_id = ak98_l2_alloc(ADDR_NFC);

+    if (BUF_NULL == buf_id)

+    {

+        ret = 1;

+        goto RETURN4;

+    }

+        

+    //config ECC module

+    tmp = ( ECC_CTL_DIR_WRITE | ECC_CTL_ADDR_CLR    \

+           | ECC_CTL_BYTE_CFG(Len) | ECC_CTL_NFC_EN);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0,  tmp|ECC_CTL_START);

+

+    REG32(FLASH_CTRL_REG0)=(((Len -  1) << 11) | WRITE_DATA_CONF | LAST_CMD_FLAG);

+

+    cmd_go(Chip);

+

+    //copy data to l2

+    for(i = 0; i < (Len / NAND_DATA_SIZE); i++)

+    {

+        ak98_l2_combuf_cpu((T_U32)(Data + (i * NAND_DATA_SIZE)), buf_id, 

+													NAND_DATA_SIZE, MEM2BUF);

+        //wait nand controler transfer data

+        while(0 != ak98_l2_get_status(buf_id));

+    }

+    

+    tmp = Len & 511;

+    if (tmp != 0)

+    {

+        ak98_l2_combuf_cpu((T_U32)(Data + i * NAND_DATA_SIZE), buf_id, tmp, MEM2BUF);

+    }

+

+    while ( !check_cmd_done());

+

+    ak98_l2_clr_status(buf_id);

+   

+    //wait for ECC complete        

+    do 

+    {

+        HAL_READ_UINT32(FLASH_ECC_REG0, tmp);

+    }while ((tmp  & ECC_CTL_END) != ECC_CTL_END);

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+    REG32(reg_addr++)= ((NFLASH_FRAME_PROGRAM1 << 11) | COMMAND_CYCLES_CONF);

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+    cmd_go(Chip);

+    while ( !check_cmd_done() );

+ 

+    for ( LoopCnt = 0; LoopCnt < MAX_LOOP_CNT; LoopCnt++)

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_WR;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN4;

+            }

+            else 

+            {

+                ret = 0;

+                goto RETURN4;

+            }

+        } 

+        udelay(100);

+    }

+    ret = 2;

+

+RETURN4:

+    ak98_l2_free(ADDR_NFC);

+    up(&nand_lock);

+    return ret;

+}

+

+/**

+ * @brief erase one block of nandflash.

+ *

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] BlkStartPage first page of the block.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return T_U32

+ * @retval 0 means write successfully

+ * @retval 1 means write unsuccessfully

+ * @retval 2 means time out

+ */

+T_U32 nand_eraseblock(T_U32 Chip, T_U32 BlkStartPage, T_PNandflash_Add pNF_Add)

+{

+    T_U32 status;

+    T_U32 *reg_addr;

+    T_U32 ret = 0;

+    T_U32 LoopCnt  = 0;

+    T_U16 fail_cnt = 0;

+

+   // printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1301 startpage=%d\n", 

+   //        BlkStartPage);

+

+    down(&nand_lock);

+ 	

+    ak98_group_config(ePIN_AS_NFC);

+ 	

+RETRY_EB:

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0, need?

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    //nandflash erase command

+    REG32(reg_addr++) = (NFLASH_BLOCK_ERASE0 << 11) | COMMAND_CYCLES_CONF;

+

+    //nandflash physic page address

+    reg_addr = nf_send_addr(reg_addr, 0, BlkStartPage, 0, pNF_Add->RowCycle);	 	

+

+    //nandflash erase command

+    REG32(reg_addr++) = (NFLASH_BLOCK_ERASE1 << 11) | COMMAND_CYCLES_CONF;

+

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+

+    // excute operation, CE1, enable power saving, CE# keep LOW wait R/B

+    cmd_go(Chip);

+	

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+	

+    for ( LoopCnt = 0; LoopCnt <MAX_LOOP_CNT; LoopCnt ++ )

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 == (status & NFLASH_WRITE_PROTECT) )

+        {

+        	#if ZZ_DEBUG

+            printk(KERN_INFO "zz nand_control.c nand_eraseblock() 1275\n");

+			#endif

+            while (1);

+        }

+        else if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 2)

+                {

+                    goto RETRY_EB;

+                }

+                ret = 1;

+                goto RETURN5;

+            }

+            else

+            {

+                ret = 0;

+                goto RETURN5;

+            }

+        }

+        udelay(100);

+    }

+    ret = 2;

+RETURN5:

+    #ifdef CONFIG_MTD_NAND_TEST  

+    T_U32 blocknum = 0;

+    blocknum = BlkStartPage/pNF_Add->PagesPerBlock;

+    *(nand_erase_test + blocknum) += 1;

+   // printk("hy erase_count[%u]=%d\n",blocknum, *(nand_erase_test + blocknum));

+    #endif

+

+    up(&nand_lock);

+

+    return ret;

+}

+

+#ifdef CONFIG_MTD_NAND_TEST  

+T_U32 nand_get_erase_block_count(T_U32 blocknum)

+{   

+    if (blocknum >= nand_total_blknum)

+    {

+        printk("blocknum is biger than total num\n");

+        return -1;

+    }

+    else

+    {

+        return *(nand_erase_test + blocknum);

+    }

+}

+#endif

+

+/**

+ * @brief copy one physical page to another one.

+ *

+ * hardware copyback mode, there should be caches in nandflash, source and destation page should be in the same plane

+ * @author yiruoxiang

+ * @date 2006-11-02

+ * @param[in] Chip which chip will be operated.

+ * @param[in] SouPhyPage the source page to read.

+ * @param[in] DesPhyPage the destination page to write.

+ * @param[in] pNF_Add information of the nandflash characteristic.

+ * @return  T_U32

+ * @retval  0 means write successfully

+ * @retval  1 means write unsuccessfully

+ * @retval  2 means time out

+ */

+T_U32 nand_copyback(T_U32 Chip, T_U32 SrcPhyPage, T_U32 DestPhyPage, T_PNandflash_Add pNF_Add)

+{

+    T_U32 status;

+    T_U32 *reg_addr;

+    T_U32 ret = 0;

+    T_U16 fail_cnt = 0;

+    T_U32 i;

+

+    down(&nand_lock);

+

+RETRY_CP:

+    reg_addr = (T_U32 *)FLASH_CTRL_REG0;

+

+    // sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+    //nandflash read1 command

+    REG32(reg_addr++) = (NFLASH_READ1 << 11) | COMMAND_CYCLES_CONF;

+

+    reg_addr = nf_send_addr(reg_addr, 0, SrcPhyPage,  pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash copyback read command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_READ << 11) | COMMAND_CYCLES_CONF;

+    }    

+

+    REG32(reg_addr++) = WAIT_JUMP_CONF;// wait R/B rising edge

+

+    //nandflash copyback write command

+    if (NAND_512B_PAGE != pNF_Add->ChipType)

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_WRITE << 11) | COMMAND_CYCLES_CONF;

+    }

+    else

+    {

+        REG32(reg_addr++) = (NFLASH_COPY_BACK_WRITE1 << 11) | COMMAND_CYCLES_CONF;

+    }

+

+    reg_addr = nf_send_addr(reg_addr, 0, DestPhyPage,  pNF_Add->ColCycle, pNF_Add->RowCycle);

+

+    //nandflash copyback confirm command

+    //if (NFLASH_SMALL_PAGE != pNF_Add->ChipType)

+    //small page slc also need to send '10H' command, resumed on 20070615

+    REG32(reg_addr++) = (NFLASH_COPY_BACK_CONFIRM << 11) | COMMAND_CYCLES_CONF;

+    

+    REG32(reg_addr) = WAIT_JUMP_CONF | LAST_CMD_FLAG;// wait R/B rising edge

+    

+    cmd_go(Chip);

+

+    // wait reg22 fifo command send done

+    while ( !check_cmd_done() );

+

+    for ( i = 0; i < MAX_LOOP_CNT; i++ )

+    {

+        status = nf_read_chipstatus(Chip);

+        if ( 0 != (status & NFLASH_HANDLE_READY) )

+        {

+            if ( 0 != (status & NFLASH_PROGRAM_SUCCESS) )

+            {

+                fail_cnt++;

+                if (fail_cnt < 10)

+                {

+                    goto RETRY_CP;    //more than 10 ms to exit, otherwise continue

+                }

+                ret = 1;

+                goto RETURN6;

+            }

+            else

+            {

+                ret = 0;

+                goto RETURN6;

+            }

+        }

+        udelay(100);//delay or handle other task

+    }

+    ret = 2;

+RETURN6:

+    up(&nand_lock);

+    return ret;

+}

+

+//***********************************************************************************

+/*

+static T_VOID nf_controller_reset(T_VOID)

+{

+    T_U32 cmd_len = 0xf5ad1;

+    T_U32 dat_len = 0xf5c5c;

+    

+    //akprintf(C3, M_DRVSYS, "reset nand controller\r\n");  

+    

+    cmd_len = REG32(FLASH_CTRL_REG23);

+    dat_len = REG32(FLASH_CTRL_REG24);

+    

+    sysctl_reset(RESET_NANDFLASH);

+

+    REG32(FLASH_CTRL_REG23) = cmd_len;

+    REG32(FLASH_CTRL_REG24) = dat_len;

+}

+*/

+//***********************************************************************************

+static T_U8 nf_read_chipstatus(T_U32 Chip)

+{

+    T_U32 status;

+

+    //sta_clr = 0,

+    REG32(FLASH_CTRL_REG22) &= ~NF_REG_CTRL_STA_STA_CLR;

+

+    REG32(FLASH_CTRL_REG0 + 0x00) = (NFLASH_STATUS_READ << 11) | COMMAND_CYCLES_CONF;

+

+    //read status,1byte

+    REG32(FLASH_CTRL_REG0 + 0x04) = (0 << 11) | READ_INFO_CONF | LAST_CMD_FLAG;

+

+    // excute operation, CE1, enable power saving, CE# keep LOW wait R/B

+    //must open write protect

+    cmd_go(Chip);

+

+    // wait end & read data (data at where)

+    while ( !check_cmd_done() );   // µÈ´ý²Ù×÷Íê³É

+

+    // read status

+    status = REG32(FLASH_CTRL_REG20);

+

+    return((T_U8)(status & 0xFF));

+}

+

+//***********************************************************************************

+static T_U32 *nf_send_addr(T_U32 *reg_addr, T_U32 ColumnAddr,T_U32 rowAddr, T_U32 col_cycle, T_U32 row_cycle)

+{

+    T_U8 cycle,value;

+

+    //send column address

+    for (cycle = 0; cycle < col_cycle; cycle++)

+    {

+        value = (ColumnAddr >> (8 * cycle)) & 0xFF;

+        REG32(reg_addr++) = (value << 11) | ADDRESS_CYCLES_CONF;

+    }

+

+    //send row address

+    for (cycle = 0; cycle < row_cycle; cycle++)

+    {

+        value = (rowAddr >> (8 * cycle)) & 0xFF;

+        REG32(reg_addr++) = (value << 11) | ADDRESS_CYCLES_CONF;

+    }

+

+    return reg_addr;

+}

+//***********************************************************************************

+static T_BOOL nf_check_data_spare_separate(T_PNAND_ECC_STRU pDataCtrl, T_PNAND_ECC_STRU pSpareCtrl, T_U32 *cycle, T_U32 *effective_size, T_U32 *ecc_type)

+{

+    T_BOOL ret = AK_TRUE;

+

+    if(AK_NULL == pDataCtrl)

+    {

+        *cycle = 1;

+        *effective_size = pSpareCtrl->buf_len;

+        *ecc_type = pSpareCtrl->ecc_type;

+    }

+    else

+    {

+        T_U32 section_len = pDataCtrl->ecc_section_len;

+

+        if(0 != (pDataCtrl->buf_len % section_len)) //spare and data is not separate

+        {

+            section_len -= pSpareCtrl->buf_len;

+

+            if(0 != (pDataCtrl->buf_len % section_len))  //param err

+            {

+                *cycle = 0;

+            }    

+            else

+            {

+                *cycle = pDataCtrl->buf_len / section_len;

+            }

+

+            ret = AK_FALSE;

+        }

+        else

+        {

+            *cycle = pDataCtrl->buf_len / section_len;

+

+            if(AK_NULL != pSpareCtrl)

+            {

+                (*cycle)++;

+            }

+        }

+

+        *effective_size = pDataCtrl->ecc_section_len;

+        *ecc_type = pDataCtrl->ecc_type;

+    }

+

+    return ret;

+}    

+//***********************************************************************************

+static T_U32 nf_get_ecccode_len(T_U32 ecc_type)

+{

+    T_U32 ecc_len = NAND_PARITY_SIZE_MODE0;

+    

+    switch(ecc_type)

+    {

+        case ECC_4BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE0;

+            break;

+        case ECC_8BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE1;

+            break;            

+        case ECC_12BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE2;

+            break;

+        case ECC_16BIT_P512B:

+            ecc_len = NAND_PARITY_SIZE_MODE3;

+            break;    

+        case ECC_24BIT_P1KB:

+            ecc_len = NAND_PARITY_SIZE_MODE4;

+            break;

+        case ECC_32BIT_P1KB:

+            ecc_len = NAND_PARITY_SIZE_MODE5;

+            break;    

+        default:

+            break; 

+    } 

+

+    return ecc_len;

+} 

+

+//***********************************************************************************

+static T_U8 nf_check_ecc_status(T_U32 stat)

+{

+    if ( (stat & ECC_CHECK_NO_ERROR) == ECC_CHECK_NO_ERROR )

+    {

+        stat |= ECC_CHECK_NO_ERROR;

+        HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);

+        HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);

+        return DATA_ECC_CHECK_OK;

+    }

+    else if ( (stat & ECC_ERROR_REPAIR_CAN_NOT_TRUST) == ECC_ERROR_REPAIR_CAN_NOT_TRUST)

+    {

+        stat |= ECC_ERROR_REPAIR_CAN_NOT_TRUST;

+        HAL_WRITE_UINT32(FLASH_ECC_REG0 ,stat);

+        HAL_READ_UINT32(FLASH_ECC_REG0 ,stat);

+        return DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST;

+    }

+    else

+    {

+        return DATA_ECC_ERROR_REPAIR_CAN_TRUST;

+    }

+}

+

+//***********************************************************************************

+static T_U32 nf_check_repair_ecc(T_U8 *pMain_buf, T_U8 *pAdd_buf, 

+                    T_U32 section_size, T_U32 add_len, T_U32 ecc_type, T_BOOL  bSeparate_spare)

+{

+    T_U32   tmp,m,j;

+    T_U32   position_info;

+    T_U32   error_count;

+    T_U32   bit_errs;

+    T_U8    max_errcnt;

+    T_U8    ecc_stat; 

+

+    //wait for ECC complete    

+    do

+    {

+        HAL_READ_UINT32(FLASH_ECC_REG0,tmp);

+    } while(0 == (tmp & ECC_CTL_END));

+    

+	do

+    {

+        HAL_READ_UINT32(FLASH_ECC_REG0,tmp);

+    } while(0 == (tmp & ECC_CTL_DEC_RDY));

+    

+    HAL_WRITE_UINT32(FLASH_ECC_REG0, (tmp | ECC_CTL_END));

+

+    ecc_stat = nf_check_ecc_status(tmp);

+

+    switch(ecc_stat)

+    {

+        case DATA_ECC_CHECK_OK:

+            break;

+

+        case DATA_ECC_ERROR_REPAIR_CAN_TRUST:        

+            s_flip_bits = 0;

+            

+            if(ecc_type >= ECC_24BIT_P1KB)

+            {

+                max_errcnt = (ecc_type - 1) * 8;

+            } 

+            else

+            {

+                max_errcnt = (ecc_type + 1) * 4;

+            }

+

+            //ecc correct

+            for (error_count = 0; error_count < max_errcnt; error_count++)

+            {  

+                HAL_READ_UINT32(FLASH_ECC_REPAIR_REG0 + error_count * 4 ,position_info);

+                ecc_repair(position_info, pMain_buf, pAdd_buf, section_size, add_len, ecc_type);

+            }

+            break;

+

+        case DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST:

+            bit_errs = 0;

+            if (!bSeparate_spare)

+            {

+                for(j = 0; j < add_len; j++)

+                {

+                    if (0xff != *(pAdd_buf+ j))

+                    {

+                        for(m = 0; m < 8; m++)

+                        {

+                            if(0 == ((*(pAdd_buf + j)) & (1 << m)))

+                            {

+                                bit_errs++;

+                            }    

+                        }

+

+                        if(bit_errs > 3)

+                        {

+                            goto RETURN1;

+                        }

+                    }

+                } 

+

+                if(0 != bit_errs)

+                {

+                    memset(pAdd_buf, 0xFF, add_len);

+				}

+           }

+           else

+           {

+                for(j = 0; j < section_size; j++)

+                {

+                    if (0xff != *(pMain_buf + j))

+                    {

+                        for(m = 0; m < 8; m++)

+                        {

+                            if(0 == ((*(pMain_buf + j)) & (1 << m)))

+                            {

+                                bit_errs++;

+                            }    

+                        }

+

+                        if(bit_errs > 3)

+                        {

+                            goto RETURN1;

+                        }

+                    }

+                }

+

+                if(0 != bit_errs)

+                {

+                    memset(pMain_buf, 0xFF, section_size);

+                }    

+           }

+   

+           break;

+    }

+    

+    return ecc_stat;

+    

+RETURN1:

+    return DATA_ECC_CHECK_ERROR;  

+}

+

+static T_U8 bitnum(T_U32 i)

+{

+    T_U8 ret = 0;

+    for(; (T_U32)(1<<ret) < i; ret++);

+

+    return ret;

+}

+

+static T_U32 ecc_repair(T_U32 wrong_info, T_U8 *main_buf, T_U8 *add_buf, T_U32 main_size, T_U32 add_size, T_U32 ecc_type)

+{

+    

+    T_U32 position = (wrong_info >> 10) & 0xfff;    

+    T_U32 offset;

+    T_U32 byte_index;

+    T_U8  correct;

+    T_U32 shift;

+    T_U32 ecccode_len = nf_get_ecccode_len(ecc_type);

+    T_U32 data_whole_len = main_size + add_size;

+

+    data_whole_len += ecccode_len;

+

+    if (position)

+    {

+        // There are chances that two errors fall into contiguous bits. Then position will have two bits set.

+        // For each bit of position

+        for (shift=0; shift<12; shift++)

+        {

+            if (0 == (position & (1<<shift)))

+            {

+                // no error in this block

+                continue;

+            }

+            

+           

+#if 1  

+           

+            byte_index = data_whole_len + 256 * (((bitnum(position & (1 << shift))) - 6) >> 1) - 3 * 256;

+#else

+            switch (position & (1<<shift))

+            {

+            case (1<<0):

+            case (1<<1):

+                // block1

+                break;

+

+            case (1<<2):

+            case (1<<3):

+                // block2

+                byte_index = data_whole_len - 5 * 256;

+                break;

+

+            case (1<<4):

+            case (1<<5):

+                // block3

+                byte_index = data_whole_len - 4 * 256;

+                break;

+

+            case (1<<6):

+            case (1<<7):

+                // block4

+                byte_index = data_whole_len - 3 * 256;

+                break;

+

+            case (1<<8):

+            case (1<<9):

+                // block5

+                byte_index = data_whole_len - 2 * 256;

+                break;

+

+            case (1<<10):

+            case (1<<11):

+                // block6

+                byte_index = data_whole_len - 1 * 256;

+                break;

+           

+            default:

+                while (1);

+                break;

+            }

+            

+            

+#endif

+            offset = 2 * (wrong_info & 0x3ff) + (((1 << shift) & 0xaaa) ? 1 : 0);            

+

+            byte_index += offset>>3;

+            correct = 1 << (7 - (offset&0x7));

+            

+#ifdef ONLY_WEAK_DANGER_PRINT

+            s_ecc_info.err_loc[s_flip_bits] = byte_index;

+            //akprintf(C3, M_DRVSYS, "byte=%d,s_flip_bits=%d ", s_ecc_info.err_loc[s_flip_bits], s_flip_bits);

+#else

+            printk(KERN_INFO "byte=%d ", byte_index);

+#endif

+

+            if (byte_index < main_size)

+            {

+				// error occurs in data

+				

+#ifdef ONLY_WEAK_DANGER_PRINT

+                s_ecc_info.bad_bytes[s_flip_bits] = main_buf[byte_index];

+                main_buf[byte_index] ^= correct;

+                s_ecc_info.good_bytes[s_flip_bits] = main_buf[byte_index];

+#else

+                main_buf[byte_index] ^= correct;

+#endif

+            }

+            else if (byte_index < (main_size+add_size))

+            {

+				// error occurs in file system info

+				

+#ifdef ONLY_WEAK_DANGER_PRINT

+                s_ecc_info.bad_bytes[s_flip_bits] = add_buf[byte_index - main_size];

+                add_buf[byte_index - main_size] ^= correct;

+                s_ecc_info.good_bytes[s_flip_bits] = add_buf[byte_index - main_size];

+#else

+                add_buf[byte_index - main_size] ^= correct;

+#endif

+            }

+            else

+            {// error occurs in parity data

+                // nothing to do            

+            

+#ifdef ONLY_WEAK_DANGER_PRINT

+                s_ecc_info.good_bytes[s_flip_bits] = s_ecc_info.bad_bytes[s_flip_bits];

+#endif

+            }

+

+            s_flip_bits++;

+            

+        }

+    }

+    return 1;

+}

+

+//************************************************************************************

+/**

+* @BRIEF    check cmd_done bit

+* @AUTHOR   lgj

+* @MODIFY   yiruoxiang

+* @DATE     2006-7-17

+* @PARAM    T_VOID

+* @RETURN

+* @RETVAL

+*/

+static T_BOOL check_cmd_done(T_VOID)

+{

+    volatile unsigned long status;

+        

+    status = *(volatile unsigned long *)(FLASH_CTRL_REG22);

+   // printk(KERN_INFO "zz check_cmd_done status=0x%x\n",status);

+

+    if ( 0 != (REG32(FLASH_CTRL_REG22) & BIT_DMA_CMD_DONE) )

+        return AK_TRUE;

+    else

+        return AK_FALSE;

+}

+

+//*****************************************************************************************

+/**

+ * @brief: start command sequence

+ */

+static T_VOID cmd_go(T_U32 Chip)

+{

+    volatile T_U32 status;

+

+    status = REG32(FLASH_CTRL_REG22);

+    status &= ~( NF_REG_CTRL_STA_CMD_DONE | NF_REG_CTRL_STA_CE0_SEL | NF_REG_CTRL_STA_CE1_SEL); //remove CE flag

+    status |= NCHIP_SELECT(Chip) | DEFAULT_GO;

+    REG32(FLASH_CTRL_REG22) = status;

+}

+

+//*****************************************************************************************

+static T_U32 calc_new(T_U8 data_opt_len, T_U8 data_we_fe, T_U8 data_we_re, T_U8 data_re_fe, T_U8 data_re_re)

+{

+    T_U32 dat_len;

+    

+    if (data_opt_len < 3)

+    {

+        data_opt_len = 3;

+    }

+    

+    if (data_opt_len == data_we_re)

+    {

+        data_we_re--;

+    }

+    

+    if (data_opt_len == data_re_re)

+    {

+        data_re_re--;

+    }

+

+    dat_len = (data_opt_len << 16) | (data_we_fe << 12) | (data_we_re << 8)

+              | (data_re_fe << 4) | (data_re_re << 0);

+

+	if (data_opt_len > 0xf)

+	{

+		printk("Large than 0xf\n");

+		dat_len = 0xF5C5C;

+	}

+

+    return dat_len;

+}

+

diff --git a/drivers/mtd/nand/ak98-nand/nand_control.h b/drivers/mtd/nand/ak98-nand/nand_control.h
new file mode 100755
index 00000000000..d707f5d22c9
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/nand_control.h
@@ -0,0 +1,199 @@
+/**

+ * @filename nand_control.h

+ * @brief AK880x nandflash driver

+ *

+ * This file describe how to control the AK880x nandflash driver.

+ * Copyright (C) 2008 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author yiruoxiang

+ * @modify jiangdihui

+ * @date 2007-1-10

+ * @version 1.0

+ * @ref

+ */

+#ifndef __NAND_CONTORL_H__

+#define __NAND_CONTORL_H__

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @defgroup NandFlash Architecture NandFlash Interface

+ *  @ingroup Architecture

+ */

+/*@{*/

+

+/* contorl/status register */

+#define NF_REG_CTRL_STA_CMD_DONE  (1UL << 31)

+#define NF_REG_CTRL_STA_CE0_SEL   (1 << 10)

+#define NF_REG_CTRL_STA_CE1_SEL   (1 << 11)

+#define NF_REG_CTRL_STA_STA_CLR   (1 << 14)

+

+/* dma cpu control register */

+#define BIT_DMA_CMD_DONE          0x80000000

+

+/* ECC control bit */

+#define ECC_CTL_DIR_READ        (0<<2)

+#define ECC_CTL_ADDR_CLR        (1<<4)

+#define ECC_CTL_NFC_EN          (1<<20)

+#define ECC_CTL_BYTE_CFG(m)     ((m)<<7)  

+#define ECC_CTL_MODE(n)         ((n)<<21)

+#define ECC_CTL_START           (1<<3)

+#define ECC_CTL_DEC_EN          (1<<1)

+#define ECC_CTL_RESULT_NO_OK    (1<<27)

+#define ECC_CTL_END             (1<<6)

+#define ECC_CTL_NO_ERR          (1<<26)

+#define ECC_CTL_DIR_WRITE       (1<<2)

+#define ECC_CTL_ENC_EN          (1<<0)

+#define ECC_CTL_DEC_RDY         (1<<25)

+#define ECC_CTL_ENC_RDY         (1<<24)

+

+#define ECC_CHECK_NO_ERROR                              (0x1<<26)

+#define ECC_ERROR_REPAIR_CAN_NOT_TRUST                  (0x1<<27)

+

+#define DATA_ECC_CHECK_OK                               1

+#define DATA_ECC_CHECK_ERROR                            0

+#define DATA_ECC_ERROR_REPAIR_CAN_TRUST                 2

+#define DATA_ECC_ERROR_REPAIR_CAN_NOT_TRUST             3

+

+//  |               page               |

+//  | data | fs(file system) | parity  |

+//  | data |          spare            |

+#define NAND_DATA_SIZE            512

+#define NAND_FS_SIZE              4

+#define NAND_PARITY_SIZE_MODE5    56    //56 Bytes parity data under 32 bit ecc

+#define NAND_PARITY_SIZE_MODE4    42    //42 Bytes parity data under 24 bit ecc

+#define NAND_PARITY_SIZE_MODE3    28    //28 Bytes parity data under 16 bit ecc

+#define NAND_PARITY_SIZE_MODE2    21    //21 Bytes parity data under 12 bit ecc

+#define NAND_PARITY_SIZE_MODE1    14    //14 Bytes parity data under  8 bit ecc

+#define NAND_PARITY_SIZE_MODE0    7     //7  Bytes parity data under  4 bit ecc

+

+

+/// @cond NANDFLASH_DRV

+//******************************************************************************************//

+//ͨ¹ýCTRL reg0½øÐÐÃüÁîѹջµÄ˵Ã÷ÈçÏ¡££¨¹²7¸öconfiuration£¬1¸öflag£©

+//*************reg0~reg19ÃüÁîµÄÀàÐÍÈçÏÂ***********

+/*

+1,nandflash±¾ÉíÊý¾Ý×ÜÏßÉÏ´«ÊäÊý¾ÝµÄÀàÐÍ

+a,COMMAND_CYCLES_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄÊÇNandflashÃüÁ

+b,ADDRESS_CYCLES_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄÊÇNandflashµØÖ·ÐÅÏ¢

+c,WRITE_DATA_CONF:±íʾÊý¾Ý×ÜÏßÉÏдÈëµÄFIFOÖеÄÊý¾ÝÐÅÏ¢£¬

+ÓÉÓÚ¶Á³öÊý¾Ý¿ÉÄÜ·ÅÔÚ²»Í¬Î»Öã¬ËùÒÔÕâÀïÓÐÁ½ÖÖ¶ÁÊý¾ÝÃüÁî

+d£¬READ_DATA_CONF£º±íʾÊý¾ÝÖÐ×ÜÏ߶ÁÊý¾Ý£¬¶Á³öÊý¾Ý·ÅÔÚFIFOÖÐ

+e£¬READ_CMD_CONFÕâÃüÃûºÃÏñ²»Ì«ºÃ£¬ÎÒ°ÑËü¸ÄΪREAD_INFO_CONF

+  ±íʾÊý¾Ý×ÜÏßÉ϶ÁµÄÊÇ״̬»òÊÇIDÐÅÏ¢Ö¸Áî,(Ò²¿ÉÓÃÓÚ¶ÁȡСÓÚ

+  8 byteµÄÊý¾ÝÁ½£©¶Á³öÊý¾Ý·ÅÔÚreg20

+

+  ÁíÍ⣬Èç¹û´øÉÏECCµÄ¶Á£¬Ð¾Æ¬»á×Ô¶¯°ÑdataÐÅÏ¢ºÍÎļþϵͳÐÅÏ¢·Åµ½Ïà

+  Ó¦µÄFIFOºÍ¼Ä´æÆ÷¡£

+

+2,ÓënandflashÎ޹أ¬ÎªÁËÒýÈëÑÓʱºÍÈ·¶¨¶ÁдԤ´¦ÀíµÈ´ýÍê³ÉʱÒýÈëµÄÃüÁî

+f,DELAY_CNT_CONF ÓÉÓÚnandflash²»»áÂíÉÏÏàÓ¦ÃüÁ´óÔ¼ÓÐ3usµ½50usµÄÑÓʱ£¬

+  Êý¾Ý²Å»á×¼±¸ºÃ£¬ËùÒÔÒýÈë¸ÃÃüÁî¡£ÑÓʱʱ¼äÔÚbit11~bit22ÖÐдÈë

+g.WAIT_JUMP_CONF ÔÚNandflash²Ù×÷ÖУ¬³ýÁË¿ÉÒÔ¶Ástatus Èí¼þ²éѯ״̬Í⣬

+»¹ÓÐÒ»¸öR/BÒý½ÅÓÃÀ´¸¨Öú¿ìËÙÈ·¶¨¶Áд²Ù×÷ÊÇ·ñÍê³É¡£¸ÃÃüÁîµÈ´ýÉÏÌøÑÓ´¥·¢¡£

+

+ÉÏÃæÃüÁîÿ´ÎÈÎÑ¡ÇÒÖ»ÄÜÑ¡Ò»Ìõ£¬²»¶Ïͨ¹ýreg0µØַѹµ½ÃüÁîÕ»ÖУ¬¼´¿ÉʵÏÖ¶Ô

+nandflashµÄËùÓвÙ×÷

+Èç¹ûÊÇ×îºóÒ»ÌõÖ¸Á±ØÐë´òÉÏLAST_CMD_FLAG±êÖ¾

+*/

+

+//////// command sequece configuration define ////////////

+

+/* command cycle's configure:

+ *      CMD_END=X, ALE=0, CLE=1, CNT_EN=0,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define COMMAND_CYCLES_CONF     0x64

+/* address cycle's:

+ *      CMD_END=X, ALE=1, CLE=0, CNT_EN=0,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define ADDRESS_CYCLES_CONF     0x62

+

+/*  read data cycle's:

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=1, WEN=0, CMD_EN=0, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define READ_DATA_CONF          0x118

+

+/*  write data cycle's:

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=0, WEN=1, CMD_EN=0, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=1, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define WRITE_DATA_CONF         0x128

+

+/* read command status's:(example: read ID(pass), status(pass), »Ø¶ÁÊý¾Ý±È½ÏÉٵIJÙ×÷?

+//¸æËßоƬÏÖÔÚ¶ÁÈ¡status IDÐÅÏ¢£¬Ð¾Æ¬°Ñ¸ÃÐÅÏ¢°áµ½ÏàÓ¦¼Ä´æÆ÷(8 byte)£¬¶ø²»ÊÇFIFO¡£·½±ã²éѯNandflash״̬¡£

+ *      CMD_END=X, ALE=0, CLE=0, CNT_EN=1,  (BIT[0:3])

+ *      REN=1, WEN=0, CMD_EN=1, STAFF_EN=0, (BIT[4:7])

+ *      DAT_EN=0, RBN_EN=0, CMD_WAIT=0,     (BIT[8:10])

+ */

+#define READ_INFO_CONF          0x58

+

+//wait delay time enable bit

+#define DELAY_CNT_CONF          (1<<10)

+

+//wait R/b enable bit

+#define WAIT_JUMP_CONF          (1<<9)

+

+// last command's bit0 set to 1

+#define LAST_CMD_FLAG           (1<<0)

+

+

+//#######excute comamnd,ctrl reg22 command configuration define ################

+//ËùÓеÄÅäÖö¨ÒåÕë¶Ô·¢ËÍÃüÁîµÄ·½Ê½¡£

+//±ØÐë½øÐÐƬѡ»òƬ±£»¤¡¢²Ù×÷ģʽ¡¢ÒÔ¼°ÊÇ·ñʹÄܵÄÊ¡µçģʽflag

+//ƬѡʹÓúêNCHIP_SELECT(x)

+#define NCHIP_SELECT(x)         ((0x01 << (x)) << 10)

+

+/*

+bit0(save mode) = 0;

+bit1-bit8(staff_cont)=0

+bit9(watit save mode jump) = 0

+bit10-bit13(chip select)=0

+bit14(sta_clr)=0

+bit15-bit18(write protect)=0

+bit19-bit29 reserved =0;

+bit30(start control) = 1;

+bit31(check statu) = 0;

+*/

+#define DEFAULT_GO              ((1 << 30)|(1<<9))

+

+

+/** @{@name Command List and Status define

+ *  Define command set and status of nandflash

+ */

+#define NFLASH_READ1                0x00

+#define NFLASH_READ2                0x30

+#define NFLASH_READ1_HALF           0x01

+#define NFLASH_READ22               0x50

+

+#define NFLASH_COPY_BACK_READ       0x35

+#define NFLASH_COPY_BACK_WRITE      0x85

+#define NFLASH_COPY_BACK_WRITE1     0x8A

+#define NFLASH_COPY_BACK_CONFIRM    0x10

+#define NFLASH_RESET                0xff

+

+#define NFLASH_FRAME_PROGRAM0       0x80

+#define NFLASH_FRAME_PROGRAM1       0x10

+

+#define NFLASH_BLOCK_ERASE0         0x60

+#define NFLASH_BLOCK_ERASE1         0xD0

+#define NFLASH_STATUS_READ          0x70

+#define NFLASH_READ_ID              0x90

+

+//status register bit

+#define NFLASH_PROGRAM_SUCCESS      0x01 //bit 0

+#define NFLASH_HANDLE_READY         0x40 //bit 6

+#define NFLASH_WRITE_PROTECT        0x80 //bit 7

+

+/*@}*/

+#ifdef __cplusplus

+}

+#endif

+

+#endif //__NAND_CONTORL_H__

diff --git a/drivers/mtd/nand/ak98-nand/sysctl.h b/drivers/mtd/nand/ak98-nand/sysctl.h
new file mode 100644
index 00000000000..852230d3b5f
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/sysctl.h
@@ -0,0 +1,91 @@
+/**

+* @FILENAME sysctl.h

+*

+* Copyright (C) 2006 Anyka (Guangzhou) Software Technology Co., LTD

+* @DATE  2006-04-19

+* @VERSION 1.0

+* @REF 

+*/

+

+#ifndef __SYSCTL_H__

+#define __SYSCTL_H__

+

+/*ÒÔ϶¨ÒåµÄclock Ä£¿é±ØÐë¶ÀÁ¢£¬²»ÄÜÒ»¸öÄ£¿é°üº¬¶à¸ö¿É¿ØÖÆclockµÄ×ÓÄ£¿é*/

+#define CLOCK_DEFAULT_ENABLE                        (0)

+#define CLOCK_CAMERA_ENABLE                         (1<<0)

+#define CLOCK_LCD_ENABLE                            (1<<1)

+#define CLOCK_USB_ENABLE                            (1<<2)

+#define CLOCK_MMCSD_ENABLE                          (1<<3)

+#define CLOCK_UART0_ENABLE                          (1<<4)

+#define CLOCK_UART1_ENABLE                          (1<<5)

+#define CLOCK_UART2_ENABLE                          (1<<6)

+#define CLOCK_UART3_ENABLE                          (1<<7)

+#define CLOCK_SDIO_ENABLE                           (1<<8)

+#define CLOCK_SPI_ENABLE                            (1<<9)

+#define CLOCK_NAND_ENABLE                           (1<<10)

+#define CLOCK_NBITS                                 (11)

+#define CLOCK_ENABLE_MAX                            (1<<CLOCK_NBITS)

+

+/** CLOCK control register bit map*/

+#define CLOCK_CTRL_IMAGE_H263_MPEG4                 (0x1)

+#define CLOCK_CTRL_CAMERA                           (1 << 1)

+#define CLOCK_CTRL_SPI12_MMC_UART2                  (1 << 2)

+#define CLOCK_CTRL_LCD                              (1 << 3)

+#define CLOCK_CTRL_AUDIO                            (1 << 4)

+#define CLOCK_CTRL_USBOTG                           (1 << 5)

+#define CLOCK_CTRL_H264                             (1 << 6)

+#define CLOCK_CTRL_USBFS                            (1 << 7)

+#define CLOCK_CTRL_SDIO_UART34                      (1 << 8)

+#define CLOCK_CTRL_SDRAM_DDR                        (1 << 10)

+#define CLOCK_CTRL_MOTION_MODULE                    (1 << 11)

+#define CLOCK_CTRL_2D_ACCELERATOR                   (1 << 12)

+#define CLOCK_CTRL_NANDFLASH                        (1 << 13)

+#define CLOCK_CTRL_L2_UART1                         (1 << 15)

+

+#define RESET_IMAGE_PROCESS                         (1<<16)

+#define RESET_CAMERA                                (1<<17)

+#define RESET_SPI                                   (1<<18)

+#define RESET_SDMMC                                 (1<<18)

+#define RESET_PCM                                   (1<<18)

+#define RESET_UART2                                 (1<<18)

+#define RESET_LCD                                   (1<<19)

+#define RESET_GPS                                   (1<<20)

+#define RESET_USB_OTG                               (1<<21)

+#define RESET_H264_DECODER                          (1<<22)

+#define RESET_USB_FS                                (1<<23)

+#define RESET_SDIO                                  (1<<24)

+#define RESET_UART3                                 (1<<24)

+#define RESET_UART4                                 (1<<24)

+#define RESET_RAM                                   (1<<26)

+#define RESET_MOTION_ESTIMATE                       (1<<27)

+#define RESET_GRAPHICS                              (1<<28)

+#define RESET_NANDFLASH                             (1<<29)

+#define RESET_L2                                    (1<<31)

+#define RESET_UART1                                 (1<<31)

+

+

+/**

+ * @BRIEF Set SleepMode

+ * @AUTHOR guoshaofeng

+ * @DATE 2007-04-23

+ * @PARAM[in] T_U32 module

+ * @RETURN T_VOID

+ * @RETVAL

+ * attention: if you close some parts such as LCD 

+            you must init it again when you reopen 

+            it 

+            some settings may cause serious result

+            better not to use it if not familar

+ */

+T_VOID sysctl_clock(T_U32 module);

+

+/**

+ * @brief reset module 

+ * @author guoshaofeng

+ * @date 2010-07-20

+ * @param module [in]: module to be reset

+ * @return T_VOID

+ */

+T_VOID sysctl_reset(T_U32 module);

+

+#endif //__SYSCTL_H__
\ No newline at end of file
diff --git a/drivers/mtd/nand/ak98-nand/wrap_nand.c b/drivers/mtd/nand/ak98-nand/wrap_nand.c
new file mode 100755
index 00000000000..aaef0fb529f
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/wrap_nand.c
@@ -0,0 +1,981 @@
+/**

+ * @filename wrap_nand.c

+ * @brief AK880x nandflash driver

+ *

+ * This file wrap the nand flash driver in nand_control.c file.

+ * Copyright (C) 2010 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author zhangzheng

+ * @modify 

+ * @date 2010-10-10

+ * @version 1.0

+ * @ref

+ */

+

+#include <linux/list.h>

+#include <linux/init.h>

+#include <linux/mtd/partitions.h>

+#include <linux/math64.h>

+#include <mtd/mtd-abi.h>

+#include "anyka_cpu.h"

+#include "nand_control.h"

+#include "wrap_nand.h"

+

+#define YAFFS_OOB_SIZE_LARGE            28

+#define YAFFS_OOB_SIZE_LITTLE		8	//lgh

+

+#define PASSWORD_ADDR_OFFSET	    (4)

+#define PASSWORD_STR			    "ANYKA783"                 

+#define PASSWORD_LENGTH			    (sizeof(PASSWORD_STR) - 1) 

+

+#define ZZ_DEBUG                    0

+#define NAND_BOOT_DATA_SIZE         472

+

+

+extern int page_shift;

+extern struct mtd_info *g_master;

+

+

+T_Nandflash_Add g_sNF = {

+							{0,0,0,0}, 

+							3, 

+							2, 

+							NAND_8K_PAGE, 

+							ECC_24BIT_P1KB, 

+							8192, 

+							128

+					    };

+

+/*

+	T_Nandflash_Add g_sNF = {

+								{0,0,0,0}, 

+								3, 

+								2, 

+								NAND_2K_PAGE, 

+								ECC_4BIT_P512B, 

+								2048, 

+								128

+							};

+*/

+/*

+	T_Nandflash_Add g_sNF = {

+								{0,0,0,0}, 

+								3, 

+								1, 

+								NAND_512B_PAGE, 

+								ECC_4BIT_P512B, 

+								512, 

+								32

+							};

+*/

+

+

+T_NAND_PHY_INFO *g_pNand_Phy_Info = NULL;

+

+#ifdef CONFIG_MTD_NAND_TEST   

+T_U32 *nand_erase_test = NULL;

+T_U32 nand_total_blknum = 0;

+#endif

+

+#if 1

+T_PNandflash_Add g_pNF = NULL;

+#else

+T_PNandflash_Add g_pNF = &g_sNF;

+#endif 

+

+T_PFHA_INIT_INFO g_pinit_info = NULL;

+T_PFHA_LIB_CALLBACK g_pCallback = NULL;

+T_U8 *nand_data_buf = NULL;

+

+T_Nandflash_Add try_nf_add[] = 

+{

+    {{0,0,0,0}, 3, 2, NAND_8K_PAGE, ECC_24BIT_P1KB, 8192, 128},

+	{{0,0,0,0}, 3, 2, NAND_4K_PAGE, ECC_8BIT_P512B, 4096, 128},

+	{{0,0,0,0}, 2, 1, NAND_512B_PAGE, ECC_8BIT_P512B, 512, 128},

+	{{0,0,0,0}, 2, 1, NAND_512B_PAGE, ECC_8BIT_P512B, 512, 128}

+};

+

+int init_fha_lib(void)

+{

+	int retval = 0;

+	

+	g_pinit_info = kmalloc(sizeof(T_FHA_INIT_INFO), GFP_KERNEL);

+	if(g_pinit_info == NULL)

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 71 g_pinit_info==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+

+	g_pinit_info->nChipCnt = 1;

+	g_pinit_info->nBlockStep = 1;

+	g_pinit_info->eAKChip = FHA_CHIP_980X;

+	g_pinit_info->ePlatform = PLAT_LINUX;

+	g_pinit_info->eMedium = MEDIUM_NAND;

+	g_pinit_info->eMode = 0;

+			

+	g_pCallback = kmalloc(sizeof(T_FHA_LIB_CALLBACK), GFP_KERNEL);

+	if(g_pCallback == NULL)

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 85 g_pCallback==NULL\n");

+		return FHA_FAIL;

+	}

+	g_pCallback->Erase = nand_erase_callback;

+	g_pCallback->Write = (FHA_Write)nand_write_callback;

+	g_pCallback->Read = (FHA_Read)nand_read_callback;

+	g_pCallback->RamAlloc = ram_alloc;

+	g_pCallback->RamFree = ram_free;

+	g_pCallback->MemCmp = (FHA_MemCmp)memcmp;

+	g_pCallback->MemSet = (FHA_MemSet)memset;

+	g_pCallback->MemCpy = (FHA_MemCpy)memcpy;

+	g_pCallback->Printf = (FHA_Printf)printk; //print_callback;

+	//g_pCallback->Printf = (FHA_Printf)printk_my; //print_callback;		//lgh

+	g_pCallback->ReadNandBytes = nand_read_bytes_callback;

+

+	#ifndef CONFIG_MTD_DOWNLOAD_MODE

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 101 before FHA_mount()\n");

+	#endif

+	

+	retval = FHA_mount(g_pinit_info, g_pCallback, AK_NULL);

+

+	if (retval)

+	{

+		

+		if(init_globe_para() == AK_FALSE)

+		{

+            printk(KERN_INFO " init_fha_lib() init_globe_para!!!\n");

+		    return FHA_FAIL;

+		}

+	}

+	else

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() FHA_mount return:%d error!!!\n", retval);

+		return FHA_FAIL;

+	}

+	

+	FHA_asa_scan(AK_TRUE);

+	#else

+	if(g_pNand_Phy_Info == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c init_fha_lib() 120 g_pNand_Phy_Info==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+	

+	retval =  FHA_burn_init(g_pinit_info, g_pCallback, g_pNand_Phy_Info);

+	FHA_asa_scan(AK_TRUE);

+	#endif

+

+	if(retval == FHA_FAIL)

+	{

+		kfree(g_pinit_info);

+		kfree(g_pCallback);

+		g_pinit_info = NULL;

+		g_pCallback = NULL;

+		printk(KERN_INFO "zz wrap_nand.c init_fha_lib() 134 failed!!!\n");

+	}	

+

+    nand_data_buf = kmalloc(g_pNF->PageSize, GFP_KERNEL);

+    if(nand_data_buf == NULL)

+    {

+        printk(KERN_NOTICE "nand_data_buf malloc fail!!!\n");

+        return FHA_FAIL;

+    }

+    

+	return retval;

+}

+

+

+void Nand_Config_Data_Spare(T_PNAND_ECC_STRU data_ctrl, T_U8* data, T_U32 data_len, ECC_TYPE ecc_type,

+							    T_PNAND_ECC_STRU spare_ctrl, T_U8* spare, T_U32 spare_len)

+{

+   	data_ctrl->buf = data;   

+    	data_ctrl->buf_len = data_len;

+    	data_ctrl->ecc_type = ecc_type;		

+		

+    	spare_ctrl->buf = spare;

+    	spare_ctrl->buf_len= spare_len;

+    	spare_ctrl->ecc_type = (ecc_type > ECC_12BIT_P512B) ? ECC_12BIT_P512B : ecc_type;	

+		

+	if(g_pNF->PageSize < NAND_PAGE_SIZE_2KB){			

+		//printk(KERN_INFO "%s:line %d: brached to 512Byte/page\n", __func__, __LINE__);

+		if(spare_len > 9)	

+			printk(KERN_ERR "%s:%d:spare length is %lu! It should be less @@9Bytes@@\n", __func__, __LINE__, spare_len);		

+	    	data_ctrl->ecc_section_len =  data_len +  spare_len;

+	    	spare_ctrl->ecc_section_len = data_len + spare_len;			

+	}

+	else{	

+	    	data_ctrl->ecc_section_len = (ecc_type > ECC_12BIT_P512B) ? NAND_DATA_SIZE_P1KB : NAND_DATA_SIZE_P512B;

+    		spare_ctrl->ecc_section_len = spare_len;			

+	}

+	/*

+	printk(KERN_INFO "data_ctrl: buf=%p, buf_len=%lu, ecc_section_len=%lu, ecc_type=%d\n", \

+		data_ctrl->buf, data_ctrl->buf_len, data_ctrl->ecc_section_len, data_ctrl->ecc_type);

+   	printk(KERN_INFO "spare_ctrl: buf=%p, buf_len=%lu, ecc_section_len=%lu, ecc_type=%d\n", \

+		spare_ctrl->buf, spare_ctrl->buf_len, spare_ctrl->ecc_section_len, spare_ctrl->ecc_type);	

+	*/

+

+} 

+

+void ak_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    struct nand_chip *chip = mtd->priv;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_write_buf() 176 g_pNF==NULL error!!!\n");

+		return;

+	}

+    	//Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	//Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+	if(g_pNF->PageSize < NAND_PAGE_SIZE_2KB)

+		Nand_Config_Data_Spare(	&data_ctrl, (T_U8 *)buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 8, YAFFS_OOB_SIZE_LITTLE);

+	else

+		Nand_Config_Data_Spare(	&data_ctrl, (T_U8 *)buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE_LARGE);

+	nand_writepage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);  

+}

+

+void ak_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    struct nand_chip *chip = mtd->priv;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_buf() 195 g_pNF==NULL error!!!\n");

+		return;

+	}

+    	//Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	//Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+	if(g_pNF->PageSize < NAND_PAGE_SIZE_2KB)

+		Nand_Config_Data_Spare(	&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 8, YAFFS_OOB_SIZE_LITTLE);

+	else

+		Nand_Config_Data_Spare(	&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE_LARGE);	

+    nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);   

+}

+

+void ak_nand_select_chip(struct mtd_info *mtd, int chip)

+{

+

+}

+

+static void ak_nand_config_timeseq(unsigned long cmd_len, unsigned long data_len)

+{

+    nand_settiming(cmd_len, data_len);    

+}

+u_char ak_nand_read_byte(struct mtd_info *mtd)

+{

+    T_U32 retval = 0;

+    return (u_char)retval;

+}

+

+int ak_nand_scan_bbt(struct mtd_info *mtd)

+{

+    /*because FHA_asa_scan has built the bbt ,so we should not to do anything*/

+    return 1; 

+}

+

+

+int ak_nand_init_size(struct mtd_info *mtd, struct nand_chip *chip,

+			u8 *id_data)

+{

+    int busw;

+

+    if (g_pNand_Phy_Info != AK_NULL)

+    {

+        mtd->writesize = g_pNand_Phy_Info->page_size;                                

+        mtd->erasesize = g_pNand_Phy_Info->page_size * g_pNand_Phy_Info->page_per_blk; 

+    }

+    else

+    {

+        printk("g_pNand_Phy_Info is NULL, init size fail!\n");

+        BUG();

+    }

+    

+    mtd->oobsize = 128;     //only save yaffs2 filesystem information.

+    busw = (chip->options & (1 << 1)) ? NAND_BUSWIDTH_16 : 0;

+   // printk("hy write=%u,erasesize =%u, busw=%d####\n",mtd->writesize,mtd->erasesize,busw);

+    return busw;

+}

+

+int ak_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                   uint8_t *buf, int page)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_page_hwecc() 224 g_pNF==NULL error!!!\n");

+		return 1;

+	} 

+ 	//Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	//Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+	if(g_pNF->PageSize < NAND_PAGE_SIZE_2KB)

+		Nand_Config_Data_Spare(	&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 8, YAFFS_OOB_SIZE_LITTLE);

+	else 

+		Nand_Config_Data_Spare(	&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE_LARGE);

+    return nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);

+}

+

+void ak_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                     const uint8_t *buf)

+{

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page_shift; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_write_page_hwecc() 242 g_pNF==NULL error\n");

+		return;

+	}

+	//Nand_Config_Data(&data_ctrl, buf, g_pNF->PageSize, g_pNF->EccType);

+	//Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+	if(g_pNF->PageSize < NAND_PAGE_SIZE_2KB)

+		Nand_Config_Data_Spare(	&data_ctrl, (T_U8 *)buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 8, YAFFS_OOB_SIZE_LITTLE);

+	else 

+		Nand_Config_Data_Spare(	&data_ctrl, (T_U8 *)buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE_LARGE);	

+

+

+	nand_writepage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);

+}

+

+int ak_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+			                    uint8_t *buf, int pag)

+{

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_read_page_raw() 254\n");

+	#endif

+    return 0;

+}

+

+void ak_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+				                  const uint8_t *buf)

+{

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_write_page_raw() 263\n");

+	#endif

+}

+

+int ak_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page, int sndcmd)

+{      

+    T_U32 chip_num = 0;

+    T_U32 row_addr = page; 

+    T_U32 clm_addr = 0;

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	

+    if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c ak_nand_read_oob() 280 g_pNF==NULL error!!!\n");

+		return 1;

+	}

+    if (sndcmd) 

+    {

+		chip->cmdfunc(mtd, 0x50, 0, page); //0x50 read oob cmd

+		sndcmd = 0;

+	}

+	//Nand_Config_Data(&data_ctrl, oob_data_buf, g_pNF->PageSize, g_pNF->EccType);

+	//Nand_Config_Spare(&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE, g_pNF->EccType);

+		

+	if(g_pNF->PageSize  < NAND_PAGE_SIZE_2KB)

+		Nand_Config_Data_Spare(	&data_ctrl, nand_data_buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 8, YAFFS_OOB_SIZE_LITTLE);

+	else

+		Nand_Config_Data_Spare(	&data_ctrl, nand_data_buf, g_pNF->PageSize, g_pNF->EccType,\

+								&spare_ctrl, chip->oob_poi + 2, YAFFS_OOB_SIZE_LARGE);	

+	

+    nand_readpage_ecc(chip_num, row_addr, clm_addr, g_pNF, &data_ctrl, &spare_ctrl);   

+	return sndcmd;

+}

+

+int ak_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page)

+{

+    return 0;

+}

+

+T_U32 nand_erase_callback(T_U32 chip_num,  T_U32 startpage)

+{

+	int ret;

+

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_erase_callback() 304 g_pNF==NULL error\n");

+		return 1;

+	}

+

+	ret = nand_eraseblock(chip_num, startpage, g_pNF);

+	/* Chang the return value to adapt the fha library */

+	if (ret == 0)

+		return 1;

+	else

+		return 0;

+}

+

+T_U32 nand_read_callback(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType)

+{

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	int i = 0;

+	T_U32 boot_page_size = 0;

+	int try_count = sizeof(try_nf_add)/sizeof(try_nf_add[0]);

+

+	if(eDataType == FHA_GET_NAND_PARAM)

+	{

+		#if ZZ_DEBUG

+		printk(KERN_INFO "zz wrap_nand.c nand_read_callback() 321 eDataType == FHA_GET_NAND_PARAM\n");

+		#endif

+		for(i=0; i<try_count; i++)

+		{	

+			#if ZZ_DEBUG

+			printk(KERN_INFO "i=%d row_cycle=%d col_cycle=%d chip_type=%d ecc_type=%d page_size=%lu PagesPerBlock=%lu\n",

+			       i, try_nf_add[i].RowCycle, try_nf_add[i].ColCycle, try_nf_add[i].ChipType, try_nf_add[i].EccType,

+			       try_nf_add[i].PageSize, try_nf_add[i].PagesPerBlock);

+			#endif

+			if(AK_TRUE== try_nand_para(chip_num, page_num, data, data_len, oob, oob_len, &try_nf_add[i]))

+			{

+				#if ZZ_DEBUG

+				printk(KERN_INFO "zz wrap_nand.c nand_read_callback() 333 try nand para successed i=%d\n", i);

+				#endif

+				return FHA_SUCCESS;

+			}

+		}

+		return FHA_FAIL;

+				

+	}

+	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_read_callback() 357 g_pNF==NULL error\n");

+		return FHA_FAIL;

+	}

+		

+    if(eDataType == FHA_DATA_BOOT)

+    {

+        boot_page_size = (data_len > 4096) ? 4096 : data_len;

+

+        if (0 == page_num)

+        {

+            data_ctrl.buf = data;

+        	data_ctrl.buf_len = NAND_BOOT_DATA_SIZE;

+        	data_ctrl.ecc_section_len = NAND_BOOT_DATA_SIZE;

+        	data_ctrl.ecc_type = ECC_32BIT_P1KB;                   

+        }

+    	else

+    	{

+            data_ctrl.buf = data;

+            data_ctrl.buf_len = boot_page_size;

+            data_ctrl.ecc_section_len = 512;

+            data_ctrl.ecc_type = g_pNF->EccType;

+    	}

+

+        nand_readpage_ecc(0, page_num, 0, g_pNF, &data_ctrl, AK_NULL);        

+    }

+	else

+	{

+    		//Nand_Config_Data(&data_ctrl, data, data_len, g_pNF->EccType);

+		//Nand_Config_Spare(&spare_ctrl, oob, oob_len, g_pNF->EccType);

+		if(g_pNF->PageSize  < NAND_PAGE_SIZE_2KB)

+			Nand_Config_Data_Spare(	&data_ctrl, data, data_len, g_pNF->EccType,\

+									&spare_ctrl, oob, oob_len);

+		else

+			Nand_Config_Data_Spare(	&data_ctrl, data, data_len, g_pNF->EccType,\

+									&spare_ctrl, oob, oob_len);		

+		nand_readpage_ecc(chip_num, page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);

+	}     

+	

+	return FHA_SUCCESS;

+}

+

+T_U32 nand_write_callback(T_U32 chip_num, T_U32 page_num, const T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType)

+{ 

+    T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+    T_U32 boot_page_size = 0;

+  	

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz wrap_nand.c nand_write_callback() 404 g_pNF==NULL error!!!\n");

+		return FHA_FAIL;

+	}

+   

+    if(eDataType == FHA_DATA_BOOT)

+    {

+        boot_page_size = (data_len > 4096) ? 4096 : data_len;

+        

+        if (0 == page_num)

+        {

+            data_ctrl.buf = data;

+            data_ctrl.buf_len = NAND_BOOT_DATA_SIZE;

+            data_ctrl.ecc_section_len = NAND_BOOT_DATA_SIZE;

+            data_ctrl.ecc_type = ECC_32BIT_P1KB;

+        }

+        else

+        {                    

+            data_ctrl.buf = data;

+            data_ctrl.buf_len = boot_page_size;

+            data_ctrl.ecc_section_len = 512;

+            data_ctrl.ecc_type = g_pNF->EccType;

+        }

+        

+    	nand_writepage_ecc(0, page_num, 0, g_pNF, &data_ctrl, AK_NULL);     	

+    }

+	else

+	{		

+    	//Nand_Config_Data(&data_ctrl, data, data_len, g_pNF->EccType);

+		//Nand_Config_Spare(&spare_ctrl, oob, oob_len, g_pNF->EccType);

+		if(g_pNF->PageSize  < NAND_PAGE_SIZE_2KB)

+			Nand_Config_Data_Spare(	&data_ctrl, data, data_len, g_pNF->EccType,\

+									&spare_ctrl, oob, oob_len);

+		else

+			Nand_Config_Data_Spare(	&data_ctrl, data, data_len, g_pNF->EccType,\

+									&spare_ctrl, oob, oob_len);	

+	

+		nand_writepage_ecc(chip_num, page_num, 0, g_pNF, &data_ctrl, &spare_ctrl);

+	}	

+    

+	return FHA_SUCCESS;

+}

+

+T_U32 nand_read_bytes_callback(T_U32 nChip, T_U32 rowAddr, T_U32 columnAddr, T_U8 *pData, T_U32 nDataLen)

+{

+	return nand_readbytes(nChip, rowAddr, columnAddr, g_pNF, pData, nDataLen);

+}

+

+void *ram_alloc(T_U32 size)

+{

+	return kmalloc(size, GFP_KERNEL);

+}

+

+void *ram_free(void *point)

+{

+	kfree(point);

+	return NULL;

+}

+

+T_S32 print_callback(T_pCSTR s, ...)

+{

+	printk(KERN_INFO "%s", s);

+	return AK_TRUE;

+}

+

+

+T_U32 init_globe_para(void)

+{

+	int ret = AK_FALSE;	

+

+	if(g_pNand_Phy_Info != NULL && g_pNF != NULL)

+	{

+		return AK_TRUE;

+	}

+	g_pNand_Phy_Info = kmalloc(sizeof(T_NAND_PHY_INFO), GFP_KERNEL);

+	if(g_pNand_Phy_Info == NULL)

+	{

+		printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 471 g_pNand_Phy_Info=NULL error!!!\n");

+		return AK_FALSE;

+	}

+	

+	if(g_pinit_info!=NULL && g_pCallback!=NULL)

+	{		

+	

+		ret = FHA_get_nand_para(g_pNand_Phy_Info);	

+		

+		if(ret == AK_FALSE)

+		{

+			printk(KERN_INFO "zz wrap_nand.c init_globe_para() 482 get nand para with fha lib error!!!\n");

+			return AK_FALSE;

+		}

+	}

+	else

+	{

+		printk(KERN_INFO "zz wrap_nand.c init_globe_para() 488 init fha lib fail!!!\n");

+		return AK_FALSE;

+	}

+	

+

+	g_pNF = kmalloc(sizeof(T_Nandflash_Add), GFP_KERNEL);

+	if(g_pNF == NULL)

+	{

+		printk(KERN_NOTICE "zz nand_char.c nand_char_ioctl() 496 g_pNF==NULL error!!!\n");

+		return AK_FALSE;

+	}

+	g_pNF->RowCycle      = g_pNand_Phy_Info->row_cycle;

+	g_pNF->ColCycle      = g_pNand_Phy_Info->col_cycle;

+	g_pNF->PageSize      = g_pNand_Phy_Info->page_size;

+	g_pNF->PagesPerBlock = g_pNand_Phy_Info->page_per_blk;

+	g_pNF->EccType       = (T_U8)((g_pNand_Phy_Info->flag & 0xf0) >> 4);  //4-7 bit is ecc type	

+    

+	switch(g_pNand_Phy_Info->page_size)

+	{

+		case 512:

+		{		

+			g_pNF->ChipType = NAND_512B_PAGE;

+			break;

+		}

+		case 2048:

+		{

+			g_pNF->ChipType = NAND_2K_PAGE;

+			break;

+		}

+		case 4096:

+		{

+			g_pNF->ChipType = NAND_4K_PAGE;

+			break;

+		}	

+		case 8192:

+		{

+			g_pNF->ChipType = NAND_8K_PAGE;

+			break;

+		}

+		default:

+		{

+			printk(KERN_INFO "zz wrap_nand.c init_globe_para() 529 g_pNand_Phy_Info->page_size=%d Error!!!\n",

+				   g_pNand_Phy_Info->page_size);

+		}

+	}

+

+	ak_nand_config_timeseq(g_pNand_Phy_Info->cmd_len, g_pNand_Phy_Info->data_len);

+	

+	printk(KERN_INFO "---------------------zz wrap_nand.c init_globe_para() 535------------------------\n");

+	printk(KERN_INFO "----------------------------Nand Physical Parameter------------------------------\n");

+	printk(KERN_INFO "chip_id = 0x%08lx\n", g_pNand_Phy_Info->chip_id);

+	printk(KERN_INFO "page_size = %d\n", g_pNand_Phy_Info->page_size);

+	printk(KERN_INFO "page_per_blk = %d\n", g_pNand_Phy_Info->page_per_blk);

+	printk(KERN_INFO "blk_num = %d\n", g_pNand_Phy_Info->blk_num);

+	printk(KERN_INFO "group_blk_num = %d\n", g_pNand_Phy_Info->group_blk_num);

+	printk(KERN_INFO "plane_blk_num = %d\n", g_pNand_Phy_Info->plane_blk_num);

+	printk(KERN_INFO "spare_size = %d\n", g_pNand_Phy_Info->spare_size);

+	printk(KERN_INFO "col_cycle = %d\n", g_pNand_Phy_Info->col_cycle);

+	printk(KERN_INFO "lst_col_mask = %d\n", g_pNand_Phy_Info->lst_col_mask);

+	printk(KERN_INFO "row_cycle = %d\n", g_pNand_Phy_Info->row_cycle);

+	printk(KERN_INFO "delay_cnt = %d\n", g_pNand_Phy_Info->delay_cnt);

+	printk(KERN_INFO "custom_nd = %d\n", g_pNand_Phy_Info->custom_nd);

+	printk(KERN_INFO "flag = 0x%08lx\n", g_pNand_Phy_Info->flag);

+	printk(KERN_INFO "cmd_len = 0x%lx\n", g_pNand_Phy_Info->cmd_len);

+	printk(KERN_INFO "data_len = 0x%lx\n", g_pNand_Phy_Info->data_len);

+	printk(KERN_INFO "---------------------------------------------------------------------------------\n");

+	

+	return AK_TRUE;

+}

+

+void free_globe_para(void)

+{

+    if(g_pNand_Phy_Info != AK_NULL)

+    {

+        kfree(g_pNand_Phy_Info);

+        g_pNand_Phy_Info = AK_NULL;

+    }

+

+    if(g_pNF != AK_NULL)

+    {

+        kfree(g_pNF);

+        g_pNF = AK_NULL;

+    }

+

+    if(nand_data_buf != AK_NULL)

+    {

+        kfree(nand_data_buf);

+        nand_data_buf = AK_NULL;

+    }

+}

+

+

+#ifdef CONFIG_MTD_NAND_TEST   

+void nand_balance_test_init(void)

+{

+    if (nand_erase_test)

+        kfree(nand_erase_test);

+

+    nand_total_blknum = g_pNand_Phy_Info->blk_num;

+    nand_erase_test = (T_U32 *)kmalloc(nand_total_blknum*sizeof(T_U32), GFP_KERNEL);

+    memset(nand_erase_test, 0, nand_total_blknum*sizeof(T_U32));

+    //printk("nand_totalblk=%d##########\n",nand_total_blknum);

+}

+

+void nand_balance_test_exit(void)

+{

+    if (nand_erase_test)

+    {

+        kfree(nand_erase_test);

+        nand_erase_test = NULL;

+    }

+}

+#endif

+

+T_U32 ak_mount_partitions(void)

+{

+	int i = 0;

+	T_U8 *fs_info = NULL;

+	int part_cnt = 0;

+	struct partitions *parts = NULL;

+	struct mtd_partition *pmtd_part = NULL;

+	

+	if(g_pinit_info!=NULL && g_pCallback!=NULL)

+	{

+		fs_info = kmalloc(g_pNF->PageSize, GFP_KERNEL);

+		FHA_get_fs_part(fs_info, g_pNF->PageSize);

+		part_cnt = *((int *)fs_info);  //calculate how many partitions

+		#if ZZ_DEBUG

+		printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 573 part_cnt=%d\n", part_cnt);

+		#endif

+		if(part_cnt == 0)

+		{

+			printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 577 part_cnt==0 error!!!\n");

+			return AK_FALSE;

+		}

+		

+		pmtd_part = kmalloc(sizeof(struct mtd_partition) * part_cnt, GFP_KERNEL);

+		if(pmtd_part == NULL)

+		{

+			printk(KERN_INFO "zz wrap_nand.c ak_mount_partitions() 584 pmtd_part==NULL error!!!\n");

+			return AK_FALSE;

+		}		

+		

+		parts = (struct partitions *)(&fs_info[4]);

+		

+		for(i=0; i<part_cnt; i++)

+		{	

+			pmtd_part[i].name= kmalloc(MTD_PART_NAME_LEN, GFP_KERNEL);

+			memcpy(pmtd_part[i].name, parts[i].name, MTD_PART_NAME_LEN);

+			pmtd_part[i].size = parts[i].size;

+			pmtd_part[i].offset = parts[i].offset;

+			pmtd_part[i].mask_flags = parts[i].mask_flags;			

+			printk(KERN_INFO "pmtd_part[%d]:\nname = %s\nsize = 0x%llx\noffset = 0x%llx\nmask_flags = 0x%x\n\n", 

+					i, 

+					pmtd_part[i].name, 

+					pmtd_part[i].size,

+					pmtd_part[i].offset,

+					pmtd_part[i].mask_flags

+				  );			

+		}		

+		

+		add_mtd_partitions(g_master, (const struct mtd_partition *)pmtd_part, part_cnt);		

+		kfree(pmtd_part);

+		kfree(fs_info);

+	}

+	else

+	{

+		printk(KERN_INFO "ak_mount_partitions() init fha lib failed!!!\n");

+	}

+

+	return AK_TRUE;

+	

+}

+

+int ak_nand_block_isbad(struct mtd_info *mtd, loff_t offs, int getchip)

+{

+	T_U32 blk_no = 0;

+	T_U32 ret = 0;

+

+	if (offs > mtd->size)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 658 offs=0x%llx Error!!!\n", offs);

+		return -EINVAL;

+	}

+	if(g_pinit_info==NULL || g_pCallback==NULL || g_pNF==NULL)

+	{

+		//printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 663 point is NULL Error!!! \n");

+		return 0;          //default good block

+	}

+	if(g_pNF->PageSize == 0 || g_pNF->PagesPerBlock == 0)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 668 divisor=0  Error!!!\n");

+		return 0;          //default good block

+	}

+	blk_no = div_u64(offs, (g_pNF->PageSize * g_pNF->PagesPerBlock));

+	ret = FHA_check_bad_block(blk_no);     //divisor is 0 error!!!!!!

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_block_isbad() 674 blk_no=%d return %d\n", 

+	       blk_no, ret);

+	#endif

+	

+	return ret;

+}

+

+int ak_nand_block_markbad(struct mtd_info *mtd, loff_t offs)

+{

+	T_U32 blk_no = 0;

+	T_U32 ret = 0;

+

+	if (offs > mtd->size)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 688 offs=0x%llx Error!!!\n", offs);

+		return -EINVAL;

+	}

+	if(g_pinit_info==NULL || g_pCallback==NULL || g_pNF==NULL)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 693 point is NULL Error!!!\n");

+		return 0;  //default mark successed

+	}

+	if(g_pNF->PageSize == 0 || g_pNF->PagesPerBlock == 0)

+	{

+		printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 698 divisor=0  Error!!!\n");

+		return 0;          //default good block

+	}	

+	blk_no = div_u64(offs, (g_pNF->PageSize * g_pNF->PagesPerBlock));

+	ret = FHA_set_bad_block(blk_no);

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c ak_nand_block_markbad() 704 blk_no=%d FHA_set_bad_block() return %d\n", 

+	       blk_no, ret);

+	#endif

+	if(ret == FHA_SUCCESS)

+	{

+		return 0;  //mark successed

+	}

+	else

+	{

+		return 1;  //mark failed

+	}

+}

+

+T_U32 try_nand_para(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_Nandflash_Add *p_add)

+{

+	T_NAND_ECC_STRU data_ctrl;    

+	T_U8 pw[PASSWORD_LENGTH +1];

+			

+	data_ctrl.buf = data;

+    data_ctrl.buf_len = data_len;

+    data_ctrl.ecc_section_len = data_len + oob_len;

+    data_ctrl.ecc_type = ECC_32BIT_P1KB;

+   

+

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c try_nand_para() 736 chip_num=%d,page_jnum=%d,data_len=%d oob_len=%d\n",

+	       chip_num, page_num, data_len, oob_len);

+	#endif 

+	

+	nand_readpage_ecc(chip_num, page_num, 0, p_add, &data_ctrl, AK_NULL);

+

+	memcpy(pw, data+PASSWORD_ADDR_OFFSET, PASSWORD_LENGTH);

+	pw[PASSWORD_LENGTH] = '\0';

+	#if ZZ_DEBUG

+	printk(KERN_INFO "zz wrap_nand.c try_nand_para() 745 password string=%s", pw);

+	#endif 

+	return  AK_TRUE;

+	if(!strcmp(pw, PASSWORD_STR))

+	{	    

+		#if ZZ_DEBUG

+		int k = 0;

+		printk(KERN_INFO "zz wrap_nand.c try_nand_para() 750 password match succussed!\n");

+		for(k=50;k<500;k++)

+		{

+			if(k%10==0)

+			{

+				printk("\n");

+			}

+			printk(KERN_INFO "0x%02x\t", data[k]);

+		}

+		#endif 

+		return  AK_TRUE;

+	}

+	return AK_FALSE;

+}

+

+

+//lgh

+void ak_dump_datactrl_sparectrl(T_PNAND_ECC_STRU data_ctrl, T_PNAND_ECC_STRU spare_ctrl)	

+{

+		printk(KERN_INFO "data_ctrl: buf=%p, buf_len=%lu, ecc_section_len=%lu, ecc_type=%d\n",\

+			data_ctrl->buf, data_ctrl->buf_len, data_ctrl->ecc_section_len, data_ctrl->ecc_type);

+		printk(KERN_INFO "spare_ctrl: buf=%p, buf_len=%lu, ecc_section_len=%lu, ecc_type=%d\n",\

+			spare_ctrl->buf, spare_ctrl->buf_len, spare_ctrl->ecc_section_len, spare_ctrl->ecc_type);

+}

+

+

+#if 0

+unsigned char buf_r_data[8192];

+unsigned char buf_w_data[8192];

+

+void zz_test_nand(void)

+{

+    unsigned char oob_buf[32];

+    int i = 0;

+    int j = 0;

+    int retval = 0;

+    T_U32 chip = 0;

+    int pagenum = 0;

+	

+	T_NAND_ECC_STRU data_ctrl;

+    T_NAND_ECC_STRU spare_ctrl;

+	nand_HWinit();

+    for(i=10; i<15; i++)

+    {

+        retval = nand_eraseblock(chip, i*128, g_pNF);

+        memset(buf_w_data, 0x9b, 8192);

+        memset(oob_buf, i, 32);

+        pagenum = i*128+10;

+		

+		Nand_Config_Data(&data_ctrl, buf_w_data, g_sNF.PageSize, g_sNF.EccType);

+		Nand_Config_Spare(&spare_ctrl, oob_buf, YAFFS_OOB_SIZE, g_sNF.EccType); 

+		

+		retval = nand_writepage_ecc(chip, pagenum, 0, &g_sNF, &data_ctrl, &spare_ctrl);

+

+        memset(buf_r_data,0xff, 8192);

+        memset(oob_buf, 0xff, 32);

+

+		Nand_Config_Data(&data_ctrl, buf_r_data, g_sNF.PageSize, g_sNF.EccType);

+		Nand_Config_Spare(&spare_ctrl, oob_buf, YAFFS_OOB_SIZE, g_sNF.EccType); 

+

+        retval = nand_readpage_ecc(chip, pagenum, 0, &g_sNF, &data_ctrl, &spare_ctrl);

+        //retval = nand_readbytes(chip, pagenum, 0, &g_sNF, buf_r_data, 2048);

+		

+		for(j=0; j<50; j++)

+		{

+			if(j%10 == 0)

+			{

+				printk(KERN_INFO "\n");

+			}

+			printk(KERN_INFO "0x%x ", buf_r_data[j]);

+		}

+		printk(KERN_INFO "\n");

+		#if 1

+		for(j=0; j<10; j++)

+		{

+			printk(KERN_INFO "oob_buf[%d] = %d ", j,oob_buf[j]);

+		}

+		printk(KERN_INFO "\n");

+		#endif

+    }

+}

+

+void erase_all_flash(void)

+{

+	int i = 0;

+	if((g_pNF == NULL) || (g_pNand_Phy_Info == NULL))

+	{

+		printk(KERN_INFO "zz wrap_nand.c erase_all_flash() 638 g_pNF == NULL || g_pNand_Phy_Info == NULL error!!!\n");

+		return;

+	}

+	for(i=0; i<(g_pNand_Phy_Info->blk_num); i++)

+	{

+		nand_eraseblock(0, i*128, g_pNF);

+	}

+}

+

+#endif

+

+

diff --git a/drivers/mtd/nand/ak98-nand/wrap_nand.h b/drivers/mtd/nand/ak98-nand/wrap_nand.h
new file mode 100755
index 00000000000..d9cafb8becd
--- /dev/null
+++ b/drivers/mtd/nand/ak98-nand/wrap_nand.h
@@ -0,0 +1,115 @@
+/**

+ * @filename wrap_nand.h

+ * @brief AK880x nandflash driver

+ *

+ * This file wrap the nand flash driver in nand_control.c file.

+ * Copyright (C) 2010 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author zhangzheng

+ * @modify 

+ * @date 2010-10-10

+ * @version 1.0

+ * @ref

+ */

+

+

+#ifndef _AK_NAND_WRAP_H_

+#define _AK_NAND_WRAP_H_

+

+#include <linux/types.h>

+#include <linux/mtd/mtd.h>

+#include <linux/mtd/nand.h>

+#include <mach-anyka/anyka_types.h>

+#include <mach-anyka/nand_list.h>

+#include <mach-anyka/fha.h>

+#include <mach-anyka/fha_asa.h>

+#include "arch_nand.h"

+

+int init_fha_lib(void);

+#if 0

+void release_fha_lib(void);

+#endif

+

+void ak_dump_datactrl_sparectrl(T_PNAND_ECC_STRU data_ctrl, T_PNAND_ECC_STRU spare_ctrl);	//lgh

+void Nand_Config_Data_Spare(T_PNAND_ECC_STRU data_ctrl, T_U8* data, T_U32 data_len, ECC_TYPE ecc_type,

+							    T_PNAND_ECC_STRU spare_ctrl, T_U8* spare, T_U32 spare_len);	//lgh

+

+void ak_nand_write_buf(struct mtd_info *mtd, const u_char * buf, int len);

+

+

+void ak_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);

+

+

+void ak_nand_select_chip(struct mtd_info *mtd, int chip);

+

+

+u_char ak_nand_read_byte(struct mtd_info *mtd);

+

+int ak_nand_scan_bbt(struct mtd_info *mtd);

+

+int ak_nand_init_size(struct mtd_info *mtd, struct nand_chip *chip, u8 *id_data);

+

+int ak_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                   uint8_t *buf, int page);

+

+

+void ak_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,

+				                     const uint8_t *buf);

+

+

+int ak_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+			                    uint8_t *buf, int pag);

+

+

+void ak_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,

+				                  const uint8_t *buf);

+

+

+int ak_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page, int sndcmd);

+

+

+int ak_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,

+			                   int page);

+

+T_U32 nand_erase_callback(T_U32 chip_num, T_U32 startpage);

+

+T_U32 nand_read_callback(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType);

+

+T_U32 nand_write_callback(T_U32 chip_num, T_U32 page_num, const T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_U32 eDataType);

+

+T_U32 nand_read_bytes_callback(T_U32 nChip, T_U32 rowAddr, T_U32 columnAddr, T_U8 *pData, T_U32 nDataLen);

+

+void *ram_alloc(T_U32 size);

+

+void *ram_free(void *point);

+

+T_S32 print_callback(T_pCSTR s, ...);

+

+T_U32 init_globe_para(void);

+

+void free_globe_para(void);

+

+#ifdef CONFIG_MTD_NAND_TEST   

+void nand_balance_test_init(void);

+

+void nand_balance_test_exit(void);

+#endif

+

+T_U32 ak_mount_partitions(void);

+

+int ak_nand_block_isbad(struct mtd_info *mtd, loff_t offs, int getchip);

+

+int ak_nand_block_markbad(struct mtd_info *mtd, loff_t offs);

+

+T_U32 try_nand_para(T_U32 chip_num, T_U32 page_num, T_U8 *data, 

+           T_U32 data_len, T_U8 *oob, T_U32 oob_len, T_Nandflash_Add *p_add);

+

+

+#if 1

+void zz_test_nand(void);

+void erase_all_flash(void);

+#endif

+

+#endif

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 2957cc70da3..f8b390fe0f4 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -31,7 +31,6 @@
  * published by the Free Software Foundation.
  *
  */
-
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
@@ -52,6 +51,9 @@
 #include <linux/mtd/partitions.h>
 #endif
 
+#include "ak98-nand/wrap_nand.h"
+
+#define ZZ_DEBUG       0
 /* Define default oob placement schemes for large and small page devices */
 static struct nand_ecclayout nand_oob_8 = {
 	.eccbytes = 3,
@@ -117,7 +119,7 @@ DEFINE_LED_TRIGGER(nand_led_trigger);
 static void nand_release_device(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
-
+    //printk(KERN_INFO "zz nand_base.c nand_release_device() line 120\n");
 	/* De-select the NAND device */
 	chip->select_chip(mtd, -1);
 
@@ -177,7 +179,7 @@ static u16 nand_read_word(struct mtd_info *mtd)
 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 {
 	struct nand_chip *chip = mtd->priv;
-
+	
 	switch (chipnr) {
 	case -1:
 		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
@@ -202,7 +204,7 @@ static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
 	struct nand_chip *chip = mtd->priv;
-
+    //printk(KERN_INFO "zz nand_base.c nand_write_buf() line 205\n");
 	for (i = 0; i < len; i++)
 		writeb(buf[i], chip->IO_ADDR_W);
 }
@@ -219,7 +221,7 @@ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int i;
 	struct nand_chip *chip = mtd->priv;
-
+    //printk(KERN_INFO "zz nand_base.c nand_read_buf() line 222\n");
 	for (i = 0; i < len; i++)
 		buf[i] = readb(chip->IO_ADDR_R);
 }
@@ -236,7 +238,7 @@ static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
 	int i;
 	struct nand_chip *chip = mtd->priv;
-
+    //printk(KERN_INFO "zz nand_base.c nand_verify_buf() line 239\n");
 	for (i = 0; i < len; i++)
 		if (buf[i] != readb(chip->IO_ADDR_R))
 			return -EFAULT;
@@ -317,7 +319,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 	int page, chipnr, res = 0;
 	struct nand_chip *chip = mtd->priv;
 	u16 bad;
-
 	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 
 	if (getchip) {
@@ -345,7 +346,7 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 
 	if (getchip)
 		nand_release_device(mtd);
-
+    
 	return res;
 }
 
@@ -362,7 +363,7 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 	struct nand_chip *chip = mtd->priv;
 	uint8_t buf[2] = { 0, 0 };
 	int block, ret;
-
+	
 	/* Get block number */
 	block = (int)(ofs >> chip->bbt_erase_shift);
 	if (chip->bbt)
@@ -402,6 +403,7 @@ static int nand_check_wp(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	/* Check the WP bit */
+//    printk(KERN_INFO "zz nand_base.c nand_check_wp() line 405\n");
 	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 	return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 }
@@ -420,10 +422,10 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 			       int allowbbt)
 {
 	struct nand_chip *chip = mtd->priv;
-
 	if (!chip->bbt)
+    {   
 		return chip->block_bad(mtd, ofs, getchip);
-
+    }
 	/* Return info from the table */
 	return nand_isbad_bbt(mtd, ofs, allowbbt);
 }
@@ -436,7 +438,7 @@ void nand_wait_ready(struct mtd_info *mtd)
 {
 	struct nand_chip *chip = mtd->priv;
 	unsigned long timeo = jiffies + 2;
-
+	
 	led_trigger_event(nand_led_trigger, LED_FULL);
 	/* wait until command is processed or timeout occures */
 	do {
@@ -463,7 +465,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 {
 	register struct nand_chip *chip = mtd->priv;
 	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
-
+	
 	/*
 	 * Write out the command to the device.
 	 */
@@ -685,6 +687,7 @@ nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 	spinlock_t *lock = &chip->controller->lock;
 	wait_queue_head_t *wq = &chip->controller->wq;
 	DECLARE_WAITQUEUE(wait, current);
+    //printk(KERN_INFO "zz nand_base.c nand_get_device() line 689\n");
  retry:
 	spin_lock(lock);
 
@@ -723,7 +726,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 
 	unsigned long timeo = jiffies;
 	int status, state = chip->state;
-
+    //printk(KERN_INFO "zz nand_base.c nand_wait() line 730\n");
 	if (state == FL_ERASING)
 		timeo += (HZ * 400) / 1000;
 	else
@@ -769,7 +772,7 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 			      uint8_t *buf, int page)
 {
 	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	//chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }
 
@@ -789,7 +792,7 @@ static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *c
 	int eccbytes = chip->ecc.bytes;
 	uint8_t *oob = chip->oob_poi;
 	int steps, size;
-
+	
 	for (steps = chip->ecc.steps; steps > 0; steps--) {
 		chip->read_buf(mtd, buf, eccsize);
 		buf += eccsize;
@@ -832,7 +835,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
-
+	
 	chip->ecc.read_page_raw(mtd, chip, buf, page);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
@@ -872,7 +875,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3
 	int data_col_addr, i, gaps = 0;
 	int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
-
+	
 	/* Column address wihin the page aligned to ECC size (256bytes). */
 	start_step = data_offs / chip->ecc.size;
 	end_step = (data_offs + readlen - 1) / chip->ecc.size;
@@ -956,7 +959,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
-
+	
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		chip->ecc.hwctl(mtd, NAND_ECC_READ);
 		chip->read_buf(mtd, p, eccsize);
@@ -1006,7 +1009,7 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 	uint8_t *ecc_code = chip->buffers->ecccode;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
-
+    
 	/* Read the OOB area first */
 	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -1049,7 +1052,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 	int eccsteps = chip->ecc.steps;
 	uint8_t *p = buf;
 	uint8_t *oob = chip->oob_poi;
-
+    
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		int stat;
 
@@ -1096,6 +1099,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
 				  struct mtd_oob_ops *ops, size_t len)
 {
+    //printk(KERN_INFO "zz nand_base.c nand_transfer_oob() line 1102 ops-mode=%d\n",ops->mode);
 	switch(ops->mode) {
 
 	case MTD_OOB_PLACE:
@@ -1155,7 +1159,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
 	uint8_t *bufpoi, *oob, *buf;
-
+	
 	stats = mtd->ecc_stats;
 
 	chipnr = (int)(from >> chip->chip_shift);
@@ -1289,7 +1293,7 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
 {
 	struct nand_chip *chip = mtd->priv;
 	int ret;
-
+	
 	/* Do not allow reads past end of device */
 	if ((from + len) > mtd->size)
 		return -EINVAL;
@@ -1307,7 +1311,7 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
 	*retlen = chip->ops.retlen;
 
 	nand_release_device(mtd);
-
+	
 	return ret;
 }
 
@@ -1321,14 +1325,13 @@ static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
 			     int page, int sndcmd)
 {
-	if (sndcmd) {
+    if (sndcmd) {
 		chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 		sndcmd = 0;
 	}
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return sndcmd;
 }
-
 /**
  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
  *			    with syndromes
@@ -1380,7 +1383,7 @@ static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
 	int status = 0;
 	const uint8_t *buf = chip->oob_poi;
 	int length = mtd->oobsize;
-
+	
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 	chip->write_buf(mtd, buf, length);
 	/* Send command to program the OOB data */
@@ -1499,7 +1502,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 	page = realpage & chip->pagemask;
 
 	while(1) {
-		sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
+		sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);	
 
 		len = min(len, readlen);
 		buf = nand_transfer_oob(chip, buf, ops, len);
@@ -1578,10 +1581,12 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from,
 		goto out;
 	}
 
-	if (!ops->datbuf)
+	if (!ops->datbuf){
 		ret = nand_do_read_oob(mtd, from, ops);
-	else
+	}
+	else{
 		ret = nand_do_read_ops(mtd, from, ops);
+	}
 
  out:
 	nand_release_device(mtd);
@@ -1603,7 +1608,6 @@ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 	chip->write_buf(mtd, buf, mtd->writesize);
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 }
-
 /**
  * nand_write_page_raw_syndrome - [Intern] raw page write function
  * @mtd:	mtd info structure
@@ -1683,7 +1687,7 @@ static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
 	const uint8_t *p = buf;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
-
+	
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 		chip->write_buf(mtd, p, eccsize);
@@ -2172,7 +2176,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 	unsigned int bbt_masked_page = 0xffffffff;
 	loff_t len;
 
-	DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
+	DEBUG(MTD_DEBUG_LEVEL0,"%s: start = 0x%012llx, len = %llu\n",
 				__func__, (unsigned long long)instr->addr,
 				(unsigned long long)instr->len);
 
@@ -2244,7 +2248,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 			instr->state = MTD_ERASE_FAILED;
 			goto erase_exit;
 		}
-
+		
 		/*
 		 * Invalidate the page cache, if we erase the block which
 		 * contains the current cached page
@@ -2363,11 +2367,11 @@ static void nand_sync(struct mtd_info *mtd)
  */
 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
 {
-	/* Check for invalid offset */
+	/* Check for invalid offset */    
 	if (offs > mtd->size)
 		return -EINVAL;
-
-	return nand_block_checkbad(mtd, offs, 1, 0);
+	
+	return nand_block_checkbad(mtd, offs, 1, 0);     
 }
 
 /**
@@ -2386,7 +2390,7 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 			return 0;
 		return ret;
 	}
-
+    
 	return chip->block_markbad(mtd, ofs);
 }
 
@@ -2440,7 +2444,9 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
 	if (!chip->read_word)
 		chip->read_word = nand_read_word;
 	if (!chip->block_bad)
+    { 
 		chip->block_bad = nand_block_bad;
+    }
 	if (!chip->block_markbad)
 		chip->block_markbad = nand_default_block_markbad;
 	if (!chip->write_buf)
@@ -2450,8 +2456,9 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
 	if (!chip->verify_buf)
 		chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
 	if (!chip->scan_bbt)
-		chip->scan_bbt = nand_default_bbt;
-
+       {   
+		    chip->scan_bbt = nand_default_bbt;
+       }
 	if (!chip->controller) {
 		chip->controller = &chip->hwcontrol;
 		spin_lock_init(&chip->controller->lock);
@@ -2470,6 +2477,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	struct nand_flash_dev *type = NULL;
 	int i, dev_id, maf_idx;
 	int tmp_id, tmp_manf;
+	u8 id_data;
 
 	/* Select the device */
 	chip->select_chip(mtd, 0);
@@ -2522,26 +2530,30 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		mtd->name = type->name;
 
 	chip->chipsize = (uint64_t)type->chipsize << 20;
+    printk(KERN_INFO "nand_base.c chip->chipsize=%lu MB\n",type->chipsize);
 
 	/* Newer devices have all the information in additional id bytes */
-	if (!type->pagesize) {
-		int extid;
-		/* The 3rd id byte holds MLC / multichip data */
-		chip->cellinfo = chip->read_byte(mtd);
-		/* The 4th id byte is the important one */
-		extid = chip->read_byte(mtd);
-		/* Calc pagesize */
-		mtd->writesize = 1024 << (extid & 0x3);
-		extid >>= 2;
-		/* Calc oobsize */
-		mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
-		extid >>= 2;
-		/* Calc blocksize. Blocksize is multiples of 64KiB */
-		mtd->erasesize = (64 * 1024) << (extid & 0x03);
-		extid >>= 2;
-		/* Get buswidth information */
-		busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-
+	if (!type->pagesize && chip->init_size) {
+		/* set the pagesize, oobsize, erasesize by the driver*/
+		busw = chip->init_size(mtd, chip, &id_data);
+	} else if (!type->pagesize) {		
+        int extid;
+        /* The 3rd id byte holds MLC / multichip data */
+        chip->cellinfo = chip->read_byte(mtd);
+        /* The 4th id byte is the important one */
+        extid = chip->read_byte(mtd);
+        /* Calc pagesize */
+        mtd->writesize = 1024 << (extid & 0x3);
+        extid >>= 2;
+        /* Calc oobsize */
+        mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
+        extid >>= 2;
+        /* Calc blocksize. Blocksize is multiples of 64KiB */
+        mtd->erasesize = (64 * 1024) << (extid & 0x03);
+        extid >>= 2;
+        /* Get buswidth information */
+        busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+		
 	} else {
 		/*
 		 * Old devices have chip data hardcoded in the device id table
@@ -2635,7 +2647,6 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
 	int i, busw, nand_maf_id;
 	struct nand_chip *chip = mtd->priv;
 	struct nand_flash_dev *type;
-
 	/* Get buswidth to select the correct functions */
 	busw = chip->options & NAND_BUSWIDTH_16;
 	/* Set the default functions */
@@ -2649,9 +2660,10 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
 		chip->select_chip(mtd, -1);
 		return PTR_ERR(type);
 	}
-
+    
 	/* Check for a chip array */
-	for (i = 1; i < maxchips; i++) {
+	for (i = 1; i < maxchips; i++) 
+    {
 		chip->select_chip(mtd, i);
 		/* See comment in nand_get_flash_type for reset */
 		chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
@@ -2662,16 +2674,49 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips)
 		    type->id != chip->read_byte(mtd))
 			break;
 	}
-	if (i > 1)
-		printk(KERN_INFO "%d NAND chips detected\n", i);
-
 	/* Store the number of chips and calc total size for mtd */
 	chip->numchips = i;
 	mtd->size = i * chip->chipsize;
-
 	return 0;
 }
 
+static void nand_panic_wait(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	int i;
+
+	if (chip->state != FL_READY)
+		for (i = 0; i < 40; i++) {
+			if (chip->dev_ready(mtd))
+				break;
+			mdelay(10);
+		}
+	chip->state = FL_READY;
+}
+
+static int nand_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
+			    size_t *retlen, const u_char *buf)
+{
+	struct nand_chip *chip = mtd->priv;
+	int ret;
+	/* Do not allow reads past end of device */
+	if ((to + len) > mtd->size)
+		return -EINVAL;
+	if (!len)
+		return 0;
+
+	nand_panic_wait(mtd);
+
+	chip->ops.len = len;
+	chip->ops.datbuf = (uint8_t *)buf;
+	chip->ops.oobbuf = NULL;
+
+	ret = nand_do_write_ops(mtd, to, &chip->ops);
+
+	*retlen = chip->ops.retlen;
+	return ret;
+}
+
 
 /**
  * nand_scan_tail - [NAND Interface] Scan for the NAND device
@@ -2685,7 +2730,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 {
 	int i;
 	struct nand_chip *chip = mtd->priv;
-
+	
 	if (!(chip->options & NAND_OWN_BUFFERS))
 		chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
 	if (!chip->buffers)
@@ -2696,7 +2741,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 
 	/*
 	 * If no default placement scheme is given, select an appropriate one
-	 */
+	 */	 
 	if (!chip->ecc.layout) {
 		switch (mtd->oobsize) {
 		case 8:
@@ -2721,11 +2766,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
-	/*
-	 * check ECC mode, default to software if 3byte/512byte hardware ECC is
-	 * selected and we have 256 byte pagesize fallback to software ECC
-	 */
-
 	switch (chip->ecc.mode) {
 	case NAND_ECC_HW_OOB_FIRST:
 		/* Similar to NAND_ECC_HW, but a separate read_page handle */
@@ -2737,7 +2777,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 		}
 		if (!chip->ecc.read_page)
 			chip->ecc.read_page = nand_read_page_hwecc_oob_first;
-
+        break;
 	case NAND_ECC_HW:
 		/* Use standard hwecc read page function ? */
 		if (!chip->ecc.read_page)
@@ -2752,7 +2792,10 @@ int nand_scan_tail(struct mtd_info *mtd)
 			chip->ecc.read_oob = nand_read_oob_std;
 		if (!chip->ecc.write_oob)
 			chip->ecc.write_oob = nand_write_oob_std;
-
+        
+        chip->ecc.size = mtd->writesize;
+		chip->ecc.bytes = 0;
+        break;
 	case NAND_ECC_HW_SYNDROME:
 		if ((!chip->ecc.calculate || !chip->ecc.correct ||
 		     !chip->ecc.hwctl) &&
@@ -2812,7 +2855,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 		chip->ecc.size = mtd->writesize;
 		chip->ecc.bytes = 0;
 		break;
-
+         
 	default:
 		printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
 		       chip->ecc.mode);
@@ -2826,8 +2869,10 @@ int nand_scan_tail(struct mtd_info *mtd)
 	chip->ecc.layout->oobavail = 0;
 	for (i = 0; chip->ecc.layout->oobfree[i].length
 			&& i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
+    {   
 		chip->ecc.layout->oobavail +=
 			chip->ecc.layout->oobfree[i].length;
+    }
 	mtd->oobavail = chip->ecc.layout->oobavail;
 
 	/*
@@ -2865,7 +2910,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 
 	/* De-select the device */
 	chip->select_chip(mtd, -1);
-
 	/* Invalidate the pagebuffer reference */
 	chip->pagebuf = -1;
 
@@ -2879,23 +2923,24 @@ int nand_scan_tail(struct mtd_info *mtd)
 	mtd->write = nand_write;
 	mtd->read_oob = nand_read_oob;
 	mtd->write_oob = nand_write_oob;
+	mtd->panic_write = nand_panic_write;
 	mtd->sync = nand_sync;
 	mtd->lock = NULL;
 	mtd->unlock = NULL;
 	mtd->suspend = nand_suspend;
 	mtd->resume = nand_resume;
-	mtd->block_isbad = nand_block_isbad;
-	mtd->block_markbad = nand_block_markbad;
-
+	mtd->block_isbad = nand_block_isbad;     //nand_block_isbad;      
+	mtd->block_markbad = nand_block_markbad; //nand_block_markbad;  
+    
 	/* propagate ecc.layout to mtd_info */
 	mtd->ecclayout = chip->ecc.layout;
-
 	/* Check, if we should skip the bad block table scan */
 	if (chip->options & NAND_SKIP_BBTSCAN)
 		return 0;
 
-	/* Build bad block table */
+	/* Build bad block table */     
 	return chip->scan_bbt(mtd);
+	
 }
 
 /* is_module_text_address() isn't exported, and it's mostly a pointless
@@ -2923,7 +2968,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 int nand_scan(struct mtd_info *mtd, int maxchips)
 {
 	int ret;
-
 	/* Many callers got this wrong, so check for it for a while... */
 	if (!mtd->owner && caller_is_module()) {
 		printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 55c23e5cd21..0da7b928c2a 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -60,6 +60,7 @@
 #include <linux/delay.h>
 #include <linux/vmalloc.h>
 
+#define ZZ_DEBUG           0         
 /**
  * check_pattern - [GENERIC] check if a pattern is in the buffer
  * @buf:	the buffer to search
@@ -956,7 +957,9 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	uint8_t *buf;
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
-
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz nand_bbt.c nand_scan_bbt() 959\n");
+	#endif
 	len = mtd->size >> (this->bbt_erase_shift + 2);
 	/* Allocate memory (2bit per block) and clear the memory bad block table */
 	this->bbt = kzalloc(len, GFP_KERNEL);
@@ -1144,7 +1147,9 @@ static struct nand_bbt_descr bbt_mirror_descr = {
 int nand_default_bbt(struct mtd_info *mtd)
 {
 	struct nand_chip *this = mtd->priv;
-
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz nand_bbt.c nand_default_bbt() 1147\n");
+	#endif
 	/* Default for AG-AND. We must use a flash based
 	 * bad block table as the devices have factory marked
 	 * _good_ blocks. Erasing those blocks leads to loss
@@ -1192,11 +1197,12 @@ int nand_default_bbt(struct mtd_info *mtd)
 */
 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
+	/*
 	struct nand_chip *this = mtd->priv;
 	int block;
 	uint8_t res;
 
-	/* Get block number * 2 */
+	// Get block number * 2 
 	block = (int)(offs >> (this->bbt_erase_shift - 1));
 	res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
 
@@ -1211,7 +1217,12 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 	case 0x02:
 		return allowbbt ? 0 : 1;
 	}
-	return 1;
+	*/
+	//return 1;
+	#if ZZ_DEBUG
+	printk(KERN_INFO "zz nand_bbt.c nand_isbad_bbt() 1217\n");
+	#endif
+	return 0;  //zhangzheng modify for debug
 }
 
 EXPORT_SYMBOL(nand_scan_bbt);
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 69ee2c90eb0..e01d59d074b 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -109,6 +109,12 @@ struct nand_flash_dev nand_flash_ids[] = {
 	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
 	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
 
+    /* 32 Gigabit */
+    {"NAND 4GiB 1,8V 8-bit",    0xA7, 0, 4096, 0, LP_OPTIONS},
+    {"NAND 4GiB 3,3V 8-bit",    0xD7, 0, 4096, 0, LP_OPTIONS},
+    {"NAND 4GiB 1,8V 16-bit",   0xB7, 0, 4096, 0, LP_OPTIONS16},
+    {"NAND 4GiB 3,3V 16-bit",   0xC7, 0, 4096, 0, LP_OPTIONS16},
+
 	/*
 	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
 	 * have a strange page/block layout !  The chosen minimum erasesize is
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b2f71f79baa..6f3b9f20cfd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -939,6 +939,8 @@ config DM9000
 	  To compile this driver as a module, choose M here.  The module
 	  will be called dm9000.
 
+source "drivers/net/ak98-mac/Kconfig"
+
 config DM9000_DEBUGLEVEL
 	int "DM9000 maximum debug level"
 	depends on DM9000
@@ -3113,6 +3115,23 @@ config PPPOL2TP
 	  and session setup). One such daemon is OpenL2TP
 	  (http://openl2tp.sourceforge.net/).
 
+config PPPOLAC
+	tristate "PPP on L2TP Access Concentrator"
+	depends on PPP && INET
+	help
+	  L2TP (RFC 2661) is a tunneling protocol widely used in virtual private
+	  networks. This driver handles L2TP data packets between a UDP socket
+	  and a PPP channel, but only permits one session per socket. Thus it is
+	  fairly simple and suited for clients.
+
+config PPPOPNS
+	tristate "PPP on PPTP Network Server"
+	depends on PPP && INET
+	help
+	  PPTP (RFC 2637) is a tunneling protocol widely used in virtual private
+	  networks. This driver handles PPTP data packets between a RAW socket
+	  and a PPP channel. It is fairly simple and easy to use.
+
 config SLIP
 	tristate "SLIP (serial line) support"
 	---help---
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 246323d7f16..ce037c2fa25 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -158,6 +158,8 @@ obj-$(CONFIG_PPP_BSDCOMP) += bsd_comp.o
 obj-$(CONFIG_PPP_MPPE) += ppp_mppe.o
 obj-$(CONFIG_PPPOE) += pppox.o pppoe.o
 obj-$(CONFIG_PPPOL2TP) += pppox.o pppol2tp.o
+obj-$(CONFIG_PPPOLAC) += pppox.o pppolac.o
+obj-$(CONFIG_PPPOPNS) += pppox.o pppopns.o
 
 obj-$(CONFIG_SLIP) += slip.o
 obj-$(CONFIG_SLHC) += slhc.o
@@ -241,6 +243,7 @@ obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_SMSC911X) += smsc911x.o
 obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
 obj-$(CONFIG_DM9000) += dm9000.o
+obj-$(CONFIG_AK98_MAC) += ak98-mac/
 obj-$(CONFIG_PASEMI_MAC) += pasemi_mac_driver.o
 pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o
 obj-$(CONFIG_MLX4_CORE) += mlx4/
diff --git a/drivers/net/ak98-mac/Ethernethw.h b/drivers/net/ak98-mac/Ethernethw.h
new file mode 100755
index 00000000000..2fa0019763c
--- /dev/null
+++ b/drivers/net/ak98-mac/Ethernethw.h
@@ -0,0 +1,731 @@
+#ifndef _MAC_REG_DEFINE_H_

+#define _MAC_REG_DEFINE_H_

+#define MAC_REG_BASE				0x60000000

+

+#define REG_MASTER_CTRL                        ( 0x1400)  /* WORD reg */

+    #define MASTER_CTRL_MAC_SOFT_RST_OFF        0       /* hw sc */

+    #define MASTER_CTRL_MAC_SOFT_RST_BITS       1

+    #define MASTER_CTRL_PCIE_SOFT_RST_OFF       1       /* hw sc */

+    #define MASTER_CTRL_PCIE_SOFT_RST_BITS      1

+    #define MASTER_CTRL_PCIE_TEST_MOD_OFF       2

+    #define MASTER_CTRL_PCIE_TEST_MOD_BITS      2

+    #define MASTER_CTRL_BERT_START_OFF          4

+    #define MASTER_CTRL_BERT_START_BITS         1

+    #define MASTER_CTRL_OOB_DIS_OFF             6

+    #define MASTER_CTRL_OOB_DIS_BITS            1       

+    #define MASTER_CTRL_SA_TIMER_EN_OFF         7

+    #define MASTER_CTRL_SA_TIMER_EN_BITS        1

+    #define MASTER_CTRL_MANUAL_TIME_EN_OFF      8

+    #define MASTER_CTRL_MANUAL_TIMER_EN_BITS    1

+    #define MASTER_CTRL_MANUAL_INT_OFF          9

+    #define MASTER_CTRL_MANUAL_INT_BITS         1

+    #define MASTER_CTRL_IRQ_MODRT_EN_OFF        10      /* tx if 2 timer */

+    #define MASTER_CTRL_IRQ_MODRT_EN_BITS       1

+    #define MASTER_CTRL_IRQ_MODRT_RXEN_OFF      11      /* rx if 2 timer */

+    #define MASTER_CTRL_IRQ_MODRT_RXEN_BITS     1

+    #define MASTER_CTRL_PCLK_SEL_DIS_OFF        12      /* ps may set it */

+    #define MASTER_CTRL_PCLK_SEL_DIS_BITS       1

+    #define MASTER_CTRL_CLKSW_MODE_OFF          13

+    #define MASTER_CTRL_CLKSW_MODE_BITS         1

+    #define MASTER_CTRL_INT_RCLR_EN_OFF         14

+    #define MASTER_CTRL_INT_CLCR_EN_BITS        1

+    #define MASTER_CTRL_OTP_SEL_OFF             31

+    #define MASTER_CTRL_OTP_SEL_BITS            1

+

+#define REG_DEV_REV_NUM                         (0x1402)  /* BYTE reg */

+#define REG_DEV_ID_NUM                          (0x1403)  /* BYTE reg */

+

+#define REG_MANUAL_TIMER_INIT                   (0x1404)  /* DWORD reg */

+

+#define REG_IRQ_MODRT_INIT                      (0x1408)  /* WORD reg */

+#define REG_IRQ_MODRT_RX_INIT                   (0x140A)  /* WORD reg */

+

+#define REG_PHY_CTRL                            (0x140C)  /* DWORD reg */

+    #define PHY_CTRL_EXIT_RST_OFF               0

+    #define PHY_CTRL_EXIT_RST_BITS              1

+    #define PHY_CTRL_RTL_MOD_OFF                1

+    #define PHY_CTRL_RTL_MOD_BITS               1

+    #define PHY_CTRL_LED_MOD_OFF                2

+    #define PHY_CTRL_LED_MOD_BITS               1

+    #define PHY_CTRL_ANEG_NOW_OFF               3

+    #define PHY_CTRL_ANEG_NOW_BITS              1

+    #define PHY_CTRL_REV_ANEG_OFF               4

+    #define PHY_CTRL_REV_ANEG_BITS              1

+    #define PHY_CTRL_GATE25M_EN_OFF             5

+    #define PHY_CTRL_GATE25M_EN_BITS            1

+    #define PHY_CTRL_LPW_EXIT_OFF               6

+    #define PHY_CTRL_LPW_EXIT_BITS              1

+    #define PHY_CTRL_PHY_IDDQ_OFF               7

+    #define PHY_CTRL_PHY_IDDQ_BITS              1

+    #define PHY_CTRL_PHY_IDDQ_DIS_OFF           8

+    #define PHY_CTRL_PHY_IDDQ_DIS_BITS          1

+    #define PHY_CTRL_GIGA_DIS_OFF               9

+    #define PHY_CTRL_GIGA_DIS_BITS              1

+    #define PHY_CTRL_HIB_EN_HW_OFF              10

+    #define PHY_CTRL_HIB_EN_HW_BITS             1

+    #define PHY_CTRL_HIB_PULSE_HW_OFF           11

+    #define PHY_CTRL_HIB_PULSE_HW_BITS          1

+    #define PHY_CTRL_SEL_ANA_RST_OFF            12

+    #define PHY_CTRL_SEL_ANA_RST_BITS           1

+    #define PHY_CTRL_PHY_PLL_ON_OFF             13

+    #define PHY_CTRL_PHY_PLL_ON_BITS            1

+    #define PHY_CTRL_POWERDOWN_HW_OFF           14

+    #define PHY_CTRL_POWERDOWN_HW_BITS          1

+    #define PHY_CTRL_PHY_PLL_BYPASS_OFF         15

+    #define PHY_CTRL_PHY_PLL_BYPASS_BITS        1

+

+#ifdef EN_HIB

+    #define PHY_CTRL_DEFAULT    (\

+        FLAG(PHY_CTRL_SEL_ANA_RST_OFF)  |\

+        FLAG(PHY_CTRL_HIB_EN_HW_OFF)    |\

+        FLAG(PHY_CTRL_HIB_PULSE_HW_OFF) )

+#else

+    #define PHY_CTRL_DEFAULT    (\

+        FLAG(PHY_CTRL_SEL_ANA_RST_OFF)  |\

+        FLAG(PHY_CTRL_HIB_PULSE_HW_OFF) )

+#endif/*EN_HIB*/

+        

+    #define PHY_CTRL_POWER_SAVING   (\

+        FLAG(PHY_CTRL_SEL_ANA_RST_OFF)  |\

+        FLAG(PHY_CTRL_HIB_EN_HW_OFF)    |\

+        FLAG(PHY_CTRL_HIB_PULSE_HW_OFF) |\

+        FLAG(PHY_CTRL_POWERDOWN_HW_OFF) |\

+        FLAG(PHY_CTRL_PHY_IDDQ_OFF) )

+    

+    

+#define REG_IDLE_STATUS                         (0x1410)  /* BYTE reg */

+    #define IDLE_STATUS_RXMAC_OFF               0

+    #define IDLE_STATUS_RXMAC_BITS              1

+    #define IDLE_STATUS_TXMAC_OFF               1

+    #define IDLE_STATUS_TXMAC_BITS              1

+    #define IDLE_STATUS_RXQ_OFF                 2

+    #define IDLE_STATUS_RXQ_BITS                1

+    #define IDLE_STATUS_TXQ_OFF                 3

+    #define IDLE_STATUS_TXQ_BITS                1

+

+#define REG_MDIO_CTRL                           (0x1414)  /* DWORD reg */

+    #define MDIO_CTRL_DATA(val)             (val&0xFFFF)    

+    #define MDIO_CTRL_REG_ADDR(val)         ((val&0x1f) << 16)

+    #define MDIO_CTRL_REG_ADDR_BITS             5

+	#define MDIO_CTRL_WRITE					(0<<21)

+	#define MDIO_CTRL_READ					(1<<21)/*read:0, write:1*/

+    #define MDIO_CTRL_RW_OFF                    21  

+    #define MDIO_CTRL_RW_BITS                   1

+    #define MDIO_CTRL_SUP_PREAMBLE          (1<<22)

+    #define MDIO_CTRL_SUP_PREAMBLE_BITS         1

+    #define MDIO_CTRL_START                 (1<<23)

+    #define MDIO_CTRL_START_BITS                1   /* sc */

+    #define MDIO_CTRL_CLK_SEL_OFF               24

+    #define MDIO_CTRL_CLK_SEL_BITS              3

+    #define MDIO_CTRL_BUSY_OFF                  27

+    #define MDIO_CTRL_BUSY_BITS                 1

+    #define MDIO_CTRL_AP_EN_OFF                 28

+    #define MDIO_CTRL_AP_EN_BITS                1

+    #define MDIO_CLK_25_4                       0

+    #define MDIO_CLK_25_6                       2

+    #define MDIO_CLK_25_8                       3

+    #define MDIO_CLK_25_10                      4

+    #define MDIO_CLK_25_14                      5

+    #define MDIO_CLK_25_20                      6

+    #define MDIO_CLK_25_28                      7

+    #define MDIO_MAX_AC_TIMER                   100 /* 1 ms */

+    #define MDIO_CTRL_POST_READ_OFF             29

+    #define MDIO_CTRL_POST_READ_BITS            1

+    #define MDIO_CTRL_MODE_OFF                  30

+    #define MDIO_CTRL_MODE_BITS                 1

+    #define MDIO_CTRL_MODE_OLD                  0

+    #define MDIO_CTRL_MODE_EXTENSION            1

+

+    

+#define REG_PHY_STATUS                          (0x1418)  /* DWORD reg */

+    #define PHY_STATUS_PHY_STATUS_OFF           0

+    #define PHY_STATUS_PHY_STATUS_BITS          16

+    #define PHY_STATUS_OE_PWSTRP_OFF            16

+    #define PHY_STATUS_OE_PWSTRP_BITS           11

+    #define PHY_STATUS_LPW_STATUS_OFF           31

+    #define PHY_STATUS_LPW_STATUS_BITS          1

+    

+#define REG_BIST0_CTRL                          (0x141C)  /* DWORD reg */

+    #define BIST0_CTRL_NOW_OFF                  0

+    #define BIST0_CTRL_NOW_BITS                 1

+    #define BIST0_CTRL_SRAM_FAIL_OFF            1

+    #define BIST0_CTRL_SRAM_FAIL_BITS           1

+    #define BIST0_CTRL_FUSE_FLAG_OFF            2

+    #define BIST0_CTRL_FUSE_FLAG_BITS           1

+    #define BIST0_CTRL_FUSE_PAT_OFF             4

+    #define BIST0_CTRL_FUSE_PAT_BITS            3

+    #define BIST0_CTRL_FUSE_STEP_OFF            8

+    #define BIST0_CTRL_FUSE_SETP_BITS           4

+    #define BIST0_CTRL_FUSE_ROW_OFF             12

+    #define BIST0_CTRL_FUSE_ROW_BITS            12

+    #define BIST0_CTRL_FUSE_COL_OFF             24

+    #define BIST0_CTRL_FUSE_COL_BITS            6

+

+#define REG_BIST1_CTRL                          (0x1420)  /* DWORD reg */

+    #define BIST1_CTRL_NOW_OFF                  0

+    #define BIST1_CTRL_NOW_BITS                 1

+    #define BIST1_CTRL_SRAM_FAIL_OFF            1

+    #define BIST1_CTRL_SRAM_FAIL_BITS           1

+    #define BIST1_CTRL_FUSE_FLAG_OFF            2

+    #define BIST1_CTRL_FUSE_FLAG_BITS           1

+    #define BIST1_CTRL_FUSE_PAT_OFF             4

+    #define BIST1_CTRL_FUSE_PAT_BITS            3

+    #define BIST1_CTRL_FUSE_STEP_OFF            8

+    #define BIST1_CTRL_FUSE_SETP_BITS           4

+    #define BIST1_CTRL_FUSE_ROW_OFF             12

+    #define BIST1_CTRL_FUSE_ROW_BITS            7

+    #define BIST1_CTRL_FUSE_COL_OFF             24

+    #define BIST1_CTRL_FUSE_COL_BITS            5

+

+#define REG_SERDES_CTRL_STS                     (0x1424)

+#define     SERDES_CTRL_STS_SELFB_PLL_SEL_OFF   14

+#define     SERDES_CTRL_STS_SELFB_PLL_SEL_BITS  2

+#define     SERDES_OVCLK_18_25                  0

+#define     SERDES_OVCLK_12_18                  1

+#define     SERDES_OVCLK_0_4                    2

+#define     SERDES_OVCLK_4_12                   3

+#define     SERDES_MAC_CLK_SLOWDOWN_OFF         17

+#define     SERDES_MAC_CLK_SLOWDOWN_BITS        1

+#define     SERDES_PHY_CLK_SLOWDOWN_OFF         18

+#define     SERDES_PHY_CLK_SLOWDOWN_BITS        1

+

+

+#define REG_LED_CTRL                            (0x1428)  /* DWORD reg */

+    #define LED_CTRL_DC_CTRL_OFF                0

+    #define LED_CTRL_DC_CTRL_BITS               2

+    #define LED_CTRL_D3_MODE_CTRL_OFF           2

+    #define LED_CTRL_D3_MODE_CTRL_BITS          2

+    #define LED_CTRL_0_PAT_MAP_OFF              4

+    #define LED_CTRL_0_PAT_MAP_BITS             2

+    #define LED_CTRL_1_PAT_MAP_OFF              6

+    #define LED_CTRL_1_PAT_MAP_BITS             2

+    #define LED_CTRL_2_PAT_MAP_OFF              8

+    #define LED_CTRL_2_PAT_MAP_BITS             2

+    

+#define REG_LED_PAT0                            (0x142C)  /* WORD reg */

+#define REG_LED_PAT1                            (0x142E)  /* WORD reg */

+#define REG_LED_PAT2                            (0x1430)  /* WORD reg */

+

+#define REG_SYS_ALIVE                           (0x1434) 

+    #define SYS_ALIVE_FLAG_OFF                  0

+    #define SYS_ALIVE_FLAG_BITS                 1

+    

+#define REG_LPI_TD                              (0x143C)

+

+#define REG_LPI_CTRL                            (0x1440)

+    #define LPI_CTRL_EN_OFF                     0

+    #define LPI_CTRL_EN_BITS                    1

+    #define LPI_CTRL_CTRL_OFF                   1

+    #define LPI_CTRL_CTRL_BITS                  1

+    #define LPI_CTRL_GMII_OFF                   2

+    #define LPI_CTRL_GMII_BITS                  1

+    #define LPI_CTRL_CHK_STATE_OFF              3

+    #define LPI_CTRL_CHK_STATE_BITS             1

+    #define LPI_CTRL_CHK_RX_OFF                 4

+    #define LPI_CTRL_CHK_RX_BITS                1

+    

+#define REG_LPI_TW                              (0x1444)

+

+    

+#define REG_MDIO_EXT_CTRL                       (0x1448)

+    #define MDIO_EXT_CTRL_REG_ADDR_OFF          0

+    #define MDIO_EXT_CTRL_REG_ADDR_BITS         16

+    #define MDIO_EXT_CTRL_DEVADDR_OFF           16

+    #define MDIO_EXT_CTRL_DEVADDR_BITS          5

+    #define MDIO_EXT_CTRL_PTADDR_OFF            21

+    #define MDIO_EXT_CTRL_PTADDR_BITS           5 

+

+#define REG_MAC_CTRL                            (0x1480)  /* DWORD reg */

+    #define MAC_CTRL_TXEN_OFF                   0

+    #define MAC_CTRL_TXEN_BITS                  1

+    #define MAC_CTRL_RXEN_OFF                   1

+    #define MAC_CTRL_RXEN_BITS                  1

+    #define MAC_CTRL_TXFC_OFF                   2

+    #define MAC_CTRL_TXFC_BITS                  1

+    #define MAC_CTRL_RXFC_OFF                   3

+    #define MAC_CTRL_RXFC_BITS                  1

+    #define MAC_CTRL_LOOPBACK_OFF               4

+    #define MAC_CTRL_LOOPBACK_BITS              1

+    #define MAC_CTRL_FULLD_OFF                  5

+    #define MAC_CTRL_FULLD_BITS                 1

+    #define MAC_CTRL_CRCE_OFF                   6

+    #define MAC_CTRL_CRCE_BITS                  1

+    #define MAC_CTRL_PCRCE_OFF                  7

+    #define MAC_CTRL_PCRCE_BITS                 1

+    #define MAC_CTRL_FLCHK_OFF                  8

+    #define MAC_CTRL_FLCHK_BITS                 1

+    #define MAC_CTRL_HUGEN_OFF                  9

+    #define MAC_CTRL_HUGEN_BITS                 1

+    #define MAC_CTRL_PRLEN_OFF                  10

+    #define MAC_CTRL_PRLEN_BITS                 4

+    #define MAC_CTRL_PRLEN_DEF                  7

+    #define MAC_CTRL_VLAN_STRIP_OFF             14

+    #define MAC_CTRL_VLAN_STRIP_BITS            1

+    #define MAC_CTRL_PROM_MODE_OFF              15

+    #define MAC_CTRL_PROM_MODE_BITS             1

+    #define MAC_CTRL_TPAUSE_OFF                 16

+    #define MAC_CTRL_TPAUSE_BITS                1

+    #define MAC_CTRL_SSTCT_OFF                  17

+    #define MAC_CTRL_SSTCT_BITS                 1

+    #define MAC_CTRL_SRTFN_OFF                  18

+    #define MAC_CTRL_SRTFN_BITS                 1

+    #define MAC_CTRL_SIMR_OFF                   19

+    #define MAC_CTRL_SIMR_BITS                  1

+    #define MAC_CTRL_SPEED_OFF                  20

+    #define MAC_CTRL_SPEED_BITS                 2

+    #define MAC_CTRL_SPEED_10_100               1

+    #define MAC_CTRL_SPEED_1000                 2                   

+    #define MAC_CTRL_MBOF_OFF                   22

+    #define MAC_CTRL_MBOF_BITS                  1

+    #define MAC_CTRL_HUGE_OFF                   23

+    #define MAC_CTRL_HUGE_BITS                  1

+    #define MAC_CTRL_RX_XSUM_EN_OFF             24

+    #define MAC_CTRL_RX_XSUM_EN_BITS            1

+    #define MAC_CTRL_MUTI_ALL_OFF               25

+    #define MAC_CTRL_MUTI_ALL_BITS              1

+    #define MAC_CTRL_BROAD_EN_OFF               26

+    #define MAC_CTRL_BROAD_EN_BITS              1

+    #define MAC_CTRL_DEBUG_MODE_OFF             27

+    #define MAC_CTRL_DEBUG_MODE_BITS            1

+    #define MAC_CTRL_SINGLE_PAUSE_OFF           28

+    #define MAC_CTRL_SINGLE_PAUSE_BITS          1   

+    #define MAC_CTRL_HASH_ALG_MODE_OFF          29

+    #define MAC_CTRL_HASH_ALG_MODE_BITS         1

+    #define MAC_CTRL_HASH_ALG_CRC32             1

+    #define MAC_CTRL_HASH_ALG_CRC16             0

+    #define MAC_CTRL_SPEED_MODE_OFF             30

+    #define MAC_CTRL_SPEED_MODE_BITS            1

+    #define MAC_CTRL_SPEED_MODE_PHY             0

+    #define MAC_CTRL_SPEED_MODE_SW              1

+

+

+#define REG_MAC_STA_ADDR                        (0x1488)  /* QWORD reg */

+/* [1488]=0x749dc320, [148c]=0x00000013, mac-addr:00-13-74-9d-c3-20 */

+

+#define REG_RX_HASH_TABLE                       (0x1490)  /* QWORD reg */

+

+#define REG_MTU                                 (0x149C)  /* WORD reg */

+

+#define REG_WOL_CTRL                            (0x14A0)  /* DWORD reg */

+    #define WOL_CTRL_PATTERN_EN_OFF             0

+    #define WOL_CTRL_PATTERN_EN_BITS            1

+    #define WOL_CTRL_PATTERN_PME_EN_OFF         1

+    #define WOL_CTRL_PATTERN_PME_EN_BITS        1

+    #define WOL_CTRL_MAGIC_EN_OFF               2

+    #define WOL_CTRL_MAGIC_EN_BITS              1

+    #define WOL_CTRL_MAGIC_PME_EN_OFF           3

+    #define WOL_CTRL_MAGIC_PME_EN_BITS          1

+    #define WOL_CTRL_LINKCHG_EN_OFF             4

+    #define WOL_CTRL_LINKCHG_EN_BITS            1

+    #define WOL_CTRL_LINKCHG_PME_EN_OFF         5

+    #define WOL_CTRL_LINKCHG_PME_EN_BITS        1

+    #define WOL_CTRL_PATTERN_ST_OFF             8

+    #define WOL_CTRL_PATTERN_ST_BITS            1

+    #define WOL_CTRL_MAGIC_ST_OFF               9

+    #define WOL_CTRL_MAGIC_ST_BITS              1

+    #define WOL_CTRL_LINKCHG_ST_OFF             10

+    #define WOL_CTRL_LINKCHG_ST_BITS            1

+    #define WOL_CTRL_CLK_SWH_EN_OFF             15

+    #define WOL_CTRL_CLK_SWH_EN_BITS            1

+    #define WOL_CTRL_PT0_EN_OFF                 16

+    #define WOL_CTRL_PT0_EN_BITS                1

+    #define WOL_CTRL_PT1_EN_OFF                 17

+    #define WOL_CTRL_PT1_EN_BITS                1

+    #define WOL_CTRL_PT2_EN_OFF                 18

+    #define WOL_CTRL_PT2_EN_BITS                1   

+    #define WOL_CTRL_PT3_EN_OFF                 19

+    #define WOL_CTRL_PT3_EN_BITS                1   

+    #define WOL_CTRL_PT4_EN_OFF                 20

+    #define WOL_CTRL_PT4_EN_BITS                1   

+    #define WOL_CTRL_PT5_EN_OFF                 21

+    #define WOL_CTRL_PT5_EN_BITS                1   

+    #define WOL_CTRL_PT6_EN_OFF                 22

+    #define WOL_CTRL_PT6_EN_BITS                1

+    #define WOL_CTRL_PT0_MATCH_OFF              24

+    #define WOL_CTRL_PT0_MATCH_BITS             1

+    #define WOL_CTRL_PT1_MATCH_OFF              25

+    #define WOL_CTRL_PT1_MATCH_BITS             1

+    #define WOL_CTRL_PT2_MATCH_OFF              26

+    #define WOL_CTRL_PT2_MATCH_BITS             1

+    #define WOL_CTRL_PT3_MATCH_OFF              27

+    #define WOL_CTRL_PT3_MATCH_BITS             1

+    #define WOL_CTRL_PT4_MATCH_OFF              28

+    #define WOL_CTRL_PT4_MATCH_BITS             1

+    #define WOL_CTRL_PT5_MATCH_OFF              29

+    #define WOL_CTRL_PT5_MATCH_BITS             1

+    #define WOL_CTRL_PT6_MATCH_OFF              30

+    #define WOL_CTRL_PT6_MATCH_BITS             1

+            

+#define REG_WOL_PT0_LEN                         (0x14A4)  /* BYTE reg */

+#define REG_WOL_PT1_LEN                         0x14A5  /* BYTE reg */

+#define REG_WOL_PT2_LEN                         0x14A6  /* BYTE reg */

+#define REG_WOL_PT3_LEN                         0x14A7  /* BYTE reg */

+#define REG_WOL_PT4_LEN                         0x14A8  /* BYTE reg */

+#define REG_WOL_PT5_LEN                         0x14A9  /* BYTE reg */

+#define REG_WOL_PT6_LEN                         0x14AA  /* BYTE reg */

+

+#define REG_SRAM_RFD0                           (0x1500)  /* DWORD reg */

+    #define SRAM_RFD0_HDRADDR_OFF               0

+    #define SRAM_RFD0_HDRADDR_BITS              12

+    #define SRAM_RFD0_TALADDR_OFF               16

+    #define SRAM_RFD0_TALADDR_BITS              12

+    

+#define REG_SRAM_RFD1                           (0x1504)  /* DWORD reg */

+    #define SRAM_RFD1_HDRADDR_OFF               0

+    #define SRAM_RFD1_HDRADDR_BITS              12

+    #define SRAM_RFD1_TALADDR_OFF               16

+    #define SRAM_RFD1_TALADDR_BITS              12

+    

+#define REG_SRAM_RFD2                           (0x1508)  /* DWORD reg */

+    #define SRAM_RFD2_HDRADDR_OFF               0

+    #define SRAM_RFD2_HDRADDR_BITS              12

+    #define SRAM_RFD2_TALADDR_OFF               16

+    #define SRAM_RFD2_TALADDR_BITS              12

+    

+#define REG_SRAM_RFD3                           (0x150C)  /* DWORD reg */

+    #define SRAM_RFD3_HDRADDR_OFF               0

+    #define SRAM_RFD3_HDRADDR_BITS              12

+    #define SRAM_RFD3_TALADDR_OFF               16

+    #define SRAM_RFD3_TALADDR_BITS              12

+    

+#define REG_SRAM_RFD_NICLEN                     (0x1510)  /* DWORD reg */

+

+#define REG_SRAM_TRD                            0x1518  /* DWORD reg */

+    #define SRAM_TRD_HDRADDR_OFF                0

+    #define SRAM_TRD_HDRADDR_BITS               12

+    #define SRAM_TRD_TALADDR_OFF                16

+    #define SRAM_TRD_TALADDR_BITS               12

+    

+#define REG_SRAM_TRD_NICLEN                     (0x151C)  /* DWORD reg */

+

+#define REG_SRAM_RXF                            (0x1520)  /* DWORD reg */

+    #define SRAM_RXF_HDRADDR_OFF                0

+    #define SRAM_RXF_HDRADDR_BITS               12

+    #define SRAM_RXF_TALADDR_OFF                16

+    #define SRAM_RXF_TALADDR_BITS               12

+    

+#define REG_SRAM_RXF_NICLEN                     (0x1524)  /* DWORD reg */

+

+#define REG_SRAM_TXF                            (0x1528)  /* DWORD reg */

+    #define SRAM_TXF_HDRADDR_OFF                0

+    #define SRAM_TXF_HDRADDR_BITS               12

+    #define SRAM_TXF_TALADDR_OFF                16

+    #define SRAM_TXF_TALADDR_BITS               12

+    

+#define REG_SRAM_TXF_NICLEN                     (0x152C)  /* DWORD reg */ 

+        

+#define REG_SRAM_TCP_HDRADDR                    (0x1530)  /* WORD reg */

+

+#define REG_SRAM_PAT_HDRADDR                    (0x1532)  /* WORD reg */

+

+#define REG_SRAM_LOAD_PTR                       (0x1534)  /* BYTE reg, sc */

+    #define SRAM_LOAD_PTR_OFF                   0

+    #define SRAM_LOAD_PTR_BITS                  1   

+

+

+#define REG_RX_BASE_ADDR_HI                     (0x1540)  /* DWORD reg */

+

+#define REG_TX_BASE_ADDR_HI                     (0x1544)  /* DWORD reg */

+

+#define REG_SMB_BASE_ADDR_HI                    (0x1548)  /* DWORD reg */

+#define REG_SMB_BASE_ADDR_LO                    (0x154C)  /* DWORD reg */

+

+#define REG_RFD0_HDRADDR_LO                     (0x1550)  /* DWORD reg */

+#define REG_RFD1_HDRADDR_LO                     (0x1554)  /* DWORD reg */

+#define REG_RFD2_HDRADDR_LO                     (0x1558)  /* DWORD reg */

+#define REG_RFD3_HDRADDR_LO                     (0x155C) /* DWORD reg */

+#define REG_RFD_RING_SIZE                       (0x1560) /* DWORD reg */

+#define REG_RFD_BUFFER_SIZE                     (0x1564)  /* DWORD reg */

+

+#define REG_RRD0_HDRADDR_LO                     (0x1568)  /* DWORD reg */

+#define REG_RRD1_HDRADDR_LO                     (0x156C)  /* DWORD reg */

+#define REG_RRD2_HDRADDR_LO                     (0x1570)  /* DWORD reg */

+#define REG_RRD3_HDRADDR_LO                     (0x1574)  /* DWORD reg */

+#define REG_RRD_RING_SIZE                       (0x1578)  /* DWORD reg */

+

+#define REG_HTPD_HDRADDR_LO                     (0x157C)  /* DWORD reg */

+#define REG_NTPD_HDRADDR_LO                     (0x1580)  /* DWORD reg */

+#define REG_TPD_RING_SIZE                       (0x1584)  /* DWORD reg */

+

+#define REG_CMB_BASE_ADDR_LO                    (0x1588)  /* DWORD reg */

+

+#define REG_RSS_KEY0                            (0x14B0)  /* DWORD reg */

+#define REG_RSS_KEY1                            (0x14B4)  /* DWORD reg */

+#define REG_RSS_KEY2                            (0x14B8)  /* DWORD reg */

+#define REG_RSS_KEY3                            (0x14BC)  /* DWORD reg */

+#define REG_RSS_KEY4                            (0x14C0)  /* DWORD reg */

+#define REG_RSS_KEY5                            (0x14C4)  /* DWORD reg */

+#define REG_RSS_KEY6                            (0x14C8)  /* DWORD reg */

+#define REG_RSS_KEY7                            (0x14CC)  /* DWORD reg */

+#define REG_RSS_KEY8                            (0x14D0)  /* DWORD reg */

+#define REG_RSS_KEY9                            (0x14D4)  /* DWORD reg */

+

+#define REG_RSS_IDT_TABLE0                      (0x14E0)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE1                      (0x14E4)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE2                      (0x14E8)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE3                      (0x14EC)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE4                      (0x14F0)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE5                      (0x14F4)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE6                      (0x14F8)  /* DWORD reg */

+#define REG_RSS_IDT_TABLE7                      (0x14FC)  /* DWORD reg */

+

+#define REG_RSS_HASH_VAL                        (0x15B0)  /* DWORD reg */

+#define REG_RSS_HASH_FLAG                       (0x15B4)  /* DOWRD reg */

+

+#define REG_RSS_BASE_CPU_NUMBER                 (0x15B8)  /* DWORD reg */

+

+#define REG_TXQ_CTRL                            (0x1590)  /* DWORD reg */

+    #define TXQ_CTRL_NUM_TPD_BURST_OFF          0

+    #define TXQ_CTRL_NUM_TPD_BURST_BITS         4

+    #define TXQ_CTRL_NUM_TPD_BURST_DEF          5

+    #define TXQ_CTRL_IP_OPT_SP_OFF              4

+    #define TXQ_CTRL_IP_OPT_SP_BITS             1

+    #define TXQ_CTRL_EN_OFF                     5

+    #define TXQ_CTRL_EN_BITS                    1

+    #define TXQ_CTRL_MODE_OFF                   6

+    #define TXQ_CTRL_MODE_BITS                  1

+    #define TXQ_CTRL_MODE_ENH                   1

+    #define TXQ_CTRL_EN_SNAP_LSO_OFF            7

+    #define TXQ_CTRL_EN_SNAP_LSO_BITS           1

+    #define TXQ_CTRL_NUM_TXF_BURST_OFF          16

+    #define TXQ_CTRL_NUM_TXF_BURST_BITS         16

+    

+    

+#define REG_TXQ_JUMBO_TSO_THRESHOLD             (0x1594)  /* DWORD reg */

+

+#define REG_TXQ_TXF_BURST_L1                    (0x1598)  /* DWORD reg */

+    #define TXQ_TXF_BURST_L1_LWM_OFF            0

+    #define TXQ_TXF_BURST_L1_LWM_BITS           12

+    #define TXQ_TXF_BURST_L1_HWM_OFF            16

+    #define TXQ_TXF_BURST_L1_HWM_BITS           12

+    #define TXQ_TXF_BURST_L1_EN_OFF             31

+    #define TXQ_TXF_BURST_L1_EN_BITS            1

+

+

+#define REG_THRUPUT_MON_CTRL                    (0x159C)  /* DWORD reg */

+    #define THRUPUT_MON_CTRL_RATE_OFF           0

+    #define THRUPUT_MON_CTRL_RATE_BITS          2

+    

+    #define THRUPUT_MON_CTRL_EN_OFF             7

+    #define THRUPUT_MON_CTRL_EN_BITS            1

+    

+#define REG_RXQ_CTRL                            (0x15A0)  /* DWORD reg */

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_OFF       0

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_BITS      2

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_NO        0

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_1MB       1

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_10MB      2

+    #define RXQ_CTRL_ASPM_THRUPUT_LIM_100MB     3

+    #define RXQ_CTRL_Q1_EN_OFF                  4

+    #define RXQ_CTRL_Q1_EN_BITS                 1

+    #define RXQ_CTRL_Q2_EN_OFF                  5

+    #define RXQ_CTRL_Q2_EN_BITS                 1

+    #define RXQ_CTRL_Q3_EN_OFF                  6

+    #define RXQ_CTRL_Q3_EN_BITS                 1

+    #define RXQ_CTRL_IPV6_XSUM_EN_OFF           7

+    #define RXQ_CTRL_IPV6_XSUM_EN_BITS          1

+    #define RXQ_CTRL_RSS_HASH_BITS_OFF          8

+    #define RXQ_CTRL_RSS_HASH_BITS_BITS         8

+    #define RXQ_CTRL_RSS_HASH_TYPE_IPV4_OFF     16

+    #define RXQ_CTRL_RSS_HASH_TYPE_IPV4_TCP_OFF 17

+    #define RXQ_CTRL_RSS_HASH_TYPE_IPV6_OFF     18

+    #define RXQ_CTRL_RSS_HASH_TYPE_IPV6_TCP_OFF 19

+    #define RXQ_CTRL_NUM_RFD_PREF_OFF           20

+    #define RXQ_CTRL_NUM_RFD_PREF_BITS          6

+    #define RXQ_CTRL_NUM_RFD_PREF_DEF           8

+    #define RXQ_CTRL_RSS_MODE_OFF               26

+    #define RXQ_CTRL_RSS_MODE_BITS              2

+    #define RXQ_CTRL_RSS_MODE_DIS               0

+    #define RXQ_CTRL_RSS_MODE_SQSI              1

+    #define RXQ_CTRL_RSS_MODE_MQSI              2

+    #define RXQ_CTRL_RSS_MODE_MQMI              3

+    #define RXQ_CTRL_NIP_QUEUE_SEL_OFF          28

+    #define RXQ_CTRL_NIP_QUEUE_SEL_BITS         1

+    #define RXQ_CTRL_RSS_HASH_EN_OFF            29

+    #define RXQ_CTRL_RSS_HASH_EN_BITS           1

+    #define RXQ_CTRL_CUT_THRU_OFF               30

+    #define RXQ_CTRL_CUT_THRU_BITS              1

+    #define RXQ_CTRL_EN_OFF                     31

+    #define RXQ_CTRL_EN_BITS                    1

+    

+#define REG_RFD_PREF_CTRL                       (0x15A4)

+    #define RFD_PREF_CTRL_UP_TH_OFF             0

+    #define RFD_PREF_CTRL_UP_TH_BITS            6

+    #define RFD_PREF_CTRL_UP_TH_DEF             16

+    #define RFD_PREF_CTRL_LOW_TH_OFF            6

+    #define RFD_PREF_CTRL_LOW_TH_BITS           6

+    #define RFD_PREF_CTRL_LOW_TH_DEF            8

+        

+    

+#define REG_FC_RXF_HI                           (0x15A8)  /* WORD reg */

+#define REG_FC_RXF_LO                           0x15AA  /* WORD reg */

+

+#define REG_RXD_CTRL                            (0x15AC)  /* DWORD reg */

+    #define RXD_CTRL_THRESHOLD_OFF              0

+    #define RXD_CTRL_THRESHOLD_BITS             12

+    #define RXD_CTRL_TIMER_OFF                  16

+    #define RXD_CTRL_TIMER_BITS                 16

+

+

+#define REG_DMA_CTRL                            (0x15C0)  /* DWORD reg */

+    #define DMA_CTRL_ORDER_MODE_OFF             0

+    #define DMA_CTRL_ORDER_MODE_BITS            3

+    #define DMA_CTRL_ORDER_MODE_IN              1

+    #define DMA_CTRL_ORDER_MODE_ENH             2

+    #define DMA_CTRL_ORDER_MODE_OUT             4    

+    #define DMA_CTRL_RCB_VAL_OFF                3

+    #define DMA_CTRL_RCB_VAL_BITS               1

+    #define DMA_CTRL_REGRDBLEN_OFF              4

+    #define DMA_CTRL_REGRDBLEN_BITS             3

+    #define DMA_CTRL_REGWRBLEN_OFF              7

+    #define DMA_CTRL_REGWRBLEN_BITS             3

+    #define DMA_CTRL_DMAR_REQ_PRI_OFF           10

+    #define DMA_CTRL_DMAR_REQ_PRI_BITS          1

+    #define DMA_CTRL_DMAR_DLY_CNT_OFF           11

+    #define DMA_CTRL_DMAR_DLY_CNT_BITS          5

+    #define DMA_CTRL_DMAR_DLY_CNT_DEF           15

+    #define DMA_CTRL_DMAW_DLY_CNT_OFF           16

+    #define DMA_CTRL_DMAW_DLY_CNT_BITS          4

+    #define DMA_CTRL_DMAW_DLY_CNT_DEF           4

+    #define DMA_CTRL_CMB_EN_OFF                 20

+    #define DMA_CTRL_CMB_EN_BITS                1

+    #define DMA_CTRL_SMB_DMA_SP_OFF             21 /* enable SMB DMA */

+    #define DMA_CTRL_SMB_DMA_SP_BITS            1

+    #define DMA_CTRL_CMB_NOW_OFF                22

+    #define DMA_CTRL_CMB_NOW_BITS               1

+    #define DMA_CTRL_SMB_DIS_OFF                24

+    #define DMA_CTRL_SMB_DIS_BITS               1

+    #define DMA_CTRL_SMB_NOW_OFF                31

+    #define DMA_CTRL_SMB_NOW_BITS               1

+ 

+#define REG_SMB_DIS                             (0x15C3)  /* BYTE reg */    

+    

+#define REG_SMB_TIMER                           (0x15C4 ) /* DWORD reg */

+

+#define REG_CMB_TPD_THRESHOLD                   (0x15C8)  /* WORD reg */

+#define REG_CMB_TIMER                           (0x15CC)  /* WORD reg */

+

+#define REG_RFD0_PROD_INDEX                     (0x15E0)  /* WORD reg */

+#define REG_RFD1_PROD_INDEX                     (0x15E4)  /* WORD reg */

+#define REG_RFD2_PROD_INDEX                     (0x15E8)  /* WORD reg */

+#define REG_RFD3_PROD_INDEX                     (0x15EC) /* WORD reg */

+

+#define REG_HTPD_PROD_INDEX                     (0x15F0)  /* WORD reg */

+#define REG_NTPD_PROD_INDEX                     (0x15F2)  /* WORD reg */

+#define REG_HTPD_CONS_INDEX                     (0x15F4)  /* WORD reg, ro */

+#define REG_NTPD_CONS_INDEX                     (0x15F6)  /* WORD reg, ro */

+

+#define REG_RFD0_CONS_INDEX                     (0x15F8)  /* WORD reg, ro */

+#define REG_RFD1_CONS_INDEX                     (0x15FA)  /* WORD reg, ro */

+#define REG_RFD2_CONS_INDEX                     (0x15FC)  /* WORD reg, ro */

+#define REG_RFD3_CONS_INDEX                     (0x15FE)  /* WORD reg, ro */

+

+

+#define REG_ISR                                 (0x1600)  /* DWORD reg */

+    #define ISR_SMB_OFF                         0

+  

+    #define ISR_TIMER_OFF                       1

+ 

+    #define ISR_SW_MANUAL_OFF                   2

+    #define ISR_SW_MANUAL_BITS                  1

+    #define ISR_RXF_OV_OFF                      (1<<3)

+    #define ISR_RXF_OV_BITS                     1

+    #define ISR_RFD0_UR_OFF                     (1<<4)

+    #define ISR_RFD0_UR_BITS                    1

+    #define ISR_RFD1_UR_OFF                     5

+    #define ISR_RFD1_UR_BITS                    1   

+    #define ISR_RFD2_UR_OFF                     6

+    #define ISR_RFD2_UR_BITS                    1

+    #define ISR_RFD3_UR_OFF                     7

+    #define ISR_RFD3_UR_BITS                    1

+    #define ISR_TXF_UR_OFF                      8

+    #define ISR_TXF_UR_BITS                     1

+    #define ISR_DMAR_OFF                        (1<<9)

+    #define ISR_DMAR_BITS                       1

+    #define ISR_DMAW_OFF                        (1<<10)

+    #define ISR_DMAW_BITS                       1

+    #define ISR_TX_CREDIT_OFF                   11

+    #define ISR_TX_CREDIT_BITS                  1

+    #define ISR_GPHY_OFF                        (1<<12)

+    #define ISR_GPHY_BITS                       1

+    #define ISR_GPHY_LPW_OFF                    (1<<13)

+    #define ISR_GPHY_LPW_BITS                   1

+    #define ISR_TXQ_OFF                         (1<<14)

+    #define ISR_TXQ_BITS                        1

+    #define ISR_TX_PKT_OFF                      (1<<15)

+    #define ISR_TX_PKT_BITS                     1

+    #define ISR_RX0_PKT_OFF                     (1<<16)

+    #define ISR_RX0_PKT_BITS                    1

+    #define ISR_RX1_PKT_OFF                     17

+    #define ISR_RX1_PKT_BITS                    1

+    #define ISR_RX2_PKT_OFF                     18

+    #define ISR_RX2_PKT_BITS                    1

+    #define ISR_RX3_PKT_OFF                     19

+    #define ISR_RX3_PKT_BITS                    1

+    #define ISR_MAC_RX_OFF                      20

+    #define ISR_MAC_RX_BITS                     1

+    #define ISR_MAC_TX_OFF                      21

+    #define ISR_MAC_TX_BITS                     1

+    #define ISR_PCIE_UR_OFF                     22

+    #define ISR_PCIE_UR_BITS                    1

+    #define ISR_PCIE_FERR_OFF                   23

+    #define ISR_PCIE_FERR_BITS                  1

+    #define ISR_PCIE_NFERR_OFF                  24

+    #define ISR_PCIE_NFERR_BITS                 1

+    #define ISR_PCIE_CERR_OFF                   25

+    #define ISR_PCIE_CERR_BITS                  1

+    #define ISR_PCIE_LINKDOWN_OFF               26

+    #define ISR_PCIE_LINKDOWN_BITS              1

+    #define ISR_DIS_OFF                         31

+    #define ISR_DIS_BITS                        1   

+

+#define REG_IMR                                 (0x1604)  /* DWORD reg */

+

+

+#define INT_FATAL_MASK          (\

+    FLAG(ISR_DMAR_OFF)          |\

+    FLAG(ISR_DMAW_OFF)          |\

+    FLAG(ISR_PCIE_FERR_OFF)     |\

+    FLAG(ISR_PCIE_LINKDOWN_OFF) )

+

+    

+#define INT_TX_MASK             (\

+    FLAG(ISR_MAC_TX_OFF)        |\

+    FLAG(ISR_TX_PKT_OFF)        |\

+    FLAG(ISR_TXF_UR_OFF)        )

+    

+#define INT_RX_MASK             (\

+    FLAG(ISR_RXF_OV_OFF)        |\

+ /*   FLAG(ISR_RFD0_UR_OFF)       |*/\

+    FLAG(ISR_RFD1_UR_OFF)       |\

+    FLAG(ISR_RFD2_UR_OFF)       |\

+    FLAG(ISR_RFD3_UR_OFF)       |\

+    FLAG(ISR_RX0_PKT_OFF)       |\

+    FLAG(ISR_RX1_PKT_OFF)       |\

+    FLAG(ISR_RX2_PKT_OFF)       |\

+    FLAG(ISR_RX3_PKT_OFF)       |\

+    FLAG(ISR_MAC_RX_OFF)        )

+

+#define INT_MASK                (\

+    INT_RX_MASK                 |\

+    INT_TX_MASK                 |\

+    INT_FATAL_MASK              |\

+    FLAG(ISR_SMB_OFF)           |\

+    FLAG(ISR_SW_MANUAL_OFF)     |\

+    FLAG(ISR_GPHY_OFF)          |\

+    FLAG(ISR_GPHY_LPW_OFF)      )

+    

+

+    

+

+#define REG_INT_RETRIG_TIMER                    (0x1608)  /* WORD reg */

+

+#define REG_HDS_CTRL                            (0x160C)  /* DWORD reg */

+    #define HDS_CTRL_EN_OFF                     0

+    #define HDS_CTRL_EN_BITS                    1

+    #define HDS_CTRL_BACKFILLSIZE_OFF           8

+    #define HDS_CTRL_BACKFILLSIZE_BITS          12

+    #define HDS_CTRL_MAX_HDRSIZE_OFF            20

+    #define HDS_CTRL_MAX_HDRSIZE_BITS           12

+

+#endif

diff --git a/drivers/net/ak98-mac/Kconfig b/drivers/net/ak98-mac/Kconfig
new file mode 100644
index 00000000000..4425f5f8350
--- /dev/null
+++ b/drivers/net/ak98-mac/Kconfig
@@ -0,0 +1,6 @@
+config AK98_MAC
+	tristate "AK98 MAC Device"
+	depends on ARCH_AK98
+	help
+	  AK98 MAC device support
+
diff --git a/drivers/net/ak98-mac/Makefile b/drivers/net/ak98-mac/Makefile
new file mode 100644
index 00000000000..412ed1907a0
--- /dev/null
+++ b/drivers/net/ak98-mac/Makefile
@@ -0,0 +1,5 @@
+
+
+obj-$(CONFIG_AK98_MAC)	+= ak98_mac.o
+
+
diff --git a/drivers/net/ak98-mac/ak98_mac.c b/drivers/net/ak98-mac/ak98_mac.c
new file mode 100644
index 00000000000..7ed18b7c28a
--- /dev/null
+++ b/drivers/net/ak98-mac/ak98_mac.c
@@ -0,0 +1,1383 @@
+/*
+ * AK98 MAC Fast Ethernet driver for Linux.
+ * Features
+ * Copyright (C) 2010 ANYKA
+ * AUTHOR Tang Anyang
+ * AUTHOR Zhang Jingyuan
+ * 10-11-01 09:08:08
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/init.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/crc32.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+
+#include <asm/delay.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <mach/map.h>
+#include <mach/mac.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+#include <mach/l2cache.h>
+
+#define MACNAME	"ak98_mac"
+#define DRV_VERSION	"1.0"
+#define TPD_RING_SIZE 0x50
+#define RFD_RING_SIZE 0x50
+#define RRD_RING_SIZE 0x50
+
+#include "eth_ops.h"
+#include "Ethernethw.h"
+#include "phyhw.h"
+
+#if 0
+#define dbg(fmt, arg...) printk(KERN_DEBUG "%s(%d): " fmt "\n", __func__, __LINE__, ##arg)
+#else
+#define dbg(fmt, arg...) {}
+#endif
+
+/* rrd format */
+typedef struct _RrdDescr_s {
+
+	unsigned short  xsum;           /*  */
+
+	unsigned short  nor     :4  ;   /* number of RFD */
+	unsigned short  si      :12 ;   /* start index of rfd-ring */
+
+	unsigned short  hash;           /* rss(MSFT) hash value */
+
+	unsigned short  hash1;  
+
+	unsigned short  vidh    :4  ;   /* vlan-id high part */
+	unsigned short  cfi     :1  ;   /* vlan-cfi */ 
+	unsigned short  pri     :3  ;   /* vlan-priority */
+	unsigned short  vidl    :8  ;   /* vlan-id low part */
+	unsigned char   hdr_len;        /* Header Length of Header-Data Split. unsigned short unit */
+	unsigned char   hds_typ :2  ;   /* Header-Data Split Type, 
+									00:no split, 
+									01:split at upper layer protocol header
+									10:split at upper layer payload */
+	unsigned char   rss_cpu :2  ;   /* CPU number used by RSS */
+	unsigned char   hash_t6 :1  ;   /* TCP(IPv6) flag for RSS hash algrithm */
+	unsigned char   hash_i6 :1  ;   /* IPv6 flag for RSS hash algrithm */
+	unsigned char   hash_t4 :1  ;   /* TCP(IPv4)  flag for RSS hash algrithm */
+	unsigned char   hash_i4 :1  ;   /* IPv4 flag for RSS hash algrithm */
+
+	unsigned short  frm_len :14 ;   /* frame length of the packet */        
+	unsigned short  l4f     :1  ;   /* L4(TCP/UDP) checksum failed */
+	unsigned short  ipf     :1  ;   /* IP checksum failed */
+	unsigned short  vtag    :1  ;   /* vlan tag */
+	unsigned short  pid     :3  ;   /* protocol id,
+						  000: non-ip packet
+						  001: ipv4(only)
+						  011: tcp/ipv4
+						  101: udp/ipv4
+						  010: tcp/ipv6
+						  100: udp/ipv6
+						  110: ipv6(only) */
+	unsigned short  res     :1  ;   /* received error summary */
+	unsigned short  crc     :1  ;   /* crc error */
+	unsigned short  fae     :1  ;   /* frame alignment error */
+	unsigned short  trunc   :1  ;   /* truncated packet, larger than MTU */
+	unsigned short  runt    :1  ;   /* runt packet */
+	unsigned short  icmp    :1  ;   /* incomplete packet, due to insufficient rx-descriptor */
+	unsigned short  bar     :1  ;   /* broadcast address received */
+	unsigned short  mar     :1  ;   /* multicast address received */
+	unsigned short  typ     :1  ;   /* type of packet (ethernet_ii(1) or snap(0)) */
+	unsigned short  resv1   :2  ;   /* reserved, must be 0 */
+	unsigned short  updt    :1  ;   /* update by hardware. after hw fulfill the buffer, this bit 
+						  should be 1 */
+} RrdDescr_t, *PRrdDescr_t;
+
+unsigned char *pMacBase = NULL;
+//unsigned char *pSystemBase;
+unsigned char *psysbase;
+unsigned long g_tpdconsumerindex = 0;
+unsigned long g_rfdconsumerindex = 0;
+unsigned long g_rrdconsumerindex = 0;
+bool g_update = false;
+
+//unsigned long rfdaddress = 0;
+unsigned long tpdaddress = 0;
+unsigned long tpdaddressVa = 0;
+void *tpdbufaddressVa = NULL;
+dma_addr_t tpdbufaddressPa = 0;
+unsigned long rrdaddressVa = 0;
+
+void *rfd_sequenceva = NULL;
+dma_addr_t rfd_sequence;
+void *RingbufVa = NULL;
+dma_addr_t RingbufPa;
+
+void *rfdbaseva = NULL;
+dma_addr_t rfdbasepa;
+
+static void ak98_mac_hash_table(struct net_device *ndev);
+
+unsigned long _2xswitchflag = 0;
+static inline void cpu_clk_2x_switch(void)
+{
+	if (ak98_get_cpu_clk() / MHz > 340)
+	{
+		printk("CPU Core > 340 MHz");
+		_2xswitchflag = 1;
+	}
+	else {
+		printk("CPU Core <= 340 MHz");
+		_2xswitchflag = 0;
+	}
+}	
+
+static inline void close_2x(void)
+{
+	if (_2xswitchflag) {
+		udelay(5);
+		REG32(psysbase + 0x04) &= ~(0x1 << 15);
+		udelay(5);
+	}
+}
+static inline void open_2x(void)
+{
+	if (_2xswitchflag) {
+		udelay(5);
+		REG32(psysbase + 0x04) |= (0x1 << 15);
+		udelay(5);
+	}
+}
+
+
+/* Structure/enum declaration ------------------------------- */
+typedef struct mac_info {
+	void __iomem	*io_addr;	/* Register I/O base address */
+	u16		 irq;		/* IRQ */
+
+	u16		tx_pkt_cnt;
+	u16		queue_pkt_len;
+	u16		queue_start_addr;
+	u16		queue_ip_summed;
+	u16		dbug_cnt;
+	u8		io_mode;		/* 0:word, 2:byte */
+	u8		phy_addr;
+	u8		imr_all;
+
+	unsigned int	flags;
+	unsigned int	in_suspend :1;
+
+	void (*inblk)(void __iomem *port, void *data, int length);
+	void (*outblk)(void __iomem *port, void *data, int length);
+	void (*dumpblk)(void __iomem *port, int length);
+
+	struct device	*dev;	     /* parent device */
+
+	struct resource	*addr_res;   /* resources found */
+	struct resource	*addr_req;   /* resources requested */
+	struct resource *irq_res;
+
+	struct mutex	 addr_lock;	/* phy and eeprom access lock */
+
+	struct delayed_work phy_poll;
+	struct net_device  *ndev;
+
+	spinlock_t	lock;
+
+	u32		msg_enable;
+
+	int		rx_csum;
+	int		can_csum;
+	int		ip_summed;
+	struct clk	*clk;
+} mac_info_t;
+
+void MacDelay(unsigned long us)
+{
+	unsigned long i =0;
+	for (i=0; i< 10*us*1000; i++)
+		;
+}
+
+/** * @brief Read Phy Register 
+* Read Phy Register from MII Interface 
+* @author Tang Anyang
+* @date 2010-11-16 
+* @param unsigned long RegAddr: Phy Register address
+* @retval unsigned long: the value of Phy Register. 
+*/
+unsigned long MIIRead(unsigned long RegAddr)
+{
+	unsigned int Val;
+	unsigned short Index;    
+	unsigned short phyVal;
+
+	Val = 
+		MDIO_CTRL_REG_ADDR(RegAddr) |		   
+		MDIO_CTRL_START|
+		MDIO_CTRL_READ;
+
+	REG32(pMacBase + REG_MDIO_CTRL)= Val;
+
+	for (Index=0; Index <MDIO_MAX_AC_TIMER; Index++)
+	{
+		Val = REG32(pMacBase + REG_MDIO_CTRL);
+		if (0 == (Val&FLAG(MDIO_CTRL_BUSY_OFF)))
+		{
+			phyVal = (unsigned short) Val;            
+			goto mr_exit;
+		}
+		MacDelay(10);
+	}
+
+	phyVal = 0;
+
+mr_exit:
+	return phyVal;
+}
+
+/** * @brief Wrtie Phy Register 
+* Write dedicated value to  Phy Register from MII Interface 
+* @author Tang Anyang
+* @date 2010-11-16 
+* @param unsigned long RegAddr: Phy Register address
+* @param  unsigned long phyVal: dedicated value. 
+*/
+void MIIWrite(unsigned long RegAddr, unsigned long phyVal)
+{
+	unsigned int Val;
+	unsigned short Index;
+
+	REG32(pMacBase + REG_MDIO_CTRL)= 0;
+	MacDelay(30);
+	for(Index = 0; Index < MDIO_MAX_AC_TIMER; Index++)
+	{
+		Val = REG32(pMacBase + REG_MDIO_CTRL);
+		if (0 == (Val & FLAG(MDIO_CTRL_BUSY_OFF)))
+		{
+			break;        
+		}
+		MacDelay(10);
+	}
+
+	Val = 
+		MDIO_CTRL_DATA(phyVal) |
+		MDIO_CTRL_REG_ADDR(RegAddr) |MDIO_CTRL_WRITE|		
+		MDIO_CTRL_START;
+
+	REG32(pMacBase +  REG_MDIO_CTRL)= Val;
+
+	for (Index=0; Index <MDIO_MAX_AC_TIMER; Index++)
+	{
+		Val = REG32(pMacBase +  REG_MDIO_CTRL);
+		if (0 == (Val&FLAG(MDIO_CTRL_BUSY_OFF)))
+		{
+
+			return;
+		}
+		MacDelay(10);
+	}
+}
+
+unsigned int HwStopMAC(void)
+{
+	unsigned int Val;
+	unsigned short Index;      
+
+	Val = REG32(pMacBase + REG_RXQ_CTRL);
+	BIT_CLEAR(Val, RXQ_CTRL_EN_OFF);
+	BIT_CLEAR(Val, RXQ_CTRL_Q1_EN_OFF);
+	BIT_CLEAR(Val, RXQ_CTRL_Q2_EN_OFF);
+	BIT_CLEAR(Val, RXQ_CTRL_Q3_EN_OFF);  
+	REG32(pMacBase + REG_RXQ_CTRL) = Val;    
+
+	Val = REG32(pMacBase + REG_TXQ_CTRL);
+	BIT_CLEAR(Val, TXQ_CTRL_EN_OFF);   
+	REG32(pMacBase + REG_TXQ_CTRL) = Val;
+
+	//  waiting for rxq/txq be idle 
+	for (Index=0; Index<50; Index++)
+	{     
+		Val = REG32(pMacBase + REG_IDLE_STATUS);
+		if (BIT_TEST(Val, IDLE_STATUS_RXQ_OFF) ||
+			BIT_TEST(Val, IDLE_STATUS_TXQ_OFF))
+		{
+			MacDelay(20);
+		}
+		else
+			break;
+	}
+
+	// stop mac tx/rx   
+	Val = REG32(pMacBase + REG_MAC_CTRL);
+	BIT_CLEAR(Val, MAC_CTRL_RXEN_OFF);
+	BIT_CLEAR(Val, MAC_CTRL_TXEN_OFF);
+	REG32(pMacBase + REG_MAC_CTRL) = Val;
+
+	MacDelay(10);
+
+	for (Index=0; Index<50; Index++) //
+	{        
+		Val = REG32(pMacBase + REG_IDLE_STATUS);
+		if (0 == (unsigned char)Val)
+			return true;
+
+		MacDelay(20);
+	}
+
+	return false;
+}
+
+void MacRest(void)
+{
+	unsigned long Val =0;
+	unsigned long Index;
+
+	// clear to unmask the corresponding INTs
+	REG32(pMacBase + REG_IMR)= 0x00; 
+	// disable interrupt
+	REG32(pMacBase + REG_ISR)=FLAG(ISR_DIS_OFF);
+
+	HwStopMAC();
+
+	// reset whole-MAC safely 
+	Val = REG32(pMacBase + REG_MASTER_CTRL);
+	BIT_SET(Val, MASTER_CTRL_MAC_SOFT_RST_OFF);
+	REG32(pMacBase + REG_MASTER_CTRL)= Val;    
+
+	MacDelay(50);
+
+	for (Index=0; Index<50; Index++) // wait atmost 1ms 
+	{   
+		Val = REG32(pMacBase + REG_IDLE_STATUS);
+		if (0 == (unsigned char)Val)
+		{
+			return ;
+		}        
+		MacDelay(20);
+	}
+
+	return;
+}
+
+bool InitEthernetMemory(void)
+{
+	int i;
+	unsigned long *tempp;
+
+	if (RingbufVa == NULL)
+		RingbufVa = dma_alloc_coherent(NULL, TPD_RING_SIZE * 16 + RRD_RING_SIZE * 16, &RingbufPa, GFP_KERNEL);
+	if(RingbufVa == NULL)
+	{
+		dbg("Alloc Memory for RingBuf Failed!");
+		return false;
+	}
+	if (rfd_sequenceva == NULL)
+		rfd_sequenceva = dma_alloc_coherent(NULL, RFD_RING_SIZE * 8, &rfd_sequence, GFP_KERNEL);
+	if (rfd_sequenceva == NULL)
+	{
+		dbg("Alloc rfd sequence buffer failed!");
+		return false;
+	}
+
+	if (tpdbufaddressVa == NULL)
+		tpdbufaddressVa = dma_alloc_coherent(NULL, TPD_RING_SIZE * 1520, &tpdbufaddressPa, GFP_KERNEL);
+	if(tpdbufaddressVa == NULL)
+	{
+		dbg("Alloc tpd sequence buffer failed!");
+		return false;
+	}
+	if (rfdbaseva == NULL)
+		rfdbaseva = dma_alloc_coherent(NULL, RFD_RING_SIZE * 1520, &rfdbasepa, GFP_KERNEL);
+	if(rfdbaseva == NULL)
+	{
+		dbg("Alloc rfd  buffer failed!");
+		return false; 	
+	}
+
+	tempp = rfd_sequenceva;
+	for(i = 0; i < TPD_RING_SIZE; i++)
+	{
+		*tempp = rfdbasepa + i*1520;	
+		tempp++;
+
+		*tempp =0x00;
+		tempp++;
+	}
+
+	return true;
+}
+
+bool init_hw(struct net_device *ndev)
+{
+	unsigned long Val = 0;
+	unsigned long IntModerate = 100;//500000/5000;
+
+	unsigned int mac_addL;
+	unsigned int mac_addH;
+	
+	unsigned long rrdaddress;
+
+	g_tpdconsumerindex = 0;
+	g_rfdconsumerindex = 0;
+	g_rrdconsumerindex = 0;
+
+	MacRest();
+	
+	ak98_gpio_cfgpin(AK98_GPIO_98, AK98_GPIO_DIR_OUTPUT);
+	ak98_gpio_setpin(AK98_GPIO_98, AK98_GPIO_LOW);
+	mdelay(10);
+	ak98_gpio_cfgpin(AK98_GPIO_98, AK98_GPIO_DIR_INPUT);
+	mdelay(1);
+	
+#if 0
+	MIIWrite(MII_BMCR,0x8000);
+
+	mdelay(50);
+	
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+	
+	while(MIIRead(MII_BMCR)&0x8000)
+	{
+		dbg("BMCR:0x%lx", MIIRead(MII_BMCR));
+	}
+#endif
+	dbg("BMCR:0x%lx", MIIRead(MII_BMCR));
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+	dbg("PHYSID1:0x%lx, PHYSID2:0x%lx", MIIRead(MII_PHYSID1), MIIRead(MII_PHYSID2));
+
+	MIIWrite(MII_BMCR, MIIRead(MII_BMCR) | 0x1100);
+	dbg("BMCR:0x%lx", MIIRead(MII_BMCR));
+	dbg("GIGA_PSSR:0x%lx", MIIRead(MII_GIGA_PSSR));
+
+	/* set mac-address */
+	mac_addL = ndev->dev_addr[5] | (ndev->dev_addr[4] << 8)
+			| (ndev->dev_addr[3] << 16) | (ndev->dev_addr[2] << 24);
+	mac_addH = ndev->dev_addr[1] | (ndev->dev_addr[0] << 8);
+
+	REG32(pMacBase + REG_MAC_STA_ADDR)= mac_addL;
+	REG32(pMacBase + REG_MAC_STA_ADDR+4)= mac_addH;
+
+	// clear the Multicast HASH table 
+	REG32(pMacBase + REG_RX_HASH_TABLE) = 0x00;
+	REG32(pMacBase + REG_RX_HASH_TABLE+4)= 0x00;
+
+	// clear any WOL setting/status /
+	Val = REG32(pMacBase + REG_WOL_CTRL);
+	REG32(pMacBase + REG_WOL_CTRL)=0x00;
+
+	tpdaddressVa = (unsigned long)RingbufVa;
+	// tx/rx/smb Ring BaseMem 
+	REG32(pMacBase + REG_NTPD_HDRADDR_LO) = RingbufPa;//NTPD_HDRADDR_LO
+	REG32(pMacBase + REG_HTPD_HDRADDR_LO)= RingbufPa;//HTPD_HDRADDR_LO
+	REG32(pMacBase + REG_TX_BASE_ADDR_HI) = 0x00;//TX_BASE_ADDR_HI
+	REG32(pMacBase + REG_TPD_RING_SIZE)= TPD_RING_SIZE;//TPD_RING_SIZE
+
+	REG32(pMacBase + REG_RX_BASE_ADDR_HI)= 0x00;//RX_BASE_ADDR_HI
+
+	REG32(pMacBase + REG_RFD0_HDRADDR_LO) = rfd_sequence;//RFD0_HDRADDR_LO    
+
+	REG32(pMacBase + REG_RFD1_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RFD2_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RFD3_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RFD_RING_SIZE)= RFD_RING_SIZE;//RFD_RING_SIZE
+	REG32(pMacBase + REG_RFD_BUFFER_SIZE)= 0x600;//RFD_BUFFER_SIZE	
+
+	rrdaddress = RingbufPa + TPD_RING_SIZE * 16;
+	rrdaddressVa = (unsigned long)RingbufVa +  TPD_RING_SIZE * 16;
+
+	REG32(pMacBase + REG_RRD0_HDRADDR_LO)= rrdaddress; // RRD0_HDRADDR_LO  
+	REG32(pMacBase + REG_RRD1_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RRD2_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RRD3_HDRADDR_LO)= 0x00;
+	REG32(pMacBase + REG_RRD_RING_SIZE)= RRD_RING_SIZE;//REG_RRD_RING_SIZE
+
+
+	REG32(pMacBase + REG_TXQ_TXF_BURST_L1)= 0;// TX watermark, to enter l1 state. 
+	REG32(pMacBase + REG_RXD_CTRL)= 0; // RXD threshold. 
+
+	// load all base/mem ptr	 
+	REG32(pMacBase + REG_SRAM_LOAD_PTR)= FLAG(SRAM_LOAD_PTR_OFF);
+
+	// set Interrupt Moderator Timer (max interrupt per sec)
+	// we use seperate time for rx/tx 
+	REG16(pMacBase + REG_IRQ_MODRT_INIT)= IntModerate * 2;
+	REG16(pMacBase + REG_IRQ_MODRT_RX_INIT)= IntModerate; 
+
+	// set Interrupt Clear Timer
+	// HW will enable self to assert interrupt event to system after
+	// waiting x-time for software to notify it accept interrupt.	  
+
+	REG32(pMacBase + REG_INT_RETRIG_TIMER)= 10000;// 20ms 
+
+	// Enable Read-Clear Interrupt Mechanism   
+	Val = FLAG(MASTER_CTRL_INT_RCLR_EN_OFF);
+	BIT_SET(Val, MASTER_CTRL_SA_TIMER_EN_OFF);
+	REG32(pMacBase + REG_MASTER_CTRL)= Val;
+
+	REG32(pMacBase + REG_FC_RXF_HI)= 0x03300400;
+	REG32(pMacBase + REG_TXQ_JUMBO_TSO_THRESHOLD)= 0xbf;
+
+	// set MTU	 
+	REG32(pMacBase + REG_MTU)= 1540;
+
+	// set DMA		
+	//mac_set_reg(REG_DMA_CTRL, 0x347ed1);//DMA Engine Control 
+	//mac_set_reg(REG_DMA_CTRL, 0x47C20);//DMA Engine Control 
+	//REG32(pMacBase + REG_DMA_CTRL)= 0x47C10;
+	REG32(pMacBase + REG_DMA_CTRL)= 0x47C14;
+
+	// set TXQ	 
+	REG32(pMacBase + REG_TXQ_CTRL)= 0x01000025;
+
+	// set RXQ	
+	//mac_set_reg(0x600015a0, 0xc08f10f0); 
+	REG32(pMacBase + REG_RXQ_CTRL)= 0xC0800000; 
+	
+	// rfd producer index	 
+	REG32(pMacBase + REG_RFD0_PROD_INDEX)= RFD_RING_SIZE - 1; 
+
+	//set MAC control
+	//REG32(pMacBase + REG_MAC_CTRL)= 0x0e10dcef;//MAC control register
+	REG32(pMacBase + REG_MAC_CTRL)= 0x06105cef;//MAC control register
+
+	REG32(pMacBase + REG_IMR)= 0x1d608;//Interrupt Mask 
+	MIIWrite(MII_IER, 0x0c00);
+
+	ak98_mac_hash_table(ndev);
+
+	return true;
+}
+
+/** * @brief Initialize Mac 
+* Initialize MAC and PHY 
+* @author Tang Anyang
+* @date 2010-11-16 
+* @param unsigned char * MacAddress: 
+*/
+bool MacInit(struct net_device *ndev)
+{
+	//struct mac_info *db;
+	volatile unsigned long count;
+	
+	//db = netdev_priv(ndev);
+	close_2x();
+	
+	//to enable the 25MHz oscillator
+	//TODO: Need to be changed to new clock API
+	REG32(psysbase + 0x54) |= (1 << 23);
+	
+	//unreset MAC module
+	count = 10000;
+	while(count--);
+	REG32(psysbase + 0x10) &= ~(1 << 30);
+	count = 10000;
+	
+	while(count--);
+	
+	//to enable the 25MHz oscillator
+	REG32(psysbase + 0x54) |= (1 << 23);
+	
+	count = 10000;
+	//reset MAC module
+	while(count--);
+	REG32(psysbase + 0x10) |= (1 << 30);
+	count = 10000;
+	
+	while(count--);
+	
+	//unreset MAC module
+	REG32(psysbase + 0x10) &= ~(1 << 30);
+	count = 10000;
+	
+	while(count--);
+
+	if (false == InitEthernetMemory())
+		return false;
+	
+	if (false == init_hw(ndev))
+		return false;
+
+	open_2x();
+
+	return true;
+}
+
+void Macexit(struct net_device *ndev)
+{
+	if (rfd_sequenceva) {
+		dma_free_coherent(NULL, RFD_RING_SIZE * 4, rfd_sequenceva, rfd_sequence);
+		rfd_sequenceva = NULL;
+		rfd_sequence = 0;
+	}
+
+	if (tpdbufaddressVa) {
+		dma_free_coherent(NULL, TPD_RING_SIZE * 1520, tpdbufaddressVa, tpdbufaddressPa);
+		tpdbufaddressVa = NULL;
+		tpdbufaddressPa = 0;
+	}
+
+	if (rfdbaseva) {
+		dma_free_coherent(NULL, RFD_RING_SIZE * 1520, rfdbaseva, rfdbasepa);
+		rfdbaseva = NULL;
+		rfdbasepa = 0;
+	}
+
+	if (RingbufVa) {
+		dma_free_coherent(NULL, TPD_RING_SIZE * 16 + RRD_RING_SIZE * 16, RingbufVa, RingbufPa);
+		RingbufVa = NULL;
+		RingbufPa = 0;
+	}
+}
+
+unsigned long GetPacketCount(void)
+{
+	unsigned long ulNewRfdConsIdx = 0;
+
+	ulNewRfdConsIdx = REG32(pMacBase +  REG_RFD0_CONS_INDEX);
+
+	dbg("ulNewRfdConsIdx:0x%lx, g_rfdconsumerindex:%lx", ulNewRfdConsIdx, g_rfdconsumerindex);
+
+	return ulNewRfdConsIdx - g_rfdconsumerindex;
+}
+
+long ReceivePacket(struct net_device *ndev)
+{
+	PRrdDescr_t prrd;
+	short length;
+	static unsigned long g_wait_count = 0;
+	unsigned char *sendbuffer;
+	struct sk_buff *skb;
+
+	ak98_l2cache_invalidate();
+	
+	prrd = (PRrdDescr_t)(rrdaddressVa + g_rfdconsumerindex*16);
+	length = prrd->frm_len;
+	dbg("g_rfdconsumerindex:%lx, length:%x, updt:%d", 
+		g_rfdconsumerindex, length, prrd->updt); 
+
+	if (length == 0)
+	{
+		if (prrd->nor == 0)
+		{
+			if (g_update)
+			{
+				g_rrdconsumerindex = g_rfdconsumerindex;
+				g_update = false;
+			}
+		}
+		length = 0;
+
+		g_rfdconsumerindex++;
+		g_rfdconsumerindex %= RFD_RING_SIZE;
+		
+		return length;
+	}
+
+	if (prrd->updt == 0)
+
+	{
+		g_wait_count++;
+
+		if (g_wait_count < 5)
+		{
+			length = -1;
+			
+			return length;
+		}
+	}
+	g_wait_count = 0;
+	prrd->updt = 0;
+	prrd->frm_len = 0;
+
+	sendbuffer = (unsigned char *)(rfdbaseva + (g_rfdconsumerindex)*1520);
+
+	skb = dev_alloc_skb(length + 2);
+	skb_reserve(skb, 2);
+	skb->dev = ndev;
+	memcpy(skb_put(skb, length), sendbuffer, length);
+	skb->protocol = eth_type_trans(skb, ndev);
+
+	netif_rx(skb);
+
+	ndev->last_rx = jiffies;
+	ndev->stats.rx_packets++;
+	ndev->stats.rx_bytes += length;
+	
+	REG32(pMacBase + REG_RFD0_PROD_INDEX) = g_rfdconsumerindex;
+
+	g_rfdconsumerindex++;
+	g_rfdconsumerindex %= RFD_RING_SIZE;
+	
+	return length;
+}
+
+void SendPacket(unsigned char *sendbuffer, unsigned long length)
+{
+	int tpdvalue = 0x80000000;	
+	unsigned char *RingbufVa;
+	unsigned long tpdbufv; 
+
+	RingbufVa = (unsigned char *)(tpdbufaddressVa+g_tpdconsumerindex*1520);
+	memcpy(RingbufVa, sendbuffer, length);
+
+	tpdbufv = tpdaddressVa + g_tpdconsumerindex*16; 
+
+	REG32(tpdbufv)= (unsigned long)0x3aa00000+length;
+	dbg("Send 0x%lx", length);
+
+	tpdbufv += 4;
+	REG32(tpdbufv)= tpdvalue;
+
+	tpdbufv += 4;
+
+	close_2x();
+	REG32(tpdbufv)= tpdbufaddressPa + g_tpdconsumerindex*1520;
+
+	tpdbufv += 4;
+	
+	g_tpdconsumerindex++;
+	
+	g_tpdconsumerindex %= TPD_RING_SIZE;
+	REG32(pMacBase + REG_HTPD_PROD_INDEX) = g_tpdconsumerindex;
+
+	open_2x();
+	
+	return;
+}
+
+/* ak98_mac_release_board
+ *
+ * release a board, and any mapped resources
+ */
+
+static void
+ak98_mac_release_board(struct platform_device *pdev, struct mac_info *db)
+{
+	/* unmap our resources */
+
+	iounmap(db->io_addr);
+
+	/* release the resources */
+
+	release_resource(db->addr_req);
+	kfree(db->addr_req);
+}
+
+/*
+ * Set AK98 MAC address
+ */
+static int set_mac_address(struct net_device *ndev, void *p)
+{
+	struct sockaddr *addr = p;
+
+	if (netif_running(ndev))
+		return -EBUSY;
+	if (!is_valid_ether_addr(addr->sa_data))
+		return -EADDRNOTAVAIL;
+
+	memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
+
+	/* set the Ethernet address */
+	REG32(pMacBase + REG_MAC_STA_ADDR) = ndev->dev_addr[0] | (ndev->dev_addr[1] << 8)
+			| (ndev->dev_addr[2] << 16) | (ndev->dev_addr[3] << 24);
+	REG32(pMacBase + REG_MAC_STA_ADDR + 4) = ndev->dev_addr[4] | (ndev->dev_addr[5] << 8);
+
+	return 0;
+}
+
+/*
+ * atl1c_hash_mc_addr
+ * 	purpose
+ * 		set hash value for a multicast address
+ * 		hash calcu processing :
+ * 			1. calcu 32bit CRC for multicast address
+ * 			2. reverse crc with MSB to LSB
+ */
+u32 ak98_mac_hash_mc_addr(u8 *mc_addr)
+{
+	u32 crc32;
+	u32 value = 0;
+	int i;
+
+	crc32 = ether_crc_le(6, mc_addr);
+	for (i = 0; i < 32; i++)
+		value |= (((crc32 >> i) & 1) << (31 - i));
+
+	return value;
+}
+
+/*
+ * Sets the bit in the multicast table corresponding to the hash value.
+ * hw - Struct containing variables accessed by shared code
+ * hash_value - Multicast address hash value
+ */
+void ak98_mac_hash_set(u32 hash_value)
+{
+	u32 hash_bit, hash_reg;
+	u32 mta;
+
+	/*
+	 * The HASH Table  is a register array of 2 32-bit registers.
+	 * It is treated like an array of 64 bits.  We want to set
+	 * bit BitArray[hash_value]. So we figure out what register
+	 * the bit is in, read it, OR in the new bit, then write
+	 * back the new value.  The register is determined by the
+	 * upper bit of the hash value and the bit within that
+	 * register are determined by the lower 5 bits of the value.
+	 */
+	hash_reg = (hash_value >> 31) & 0x1;
+	hash_bit = (hash_value >> 26) & 0x1F;
+
+	if (hash_reg == 0)
+		mta = REG32(pMacBase + REG_RX_HASH_TABLE);
+	else
+		mta = REG32(pMacBase + REG_RX_HASH_TABLE + 4);
+
+	mta |= (1 << hash_bit);
+	if (hash_reg == 0)
+		REG32(pMacBase + REG_RX_HASH_TABLE) = mta;
+	else
+		REG32(pMacBase + REG_RX_HASH_TABLE + 4) = mta;
+}
+
+/*
+ *  Set AK98 MAC multicast address
+ */
+static void
+ak98_mac_hash_table(struct net_device *ndev)
+{
+	struct dev_mc_list *mc_ptr;
+	u32 mac_ctrl_data;
+	u32 hash_value;
+
+	/* Check for Promiscuous and All Multicast modes */
+	mac_ctrl_data = REG32(pMacBase + REG_MAC_CTRL);
+
+	if (ndev->flags & IFF_PROMISC) {
+		mac_ctrl_data |= FLAG(MAC_CTRL_PROM_MODE_OFF);
+	} else if (ndev->flags & IFF_ALLMULTI) {
+		mac_ctrl_data |= FLAG(MAC_CTRL_MUTI_ALL_OFF);
+		mac_ctrl_data &= ~(FLAG(MAC_CTRL_PROM_MODE_OFF));
+	} else {
+		mac_ctrl_data &= ~(FLAG(MAC_CTRL_MUTI_ALL_OFF) | FLAG(MAC_CTRL_PROM_MODE_OFF));
+	}
+
+	REG32(pMacBase + REG_MAC_CTRL) = mac_ctrl_data;
+
+	/* clear the old settings from the multicast hash table */
+	REG32(pMacBase + REG_RX_HASH_TABLE) = 0;
+	REG32(pMacBase + REG_RX_HASH_TABLE + 4) = 0;;
+
+	/* comoute mc addresses' hash value ,and put it into hash table */
+	for (mc_ptr = ndev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
+		hash_value = ak98_mac_hash_mc_addr(mc_ptr->dmi_addr);
+		ak98_mac_hash_set(hash_value);
+	}
+}
+
+/* Our watchdog timed out. Called by the networking layer */
+static void ak98_mac_timeout(struct net_device *ndev)
+{
+	/* Initialize AK98 MAC */
+	if (MacInit(ndev) == false) {
+		printk("Mac reset fail\n");
+		return;
+	}
+
+	netif_wake_queue(ndev);
+}
+
+/*
+ *  Hardware start transmission.
+ *  Send a packet to media from the upper layer.
+ */
+static int
+ak98_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	unsigned long flags;
+	int len;
+	char *data, shortpkt[ETH_ZLEN];
+	mac_info_t *db = netdev_priv(ndev);
+
+	/* keep the upload from being interrupted, since we
+	 *     ask the chip to start transmitting before the
+	 *     whole packet has been completely uploaded. */
+	spin_lock_irqsave(&db->lock, flags);
+	data = skb->data;
+	len = skb->len;
+	if (len < ETH_ZLEN) {
+		memset(shortpkt, 0, ETH_ZLEN);
+		memcpy(shortpkt, skb->data, skb->len);
+		len = ETH_ZLEN;
+		data = shortpkt;
+	}
+	netif_stop_queue(ndev);
+
+	SendPacket(data, len);
+	spin_unlock_irqrestore(&db->lock, flags);
+	ndev->stats.tx_bytes += skb->len;
+	ndev->trans_start = jiffies;
+	dev_kfree_skb(skb);
+
+	return NETDEV_TX_OK;
+}
+
+int receive(struct net_device *ndev)
+{
+	int length = 0;
+
+	g_rfdconsumerindex = g_rrdconsumerindex;
+	g_update = true;
+	
+	while (GetPacketCount())
+	{
+		length = ReceivePacket(ndev);
+		if (length == 0)
+			break;
+		else if (length == -1)
+			continue;
+	}
+	if(g_update)
+		g_rrdconsumerindex = g_rfdconsumerindex;
+	
+	return length;
+}
+
+static irqreturn_t ak98_mac_interrupt(int irq, void *dev_id)
+{
+	struct net_device *ndev = dev_id;
+	mac_info_t *db = netdev_priv(ndev);
+	unsigned long flags;
+	unsigned long IntStatus = 0;
+	unsigned long status;
+	
+	/* holders of db->lock must always block IRQs */
+	spin_lock_irqsave(&db->lock, flags);
+
+	close_2x();
+	IntStatus = REG32(pMacBase + REG_ISR);
+
+	dbg("IntStatus %lx", IntStatus);
+
+	if(IntStatus & ISR_GPHY_OFF) {
+		unsigned long dwPHYIntStatus = MIIRead(MII_ISR);
+		if(dwPHYIntStatus & (ISR_LINK_DOWN | ISR_LINK_UP)) {
+			status = MIIRead(MII_BMSR);
+			dbg("BMSR: 0x%lx", status);
+			if ((status & BMSR_LINK_STATUS) == 0) {
+				netif_carrier_off(ndev);
+				dbg("%s: link down", ndev->name);
+			} else {
+				netif_carrier_on(ndev);
+				dbg("%s: link up", ndev->name);
+			}
+		}
+		REG32(pMacBase + REG_ISR) = ISR_GPHY_OFF;
+	}
+	if(IntStatus & ISR_GPHY_LPW_OFF) {
+		unsigned long dwPHYIntStatus = MIIRead(MII_ISR);
+		if(dwPHYIntStatus & ISR_LINK_UP) {
+			//SetNetLinkStatus(TRUE); 
+			netif_carrier_on(ndev);
+			dbg("%s: low power state link up", ndev->name);
+		}
+		if(dwPHYIntStatus & ISR_LINK_DOWN) {
+			//SetNetLinkStatus(FALSE); 
+			netif_carrier_off(ndev);
+			dbg("%s: low power state link down", ndev->name);
+		}
+	}
+	
+	if(IntStatus & ISR_TX_PKT_OFF) {
+		REG32(pMacBase + REG_ISR) = ISR_TX_PKT_OFF;
+		dbg("send complete!%lx", g_tpdconsumerindex);
+		ndev->stats.tx_packets++;
+		netif_wake_queue(ndev);
+	}
+	if(IntStatus & ISR_RX0_PKT_OFF) {
+		receive(ndev);
+		REG32(pMacBase + REG_ISR) = ISR_RX0_PKT_OFF;
+	}
+	if(IntStatus & ISR_RXF_OV_OFF) {
+		panic("Liu Hejun, come to help me!\n");
+		receive(ndev);
+	}
+	if(IntStatus & ISR_DMAW_OFF)
+	{
+		printk("DMAW operation timeout");
+		init_hw(ndev);
+		netif_wake_queue(ndev);
+	}
+	if(IntStatus & ISR_DMAR_OFF)
+	{
+		printk("DMAR operation timeout");
+		init_hw(ndev);
+		netif_wake_queue(ndev);
+	}
+	if(IntStatus & ISR_TXQ_OFF)
+	{
+		printk("TXQ operation timeout");
+		init_hw(ndev);
+		netif_wake_queue(ndev);
+	}
+
+	open_2x();
+
+	spin_unlock_irqrestore(&db->lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ *Used by netconsole
+ */
+static void ak98_mac_poll_controller(struct net_device *ndev)
+{
+	disable_irq(ndev->irq);
+	ak98_mac_interrupt(ndev->irq, ndev);
+	enable_irq(ndev->irq);
+}
+#endif
+
+/*
+ *  Open the interface.
+ *  The interface is opened whenever "ifconfig" actives it.
+ */
+static int
+ak98_mac_open(struct net_device *ndev)
+{
+	mac_info_t *db = netdev_priv(ndev);
+	unsigned long status;
+
+	clk_enable(db->clk);
+
+	/* Initialize AK98 MAC */
+	if (MacInit(ndev) == false) {
+		printk("mac init fail\n");
+		return -ENOMEM;
+	} else
+		printk("mac init success!\n");
+
+	if (request_irq(ndev->irq, &ak98_mac_interrupt, 0, ndev->name, ndev))
+		return -EAGAIN;
+
+	disable_irq(ndev->irq);
+	status = MIIRead(MII_BMSR);
+	dbg("BMSR: 0x%lx", status);
+	if ((status & BMSR_LINK_STATUS) == 0)
+		netif_carrier_off(ndev);
+	else
+		netif_carrier_on(ndev);
+	enable_irq(ndev->irq);
+
+	netif_start_queue(ndev);
+	
+	return 0;
+}
+
+/*
+ * Stop the interface.
+ * The interface is stopped when it is brought.
+ */
+static int
+ak98_mac_stop(struct net_device *ndev)
+{
+	mac_info_t *db = netdev_priv(ndev);
+
+	netif_stop_queue(ndev);
+	netif_carrier_off(ndev);
+	
+	/* free interrupt */
+	free_irq(ndev->irq, ndev);
+	
+	close_2x();
+	MacRest();
+	MIIWrite(MII_BMCR, MIIRead(MII_BMCR) | 0x800);
+	open_2x();
+
+	clk_disable(db->clk);
+
+	return 0;
+}
+
+/* Get the current statistics.	This may be called with the card open or
+  closed. */
+static struct net_device_stats *
+ak98_mac_get_stats(struct net_device *ndev)
+{
+	//struct mac_info_t *db = netdev_priv(ndev);
+	//unsigned long flags;
+
+	//spin_lock_irqsave(&lp->lock, flags);
+	/* Update the statistics from the device registers. */
+	//db->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6);
+	//db->stats.collisions += (readreg(dev, PP_TxCol) >> 6);
+	//spin_unlock_irqrestore(&lp->lock, flags);
+
+	return &ndev->stats;
+}
+
+static const struct net_device_ops ak98_mac_netdev_ops = {
+	.ndo_open		= ak98_mac_open,
+	.ndo_stop		= ak98_mac_stop,
+	.ndo_start_xmit		= ak98_mac_start_xmit,
+	.ndo_tx_timeout		= ak98_mac_timeout,
+	.ndo_set_multicast_list	= ak98_mac_hash_table,
+	.ndo_change_mtu		= eth_change_mtu,
+	.ndo_validate_addr	= eth_validate_addr,
+	.ndo_set_mac_address	= set_mac_address,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+	.ndo_poll_controller	= ak98_mac_poll_controller,
+#endif
+	.ndo_get_stats		= ak98_mac_get_stats,
+};
+
+/*
+ * Search AK98 MAC, allocate space and register it
+ */
+static int __devinit
+ak98_mac_probe(struct platform_device *pdev)
+{
+	struct ak98_mac_data *pdata = pdev->dev.platform_data;
+	struct mac_info *db;	/* Point a board information structure */
+	struct net_device *ndev;
+	//volatile unsigned long count;
+
+	int ret = 0;
+	int iosize;
+	int i;
+
+	cpu_clk_2x_switch();
+
+	/* Init network device */
+	ndev = alloc_etherdev(sizeof(struct mac_info));
+	if (!ndev) {
+		dev_err(&pdev->dev, "could not allocate device.\n");
+		return -ENOMEM;
+	}
+
+	SET_NETDEV_DEV(ndev, &pdev->dev);
+
+	dev_dbg(&pdev->dev, "ak98_mac_probe()\n");
+
+	/* setup board info structure */
+	db = netdev_priv(ndev);
+
+	db->dev = &pdev->dev;
+	db->ndev = ndev;
+
+	db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	db->irq_res  = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+	if (db->addr_res == NULL || db->irq_res == NULL) {
+		dev_err(db->dev, "insufficient resources\n");
+		ret = -ENOENT;
+		goto out;
+	}
+
+	iosize = resource_size(db->addr_res);
+	db->addr_req = request_mem_region(db->addr_res->start, iosize,
+					  pdev->name);
+
+	if (db->addr_req == NULL) {
+		dev_err(db->dev, "cannot claim address reg area\n");
+		ret = -EIO;
+		goto out;
+	}
+
+	db->io_addr = ioremap(db->addr_res->start, iosize);
+
+	if (db->io_addr == NULL) {
+		dev_err(db->dev, "failed to ioremap address reg\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* get mac clock */
+	db->clk = clk_get(db->dev, "mac_clk");
+	if (IS_ERR(db->clk)) {
+		dbg("clocks missing");
+		ret = -ENODEV;
+		goto out;
+	}
+	spin_lock_init(&db->lock);
+
+	/* fill in parameters for net-dev structure */
+	ndev->base_addr = (unsigned long)db->io_addr;
+	ndev->irq	= db->irq_res->start;
+
+	/* driver system function */
+	ether_setup(ndev);
+
+	ndev->netdev_ops	= &ak98_mac_netdev_ops;
+	ndev->watchdog_timeo	= msecs_to_jiffies(5000);
+
+	memcpy(ndev->dev_addr, pdata->dev_addr, 6);
+
+	if (!is_valid_ether_addr(ndev->dev_addr)) {
+		/* try reading from mac */
+		
+		for (i = 0; i < 6; i++)
+			ndev->dev_addr[i] = 'A' + i;
+	}
+
+	if (!is_valid_ether_addr(ndev->dev_addr))
+		dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
+			 "set using ifconfig\n", ndev->name);
+
+	pMacBase = db->io_addr;
+
+	psysbase = AK98_VA_SYSCTRL; 
+	if(psysbase == NULL)
+	{
+		dbg("sysbase alloc error!");
+	}
+
+	// initial share pin
+	ak98_group_config(ePIN_AS_MAC);
+	
+	ak98_setpin_as_gpio(AK98_GPIO_98);
+	ak98_gpio_pullup(AK98_GPIO_98, AK98_PULLDOWN_DISABLE);
+	ak98_gpio_cfgpin(AK98_GPIO_98, AK98_GPIO_DIR_INPUT);
+	
+	platform_set_drvdata(pdev, ndev);
+	ret = register_netdev(ndev);
+
+	if (ret == 0)
+		printk(KERN_INFO "%s: ak98_mac at %p IRQ %d MAC: %pM\n",
+		       ndev->name, db->io_addr, ndev->irq, ndev->dev_addr);
+
+	return 0;
+out:
+	dev_err(db->dev, "not found (%d).\n", ret);
+
+	ak98_mac_release_board(pdev, db);
+	free_netdev(ndev);
+
+	return ret;
+}
+
+static int
+ak98_mac_drv_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	mac_info_t *db = netdev_priv(ndev);
+
+	if (ndev) {
+		db = netdev_priv(ndev);
+		db->in_suspend = 1;
+
+		if (netif_running(ndev)) {
+			netif_device_detach(ndev);
+
+			close_2x();
+			MacRest();
+			MIIWrite(MII_BMCR, MIIRead(MII_BMCR) | 0x800);
+			//MIIWrite(0x29, MIIRead(0x29) | 0x8000);
+			open_2x();
+			
+			clk_disable(db->clk);
+		}
+	}
+	return 0;
+}
+
+static int
+ak98_mac_drv_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	mac_info_t *db = netdev_priv(ndev);
+	unsigned long status;
+
+	if (ndev) {
+		if (netif_running(ndev)) {	
+			clk_enable(db->clk);
+
+			/* Initialize AK98 MAC */
+			if (MacInit(ndev) == false) {
+				printk("mac init fail\n");
+				return -ENOMEM;
+			} else
+				printk("mac init success!\n");
+			
+			disable_irq(ndev->irq);
+			status = MIIRead(MII_BMSR);
+			dbg("BMSR: 0x%lx", status);
+			if ((status & BMSR_LINK_STATUS) == 0)
+				netif_carrier_off(ndev);
+			else
+				netif_carrier_on(ndev);
+			enable_irq(ndev->irq);
+			
+			netif_device_attach(ndev);
+		}
+	}
+	return 0;
+}
+
+static struct dev_pm_ops ak98_mac_drv_pm_ops = {
+	.suspend	= ak98_mac_drv_suspend,
+	.resume		= ak98_mac_drv_resume,
+};
+
+static int __devexit
+ak98_mac_drv_remove(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+
+	platform_set_drvdata(pdev, NULL);
+
+	unregister_netdev(ndev);
+	ak98_mac_release_board(pdev, (mac_info_t *) netdev_priv(ndev));
+	Macexit(ndev);
+	free_netdev(ndev);		/* free device structure */
+
+	dev_dbg(&pdev->dev, "released and freed device\n");
+	return 0;
+}
+
+static struct platform_driver ak98_mac_driver = {
+	.driver	= {
+		.name    = "ak98_mac",
+		.owner	 = THIS_MODULE,
+		.pm	 = &ak98_mac_drv_pm_ops,
+	},
+	.probe   = ak98_mac_probe,
+	.remove  = __devexit_p(ak98_mac_drv_remove),
+};
+
+static int __init
+ak98_mac_init(void)
+{
+	printk(KERN_INFO "%s Ethernet Driver, V%s\n", MACNAME, DRV_VERSION);
+
+	return platform_driver_register(&ak98_mac_driver);
+}
+
+static void __exit
+ak98_mac_cleanup(void)
+{
+	platform_driver_unregister(&ak98_mac_driver);
+}
+
+module_init(ak98_mac_init);
+module_exit(ak98_mac_cleanup);
+
+MODULE_AUTHOR("Tang Anyang, Zhang Jingyuan (C) ANYKA");
+MODULE_DESCRIPTION("AK98 MAC driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak98_mac");
diff --git a/drivers/net/ak98-mac/eth_ops.h b/drivers/net/ak98-mac/eth_ops.h
new file mode 100644
index 00000000000..2d6b00affad
--- /dev/null
+++ b/drivers/net/ak98-mac/eth_ops.h
@@ -0,0 +1,8 @@
+#ifndef _ETHERNET_OPERATION_H_
+#define _ETHERNET_OPERATION_H_
+
+#define FLAG(_off)				((unsigned int)1 << (_off))
+#define BIT_SET(_val, _off)		( (_val) |= FLAG(_off) )
+#define BIT_CLEAR(_val, _off)	( (_val) &= ~FLAG(_off) )
+#define BIT_TEST(_val, _off)	(0 != ( (_val) & FLAG(_off) ) ) 
+#endif
diff --git a/drivers/net/ak98-mac/phyhw.h b/drivers/net/ak98-mac/phyhw.h
new file mode 100755
index 00000000000..a4caf42c337
--- /dev/null
+++ b/drivers/net/ak98-mac/phyhw.h
@@ -0,0 +1,140 @@
+#ifndef _ANYKA_PHY_REG_H_

+#define _ANYKA_PHY_REG_H_

+/********************* PHY regs definition ***************************/

+#define LC_10H      0x01

+#define LC_10F      0x02

+#define LC_100H     0x04

+#define LC_100F     0x08

+#define LC_1000F    0x10

+#define LC_ALL     (LC_10H|LC_10F|LC_100H|LC_100F|LC_1000F)

+

+/* PHY Control Register */

+#define MII_BMCR                                0x00

+    #define BMCR_SPEED_SELECT_MSB               0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */

+    #define BMCR_COLL_TEST_ENABLE               0x0080  /* Collision test enable */

+    #define BMCR_FULL_DUPLEX                    0x0100  /* FDX =1, half duplex =0 */

+    #define BMCR_RESTART_AUTO_NEG               0x0200  /* Restart auto negotiation */

+    #define BMCR_ISOLATE                        0x0400  /* Isolate PHY from MII */

+    #define BMCR_POWER_DOWN                     0x0800  /* Power down */

+    #define BMCR_AUTO_NEG_EN                    0x1000  /* Auto Neg Enable */

+    #define BMCR_SPEED_SELECT_LSB               0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */

+    #define BMCR_LOOPBACK                       0x4000  /* 0 = normal, 1 = loopback */

+    #define BMCR_RESET                          0x8000  /* 0 = normal, 1 = PHY reset */

+    #define BMCR_SPEED_MASK                     0x2040

+    #define BMCR_SPEED_1000                     0x0040

+    #define BMCR_SPEED_100                      0x2000

+    #define BMCR_SPEED_10                       0x0000

+

+/* PHY Status Register */    

+#define MII_BMSR                                0x01 

+    #define BMMSR_EXTENDED_CAPS                 0x0001  /* Extended register capabilities */

+    #define BMSR_JABBER_DETECT                  0x0002  /* Jabber Detected */

+    #define BMSR_LINK_STATUS                    0x0004  /* Link Status 1 = link */

+    #define BMSR_AUTONEG_CAPS                   0x0008  /* Auto Neg Capable */

+    #define BMSR_REMOTE_FAULT                   0x0010  /* Remote Fault Detect */

+    #define BMSR_AUTONEG_COMPLETE               0x0020  /* Auto Neg Complete */

+    #define BMSR_PREAMBLE_SUPPRESS              0x0040  /* Preamble may be suppressed */

+    #define BMSR_EXTENDED_STATUS                0x0100  /* Ext. status info in Reg 0x0F */

+    #define BMSR_100T2_HD_CAPS                  0x0200  /* 100T2 Half Duplex Capable */

+    #define BMSR_100T2_FD_CAPS                  0x0400  /* 100T2 Full Duplex Capable */

+    #define BMSR_10T_HD_CAPS                    0x0800  /* 10T   Half Duplex Capable */

+    #define BMSR_10T_FD_CAPS                    0x1000  /* 10T   Full Duplex Capable */

+    #define BMSR_100X_HD_CAPS                   0x2000  /* 100X  Half Duplex Capable */

+    #define BMMII_SR_100X_FD_CAPS               0x4000  /* 100X  Full Duplex Capable */

+    #define BMMII_SR_100T4_CAPS                 0x8000  /* 100T4 Capable */

+

+#define MII_PHYSID1                             0x02     

+#define MII_PHYSID2                             0x03  

+#define L1D_MPW_PHYID1                          0xD01C  /* V7 */

+#define L1D_MPW_PHYID2                          0xD01D  /* V1-V6 */

+#define L1D_MPW_PHYID3                          0xD01E  /* V8 */

+ 

+

+/* Autoneg Advertisement Register */

+#define MII_ADVERTISE                           0x04

+    #define ADVERTISE_SELECTOR_FIELD            0x0001  /* indicates IEEE 802.3 CSMA/CD */

+    #define ADVERTISE_10T_HD_CAPS               0x0020  /* 10T   Half Duplex Capable */

+    #define ADVERTISE_10T_FD_CAPS               0x0040  /* 10T   Full Duplex Capable */

+    #define ADVERTISE_100TX_HD_CAPS             0x0080  /* 100TX Half Duplex Capable */

+    #define ADVERTISE_100TX_FD_CAPS             0x0100  /* 100TX Full Duplex Capable */

+    #define ADVERTISE_100T4_CAPS                0x0200  /* 100T4 Capable */

+    #define ADVERTISE_PAUSE                     0x0400  /* Pause operation desired */

+    #define ADVERTISE_ASM_DIR                   0x0800  /* Asymmetric Pause Direction bit */

+    #define ADVERTISE_REMOTE_FAULT              0x2000  /* Remote Fault detected */

+    #define ADVERTISE_NEXT_PAGE                 0x8000  /* Next Page ability supported */

+    #define ADVERTISE_SPEED_MASK                0x01E0

+    #define ADVERTISE_DEFAULT_CAP               0x0DE0

+

+/* Link partner ability register */   

+#define MII_LPA                                 0x05 

+    #define LPA_SLCT                            0x001   /* Same as advertise selector  */

+    #define LPA_10HALF                          0x002   /* Can do 10mbps half-duplex   */

+    #define LPA_10FULL                          0x0040  /* Can do 10mbps full-duplex   */

+    #define LPA_100HALF                         0x0080  /* Can do 100mbps half-duplex  */

+    #define LPA_100FULL                         0x0100  /* Can do 100mbps full-duplex  */

+    #define LPA_100BASE4                        0x0200  /* 100BASE-T4  */

+    #define LPA_PAUSE                           0x0400  /* PAUSE */

+    #define LPA_ASYPAUSE                        0x0800  /* Asymmetrical PAUSE */

+    #define LPA_RFAULT                          0x2000  /* Link partner faulted        */

+    #define LPA_LPACK                           0x4000  /* Link partner acked us       */

+    #define LPA_NPAGE                           0x8000  /* Next page bit               */

+

+/* 1000BASE-T Control Register */      

+#define MII_GIGA_CR                             0x09   

+    #define GIGA_CR_1000T_HD_CAPS               0x0100  /* Advertise 1000T HD capability */

+    #define GIGA_CR_1000T_FD_CAPS               0x0200  /* Advertise 1000T FD capability  */

+    #define GIGA_CR_1000T_REPEATER_DTE          0x0400  /* 1=Repeater/switch device port */

+                            /* 0=DTE device */

+    #define GIGA_CR_1000T_MS_VALUE              0x0800  /* 1=Configure PHY as Master */

+                            /* 0=Configure PHY as Slave */

+    #define GIGA_CR_1000T_MS_ENABLE             0x1000  /* 1=Master/Slave manual config value */

+                            /* 0=Automatic Master/Slave config */

+    #define GIGA_CR_1000T_TEST_MODE_NORMAL      0x0000  /* Normal Operation */

+    #define GIGA_CR_1000T_TEST_MODE_1           0x2000  /* Transmit Waveform test */

+    #define GIGA_CR_1000T_TEST_MODE_2           0x4000  /* Master Transmit Jitter test */

+    #define GIGA_CR_1000T_TEST_MODE_3           0x6000  /* Slave Transmit Jitter test */

+    #define GIGA_CR_1000T_TEST_MODE_4           0x8000  /* Transmitter Distortion test */

+    #define GIGA_CR_1000T_SPEED_MASK            0x0300

+    #define GIGA_CR_1000T_DEFAULT_CAP           0x0300

+

+/* 1000BASE-T Status Register */      

+#define MII_GIGA_SR                             0x0A   

+

+/* PHY Specific Status Register */

+#define MII_GIGA_PSSR                           0x11    

+    #define GIGA_PSSR_SPD_DPLX_RESOLVED         0x0800  /* 1=Speed & Duplex resolved */

+    #define GIGA_PSSR_DPLX                      0x2000  /* 1=Duplex 0=Half Duplex */

+    #define GIGA_PSSR_SPEED                     0xC000  /* Speed, bits 14:15 */

+    #define GIGA_PSSR_10MBS                     0x0000  /* 00=10Mbs */

+    #define GIGA_PSSR_100MBS                    0x4000  /* 01=100Mbs */

+    #define GIGA_PSSR_1000MBS                   0x8000  /* 10=1000Mbs */

+    

+/* PHY Interrupt Enable Register */

+#define MII_IER                                 0x12

+    #define IER_LINK_UP                         0x0400    

+    #define IER_LINK_DOWN                       0x0800

+    

+/* PHY Interrupt Status Register */

+#define MII_ISR                                 0x13

+    #define ISR_LINK_UP                         0x0400

+    #define ISR_LINK_DOWN                       0x0800  

+

+/* Cable-Detect-Test Control Register */

+#define MII_CDTC                                0x16

+    #define CDTC_EN                             1   /* sc */

+    #define CDTC_PAIR_OFFSET                    8

+    #define CDTC_PAIR_MASK                      3

+

+

+/* Cable-Detect-Test Status Register */    

+#define MII_CDTS                                0x1C 

+    #define CDTS_STATUS_OFFSET                  8

+    #define CDTS_STATUS_MASK                    3

+    #define CDTS_STATUS_NORMAL                  0 

+    #define CDTS_STATUS_SHORT                   1

+    #define CDTS_STATUS_OPEN                    2

+    #define CDTS_STATUS_INVALID                 3

+    

+#define MII_DBG_ADDR                            0x1D

+#define MII_DBG_DATA                            0x1E

+#endif
\ No newline at end of file
diff --git a/drivers/net/pppolac.c b/drivers/net/pppolac.c
new file mode 100644
index 00000000000..af3202a920a
--- /dev/null
+++ b/drivers/net/pppolac.c
@@ -0,0 +1,380 @@
+/* drivers/net/pppolac.c
+ *
+ * Driver for PPP on L2TP Access Concentrator / PPPoLAC Socket (RFC 2661)
+ *
+ * Copyright (C) 2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This driver handles L2TP data packets between a UDP socket and a PPP channel.
+ * To keep things simple, only one session per socket is permitted. Packets are
+ * sent via the socket, so it must keep connected to the same address. One must
+ * not set sequencing in ICCN but let LNS controll it. Currently this driver
+ * only works on IPv4 due to the lack of UDP encapsulation support in IPv6. */
+
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/file.h>
+#include <linux/netdevice.h>
+#include <linux/net.h>
+#include <linux/udp.h>
+#include <linux/ppp_defs.h>
+#include <linux/if_ppp.h>
+#include <linux/if_pppox.h>
+#include <linux/ppp_channel.h>
+#include <net/tcp_states.h>
+#include <asm/uaccess.h>
+
+#define L2TP_CONTROL_BIT	0x80
+#define L2TP_LENGTH_BIT		0x40
+#define L2TP_SEQUENCE_BIT	0x08
+#define L2TP_OFFSET_BIT		0x02
+#define L2TP_VERSION		0x02
+#define L2TP_VERSION_MASK	0x0F
+
+#define PPP_ADDR	0xFF
+#define PPP_CTRL	0x03
+
+union unaligned {
+	__u32 u32;
+} __attribute__((packed));
+
+static inline union unaligned *unaligned(void *ptr)
+{
+	return (union unaligned *)ptr;
+}
+
+static int pppolac_recv_core(struct sock *sk_udp, struct sk_buff *skb)
+{
+	struct sock *sk = (struct sock *)sk_udp->sk_user_data;
+	struct pppolac_opt *opt = &pppox_sk(sk)->proto.lac;
+	__u8 bits;
+	__u8 *ptr;
+
+	/* Drop the packet if it is too short. */
+	if (skb->len < sizeof(struct udphdr) + 6)
+		goto drop;
+
+	/* Put it back if it is a control packet. */
+	if (skb->data[sizeof(struct udphdr)] & L2TP_CONTROL_BIT)
+		return opt->backlog_rcv(sk_udp, skb);
+
+	/* Skip UDP header. */
+	skb_pull(skb, sizeof(struct udphdr));
+
+	/* Check the version. */
+	if ((skb->data[1] & L2TP_VERSION_MASK) != L2TP_VERSION)
+		goto drop;
+	bits = skb->data[0];
+	ptr = &skb->data[2];
+
+	/* Check the length if it is present. */
+	if (bits & L2TP_LENGTH_BIT) {
+		if ((ptr[0] << 8 | ptr[1]) != skb->len)
+			goto drop;
+		ptr += 2;
+	}
+
+	/* Skip all fields including optional ones. */
+	if (!skb_pull(skb, 6 + (bits & L2TP_SEQUENCE_BIT ? 4 : 0) +
+			(bits & L2TP_LENGTH_BIT ? 2 : 0) +
+			(bits & L2TP_OFFSET_BIT ? 2 : 0)))
+		goto drop;
+
+	/* Skip the offset padding if it is present. */
+	if (bits & L2TP_OFFSET_BIT &&
+			!skb_pull(skb, skb->data[-2] << 8 | skb->data[-1]))
+		goto drop;
+
+	/* Check the tunnel and the session. */
+	if (unaligned(ptr)->u32 != opt->local)
+		goto drop;
+
+	/* Check the sequence if it is present. According to RFC 2661 section
+	 * 5.4, the only thing to do is to update opt->sequencing. */
+	opt->sequencing = bits & L2TP_SEQUENCE_BIT;
+
+	/* Skip PPP address and control if they are present. */
+	if (skb->len >= 2 && skb->data[0] == PPP_ADDR &&
+			skb->data[1] == PPP_CTRL)
+		skb_pull(skb, 2);
+
+	/* Fix PPP protocol if it is compressed. */
+	if (skb->len >= 1 && skb->data[0] & 1)
+		skb_push(skb, 1)[0] = 0;
+
+	/* Finally, deliver the packet to PPP channel. */
+	skb_orphan(skb);
+	ppp_input(&pppox_sk(sk)->chan, skb);
+	return NET_RX_SUCCESS;
+drop:
+	kfree_skb(skb);
+	return NET_RX_DROP;
+}
+
+static int pppolac_recv(struct sock *sk_udp, struct sk_buff *skb)
+{
+	sock_hold(sk_udp);
+	sk_receive_skb(sk_udp, skb, 0);
+	return 0;
+}
+
+static struct sk_buff_head delivery_queue;
+
+static void pppolac_xmit_core(struct work_struct *delivery_work)
+{
+	mm_segment_t old_fs = get_fs();
+	struct sk_buff *skb;
+
+	set_fs(KERNEL_DS);
+	while ((skb = skb_dequeue(&delivery_queue))) {
+		struct sock *sk_udp = skb->sk;
+		struct kvec iov = {.iov_base = skb->data, .iov_len = skb->len};
+		struct msghdr msg = {
+			.msg_iov = (struct iovec *)&iov,
+			.msg_iovlen = 1,
+			.msg_flags = MSG_NOSIGNAL | MSG_DONTWAIT,
+		};
+		sk_udp->sk_prot->sendmsg(NULL, sk_udp, &msg, skb->len);
+		kfree_skb(skb);
+	}
+	set_fs(old_fs);
+}
+
+static DECLARE_WORK(delivery_work, pppolac_xmit_core);
+
+static int pppolac_xmit(struct ppp_channel *chan, struct sk_buff *skb)
+{
+	struct sock *sk_udp = (struct sock *)chan->private;
+	struct pppolac_opt *opt = &pppox_sk(sk_udp->sk_user_data)->proto.lac;
+
+	/* Install PPP address and control. */
+	skb_push(skb, 2);
+	skb->data[0] = PPP_ADDR;
+	skb->data[1] = PPP_CTRL;
+
+	/* Install L2TP header. */
+	if (opt->sequencing) {
+		skb_push(skb, 10);
+		skb->data[0] = L2TP_SEQUENCE_BIT;
+		skb->data[6] = opt->sequence >> 8;
+		skb->data[7] = opt->sequence;
+		skb->data[8] = 0;
+		skb->data[9] = 0;
+		opt->sequence++;
+	} else {
+		skb_push(skb, 6);
+		skb->data[0] = 0;
+	}
+	skb->data[1] = L2TP_VERSION;
+	unaligned(&skb->data[2])->u32 = opt->remote;
+
+	/* Now send the packet via the delivery queue. */
+	skb_set_owner_w(skb, sk_udp);
+	skb_queue_tail(&delivery_queue, skb);
+	schedule_work(&delivery_work);
+	return 1;
+}
+
+/******************************************************************************/
+
+static struct ppp_channel_ops pppolac_channel_ops = {
+	.start_xmit = pppolac_xmit,
+};
+
+static int pppolac_connect(struct socket *sock, struct sockaddr *useraddr,
+	int addrlen, int flags)
+{
+	struct sock *sk = sock->sk;
+	struct pppox_sock *po = pppox_sk(sk);
+	struct sockaddr_pppolac *addr = (struct sockaddr_pppolac *)useraddr;
+	struct socket *sock_udp = NULL;
+	struct sock *sk_udp;
+	int error;
+
+	if (addrlen != sizeof(struct sockaddr_pppolac) ||
+			!addr->local.tunnel || !addr->local.session ||
+			!addr->remote.tunnel || !addr->remote.session) {
+		return -EINVAL;
+	}
+
+	lock_sock(sk);
+	error = -EALREADY;
+	if (sk->sk_state != PPPOX_NONE)
+		goto out;
+
+	sock_udp = sockfd_lookup(addr->udp_socket, &error);
+	if (!sock_udp)
+		goto out;
+	sk_udp = sock_udp->sk;
+	lock_sock(sk_udp);
+
+	/* Remove this check when IPv6 supports UDP encapsulation. */
+	error = -EAFNOSUPPORT;
+	if (sk_udp->sk_family != AF_INET)
+		goto out;
+	error = -EPROTONOSUPPORT;
+	if (sk_udp->sk_protocol != IPPROTO_UDP)
+		goto out;
+	error = -EDESTADDRREQ;
+	if (sk_udp->sk_state != TCP_ESTABLISHED)
+		goto out;
+	error = -EBUSY;
+	if (udp_sk(sk_udp)->encap_type || sk_udp->sk_user_data)
+		goto out;
+	if (!sk_udp->sk_bound_dev_if) {
+		struct dst_entry *dst = sk_dst_get(sk_udp);
+		error = -ENODEV;
+		if (!dst)
+			goto out;
+		sk_udp->sk_bound_dev_if = dst->dev->ifindex;
+		dst_release(dst);
+	}
+
+	po->chan.hdrlen = 12;
+	po->chan.private = sk_udp;
+	po->chan.ops = &pppolac_channel_ops;
+	po->chan.mtu = PPP_MTU - 80;
+	po->proto.lac.local = unaligned(&addr->local)->u32;
+	po->proto.lac.remote = unaligned(&addr->remote)->u32;
+	po->proto.lac.backlog_rcv = sk_udp->sk_backlog_rcv;
+
+	error = ppp_register_channel(&po->chan);
+	if (error)
+		goto out;
+
+	sk->sk_state = PPPOX_CONNECTED;
+	udp_sk(sk_udp)->encap_type = UDP_ENCAP_L2TPINUDP;
+	udp_sk(sk_udp)->encap_rcv = pppolac_recv;
+	sk_udp->sk_backlog_rcv = pppolac_recv_core;
+	sk_udp->sk_user_data = sk;
+out:
+	if (sock_udp) {
+		release_sock(sk_udp);
+		if (error)
+			sockfd_put(sock_udp);
+	}
+	release_sock(sk);
+	return error;
+}
+
+static int pppolac_release(struct socket *sock)
+{
+	struct sock *sk = sock->sk;
+
+	if (!sk)
+		return 0;
+
+	lock_sock(sk);
+	if (sock_flag(sk, SOCK_DEAD)) {
+		release_sock(sk);
+		return -EBADF;
+	}
+
+	if (sk->sk_state != PPPOX_NONE) {
+		struct sock *sk_udp = (struct sock *)pppox_sk(sk)->chan.private;
+		lock_sock(sk_udp);
+		pppox_unbind_sock(sk);
+		udp_sk(sk_udp)->encap_type = 0;
+		udp_sk(sk_udp)->encap_rcv = NULL;
+		sk_udp->sk_backlog_rcv = pppox_sk(sk)->proto.lac.backlog_rcv;
+		sk_udp->sk_user_data = NULL;
+		release_sock(sk_udp);
+		sockfd_put(sk_udp->sk_socket);
+	}
+
+	sock_orphan(sk);
+	sock->sk = NULL;
+	release_sock(sk);
+	sock_put(sk);
+	return 0;
+}
+
+/******************************************************************************/
+
+static struct proto pppolac_proto = {
+	.name = "PPPOLAC",
+	.owner = THIS_MODULE,
+	.obj_size = sizeof(struct pppox_sock),
+};
+
+static struct proto_ops pppolac_proto_ops = {
+	.family = PF_PPPOX,
+	.owner = THIS_MODULE,
+	.release = pppolac_release,
+	.bind = sock_no_bind,
+	.connect = pppolac_connect,
+	.socketpair = sock_no_socketpair,
+	.accept = sock_no_accept,
+	.getname = sock_no_getname,
+	.poll = sock_no_poll,
+	.ioctl = pppox_ioctl,
+	.listen = sock_no_listen,
+	.shutdown = sock_no_shutdown,
+	.setsockopt = sock_no_setsockopt,
+	.getsockopt = sock_no_getsockopt,
+	.sendmsg = sock_no_sendmsg,
+	.recvmsg = sock_no_recvmsg,
+	.mmap = sock_no_mmap,
+};
+
+static int pppolac_create(struct net *net, struct socket *sock)
+{
+	struct sock *sk;
+
+	sk = sk_alloc(net, PF_PPPOX, GFP_KERNEL, &pppolac_proto);
+	if (!sk)
+		return -ENOMEM;
+
+	sock_init_data(sock, sk);
+	sock->state = SS_UNCONNECTED;
+	sock->ops = &pppolac_proto_ops;
+	sk->sk_protocol = PX_PROTO_OLAC;
+	sk->sk_state = PPPOX_NONE;
+	return 0;
+}
+
+/******************************************************************************/
+
+static struct pppox_proto pppolac_pppox_proto = {
+	.create = pppolac_create,
+	.owner = THIS_MODULE,
+};
+
+static int __init pppolac_init(void)
+{
+	int error;
+
+	error = proto_register(&pppolac_proto, 0);
+	if (error)
+		return error;
+
+	error = register_pppox_proto(PX_PROTO_OLAC, &pppolac_pppox_proto);
+	if (error)
+		proto_unregister(&pppolac_proto);
+	else
+		skb_queue_head_init(&delivery_queue);
+	return error;
+}
+
+static void __exit pppolac_exit(void)
+{
+	unregister_pppox_proto(PX_PROTO_OLAC);
+	proto_unregister(&pppolac_proto);
+}
+
+module_init(pppolac_init);
+module_exit(pppolac_exit);
+
+MODULE_DESCRIPTION("PPP on L2TP Access Concentrator (PPPoLAC)");
+MODULE_AUTHOR("Chia-chi Yeh <chiachi@android.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/pppopns.c b/drivers/net/pppopns.c
new file mode 100644
index 00000000000..298097127c9
--- /dev/null
+++ b/drivers/net/pppopns.c
@@ -0,0 +1,357 @@
+/* drivers/net/pppopns.c
+ *
+ * Driver for PPP on PPTP Network Server / PPPoPNS Socket (RFC 2637)
+ *
+ * Copyright (C) 2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This driver handles PPTP data packets between a RAW socket and a PPP channel.
+ * The socket is created in the kernel space and connected to the same address
+ * of the control socket. To keep things simple, packets are always sent with
+ * sequence but without acknowledgement. This driver should work on both IPv4
+ * and IPv6. */
+
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/file.h>
+#include <linux/netdevice.h>
+#include <linux/net.h>
+#include <linux/ppp_defs.h>
+#include <linux/if.h>
+#include <linux/if_ppp.h>
+#include <linux/if_pppox.h>
+#include <linux/ppp_channel.h>
+#include <asm/uaccess.h>
+
+#define GRE_HEADER_SIZE		8
+
+#define PPTP_GRE_BITS		htons(0x2001)
+#define PPTP_GRE_BITS_MASK	htons(0xEF7F)
+#define PPTP_GRE_SEQ_BIT	htons(0x1000)
+#define PPTP_GRE_ACK_BIT	htons(0x0080)
+#define PPTP_GRE_TYPE		htons(0x880B)
+
+#define PPP_ADDR	0xFF
+#define PPP_CTRL	0x03
+
+struct header {
+	__u16	bits;
+	__u16	type;
+	__u16	length;
+	__u16	call;
+	__u32	sequence;
+} __attribute__((packed));
+
+static int pppopns_recv_core(struct sock *sk_raw, struct sk_buff *skb)
+{
+	struct sock *sk = (struct sock *)sk_raw->sk_user_data;
+	struct pppopns_opt *opt = &pppox_sk(sk)->proto.pns;
+	struct header *hdr;
+
+	/* Skip transport header */
+	skb_pull(skb, skb_transport_header(skb) - skb->data);
+
+	/* Drop the packet if it is too short. */
+	if (skb->len < GRE_HEADER_SIZE)
+		goto drop;
+
+	/* Check the header. */
+	hdr = (struct header *)skb->data;
+	if (hdr->type != PPTP_GRE_TYPE || hdr->call != opt->local ||
+			(hdr->bits & PPTP_GRE_BITS_MASK) != PPTP_GRE_BITS)
+		goto drop;
+
+	/* Skip all fields including optional ones. */
+	if (!skb_pull(skb, GRE_HEADER_SIZE +
+			(hdr->bits & PPTP_GRE_SEQ_BIT ? 4 : 0) +
+			(hdr->bits & PPTP_GRE_ACK_BIT ? 4 : 0)))
+		goto drop;
+
+	/* Check the length. */
+	if (skb->len != ntohs(hdr->length))
+		goto drop;
+
+	/* Skip PPP address and control if they are present. */
+	if (skb->len >= 2 && skb->data[0] == PPP_ADDR &&
+			skb->data[1] == PPP_CTRL)
+		skb_pull(skb, 2);
+
+	/* Fix PPP protocol if it is compressed. */
+	if (skb->len >= 1 && skb->data[0] & 1)
+		skb_push(skb, 1)[0] = 0;
+
+	/* Finally, deliver the packet to PPP channel. */
+	skb_orphan(skb);
+	ppp_input(&pppox_sk(sk)->chan, skb);
+	return NET_RX_SUCCESS;
+drop:
+	kfree_skb(skb);
+	return NET_RX_DROP;
+}
+
+static void pppopns_recv(struct sock *sk_raw, int length)
+{
+	struct sk_buff *skb;
+	while ((skb = skb_dequeue(&sk_raw->sk_receive_queue))) {
+		sock_hold(sk_raw);
+		sk_receive_skb(sk_raw, skb, 0);
+	}
+}
+
+static struct sk_buff_head delivery_queue;
+
+static void pppopns_xmit_core(struct work_struct *delivery_work)
+{
+	mm_segment_t old_fs = get_fs();
+	struct sk_buff *skb;
+
+	set_fs(KERNEL_DS);
+	while ((skb = skb_dequeue(&delivery_queue))) {
+		struct sock *sk_raw = skb->sk;
+		struct kvec iov = {.iov_base = skb->data, .iov_len = skb->len};
+		struct msghdr msg = {
+			.msg_iov = (struct iovec *)&iov,
+			.msg_iovlen = 1,
+			.msg_flags = MSG_NOSIGNAL | MSG_DONTWAIT,
+		};
+		sk_raw->sk_prot->sendmsg(NULL, sk_raw, &msg, skb->len);
+		kfree_skb(skb);
+	}
+	set_fs(old_fs);
+}
+
+static DECLARE_WORK(delivery_work, pppopns_xmit_core);
+
+static int pppopns_xmit(struct ppp_channel *chan, struct sk_buff *skb)
+{
+	struct sock *sk_raw = (struct sock *)chan->private;
+	struct pppopns_opt *opt = &pppox_sk(sk_raw->sk_user_data)->proto.pns;
+	struct header *hdr;
+	__u16 length;
+
+	/* Install PPP address and control. */
+	skb_push(skb, 2);
+	skb->data[0] = PPP_ADDR;
+	skb->data[1] = PPP_CTRL;
+	length = skb->len;
+
+	/* Install PPTP GRE header. */
+	hdr = (struct header *)skb_push(skb, 12);
+	hdr->bits = PPTP_GRE_BITS | PPTP_GRE_SEQ_BIT;
+	hdr->type = PPTP_GRE_TYPE;
+	hdr->length = htons(length);
+	hdr->call = opt->remote;
+	hdr->sequence = htonl(opt->sequence);
+	opt->sequence++;
+
+	/* Now send the packet via the delivery queue. */
+	skb_set_owner_w(skb, sk_raw);
+	skb_queue_tail(&delivery_queue, skb);
+	schedule_work(&delivery_work);
+	return 1;
+}
+
+/******************************************************************************/
+
+static struct ppp_channel_ops pppopns_channel_ops = {
+	.start_xmit = pppopns_xmit,
+};
+
+static int pppopns_connect(struct socket *sock, struct sockaddr *useraddr,
+	int addrlen, int flags)
+{
+	struct sock *sk = sock->sk;
+	struct pppox_sock *po = pppox_sk(sk);
+	struct sockaddr_pppopns *addr = (struct sockaddr_pppopns *)useraddr;
+	struct sockaddr_storage ss;
+	struct socket *sock_tcp = NULL;
+	struct socket *sock_raw = NULL;
+	struct sock *sk_tcp;
+	struct sock *sk_raw;
+	int error;
+
+	if (addrlen != sizeof(struct sockaddr_pppopns))
+		return -EINVAL;
+
+	lock_sock(sk);
+	error = -EALREADY;
+	if (sk->sk_state != PPPOX_NONE)
+		goto out;
+
+	sock_tcp = sockfd_lookup(addr->tcp_socket, &error);
+	if (!sock_tcp)
+		goto out;
+	sk_tcp = sock_tcp->sk;
+	error = -EPROTONOSUPPORT;
+	if (sk_tcp->sk_protocol != IPPROTO_TCP)
+		goto out;
+	addrlen = sizeof(struct sockaddr_storage);
+	error = kernel_getpeername(sock_tcp, (struct sockaddr *)&ss, &addrlen);
+	if (error)
+		goto out;
+	if (!sk_tcp->sk_bound_dev_if) {
+		struct dst_entry *dst = sk_dst_get(sk_tcp);
+		error = -ENODEV;
+		if (!dst)
+			goto out;
+		sk_tcp->sk_bound_dev_if = dst->dev->ifindex;
+		dst_release(dst);
+	}
+
+	error = sock_create(ss.ss_family, SOCK_RAW, IPPROTO_GRE, &sock_raw);
+	if (error)
+		goto out;
+	sk_raw = sock_raw->sk;
+	sk_raw->sk_bound_dev_if = sk_tcp->sk_bound_dev_if;
+	error = kernel_connect(sock_raw, (struct sockaddr *)&ss, addrlen, 0);
+	if (error)
+		goto out;
+
+	po->chan.hdrlen = 14;
+	po->chan.private = sk_raw;
+	po->chan.ops = &pppopns_channel_ops;
+	po->chan.mtu = PPP_MTU - 80;
+	po->proto.pns.local = addr->local;
+	po->proto.pns.remote = addr->remote;
+	po->proto.pns.data_ready = sk_raw->sk_data_ready;
+	po->proto.pns.backlog_rcv = sk_raw->sk_backlog_rcv;
+
+	error = ppp_register_channel(&po->chan);
+	if (error)
+		goto out;
+
+	sk->sk_state = PPPOX_CONNECTED;
+	lock_sock(sk_raw);
+	sk_raw->sk_data_ready = pppopns_recv;
+	sk_raw->sk_backlog_rcv = pppopns_recv_core;
+	sk_raw->sk_user_data = sk;
+	release_sock(sk_raw);
+out:
+	if (sock_tcp)
+		sockfd_put(sock_tcp);
+	if (error && sock_raw)
+		sock_release(sock_raw);
+	release_sock(sk);
+	return error;
+}
+
+static int pppopns_release(struct socket *sock)
+{
+	struct sock *sk = sock->sk;
+
+	if (!sk)
+		return 0;
+
+	lock_sock(sk);
+	if (sock_flag(sk, SOCK_DEAD)) {
+		release_sock(sk);
+		return -EBADF;
+	}
+
+	if (sk->sk_state != PPPOX_NONE) {
+		struct sock *sk_raw = (struct sock *)pppox_sk(sk)->chan.private;
+		lock_sock(sk_raw);
+		pppox_unbind_sock(sk);
+		sk_raw->sk_data_ready = pppox_sk(sk)->proto.pns.data_ready;
+		sk_raw->sk_backlog_rcv = pppox_sk(sk)->proto.pns.backlog_rcv;
+		sk_raw->sk_user_data = NULL;
+		release_sock(sk_raw);
+		sock_release(sk_raw->sk_socket);
+	}
+
+	sock_orphan(sk);
+	sock->sk = NULL;
+	release_sock(sk);
+	sock_put(sk);
+	return 0;
+}
+
+/******************************************************************************/
+
+static struct proto pppopns_proto = {
+	.name = "PPPOPNS",
+	.owner = THIS_MODULE,
+	.obj_size = sizeof(struct pppox_sock),
+};
+
+static struct proto_ops pppopns_proto_ops = {
+	.family = PF_PPPOX,
+	.owner = THIS_MODULE,
+	.release = pppopns_release,
+	.bind = sock_no_bind,
+	.connect = pppopns_connect,
+	.socketpair = sock_no_socketpair,
+	.accept = sock_no_accept,
+	.getname = sock_no_getname,
+	.poll = sock_no_poll,
+	.ioctl = pppox_ioctl,
+	.listen = sock_no_listen,
+	.shutdown = sock_no_shutdown,
+	.setsockopt = sock_no_setsockopt,
+	.getsockopt = sock_no_getsockopt,
+	.sendmsg = sock_no_sendmsg,
+	.recvmsg = sock_no_recvmsg,
+	.mmap = sock_no_mmap,
+};
+
+static int pppopns_create(struct net *net, struct socket *sock)
+{
+	struct sock *sk;
+
+	sk = sk_alloc(net, PF_PPPOX, GFP_KERNEL, &pppopns_proto);
+	if (!sk)
+		return -ENOMEM;
+
+	sock_init_data(sock, sk);
+	sock->state = SS_UNCONNECTED;
+	sock->ops = &pppopns_proto_ops;
+	sk->sk_protocol = PX_PROTO_OPNS;
+	sk->sk_state = PPPOX_NONE;
+	return 0;
+}
+
+/******************************************************************************/
+
+static struct pppox_proto pppopns_pppox_proto = {
+	.create = pppopns_create,
+	.owner = THIS_MODULE,
+};
+
+static int __init pppopns_init(void)
+{
+	int error;
+
+	error = proto_register(&pppopns_proto, 0);
+	if (error)
+		return error;
+
+	error = register_pppox_proto(PX_PROTO_OPNS, &pppopns_pppox_proto);
+	if (error)
+		proto_unregister(&pppopns_proto);
+	else
+		skb_queue_head_init(&delivery_queue);
+	return error;
+}
+
+static void __exit pppopns_exit(void)
+{
+	unregister_pppox_proto(PX_PROTO_OPNS);
+	proto_unregister(&pppopns_proto);
+}
+
+module_init(pppopns_init);
+module_exit(pppopns_exit);
+
+MODULE_DESCRIPTION("PPP on PPTP Network Server (PPPoPNS)");
+MODULE_AUTHOR("Chia-chi Yeh <chiachi@android.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index cea6cef27e8..db56a995feb 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -110,4 +110,19 @@ config CHARGER_PCF50633
 	help
 	 Say Y to include support for NXP PCF50633 Main Battery Charger.
 
+config BATTERY_AK98
+	tristate "Fake battery from AK98"
+	depends on ARCH_AK98
+	help
+	  Say Y to enable support for the fake battery from SOCLE.
+	  
+config FREQ_POLICY_AK98
+	tristate "Frequency scaling governor from AK98"
+	default y
+	depends on ARCH_AK98 && AK98_CPUFREQ
+	help
+	  Say Y to enable support for frequency scaling(policy layer) from ak98.
+	  
+
+
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index b96f29d91c2..9f33681d12a 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -27,5 +27,8 @@ obj-$(CONFIG_BATTERY_TOSA)	+= tosa_battery.o
 obj-$(CONFIG_BATTERY_WM97XX)	+= wm97xx_battery.o
 obj-$(CONFIG_BATTERY_BQ27x00)	+= bq27x00_battery.o
 obj-$(CONFIG_BATTERY_DA9030)	+= da9030_battery.o
+obj-$(CONFIG_BATTERY_AK98)		+= ak98_battery.o
+obj-$(CONFIG_FREQ_POLICY_AK98)	+= ak98_freq_policy.o
 obj-$(CONFIG_BATTERY_MAX17040)	+= max17040_battery.o
 obj-$(CONFIG_CHARGER_PCF50633)	+= pcf50633-charger.o
+
diff --git a/drivers/power/ak98_battery.c b/drivers/power/ak98_battery.c
new file mode 100755
index 00000000000..a30876f8765
--- /dev/null
+++ b/drivers/power/ak98_battery.c
@@ -0,0 +1,865 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/ts.h>
+#include <mach/adc1.h>
+#include <mach/bat.h>
+
+
+/* BATTERY DEFINE*/
+#define AK98_BAT_DELAY					(HZ * 1)		/* delay 1s */
+#define AK98_DELAY_MINUTE				(1)				/* time to update charge capacity */
+#define AK98_CHARGE_DELAY				(HZ * 60 * AK98_DELAY_MINUTE)		
+#define AK98_USB_DELAY  				100				/* delay 100ms */
+#define AK98_AC_DELAY   				100				/* delay 100ms */
+
+#define PK(fmt...) 		  		//printk(fmt)  // debug ac usb interrupt and read ad4 voltage
+#define PK_SAMPLE(fmt...) 	 	//printk(fmt)  //debug read voltage sample
+#define PK_CHARGE(fmt...)  		//printk(fmt)  //debug charge 
+#define PK_DISCHARGE(fmt...)  	//printk(fmt) //debug discharge
+
+static void ak98usb_timer_handler(unsigned long data);
+static void ak98ac_timer_handler(unsigned long data);
+static void charge_timer_handler(unsigned long data);
+static void voltage_timer_handler(unsigned long data);
+static void ak98_update_bat_state(void);
+static void ak98_update_ac_state(void);
+static void ak98_update_usb_state(void);
+static void ak98_bat_data_init(void);
+
+
+
+struct battery_data{
+	int		bat_voltage;			// battery read voltage
+	int		bat_capacity;			// battery capacity
+	int		bat_status;				// battery charge status
+	int		usb_status;				// battery charge usb status
+	int		ac_status;				// ac online status
+	int		charge_time;			// charge time
+};
+
+struct read_voltage_sample{
+	int 	voltage_index;			// voltage[6] index
+	int 	voltage_max;			// sample max voltage
+	int 	voltage_min;			// sample min voltage
+	int		voltage_sum;			// sum of read voltage
+};
+
+struct ak98_bat{
+	struct ak98_bat_mach_info *pdata;
+	struct battery_data batdata;
+	struct read_voltage_sample voltage;
+};
+
+static struct ak98_bat bat_main ={
+	.pdata	= NULL,
+};
+
+static struct timer_list ak98usb_timer			= TIMER_INITIALIZER(ak98usb_timer_handler, 0, 0);
+static struct timer_list ak98ac_timer   		= TIMER_INITIALIZER(ak98ac_timer_handler, 0, 0);
+static struct timer_list update_voltage_timer	= TIMER_INITIALIZER(voltage_timer_handler, 0, 0);
+static struct timer_list update_charge_timer 	= TIMER_INITIALIZER(charge_timer_handler, 0, 0);
+
+	
+/**
+ * @brief get adc1 ad4 value. if input voltage from 0 to AVDD, it will return the value from 0 to 1023 
+ * @author  
+ * @date 
+ * @return int
+ */
+static int ak98_getbat_voltage(void)
+{	
+    int ad4_value = 0;
+	unsigned int count = 0;
+
+	PK("##################%s:\n",__func__);
+	
+   	//open adc1 and juge if touch scheen is reading.
+	ak98_power_ADC1(POWER_ON);
+    //enable ad4
+    ak98_enable_bat_mon();	
+	        
+	//sample 5 times
+	count = 5;
+    while ( count-- )
+    {
+    	
+        mdelay(1);							//delay for get next point ad4
+        ad4_value += ak98_read_voltage();	//0x3ff for 10 bit adc
+
+	}
+
+	//disable ad4
+    ak98_disable_bat_mon();
+	//power off adc1
+	ak98_power_ADC1(POWER_OFF);   
+
+	//caculate battery value
+	ad4_value =	ad4_value / 5; 							// average of read voltage
+	PK("ad4_data = %d:\n",ad4_value);
+	
+	ad4_value = (ad4_value * bat_main.pdata->bat_adc.adc_avdd) / (1024);	// real read voltage
+	PK("ad4_voltage = %d:\n",ad4_value);
+
+	ad4_value = (ad4_value * (bat_main.pdata->bat_adc.up_resistance + bat_main.pdata->bat_adc.dw_resistance))
+				/ bat_main.pdata->bat_adc.dw_resistance;
+	PK("bat_voltage = %d:\n",ad4_value);
+		
+	ad4_value += bat_main.pdata->bat_adc.voltage_correct;				// correct battery voltage
+	PK("correct_voltage = %d:\n",ad4_value);
+		    
+    return ad4_value;
+}
+
+static void bat_set_int_inverse(unsigned int pin)
+{
+
+	if (ak98_gpio_getpin(pin) == AK98_GPIO_HIGH)
+	{
+		ak98_gpio_intpol(pin, AK98_GPIO_INT_LOWLEVEL);	
+	}
+	else
+	{
+		ak98_gpio_intpol(pin, AK98_GPIO_INT_HIGHLEVEL);
+	}
+
+}
+
+
+// battery power supply define
+static int ak98_battery_get_property(struct power_supply *bat_ps,
+			    enum power_supply_property psp,
+			    union power_supply_propval *val)
+{
+	ak98_update_bat_state();
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_STATUS:
+		val->intval = bat_main.batdata.bat_status;
+		break;
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+		val->intval = bat_main.batdata.bat_voltage;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX:
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+		val->intval = bat_main.pdata->bat_mach_info.max_voltage;
+		break;
+	case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+		val->intval = bat_main.pdata->bat_mach_info.min_voltage;
+		break;
+	case POWER_SUPPLY_PROP_TEMP:
+		val->intval = 25;
+		break;
+	case POWER_SUPPLY_PROP_PRESENT:
+		val->intval = 1;
+		break;
+	case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
+		val->intval = bat_main.batdata.charge_time * 60;
+		break;		
+	case POWER_SUPPLY_PROP_CAPACITY:
+		val->intval = bat_main.batdata.bat_capacity;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static void ak98_battery_external_power_changed(struct power_supply *bat_ps)
+{
+	// NULL
+
+}
+
+
+static enum power_supply_property ak98_battery_main_props[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_VOLTAGE_MAX,
+	POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+	POWER_SUPPLY_PROP_TEMP,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
+	POWER_SUPPLY_PROP_CAPACITY,
+};
+
+struct power_supply bat_ps = {
+	.name					= "battery",
+	.type					= POWER_SUPPLY_TYPE_BATTERY,
+	.properties				= ak98_battery_main_props,
+	.num_properties			= ARRAY_SIZE(ak98_battery_main_props),
+	.get_property			= ak98_battery_get_property,
+	.external_power_changed = ak98_battery_external_power_changed,
+	.use_for_apm			= 1,
+};
+
+#ifdef ANYKA_BATTERY_DEBUG
+static char *status_text[] = {
+	[POWER_SUPPLY_STATUS_UNKNOWN] =		"Unknown",
+	[POWER_SUPPLY_STATUS_CHARGING] =	"Charging",
+	[POWER_SUPPLY_STATUS_DISCHARGING] =	"Discharging",
+};
+#endif
+
+
+
+// battery power supply define end
+
+
+// usb power supply define
+static int usb_get_property(struct power_supply *psy,
+			enum power_supply_property psp,
+			union power_supply_propval *val)
+{
+	int ret = 0;
+	
+
+	ak98_update_usb_state();	
+	
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = bat_main.batdata.usb_status;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static enum power_supply_property power_props[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+struct power_supply usb_ps ={
+	.name				= "usb",
+	.type				= POWER_SUPPLY_TYPE_USB,
+	.properties 		= power_props,
+	.num_properties 	= ARRAY_SIZE(power_props),
+	.get_property		= usb_get_property,
+};
+// usb power supply define end!
+
+
+// ac power supply
+static int ac_get_property(struct power_supply *psy,
+			enum power_supply_property psp,
+			union power_supply_propval *val)
+{
+	int ret = 0;
+	
+	ak98_update_ac_state();	
+	
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = bat_main.batdata.ac_status;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+
+static enum power_supply_property ac_power_props[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+struct power_supply ac_ps ={
+	.name				= "ac",
+	.type				= POWER_SUPPLY_TYPE_MAINS,
+	.properties 		= ac_power_props,
+	.num_properties 	= ARRAY_SIZE(ac_power_props),
+	.get_property		= ac_get_property,
+};
+// ac power supply define end!
+
+
+
+#ifdef CONFIG_PM
+static int ak98_battery_suspend(struct platform_device *dev, pm_message_t state)
+{
+	return 0;
+}
+
+static int ak98_battery_resume(struct platform_device *dev)
+{
+	ak98_bat_data_init();	
+	power_supply_changed(&bat_ps);
+	power_supply_changed(&ac_ps);
+	power_supply_changed(&usb_ps);	
+	return 0;
+}
+#else
+#define ak98_battery_suspend NULL
+#define ak98_battery_resume NULL
+#endif
+
+/*
+*   
+*  return array_y value
+*/
+static int get_arrayy_from_arrayx(const int array_x[],const int array_y[],
+								  int array_nums, int x_num )
+{
+	int x0, y0;
+	int x1, y1;
+	int n;
+	int num = x_num;
+	int ret = 0;
+
+	PK_DISCHARGE("array_x:%4d,%4d,%4d,%4d,%4d\n",array_x[0],array_x[1],
+		array_x[2],array_x[3],array_x[4]);
+	PK_DISCHARGE("array_y:%4d,%4d,%4d,%4d,%4d\n",array_y[0],array_y[1],
+		array_y[2],array_y[3],array_y[4]);
+	PK_DISCHARGE("array_nums=%d;x_num=%d\n",array_nums,x_num);
+	PK_DISCHARGE("length=%d;points=%d\n",bat_main.pdata->discharge.length
+		,bat_main.pdata->discharge.points);
+	
+	if (num < array_x[0])
+	{
+		num = array_x[0];
+	}
+
+	if (num > array_x[array_nums-1])
+	{
+		num = array_x[array_nums-1];
+	}
+
+	PK_DISCHARGE("array_nums=%d;num=%d\n",array_nums,num);
+	
+
+	for (n=1; n<array_nums; n++)
+	{
+		if (num <= array_x[n])
+		{
+			x0 = array_x[n-1];
+			y0 = array_y[n-1];
+			x1 = array_x[n];
+			y1 = array_y[n];
+			ret = ((num -x0) * (y1 - y0)) / (x1 - x0) + y0;
+			PK_DISCHARGE("ret=%d;\n",ret);
+			break;
+		}
+	}
+	
+	return ret;
+}
+
+
+//caculate charge time from capacity,modify ak98_bat_data.charge_time
+static void get_charge_time_from_cap(int bat_capacity)
+{
+	bat_main.batdata.charge_time = get_arrayy_from_arrayx(bat_main.pdata->charge.capacity,
+										bat_main.pdata->charge.time,
+										bat_main.pdata->charge.points, bat_capacity);
+}
+
+//caculate capacity from charge time,modify ak98_bat_data.bat_capacity
+static void get_charge_cap_from_time(int time)
+{
+	bat_main.batdata.bat_capacity = get_arrayy_from_arrayx(bat_main.pdata->charge.time,
+										bat_main.pdata->charge.capacity,
+										bat_main.pdata->charge.points, time);
+}
+
+//caculate capacity from charge voltage,modify bat_data.bat_capacity
+static void get_charge_cap_from_voltage(int voltage)
+{
+	bat_main.batdata.bat_capacity = get_arrayy_from_arrayx(bat_main.pdata->charge_cv.voltage
+								,bat_main.pdata->charge_cv.capacity
+								,bat_main.pdata->charge_cv.points, voltage);
+}
+
+
+//caculate capacity from discharge voltage,modify bat_data.bat_capacity
+static void get_discharge_cap_from_voltage(int voltage)
+{
+	bat_main.batdata.bat_capacity= get_arrayy_from_arrayx(bat_main.pdata->discharge.voltage,
+										bat_main.pdata->discharge.capacity,
+										bat_main.pdata->discharge.points, voltage);
+}
+
+static void ak98_add_battime_min(int n)
+{
+	bat_main.batdata.charge_time += n;
+	
+	if (bat_main.batdata.charge_time < 0)
+	{
+		bat_main.batdata.charge_time =0;		
+	}
+	
+	if (bat_main.batdata.charge_time >= bat_main.pdata->bat_mach_info.charge_max_time)
+	{
+		bat_main.batdata.charge_time = bat_main.pdata->bat_mach_info.charge_max_time - 1;
+	}
+}
+
+static void ak98_init_sample_value(void)
+{
+	bat_main.voltage.voltage_index		= 0;		
+	bat_main.voltage.voltage_sum		= 0;
+	bat_main.voltage.voltage_max	  	= 0;
+	bat_main.voltage.voltage_min	  	= bat_main.pdata->bat_mach_info.max_voltage * 2;
+}
+
+static void ak98_update_voltage(void)
+{
+	int temp;
+	
+	PK_SAMPLE("\n###############%s; \n",__func__);
+
+	// if voltage_index in correct range
+	if ((bat_main.voltage.voltage_index > bat_main.pdata->bat_mach_info.voltage_sample) 
+		|| (bat_main.voltage.voltage_index < 0))		
+	{
+		printk("%s:error voltage sample index\n",__func__);
+		ak98_init_sample_value();
+	}
+	
+	// read voltage sample,and save voltage max and min;
+	temp = ak98_getbat_voltage();
+	if (temp > bat_main.voltage.voltage_max)
+	{
+		bat_main.voltage.voltage_max = temp;	
+	}
+
+	if (temp < bat_main.voltage.voltage_min)
+	{
+		bat_main.voltage.voltage_min = temp;
+	}
+	
+	PK_SAMPLE("read_voltage=%d\n",temp);
+	PK_SAMPLE("voltage_max=%d;	voltage_min=%d;\n",
+			  bat_main.voltage.voltage_max,bat_main.voltage.voltage_min);
+	PK_SAMPLE("voltage_index=%d; voltage_sum=%d;\n",bat_main.voltage.voltage_index,
+				bat_main.voltage.voltage_sum);
+	
+	bat_main.voltage.voltage_sum += temp;
+	
+	if (++bat_main.voltage.voltage_index == bat_main.pdata->bat_mach_info.voltage_sample)
+	{
+		bat_main.voltage.voltage_sum	 -= bat_main.voltage.voltage_min 
+											+ bat_main.voltage.voltage_max;
+		bat_main.voltage.voltage_index -= 2;
+		bat_main.batdata.bat_voltage	= bat_main.voltage.voltage_sum 
+										/ bat_main.voltage.voltage_index;
+
+		PK_SAMPLE("=========bat_data.voltage = %d;=======\n",bat_main.batdata.bat_voltage);
+		ak98_init_sample_value();
+	}
+	
+}
+
+static void update_discharge_capacity(void)
+{
+	ak98_update_bat_state();
+	if (bat_main.batdata.bat_status == POWER_SUPPLY_STATUS_DISCHARGING)
+	{
+		int old_capacity = bat_main.batdata.bat_capacity;		
+
+		PK_DISCHARGE("###########%s:\n",__func__);
+		
+		get_discharge_cap_from_voltage(bat_main.batdata.bat_voltage);
+
+		if (bat_main.batdata.bat_capacity > old_capacity)
+		{
+			bat_main.batdata.bat_capacity = old_capacity;
+		}
+		
+		if (bat_main.batdata.bat_capacity <= bat_main.pdata->bat_mach_info.power_down_level)
+		{
+			bat_main.batdata.bat_capacity = 0;
+		}
+
+		if (old_capacity != bat_main.batdata.bat_capacity)
+		{
+			get_charge_time_from_cap(bat_main.batdata.bat_capacity);
+			power_supply_changed(&bat_ps);
+		}
+
+		PK_DISCHARGE("voltage = %d;capacity = %d;\n",
+					 bat_main.batdata.bat_voltage,bat_main.batdata.bat_capacity);
+	}
+}
+
+static void ak98usb_timer_handler(unsigned long data)
+{	
+	PK("##################%s:\n", __func__);
+	
+	power_supply_changed(&usb_ps);	
+	bat_set_int_inverse(bat_main.pdata->usb_gpio.pindata.pin);	
+	enable_irq(bat_main.pdata->usb_gpio.irq);
+}
+
+static void ak98ac_timer_handler(unsigned long data)
+{
+	PK("##################%s:\n", __func__);
+	
+	power_supply_changed(&bat_ps);
+	power_supply_changed(&ac_ps);
+	
+	bat_set_int_inverse(bat_main.pdata->ac_gpio.pindata.pin);	
+	enable_irq(bat_main.pdata->ac_gpio.irq);
+}
+
+static int read_pin_is_active(int pin, int active)
+{
+	if (pin >= 0)
+	{
+		return (ak98_gpio_getpin((unsigned int)pin)) == active ? AK_TRUE : AK_FALSE;
+	}
+	else
+	{
+		return AK_FALSE; 
+	}	
+
+
+}
+
+// battery from not full to full
+static void ak98_capacity_is_full(void)
+{
+	static int full_count = 1;
+	
+	ak98_update_bat_state();
+	if ((bat_main.batdata.bat_status == POWER_SUPPLY_STATUS_CHARGING)
+		&& (bat_main.batdata.bat_capacity != bat_main.pdata->bat_mach_info.full_capacity)
+		&& read_pin_is_active(bat_main.pdata->state_gpio.pindata.pin,bat_main.pdata->state_gpio.active)) 
+	{
+		if (++full_count > 10)
+		{
+			// full_count reach 10, battery capacity is real full
+			full_count = 1;
+			bat_main.batdata.bat_capacity = bat_main.pdata->bat_mach_info.full_capacity; 		
+			get_charge_time_from_cap(bat_main.batdata.bat_capacity);
+			PK_CHARGE("###############%s:\n",__func__);
+		}			
+	}
+	else
+	{
+		full_count = 1;
+	}
+	
+}
+
+// battery from full to not full
+static void ak98_capacity_isnot_full(void)
+{
+	ak98_update_bat_state();
+	if ((bat_main.batdata.bat_status == POWER_SUPPLY_STATUS_CHARGING)
+		&& (bat_main.batdata.bat_capacity == bat_main.pdata->bat_mach_info.full_capacity)
+		&& !read_pin_is_active(bat_main.pdata->state_gpio.pindata.pin,bat_main.pdata->state_gpio.active)) 
+	{
+		// battery capacity is not full
+		bat_main.batdata.bat_capacity = bat_main.pdata->bat_mach_info.full_capacity - 1;
+		get_charge_time_from_cap(bat_main.batdata.bat_capacity);
+		PK_CHARGE("###############%s:\n",__func__);
+	}		
+}
+
+static void voltage_timer_handler(unsigned long data)
+{
+	PK_DISCHARGE("###############%s:\n",__func__);
+	
+	ak98_update_voltage();
+	if (0 == bat_main.voltage.voltage_index)
+	{
+		update_discharge_capacity();
+		PK_DISCHARGE("voltage=%d; time=%d;capacity=%d;\n",
+					 bat_main.batdata.bat_voltage,bat_main.batdata.charge_time,
+					 bat_main.batdata.bat_capacity);
+	}
+	
+	mod_timer(&update_voltage_timer,jiffies + AK98_BAT_DELAY);
+}
+
+static void update_charge_capacity(void)
+{
+	int old_capacity = bat_main.batdata.bat_capacity;
+	
+	ak98_update_bat_state();
+	if (bat_main.batdata.bat_status == POWER_SUPPLY_STATUS_CHARGING)
+	{
+		PK_CHARGE("###############%s:\n",__func__);
+	
+		if ( bat_main.pdata->bat_mach_info.full_capacity != bat_main.batdata.bat_capacity )
+		{
+			ak98_add_battime_min(AK98_DELAY_MINUTE);
+			get_charge_cap_from_time(bat_main.batdata.charge_time);
+			ak98_capacity_is_full();		
+		}
+		else
+		{
+			ak98_capacity_isnot_full();			
+		}
+
+		if (bat_main.batdata.bat_capacity != old_capacity)
+		{
+			power_supply_changed(&bat_ps);
+		}
+					
+		PK_CHARGE("voltage = %d; time = %d; capacity = %d;\n",
+		  bat_main.batdata.bat_voltage,bat_main.batdata.charge_time
+		  ,bat_main.batdata.bat_capacity);
+	}	  
+}
+
+static void charge_timer_handler(unsigned long data)
+{
+	PK_CHARGE("###############%s:\n",__func__);
+
+	update_charge_capacity();
+	mod_timer(&update_charge_timer,jiffies + AK98_CHARGE_DELAY);
+//	mod_timer(&update_charge_timer,jiffies + HZ * 1);
+}
+
+static int ak98_get_charge_state(int pinstate,int active)
+{
+	if (pinstate >= 0)
+	{
+		return (ak98_gpio_getpin((unsigned int)pinstate)) == active ? 
+			   POWER_SUPPLY_STATUS_CHARGING : POWER_SUPPLY_STATUS_DISCHARGING;
+	}
+	else
+	{
+		return POWER_SUPPLY_STATUS_UNKNOWN; 
+	}	
+}
+
+static void ak98_update_bat_state(void)
+{
+	bat_main.batdata.bat_status = ak98_get_charge_state(bat_main.pdata->ac_gpio.pindata.pin
+									,bat_main.pdata->ac_gpio.active);	
+}
+
+static void ak98_update_ac_state(void)
+{
+	bat_main.batdata.ac_status = ak98_get_charge_state(bat_main.pdata->ac_gpio.pindata.pin
+									,bat_main.pdata->ac_gpio.active);	
+}
+
+static void ak98_update_usb_state(void)
+{
+	if (bat_main.pdata->usb_gpio.irq > 0)
+	{
+		bat_main.batdata.usb_status = ak98_get_charge_state(bat_main.pdata->usb_gpio.pindata.pin
+										,bat_main.pdata->usb_gpio.active);
+	}
+	else
+	{
+		bat_main.batdata.usb_status = POWER_SUPPLY_STATUS_DISCHARGING;				
+	}
+}
+
+static irqreturn_t ak98bat_ac_irqhandler(int irq, void *handle)
+{
+
+	PK("##################%s:\n", __func__);
+
+	disable_irq_nosync(irq);
+	mod_timer(&ak98ac_timer,jiffies + msecs_to_jiffies(AK98_AC_DELAY));
+	
+	return IRQ_HANDLED;	
+}
+
+static irqreturn_t ak98bat_usb_irqhandler(int irq, void *handle) 
+{
+
+	PK("##################%s:\n", __func__);
+
+	disable_irq_nosync(irq);
+	mod_timer(&ak98usb_timer,jiffies + msecs_to_jiffies(AK98_USB_DELAY));
+	
+	return IRQ_HANDLED;		
+}
+
+static void ak98_bat_data_init(void)
+{
+	ak98_update_bat_state();
+	ak98_update_ac_state();
+	ak98_update_usb_state();
+	
+	bat_main.batdata.bat_voltage = ak98_getbat_voltage();
+	if (bat_main.batdata.bat_status == POWER_SUPPLY_STATUS_CHARGING)
+	{
+		get_charge_cap_from_voltage(bat_main.batdata.bat_voltage);
+	}
+	else
+	{
+		get_discharge_cap_from_voltage(bat_main.batdata.bat_voltage);
+	}
+	
+	get_charge_time_from_cap(bat_main.batdata.bat_capacity);
+	ak98_capacity_isnot_full();
+	ak98_init_sample_value();
+}
+
+static int __devinit ak98_battery_probe(struct platform_device *dev)
+{
+	int ret = 0;
+	struct ak98_bat_mach_info *info;
+
+	printk("%s:\n",__func__);
+
+	info = (struct ak98_bat_mach_info *)dev->dev.platform_data;
+	if (!info) 
+	{
+		printk(KERN_ERR "%s:no platform data for battery\n",__func__);
+		ret = -EINVAL;
+		goto out;
+	}	
+
+	bat_main.pdata	= info;
+
+	// use for ac charge in irq
+	if (info->ac_gpio.irq >= 0)
+	{
+		info->gpio_init(&info->ac_gpio.pindata);
+		bat_set_int_inverse(info->ac_gpio.pindata.pin);	
+		if (request_irq(info->ac_gpio.irq, ak98bat_ac_irqhandler, 0, "ac_charge", dev))
+		{
+			printk(KERN_ERR "%s:Could not allocate IRQ %d\n", __func__,info->ac_gpio.irq);
+			ret = -EIO;
+			goto out;
+		}
+	}
+	
+	// use for usb charge in irq
+	if (info->usb_gpio.irq >= 0)
+	{
+		info->gpio_init(&info->usb_gpio.pindata);
+		bat_set_int_inverse(info->usb_gpio.pindata.pin);	
+		if (request_irq(info->usb_gpio.irq, ak98bat_usb_irqhandler, 0, "usb_charge", dev))
+		{
+			printk(KERN_ERR "%s:Could not allocate IRQ %d\n", __func__,info->usb_gpio.irq);
+			ret = -EIO;
+			goto free_acirq_out;
+		}
+	}
+
+	// use for charge full state 
+	if (info->state_gpio.pindata.pin >= 0)
+	{
+		info->gpio_init(&info->state_gpio.pindata);
+	}
+	
+	/* initialize hardware */
+	ak98_init_ADC1(info->bat_adc.sample_rate, info->bat_adc.wait_time);
+	ak98_bat_data_init();
+	
+	mod_timer(&update_voltage_timer,jiffies + AK98_BAT_DELAY);
+	mod_timer(&update_charge_timer,jiffies + AK98_CHARGE_DELAY);
+		
+	ret = power_supply_register(&dev->dev, &bat_ps);
+	if (ret != 0)
+	{
+		goto free_out;
+	}
+	
+	ret = power_supply_register(&dev->dev,&usb_ps);
+	if (ret != 0)
+	{
+		goto free_bat_ps_out;
+	}
+	
+	ret = power_supply_register(&dev->dev,&ac_ps);
+	if (ret != 0)
+	{
+		goto free_usb_ps_out;
+	}
+
+	
+	return ret;
+	
+free_usb_ps_out:
+	power_supply_unregister(&usb_ps);
+free_bat_ps_out:
+	power_supply_unregister(&bat_ps);
+free_out:
+	if (info->usb_gpio.irq > 0)
+	{
+		disable_irq(info->usb_gpio.irq);
+		free_irq(info->usb_gpio.irq, dev);
+	}
+free_acirq_out:
+	if (info->ac_gpio.irq > 0)
+	{
+		disable_irq(info->ac_gpio.irq);
+		free_irq(info->ac_gpio.irq, dev);
+	}
+out:
+	printk(KERN_ERR "###########%s:ERR out##########\n",__func__);
+	return ret;
+
+
+}
+
+static int __devexit ak98_battery_remove(struct platform_device *dev)
+{	
+	struct ak98_bat_mach_info *info;
+	
+	info = (struct ak98_bat_mach_info *)dev->dev.platform_data;
+	if (!info) {
+		printk(KERN_ERR "no platform data for battery\n");
+		return -EINVAL;
+	}	
+
+	if (info->ac_gpio.irq > 0)
+	{
+		disable_irq(info->ac_gpio.irq);
+		free_irq(info->ac_gpio.irq, dev);
+	}
+	
+	if (info->usb_gpio.irq > 0)
+	{
+		disable_irq(info->usb_gpio.irq);
+		free_irq(info->usb_gpio.irq, dev);
+	}
+	
+	power_supply_unregister(&bat_ps);
+	power_supply_unregister(&usb_ps);
+	power_supply_unregister(&ac_ps);
+	return 0;
+}
+
+static struct platform_driver ak98_battery_driver = {
+	.driver		= {
+		.name	= "fake_battery",
+	},
+	.probe		= ak98_battery_probe,
+	.remove		= __devexit_p(ak98_battery_remove),
+	.suspend	= ak98_battery_suspend,
+	.resume		= ak98_battery_resume,
+};
+
+static int __init ak98_battery_init(void)
+{
+	return platform_driver_register(&ak98_battery_driver);
+}
+
+static void __exit ak98_battery_exit(void)
+{
+	platform_driver_unregister(&ak98_battery_driver);
+}
+
+module_init(ak98_battery_init);
+module_exit(ak98_battery_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Anyka <xxx@anyak.oa>");
+MODULE_DESCRIPTION("Fake battery driver");
diff --git a/drivers/power/ak98_freq_policy.c b/drivers/power/ak98_freq_policy.c
new file mode 100755
index 00000000000..38ac41557b2
--- /dev/null
+++ b/drivers/power/ak98_freq_policy.c
@@ -0,0 +1,673 @@
+/*
+ * AK98 frequency conversion policy layer
+ *
+ * Copyright (C) 2011 ANYKA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/miscdevice.h>
+#include <linux/proc_fs.h>
+#include <linux/stat.h>
+#include <linux/sched.h>
+#include <asm/uaccess.h>
+#include <linux/string.h>
+#include <linux/ak98_freq_policy.h>
+#include <linux/semaphore.h>
+#include <linux/delay.h>
+
+
+
+//#define FREQ_DEBUG
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef FREQ_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+
+struct t_app_to_mode app_to_mode[] = {
+		{"browser", NORMAL_MODE_CLOCK_5},
+		{"Email", NORMAL_MODE_CLOCK_5},
+		{"LauncherApp", NORMAL_MODE_CLOCK_3},
+		{"PartialWakeLockApp", LOW_MODE_CLOCK_1},
+		{"ScreenDimWakeLockApp", NORMAL_MODE_CLOCK_3},
+		{"ScreenBrightWakeLockApp", NORMAL_MODE_CLOCK_5},
+		{"FullWakeLockApp", NORMAL_MODE_CLOCK_5},
+		{"WifiService", NORMAL_MODE_CLOCK_5},
+		{"low_test0",LOW_MODE_CLOCK_0},
+		{"AudioOutLock", LOW_MODE_CLOCK_1},
+		{"CameraService", NORMAL_MODE_CLOCK_5},
+		{"MediaRecorder",NORMAL_MODE_CLOCK_5},
+		{"WindowRotate",NORMAL_MODE_CLOCK_5},
+		{"MonitorCpuLow", NORMAL_MODE_CLOCK_3},
+		{"MonitorCpuHigh", NORMAL_MODE_CLOCK_5},
+		{"low_test2", LOW_MODE_CLOCK_2},
+		{"low_test3", LOW_MODE_CLOCK_3},
+		{"low_test4", LOW_MODE_CLOCK_4},
+		{"low_test5", LOW_MODE_CLOCK_5},
+		{"low_test6", LOW_MODE_CLOCK_6},
+		{"low_test7", LOW_MODE_CLOCK_7},
+		{"normal_test0", NORMAL_MODE_CLOCK_0},
+		{"normal_test1", NORMAL_MODE_CLOCK_1},
+		{"normal_test2", NORMAL_MODE_CLOCK_2},
+		{"normal_test3", NORMAL_MODE_CLOCK_3},
+		{"normal_test4", NORMAL_MODE_CLOCK_4},
+		{"normal_test5", NORMAL_MODE_CLOCK_5},
+		{"normal_test6", NORMAL_MODE_CLOCK_6},
+		{"normal_test7", NORMAL_MODE_CLOCK_7},
+		{"video_test0", VIDEO_MODE_CLOCK_0},
+		{"video_test1", VIDEO_MODE_CLOCK_1},
+		{"video_test2", VIDEO_MODE_CLOCK_2},
+		{"video_test3", VIDEO_MODE_CLOCK_3},
+		{"video_test4", VIDEO_MODE_CLOCK_4},
+		{"video_test5", VIDEO_MODE_CLOCK_5},
+		{"video_test6", VIDEO_MODE_CLOCK_6},
+		{"video_test7", VIDEO_MODE_CLOCK_7},		
+		{"bkmusic_test", BK_MUSIC_MODE},	
+};
+
+
+
+struct mode_table_node name_to_mode[] = {
+		{"LOW_MODE_CLOCK_0", LOW_MODE_CLOCK_0},
+		{"LOW_MODE_CLOCK_1", LOW_MODE_CLOCK_1},
+		{"LOW_MODE_CLOCK_2", LOW_MODE_CLOCK_2},
+		{"LOW_MODE_CLOCK_3", LOW_MODE_CLOCK_3},
+		{"LOW_MODE_CLOCK_4", LOW_MODE_CLOCK_4},
+		{"LOW_MODE_CLOCK_5", LOW_MODE_CLOCK_5},
+		{"LOW_MODE_CLOCK_6", LOW_MODE_CLOCK_6},
+		{"LOW_MODE_CLOCK_7", LOW_MODE_CLOCK_7},
+		{"NORMAL_MODE_CLOCK_0", NORMAL_MODE_CLOCK_0},
+		{"NORMAL_MODE_CLOCK_1", NORMAL_MODE_CLOCK_1},
+		{"NORMAL_MODE_CLOCK_2", NORMAL_MODE_CLOCK_2},
+		{"NORMAL_MODE_CLOCK_3", NORMAL_MODE_CLOCK_3},
+		{"NORMAL_MODE_CLOCK_4", NORMAL_MODE_CLOCK_4},
+		{"NORMAL_MODE_CLOCK_5", NORMAL_MODE_CLOCK_5},
+		{"NORMAL_MODE_CLOCK_6", NORMAL_MODE_CLOCK_6},
+		{"NORMAL_MODE_CLOCK_7", NORMAL_MODE_CLOCK_7},
+		{"VIDEO_MODE_CLOCK_0", VIDEO_MODE_CLOCK_0},
+		{"VIDEO_MODE_CLOCK_1", VIDEO_MODE_CLOCK_1},
+		{"VIDEO_MODE_CLOCK_2", VIDEO_MODE_CLOCK_2},
+		{"VIDEO_MODE_CLOCK_3", VIDEO_MODE_CLOCK_3},
+		{"VIDEO_MODE_CLOCK_4", VIDEO_MODE_CLOCK_4},
+		{"VIDEO_MODE_CLOCK_5", VIDEO_MODE_CLOCK_5},
+		{"VIDEO_MODE_CLOCK_6", VIDEO_MODE_CLOCK_6},
+		{"VIDEO_MODE_CLOCK_7", VIDEO_MODE_CLOCK_7},
+};
+const char *undefined_mode = "Undefined mode";
+
+
+/**************************************************************/
+
+
+static void change_work(struct work_struct *work);
+static const char* get_mode_name(T_MODE_TYPE mode);
+static int is_higher_mode(T_MODE_TYPE mode1, T_MODE_TYPE mode2);
+static int change_mode(T_MODE_TYPE mode );
+T_MODE_TYPE get_target_mode(void);
+static T_MODE_TYPE get_mode_by_name(char *name);
+
+#define MAX_HOLD_MODE_PENDING 20
+struct callback_params {
+	AK98_RQSTMODE_CALLBACK fn;
+	void *data;
+};
+
+
+static struct callback_params g_param_queue[MAX_HOLD_MODE_PENDING];
+static int g_head, g_tail;
+static struct rqst_node g_rqst_list[NUM_OF_MODE];
+static int g_hold_modes[NUM_OF_MODE] = {0};
+/* mode under which  system is running*/
+static T_MODE_TYPE g_current_mode;
+/* mode under which system should be running , it's value is calculated according to all the mode requests*/
+static T_MODE_TYPE g_target_mode;
+static unsigned int g_current_pll;
+static unsigned int g_target_pll;
+
+static int g_tag_cnt=0;
+//static struct timer_list change_timer = TIMER_INITIALIZER(change_timer_handler, 0, 0);
+
+static struct workqueue_struct *g_freq_policy_wq;
+static struct delayed_work	g_work;
+static struct delayed_work  g_hold_mode_work;
+static struct semaphore g_sem;
+static int pll_change = 0;
+
+
+static void judge_and_change(void)
+{
+	g_target_mode = get_target_mode();
+	g_target_pll = get_pll_sel(g_target_mode);
+	PDEBUG("current mode: %s   target mode: %s\n", get_mode_name(g_current_mode), get_mode_name(g_target_mode));
+
+    /* response immediately when higher mode request is coming */	
+	if (is_higher_mode(g_target_mode, g_current_mode))
+	{
+		//del_timer(&change_timer);
+		cancel_delayed_work(&g_work);
+		if (g_target_pll != g_current_pll)
+		{
+			pll_change = 1;
+			queue_delayed_work(g_freq_policy_wq, &g_work,
+				      msecs_to_jiffies(PLL_CHANGE_DELAY));
+		}
+		else if (0 == change_mode(g_target_mode))
+		{
+			g_current_mode = g_target_mode;
+			g_current_pll = g_target_pll;
+		}
+	}
+	else if (is_higher_mode(g_current_mode, g_target_mode))
+	{
+		//del_timer(&change_timer);
+		cancel_delayed_work(&g_work);
+		queue_delayed_work(g_freq_policy_wq, &g_work,
+				      msecs_to_jiffies(REQUEST_DELAY));
+		//mod_timer(&change_timer, jiffies+ msecs_to_jiffies(REQUEST_DELAY));
+	}
+	
+}
+
+static void hold_mode_work(struct work_struct *work)
+{	
+	down(&g_sem);
+	
+	judge_and_change();	
+	if (g_param_queue[g_head].fn)
+		(*(g_param_queue[g_head].fn))(g_param_queue[g_head].data);
+	g_head++;
+	if (g_head == MAX_HOLD_MODE_PENDING)
+		g_head = 0;
+	
+	up(&g_sem);
+}
+
+
+int ak98_request_hold_mode(T_MODE_TYPE mode, AK98_RQSTMODE_CALLBACK fn, 
+	void *data)
+
+{
+	if (!(mode >= LOWEST_MODE && mode <= HIGHEST_MODE))
+		panic("Wrong value passed to mode. --- %d\n", mode);
+	
+	g_hold_modes[mode]++;
+	g_param_queue[g_tail].fn = fn;
+	g_param_queue[g_tail].data = data;
+
+	g_tail++;
+	if (g_tail == g_head)
+	{
+		printk("Too many hold mode are pending.\n");
+		return -1;
+	}
+	if (g_tail == MAX_HOLD_MODE_PENDING)
+		g_tail = 0;
+	queue_delayed_work(g_freq_policy_wq, &g_hold_mode_work,
+				      0);	
+	return 0;
+}
+
+EXPORT_SYMBOL(ak98_request_hold_mode);
+
+int ak98_release_hold_mode(T_MODE_TYPE mode)
+{
+	if (!(mode >= LOWEST_MODE && mode <= HIGHEST_MODE))
+		panic("Wrong value passed to mode. --- %d\n", mode);
+
+	if (g_hold_modes[mode] <= 0)
+		return -1;
+	
+	g_hold_modes[mode]--;
+	PDEBUG("Release pid: %d  tag: %d\n", pid, tag);
+	g_target_mode = get_target_mode();
+
+	/* if not equal, g_target_mode must be lower than 
+	 * g_current_mode (thats to say: g_target_mode <= g_current_mode)
+	*/
+	PDEBUG("target mode: %s\n", get_mode_name(g_target_mode));
+	if (g_target_mode != g_current_mode)
+	{
+		cancel_delayed_work(&g_work);
+		queue_delayed_work(g_freq_policy_wq, &g_work,
+				      msecs_to_jiffies(RELEASE_DELAY));		
+	}	
+	return 0;
+}
+
+EXPORT_SYMBOL(ak98_release_hold_mode);
+
+static const char* get_mode_name(T_MODE_TYPE mode)
+{
+	int i, n=ARRAY_SIZE(name_to_mode);
+
+	if (name_to_mode[mode].mode == mode)
+		return name_to_mode[mode].modeName;
+	for (i=0; i<n; i++)
+		if (name_to_mode[i].mode == mode)
+			return name_to_mode[i].modeName;
+	return undefined_mode;
+}
+static int is_higher_mode(T_MODE_TYPE mode1, T_MODE_TYPE mode2)
+{
+	if (HIGHEST_MODE > LOWEST_MODE)
+		return mode1 > mode2;
+	else
+		return mode1 < mode2;
+}
+/*
+T_OPERATION_MODE get_current_mode(void)
+{
+	return DEFAULT_MODE;
+}
+int request_cpufreq_enter(T_MODE_TYPE mode)
+{
+	PDEBUG("request mode %s\n", get_mode_name(mode));
+	return 0;
+}*/
+
+static int change_mode(T_MODE_TYPE mode)
+{
+
+	return request_cpufreq_enter(mode);
+}
+
+static void change_work(struct work_struct *work)
+{
+	down(&g_sem);
+	if (is_higher_mode(g_current_mode, g_target_mode))
+	{	
+		PDEBUG("change mode: from %s to %s\n", get_mode_name(g_current_mode), get_mode_name(g_target_mode));
+		if (change_mode(g_target_mode) == 0)
+		{
+			g_current_mode = g_target_mode;
+			g_current_pll = g_target_pll;
+		}
+	}
+	else if (pll_change)
+	{
+		pll_change = 0;
+		if (change_mode(g_target_mode) == 0)
+		{
+			g_current_mode = g_target_mode;
+			g_current_pll = g_target_pll;
+		}
+	}
+	up(&g_sem);
+}
+
+static ssize_t ak98_freq_policy_read(struct file *file, char *buf,
+			     size_t count, loff_t * ppos)
+{
+	int i;
+	struct rqst_node *cur;
+	struct list_head *pos,*n;
+	
+	//spin_lock(&freq_policy_lock);
+	down(&g_sem);
+	printk("Hold mode:\n");
+	for (i=HIGHEST_MODE; i>=LOWEST_MODE; --i)
+	{
+		if (g_hold_modes[i]>0)
+			printk("%s  %d\n", get_mode_name(i), g_hold_modes[i]);
+	}
+	printk("---------------------\n");
+	for (i=LOW_IX; i<= HIGH_IX; i++)
+	{
+		printk("%s(%d) --", get_mode_name(i),g_rqst_list[i].app_info.appName[0]);
+		list_for_each_safe(pos, n, &(g_rqst_list[i].list))
+		{
+			cur = list_entry(pos, struct rqst_node, list);
+			printk("%s(%d %d) ",cur->app_info.appName, cur->app_info.pid, cur->app_info.tag);			
+		}
+		printk("\n");
+	}
+	printk("current mode: %s  target mode: %s\n", get_mode_name(g_current_mode), 
+		get_mode_name(g_target_mode));
+	printk("bk music mode: %s\n", get_mode_name(BK_MUSIC_MODE));
+	//spin_unlock(&freq_policy_lock);
+	up(&g_sem);
+	return 0;
+}
+
+/*
+ * if video request and normal request are not empty, then target mode is max video request + 1
+ * else if video request is not empty , then target mode is max video request
+ * else if normal request is not empty, then target mode is max normal request
+ * else target mode is max low request
+ */
+T_MODE_TYPE get_target_mode(void)
+{
+	int i;
+	int low_max = -1;
+	int normal_max = -1;
+	int video_max = -1;
+	//struct rqst_mode *cur;
+
+	/*
+		if mode requested by ak98_request_hold_mode exists, then keep the mode ignore 
+	*/
+	for (i=HIGHEST_MODE; i>=LOWEST_MODE; --i)
+		if (g_hold_modes[i]>0)
+			return i;
+
+	for (i=LOW_MODE_CLOCK_MAX; i>=LOW_MODE_CLOCK_MIN; i--)
+	{
+		if (!list_empty(&(g_rqst_list[i].list)))
+		{
+			normal_max = i;
+			break;
+		}
+	}	
+
+	for (i=NORMAL_MODE_CLOCK_MAX; i>=NORMAL_MODE_CLOCK_MIN; i--)
+	{
+		if (!list_empty(&(g_rqst_list[i].list)))
+		{
+			normal_max = i;
+			break;
+		}
+	}
+	
+	for (i=VIDEO_MODE_CLOCK_MAX; i>=VIDEO_MODE_CLOCK_MIN; i--)
+	{
+		if (!list_empty(&(g_rqst_list[i].list)))
+		{
+			video_max = i;
+			break;
+		}
+	}
+
+	if (normal_max >=NORMAL_DELTA_MIN && video_max != -1)
+	{
+		if (normal_max >= BK_MUSIC_MODE)
+			return video_max+2 > VIDEO_MODE_CLOCK_MAX ? VIDEO_MODE_CLOCK_MAX: video_max+2;
+		else
+			return video_max+1 > VIDEO_MODE_CLOCK_MAX ? VIDEO_MODE_CLOCK_MAX: video_max+1;
+		
+	}
+	else if (video_max != -1)
+		return video_max;
+	else if (normal_max != -1)
+	{
+		//have bk music mode request
+		if (normal_max > BK_MUSIC_MODE && !list_empty(&(g_rqst_list[BK_MUSIC_MODE].list)))
+			return normal_max+1 > NORMAL_MODE_CLOCK_MAX ? NORMAL_MODE_CLOCK_MAX:normal_max+1;
+		return normal_max;
+	}
+	else if (low_max != -1) 
+		return low_max;
+
+	return DEFAULT_MODE;	
+}
+
+
+static int ak98_freq_policy_rqst_mode(char *app_name)
+{
+	pid_t pid = task_tgid_vnr(current);
+	struct rqst_node *new_node;	
+	T_MODE_TYPE t_rqst_mode;
+
+	t_rqst_mode = get_mode_by_name(app_name);
+	PDEBUG("name: %s pid: %d  request  mode: %s\n", app_name, pid, get_mode_name(t_rqst_mode));
+
+	if ( (t_rqst_mode < LOW_IX) | (t_rqst_mode > HIGH_IX) )
+		return -EINVAL;
+	
+	new_node = kzalloc(sizeof(struct rqst_node), GFP_KERNEL);
+	if (new_node == NULL)
+		return -ENOMEM;
+	
+
+	//spin_lock(&freq_policy_lock);
+	down(&g_sem);
+	strcpy(new_node->app_info.appName,app_name);
+	new_node->app_info.pid = pid;
+	//reserved,  count of requesting this mode
+	g_rqst_list[t_rqst_mode].app_info.appName[0]++;
+	new_node->app_info.tag = g_tag_cnt++;
+
+	if (g_tag_cnt < 0)
+		g_tag_cnt = 100;
+	
+	list_add(&(new_node->list), &(g_rqst_list[t_rqst_mode].list));
+
+	judge_and_change();	
+	
+	//spin_unlock(&freq_policy_lock);
+	up(&g_sem);
+	return new_node->app_info.tag;
+}
+
+
+/* if tag == -1, then delete requests by pid
+  * else delete the requests by pid and tag
+  */
+static void ak98_freq_policy_rls_mode(int tag)
+{
+	pid_t pid = task_tgid_vnr(current);
+	int i;
+	struct list_head *pos, *n;
+	struct rqst_node *cur;
+	int del_flg = 0;
+			
+	//spin_lock(&freq_policy_lock);
+	
+	down(&g_sem);
+
+	/* delete mode requests of application whose pid is pid */
+	for (i=LOW_IX; i<= HIGH_IX; i++)
+	{
+		list_for_each_safe(pos, n, &(g_rqst_list[i].list))
+		{
+			cur = list_entry(pos, struct rqst_node, list);
+			if (cur->app_info.pid == pid && (tag == -1 || tag == cur->app_info.tag))
+			{
+				g_rqst_list[i].app_info.appName[0]--;
+				list_del(pos);
+				kfree(cur);
+				cur = NULL;
+				del_flg = 1;
+			}			
+		}
+	}
+
+	if (del_flg == 0)
+	{
+		//spin_unlock(&freq_policy_lock);	
+		up(&g_sem);
+		return;
+	}
+
+	PDEBUG("Release pid: %d  tag: %d\n", pid, tag);
+	g_target_mode = get_target_mode();
+
+	/* if not equal, g_target_mode must be lower than 
+	 * g_current_mode (thats to say: g_target_mode <= g_current_mode)
+	*/
+	PDEBUG("target mode: %s\n", get_mode_name(g_target_mode));
+	if (g_target_mode != g_current_mode)
+	{
+		cancel_delayed_work(&g_work);
+		queue_delayed_work(g_freq_policy_wq, &g_work,
+				      msecs_to_jiffies(RELEASE_DELAY));
+		//del_timer(&change_timer);
+		//mod_timer(&change_timer, jiffies+ msecs_to_jiffies(RELEASE_DELAY));
+	}
+	
+	//spin_unlock(&freq_policy_lock);	
+	up(&g_sem);
+	
+}
+
+static T_MODE_TYPE get_mode_by_name(char *name)
+{
+	int i, n = ARRAY_SIZE(app_to_mode);
+	for (i=0; i<n; i++)
+	{
+		if (strcasecmp(name, app_to_mode[i].appName)==0)
+		{
+			return app_to_mode[i].mode;
+		}
+	}
+	return DEFAULT_MODE;
+}
+
+static int ak98_freq_policy_ioctl(struct inode *node, struct file *file, 
+	                          unsigned int cmd, unsigned long data)
+{
+	int ret = 0;
+	char app_name[MAX_NAME_LEN];
+
+	switch (cmd)
+	{
+		case REQUEST_MODE:
+			if (copy_from_user(app_name, (void __user *)data, sizeof(app_name)))
+				return -EFAULT;
+			
+			ret = ak98_freq_policy_rqst_mode(app_name);
+			break;
+		case RELEASE_MODE:
+			PDEBUG("release mode request whit tag %d\n", (int)data);
+			ak98_freq_policy_rls_mode(data);
+			break;
+		default:
+			return -EINVAL;
+			break;
+	}
+
+	return ret;
+}
+
+static ssize_t ak98_freq_policy_write(struct file *file, const char *buf,
+			      size_t count, loff_t * ppos)
+{
+	printk("not support write!\n");
+	return -ENOTTY;	
+}
+
+static int ak98_freq_policy_open(struct inode *inode, struct file *file)
+{	
+	return 0;
+}
+
+static int ak98_freq_policy_release(struct inode *inode, struct file *file)
+{
+	
+	ak98_freq_policy_rls_mode(-1);
+	return 0;
+}
+
+
+/*
+ *	The various file operations we support.
+ */
+static const struct file_operations freq_policy_fops = {
+      .owner	= THIS_MODULE,
+      .open		= ak98_freq_policy_open,
+      .release	= ak98_freq_policy_release,
+      .read		= ak98_freq_policy_read,
+      .write	= ak98_freq_policy_write,
+      .ioctl	= ak98_freq_policy_ioctl,
+};
+
+static struct miscdevice freq_policy_dev = {
+	.minor	= MISC_DYNAMIC_MINOR,
+	.name	= "rqstMode",
+	.fops	= &freq_policy_fops,
+	.mode	= S_IRWXO,
+};
+
+static int ak98_freq_policy_probe(struct platform_device *pdev)
+{	
+	int ret, i;
+
+	ret = misc_register(&freq_policy_dev);
+	if (ret) {
+		PDEBUG( "freq_policy: "
+		       "Unable to register misc device.\n");		
+		return ret;
+	}
+
+	for (i=LOW_IX; i<=HIGH_IX; i++)
+		INIT_LIST_HEAD(&(g_rqst_list[i].list));
+
+	g_current_mode = get_current_mode();
+	g_target_mode = LOWEST_MODE;
+	g_current_pll = get_pll_sel(g_current_mode);
+
+	INIT_DELAYED_WORK(&g_work, change_work);	
+	INIT_DELAYED_WORK(&g_hold_mode_work, hold_mode_work);	
+	
+	sema_init(&g_sem, 1);
+	PDEBUG("AK98 frequency conversion policy driver\n");
+	return 0;
+}
+
+
+static int __devexit ak98_freq_policy_remove(struct platform_device *pdev)
+{
+	int i;
+	struct rqst_node *cur;
+	struct list_head *pos, *n;
+	misc_deregister(&freq_policy_dev);
+	/* delete mode requests of application whose pid is pid */
+	for (i=LOW_IX; i<= HIGH_IX; i++)
+	{
+		list_for_each_safe(pos, n, &(g_rqst_list[i].list))
+		{
+			cur = list_entry(pos, struct rqst_node, list);			
+			list_del(pos);
+			kfree(cur);
+		}
+	}
+	return 0;
+}
+
+static struct platform_driver ak98_freq_policy_driver = {
+	.remove		= __devexit_p(ak98_freq_policy_remove),
+	.driver		= {
+	.name		= "freq_policy",
+	.owner		= THIS_MODULE,
+	},
+};
+
+static int __init ak98_freq_policy_init(void)
+{
+
+	g_freq_policy_wq = create_singlethread_workqueue("freq_policy_wq");
+	if (!g_freq_policy_wq)
+		return -ENOMEM;
+	return platform_driver_probe(&ak98_freq_policy_driver, ak98_freq_policy_probe);
+}
+subsys_initcall(ak98_freq_policy_init);
+
+static void __exit ak98_freq_policy_exit(void)
+{
+	if (g_freq_policy_wq)
+			destroy_workqueue(g_freq_policy_wq);
+	platform_driver_unregister(&ak98_freq_policy_driver);
+}
+module_exit(ak98_freq_policy_exit);
+
+MODULE_AUTHOR("Wenyong Zhou  ANYKA Inc");
+MODULE_DESCRIPTION("Frequency conversion policy driver for AK98");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:freq_policy");
diff --git a/drivers/power/power_supply_core.c b/drivers/power/power_supply_core.c
index cce75b40b43..381460a1ca9 100644
--- a/drivers/power/power_supply_core.c
+++ b/drivers/power/power_supply_core.c
@@ -38,23 +38,40 @@ static int __power_supply_changed_work(struct device *dev, void *data)
 
 static void power_supply_changed_work(struct work_struct *work)
 {
+	unsigned long flags;
 	struct power_supply *psy = container_of(work, struct power_supply,
 						changed_work);
 
 	dev_dbg(psy->dev, "%s\n", __func__);
 
-	class_for_each_device(power_supply_class, NULL, psy,
-			      __power_supply_changed_work);
+	spin_lock_irqsave(&psy->changed_lock, flags);
+	if (psy->changed) {
+		psy->changed = false;
+		spin_unlock_irqrestore(&psy->changed_lock, flags);
 
-	power_supply_update_leds(psy);
+		class_for_each_device(power_supply_class, NULL, psy,
+				      __power_supply_changed_work);
 
-	kobject_uevent(&psy->dev->kobj, KOBJ_CHANGE);
+		power_supply_update_leds(psy);
+
+		kobject_uevent(&psy->dev->kobj, KOBJ_CHANGE);
+		spin_lock_irqsave(&psy->changed_lock, flags);
+	}
+	if (!psy->changed)
+		wake_unlock(&psy->work_wake_lock);
+	spin_unlock_irqrestore(&psy->changed_lock, flags);
 }
 
 void power_supply_changed(struct power_supply *psy)
 {
+	unsigned long flags;
+
 	dev_dbg(psy->dev, "%s\n", __func__);
 
+	spin_lock_irqsave(&psy->changed_lock, flags);
+	psy->changed = true;
+	wake_lock(&psy->work_wake_lock);
+	spin_unlock_irqrestore(&psy->changed_lock, flags);
 	schedule_work(&psy->changed_work);
 }
 EXPORT_SYMBOL_GPL(power_supply_changed);
@@ -156,6 +173,8 @@ int power_supply_register(struct device *parent, struct power_supply *psy)
 	}
 
 	INIT_WORK(&psy->changed_work, power_supply_changed_work);
+	spin_lock_init(&psy->changed_lock);
+	wake_lock_init(&psy->work_wake_lock, WAKE_LOCK_SUSPEND, "power-supply");
 
 	rc = power_supply_create_attrs(psy);
 	if (rc)
@@ -172,6 +191,7 @@ int power_supply_register(struct device *parent, struct power_supply *psy)
 create_triggers_failed:
 	power_supply_remove_attrs(psy);
 create_attrs_failed:
+	wake_lock_destroy(&psy->work_wake_lock);
 	device_unregister(psy->dev);
 dev_create_failed:
 success:
@@ -184,6 +204,7 @@ void power_supply_unregister(struct power_supply *psy)
 	flush_scheduled_work();
 	power_supply_remove_triggers(psy);
 	power_supply_remove_attrs(psy);
+	wake_lock_destroy(&psy->work_wake_lock);
 	device_unregister(psy->dev);
 }
 EXPORT_SYMBOL_GPL(power_supply_unregister);
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3c20dae43ce..9a33cd8d24b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -109,6 +109,24 @@ config RTC_INTF_DEV_UIE_EMUL
 	  clock several times per second, please enable this option
 	  only if you know that you really need it.
 
+config RTC_INTF_ALARM
+	bool "Android alarm driver"
+	depends on RTC_CLASS
+	default y
+	help
+	  Provides non-wakeup and rtc backed wakeup alarms based on rtc or
+	  elapsed realtime, and a non-wakeup alarm on the monotonic clock.
+	  Also provides an interface to set the wall time which must be used
+	  for elapsed realtime to work.
+
+config RTC_INTF_ALARM_DEV
+	bool "Android alarm device"
+	depends on RTC_INTF_ALARM
+	default y
+	help
+	  Exports the alarm interface to user-space.
+
+
 config RTC_DRV_TEST
 	tristate "Test driver/device"
 	help
@@ -827,4 +845,11 @@ config RTC_DRV_PCAP
 	  If you say Y here you will get support for the RTC found on
 	  the PCAP2 ASIC used on some Motorola phones.
 
+config RTC_DRV_AK98
+	tristate "AK98 RTC"
+	depends on ARCH_AK98
+	help
+           If you say Y here you will get support for the onboard
+           AK98 RTC.
+
 endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index aa3fbd5517a..10c40ea23d8 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_RTC_HCTOSYS)	+= hctosys.o
 obj-$(CONFIG_RTC_CLASS)		+= rtc-core.o
 rtc-core-y			:= class.o interface.o
 
+obj-$(CONFIG_RTC_INTF_ALARM) += alarm.o
+obj-$(CONFIG_RTC_INTF_ALARM_DEV) += alarm-dev.o
 rtc-core-$(CONFIG_RTC_INTF_DEV)	+= rtc-dev.o
 rtc-core-$(CONFIG_RTC_INTF_PROC) += rtc-proc.o
 rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
@@ -85,3 +87,4 @@ obj-$(CONFIG_RTC_DRV_VR41XX)	+= rtc-vr41xx.o
 obj-$(CONFIG_RTC_DRV_WM831X)	+= rtc-wm831x.o
 obj-$(CONFIG_RTC_DRV_WM8350)	+= rtc-wm8350.o
 obj-$(CONFIG_RTC_DRV_X1205)	+= rtc-x1205.o
+obj-$(CONFIG_RTC_DRV_AK98)	+= rtc-ak98.o
diff --git a/drivers/rtc/alarm-dev.c b/drivers/rtc/alarm-dev.c
new file mode 100644
index 00000000000..686e6f7ed48
--- /dev/null
+++ b/drivers/rtc/alarm-dev.c
@@ -0,0 +1,286 @@
+/* drivers/rtc/alarm-dev.c
+ *
+ * Copyright (C) 2007-2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/mach/time.h>
+#include <linux/android_alarm.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/uaccess.h>
+#include <linux/wakelock.h>
+
+#define ANDROID_ALARM_PRINT_INFO (1U << 0)
+#define ANDROID_ALARM_PRINT_IO (1U << 1)
+#define ANDROID_ALARM_PRINT_INT (1U << 2)
+
+static int debug_mask = ANDROID_ALARM_PRINT_INFO;
+module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+#define pr_alarm(debug_level_mask, args...) \
+	do { \
+		if (debug_mask & ANDROID_ALARM_PRINT_##debug_level_mask) { \
+			pr_info(args); \
+		} \
+	} while (0)
+
+#define ANDROID_ALARM_WAKEUP_MASK ( \
+	ANDROID_ALARM_RTC_WAKEUP_MASK | \
+	ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
+
+/* support old usespace code */
+#define ANDROID_ALARM_SET_OLD               _IOW('a', 2, time_t) /* set alarm */
+#define ANDROID_ALARM_SET_AND_WAIT_OLD      _IOW('a', 3, time_t)
+
+static int alarm_opened;
+static DEFINE_SPINLOCK(alarm_slock);
+static struct wake_lock alarm_wake_lock;
+static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue);
+static uint32_t alarm_pending;
+static uint32_t alarm_enabled;
+static uint32_t wait_pending;
+
+static struct alarm alarms[ANDROID_ALARM_TYPE_COUNT];
+
+static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	int rv = 0;
+	unsigned long flags;
+	struct timespec new_alarm_time;
+	struct timespec new_rtc_time;
+	struct timespec tmp_time;
+	enum android_alarm_type alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd);
+	uint32_t alarm_type_mask = 1U << alarm_type;
+
+	if (alarm_type >= ANDROID_ALARM_TYPE_COUNT)
+		return -EINVAL;
+
+	if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) {
+		if ((file->f_flags & O_ACCMODE) == O_RDONLY)
+			return -EPERM;
+		if (file->private_data == NULL &&
+		    cmd != ANDROID_ALARM_SET_RTC) {
+			spin_lock_irqsave(&alarm_slock, flags);
+			if (alarm_opened) {
+				spin_unlock_irqrestore(&alarm_slock, flags);
+				return -EBUSY;
+			}
+			alarm_opened = 1;
+			file->private_data = (void *)1;
+			spin_unlock_irqrestore(&alarm_slock, flags);
+		}
+	}
+
+	switch (ANDROID_ALARM_BASE_CMD(cmd)) {
+	case ANDROID_ALARM_CLEAR(0):
+		spin_lock_irqsave(&alarm_slock, flags);
+		pr_alarm(IO, "alarm %d clear\n", alarm_type);
+		alarm_try_to_cancel(&alarms[alarm_type]);
+		if (alarm_pending) {
+			alarm_pending &= ~alarm_type_mask;
+			if (!alarm_pending && !wait_pending)
+				wake_unlock(&alarm_wake_lock);
+		}
+		alarm_enabled &= ~alarm_type_mask;
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		break;
+
+	case ANDROID_ALARM_SET_OLD:
+	case ANDROID_ALARM_SET_AND_WAIT_OLD:
+		if (get_user(new_alarm_time.tv_sec, (int __user *)arg)) {
+			rv = -EFAULT;
+			goto err1;
+		}
+		new_alarm_time.tv_nsec = 0;
+		goto from_old_alarm_set;
+
+	case ANDROID_ALARM_SET_AND_WAIT(0):
+	case ANDROID_ALARM_SET(0):
+		if (copy_from_user(&new_alarm_time, (void __user *)arg,
+		    sizeof(new_alarm_time))) {
+			rv = -EFAULT;
+			goto err1;
+		}
+from_old_alarm_set:
+		spin_lock_irqsave(&alarm_slock, flags);
+		pr_alarm(IO, "alarm %d set %ld.%09ld\n", alarm_type,
+			new_alarm_time.tv_sec, new_alarm_time.tv_nsec);
+		alarm_enabled |= alarm_type_mask;
+		alarm_start_range(&alarms[alarm_type],
+			timespec_to_ktime(new_alarm_time),
+			timespec_to_ktime(new_alarm_time));
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		if (ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0)
+		    && cmd != ANDROID_ALARM_SET_AND_WAIT_OLD)
+			break;
+		/* fall though */
+	case ANDROID_ALARM_WAIT:
+		spin_lock_irqsave(&alarm_slock, flags);
+		pr_alarm(IO, "alarm wait\n");
+		if (!alarm_pending && wait_pending) {
+			wake_unlock(&alarm_wake_lock);
+			wait_pending = 0;
+		}
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		rv = wait_event_interruptible(alarm_wait_queue, alarm_pending);
+		if (rv)
+			goto err1;
+		spin_lock_irqsave(&alarm_slock, flags);
+		rv = alarm_pending;
+		wait_pending = 1;
+		alarm_pending = 0;
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		break;
+	case ANDROID_ALARM_SET_RTC:
+		if (copy_from_user(&new_rtc_time, (void __user *)arg,
+		    sizeof(new_rtc_time))) {
+			rv = -EFAULT;
+			goto err1;
+		}
+		rv = alarm_set_rtc(new_rtc_time);
+		spin_lock_irqsave(&alarm_slock, flags);
+		alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK;
+		wake_up(&alarm_wait_queue);
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		if (rv < 0)
+			goto err1;
+		break;
+	case ANDROID_ALARM_GET_TIME(0):
+		switch (alarm_type) {
+		case ANDROID_ALARM_RTC_WAKEUP:
+		case ANDROID_ALARM_RTC:
+			getnstimeofday(&tmp_time);
+			break;
+		case ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP:
+		case ANDROID_ALARM_ELAPSED_REALTIME:
+			tmp_time =
+				ktime_to_timespec(alarm_get_elapsed_realtime());
+			break;
+		case ANDROID_ALARM_TYPE_COUNT:
+		case ANDROID_ALARM_SYSTEMTIME:
+			ktime_get_ts(&tmp_time);
+			break;
+		}
+		if (copy_to_user((void __user *)arg, &tmp_time,
+		    sizeof(tmp_time))) {
+			rv = -EFAULT;
+			goto err1;
+		}
+		break;
+
+	default:
+		rv = -EINVAL;
+		goto err1;
+	}
+err1:
+	return rv;
+}
+
+static int alarm_open(struct inode *inode, struct file *file)
+{
+	file->private_data = NULL;
+	return 0;
+}
+
+static int alarm_release(struct inode *inode, struct file *file)
+{
+	int i;
+	unsigned long flags;
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	if (file->private_data != 0) {
+		for (i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) {
+			uint32_t alarm_type_mask = 1U << i;
+			if (alarm_enabled & alarm_type_mask) {
+				pr_alarm(INFO, "alarm_release: clear alarm, "
+					"pending %d\n",
+					!!(alarm_pending & alarm_type_mask));
+				alarm_enabled &= ~alarm_type_mask;
+			}
+			spin_unlock_irqrestore(&alarm_slock, flags);
+			alarm_cancel(&alarms[i]);
+			spin_lock_irqsave(&alarm_slock, flags);
+		}
+		if (alarm_pending | wait_pending) {
+			if (alarm_pending)
+				pr_alarm(INFO, "alarm_release: clear "
+					"pending alarms %x\n", alarm_pending);
+			wake_unlock(&alarm_wake_lock);
+			wait_pending = 0;
+			alarm_pending = 0;
+		}
+		alarm_opened = 0;
+	}
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	return 0;
+}
+
+static void alarm_triggered(struct alarm *alarm)
+{
+	unsigned long flags;
+	uint32_t alarm_type_mask = 1U << alarm->type;
+
+	pr_alarm(INT, "alarm_triggered type %d\n", alarm->type);
+	spin_lock_irqsave(&alarm_slock, flags);
+	if (alarm_enabled & alarm_type_mask) {
+		wake_lock_timeout(&alarm_wake_lock, 5 * HZ);
+		alarm_enabled &= ~alarm_type_mask;
+		alarm_pending |= alarm_type_mask;
+		wake_up(&alarm_wait_queue);
+	}
+	spin_unlock_irqrestore(&alarm_slock, flags);
+}
+
+static const struct file_operations alarm_fops = {
+	.owner = THIS_MODULE,
+	.unlocked_ioctl = alarm_ioctl,
+	.open = alarm_open,
+	.release = alarm_release,
+};
+
+static struct miscdevice alarm_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "alarm",
+	.fops = &alarm_fops,
+};
+
+static int __init alarm_dev_init(void)
+{
+	int err;
+	int i;
+
+	err = misc_register(&alarm_device);
+	if (err)
+		return err;
+
+	for (i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++)
+		alarm_init(&alarms[i], i, alarm_triggered);
+	wake_lock_init(&alarm_wake_lock, WAKE_LOCK_SUSPEND, "alarm");
+
+	return 0;
+}
+
+static void  __exit alarm_dev_exit(void)
+{
+	misc_deregister(&alarm_device);
+	wake_lock_destroy(&alarm_wake_lock);
+}
+
+module_init(alarm_dev_init);
+module_exit(alarm_dev_exit);
+
diff --git a/drivers/rtc/alarm.c b/drivers/rtc/alarm.c
new file mode 100644
index 00000000000..7232a538d39
--- /dev/null
+++ b/drivers/rtc/alarm.c
@@ -0,0 +1,586 @@
+/* drivers/rtc/alarm.c
+ *
+ * Copyright (C) 2007-2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/mach/time.h>
+#include <linux/android_alarm.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/wakelock.h>
+
+#define ANDROID_ALARM_PRINT_ERROR (1U << 0)
+#define ANDROID_ALARM_PRINT_INIT_STATUS (1U << 1)
+#define ANDROID_ALARM_PRINT_TSET (1U << 2)
+#define ANDROID_ALARM_PRINT_CALL (1U << 3)
+#define ANDROID_ALARM_PRINT_SUSPEND (1U << 4)
+#define ANDROID_ALARM_PRINT_INT (1U << 5)
+#define ANDROID_ALARM_PRINT_FLOW (1U << 6)
+
+static int debug_mask = ANDROID_ALARM_PRINT_ERROR | \
+			ANDROID_ALARM_PRINT_INIT_STATUS;
+module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+#define pr_alarm(debug_level_mask, args...) \
+	do { \
+		if (debug_mask & ANDROID_ALARM_PRINT_##debug_level_mask) { \
+			pr_info(args); \
+		} \
+	} while (0)
+
+#define ANDROID_ALARM_WAKEUP_MASK ( \
+	ANDROID_ALARM_RTC_WAKEUP_MASK | \
+	ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
+
+/* support old usespace code */
+#define ANDROID_ALARM_SET_OLD               _IOW('a', 2, time_t) /* set alarm */
+#define ANDROID_ALARM_SET_AND_WAIT_OLD      _IOW('a', 3, time_t)
+
+struct alarm_queue {
+	struct rb_root alarms;
+	struct rb_node *first;
+	struct hrtimer timer;
+	ktime_t delta;
+	bool stopped;
+	ktime_t stopped_time;
+};
+
+static struct rtc_device *alarm_rtc_dev;
+static DEFINE_SPINLOCK(alarm_slock);
+static DEFINE_MUTEX(alarm_setrtc_mutex);
+static struct wake_lock alarm_rtc_wake_lock;
+static struct platform_device *alarm_platform_dev;
+struct alarm_queue alarms[ANDROID_ALARM_TYPE_COUNT];
+static bool suspended;
+
+static void update_timer_locked(struct alarm_queue *base, bool head_removed)
+{
+	struct alarm *alarm;
+	bool is_wakeup = base == &alarms[ANDROID_ALARM_RTC_WAKEUP] ||
+			base == &alarms[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP];
+
+	if (base->stopped) {
+		pr_alarm(FLOW, "changed alarm while setting the wall time\n");
+		return;
+	}
+
+	if (is_wakeup && !suspended && head_removed)
+		wake_unlock(&alarm_rtc_wake_lock);
+
+	if (!base->first)
+		return;
+
+	alarm = container_of(base->first, struct alarm, node);
+
+	pr_alarm(FLOW, "selected alarm, type %d, func %pF at %lld\n",
+		alarm->type, alarm->function, ktime_to_ns(alarm->expires));
+
+	if (is_wakeup && suspended) {
+		pr_alarm(FLOW, "changed alarm while suspened\n");
+		wake_lock_timeout(&alarm_rtc_wake_lock, 1 * HZ);
+		return;
+	}
+
+	hrtimer_try_to_cancel(&base->timer);
+	base->timer._expires = ktime_add(base->delta, alarm->expires);
+	base->timer._softexpires = ktime_add(base->delta, alarm->softexpires);
+	hrtimer_start_expires(&base->timer, HRTIMER_MODE_ABS);
+}
+
+static void alarm_enqueue_locked(struct alarm *alarm)
+{
+	struct alarm_queue *base = &alarms[alarm->type];
+	struct rb_node **link = &base->alarms.rb_node;
+	struct rb_node *parent = NULL;
+	struct alarm *entry;
+	int leftmost = 1;
+
+	pr_alarm(FLOW, "added alarm, type %d, func %pF at %lld\n",
+		alarm->type, alarm->function, ktime_to_ns(alarm->expires));
+
+	if (base->first == &alarm->node)
+		base->first = rb_next(&alarm->node);
+	if (!RB_EMPTY_NODE(&alarm->node)) {
+		rb_erase(&alarm->node, &base->alarms);
+		RB_CLEAR_NODE(&alarm->node);
+	}
+
+	while (*link) {
+		parent = *link;
+		entry = rb_entry(parent, struct alarm, node);
+		/*
+		* We dont care about collisions. Nodes with
+		* the same expiry time stay together.
+		*/
+		if (alarm->expires.tv64 < entry->expires.tv64) {
+			link = &(*link)->rb_left;
+		} else {
+			link = &(*link)->rb_right;
+			leftmost = 0;
+		}
+	}
+	if (leftmost) {
+		base->first = &alarm->node;
+		update_timer_locked(base, false);
+	}
+
+	rb_link_node(&alarm->node, parent, link);
+	rb_insert_color(&alarm->node, &base->alarms);
+}
+
+/**
+ * alarm_init - initialize an alarm
+ * @alarm:	the alarm to be initialized
+ * @type:	the alarm type to be used
+ * @function:	alarm callback function
+ */
+void alarm_init(struct alarm *alarm,
+	enum android_alarm_type type, void (*function)(struct alarm *))
+{
+	RB_CLEAR_NODE(&alarm->node);
+	alarm->type = type;
+	alarm->function = function;
+
+	pr_alarm(FLOW, "created alarm, type %d, func %pF\n", type, function);
+}
+
+
+/**
+ * alarm_start_range - (re)start an alarm
+ * @alarm:	the alarm to be added
+ * @start:	earliest expiry time
+ * @end:	expiry time
+ */
+void alarm_start_range(struct alarm *alarm, ktime_t start, ktime_t end)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	alarm->softexpires = start;
+	alarm->expires = end;
+	alarm_enqueue_locked(alarm);
+	spin_unlock_irqrestore(&alarm_slock, flags);
+}
+
+/**
+ * alarm_try_to_cancel - try to deactivate an alarm
+ * @alarm:	alarm to stop
+ *
+ * Returns:
+ *  0 when the alarm was not active
+ *  1 when the alarm was active
+ * -1 when the alarm may currently be excuting the callback function and
+ *    cannot be stopped (it may also be inactive)
+ */
+int alarm_try_to_cancel(struct alarm *alarm)
+{
+	struct alarm_queue *base = &alarms[alarm->type];
+	unsigned long flags;
+	bool first = false;
+	int ret = 0;
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	if (!RB_EMPTY_NODE(&alarm->node)) {
+		pr_alarm(FLOW, "canceled alarm, type %d, func %pF at %lld\n",
+			alarm->type, alarm->function,
+			ktime_to_ns(alarm->expires));
+		ret = 1;
+		if (base->first == &alarm->node) {
+			base->first = rb_next(&alarm->node);
+			first = true;
+		}
+		rb_erase(&alarm->node, &base->alarms);
+		RB_CLEAR_NODE(&alarm->node);
+		if (first)
+			update_timer_locked(base, true);
+	} else
+		pr_alarm(FLOW, "tried to cancel alarm, type %d, func %pF\n",
+			alarm->type, alarm->function);
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	if (!ret && hrtimer_callback_running(&base->timer))
+		ret = -1;
+	return ret;
+}
+
+/**
+ * alarm_cancel - cancel an alarm and wait for the handler to finish.
+ * @alarm:	the alarm to be cancelled
+ *
+ * Returns:
+ *  0 when the alarm was not active
+ *  1 when the alarm was active
+ */
+int alarm_cancel(struct alarm *alarm)
+{
+	for (;;) {
+		int ret = alarm_try_to_cancel(alarm);
+		if (ret >= 0)
+			return ret;
+		cpu_relax();
+	}
+}
+
+/**
+ * alarm_set_rtc - set the kernel and rtc walltime
+ * @new_time:	timespec value containing the new time
+ */
+int alarm_set_rtc(struct timespec new_time)
+{
+	int i;
+	int ret;
+	unsigned long flags;
+	struct rtc_time rtc_new_rtc_time;
+	struct timespec tmp_time;
+
+	rtc_time_to_tm(new_time.tv_sec, &rtc_new_rtc_time);
+
+	pr_alarm(TSET, "set rtc %ld %ld - rtc %02d:%02d:%02d %02d/%02d/%04d\n",
+		new_time.tv_sec, new_time.tv_nsec,
+		rtc_new_rtc_time.tm_hour, rtc_new_rtc_time.tm_min,
+		rtc_new_rtc_time.tm_sec, rtc_new_rtc_time.tm_mon + 1,
+		rtc_new_rtc_time.tm_mday,
+		rtc_new_rtc_time.tm_year + 1900);
+
+	mutex_lock(&alarm_setrtc_mutex);
+	spin_lock_irqsave(&alarm_slock, flags);
+	wake_lock(&alarm_rtc_wake_lock);
+	getnstimeofday(&tmp_time);
+	for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
+		hrtimer_try_to_cancel(&alarms[i].timer);
+		alarms[i].stopped = true;
+		alarms[i].stopped_time = timespec_to_ktime(tmp_time);
+	}
+	alarms[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].delta =
+		alarms[ANDROID_ALARM_ELAPSED_REALTIME].delta =
+		ktime_sub(alarms[ANDROID_ALARM_ELAPSED_REALTIME].delta,
+			timespec_to_ktime(timespec_sub(tmp_time, new_time)));
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	ret = do_settimeofday(&new_time);
+	spin_lock_irqsave(&alarm_slock, flags);
+	for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
+		alarms[i].stopped = false;
+		update_timer_locked(&alarms[i], false);
+	}
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	if (ret < 0) {
+		pr_alarm(ERROR, "alarm_set_rtc: Failed to set time\n");
+		goto err;
+	}
+	if (!alarm_rtc_dev) {
+		pr_alarm(ERROR,
+			"alarm_set_rtc: no RTC, time will be lost on reboot\n");
+		goto err;
+	}
+	ret = rtc_set_time(alarm_rtc_dev, &rtc_new_rtc_time);
+	if (ret < 0)
+		pr_alarm(ERROR, "alarm_set_rtc: "
+			"Failed to set RTC, time will be lost on reboot\n");
+err:
+	wake_unlock(&alarm_rtc_wake_lock);
+	mutex_unlock(&alarm_setrtc_mutex);
+	return ret;
+}
+
+/**
+ * alarm_get_elapsed_realtime - get the elapsed real time in ktime_t format
+ *
+ * returns the time in ktime_t format
+ */
+ktime_t alarm_get_elapsed_realtime(void)
+{
+	ktime_t now;
+	unsigned long flags;
+	struct alarm_queue *base = &alarms[ANDROID_ALARM_ELAPSED_REALTIME];
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	now = base->stopped ? base->stopped_time : ktime_get_real();
+	now = ktime_sub(now, base->delta);
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	return now;
+}
+
+static enum hrtimer_restart alarm_timer_triggered(struct hrtimer *timer)
+{
+	struct alarm_queue *base;
+	struct alarm *alarm;
+	unsigned long flags;
+	ktime_t now;
+
+	spin_lock_irqsave(&alarm_slock, flags);
+
+	base = container_of(timer, struct alarm_queue, timer);
+	now = base->stopped ? base->stopped_time : hrtimer_cb_get_time(timer);
+	now = ktime_sub(now, base->delta);
+
+	pr_alarm(INT, "alarm_timer_triggered type %d at %lld\n",
+		base - alarms, ktime_to_ns(now));
+
+	while (base->first) {
+		alarm = container_of(base->first, struct alarm, node);
+		if (alarm->softexpires.tv64 > now.tv64) {
+			pr_alarm(FLOW, "don't call alarm, %pF, %lld (s %lld)\n",
+				alarm->function, ktime_to_ns(alarm->expires),
+				ktime_to_ns(alarm->softexpires));
+			break;
+		}
+		base->first = rb_next(&alarm->node);
+		rb_erase(&alarm->node, &base->alarms);
+		RB_CLEAR_NODE(&alarm->node);
+		pr_alarm(CALL, "call alarm, type %d, func %pF, %lld (s %lld)\n",
+			alarm->type, alarm->function,
+			ktime_to_ns(alarm->expires),
+			ktime_to_ns(alarm->softexpires));
+		spin_unlock_irqrestore(&alarm_slock, flags);
+		alarm->function(alarm);
+		spin_lock_irqsave(&alarm_slock, flags);
+	}
+	if (!base->first)
+		pr_alarm(FLOW, "no more alarms of type %d\n", base - alarms);
+	update_timer_locked(base, true);
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	return HRTIMER_NORESTART;
+}
+
+static void alarm_triggered_func(void *p)
+{
+	struct rtc_device *rtc = alarm_rtc_dev;
+	if (!(rtc->irq_data & RTC_AF))
+		return;
+	pr_alarm(INT, "rtc alarm triggered\n");
+	wake_lock_timeout(&alarm_rtc_wake_lock, 1 * HZ);
+}
+
+static int alarm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	int                 err = 0;
+	unsigned long       flags;
+	struct rtc_wkalrm   rtc_alarm;
+	struct rtc_time     rtc_current_rtc_time;
+	unsigned long       rtc_current_time;
+	unsigned long       rtc_alarm_time;
+	struct timespec     rtc_current_timespec;
+	struct timespec     rtc_delta;
+	struct alarm_queue *wakeup_queue = NULL;
+	struct alarm_queue *tmp_queue = NULL;
+
+	pr_alarm(SUSPEND, "alarm_suspend(%p, %d)\n", pdev, state.event);
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	suspended = true;
+	spin_unlock_irqrestore(&alarm_slock, flags);
+
+	hrtimer_cancel(&alarms[ANDROID_ALARM_RTC_WAKEUP].timer);
+	hrtimer_cancel(&alarms[
+			ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK].timer);
+
+	tmp_queue = &alarms[ANDROID_ALARM_RTC_WAKEUP];
+	if (tmp_queue->first)
+		wakeup_queue = tmp_queue;
+	tmp_queue = &alarms[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP];
+	if (tmp_queue->first && (!wakeup_queue ||
+				hrtimer_get_expires(&tmp_queue->timer).tv64 <
+				hrtimer_get_expires(&wakeup_queue->timer).tv64))
+		wakeup_queue = tmp_queue;
+	if (wakeup_queue) {
+		rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
+		rtc_current_timespec.tv_nsec = 0;
+		rtc_tm_to_time(&rtc_current_rtc_time,
+			       &rtc_current_timespec.tv_sec);
+		save_time_delta(&rtc_delta, &rtc_current_timespec);
+
+		rtc_alarm_time = timespec_sub(ktime_to_timespec(
+			hrtimer_get_expires(&wakeup_queue->timer)),
+			rtc_delta).tv_sec;
+
+		rtc_time_to_tm(rtc_alarm_time, &rtc_alarm.time);
+		rtc_alarm.enabled = 1;
+		rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
+		rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
+		rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_time);
+		pr_alarm(SUSPEND,
+			"rtc alarm set at %ld, now %ld, rtc delta %ld.%09ld\n",
+			rtc_alarm_time, rtc_current_time,
+			rtc_delta.tv_sec, rtc_delta.tv_nsec);
+		if (rtc_current_time + 1 >= rtc_alarm_time) {
+			pr_alarm(SUSPEND, "alarm about to go off\n");
+			memset(&rtc_alarm, 0, sizeof(rtc_alarm));
+			rtc_alarm.enabled = 0;
+			rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
+
+			spin_lock_irqsave(&alarm_slock, flags);
+			suspended = false;
+			wake_lock_timeout(&alarm_rtc_wake_lock, 2 * HZ);
+			update_timer_locked(&alarms[ANDROID_ALARM_RTC_WAKEUP],
+									false);
+			update_timer_locked(&alarms[
+				ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP], false);
+			err = -EBUSY;
+			spin_unlock_irqrestore(&alarm_slock, flags);
+		}
+	}
+	return err;
+}
+
+static int alarm_resume(struct platform_device *pdev)
+{
+	struct rtc_wkalrm alarm;
+	unsigned long       flags;
+
+	pr_alarm(SUSPEND, "alarm_resume(%p)\n", pdev);
+
+	memset(&alarm, 0, sizeof(alarm));
+	alarm.enabled = 0;
+	rtc_set_alarm(alarm_rtc_dev, &alarm);
+
+	spin_lock_irqsave(&alarm_slock, flags);
+	suspended = false;
+	update_timer_locked(&alarms[ANDROID_ALARM_RTC_WAKEUP], false);
+	update_timer_locked(&alarms[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP],
+									false);
+	spin_unlock_irqrestore(&alarm_slock, flags);
+
+	return 0;
+}
+
+static struct rtc_task alarm_rtc_task = {
+	.func = alarm_triggered_func
+};
+
+static int rtc_alarm_add_device(struct device *dev,
+				struct class_interface *class_intf)
+{
+	int err;
+	struct rtc_device *rtc = to_rtc_device(dev);
+
+	mutex_lock(&alarm_setrtc_mutex);
+
+	if (alarm_rtc_dev) {
+		err = -EBUSY;
+		goto err1;
+	}
+
+	alarm_platform_dev =
+		platform_device_register_simple("alarm", -1, NULL, 0);
+	if (IS_ERR(alarm_platform_dev)) {
+		err = PTR_ERR(alarm_platform_dev);
+		goto err2;
+	}
+	err = rtc_irq_register(rtc, &alarm_rtc_task);
+	if (err)
+		goto err3;
+	alarm_rtc_dev = rtc;
+	pr_alarm(INIT_STATUS, "using rtc device, %s, for alarms", rtc->name);
+	mutex_unlock(&alarm_setrtc_mutex);
+
+	return 0;
+
+err3:
+	platform_device_unregister(alarm_platform_dev);
+err2:
+err1:
+	mutex_unlock(&alarm_setrtc_mutex);
+	return err;
+}
+
+static void rtc_alarm_remove_device(struct device *dev,
+				    struct class_interface *class_intf)
+{
+	if (dev == &alarm_rtc_dev->dev) {
+		pr_alarm(INIT_STATUS, "lost rtc device for alarms");
+		rtc_irq_unregister(alarm_rtc_dev, &alarm_rtc_task);
+		platform_device_unregister(alarm_platform_dev);
+		alarm_rtc_dev = NULL;
+	}
+}
+
+static struct class_interface rtc_alarm_interface = {
+	.add_dev = &rtc_alarm_add_device,
+	.remove_dev = &rtc_alarm_remove_device,
+};
+
+static struct platform_driver alarm_driver = {
+	.suspend = alarm_suspend,
+	.resume = alarm_resume,
+	.driver = {
+		.name = "alarm"
+	}
+};
+
+static int __init alarm_late_init(void)
+{
+	unsigned long   flags;
+	struct timespec tmp_time, system_time;
+
+	/* this needs to run after the rtc is read at boot */
+	spin_lock_irqsave(&alarm_slock, flags);
+	/* We read the current rtc and system time so we can later calulate
+	 * elasped realtime to be (boot_systemtime + rtc - boot_rtc) ==
+	 * (rtc - (boot_rtc - boot_systemtime))
+	 */
+	getnstimeofday(&tmp_time);
+	ktime_get_ts(&system_time);
+	alarms[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].delta =
+		alarms[ANDROID_ALARM_ELAPSED_REALTIME].delta =
+			timespec_to_ktime(timespec_sub(tmp_time, system_time));
+
+	spin_unlock_irqrestore(&alarm_slock, flags);
+	return 0;
+}
+
+static int __init alarm_driver_init(void)
+{
+	int err;
+	int i;
+
+	for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
+		hrtimer_init(&alarms[i].timer,
+				CLOCK_REALTIME, HRTIMER_MODE_ABS);
+		alarms[i].timer.function = alarm_timer_triggered;
+	}
+	hrtimer_init(&alarms[ANDROID_ALARM_SYSTEMTIME].timer,
+		     CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+	alarms[ANDROID_ALARM_SYSTEMTIME].timer.function = alarm_timer_triggered;
+	err = platform_driver_register(&alarm_driver);
+	if (err < 0)
+		goto err1;
+	wake_lock_init(&alarm_rtc_wake_lock, WAKE_LOCK_SUSPEND, "alarm_rtc");
+	rtc_alarm_interface.class = rtc_class;
+	err = class_interface_register(&rtc_alarm_interface);
+	if (err < 0)
+		goto err2;
+
+	return 0;
+
+err2:
+	wake_lock_destroy(&alarm_rtc_wake_lock);
+	platform_driver_unregister(&alarm_driver);
+err1:
+	return err;
+}
+
+static void  __exit alarm_exit(void)
+{
+	class_interface_unregister(&rtc_alarm_interface);
+	wake_lock_destroy(&alarm_rtc_wake_lock);
+	platform_driver_unregister(&alarm_driver);
+}
+
+late_initcall(alarm_late_init);
+module_init(alarm_driver_init);
+module_exit(alarm_exit);
+
diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
index be5a6b73e60..2bc9ef37b46 100644
--- a/drivers/rtc/class.c
+++ b/drivers/rtc/class.c
@@ -40,25 +40,32 @@ static void rtc_device_release(struct device *dev)
  */
 
 static struct timespec	delta;
+static struct timespec	delta_delta;
 static time_t		oldtime;
 
 static int rtc_suspend(struct device *dev, pm_message_t mesg)
 {
 	struct rtc_device	*rtc = to_rtc_device(dev);
 	struct rtc_time		tm;
-	struct timespec		ts = current_kernel_time();
+	struct timespec		ts;
+	struct timespec		new_delta;
 
 	if (strcmp(dev_name(&rtc->dev), CONFIG_RTC_HCTOSYS_DEVICE) != 0)
 		return 0;
 
+	getnstimeofday(&ts);
 	rtc_read_time(rtc, &tm);
 	rtc_tm_to_time(&tm, &oldtime);
 
 	/* RTC precision is 1 second; adjust delta for avg 1/2 sec err */
-	set_normalized_timespec(&delta,
+	set_normalized_timespec(&new_delta,
 				ts.tv_sec - oldtime,
 				ts.tv_nsec - (NSEC_PER_SEC >> 1));
 
+	/* prevent 1/2 sec errors from accumulating */
+	delta_delta = timespec_sub(new_delta, delta);
+	if (delta_delta.tv_sec < -2 || delta_delta.tv_sec >= 2)
+		delta = new_delta;
 	return 0;
 }
 
@@ -78,6 +85,8 @@ static int rtc_resume(struct device *dev)
 		return 0;
 	}
 	rtc_tm_to_time(&tm, &newtime);
+	if (delta_delta.tv_sec < -1)
+		newtime++;
 	if (newtime <= oldtime) {
 		if (newtime < oldtime)
 			pr_debug("%s:  time travel!\n", dev_name(&rtc->dev));
diff --git a/drivers/rtc/rtc-ak88.c b/drivers/rtc/rtc-ak88.c
new file mode 100644
index 00000000000..766d5770c8c
--- /dev/null
+++ b/drivers/rtc/rtc-ak88.c
@@ -0,0 +1,622 @@
+/*
+ * drivers/rtc/rtc-ak880x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/clk.h>
+#include <linux/log2.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+
+#define AK88_RTC_CONF		(AK88_VA_SYSCTRL+0x50)
+#define AK88_RTC_DATA		(AK88_VA_SYSCTRL+0x54)
+
+#define SYSCTRL_INT_CTRL        (AK88_VA_SYSCTRL + 0x4C)
+#define AK88_RTC_READY	(1<<24)
+
+#define AK88_RTC_READ		(0x3<<17)
+#define AK88_RTC_WRITE	(0x2<<17)
+
+#define AK88_RTC_SECOND	(0x0)
+#define AK88_RTC_DAYHOUR	(0x1)
+#define AK88_ALARM_TIME1	(0x2)
+#define AK88_ALARM_TIME2	(0x3)
+#define AK88_WDT_TIMER1	(0x4)
+#define AK88_WDT_TIMER2	(0x5)
+#define AK88_RTC_REG_MAX	AK88_WDT_TIMER2
+
+#define RTC_WAKEUP_SIGNAL_ENABLE	(0x1<<1)
+#define RTC_WAKEUP_SIGNAL_CLEAR		(0x1<<0)
+#define RTC_WAKEUP_SIGNAL_LOWACTIVE	(0x1<<2)
+
+extern int rtc_year_days(unsigned int mday, unsigned int month, unsigned int year);
+static unsigned long base[] = { 4,5,6,0,2,3,4,5,0,1,2,3,5,6,0,1,3,4,5,6,1};
+static const unsigned short rtc_ydays[2][13] = {
+	/* Normal years */
+	{ 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 },
+	/* Leap years */
+	{ 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335, 366 }
+};
+
+static int ak880x_rtc_wakeup_enable(int en);
+static int alarm_year = 2009;
+static int alarm_day = 0;
+static int leap_year(int y)
+{
+	if( (y%4==0&&y%100!=0) || (y%400==0) )
+		return 1;
+	else
+		return 0;
+}
+
+
+/*
+ * When the RTC module begins to receive/send data, bit [24] of Interrupt Enable/Status
+ * Register of System Control Module (Add: 0x0800, 004C) is set to 0; and then this
+ * bit is set to 1 automatically to indicate that the data has been well received/sent
+ */
+static int inline ak880x_rtc_ready(void)
+{
+	return __raw_readl(SYSCTRL_INT_CTRL) & AK88_RTC_READY;
+}
+
+static void inline rtc_ready_irq_enable(int enable)
+{
+	unsigned long regval = __raw_readl(SYSCTRL_INT_CTRL);
+
+	if (enable)
+		__raw_writel(regval | (1<<8), SYSCTRL_INT_CTRL);
+	else
+		__raw_writel(regval & ~(1<<8), SYSCTRL_INT_CTRL);
+}
+
+#define RTC_MAX_TIMEOUT		20000	/* that's enough */
+
+unsigned int ak880x_rtc_read(unsigned int addr)
+{
+	unsigned long regval = 0;
+	unsigned int timeout = 0;
+
+	if (addr > AK88_RTC_REG_MAX)
+		return -1;
+
+	local_irq_disable();
+
+	rtc_ready_irq_enable(1);
+
+	regval  = __raw_readl(AK88_RTC_CONF);
+	regval  &= (~0x7ffff);
+	regval  |= (AK88_RTC_READ | (addr<<14));
+
+	__raw_writel(regval, AK88_RTC_CONF);
+
+	while (1) {
+		if (timeout > RTC_MAX_TIMEOUT) {
+			printk("%s: timeout, please check rtc clock\n", __FUNCTION__);
+			rtc_ready_irq_enable(0);
+			break;
+		}
+		timeout ++;
+
+		if (ak880x_rtc_ready()) {
+			rtc_ready_irq_enable(0);
+			break;
+		}
+	}
+
+	local_irq_enable();
+
+	udelay(1000/32+1);
+	regval = __raw_readl(AK88_RTC_DATA);
+	regval = (regval & 0x3fff);
+
+	return regval;
+}
+EXPORT_SYMBOL(ak880x_rtc_read);
+
+static unsigned int ak880x_rtc_write(unsigned int addr, unsigned int value)
+{
+	unsigned long regval = 0;
+	unsigned int timeout = 0;
+
+	if (addr > AK88_RTC_REG_MAX)
+		return -1;
+
+	local_irq_disable();
+
+	rtc_ready_irq_enable(1);
+
+	value &= 0x3fff;
+	regval  = __raw_readl(AK88_RTC_CONF);
+	regval  &= (~0x7ffff);
+	regval  |= (AK88_RTC_WRITE | (addr<<14) | value);
+
+	__raw_writel(regval, AK88_RTC_CONF);
+
+	while (1) {
+		if (timeout > RTC_MAX_TIMEOUT) {
+			printk("%s: timeout, please check rtc clock\n", __FUNCTION__);
+			rtc_ready_irq_enable(0);
+			return 1;
+		}
+		timeout ++;
+
+		if (ak880x_rtc_ready()) {
+			rtc_ready_irq_enable(0);
+			break;
+		}
+	}
+	local_irq_enable();
+
+	/* printk("write timeout: %d\n", timeout); */
+
+	return 0;
+}
+
+static inline void ak880x_rtc_int_clear(void) 
+{
+	unsigned int regval;
+
+	regval = ak880x_rtc_read(AK88_WDT_TIMER1);
+	regval &= ~0x1;
+	regval |= RTC_WAKEUP_SIGNAL_CLEAR;
+
+	ak880x_rtc_write(AK88_WDT_TIMER1, regval);
+}
+
+static inline void ak880x_alarmint_enable(void)
+{
+	unsigned int regval = 0;
+
+	regval = ak880x_rtc_read(AK88_WDT_TIMER1);
+
+	regval |= (RTC_WAKEUP_SIGNAL_ENABLE | RTC_WAKEUP_SIGNAL_CLEAR);
+
+	ak880x_rtc_write(AK88_WDT_TIMER1, regval);
+}
+
+static int ak880x_rtc_wakeup_enable(int en)
+{
+	unsigned int val;
+
+	printk("%s: %s\n", __FUNCTION__, en ? "enable" : "disable");
+
+	/* read rtc wakeup setting and clear status */
+	val = ak880x_rtc_read(AK88_WDT_TIMER1);
+	val &= ~(0x7);
+	val |= RTC_WAKEUP_SIGNAL_CLEAR;
+	ak880x_rtc_write(AK88_WDT_TIMER1, val);
+	val &= ~RTC_WAKEUP_SIGNAL_CLEAR;
+
+	if (en)
+	{
+		/* enable wakeup signal */
+		val |= (RTC_WAKEUP_SIGNAL_ENABLE) ;//| RTC_WAKEUP_SIGNAL_LOWACTIVE);
+		ak880x_rtc_write(AK88_WDT_TIMER1, val);
+	} 
+	else 
+	{
+		/* disable wakeup signal */
+		/* val |= RTC_WAKEUP_SIGNAL_CLEAR; */
+		/* ak880x_rtc_write(AK88_WDT_TIMER1, val); */
+	}
+	return 0;
+}
+
+
+static int ak880x_rtc_gettime(struct device *dev, struct rtc_time *tm)
+{
+	unsigned int second = 0;
+	unsigned int dayhour = 0;
+	unsigned int year, month, day, wday, mday, weeks;
+	unsigned int alarm_hour, alarm_day, alarm_wday, alarm_weeks, alarm_time1, alarm_time2;
+	int leap;
+	int year_delta = 0;
+	int i=0, tmp=0;
+	unsigned long day_of_year;
+
+	year_delta = ak880x_rtc_read(AK88_ALARM_TIME1) % 60;
+	year = 2009 + year_delta;
+	leap = leap_year(year);
+	day_of_year = ((leap)?365:364);
+
+	dayhour = ak880x_rtc_read(AK88_RTC_DAYHOUR);
+	weeks = (dayhour&0x3f00)>>8;
+	wday =  (dayhour&0xe0)>>5;
+	day = weeks*7 + wday;
+
+	if(day > day_of_year)
+	{
+		day = day - day_of_year -1;
+		year_delta ++;
+		year ++;
+		dayhour = dayhour & ~0xffe0;
+		dayhour |= (day/7)<<8;
+		dayhour |= (day%7)<<5;
+		wday =  (dayhour&0xe0)>>5;
+		ak880x_rtc_write(AK88_RTC_DAYHOUR, dayhour);
+
+		alarm_time1 = ak880x_rtc_read(AK88_ALARM_TIME1);
+		ak880x_rtc_write(AK88_ALARM_TIME1, alarm_time1 - alarm_time1%60 + year_delta);
+
+		leap = leap_year(year);
+
+		alarm_time2 = ak880x_rtc_read(AK88_ALARM_TIME2);
+		alarm_hour = alarm_time2 & 0x1f;
+		alarm_day = alarm_time2 & (~0x1f);
+		alarm_weeks = (alarm_day/7)<<8;
+		alarm_wday = (alarm_day%7)<<5;
+		alarm_day = alarm_weeks*7 + alarm_wday;
+		if(alarm_day > day_of_year)
+			alarm_day = alarm_day - day_of_year - 1;
+		ak880x_rtc_write(AK88_ALARM_TIME2, (alarm_day/7)<<8 | (alarm_day%7)<<5 | alarm_hour);
+	}
+
+	while(1)
+	{
+		if( rtc_ydays[leap][i] >= (day+1))
+		{
+			i--;
+			break;
+		}
+		i++;
+	}
+	month = i;
+	mday = day + 1 - rtc_ydays[leap][i];
+	second = ak880x_rtc_read(AK88_RTC_SECOND);
+
+	tm->tm_year = year - 1900;
+	tm->tm_hour = dayhour & 0x1f;
+	tm->tm_min = second / 60;
+	tm->tm_sec = second % 60;
+	tm->tm_mon = month;
+	tm->tm_mday = mday; 
+	tm->tm_wday = (wday + base[year_delta])%7; 
+	tm->tm_yday = day;
+	tm->tm_isdst = -1;
+
+	return 0;
+}
+
+
+static int ak880x_rtc_settime(struct device *dev, struct rtc_time *tm)
+{
+	unsigned int second = 0;
+	unsigned int dayhour = 0;
+	unsigned int year_delta = 0;
+	unsigned int rtc_time1 = 0;
+	unsigned int rtc_set_year = 0;
+	unsigned int alarm_set_year = 0;
+	int days;
+
+	year_delta = (tm->tm_year + 1900 - 2009);
+	rtc_time1 = ak880x_rtc_read(AK88_ALARM_TIME1);
+	rtc_time1 = rtc_time1 - rtc_time1 % 60 + year_delta;
+	ak880x_rtc_write(AK88_ALARM_TIME1, rtc_time1);
+
+	if(tm->tm_hour>=0 && tm->tm_min>=0 && tm->tm_sec>=0)
+	{
+		second = tm->tm_min * 60 + tm->tm_sec;
+		ak880x_rtc_write(AK88_RTC_SECOND, second);
+		dayhour = ak880x_rtc_read(AK88_RTC_DAYHOUR) & (~0x1f);
+		dayhour |= tm->tm_hour;
+		ak880x_rtc_write(AK88_RTC_DAYHOUR, dayhour);
+	}
+
+	if(tm->tm_mon>=0 && tm->tm_mday>=0)
+	{
+		days = tm->tm_yday;
+		dayhour = ak880x_rtc_read(AK88_RTC_DAYHOUR) & ~0xffe0;
+		dayhour |= (days/7)<<8;
+		dayhour |= (days%7)<<5;
+		ak880x_rtc_write(AK88_RTC_DAYHOUR, dayhour);
+	}
+	return 0;
+}
+
+static int ak880x_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+	/* unsigned int second = 0;
+	unsigned int dayhour = 0;
+	int ret;
+
+	second = ak880x_rtc_read(AK88_ALARM_TIME1);
+	dayhour = ak880x_rtc_read(AK88_ALARM_TIME2);
+
+	alarm_day = ((dayhour&0x3f00)>>8)*7 + ((dayhour&0xe0)>>5)+1;
+	wkalrm->time.tm_sec = (second+1) % 60;
+	wkalrm->time.tm_min = (second+1) / 60;
+	wkalrm->time.tm_hour = dayhour & 0x1f;
+	wkalrm->time.tm_yday = alarm_day; 
+	wkalrm->time.tm_mon = 0; 
+	wkalrm->time.tm_mday = 0; 
+	wkalrm->time.tm_wday = 0; 
+	wkalrm->time.tm_year = 0; 
+	wkalrm->time.tm_isdst = -1; */
+
+	return 0;
+}
+
+static int ak880x_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+	unsigned long second = 0;
+	unsigned long alarm_dayhour = 0;
+	unsigned long rtc_dayhour = 0;
+	unsigned long year, month, day, wday, mday, weeks;
+	int leap;
+	int year_delta = 0;
+	int i=0, tmp=0;
+	unsigned long day_of_year;
+
+	alarm_year = wkalrm->time.tm_year + 1900; 
+	alarm_day = rtc_year_days(wkalrm->time.tm_mday, wkalrm->time.tm_mon, alarm_year);
+	year_delta = ak880x_rtc_read(AK88_ALARM_TIME1) % 60;
+	year = 2009 + year_delta;
+	leap = leap_year(year);
+
+	day_of_year = ((leap)?365:364);
+	rtc_dayhour = ak880x_rtc_read(AK88_RTC_DAYHOUR);
+	weeks = (rtc_dayhour&0x3f00)>>8;
+	wday =  (rtc_dayhour&0xe0)>>5;
+	day = weeks*7 + wday;
+	if(day > day_of_year)
+	{
+		day = day - day_of_year - 1;
+		year_delta ++;
+		year ++;
+		rtc_dayhour = rtc_dayhour & 0x1f;
+		rtc_dayhour |= (day/7)<<8;
+		rtc_dayhour |= (day%7)<<5;
+		/* wday =  (rtc_dayhour&0xe0)>>5; */
+		ak880x_rtc_write(AK88_RTC_DAYHOUR, rtc_dayhour);
+		leap = leap_year(year);
+	}
+
+	if((alarm_year - year) < 0)
+	{
+		ak880x_rtc_wakeup_enable(0);
+		printk("alarm set error\n");
+		return -1;
+	}
+
+	if((alarm_year - year) > 1)
+	{
+		ak880x_rtc_wakeup_enable(0);
+		printk("alarm time: over one year\n");
+		return -1;
+	}
+
+	if(wkalrm->time.tm_hour>=0 && wkalrm->time.tm_min>=0 && wkalrm->time.tm_sec>=0)
+	{
+		/* second = wkalrm->time.tm_min * 60 + wkalrm->time.tm_sec; */
+		second = wkalrm->time.tm_min * 60;
+		second += year_delta;
+		ak880x_rtc_write(AK88_ALARM_TIME1, second);
+
+		alarm_dayhour = ak880x_rtc_read(AK88_ALARM_TIME2) & ~0x1f;
+		alarm_dayhour |= wkalrm->time.tm_hour;
+		ak880x_rtc_write(AK88_ALARM_TIME2, alarm_dayhour);
+	}
+
+	if((alarm_year - year) == 0)
+	{
+		alarm_dayhour = ak880x_rtc_read(AK88_ALARM_TIME2) & 0x1f;
+		alarm_dayhour |= (alarm_day/7)<<8;
+		alarm_dayhour |= (alarm_day%7)<<5;
+		ak880x_rtc_write(AK88_ALARM_TIME2, alarm_dayhour);
+	}
+
+	if((alarm_year - year) == 1)
+	{
+		if(alarm_day > day)
+		{
+			ak880x_rtc_wakeup_enable(0);
+			printk("alarm time: over one year\n");
+			return -1;
+		}
+		else
+		{
+			day_of_year = leap_year(year);
+			alarm_dayhour = ak880x_rtc_read(AK88_ALARM_TIME2) & 0x1f;
+			alarm_dayhour |= ((day_of_year +1 + alarm_day)/7)<<8;
+			alarm_dayhour |= ((day_of_year +1 + alarm_day)%7)<<5;
+			ak880x_rtc_write(AK88_ALARM_TIME2, alarm_dayhour);
+		}
+	}
+
+	if (wkalrm->enabled)
+		ak880x_rtc_wakeup_enable(1);
+	else
+		ak880x_rtc_wakeup_enable(0);
+
+	return 0;
+}
+
+static int ak880x_rtc_ioctl(struct device *dev,
+		unsigned int cmd, unsigned long arg)
+{
+	unsigned int ret = -ENOIOCTLCMD;
+
+	switch (cmd) {
+		case RTC_AIE_OFF:
+			ak880x_rtc_wakeup_enable(0);
+			ret = 0;
+			break;
+		case RTC_AIE_ON:
+			ak880x_rtc_wakeup_enable(1);
+			ret = 0;
+			break;
+
+		case RTC_UIE_ON:
+		case RTC_UIE_OFF:
+			ret = -EINVAL;
+			break;
+	}
+
+	return ret;
+}
+
+static int ak880x_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	return 0;
+}
+
+static irqreturn_t ak880x_rtc_alarmirq(int irq, void *id)
+{
+	struct rtc_device *rdev = id;
+	ak880x_rtc_int_clear();
+	rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
+
+	return IRQ_HANDLED;
+}
+
+static int ak880x_rtc_open(struct device *dev)
+{
+	return 0;
+}
+
+static void ak880x_rtc_release(struct device *dev)
+{
+}
+
+static const struct rtc_class_ops ak880x_rtc_ops = {
+	.open		= ak880x_rtc_open,
+	.release	= ak880x_rtc_release,
+	.ioctl		= ak880x_rtc_ioctl,
+	.read_time	= ak880x_rtc_gettime,
+	.set_time	= ak880x_rtc_settime,
+	.read_alarm	= ak880x_rtc_getalarm,
+	.set_alarm	= ak880x_rtc_setalarm,
+	.proc	        = ak880x_rtc_proc,
+};
+
+static int ak880x_rtc_remove(struct platform_device *dev)
+{
+	struct rtc_device *rtc = platform_get_drvdata(dev);
+
+	free_irq(IRQ_RTC_ALARM, rtc);
+
+	platform_set_drvdata(dev, NULL);
+	rtc_device_unregister(rtc);
+
+	return 0;
+}
+
+static int ak880x_rtc_probe(struct platform_device *pdev)
+{
+	struct rtc_device *rtc;
+	/* struct resource *res; */
+	int ret;
+
+	rtc = rtc_device_register("ak880x-rtc", &pdev->dev, &ak880x_rtc_ops,
+			THIS_MODULE);
+
+	if (IS_ERR(rtc)) {
+		dev_err(&pdev->dev, "cannot attach rtc\n");
+		ret = PTR_ERR(rtc);
+
+		return -1;
+	}
+
+	rtc->max_user_freq = 128;
+
+	platform_set_drvdata(pdev, rtc);
+
+	ak880x_rtc_wakeup_enable(0);
+
+	ret = request_irq(IRQ_RTC_ALARM, ak880x_rtc_alarmirq,
+			IRQF_DISABLED,  "ak880x-rtc alarm", rtc);
+	if (ret) {
+		printk("IRQ %d error %d\n", IRQ_RTC_ALARM, ret);
+		return ret;
+	}
+
+	return 0;
+
+}
+
+#ifdef CONFIG_PM
+
+static void ak880x_rtc_enable(struct platform_device *pdev, int en)
+{
+}
+static struct timespec ak880x_rtc_delta;
+/* RTC Power management control */
+static int ak880x_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtc_time tm;
+	struct timespec time;
+
+	time.tv_nsec = 0;
+
+	/* calculate time delta for suspend */
+
+	ak880x_rtc_gettime(&pdev->dev, &tm);
+	rtc_tm_to_time(&tm, &time.tv_sec);
+	save_time_delta(&ak880x_rtc_delta, &time);
+
+	return 0;
+}
+
+static int ak880x_rtc_resume(struct platform_device *pdev)
+{
+	struct rtc_time tm;
+	struct timespec time;
+
+	time.tv_nsec = 0;
+	ak880x_rtc_gettime(&pdev->dev, &tm);
+	rtc_tm_to_time(&tm, &time.tv_sec);
+	restore_time_delta(&ak880x_rtc_delta, &time);
+	return 0;
+}
+#else
+#define ak880x_rtc_suspend NULL
+#define ak880x_rtc_resume  NULL
+#endif
+
+static struct platform_driver ak880x_rtcdrv = {
+	.probe		= ak880x_rtc_probe,
+	.remove		= ak880x_rtc_remove,
+	.suspend	= ak880x_rtc_suspend,
+	.resume		= ak880x_rtc_resume,
+	.driver		= {
+		.name	= "ak880x-rtc",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init ak880x_rtc_init(void)
+{
+	printk("AK88 RTC, (c) 2010 ANYKA \n");
+	return platform_driver_register(&ak880x_rtcdrv);
+}
+
+static void __exit ak880x_rtc_exit(void)
+{
+	platform_driver_unregister(&ak880x_rtcdrv);
+}
+
+module_init(ak880x_rtc_init);
+module_exit(ak880x_rtc_exit);
+
+MODULE_DESCRIPTION("ANYKA AK88 RTC Driver");
+MODULE_AUTHOR("anyka");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak880x-rtc");
diff --git a/drivers/rtc/rtc-ak98.c b/drivers/rtc/rtc-ak98.c
new file mode 100644
index 00000000000..4c7b6be06bc
--- /dev/null
+++ b/drivers/rtc/rtc-ak98.c
@@ -0,0 +1,468 @@
+/*
+ * drivers/rtc/rtc-ak98.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * 2011-3-22 for AK98 zwy
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/clk.h>
+#include <linux/log2.h>
+#include <linux/delay.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/rtc.h>
+
+
+
+//#define RTC_DEBUG
+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))
+
+
+#undef PDEBUG           /* undef it, just in case */
+#ifdef RTC_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+static int ak98_rtc_wakeup_enable(int en);
+static void ak98_rtc_alarm_enable(void );
+static void ak98_rtc_alarm_disable(void );
+
+
+static inline void ak98_rtc_int_clear(void) 
+{
+	unsigned int regval;
+	
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	regval = ak98_rtc_read(AK98_RTC_SETTING);
+	regval |= (1<<0);
+
+	ak98_rtc_write(AK98_RTC_SETTING, regval);
+
+}
+
+
+static int ak98_rtc_wakeup_enable(int en)
+{
+	unsigned int val;
+
+	PDEBUG("%s(): Entering...\n", __func__);
+	PDEBUG("%s: %s\n", __FUNCTION__, en ? "enable" : "disable");
+
+	/* read rtc wakeup setting and clear status */
+	val = REG32(AK98_RTC_CDR);
+	val &= ~RTC_WAKEUP_EN;	
+	REG32(AK98_RTC_CDR) =  val;
+
+
+	if (en)
+	{
+		/* enable wakeup signal */
+		val |= RTC_WAKEUP_EN ;//| RTC_WAKEUP_SIGNAL_LOWACTIVE);
+		REG32(AK98_RTC_CDR) =  val;
+	} 
+	else 
+	{
+		/* disable wakeup signal */
+		/* val |= RTC_WAKEUP_SIGNAL_CLEAR; */
+		/* ak98_rtc_write(AK98_WDT_TIMER1, val); */
+	}
+	return 0;
+
+}
+
+
+static int ak98_rtc_gettime(struct device *dev, struct rtc_time *tm)
+{	
+	unsigned long rtcset;
+	unsigned long rtc_time1;
+	unsigned long rtc_time2;
+	unsigned long rtc_time3;
+
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	rtcset = ak98_rtc_read(AK98_RTC_SETTING);
+	rtcset |= RTC_SETTING_REAL_TIME_RE;
+	ak98_rtc_write(AK98_RTC_SETTING, rtcset);
+	
+	rtc_time1 = ak98_rtc_read(AK98_RTC_REAL_TIME1);
+	rtc_time2 = ak98_rtc_read(AK98_RTC_REAL_TIME2);
+	rtc_time3 = ak98_rtc_read(AK98_RTC_REAL_TIME3);
+
+	tm->tm_year  = ((rtc_time3 >> 4) & 0x7F) - EPOCH_START_YEAR + RTC_START_YEAR;
+	tm->tm_mon   = (rtc_time3 & 0xF) - 1;
+	tm->tm_mday  = (rtc_time2 >> 5) & 0x1F;
+	tm->tm_hour  = rtc_time2 & 0x1F;
+	tm->tm_min   = (rtc_time1 >> 6) & 0x3F;
+	tm->tm_sec   = rtc_time1 & 0x3F;
+	tm->tm_wday  = (rtc_time2 >> 10) & 0x7;
+	tm->tm_isdst = -1;
+
+	PDEBUG("%d-%d-%d %d:%d:%d\n",tm->tm_year, tm->tm_mon, tm->tm_mday,tm->tm_hour, tm->tm_min,tm->tm_sec);
+	return 0;
+}
+
+
+static int ak98_rtc_settime(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long regval;
+
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	if ((tm->tm_year < (RTC_START_YEAR - EPOCH_START_YEAR))
+		|| (tm->tm_year > (RTC_START_YEAR - EPOCH_START_YEAR + RTC_YEAR_COUNT))) {
+		printk("%s(): RTC Year must between (%d ~ %d)\n", 
+			__func__, RTC_START_YEAR, (RTC_START_YEAR + RTC_YEAR_COUNT));
+		return -1;
+	}
+
+	ak98_rtc_write(AK98_RTC_REAL_TIME1, (tm->tm_min << 6) | tm->tm_sec);
+	ak98_rtc_write(AK98_RTC_REAL_TIME2, (tm->tm_wday << 10) | (tm->tm_mday << 5) | tm->tm_hour);
+	ak98_rtc_write(AK98_RTC_REAL_TIME3, ((tm->tm_year + EPOCH_START_YEAR - RTC_START_YEAR) << 4) | (tm->tm_mon + 1));
+
+	regval = ak98_rtc_read(AK98_RTC_SETTING);
+	regval |= RTC_SETTING_REAL_TIME_WR;
+	ak98_rtc_write(AK98_RTC_SETTING, regval);
+
+	while (ak98_rtc_read(AK98_RTC_SETTING) & RTC_SETTING_REAL_TIME_WR)
+		;
+	
+	udelay(40);
+
+	return 0;
+}
+
+static int ak98_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{	
+	unsigned long rtc_alarm1;
+	unsigned long rtc_alarm2;
+	unsigned long rtc_alarm3;
+
+	PDEBUG("Entering %s\n", __FUNCTION__);
+
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+
+	PDEBUG("%x %x %x\n", rtc_alarm1, rtc_alarm2, rtc_alarm3);
+	
+	wkalrm->time.tm_sec = rtc_alarm1 & 0x3F;
+	wkalrm->time.tm_min = (rtc_alarm1 >> 6) & 0x3F;
+	wkalrm->time.tm_hour = rtc_alarm2 & 0x1F;
+	wkalrm->time.tm_mday = (rtc_alarm2 >> 5) & 0x1F;
+	wkalrm->time.tm_mon = (rtc_alarm3 & 0xF) - 1;
+	wkalrm->time.tm_year = ((rtc_alarm3 >> 4) & 0x3F) - EPOCH_START_YEAR + RTC_START_YEAR;
+	wkalrm->time.tm_isdst = -1;
+
+	PDEBUG("%d-%d-%d %d:%d:%d",wkalrm->time.tm_year,wkalrm->time.tm_mon,wkalrm->time.tm_mday,
+		wkalrm->time.tm_hour,wkalrm->time.tm_min ,wkalrm->time.tm_sec);
+	return 0;
+}
+
+
+static int ak98_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+	unsigned long rtc_alarm1;
+	unsigned long rtc_alarm2;
+	unsigned long rtc_alarm3;
+
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+
+	PDEBUG("%u %u %u\n", rtc_alarm1, rtc_alarm2, rtc_alarm3);
+	PDEBUG("%d-%d-%d %d:%d:%d",wkalrm->time.tm_year,wkalrm->time.tm_mon,wkalrm->time.tm_mday,
+			wkalrm->time.tm_hour,wkalrm->time.tm_min ,wkalrm->time.tm_sec);
+
+	rtc_alarm1 &= ~(0xFFF);
+	rtc_alarm2 &= ~(0x3FF);
+	rtc_alarm3 &= ~(0x7FF);
+	
+	
+	rtc_alarm1 |= ((wkalrm->time.tm_min << 6) + wkalrm->time.tm_sec);
+	rtc_alarm2 |= ((wkalrm->time.tm_mday << 5) + wkalrm->time.tm_hour);
+	rtc_alarm3 |= (((wkalrm->time.tm_year + EPOCH_START_YEAR - RTC_START_YEAR) << 4) + (wkalrm->time.tm_mon + 1));
+	
+	ak98_rtc_write(AK98_RTC_ALARM_TIME1, rtc_alarm1);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME2, rtc_alarm2);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME3, rtc_alarm3);
+
+	PDEBUG("%u %u %u\n", rtc_alarm1, rtc_alarm2, rtc_alarm3);
+
+	if (wkalrm->enabled == 1)
+	{
+		ak98_rtc_wakeup_enable(1);
+		ak98_rtc_alarm_enable();
+	}
+	else
+	{
+		ak98_rtc_alarm_disable();
+		ak98_rtc_wakeup_enable(0);
+	}	
+	
+	return 0;
+}
+static void ak98_rtc_alarm_enable(void )
+{
+	unsigned long rtc_alarm1;
+	unsigned long rtc_alarm2;
+	unsigned long rtc_alarm3;
+
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+
+	rtc_alarm1 |= (1<<13);
+	rtc_alarm2 |= (1<<13);
+	rtc_alarm3 |= (1<<13);
+
+	ak98_rtc_write(AK98_RTC_ALARM_TIME1, rtc_alarm1);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME2, rtc_alarm2);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME3, rtc_alarm3);	
+}
+
+static void ak98_rtc_alarm_disable(void )
+{
+	unsigned long rtc_alarm1;
+	unsigned long rtc_alarm2;
+	unsigned long rtc_alarm3;
+
+	rtc_alarm1 = ak98_rtc_read(AK98_RTC_ALARM_TIME1);
+	rtc_alarm2 = ak98_rtc_read(AK98_RTC_ALARM_TIME2);
+	rtc_alarm3 = ak98_rtc_read(AK98_RTC_ALARM_TIME3);
+
+	rtc_alarm1 &= ~(1<<13);
+	rtc_alarm2 &= ~(1<<13);
+	rtc_alarm3 &= ~(1<<13);
+
+	ak98_rtc_write(AK98_RTC_ALARM_TIME1, rtc_alarm1);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME2, rtc_alarm2);
+	ak98_rtc_write(AK98_RTC_ALARM_TIME3, rtc_alarm3);	
+}
+
+
+static int ak98_rtc_ioctl(struct device *dev,
+		unsigned int cmd, unsigned long arg)
+{
+	//PDEBUG("Entering %s: cmd %d\n", __FUNCTION__, cmd);
+	unsigned int ret = -ENOIOCTLCMD;
+
+	switch (cmd) {
+		case RTC_AIE_OFF:
+			PDEBUG("RTC_AIE_OFF\n");
+			ak98_rtc_alarm_disable();
+			ak98_rtc_wakeup_enable(0);
+
+			ret = 0;
+			break;
+		case RTC_AIE_ON:
+			PDEBUG("RTC_AIE_ON\n");
+			ak98_rtc_wakeup_enable(1);
+			ak98_rtc_alarm_enable();
+			ret = 0;
+			break;
+
+		case RTC_UIE_ON:
+		case RTC_UIE_OFF:
+			ret = -ENOTTY;
+			break;
+		case RTC_RD_TIME:
+			PDEBUG("Read Time\n");
+			break;
+		case RTC_SET_TIME:
+			PDEBUG("Set Time\n");
+			break;
+		case RTC_ALM_SET:
+			PDEBUG("Set alarm\n");
+			break;
+		case RTC_ALM_READ:
+			PDEBUG("Read alarm\n");
+			break;
+		default:
+			return -ENOTTY;
+
+	}
+
+	return ret;
+}
+
+static int ak98_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	return 0;
+}
+
+static irqreturn_t ak98_rtc_alarmirq(int irq, void *id)
+{
+	struct rtc_device *rdev = id;
+	PDEBUG("%s(): Entering...\n", __func__);	
+	ak98_rtc_int_clear();
+	rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
+
+	return IRQ_HANDLED;
+}
+
+static int ak98_rtc_open(struct device *dev)
+{
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	return 0;
+}
+
+static void ak98_rtc_release(struct device *dev)
+{
+	PDEBUG("Entering %s\n", __FUNCTION__);
+
+}
+
+static const struct rtc_class_ops ak98_rtc_ops = {
+	.open		= ak98_rtc_open,
+	.release	= ak98_rtc_release,
+	.ioctl		= ak98_rtc_ioctl,
+	.read_time	= ak98_rtc_gettime,
+	.set_time	= ak98_rtc_settime,
+	.read_alarm	= ak98_rtc_getalarm,
+	.set_alarm	= ak98_rtc_setalarm,
+	.proc	        = ak98_rtc_proc,
+};
+
+static int ak98_rtc_remove(struct platform_device *dev)
+{
+	struct rtc_device *rtc = platform_get_drvdata(dev);
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	free_irq(IRQ_RTC_ALARM, rtc);
+
+	platform_set_drvdata(dev, NULL);
+	rtc_device_unregister(rtc);
+
+	return 0;
+}
+
+static int ak98_rtc_probe(struct platform_device *pdev)
+{
+	struct rtc_device *rtc;
+	/* struct resource *res; */
+	int ret;
+
+	rtc = rtc_device_register("ak98-rtc", &pdev->dev, &ak98_rtc_ops,
+			THIS_MODULE);
+
+	if (IS_ERR(rtc)) {
+		dev_err(&pdev->dev, "cannot attach rtc\n");
+		ret = PTR_ERR(rtc);
+
+		return -1;
+	}
+
+	rtc->max_user_freq = 128;
+
+	platform_set_drvdata(pdev, rtc);
+
+	ak98_rtc_wakeup_enable(0);
+
+	ret = request_irq(IRQ_RTC_ALARM, ak98_rtc_alarmirq,
+			IRQF_DISABLED,  "ak98-rtc alarm", rtc);
+	if (ret) {
+		printk("IRQ %d error %d\n", IRQ_RTC_ALARM, ret);
+		return ret;
+	}
+
+	return 0;
+
+}
+
+#ifdef CONFIG_PM
+
+
+static struct timespec ak98_rtc_delta;
+/* RTC Power management control */
+static int ak98_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtc_time tm;
+	struct timespec time;
+
+	time.tv_nsec = 0;
+
+	/* calculate time delta for suspend */
+
+	ak98_rtc_gettime(&pdev->dev, &tm);
+	rtc_tm_to_time(&tm, &time.tv_sec);
+	save_time_delta(&ak98_rtc_delta, &time);
+
+	return 0;
+}
+
+static int ak98_rtc_resume(struct platform_device *pdev)
+{
+	struct rtc_time tm;
+	struct timespec time;
+
+	time.tv_nsec = 0;
+	ak98_rtc_gettime(&pdev->dev, &tm);
+	rtc_tm_to_time(&tm, &time.tv_sec);
+	restore_time_delta(&ak98_rtc_delta, &time);
+	
+	return 0;
+}
+#else
+#define ak98_rtc_suspend NULL
+#define ak98_rtc_resume  NULL
+#endif
+
+static struct platform_driver ak98_rtcdrv = {
+	.probe		= ak98_rtc_probe,
+	.remove		= ak98_rtc_remove,
+	.suspend	= ak98_rtc_suspend,
+	.resume		= ak98_rtc_resume,
+	.driver		= {
+		.name	= "ak98-rtc",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init ak98_rtc_init(void)
+{
+	PDEBUG("RTC Init...\n");
+	
+	ak98_rtc_power(RTC_ON);
+
+	printk("AK98 RTC, (c) 2010 ANYKA \n");
+	return platform_driver_register(&ak98_rtcdrv);
+}
+
+static void __exit ak98_rtc_exit(void)
+{	
+	/*
+		When RTC is powered off, this bit(AK98_RTC_CONF [24] ) should be set to 0
+	*/
+	ak98_rtc_power(RTC_OFF);
+	platform_driver_unregister(&ak98_rtcdrv);
+}
+
+module_init(ak98_rtc_init);
+module_exit(ak98_rtc_exit);
+
+MODULE_DESCRIPTION("ANYKA AK98 RTC Driver");
+MODULE_AUTHOR("anyka");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak98-rtc");
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e5225725727..022d7aea09f 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1477,4 +1477,32 @@ config SERIAL_BCM63XX_CONSOLE
 	  If you have enabled the serial port on the bcm63xx CPU
 	  you can make it the console by answering Y to this option.
 
+config SERIAL_AK88
+	tristate "AK88 serial port support"
+	select SERIAL_CORE
+	depends on ARCH_AK88
+	help
+	  AK88 Uart support.
+
+config SERIAL_AK88_CONSOLE
+	bool "Console on AK88 serial port"
+	depends on SERIAL_AK88
+	select SERIAL_CORE_CONSOLE
+	help
+          Say Y here if you want enable console support on AK88 serial port.
+
+config SERIAL_AK98
+	tristate "AK98 serial port support"
+	select SERIAL_CORE
+	depends on ARCH_AK98
+	help
+	  AK98 Uart support.
+
+config SERIAL_AK98_CONSOLE
+	bool "Console on AK98 serial port"
+	depends on SERIAL_AK98
+	select SERIAL_CORE_CONSOLE
+	help
+          Say Y here if you want enable console support on AK98 serial port.
+
 endmenu
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d21d5dd5d04..4a7c5f75800 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -81,3 +81,6 @@ obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
 obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
 obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
 obj-$(CONFIG_SERIAL_TIMBERDALE)	+= timbuart.o
+obj-$(CONFIG_SERIAL_AK88)	+= ak88_uart.o
+obj-$(CONFIG_SERIAL_AK98)	+= ak98_uart.o
+
diff --git a/drivers/serial/ak88_uart.c b/drivers/serial/ak88_uart.c
new file mode 100644
index 00000000000..102707020ba
--- /dev/null
+++ b/drivers/serial/ak88_uart.c
@@ -0,0 +1,1293 @@
+#if defined(CONFIG_SERIAL_AK88_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/sysrq.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+
+
+#define AK88_UART0_TXBUF_BASE	(AK88_VA_L2MEM + 0x1000)	/* offset 0x0[tx], 0x80[rx] */
+#define AK88_UART0_RXBUF_BASE	(AK88_VA_L2MEM + 0x1080)	/* offset 0x0[tx], 0x80[rx] */
+#define AK88_UART1_TXBUF_BASE	(AK88_VA_L2MEM + 0x1100)
+#define AK88_UART1_RXBUF_BASE	(AK88_VA_L2MEM + 0x1180)
+#define AK88_UART2_TXBUF_BASE	(AK88_VA_L2MEM + 0x1200)
+#define AK88_UART2_RXBUF_BASE	(AK88_VA_L2MEM + 0x1280)
+#define AK88_UART3_TXBUF_BASE	(AK88_VA_L2MEM + 0x1300)
+#define AK88_UART3_RXBUF_BASE	(AK88_VA_L2MEM + 0x1380)
+
+#define AK88_UART_BASE(x)	(((AK88_VA_UART) + ((x) * 0x1000)))
+
+#define AK88_UART0_BASE	(AK88_VA_UART + 0x0000)
+#define AK88_UART1_BASE	(AK88_VA_UART + 0x1000)
+#define AK88_UART2_BASE	(AK88_VA_UART + 0x2000)
+#define AK88_UART3_BASE	(AK88_VA_UART + 0x3000)
+
+#define AK88_UART0_PA_BASE	(AK88_PA_UART + 0x0000)
+#define AK88_UART1_PA_BASE	(AK88_PA_UART + 0x1000)
+#define AK88_UART2_PA_BASE	(AK88_PA_UART + 0x2000)
+#define AK88_UART3_PA_BASE	(AK88_PA_UART + 0x3000)
+
+#define UART_CONF1		0x00
+#define	UART_CONF2		0x04
+#define	DATA_CONF		0x08
+#define	BUF_THRESHOLD		0x0C
+#define	UART_RXBUF		0x10
+#define	RXBUF_THRESHOLD_EXT	0x14
+
+#define	AKUART_INT_MASK		0x3FE00000
+
+#define TX_THR_INT_ENABLE	(29)
+#define RX_THR_INT_ENABLE	(28)
+#define TX_END_INT_ENABLE	(27)
+#if	defined(CONFIG_ARCH_AK7801)
+#define	RXBUF_FULL_INT_ENABLE	(26)
+#elif	defined(CONFIG_ARCH_AK88)
+#define	RXBUF_FULL_INT_ENABLE	(25)
+#endif
+#define TXBUF_EMP_INT_ENABLE	(24)
+#define RECVDATA_ERR_INT_ENABLE	(23)
+#define RX_TIMEOUT_INT_ENABLE	(22)
+#define	MEM_RDY_INT_ENABLE	(21)
+
+#define TX_THR_INT		(31)
+#define RX_THR_INT		(30)
+#define	TX_END_INT		(19)
+#define	RX_OV			(18)
+#define	MEM_RDY_INT		(17)
+#define TX_BYT_CNT_VLD		(16)
+#define RECVDATA_ERR_INT	(3)
+#define	RX_TIMEOUT		(2)
+#define RXBUF_FULL		(1)
+#define TXFIFO_EMPTY		(0)
+
+
+#define UART_RX_FIFO_SIZE	32
+
+extern void printch(char);
+extern void printascii(const char *);
+
+
+#if 0
+#define dbg(x...)	printk(x)
+#else
+#define dbg(x...)	do {} while(0)
+#endif
+
+#if 0
+#define dbg_irq(x...)	printk(x)
+#else
+#define dbg_irq(x...)	do {} while(0)
+#endif
+
+/* UART name and device definitions */
+#define NR_PORTS		4
+
+#define AK88_SERIAL_NAME	"ttySAK"
+#define AK88_SERIAL_MAJOR	204
+#define AK88_SERIAL_MINOR	64
+
+
+#ifdef CONFIG_SERIAL_AK88_CONSOLE
+
+static struct console ak880x_serial_console;
+
+#define AK88_SERIAL_CONSOLE &ak880x_serial_console
+#else
+#define AK88_SERIAL_CONSOLE NULL
+#endif
+
+struct ak880x_uart_port {
+	char			*name;
+	struct uart_port	port;
+
+	unsigned char __iomem   *rxfifo_base;
+	unsigned char __iomem   *txfifo_base;
+
+	unsigned int		rxfifo_offset;
+#if	defined(CONFIG_ARCH_AK88)
+	unsigned int		rxbuf_offset;
+#endif
+	unsigned int		nbr_to_read;
+	unsigned int		timeout_cnt;
+
+
+	unsigned char		claimed;
+	struct clk		*clk;
+};
+
+/* macros to change one thing to another */
+
+#define tx_enabled(port)	((port)->unused[0])
+#define rx_enabled(port)	((port)->unused[1])
+
+static int clk_asic_getrate(void)
+{
+	union ak880x_clk_div1_reg clk_div1_reg;
+	unsigned int clkrate,asicrate;
+	unsigned int asic_div;
+
+	clk_div1_reg.regval = __raw_readl(AK88_VA_SYSCTRL+0x04);
+
+ 	clkrate = 4 * (clk_div1_reg.clk_div.m + 45) / (clk_div1_reg.clk_div.n + 1);  //default 
+
+#ifdef CONFIG_ARCH_AK7801
+	if (clk_div1_reg.clk_div.m > 0x20)
+		clkrate = 4 * 62 /(clk_div1_reg.clk_div.n + 1);
+	else
+		clkrate = 4 * (clk_div1_reg.clk_div.m + 62) / (clk_div1_reg.clk_div.n + 1);
+#endif
+
+#ifdef CONFIG_ARCH_AK88
+	clkrate = 4 * (clk_div1_reg.clk_div.m + 45) / (clk_div1_reg.clk_div.n + 1);
+#endif
+
+	asic_div = clk_div1_reg.clk_div.asic_clk ;
+        asicrate = clkrate ;
+
+	if(asic_div==0){
+ 		#ifdef CONFIG_BOARD_AK8801EPC
+		        asicrate = clkrate /2 ;
+		#else
+ 		        asicrate = clkrate ;
+ 		#endif
+ 	}
+	else{
+	   	if(asic_div==1)
+			asicrate = clkrate /2;
+		else
+			asicrate = clkrate >> asic_div;
+ 	} 
+
+	return asicrate;
+}
+
+
+static int uart_intevent_decode(unsigned long status,
+		unsigned int maskbit, unsigned int statusbit)
+{
+	if ((status & 1<<maskbit) && (status & 1<<statusbit))
+		return 1;
+	else
+		return 0;
+}
+
+static inline void uart_subint_disable(struct ak880x_uart_port *ourport, unsigned long mask)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+	uart_reg &= ~mask;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+}
+
+static inline void uart_subint_enable(struct ak880x_uart_port *ourport, unsigned long unmask)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+	uart_reg |= unmask;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+}
+
+static void uart_subint_clear(struct ak880x_uart_port *ourport, unsigned int subint)
+{
+	unsigned long uart_reg;
+
+	switch (subint) {
+	case TX_THR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+
+	case RX_THR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+
+	case RECVDATA_ERR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+
+	case RXBUF_FULL:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+
+	case RX_TIMEOUT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+#if	defined(CONFIG_ARCH_AK88)
+		uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+		uart_reg |= (1<<23);
+		__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+#endif
+		break;
+
+	default:
+		printk(KERN_ERR "ak880x-uart: unkown subint type: %d\n", subint);
+		break;
+	}
+
+	return;
+}
+
+static inline void uart_clr_rx_status(struct ak880x_uart_port *ourport)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF1);
+
+#define RX_STATUS_CLR	(1<<29)
+	uart_reg |= RX_STATUS_CLR;
+
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF1);
+}
+
+static inline void uart_clr_tx_status(struct ak880x_uart_port *ourport)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF1);
+
+#define TX_STATUS_CLR	(1<<28)
+	uart_reg |= TX_STATUS_CLR;
+
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF1);
+}
+
+static inline struct ak880x_uart_port *to_ourport(struct uart_port *port)
+{
+	return container_of(port, struct ak880x_uart_port, port);
+}
+
+/*
+ * forcibly clear a uart buffer status
+ */
+static inline void clear_uart_txbuf_status(struct ak880x_uart_port *ourport)
+{
+	unsigned long regval;
+	local_irq_disable();
+	regval = __raw_readl(AK88_VA_L2CTRL + 0x8C);
+
+	regval |= (0x1 << (16 + ourport->port.line * 2));
+
+	__raw_writel(regval,  AK88_VA_L2CTRL + 0x8C);
+	local_irq_enable();
+}
+
+static inline void clear_uart_rxbuf_status(struct ak880x_uart_port *ourport)
+{
+	unsigned long regval;
+
+	/* regval = __raw_readl(AK88_VA_L2CTRL + 0x8C);
+
+	regval |= (0x1 << (17 + ourport->port.line * 2));
+
+	__raw_writel(regval,  AK88_VA_L2CTRL + 0x8C); */
+}
+
+/* static inline void ak880x_uart_putchar(struct ak880x_uart_port *ourport, int ch) */
+static inline void ak880x_uart_putchar(struct ak880x_uart_port *ourport, unsigned char ch)
+{
+	unsigned long regval;
+
+	clear_uart_txbuf_status(ourport);
+
+	/* __raw_writel((unsigned long)ch, ourport->txfifo_base); */
+	__raw_writel(ch, ourport->txfifo_base);
+	__raw_writel(0x0, ourport->txfifo_base + 0x3C);	/*to inform the buf is full*/
+
+	regval = __raw_readl(ourport->port.membase + UART_CONF1);
+	__raw_writel(regval | 0x1<<28, ourport->port.membase + UART_CONF1); /* clear the tx count reg */
+
+	regval = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	__raw_writel(regval | 0x1<<11, ourport->port.membase + BUF_THRESHOLD); /*clear the tx count reg*/
+
+	regval = __raw_readl(ourport->port.membase + UART_CONF2);
+	__raw_writel(regval | (0x1<<4 | 0x1<<16), ourport->port.membase + UART_CONF2);
+
+	while ( (__raw_readl(ourport->port.membase + DATA_CONF) & 0x1fff) != 0)
+	{
+//		if (ourport->port.line == 3)
+//			/* mdelay(1); */
+//			dbg("port %d waiting: 0x%x\n", ourport->port.line, (__raw_readl(ourport->port.membase + DATA_CONF) & 0x1fff));
+	}
+}
+
+static inline int uart_hwport_init(struct ak880x_uart_port *ourport)
+{
+	unsigned int regval = 0;
+
+	/* set share pin to UARTn, and disable pull-up */
+	switch (ourport->port.line) {
+	case 0:
+		/* set share pin */
+		*(volatile unsigned long*)(AK88_SHAREPIN_CON1) |= (1<<9);
+
+		/* enable ppu function */
+		*(volatile unsigned long*)(AK88_PPU_PPD1) &= ~(0x3<<14);
+		rL2_CONBUF8_15 |= 3<<16;
+		rL2_FRACDMAADDR |= 1<<29;
+		break;
+
+	case 1:
+		AK88_GPIO_UART1(1);
+		AK88_GPIO_UART1_FLOW(1);
+		ak880x_gpio_pullup(AK88_GPIO_16, 1);
+		ak880x_gpio_pullup(AK88_GPIO_17, 1);
+		ak880x_gpio_pullup(AK88_GPIO_18, 1);
+		ak880x_gpio_pullup(AK88_GPIO_19, 1);
+
+		regval = __raw_readl(AK88_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<14) | (0xF<<2));
+		regval |= (0x5<<2 | 0xF<<14);
+		__raw_writel(regval, AK88_VA_SYSCTRL+0xD4);
+		rL2_CONBUF8_15 |= 3<<18;
+		rL2_FRACDMAADDR |= 1<<29;
+		break;
+
+	case 2:
+		AK88_GPIO_UART2(1);
+		AK88_GPIO_UART2_FLOW(0);
+		ak880x_gpio_pullup(AK88_GPIO_20, 1);
+		ak880x_gpio_pullup(AK88_GPIO_21, 1);
+		ak880x_gpio_pullup(AK88_GPIO_22, 1);
+		ak880x_gpio_pullup(AK88_GPIO_23, 1);
+
+		regval = __raw_readl(AK88_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<18) | (0xF<<6));
+		regval |= (0x5<<6 | 0xF<<18);
+		__raw_writel(regval, AK88_VA_SYSCTRL+0xD4);
+		rL2_CONBUF8_15 |= 3<<20;
+		rL2_FRACDMAADDR |= 1<<29;
+		break;
+
+	case 3:
+		AK88_GPIO_UART3(1);
+		AK88_GPIO_UART3_FLOW(0);
+		AK88_UART3_ENABLE();
+
+		ak880x_gpio_pullup(AK88_GPIO_24, 1);
+		ak880x_gpio_pullup(AK88_GPIO_25, 1);
+		ak880x_gpio_pullup(AK88_GPIO_26, 1);
+		ak880x_gpio_pullup(AK88_GPIO_27, 1);
+
+		regval = __raw_readl(AK88_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<22) | (0xF<<10));
+		regval |= (0x5<<10 | 0xF<<22);
+		__raw_writel(regval, AK88_VA_SYSCTRL+0xD4);
+		rL2_CONBUF8_15 |= 3<<22;
+		rL2_FRACDMAADDR |= 1<<29;
+		break;
+
+	default:
+		printk(KERN_ERR "unknown uart port\n");
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int uart_enable_clock(struct ak880x_uart_port *ourport, int enable)
+{
+	unsigned long regval;
+
+	regval = __raw_readl(AK88_VA_SYSCTRL + 0x0C);
+
+	switch (ourport->port.line) {
+	case 0:
+		if (enable)
+			regval &= ~(1<<15);
+		/* else
+			regval |= (1<<15); */
+		break;
+
+	case 1:
+		if (enable)
+			regval &= ~(1<<2);
+		else
+			/* shared with SPI SD clock */
+			;
+			/* regval |= (1<<2); */
+		break;
+
+	case 2:
+	case 3:
+		if (enable)
+			regval &= ~(1<<8);
+		else
+			regval |= (1<<8);
+		break;
+
+	default:
+		printk(KERN_ERR "unknown uart port\n");
+		return -1;
+		break;
+	}
+
+	__raw_writel(regval, AK88_VA_SYSCTRL + 0x0C);
+
+	return 0;
+}
+
+/* power power management control */
+static void ak880x_serial_pm(struct uart_port *port, unsigned int level,
+		unsigned int old)
+{
+	switch (level) {
+	case 3:	/* disable */
+	//	dbg("%s: enterring pm level: %d\n", __FUNCTION__, level);
+		break;
+
+	case 0:	/* enable */
+	//	dbg("%s: enterring pm level: %d\n", __FUNCTION__, level);
+		break;
+
+	default:
+		printk(KERN_ERR "ak880x_serial: unknown pm %d\n", level);
+		return ;
+	}
+
+}
+
+static unsigned int ak880x_serial_tx_empty(struct uart_port *port)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(port->membase + UART_CONF2);
+
+	if (uart_reg & 1<<TXFIFO_EMPTY)
+		return 1;
+
+	return 0;
+}
+
+/* no modem control lines */
+static unsigned int ak880x_serial_get_mctrl(struct uart_port *port)
+{
+	/* FIXME */
+	dbg("%s\n", __FUNCTION__);
+	return 0;
+}
+
+static void ak880x_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	/* todo - possibly remove AFC and do manual CTS */
+	dbg("%s\n", __FUNCTION__);
+}
+
+static void ak880x_serial_stop_tx(struct uart_port *port)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+
+	/* dbg("%s\n", __FUNCTION__); */
+
+	if (tx_enabled(port)) {
+		uart_subint_disable(ourport, 1<<TX_END_INT_ENABLE);
+		tx_enabled(port) = 0;
+	}
+}
+
+static void ak880x_serial_start_tx(struct uart_port *port)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+
+	/* dbg("%s\n", __FUNCTION__); */
+
+	if (!tx_enabled(port)) {
+		uart_subint_enable(ourport, 1<<TX_END_INT_ENABLE);
+		tx_enabled(port) = 1;
+	}
+}
+
+static void ak880x_serial_stop_rx(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static void ak880x_serial_enable_ms(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static void ak880x_serial_break_ctl(struct uart_port *port, int break_state)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static irqreturn_t ak880x_uart_irqhandler(int irq, void *dev_id)
+{
+	struct ak880x_uart_port	*ourport = dev_id;
+	struct uart_port *port = &ourport->port;
+	struct circ_buf *xmit = &port->state->xmit;	//&port->info->xmit;
+	struct tty_struct *tty = port->state->port.tty;	//port->info->tty;
+	unsigned int flag= TTY_NORMAL;
+
+	unsigned char __iomem   *pbuf;
+	unsigned char *pxmitbuf;
+	unsigned long uart_status;
+	unsigned int rxcount = 0;
+	unsigned char ch = 0;
+	unsigned int i;
+	int txcount , tx_tail;
+	unsigned int l2_offset = 0;
+	unsigned long regval;
+
+	uart_status = __raw_readl(ourport->port.membase + UART_CONF2);
+
+	/* clear error */
+	if ( uart_intevent_decode(uart_status, RECVDATA_ERR_INT_ENABLE, RECVDATA_ERR_INT) )
+	{
+		dbg_irq("ak880x-uart: error occurs in received data\n");
+		uart_subint_clear(ourport, RECVDATA_ERR_INT);
+//		return IRQ_HANDLED;
+	}
+
+	if ( uart_intevent_decode(uart_status, TX_END_INT_ENABLE, TX_END_INT) )
+	{
+		/* if there isnt anything more to transmit, or the uart is now
+		 * stopped, disable the uart and exit
+		 */
+		if (uart_circ_empty(xmit) || uart_tx_stopped(port))
+		{
+			ak880x_serial_stop_tx(port);
+			goto ak880x_rx_irq;
+		}
+
+		txcount = uart_circ_chars_pending(xmit);
+
+		if(txcount > 32)
+			txcount = 32;
+		pbuf = ourport->txfifo_base;
+		pxmitbuf = xmit->buf;
+//		clear_uart_txbuf_status(ourport);
+
+		regval = __raw_readl(ourport->port.membase + UART_CONF1);
+		__raw_writel(regval | 0x1<<28, ourport->port.membase + UART_CONF1); /* clear the tx count reg */
+
+		__raw_writel(0x0, ourport->txfifo_base + 0x3C);	/*to inform the buf is full*/
+		l2_offset = 0;
+		tx_tail = xmit->tail;
+		regval = 0;
+		for(i = 0; i < txcount; i++)
+		{
+			regval |= pxmitbuf[tx_tail]<<((i & 3) * 8 );
+			if((i & 3) == 3)
+			{
+				__raw_writel(regval, pbuf + l2_offset);
+				l2_offset = l2_offset + 4;
+				regval = 0;
+			}
+			tx_tail = (tx_tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx += 1;
+		}
+		if(i & 3)
+		{
+			__raw_writel(regval, pbuf + l2_offset);
+		}
+
+		regval = (__raw_readl(ourport->port.membase + UART_CONF2) & 0xFFFE000F) | (txcount<< 4)  | (0x1<<16);
+		__raw_writel(regval, ourport->port.membase + UART_CONF2);
+		xmit->tail = tx_tail;
+
+		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+			uart_write_wakeup(port);
+
+		if (uart_circ_empty(xmit))
+			ak880x_serial_stop_tx(port);
+	}
+ak880x_rx_irq:
+
+
+	if ( uart_intevent_decode(uart_status, RXBUF_FULL_INT_ENABLE, RXBUF_FULL))
+	{
+		printk("%s: overflow\n", __func__);
+
+		/* FIXME: 1st, Read Rx Buf */
+
+		/* 2nd, set buf flag [access 15th byte] ?
+		 *
+		 */
+		clear_uart_rxbuf_status(ourport);
+
+		/* 3nd, clear irq */
+		uart_subint_clear(ourport, RXBUF_FULL);
+
+		__raw_readb(ourport->rxfifo_base + 0x3C);
+		__raw_readb(ourport->rxfifo_base + 0x7C);
+	}
+
+	/* rx threshold interrupt */
+	if ( uart_intevent_decode(uart_status, RX_THR_INT_ENABLE, RX_THR_INT) ||
+		uart_intevent_decode(uart_status, RX_TIMEOUT_INT_ENABLE, RX_TIMEOUT))
+	{
+		if ( uart_intevent_decode(uart_status, RX_THR_INT_ENABLE, RX_THR_INT))
+			uart_subint_clear(ourport, RX_THR_INT);
+		else
+			uart_subint_clear(ourport, RX_TIMEOUT);
+
+		ourport->nbr_to_read = (__raw_readl(ourport->port.membase + DATA_CONF)>>13) & 0x1F;
+		ourport->timeout_cnt = (__raw_readl(ourport->port.membase + DATA_CONF)>>23) & 0x3;
+
+
+		if (ourport->nbr_to_read  != ourport->rxfifo_offset)
+		{
+			l2_offset = (ourport->rxfifo_offset<<2) + ourport->rxbuf_offset;
+			pbuf = ourport->rxfifo_base + l2_offset;
+			if(l2_offset <= (ourport->nbr_to_read<<2))
+			{
+				rxcount = (ourport->nbr_to_read<<2) - l2_offset;
+				for (i=0; i<rxcount; i++)
+				{
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}
+			}
+			else
+			{
+				rxcount = 128 - l2_offset;
+
+				for (i=0; i<rxcount; i++)
+				{
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}
+
+				rxcount = ourport->nbr_to_read<<2;
+
+				pbuf = ourport->rxfifo_base;
+				for (i=0; i<rxcount; i++)
+				{
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}
+
+			}
+			ourport->rxbuf_offset = 0;
+			ourport->rxfifo_offset = ourport->nbr_to_read;
+		}
+
+
+		if(ourport->timeout_cnt != ourport->rxbuf_offset)
+		{
+			for (i = ourport->rxbuf_offset; i<ourport->timeout_cnt; i++)
+			{
+				ch = (__raw_readl(ourport->port.membase + UART_RXBUF) >> i*8) & 0xFF;
+				uart_insert_char(port, 0, 0, ch, flag);
+			}
+			ourport->rxbuf_offset = (ourport->timeout_cnt);
+		}
+
+	        tty_flip_buffer_push(tty);
+	}
+
+	return IRQ_HANDLED;
+
+}
+
+static void ak880x_serial_shutdown(struct uart_port *port)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+	unsigned int uart_reg = 0;
+
+	/*
+	 * 1st, free irq.
+	 * 2nd, disable/mask hw uart setting.
+	 * 3rd, close uart clock.
+	 */
+
+	uart_reg = __raw_readl(ourport->port.membase + 0xc);
+	uart_reg  &= (~(1<<5));
+	__raw_writel(uart_reg, ourport->port.membase + 0xc);
+
+	uart_reg = __raw_readl(ourport->port.membase + 0x0);
+	uart_reg  &= (~(1<<29));
+	__raw_writel(uart_reg, ourport->port.membase + 0x0);
+	uart_reg  &= (~1<<21);
+	__raw_writel(uart_reg, ourport->port.membase + 0x0);
+
+	rL2_CONBUF8_15 |= 1<<23;
+
+	free_irq(port->irq, ourport);
+	uart_enable_clock(ourport, 0);
+}
+
+/*
+ * 1, setup gpio.
+ * 2, enable clock.
+ * 3, request irq and setting up uart control.
+ * 4, enable subirq.
+ */
+static int ak880x_serial_startup(struct uart_port *port)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+	unsigned long uart_reg;
+	int ret;
+
+	if ( rx_enabled(port) && tx_enabled(port))
+		return 0;
+
+	uart_enable_clock(ourport, 1);
+	uart_hwport_init(ourport);
+
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF1);
+#if	defined(CONFIG_ARCH_AK7801)
+	uart_reg |= ((1<<21) | (1<<23) | (1<<28) | (1<<29));
+#elif	defined(CONFIG_ARCH_AK88)
+	uart_reg |= ((1<<21) | (1<<23) | (1<<24) | (1<<28) | (1<<29));
+#endif
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF1);
+
+	__raw_writel(0, ourport->port.membase + UART_CONF2);
+
+	/* set threshold to 4bytes */
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	uart_reg &= ~0x1F;
+	/* uart_reg |= (1<<5|1<<11); */
+	uart_reg |= (1<<11);
+
+#if	defined(CONFIG_ARCH_AK88)
+	__raw_writel(0, ourport->port.membase + RXBUF_THRESHOLD_EXT);
+//	uart_reg |= 0x3; /* 4 Bytes */
+//	__raw_writel(2, ourport->port.membase + RXBUF_THRESHOLD_EXT); //2 * 32byte
+	uart_reg |= 0x1F; /* 16 Bytes */
+#endif
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+
+	/* ourport->rxfifo_offset = 0; */
+	uart_clr_rx_status(ourport);
+	clear_uart_rxbuf_status(ourport);
+	ourport->rxfifo_offset = 0;
+#if	defined(CONFIG_ARCH_AK88)
+	ourport->rxbuf_offset = (__raw_readl(ourport->port.membase + DATA_CONF)>>23) & 0x3;
+#endif
+
+	/* clear count */
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	uart_reg |= (1<<5);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+	udelay(10);
+	uart_reg &= ~(1<<5);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+
+	ret = request_irq(port->irq, ak880x_uart_irqhandler,
+			IRQF_DISABLED, ourport->name, ourport);
+	if (ret) {
+		printk(KERN_ERR "can't request irq %d for %s\n", port->irq, ourport->name);
+		goto startup_err;
+	}
+
+	uart_reg = 0;
+	uart_reg |= 1<<RX_THR_INT_ENABLE|1<<RECVDATA_ERR_INT_ENABLE|1<<RXBUF_FULL_INT_ENABLE|1<<RX_TIMEOUT_INT_ENABLE| 1<<TX_END_INT_ENABLE ;
+//	uart_reg |= 1<<RX_THR_INT_ENABLE|1<<RECVDATA_ERR_INT_ENABLE|1<<RXBUF_FULL_INT_ENABLE|1<<RX_TIMEOUT_INT_ENABLE;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+
+	rx_enabled(port) = 1;
+	tx_enabled(port) = 1;
+//	tx_enabled(port) = 0;
+
+	ourport->rxfifo_offset =0;
+
+	return 0;
+
+startup_err:
+	ak880x_serial_shutdown(port);
+	return ret;
+}
+
+static void ak880x_serial_set_termios(struct uart_port *port,
+		struct ktermios *termios,
+		struct ktermios *old)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+	unsigned int baud;
+	unsigned long flags;
+	unsigned long regval;
+	unsigned long asic_clk;
+
+	asic_clk = 1000 * 1000 * clk_asic_getrate();
+	termios->c_cflag &= ~(HUPCL | CMSPAR);
+	termios->c_cflag |= CLOCAL;
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 * min: 2.4bps, max: 3Mbps
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 2400, 115200*26);
+#ifdef CONFIG_BOARD_AK8802EBOOK
+	if (port->line == 0)
+		baud = 12800;
+#endif
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* baudrate setting */
+	regval = ((asic_clk / baud - 1) & 0xFFFF);
+	if (asic_clk % baud)
+		regval |= (1<<22);
+
+#if	defined(CONFIG_ARCH_AK7801)
+	regval |= ((1<<21) | (1<<23) | (1<<28) | (1<<29));
+#elif	defined(CONFIG_ARCH_AK88)
+	regval |= ((1<<21) | (1<<23) | (1<<24) | (1<<28) | (1<<29));
+#endif
+
+	ourport->rxfifo_offset = 0;
+
+	/* flow control setting */
+	if(port->line != 0)
+	{
+		if((termios->c_cflag & CRTSCTS))
+		{
+			switch (port->line) {
+			case 1:
+				AK88_GPIO_UART1_FLOW(1);
+				break;
+			case 2:
+				AK88_GPIO_UART2_FLOW(1);
+				break;
+			case 3:
+				AK88_GPIO_UART3_FLOW(1);
+				break;
+			}
+			regval &= ~(1<<18|1<<19);
+		}
+		else
+		{
+			switch(port->line) {
+			case 1:
+				AK88_GPIO_UART1_FLOW(0);
+				break;
+			case 2:
+				AK88_GPIO_UART2_FLOW(0);
+				break;
+			case 3:
+				AK88_GPIO_UART3_FLOW(0);
+				break;
+			}
+			regval |= (1<<18|1<<19);
+		}
+	}
+
+	/* parity setting */
+	if (termios->c_cflag & PARENB) {
+		if (termios->c_cflag & PARODD)
+			regval |= (0x2<<25);
+		else
+			regval |= (0x3<<25);
+	}
+#ifdef CONFIG_BOARD_AK8802EBOOK
+	if (port->line == 0)
+		regval |= (0x2<<25); /* ps/2 protol employ odd parity */
+#endif
+
+
+	__raw_writel(regval, port->membase + UART_CONF1);
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/*
+	 * Which character status flags should we ignore?
+	 */
+	port->ignore_status_mask = 0;
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *ak880x_serial_type(struct uart_port *port)
+{
+	switch (port->type) {
+	case PORT_AK88:
+		return "AK88";
+	default:
+		return NULL;
+	}
+}
+
+static void ak880x_serial_release_port(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static int ak880x_serial_request_port(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+	return 0;
+}
+
+static void ak880x_serial_config_port(struct uart_port *port, int flags)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+
+	port->type = PORT_AK88;
+	ourport->rxfifo_offset = 0;
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int
+ak880x_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	dbg("%s\n", __FUNCTION__);
+
+	return 0;
+}
+
+
+static struct uart_ops ak880x_serial_ops = {
+	.pm             = ak880x_serial_pm,
+	.tx_empty       = ak880x_serial_tx_empty,
+	.get_mctrl      = ak880x_serial_get_mctrl,
+	.set_mctrl      = ak880x_serial_set_mctrl,
+	.stop_tx        = ak880x_serial_stop_tx,
+	.start_tx       = ak880x_serial_start_tx,
+	.stop_rx        = ak880x_serial_stop_rx,
+	.enable_ms      = ak880x_serial_enable_ms,
+	.break_ctl      = ak880x_serial_break_ctl,
+	.startup        = ak880x_serial_startup,
+	.shutdown       = ak880x_serial_shutdown,
+	.set_termios    = ak880x_serial_set_termios,
+	.type           = ak880x_serial_type,
+	.release_port   = ak880x_serial_release_port,
+	.request_port   = ak880x_serial_request_port,
+	.config_port    = ak880x_serial_config_port,
+	.verify_port    = ak880x_serial_verify_port,
+};
+
+
+static struct ak880x_uart_port ak880x_serial_ports[NR_PORTS] = {
+	[0] = {
+		.name = "uart0",
+		.rxfifo_base	= AK88_UART0_RXBUF_BASE,
+		.txfifo_base	= AK88_UART0_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak880x_serial_ports[0].port.lock),
+			.iotype		= UPIO_MEM,
+			.mapbase	= AK88_UART0_PA_BASE,
+			.membase	= AK88_UART0_BASE,
+			.irq		= IRQ_UART0,
+			.uartclk        = 0,
+			.fifosize       = 64,
+			.ops            = &ak880x_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line           = 0,
+		},
+	},
+	[1] = {
+		.name = "uart1",
+		.rxfifo_base	= AK88_UART1_RXBUF_BASE,
+		.txfifo_base	= AK88_UART1_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak880x_serial_ports[1].port.lock),
+			.iotype		= UPIO_MEM,
+			.mapbase	= AK88_UART1_PA_BASE,
+			.membase	= AK88_UART1_BASE,
+			.irq		= IRQ_UART1,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak880x_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 1,
+		},
+	},
+	[2] = {
+		.name = "uart2",
+		.rxfifo_base	= AK88_UART2_RXBUF_BASE,
+		.txfifo_base	= AK88_UART2_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak880x_serial_ports[2].port.lock),
+			.iotype		= UPIO_MEM,
+			.irq		= IRQ_UART2,
+			.mapbase	= AK88_UART2_PA_BASE,
+			.membase	= AK88_UART2_BASE,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak880x_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 2,
+		},
+	},
+	[3] = {
+		.name = "uart3",
+		.rxfifo_base	= AK88_UART3_RXBUF_BASE,
+		.txfifo_base	= AK88_UART3_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak880x_serial_ports[3].port.lock),
+			.iotype		= UPIO_MEM,
+			.irq		= IRQ_UART3,
+			.mapbase	= AK88_UART3_PA_BASE,
+			.membase	= AK88_UART3_BASE,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak880x_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 3,
+		},
+	}
+};
+
+
+
+static struct uart_driver ak880x_uart_drv = {
+	.owner		= THIS_MODULE,
+	.dev_name	= AK88_SERIAL_NAME,
+	.nr		= NR_PORTS,
+	.cons		= AK88_SERIAL_CONSOLE,
+	.driver_name	= AK88_SERIAL_NAME,
+	.major		= AK88_SERIAL_MAJOR,
+	.minor		= AK88_SERIAL_MINOR,
+};
+
+/* ak880x_serial_init_port
+ *
+ * initialise a single serial port from the platform device given
+ */
+static int ak880x_serial_init_port(struct ak880x_uart_port *ourport,
+		struct platform_device *platdev)
+{
+	struct uart_port *port = &ourport->port;
+
+	if (platdev == NULL)
+		return -ENODEV;
+
+	/* setup info for port */
+	port->dev = &platdev->dev;
+
+	ourport->clk = clk_get(port->dev, "asic_clk");
+
+	return 0;
+}
+
+
+
+static int ak880x_serial_probe(struct platform_device *dev)
+{
+	struct ak880x_uart_port *ourport;
+	int ret = 0;
+
+	ourport = &ak880x_serial_ports[dev->id];
+
+	dbg(KERN_INFO "%s: initialising port %s...\n", __FUNCTION__, ourport->name);
+
+	ret = ak880x_serial_init_port(ourport, dev);
+	if (ret < 0)
+		goto probe_err;
+
+	dbg("%s: adding port\n", __FUNCTION__);
+	uart_add_one_port(&ak880x_uart_drv, &ourport->port);
+	platform_set_drvdata(dev, &ourport->port);
+
+	return 0;
+
+probe_err:
+	return ret;
+}
+
+static int ak880x_serial_remove(struct platform_device *dev)
+{
+	return 0;
+}
+
+
+static struct platform_driver ak880x_serial_drv = {
+	.probe          = ak880x_serial_probe,
+	.remove         = ak880x_serial_remove,
+//	.suspend        = ak880x_serial_suspend,
+//	.resume         = ak880x_serial_resume,
+	.driver         = {
+		.name   = "ak880x-uart",
+		.owner  = THIS_MODULE,
+	},
+};
+
+
+
+/* module initialisation code */
+
+static int __init ak880x_serial_modinit(void)
+{
+	int ret;
+
+	printk("AK88 UART Driver, (c) 2010 ANYKA\n");
+
+	dbg("Enterring %s\n", __FUNCTION__);
+
+	ret = uart_register_driver(&ak880x_uart_drv);
+	if (ret < 0) {
+		printk(KERN_ERR "failed to register UART driver\n");
+		return -1;
+	}
+
+	platform_driver_register(&ak880x_serial_drv);
+
+	return 0;
+}
+
+static void __exit ak880x_serial_modexit(void)
+{
+	platform_driver_unregister(&ak880x_serial_drv);
+	uart_unregister_driver(&ak880x_uart_drv);
+}
+
+module_init(ak880x_serial_modinit);
+module_exit(ak880x_serial_modexit);
+
+#ifdef CONFIG_SERIAL_AK88_CONSOLE
+
+/* Console code */
+
+static struct uart_port *cons_uart;
+
+/*
+static int
+ak880x_serial_console_txrdy(struct uart_port *port)
+{
+	//TODO:
+}
+*/
+
+static void
+ak880x_serial_console_putchar(struct uart_port *port, int ch)
+{
+	struct ak880x_uart_port *ourport = to_ourport(port);
+
+	/*
+	 * printch(ch);
+	 */
+	ak880x_uart_putchar(ourport, ch);
+}
+
+static void
+ak880x_serial_console_write(struct console *co, const char *s,
+			     unsigned int count)
+{
+	uart_console_write(cons_uart, s, count, ak880x_serial_console_putchar);
+}
+
+static void __init
+ak880x_serial_get_options(struct uart_port *port, int *baud,
+			   int *parity, int *bits)
+{
+#if 0
+	unsigned long regval;
+	struct clk *clk;
+
+	*bits	= 8;
+
+	regval = __raw_readl(port->membase + UART_CONF1);
+
+	if (regval & 0x1<<26) {
+		if (regval & 0x1<<25)
+			*parity = 'e';
+		else
+			*parity = 'o';
+	}
+	else
+		*parity = 'n';
+
+	clk = clk_get(port->dev, "asic_clk");
+	if (!IS_ERR(clk) && clk != NULL)
+		*baud = clk_get_rate(clk) / ((regval & 0xFFFF) + 1);
+
+	printk("calculated baudrate: %d\n", *baud);
+#endif
+}
+
+static int __init
+ak880x_serial_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	dbg("ak880x_serial_console_setup: co=%p (%d), %s\n", co, co->index, options);
+
+	port = &ak880x_serial_ports[co->index].port;
+
+	/* is this a valid port */
+
+	if (co->index == -1 || co->index >= NR_PORTS)
+		co->index = 0;
+
+	dbg("ak880x_serial_console_setup: port=%p (%d)\n", port, co->index);
+
+	cons_uart = port;
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		ak880x_serial_get_options(port, &baud, &parity, &bits);
+
+	dbg("ak880x_serial_console_setup: baud %d\n", baud);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console ak880x_serial_console =
+{
+	.name		= AK88_SERIAL_NAME,
+	.device		= uart_console_device,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.write		= ak880x_serial_console_write,
+	.setup		= ak880x_serial_console_setup
+};
+
+
+/* ak880x_serial_initconsole
+ *
+ * initialise the console from one of the uart drivers
+*/
+static int ak880x_serial_initconsole(void)
+{
+	dbg("ak880x_serial_initconsole\n");
+
+	ak880x_serial_console.data = &ak880x_uart_drv;
+
+	register_console(&ak880x_serial_console);
+
+	return 0;
+}
+
+console_initcall(ak880x_serial_initconsole);
+
+#endif /* CONFIG_SERIAL_AK88_CONSOLE */
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("Anyka 880x Serial port driver");
diff --git a/drivers/serial/ak98_uart.c b/drivers/serial/ak98_uart.c
new file mode 100644
index 00000000000..ff7688add7d
--- /dev/null
+++ b/drivers/serial/ak98_uart.c
@@ -0,0 +1,1390 @@
+/*
+ * driver/serial/ak98_uart.c
+ */
+
+#if defined(CONFIG_SERIAL_AK98_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/sysrq.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include <asm/io.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/clock.h>
+#include <mach/regs-l2.h>
+#include <mach/map.h>
+#include "ak98_uart.h"
+
+extern void printch(char);
+extern void printascii(const char *);
+
+
+#if 0
+#define dbg(x...)	printk(x)
+#else
+#define dbg(x...)	do {} while(0)
+#endif
+
+#if 0
+#define dbg_irq(x...)	printk(x)
+#else
+#define dbg_irq(x...)	do {} while(0)
+#endif
+
+/* UART name and device definitions */
+#define NR_PORTS		4
+
+#define AK98_SERIAL_NAME	"ttySAK"
+#define AK98_SERIAL_MAJOR	204
+#define AK98_SERIAL_MINOR	64
+
+
+#ifdef CONFIG_SERIAL_AK98_CONSOLE
+
+static struct console ak98_serial_console;
+
+#define AK98_SERIAL_CONSOLE &ak98_serial_console
+#else
+#define AK98_SERIAL_CONSOLE NULL
+#endif
+
+struct ak98_uart_port {
+	char			*name;
+	struct uart_port	port;
+
+	unsigned char __iomem   *rxfifo_base;
+	unsigned char __iomem   *txfifo_base;
+
+	unsigned int		rxfifo_offset;
+	unsigned int		nbr_to_read;
+	unsigned int		timeout_cnt;
+
+	unsigned char		claimed;
+	struct clk		*clk;
+#ifdef CONFIG_CPU_FREQ
+	struct notifier_block freq_transition;
+#endif
+};
+
+/* macros to change one thing to another */
+#define tx_enabled(port)	((port)->unused[0])
+#define rx_enabled(port)	((port)->unused[1])
+
+static int uart_intevent_decode(unsigned long status, unsigned int maskbit, unsigned int statusbit)
+{
+	if ((status & 1<<maskbit) && (status & 1<<statusbit))
+		return 1;
+	else
+		return 0;
+}
+
+static inline void uart_subint_disable(struct ak98_uart_port *ourport, unsigned long mask)
+{
+	unsigned long uart_reg;
+	
+	/* disable tx_end interrupt */
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+	uart_reg &= ~mask;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+}
+
+static inline void uart_subint_enable(struct ak98_uart_port *ourport, unsigned long unmask)
+{
+	unsigned long uart_reg;
+
+	/* enable tx_end interrupt */
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+	uart_reg |= unmask;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+}
+
+static void uart_subint_clear(struct ak98_uart_port *ourport, unsigned int subint)
+{
+	unsigned long uart_reg;
+
+	switch (subint) {
+
+	case TX_THR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+	break;
+
+	case RX_THR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg &= AKUART_INT_MASK;
+		uart_reg |= (1<<subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+	
+	case RECVDATA_ERR_INT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg &= AKUART_INT_MASK;
+		uart_reg |= (0x1 << subint);
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+		break;
+
+	case RX_TIMEOUT:
+		uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+		uart_reg |= (0x1 << subint);
+		uart_reg &= ~( 0x1<<3 );
+		__raw_writel(uart_reg, ourport->port.membase + UART_CONF2); 
+		
+		/* start to receive data */
+		uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+		uart_reg |= (1 << 31);
+		__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);	
+		break;
+#if 0
+    case RXBUF_FULL:
+        uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+        uart_reg |= (1<<subint);
+        __raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+        break;
+#endif
+	default:
+		printk(KERN_ERR "ak98-uart: unkown subint type: %d\n", subint);
+		break;
+	}
+
+	return;
+}
+
+static inline struct ak98_uart_port *to_ourport(struct uart_port *port)
+{
+	return container_of(port, struct ak98_uart_port, port);
+}
+
+static inline void uart_txend_interrupt(struct ak98_uart_port *ourport, unsigned short status)
+{
+	unsigned long uart_reg;
+
+	/*handle Tx_end end interrupt */
+	uart_reg = __raw_readl(ourport->port.membase + UART_CONF2);
+	switch(status)
+	{
+		case ENABLE:
+			uart_reg |= (UARTN_CONFIG2_TX_END_INT_EN);
+			break;
+			
+		case DISABLE:
+			uart_reg &= ~(UARTN_CONFIG2_TX_END_INT_EN);
+			break;
+			
+		default:
+			break;
+	}
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+}
+
+/* clear a UARTn buffer status flag */
+static inline void clear_uart_buf_status(struct ak98_uart_port *ourport, unsigned short status)
+{
+    unsigned long regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
+	regval = __raw_readl(AK98_VA_L2CTRL + 0x8C);
+	switch(status)
+	{
+		case RX_STATUS: 
+			regval |= (0x1 << (17 + ourport->port.line * 2));
+			break;
+			
+		case TX_STATUS:
+			regval |= (0x1 << (16 + ourport->port.line * 2));
+			break;
+				
+		default:
+			break;
+    }
+	__raw_writel(regval,  AK98_VA_L2CTRL + 0x8C);
+
+	local_irq_restore(flags);
+}
+
+/* clear TX and RX internal status */
+static inline void clear_internal_status(struct ak98_uart_port *ourport, unsigned short status)
+{
+    unsigned long regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
+	regval = __raw_readl(ourport->port.membase + UART_CONF1);
+    switch(status)
+	{
+		case RX_STATUS:  
+			__raw_writel(regval | (0x1 << 29), ourport->port.membase + UART_CONF1);
+			break;
+
+		case TX_STATUS:
+			__raw_writel(regval | (0x1 << 28), ourport->port.membase + UART_CONF1);
+    		break;			
+			
+		default:
+			break;
+    }
+
+	local_irq_restore(flags);
+}
+
+/* clear TX_th and RX_th count interrupt */
+static inline void clear_Int_status(struct ak98_uart_port *ourport, unsigned short status)
+{
+    unsigned long regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
+	regval = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+    switch(status)
+	{
+		case RX_STATUS:  
+			__raw_writel(regval | (0x1 << 5), ourport->port.membase + BUF_THRESHOLD);
+			break;
+
+		case TX_STATUS:
+			__raw_writel(regval | (0x1 << 11), ourport->port.membase + BUF_THRESHOLD);
+    		break;			
+			
+		default:
+			break;
+    }
+
+	local_irq_restore(flags);
+}
+
+
+/* enable/disable interrupt of  RX_th */
+static inline void uart_Rx_interrupt(struct ak98_uart_port *ourport, unsigned short status)
+{
+    unsigned long regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	
+	regval = __raw_readl(ourport->port.membase + UART_CONF2);
+	if(status)
+		__raw_writel(regval | (0x1 << RX_INTTERUPT), ourport->port.membase + UART_CONF2);
+	else
+		__raw_writel(regval & ~(0x1 << RX_INTTERUPT), ourport->port.membase + UART_CONF2);
+
+	local_irq_restore(flags);
+}
+
+
+
+static inline int uart_hwport_init(struct ak98_uart_port *ourport)
+{
+	unsigned int regval = 0;
+
+	/* set share pin to UARTn, and disable pull-up */
+	switch (ourport->port.line) {
+	case 0:
+		ak98_group_config(ePIN_AS_UART1);
+#if 0
+		/* set share pin */
+        regval = __raw_readl(AK98_SHAREPIN_CON1);
+        regval |= (1<<9);
+        __raw_writel(regval, AK98_SHAREPIN_CON1);
+
+        /* enable ppu function */
+        regval = __raw_readl(AK98_PPU_PPD1);
+        regval &= ~(0x3<<14);
+        __raw_writel(regval, AK98_PPU_PPD1);
+#endif
+
+		/* 0x2002c08c: clear tx/rx buffer status flag */
+		rL2_CONBUF8_15 |= (0x3 << 16);
+		/* 0x2002c084: enable buffer status bit may be changed */		
+		rL2_FRACDMAADDR |= (0x1 << 29);
+		break;
+
+	case 1:
+		/* set share pin */
+		ak98_group_config(ePIN_AS_UART2);
+
+		regval = __raw_readl(AK98_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<14) | (0xF<<2));
+		regval |= (0x5<<2 | 0xF<<14);
+		__raw_writel(regval, AK98_VA_SYSCTRL+0xD4);
+
+		rL2_CONBUF8_15 |= (0x3 << 18);
+		rL2_FRACDMAADDR |= (0x1 << 29);
+		break;
+
+	case 2:
+		ak98_group_config(ePIN_AS_UART3);
+
+		regval = __raw_readl(AK98_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<18) | (0xF<<6));
+		regval |= (0x5<<6 | 0xF<<18);
+		__raw_writel(regval, AK98_VA_SYSCTRL+0xD4);
+		
+		rL2_CONBUF8_15 |= (0x3<<20);
+		rL2_FRACDMAADDR |= (0x1<<29);
+		break;
+
+	case 3:
+		ak98_group_config(ePIN_AS_UART4);
+		
+		regval = __raw_readl(AK98_VA_SYSCTRL+0xD4);
+		regval &= ~((0xF<<22) | (0xF<<10));
+		regval |= (0x5<<10 | 0xF<<22);
+		__raw_writel(regval, AK98_VA_SYSCTRL+0xD4);
+		
+		rL2_CONBUF8_15 |= (0x3<<22);
+		rL2_FRACDMAADDR |= (0x1<<29);
+		break;
+
+	default:
+		printk(KERN_ERR "unknown uart port\n");
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int uart_enable_clock(struct ak98_uart_port *ourport, int enable)
+{
+	unsigned long regval1, regval2;
+
+	regval2 = __raw_readl(AK98_VA_SYSCTRL + 0x10);
+
+	switch (ourport->port.line) {
+	case 0:
+		if (enable) {
+			regval1 = __raw_readl(AK98_VA_SYSCTRL + 0x0C);
+			regval1 &= ~(1 << 12);
+			__raw_writel(regval1, AK98_VA_SYSCTRL + 0x0C);
+		}
+		else {
+			regval1 = __raw_readl(AK98_VA_SYSCTRL + 0x0C);
+			regval1 |= (1 << 12); 
+			__raw_writel(regval1, AK98_VA_SYSCTRL + 0x0C);
+		}
+		return 0;
+	case 1:
+		if (enable)
+		{
+			regval2 &= ~(1 << 4);
+			regval2 &= ~(1 <<20);
+		}
+		else
+			regval2 |= (1 << 4);
+		break;
+
+	case 2:
+		if (enable)
+		{
+			regval2 &= ~(1 << 5);
+			regval2 &= ~(1 <<21);
+		}
+		else			
+			regval2 |= (1 << 5);
+		break;
+
+
+	case 3:
+		if (enable)
+		{
+			regval2 &= ~(1 << 6);
+			regval2 &= ~(1 <<22);
+		}
+		else
+			regval2 |= (1 << 6);
+		break;
+
+	default:
+		printk(KERN_ERR "unknown uart port\n");
+		return -1;
+	}
+	__raw_writel(regval2, AK98_VA_SYSCTRL + 0x10);
+
+	return 0;
+}
+
+/* power management control */
+static void ak98_serial_pm(struct uart_port *port, unsigned int level, unsigned int old)
+{
+	switch (level) {
+	case 3: /* disable */	
+		//dbg("%s: enterring pm level: %d\n", __FUNCTION__, level);
+		break;
+
+	case 0:	/* enable  */
+		//dbg("%s: enterring pm level: %d\n", __FUNCTION__, level);
+		break;
+
+	default:
+		dbg(KERN_ERR "ak98_serial: unknown pm %d\n", level);
+		break;
+	}
+}
+
+/* is tx fifo empty */
+static unsigned int ak98_serial_tx_empty(struct uart_port *port)
+{
+	unsigned long uart_reg;
+
+	uart_reg = __raw_readl(port->membase + UART_CONF2);
+
+	if (uart_reg & (1 << TXFIFO_EMPTY))
+		return 1;
+
+	return 0;
+}
+
+/* no modem control lines */
+static unsigned int ak98_serial_get_mctrl(struct uart_port *port)
+{
+	/* FIXME */
+	dbg("%s\n", __FUNCTION__);
+	return 0;
+}
+
+static void ak98_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	/* todo - possibly remove AFC and do manual CTS */
+	dbg("%s\n", __FUNCTION__);
+}
+
+
+static void ak98_serial_start_tx(struct uart_port *port)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+
+	dbg("%s\n", __FUNCTION__); 
+
+	if (!tx_enabled(port))
+	{
+		uart_txend_interrupt(ourport, ENABLE);
+		tx_enabled(port) = 1;
+	}
+}
+
+static void ak98_serial_stop_tx(struct uart_port *port)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+
+	dbg("%s\n", __FUNCTION__); 
+
+	if (tx_enabled(port))
+   	{
+   		uart_txend_interrupt(ourport, DISABLE);
+		tx_enabled(port) = 0;
+	}
+}
+
+static void ak98_serial_stop_rx(struct uart_port *port)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+
+	dbg("%s\n", __FUNCTION__);
+
+	if (rx_enabled(port))
+   	{
+		uart_Rx_interrupt(ourport, DISABLE);
+		rx_enabled(port) = 0;
+	}
+}
+
+static void ak98_serial_enable_ms(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static void ak98_serial_break_ctl(struct uart_port *port, int break_state)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static irqreturn_t ak98_uart_irqhandler(int irq, void *dev_id)
+{
+	struct ak98_uart_port	*ourport = dev_id;
+	struct uart_port *port = &ourport->port;
+	struct circ_buf *xmit = &port->state->xmit;	    //&port->info->xmit;
+	struct tty_struct *tty = port->state->port.tty;	//port->info->tty;
+	unsigned int flag= TTY_NORMAL;
+
+	unsigned char __iomem   *pbuf;
+	unsigned char *pxmitbuf;
+	unsigned long uart_status;
+	unsigned int rxcount = 0;
+	unsigned char ch = 0;
+	unsigned int i;
+	int txcount , tx_tail;
+	unsigned int l2_offset = 0;
+	unsigned long regval;
+
+	uart_status = __raw_readl(ourport->port.membase + UART_CONF2);
+
+	/* clear R_err interrupt */
+	if ( uart_intevent_decode(uart_status, RECVDATA_ERR_INT_ENABLE, RECVDATA_ERR_INT) )
+	{
+		dbg_irq("ak98-uart: error occurs in received data\n");
+		uart_subint_clear(ourport, RECVDATA_ERR_INT);
+	}
+
+	if ( uart_intevent_decode(uart_status, TX_END_INTERRUPT, TX_END_STATUS) )
+	{
+		/* if there is not anything more to transmit, or the uart is now
+		 * stopped, disable the uart and exit
+		 */
+		if (uart_circ_empty(xmit) || uart_tx_stopped(port))
+		{
+			ak98_serial_stop_tx(port);
+			goto ak98_rx_irq;
+		}
+
+		txcount = uart_circ_chars_pending(xmit);
+
+		if(txcount > 32)
+			txcount = 32;
+		pbuf = ourport->txfifo_base;
+		pxmitbuf = xmit->buf;
+
+		/* clear a uartx buffer status */
+		clear_uart_buf_status(ourport, TX_STATUS);
+
+		/* clear the tx internal status */
+		clear_internal_status(ourport, TX_STATUS);
+
+		__raw_writel(0x0, ourport->txfifo_base + 0x3C);
+
+		l2_offset = 0;
+		tx_tail = xmit->tail;
+		regval = 0;
+		for(i = 0; i < txcount; i++)
+		{
+			regval |= pxmitbuf[tx_tail]<<((i & 3) * 8 );
+			if((i & 3) == 3)
+			{
+				__raw_writel(regval, pbuf + l2_offset);
+				l2_offset = l2_offset + 4;
+				regval = 0;
+			}
+			tx_tail = (tx_tail + 1) & (UART_XMIT_SIZE - 1);
+			port->icount.tx += 1;
+		}
+		if(i & 3)
+		{
+			__raw_writel(regval, pbuf + l2_offset);
+		}
+
+		regval = (__raw_readl(ourport->port.membase + UART_CONF2)&(~UARTN_CONFIG2_TX_BYT_CNT_MASK)) | (UARTN_CONFIG2_TX_BYT_CNT(txcount))  | (UARTN_CONFIG2_TX_BYT_CNT_VLD);
+		__raw_writel(regval, ourport->port.membase + UART_CONF2);
+		xmit->tail = tx_tail;
+
+		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+			uart_write_wakeup(port);
+
+		if (uart_circ_empty(xmit))
+			ak98_serial_stop_tx(port);
+	}
+	
+ak98_rx_irq:
+
+	/* rx threshold interrupt */
+	if ( uart_intevent_decode(uart_status, RX_THR_INT_ENABLE, RX_THR_INT) ||
+		uart_intevent_decode(uart_status, RX_TIMEOUT_INT_ENABLE, RX_TIMEOUT))
+	{
+		if ( uart_intevent_decode(uart_status, RX_THR_INT_ENABLE, RX_THR_INT))
+			uart_subint_clear(ourport, RX_THR_INT);
+		else {
+			uart_subint_clear(ourport, RX_TIMEOUT);
+		}
+
+		while(__raw_readl(ourport->port.membase + UART_CONF2) & (UARTN_CONFIG2_MEM_RDY));
+		
+		ourport->nbr_to_read = (__raw_readl(ourport->port.membase + DATA_CONF)>>13) & 0x7f;
+
+		if (ourport->nbr_to_read  != ourport->rxfifo_offset) {
+			l2_offset = ourport->rxfifo_offset; 
+			pbuf = ourport->rxfifo_base + l2_offset;
+
+			/* copy data */
+			if (ourport->nbr_to_read > l2_offset) {
+            			rxcount = ourport->nbr_to_read - l2_offset;
+				for (i=0; i<rxcount; i++) {
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}	
+		        } else {
+				rxcount = (UART_RX_FIFO_SIZE - l2_offset);
+				for (i=0; i<rxcount; i++) {
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}
+			
+				pbuf = ourport->rxfifo_base;
+				for (i=0; i < ourport->nbr_to_read; i++) {
+					ch = __raw_readb(pbuf + i);
+					uart_insert_char(port, 0, 0, ch, flag);
+				}
+			}
+			ourport->rxfifo_offset = ourport->nbr_to_read;
+		}
+
+		tty_flip_buffer_push(tty);
+	}
+
+	return IRQ_HANDLED;
+
+}
+
+static void ak98_serial_shutdown(struct uart_port *port)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+	unsigned int uart_reg = 0;
+
+	/*
+	 * 1st, free irq.
+	 * 2nd, disable/mask hw uart setting.
+	 * 3rd, close uart clock.
+	 */
+	
+	/* mask all interrupt */
+	__raw_writel(0, ourport->port.membase + UART_CONF2);
+	
+	uart_reg = __raw_readl(ourport->port.membase + 0xc);
+	uart_reg  &= (~(1<<5));
+	__raw_writel(uart_reg, ourport->port.membase + 0xc);
+	uart_reg = __raw_readl(ourport->port.membase + 0x0);
+	uart_reg  &= (~(1<<29));
+	__raw_writel(uart_reg, ourport->port.membase + 0x0);
+	/* clear uartx interrupt */
+	uart_reg  &= (~1<<21);
+	__raw_writel(uart_reg, ourport->port.membase + 0x0);
+
+	/* clear uartn TX/RX buf status flag and call ak98_setpin_as_gpio() */
+	switch(ourport->port.line)
+	{
+		case 0:
+			rL2_CONBUF8_15 |= (0x3<<16);
+			break;
+		case 1:
+			rL2_CONBUF8_15 |= (0x3<<18);
+			break;
+		case 2:
+			rL2_CONBUF8_15 |= (0x3<<20);
+			break;
+		case 3:
+			rL2_CONBUF8_15 |= (0x3<<22);
+			break;
+	}	
+	free_irq(port->irq, ourport);	
+	uart_enable_clock(ourport, 0);
+}
+
+/*
+ * 1, setup gpio.
+ * 2, enable clock.
+ * 3, request irq and setting up uart control.
+ * 4, enable subirq.
+ */
+static int ak98_serial_startup(struct uart_port *port)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+	unsigned long uart_reg;
+	int ret;
+
+	if ( rx_enabled(port) && tx_enabled(port))
+		return 0;
+
+	/* enable uart clock */
+	uart_enable_clock(ourport, 1);
+	
+	/* set share pin to UARTn */
+	uart_hwport_init(ourport);
+
+	//clear L2 Buffer
+	clear_uart_buf_status(ourport, RX_STATUS);
+	
+	uart_reg = UARTN_CONFIG1_RTS_EN_BY_CIRCUIT | UARTN_CONFIG1_EN |UARTN_CONFIG1_RX_STA_CLR|UARTN_CONFIG1_TX_STA_CLR|UARTN_CONFIG1_TIMEOUT_EN;
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF1);
+
+	/* mask all interrupt */
+	__raw_writel(0, ourport->port.membase + UART_CONF2);
+
+	/*
+	 * config stop bit and timeout value
+	 * set timeout = 32, stop bit = 1;
+	 */
+	uart_reg = (0x1f << 16);
+	__raw_writel(uart_reg, ourport->port.membase + UART_STOPBIT_TIMEOUT);	
+
+
+   /* 
+      * set threshold to 32bytes 
+      * set RX_th_cfg_h = 0, set RX_th_cfg_l = 31
+      */
+	uart_reg = __raw_readl(ourport->port.membase + DATA_CONF);
+	uart_reg &= ~UARTN_RX_TH_CFG_H_MASK;
+	__raw_writel(uart_reg, ourport->port.membase + DATA_CONF);	
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+    uart_reg &= ~(UARTN_RX_TH_CFG_L_MASK);
+	uart_reg |= UARTN_RX_TH_CFG_L(0x1F);	/* 32 Bytes */
+	//uart_reg |= (1 << 11);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+	
+	clear_internal_status(ourport, RX_STATUS);
+
+	/* ourport->rxfifo_offset = 0; */
+	ourport->rxfifo_offset = 0;
+
+   	/* to clear  RX_th count interrupt */
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	uart_reg |= (UARTN_RX_TH_CLR);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+	udelay(10);
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	uart_reg &= ~(UARTN_RX_TH_CLR);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+		udelay(10);
+	uart_reg = __raw_readl(ourport->port.membase + BUF_THRESHOLD);
+	uart_reg |= (UARTN_RX_START);
+	__raw_writel(uart_reg, ourport->port.membase + BUF_THRESHOLD);
+	
+
+    /*
+	 *  enable timeout, rx mem_rdy and rx_th tx_end interrupt 
+	 */
+	 uart_reg = (UARTN_CONFIG2_RX_TH_INT_EN|UARTN_CONFIG2_RX_BUF_FULL_INT_EN|UARTN_CONFIG2_TIMEOUT_INT_EN|UARTN_CONFIG2_R_ERR_INT_EN);
+	__raw_writel(uart_reg, ourport->port.membase + UART_CONF2);
+
+	rx_enabled(port) = 1;
+	tx_enabled(port) = 0;
+
+	//ourport->rxfifo_offset =0;
+	
+	/* register interrupt */
+	ret = request_irq(port->irq, ak98_uart_irqhandler, IRQF_DISABLED, ourport->name, ourport);
+	if (ret) {
+		printk(KERN_ERR "can't request irq %d for %s\n", port->irq, ourport->name);
+		goto startup_err;
+	}
+	return 0;
+
+startup_err:
+	ak98_serial_shutdown(port);
+	return ret;
+}
+
+static void ak98_serial_set_termios(struct uart_port *port, 
+				struct ktermios *termios, struct ktermios *old)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+	unsigned int baud;
+	unsigned long flags;
+	unsigned long regval;
+	unsigned long asic_clk;
+
+	asic_clk = ak98_get_asic_clk();
+	termios->c_cflag &= ~(HUPCL | CMSPAR);
+	termios->c_cflag |= CLOCAL;
+
+	/*
+	 * Ask the core to calculate the divisor for us.
+	 * min: 2.4kbps, max: 2.4Mbps
+	 */
+	baud = uart_get_baud_rate(port, termios, old, 2400, 115200*20);
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* baudrate setting */
+	regval = __raw_readl(port->membase + UART_CONF1);
+	regval &= ~(0xffff);
+	regval &= ~(0x1 << 22);
+	regval |= ((asic_clk / baud - 1) & 0xffff);
+	regval |= (1 << 28) | (1 << 29);
+
+	if (asic_clk % baud)
+		regval |= (0x1 << 22);
+
+	ourport->rxfifo_offset = 0;
+
+	/* flow control setting */
+	if(port->line != 0)
+	{
+		if((termios->c_cflag & CRTSCTS)) /* directly */
+		{
+			switch (port->line) {
+			case 1:
+				AK98_GPIO_UART1_FLOW(1);
+				break;
+			case 2:
+				AK98_GPIO_UART2_FLOW(1);
+				break;
+			case 3:
+				AK98_GPIO_UART3_FLOW(1);
+				break;
+			}
+			regval &= ~(1<<18|1<<19);
+		}
+		else  /* inversly */
+		{
+			switch(port->line) {
+			case 1:
+				ak98_setpin_as_gpio(18);
+				break;
+			case 2:
+				ak98_setpin_as_gpio(22);
+				break;
+			case 3:
+				ak98_setpin_as_gpio(26);
+				break;
+			}
+			regval |= (1<<18|1<<19);
+		}
+	}
+
+	/* parity setting */
+	if (termios->c_cflag & PARENB) {
+		if (termios->c_cflag & PARODD)
+			regval |= (0x2 << 25);  /* odd parity */
+		else
+			regval |= (0x3 << 25);  /* evnt parity*/
+	}
+	__raw_writel(regval, port->membase + UART_CONF1);
+
+	/*
+	 * Update the per-port timeout.
+	 */
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	/*
+	 * Which character status flags should we ignore?
+	 */
+	port->ignore_status_mask = 0;
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static const char *ak98_serial_type(struct uart_port *port)
+{
+	switch (port->type) 
+	{
+		case PORT_AK98:
+			return "AK98";
+		default:
+			return NULL;
+	}
+}
+
+static void ak98_serial_release_port(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+}
+
+static int ak98_serial_request_port(struct uart_port *port)
+{
+	dbg("%s\n", __FUNCTION__);
+	return 0;
+}
+
+static void ak98_serial_config_port(struct uart_port *port, int flags)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+
+	port->type = PORT_AK98;
+	ourport->rxfifo_offset = 0;
+}
+
+/*
+ * verify the new serial_struct (for TIOCSSERIAL).
+ */
+static int
+ak98_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+	dbg("%s\n", __FUNCTION__);
+
+	return 0;
+}
+
+
+static struct uart_ops ak98_serial_ops = {
+	.pm             = ak98_serial_pm,
+	.tx_empty       = ak98_serial_tx_empty,
+	.get_mctrl      = ak98_serial_get_mctrl,
+	.set_mctrl      = ak98_serial_set_mctrl,
+	.stop_tx        = ak98_serial_stop_tx,
+	.start_tx       = ak98_serial_start_tx,
+	.stop_rx        = ak98_serial_stop_rx,
+	.enable_ms      = ak98_serial_enable_ms,
+	.break_ctl      = ak98_serial_break_ctl,
+	.startup        = ak98_serial_startup,
+	.shutdown       = ak98_serial_shutdown,
+	.set_termios    = ak98_serial_set_termios,
+	.type           = ak98_serial_type,
+	.release_port   = ak98_serial_release_port,
+	.request_port   = ak98_serial_request_port,
+	.config_port    = ak98_serial_config_port,
+	.verify_port    = ak98_serial_verify_port,
+};
+
+
+static struct ak98_uart_port ak98_serial_ports[NR_PORTS] = {
+	[0] = {
+		.name = "uart0",
+		.rxfifo_base	= AK98_UART0_RXBUF_BASE,
+		.txfifo_base	= AK98_UART0_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak98_serial_ports[0].port.lock),
+			.iotype		= UPIO_MEM,
+			.mapbase	= AK98_UART0_PA_BASE,
+			.membase	= AK98_UART0_BASE,
+			.irq		= IRQ_UART0,
+			.uartclk        = 0,
+			.fifosize       = 64,
+			.ops            = &ak98_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line           = 0,
+		},
+	#ifdef CONFIG_CPU_FREQ
+	.freq_transition = {
+			.priority = INT_MAX -1,
+		},
+	#endif
+	},
+	[1] = {
+		.name = "uart1",
+		.rxfifo_base	= AK98_UART1_RXBUF_BASE,
+		.txfifo_base	= AK98_UART1_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak98_serial_ports[1].port.lock),
+			.iotype		= UPIO_MEM,
+			.mapbase	= AK98_UART1_PA_BASE,
+			.membase	= AK98_UART1_BASE,
+			.irq		= IRQ_UART1,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak98_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 1,
+		},
+	},
+	[2] = {
+		.name = "uart2",
+		.rxfifo_base	= AK98_UART2_RXBUF_BASE,
+		.txfifo_base	= AK98_UART2_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak98_serial_ports[2].port.lock),
+			.iotype		= UPIO_MEM,
+			.irq		= IRQ_UART2,
+			.mapbase	= AK98_UART2_PA_BASE,
+			.membase	= AK98_UART2_BASE,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak98_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 2,
+		},
+	},
+	[3] = {
+		.name = "uart3",
+		.rxfifo_base	= AK98_UART3_RXBUF_BASE,
+		.txfifo_base	= AK98_UART3_TXBUF_BASE,
+		.port = {
+			.lock		= __SPIN_LOCK_UNLOCKED(ak98_serial_ports[3].port.lock),
+			.iotype		= UPIO_MEM,
+			.irq		= IRQ_UART3,
+			.mapbase	= AK98_UART3_PA_BASE,
+			.membase	= AK98_UART3_BASE,
+			.uartclk	= 0,
+			.fifosize	= 64,
+			.ops		= &ak98_serial_ops,
+			.flags		= UPF_BOOT_AUTOCONF,
+			.line		= 3,
+		},
+	}
+};
+
+static struct uart_driver ak98_uart_drv = {
+	.owner		= THIS_MODULE,
+	.dev_name	= AK98_SERIAL_NAME,
+	.driver_name	= AK98_SERIAL_NAME,
+	.nr			= NR_PORTS,
+	.major		= AK98_SERIAL_MAJOR,
+	.minor		= AK98_SERIAL_MINOR,
+	.cons		= AK98_SERIAL_CONSOLE,
+};
+
+#ifdef CONFIG_CPU_FREQ
+
+static int ak98_serial_cpufreq_transition(struct notifier_block *nb,
+    unsigned long val, void *data)
+{
+    struct ak98_uart_port *port;
+    struct uart_port *uport;
+
+    port = container_of(nb, struct ak98_uart_port, freq_transition);
+    uport = &port->port;
+
+    if(val == CPUFREQ_PRECHANGE){
+        /* we should really shut the port down whilst the
+		 * frequency change is in progress. */
+    }
+    else if(val == CPUFREQ_POSTCHANGE) {
+
+        struct ktermios *termios;
+        struct tty_struct *tty;
+
+        if (uport->state == NULL)
+            goto exit;
+
+        tty = uport->state->port.tty;
+        if (tty == NULL)
+            goto exit;
+
+        termios = tty->termios;
+        if (termios == NULL) {
+            printk(KERN_WARNING "%s: no termios?\n", __func__);
+            goto exit;
+        }
+
+        ak98_serial_set_termios(uport, termios, NULL);
+    }
+exit:
+    return 0;
+
+}
+
+static inline int ak98_serial_cpufreq_register(struct ak98_uart_port *port)
+{
+    port->freq_transition.notifier_call = ak98_serial_cpufreq_transition;
+
+    return cpufreq_register_notifier(&port->freq_transition,
+        CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void ak98_serial_cpufreq_unregister(struct ak98_uart_port *port)
+{
+    cpufreq_unregister_notifier(&port->freq_transition,
+        CPUFREQ_TRANSITION_NOTIFIER);
+}
+#else
+static inline int ak98_serial_cpufreq_register(struct ak98_uart_port *port)
+{
+    return 0;
+}
+
+static inline void ak98_serial_cpufreq_unregister(struct ak98_uart_port *port)
+{
+}
+
+#endif
+
+
+/* ak98_serial_init_port
+ *
+ * initialise a single serial port from the platform device given
+ */
+static int ak98_serial_init_port(struct ak98_uart_port *ourport,
+		struct platform_device *platdev)
+{
+	struct uart_port *port = &ourport->port;
+
+	if (platdev == NULL)
+		return -ENODEV;
+
+	/* setup info for port */
+	port->dev = &platdev->dev;
+
+	ourport->clk = clk_get(port->dev, "asic_clk");
+
+	return 0;
+}
+
+static int ak98_serial_probe(struct platform_device *dev)
+{
+	struct ak98_uart_port *ourport;
+	int ret = 0;
+
+	ourport = &ak98_serial_ports[dev->id];
+
+	dbg(KERN_INFO "%s: initialising port %s...\n", __FUNCTION__, ourport->name);
+
+	ret = ak98_serial_init_port(ourport, dev);
+	if (ret < 0)
+		goto probe_err;
+
+	uart_add_one_port(&ak98_uart_drv, &ourport->port);
+	
+	platform_set_drvdata(dev, &ourport->port);
+	
+	ret = ak98_serial_cpufreq_register(ourport);
+	if(ret < 0)
+		dev_err(&dev->dev, "faild to add cpufreq notifier\n");
+	return 0;
+
+probe_err:
+	return ret;
+}
+
+static int ak98_serial_remove(struct platform_device *dev)
+{
+	struct uart_port *port = (struct uart_port *)dev_get_drvdata(&dev->dev);
+
+	if (port) {		
+		ak98_serial_cpufreq_unregister(to_ourport(port));
+		uart_remove_one_port(&ak98_uart_drv, port);
+	}
+	return 0;
+}
+
+/* UART power management code */
+
+#ifdef CONFIG_PM
+
+static int ak98_serial_suspend(struct platform_device *dev, pm_message_t state)
+{
+	struct uart_port *port = (struct uart_port *)dev_get_drvdata(&dev->dev);
+
+	if (port) 
+		uart_suspend_port(&ak98_uart_drv, port);
+	return 0;
+}
+
+static int ak98_serial_resume(struct platform_device *dev)
+{
+	struct uart_port *port = (struct uart_port *)dev_get_drvdata(&dev->dev);
+
+	if (port) 	
+		uart_resume_port(&ak98_uart_drv, port);
+	return 0;
+}
+#else
+#define ak98_serial_suspend NULL
+#define ak98_serial_resume	NULL
+#endif
+
+static struct platform_driver ak98_serial_drv = {
+	.probe          = ak98_serial_probe,
+	.remove         = ak98_serial_remove,
+	.suspend        = ak98_serial_suspend,
+	.resume         = ak98_serial_resume,
+	.driver         = {
+		.name   = "ak98-uart",
+		.owner  = THIS_MODULE,
+	},
+};
+
+
+/* module initialisation code */
+static int __init ak98_serial_modinit(void)
+{
+	int ret;
+
+	printk("AK98 UART Driver, (c) 2010 ANYKA\n");
+
+	dbg("Enterring %s\n", __FUNCTION__);
+
+	//register 
+	ret = uart_register_driver(&ak98_uart_drv);
+	if (ret < 0) {
+		printk(KERN_ERR "failed to register UART driver\n");
+		return -1;
+	}
+
+	platform_driver_register(&ak98_serial_drv);
+
+	return 0;
+}
+
+static void __exit ak98_serial_modexit(void)
+{
+	dbg("Exit... %s\n", __FUNCTION__);
+
+	platform_driver_unregister(&ak98_serial_drv);
+	
+	uart_unregister_driver(&ak98_uart_drv);
+}
+
+module_init(ak98_serial_modinit);
+module_exit(ak98_serial_modexit);
+
+
+/************* Console code ************/
+#ifdef CONFIG_SERIAL_AK98_CONSOLE
+
+static struct uart_port *cons_uart;
+
+static inline void ak98_uart_putchar(struct ak98_uart_port *ourport, unsigned char ch)
+{
+	unsigned long regval;
+
+	/* clear the tx internal status */
+	clear_internal_status(ourport, TX_STATUS);
+
+	/* clear a uartx buffer status */
+	clear_uart_buf_status(ourport, TX_STATUS);
+
+	/*to inform the buf is full*/	
+	__raw_writel(ch, ourport->txfifo_base);
+	__raw_writel(0x0, ourport->txfifo_base + 0x3C);
+
+   	/* to clear  TX_th count interrupt */
+	clear_Int_status(ourport, TX_STATUS);
+
+	/* start to transmit */
+	regval = __raw_readl(ourport->port.membase + UART_CONF2);
+	regval &= AKUART_INT_MASK;
+	regval |= (0x1<<4) | (0x1<<16);
+	__raw_writel(regval, ourport->port.membase + UART_CONF2);
+	
+
+	/* wait for tx end */
+	while (!(__raw_readl(ourport->port.membase + UART_CONF2) & (1 << TX_END_STATUS)))
+		
+		;
+}
+
+static inline void ak98_wait_for_txend(struct ak98_uart_port *ourport)
+{
+	unsigned int timeout = 10000;
+
+	/*
+	 * Wait up to 10ms for the character(s) to be sent
+	 */
+    while (!(__raw_readl(ourport->port.membase + UART_CONF2) & (1 << TX_END_STATUS))) {
+        if (--timeout == 0)
+            break;
+        udelay(1);
+    }
+}
+
+static void
+ak98_serial_console_putchar(struct uart_port *port, int ch)
+{
+	struct ak98_uart_port *ourport = to_ourport(port);
+
+	ak98_wait_for_txend(ourport);
+
+	ak98_uart_putchar(ourport, ch);
+}
+
+static void
+ak98_serial_console_write(struct console *co, const char *s, unsigned int count)
+{
+	uart_console_write(cons_uart, s, count, ak98_serial_console_putchar);
+}
+
+static void __init
+ak98_serial_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
+{
+
+#if 0
+	unsigned long regval;
+	struct clk *clk;
+
+	*bits	= 8;
+
+	regval = __raw_readl(port->membase + UART_CONF1);
+
+	if (regval & 0x1<<26) {
+		if (regval & 0x1<<25)
+			*parity = 'e';
+		else
+			*parity = 'o';
+	}
+	else
+		*parity = 'n';
+
+	clk = clk_get(port->dev, "asic_clk");
+	if (!IS_ERR(clk) && clk != NULL)
+		*baud = clk_get_rate(clk) / ((regval & 0xFFFF) + 1);
+
+	printk("calculated baudrate: %d\n", *baud);
+#endif
+}
+
+
+static int __init
+ak98_serial_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	dbg("ak98_serial_console_setup: co=%p (%d), %s\n", co, co->index, options);
+
+	port = &ak98_serial_ports[co->index].port;
+
+	/* is this a valid port */
+
+	if (co->index == -1 || co->index >= NR_PORTS)
+		co->index = 0;
+
+	dbg("ak98_serial_console_setup: port=%p (%d)\n", port, co->index);
+
+	cons_uart = port;
+
+	/*
+	 * Check whether an invalid uart number has been specified, and
+	 * if so, search for the first available port that does have
+	 * console support.
+	 */
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+	else
+		ak98_serial_get_options(port, &baud, &parity, &bits);
+
+	dbg("ak98_serial_console_setup: baud %d\n", baud);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+
+static struct console ak98_serial_console = {
+	.name		= AK98_SERIAL_NAME,
+	.device		= uart_console_device,
+	.flags		= CON_PRINTBUFFER,
+	.index		= -1,
+	.write		= ak98_serial_console_write,
+	.setup		= ak98_serial_console_setup
+};
+
+
+/* ak98_serial_initconsole
+ *
+ * initialise the console from one of the uart drivers
+*/
+static int ak98_serial_initconsole(void)
+{
+	dbg("ak98_serial_initconsole\n");
+
+	ak98_serial_console.data = &ak98_uart_drv;
+
+	register_console(&ak98_serial_console);
+
+	return 0;
+}
+
+console_initcall(ak98_serial_initconsole);
+
+#endif /* CONFIG_SERIAL_AK98_CONSOLE */
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("Anyka 880x Serial port driver");
+
diff --git a/drivers/serial/ak98_uart.h b/drivers/serial/ak98_uart.h
new file mode 100644
index 00000000000..d83d14eb37e
--- /dev/null
+++ b/drivers/serial/ak98_uart.h
@@ -0,0 +1,126 @@
+#ifndef _ATHENA_AK98_UART_H_

+#define _ATHENA_AK98_UART_H_

+#define AK98_UART0_TXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1000)

+#define AK98_UART0_RXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1080)

+#define AK98_UART1_TXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1100)

+#define AK98_UART1_RXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1180)

+#define AK98_UART2_TXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1200)

+#define AK98_UART2_RXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1280)

+#define AK98_UART3_TXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1300)

+#define AK98_UART3_RXBUF_BASE	REG_VA_ADDR(AK98_VA_L2MEM, 0x1380)

+

+#define AK98_UART0_BASE			REG_VA_ADDR(AK98_VA_UART, 0x0000)

+#define AK98_UART1_BASE			REG_VA_ADDR(AK98_VA_UART, 0x1000)

+#define AK98_UART2_BASE			REG_VA_ADDR(AK98_VA_UART, 0x2000)

+#define AK98_UART3_BASE			REG_VA_ADDR(AK98_VA_UART, 0x3000)

+

+#define AK98_UART0_PA_BASE		REG_PA_ADDR(AK98_PA_UART, 0x0000)

+#define AK98_UART1_PA_BASE		REG_PA_ADDR(AK98_PA_UART, 0x1000)

+#define AK98_UART2_PA_BASE		REG_PA_ADDR(AK98_PA_UART, 0x2000)

+#define AK98_UART3_PA_BASE		REG_PA_ADDR(AK98_PA_UART, 0x3000)

+

+#define UART_CONF1			0x00

+#define	UART_CONF2			0x04

+#define	DATA_CONF			0x08

+#define	BUF_THRESHOLD		0x0C

+#define	UART_RXBUF			0x10

+#define UART_STOPBIT_TIMEOUT  (0x18)

+

+

+#define RX_THR_INT_ENABLE		(28)

+#define TX_END_INTERRUPT		(27)

+#define TXBUF_EMP_INT_ENABLE	(24)

+#define RECVDATA_ERR_INT_ENABLE	(23)

+#define RX_TIMEOUT_INT_ENABLE	(22)

+#define	MEM_RDY_INT_ENABLE		(21)

+#define TX_THR_INT			(31)

+#define RX_THR_INT			(30)

+#define	TX_END_STATUS		(19)

+#define	RX_OV				(18)

+#define	MEM_RDY_INT			(17)

+#define TX_BYT_CNT_VLD		(16)

+#define RECVDATA_ERR_INT	(3)

+#define	RX_TIMEOUT			(2)

+#define RXBUF_FULL			(1)

+#define TXFIFO_EMPTY		(0)

+

+#define TX_INTTERUPT		(29)

+#define RX_INTTERUPT		(28)

+

+#define	TX_STATUS		(1)

+#define	RX_STATUS		(0)

+#define DISABLE			(0)

+#define ENABLE			(1)

+#define	AKUART_INT_MASK		0x3FE00000

+#define UART_RX_FIFO_SIZE	128

+

+// Configuration Register 1 of UARTn

+#define UARTN_CONFIG1_DIV_CNT(cnt)          ((cnt) & 0xffff)

+#define UARTN_CONFIG1_UTD_INVERSELY         (1 << 16)

+#define UARTN_CONFIG1_URD_INVERSELY         (1 << 17)

+#define UARTN_CONFIG1_CTS_INVERSELY         (1 << 18)

+#define UARTN_CONFIG1_RTS_INVERSELY         (1 << 19)

+#define UARTN_CONFIG1_RTS_EN_BY_CIRCUIT     (1 << 20)

+#define UARTN_CONFIG1_EN                    (1 << 21)

+#define UARTN_CONFIG1_DIV_ADJ_EN            (1 << 22)

+#define UARTN_CONFIG1_TIMEOUT_EN            (1 << 23)

+#define UARTN_CONFIG1_PAR_EVEN              (1 << 25)

+#define UARTN_CONFIG1_PAR_EN                (1 << 26)

+#define UARTN_CONFIG1_ENDIAN_BIG            (1 << 27)

+#define UARTN_CONFIG1_TX_STA_CLR            (1 << 28)

+#define UARTN_CONFIG1_RX_STA_CLR            (1 << 29)

+#define UARTN_RX_ADDR_CLR					(1 << 30)

+#define UARTN_TX_ADDR_CLR					(1 << 31)

+

+// Configuration Register 2 of UARTn

+#define UARTN_CONFIG2_TX_FIFO_EMPTY         (1 << 0)  // read only

+#define UARTN_CONFIG2_RX_BUF_FULL           (1 << 1)  // write clear

+#define UARTN_CONFIG2_TIMEOUT               (1 << 2)  // write clear

+#define UARTN_CONFIG2_R_ERR                 (1 << 3)  // write clear

+#define UARTN_CONFIG2_TX_BYT_CNT(cnt)       (cnt << 4)

+#define UARTN_CONFIG2_TX_BYT_CNT_MASK       (0xfff << 4)

+#define UARTN_CONFIG2_TX_BYT_CNT_VLD        (1 << 16) // auto clear

+#define UARTN_CONFIG2_MEM_RDY               (1 << 17) // read only

+

+#define UARTN_CONFIG2_TX_END                (1 << 19) // read only

+

+#define UARTN_CONFIG2_RX_BUF_FULL_INT_EN        (1 << 21)

+#define UARTN_CONFIG2_TIMEOUT_INT_EN        (1 << 22)

+#define UARTN_CONFIG2_R_ERR_INT_EN          (1 << 23)

+#define UARTN_CONFIG2_TX_BUF_EMP_INT_EN     (1 << 24)

+

+#define UARTN_CONFIG2_TX_END_INT_EN         (1 << 27)

+#define UARTN_CONFIG2_RX_TH_INT_EN          (1 << 28)

+#define UARTN_CONFIG2_TX_TH_INT_EN          (1 << 29)

+

+#define UARTN_CONFIG2_RX_TH_STA             (1 << 30) // write clear

+#define UARTN_CONFIG2_TX_TH_STA             (1 << 31) // write clear

+

+// Data Configuration Register of UARTn

+#define UARTN_DATACONFIG_TX_BYT_SUM(rval)   	((rval) & 0x1FFF)

+#define UARTN_DATACONFIG_RX_ADR(rval)       	(((rval) >> 13) & 0x7F)

+#define UARTN_DATACONFIG_TX_ADR(rval)       	(((rval) >> 20) & 0x1F)

+#define UARTN_RX_TH_CFG_H_MASK              	(0x7f >> 25)

+#define UARTN_RX_TH_CFG_H(value)              (((value & 0x7f) >> 25))

+

+

+// TX RX Data Threshold Resgister

+#define UARTN_RX_TH_CFG_L_MASK             (0x1f)

+#define UARTN_RX_TH_CFG_L(value)              (value)

+

+#define UARTN_RX_TH_CLR                     (1 << 5)

+#define UARTN_TX_TH_CFG(value)              (((value) & 0x1f) << 6)

+#define UARTN_TX_TH_CLR                     (1 << 11)

+#define UARTN_RX_TH_CNT(rvalue)             (((rvalue) >> 12) & 0xFFF)   // read only

+#define UARTN_TX_TH_CNT(rvalue)             (((rvalue) >> 24) & 0x1F)   // read only

+#define UARTN_BFIFO_BYTE_NUM(rvalue)		(((rvalue) >> 29) & 0x03)   // read only

+#define UARTN_RX_START						(1 <<31)

+

+

+//Stop Bit Timeout Configuration Register

+

+#define UARTN_BIT_CFG(value)              ((value) & 0x1ff)

+#define UARTN_TIME_OUT_CFG(value)              (((value) >> 16) & 0x0ffff)

+

+

+#endif

diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index dcc72444e8e..47ad0cb20e4 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -94,6 +94,9 @@ static void __uart_start(struct tty_struct *tty)
 	struct uart_state *state = tty->driver_data;
 	struct uart_port *port = state->uart_port;
 
+	if (port->ops->wake_peer)
+		port->ops->wake_peer(port);
+
 	if (!uart_circ_empty(&state->xmit) && state->xmit.buf &&
 	    !tty->stopped && !tty->hw_stopped)
 		port->ops->start_tx(port);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4b6f7cba3b3..208d96a576a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -244,6 +244,18 @@ config SPI_XILINX
 	  See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
 	  Product Specification document (DS464) for hardware details.
 
+config SPI_AK88
+	tristate "AK88 SPI controller"
+	depends on SPI_MASTER && ARCH_AK88
+	select SPI_BITBANG
+	help
+	  SPI driver for ak88 ARM SoCs
+config SPI_AK98
+     tristate "AK98 SPI controller"
+     depends on SPI_MASTER && ARCH_AK98
+     select SPI_BITBANG
+     help
+       SPI driver for ak98 ARM SoCs
 #
 # Add new SPI master controllers in alphabetical order above this line
 #
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 21a118269ca..5babe442516 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,8 @@ obj-$(CONFIG_SPI_TXX9)			+= spi_txx9.o
 obj-$(CONFIG_SPI_XILINX)		+= xilinx_spi.o
 obj-$(CONFIG_SPI_SH_SCI)		+= spi_sh_sci.o
 obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
+obj-$(CONFIG_SPI_AK88)		+= spi_ak88.o
+obj-$(CONFIG_SPI_AK98)      += spi_ak98.o
 # 	... add above this line ...
 
 # SPI protocol drivers (device/link on bus)
diff --git a/drivers/spi/spi_ak88.c b/drivers/spi/spi_ak88.c
new file mode 100644
index 00000000000..49c8271d72c
--- /dev/null
+++ b/drivers/spi/spi_ak88.c
@@ -0,0 +1,584 @@
+/*
+ * drivers/spi/spi_ak880x.c
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+
+#include <mach/spi.h>
+#include <mach/gpio.h>
+
+/* #define DEBUG */
+#ifdef DEBUG
+#define pk_debug(fmt, arg...)	printk(fmt,##arg)
+#else
+#define pk_debug(fmt, arg...)
+#endif
+
+
+struct ak880x_spi {
+	/* bitbang has to be first */
+	struct spi_bitbang	 bitbang;
+	struct completion	 done;
+
+	void __iomem		*regs;
+	int			 irq;
+	int			 len;
+	int			 count;
+
+	void			(*set_cs)(struct ak880x_spi_info *spi, int cs, int pol);
+
+	/* data buffers */
+	const unsigned char	*tx;
+	unsigned char		*rx;
+
+	struct clk		*clk;
+	struct resource		*ioarea;
+	struct spi_master	*master;
+	struct spi_device	*curdev;
+	struct device		*dev;
+	struct ak880x_spi_info	*pdata;
+};
+
+#define SPICON_DEFAULT	(AK88_SPICON_MS | AK88_SPICON_CLKDIV)
+#define SPIINT_DEFAULT	(AK88_SPIINT_RXHFULL | AK88_SPIINT_TXHFULL)
+
+static inline struct ak880x_spi *to_hw(struct spi_device *sdev)
+{
+		return spi_master_get_devdata(sdev->master);
+}
+
+static void ak880x_spi_chipsel(struct spi_device *spi, int value)
+{
+	struct ak880x_spi *hw = to_hw(spi);
+	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
+	unsigned int spicon;
+
+	pk_debug("***%s******\n", __FUNCTION__);
+
+	switch(value) {
+		case BITBANG_CS_INACTIVE:
+			hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
+			break;
+		case BITBANG_CS_ACTIVE:
+			spicon = ioread32(hw->regs + AK88_SPICON);
+			if (spi->mode & SPI_CPHA)
+				spicon |= AK88_SPICON_CPHA;
+			else
+				spicon &= ~AK88_SPICON_CPHA;
+
+			if (spi->mode & SPI_CPOL)
+				spicon |= AK88_SPICON_CPOL;
+			else
+				spicon &= ~AK88_SPICON_CPOL;
+			
+			iowrite32(spicon, hw->regs + AK88_SPICON);
+			hw->set_cs(hw->pdata, spi->chip_select, cspol);
+			break;
+	}
+
+}
+
+static int ak880x_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak880x_spi *hw = to_hw(spi);
+	unsigned int bpw;
+	unsigned int hz;
+	unsigned int div;
+	unsigned int spicon;
+
+	pk_debug("***%s******\n", __FUNCTION__);
+
+	bpw = t ? t->bits_per_word : spi->bits_per_word;
+	hz  = t ? t->speed_hz : spi->max_speed_hz;
+
+	div = clk_get_rate(hw->clk)*1000*1000 / hz;
+	div = div/2 - 1;
+
+	if (div > 255)
+		div = 255;
+
+	spicon = ioread32(hw->regs + AK88_SPICON);
+	iowrite32((div << 8) | (spicon & ~(0xff<<8)), hw->regs + AK88_SPICON);
+
+	spin_lock(&hw->bitbang.lock);
+	if (!hw->bitbang.busy) {
+		hw->bitbang.chipselect(spi, BITBANG_CS_ACTIVE);
+		/* need to ndelay for 0.5 clocktick ? */
+	}
+	spin_unlock(&hw->bitbang.lock);
+
+	return 0;
+}
+
+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
+static int ak880x_spi_setup(struct spi_device *spi)
+{
+	int ret;
+
+	pk_debug("***%s******\n", __FUNCTION__);
+
+	if (!spi->bits_per_word)
+		spi->bits_per_word = 32;
+
+	if (spi->mode & ~MODEBITS) {
+		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
+			spi->mode & ~MODEBITS);
+		return -EINVAL;
+	}
+
+	ret = ak880x_spi_setupxfer(spi, NULL);
+	if (ret < 0) {
+		dev_err(&spi->dev, "setupxfer returned %d\n", ret);
+		return ret;
+	}
+
+	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
+		__FUNCTION__, spi->mode, spi->bits_per_word,
+		spi->max_speed_hz);
+
+	return 0;
+}
+
+#if 0
+static inline unsigned int hw_txbyte(struct ak880x_spi *hw, int count)
+{
+		//return hw->tx ? hw->tx[count] : 0;
+		return hw->tx ? *(int*)(hw->tx+count) : 0;
+}
+#endif
+
+static inline void ak880x_spi_setirq(int type, int sw)
+{
+	if (sw) {
+		rSPI1_INTEN |= type;
+	} else {
+		rSPI1_INTEN &= (~type);
+	}
+}
+	
+
+#if 0
+static void read_id(void)
+{
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x30;
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x38;
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x38;
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x38;
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x38;
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+}
+#endif
+
+static int ak880x_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak880x_spi *hw = to_hw(spi);
+	u32 spicon = ioread32(hw->regs + AK88_SPICON);
+
+	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
+		t->tx_buf, t->rx_buf, t->len);
+
+	hw->tx = t->tx_buf;
+	hw->rx = t->rx_buf;
+	hw->len = t->len;
+	hw->count = 0;
+
+	if (!hw->tx) { /* read only */
+		/* spicon = ioread32(hw->regs + AK88_SPICON); */
+	} else if (!hw->rx) {/* write only */
+		/* spicon = ioread32(hw->regs + AK88_SPICON); */
+		iowrite32(spicon, hw->regs + AK88_SPICON);
+		iowrite32(spicon | AK88_SPICON_ARRM | AK88_SPICON_CS, hw->regs + AK88_SPICON);
+		iowrite32(hw->len, hw->regs + AK88_SPICNT);
+		iowrite32(*(int*)hw->tx, hw->regs + AK88_SPIOUT);
+		while (ioread32(hw->regs + AK88_SPISTA) & AK88_SPISTA_MPROC);
+		mdelay(1);
+		iowrite32(spicon, hw->regs + AK88_SPICON);
+	} else {
+		/* spicon = ioread32(hw->regs + AK88_SPICON); */
+		iowrite32(spicon & ~(AK88_SPICON_TGDM | AK88_SPICON_ARRM), hw->regs + AK88_SPICON);
+	}
+
+#if 0
+	mdelay(1);
+	rSPI1_CON |= (1<<5);
+	mdelay(1);
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0x08;
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	mdelay(1);
+	/* printk("in: 0x%x\n", rSPI1_INDATA); */
+	rSPI1_COUNT = 1;
+	rSPI1_OUTDATA = 0xff;
+	mdelay(1);
+	printk("in: 0x%x\n", rSPI1_INDATA);
+	mdelay(1);
+	rSPI1_CON &= ~(1<<5);
+#endif
+
+	pk_debug("rSPI1_CON = 0x%x,\trSPI1_COUNT = 0x%x,\trSPI1_INTEN = 0x%x,\t rCLK_CON = 0x%x,\t extx: %x,\t exrx: %x,\t rSPI1_STAT = 0x%x\n",
+		       	rSPI1_CON, rSPI1_COUNT, rSPI1_INTEN, rCLK_CON, rSPI1_TXBUF, rSPI1_RXBUF, rSPI1_STAT);
+
+	/* wait_for_completion(&hw->done); */
+
+	/* iowrite32(spicon & ~(AK88_SPICON_TGDM | AK88_SPICON_ARRM | AK88_SPICON_CS), hw->regs + AK88_SPICON); */
+	
+	return hw->count;
+}
+
+static irqreturn_t ak880x_spi_irq(int irq, void *dev)
+{
+	u32 n;
+	struct ak880x_spi *hw = dev;
+
+#if 0
+	n = (hw->len >= 4) ? 4 : hw->len;
+
+	/* iowrite32(n, hw->regs + AK88_SPICNT); */
+
+	if (hw->tx) {
+		iowrite32(hw->len, hw->regs + AK88_SPICNT); /* one byte one time */
+		/* iowrite32(n, hw->regs + AK88_SPICNT); */
+		/* iowrite32(*(int*)(hw->tx + hw->count), hw->regs + AK88_SPIOUT); */
+		iowrite32(hw->tx[0], hw->regs + AK88_SPIOUT);
+		printk("n: %d, len: %d, count: %d, hw->tx[0]: %x\n", n, hw->len, hw->count,  hw->tx[0]);
+	}
+		
+
+	if (hw->rx) {
+		iowrite32(hw->len, hw->regs + AK88_SPICNT); /* one byte one time */
+		iowrite32(0xffffffff, hw->regs + AK88_SPIOUT);
+		printk("\n***rSPI1_INDATA : 0x%x***\n", rSPI1_INDATA);
+		if (n == 4) {
+			*(int*)(hw->rx+hw->count) = ioread32(hw->regs + AK88_SPIIN);
+		} else {
+			int tmp = ioread32(hw->regs + AK88_SPIIN);
+			memcpy(hw->rx + hw->count, (char*)&tmp, n);
+		}
+	}
+
+	hw->count += n;
+	hw->len -= n;
+
+	while (rSPI1_COUNT);
+
+#endif
+	if (!hw->len) {
+		/* disable_irq(hw->irq); */
+		ak880x_spi_setirq(AK88_SPIINT_TXHEMP, 0);
+		ak880x_spi_setirq(AK88_SPIINT_RXHFULL, 0);
+		ak880x_spi_setirq(AK88_SPIINT_TIMEOUT, 0);
+		ak880x_spi_setirq(AK88_SPIINT_RXEMP, 0);
+		complete(&hw->done);
+	}
+	pk_debug("rSPI1_COUNT : 0x%x,\t rSPI1_STAT : 0x%x\n", rSPI1_COUNT, rSPI1_STAT);
+
+	return IRQ_HANDLED;
+}
+
+static void ak880x_spi_gpiocs(struct ak880x_spi_info *spi, int cs, int pol)
+{
+	/* ak880x_gpio_setpin(spi->pin_cs, pol); */
+}
+
+static int __init ak880x_spi_probe(struct platform_device *pdev)
+{
+	struct ak880x_spi *hw;
+	struct spi_master *master;
+	struct resource *res;
+	int err = 0;
+	unsigned int spicon = 0;
+	unsigned int spiint = 0;
+
+	master = spi_alloc_master(&pdev->dev, sizeof(struct ak880x_spi));
+	if (master == NULL) {
+		dev_err(&pdev->dev, "No memory for spi_master\n");
+		err = -ENOMEM;
+		goto err_nomem;
+	}
+	hw = spi_master_get_devdata(master);
+	memset(hw, 0, sizeof(struct ak880x_spi));
+
+	hw->master = spi_master_get(master);
+	hw->pdata = pdev->dev.platform_data;
+	hw->dev = &pdev->dev;
+
+
+	if (hw->pdata == NULL) {
+		dev_err(&pdev->dev, "No platform data supplied\n");
+		err = -ENOENT;
+		goto err_no_pdata;
+	}
+
+	platform_set_drvdata(pdev, hw);
+	init_completion(&hw->done);
+
+	/* setup the state for the bitbang driver */
+
+
+	hw->bitbang.master         = hw->master;
+	hw->bitbang.setup_transfer = ak880x_spi_setupxfer;
+	hw->bitbang.chipselect     = ak880x_spi_chipsel;
+	hw->bitbang.txrx_bufs      = ak880x_spi_txrx;
+	hw->bitbang.master->setup  = ak880x_spi_setup;
+
+	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
+
+	/* find and map our resources */
+#if 1
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+		err = -ENOENT;
+		goto err_no_iores;
+	}
+
+	hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
+					pdev->name);
+	if (hw->ioarea == NULL) {
+		dev_err(&pdev->dev, "Cannot reserve region\n");
+		err = -ENXIO;
+		goto err_no_iores;
+	}
+
+	hw->regs = ioremap(res->start, (res->end - res->start)+1);
+	if (hw->regs == NULL) {
+		dev_err(&pdev->dev, "Cannot map IO\n");
+		err = -ENXIO;
+		goto err_no_iomap;
+	}
+
+	hw->irq = platform_get_irq(pdev, 0);
+	if (hw->irq < 0) {
+		dev_err(&pdev->dev, "No IRQ specified\n");
+		err = -ENOENT;
+		goto err_no_irq;
+	}
+
+	err = request_irq(hw->irq, ak880x_spi_irq, 0, pdev->name, hw);
+	if (err < 0) {
+		dev_err(&pdev->dev, "Cannot claim IRQ\n");
+		goto err_no_irq;
+	}
+	/* disable_irq(hw->irq); */
+
+	hw->clk = clk_get(&pdev->dev, "spi_clk");
+	if (IS_ERR(hw->clk)) {
+		dev_err(&pdev->dev, "No clock for device\n");
+		err = PTR_ERR(hw->clk);
+		goto err_no_clk;
+	} 
+	/* for the moment, permanently enable the clock */
+	clk_enable(hw->clk);
+
+#endif
+	/* program defaults into the registers */
+	spicon = AK88_SPICON_CLKDIV
+		| AK88_SPICON_EN 
+		| AK88_SPICON_MS 
+		| AK88_SPICON_CPHA
+//		| AK88_SPICON_ARRM 
+//		| AK88_SPICON_TGDM
+		;
+
+	iowrite32(spicon, hw->regs + AK88_SPICON);
+	
+	//spiint = AK88_SPIINT_RXEMP | AK88_SPIINT_TXHEMP;
+	/* spiint = AK88_SPIINT_TXHEMP; */
+	spiint = 0;
+	iowrite32(spiint, hw->regs + AK88_SPIINT);
+
+#define IRQ_MASK_SPI1 (1<<18);
+	//rIRQ_MASK |= IRQ_MASK_SPI1;
+	
+	pk_debug("rSPI1_CON = 0x%x,\trSPI1_COUNT = 0x%x,\trSPI1_INTEN = 0x%x,\t rCLK_CON = 0x%x,\t rSPI1_STAT = 0x%x\n",
+		       	rSPI1_CON, rSPI1_COUNT, rSPI1_INTEN, rCLK_CON, rSPI1_STAT);
+
+	/* setup any gpio we can */
+	hw->set_cs = ak880x_spi_gpiocs;
+
+	/* register our spi controller */
+
+	master->num_chipselect = 1;
+	err = spi_bitbang_start(&hw->bitbang);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register SPI master\n");
+		goto err_register;
+	}
+
+	//enable_irq(hw->irq);
+	return 0;
+
+ err_register:
+	clk_disable(hw->clk);
+	clk_put(hw->clk);
+
+ err_no_clk:
+	free_irq(hw->irq, hw);
+
+ err_no_irq:
+	iounmap(hw->regs);
+
+ err_no_iomap:
+	release_resource(hw->ioarea);
+	kfree(hw->ioarea);
+
+ err_no_iores:
+ err_no_pdata:
+	spi_master_put(hw->master);;
+
+ err_nomem:
+	return err;
+}
+
+static int ak880x_spi_remove(struct platform_device *dev)
+{
+	struct ak880x_spi *hw = platform_get_drvdata(dev);
+
+	platform_set_drvdata(dev, NULL);
+
+	spi_unregister_master(hw->master);
+
+	clk_disable(hw->clk);
+	clk_put(hw->clk);
+
+	free_irq(hw->irq, hw);
+	iounmap(hw->regs);
+
+	release_resource(hw->ioarea);
+	kfree(hw->ioarea);
+
+	spi_master_put(hw->master);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int ak880x_spi_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+	struct ak880x_spi *hw = platform_get_drvdata(pdev);
+
+	clk_disable(hw->clk);
+	return 0;
+}
+
+static int ak880x_spi_resume(struct platform_device *pdev)
+{
+	struct ak880x_spi *hw = platform_get_drvdata(pdev);
+
+	clk_enable(hw->clk);
+	return 0;
+}
+
+#else
+#define ak880x_spi_suspend NULL
+#define ak880x_spi_resume  NULL
+#endif
+
+MODULE_ALIAS("platform:ak880x_spi");
+static struct platform_driver ak880x_spidrv = {
+	.remove		= __exit_p(ak880x_spi_remove),
+	.suspend	= ak880x_spi_suspend,
+	.resume		= ak880x_spi_resume,
+	.driver		= {
+		.name	= "ak7801-spi",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init ak880x_spi_init(void)
+{
+	printk("AK88 SPI Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_probe(&ak880x_spidrv, ak880x_spi_probe);
+}
+
+static void __exit ak880x_spi_exit(void)
+{
+	platform_driver_unregister(&ak880x_spidrv);
+}
+
+module_init(ak880x_spi_init);
+module_exit(ak880x_spi_exit);
+
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("AK88 spi support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/spi/spi_ak98.c b/drivers/spi/spi_ak98.c
new file mode 100755
index 00000000000..df76bfa5634
--- /dev/null
+++ b/drivers/spi/spi_ak98.c
@@ -0,0 +1,959 @@
+/* linux/drivers/spi/spi_ak98.c
+ *  modify based on  spi_s3c24xx.c
+ *
+ * Copyright (c) 2006 Ben Dooks
+ * Copyright (c) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+#include <linux/io.h>
+#include <mach/gpio.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+
+#include <mach/spi.h>
+#include <mach/clock.h>
+
+
+//#define SPI_DEBUG
+/* #define DEBUG */
+#undef PDEBUG           /* undef it, just in case */
+#ifdef SPI_DEBUG
+# ifdef __KERNEL__
+/* This one if debugging is on, and kernel space */
+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)
+# else
+/* This one for user space */
+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)
+# endif
+#else
+# define PDEBUG(fmt, args...) /* not debugging: nothing */
+#endif
+
+
+#define READ_TIMEOUT 10000000
+#define TRANS_TIMEOUT 10000000
+#define MAX_LEN 64*1024
+#define AK98SPI_DELAY 100000
+/**
+ * ak98_spi_devstate - per device data
+ * @hz: Last frequency calculated for @sppre field.
+ * @mode: Last mode setting for the @spcon field.
+ * @spcon: Value to write to the SPCON register.
+ * @sppre: Value to write to the SPIINT register.
+ */
+struct ak98_spi_devstate {
+	unsigned int	hz;
+	u16	mode;
+	u16		spcon;
+	u8		spint;
+	u8		div;
+};
+
+struct ak98_spi {
+	/* bitbang has to be first */
+	struct spi_bitbang	 bitbang;
+	struct completion	 done;
+
+	void __iomem		*regs;
+	int			 irq;
+	int			 len;
+	int			 count;
+
+	void			(*set_cs)(struct ak98_spi_info *spi,
+					  int cs, int pol);
+
+	/* data buffers */
+	const unsigned char	*tx;
+	unsigned char		*rx;
+
+	struct clk		*clk;
+	struct resource		*ioarea;
+	struct spi_master	*master;
+	struct spi_device	*curdev;
+	struct device		*dev;
+	struct ak98_spi_info *pdata;
+};
+
+#define DFT_CON ( AK98_SPICON_EN | AK98_SPICON_MS)
+#define DFT_DIV		127
+#define FORCE_CS   1 << 5
+#define SPPIN_DEFAULT (0)
+
+#if 0
+static void spi_reg_print(struct ak98_spi *hw)
+{
+	PDEBUG("\n");
+	PDEBUG("CON: \t0x%x\n", ioread32(hw->regs + AK98_SPICON));
+	PDEBUG("STA: \t0x%x\n", ioread32(hw->regs + AK98_SPISTA));
+	PDEBUG("INT: \t0x%x\n", ioread32(hw->regs + AK98_SPIINT));
+	PDEBUG("CNT: \t0x%x\n", ioread32(hw->regs + AK98_SPICNT));
+	PDEBUG("DOUT: \t0x%x\n", ioread32(hw->regs + AK98_SPIOUT));
+	PDEBUG("DIN: \t0x%x\n", ioread32(hw->regs + AK98_SPIIN));
+}
+#endif
+
+static inline struct ak98_spi *to_hw(struct spi_device *sdev)
+{
+	return spi_master_get_devdata(sdev->master);
+}
+
+static void ak98_spi_gpiocs(struct ak98_spi_info *spi, int cs, int pol)
+{
+	//gpio_set_value(spi->pin_cs, pol);
+}
+
+static void ak98_spi_chipsel(struct spi_device *spi, int value)
+{
+	//struct ak98_spi_devstate *cs = spi->controller_state;
+	struct ak98_spi *hw = to_hw(spi);
+	//unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
+	unsigned int spicon;
+
+	//PDEBUG("Entering %s\n", __FUNCTION__);
+	/* change the chipselect state and the state of the spi engine clock */	
+	switch (value) {
+	case BITBANG_CS_INACTIVE:
+		PDEBUG("BITBANG_CS_INACTIVE\n");
+		//hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
+		//writeb(cs->spcon, hw->regs + S3C2410_SPCON);
+		break;
+
+	case BITBANG_CS_ACTIVE:
+		PDEBUG("BITBANG_CS_ACTIVE");
+		spicon = ioread32(hw->regs + AK98_SPICON);
+		if (spi->mode & SPI_CPHA)
+			spicon |= AK98_SPICON_CPHA;
+		else
+			spicon &= ~AK98_SPICON_CPHA;
+		if (spi->mode & SPI_CPOL)
+			spicon |= AK98_SPICON_CPOL;
+		else
+			spicon &= ~AK98_SPICON_CPOL;
+
+		iowrite32(spicon  , hw->regs + AK98_SPICON);
+		//hw->set_cs(hw->pdata, spi->chip_select, cspol);
+		break;
+	}
+}
+
+static int ak98_spi_update_state(struct spi_device *spi,
+				    struct spi_transfer *t)
+{
+	//struct ak98_spi *hw = to_hw(spi);
+	struct ak98_spi_devstate *cs = spi->controller_state;
+	unsigned int bpw;
+	unsigned int hz;
+	unsigned int div;
+	unsigned long clk;
+
+	bpw = t ? t->bits_per_word : spi->bits_per_word;
+	hz  = t ? t->speed_hz : spi->max_speed_hz;
+
+	if (!bpw)
+		bpw = 8;
+
+	if (!hz)
+		hz = spi->max_speed_hz;
+
+	if (bpw != 8) {
+		dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
+		return -EINVAL;
+	}
+	
+	if (spi->mode != cs->mode) {
+		u16 spcon = DFT_CON;
+	printk("set mode---------------------------.\n");
+		if ( (spi->mode & SPI_CPHA) == SPI_CPHA)
+			spcon |= AK98_SPICON_CPHA;
+
+		if ( (spi->mode & SPI_CPOL) == SPI_CPOL)
+			spcon |= AK98_SPICON_CPOL;
+
+		cs->mode = spi->mode;
+		cs->spcon = spcon;
+	}
+
+	PDEBUG("cs->hz: %u\n", cs->hz);
+	if (cs->hz != hz) {
+		clk = ak98_get_asic_clk();
+		PDEBUG("hz: %u\n", hz);
+		PDEBUG("clk: %lu\n", clk);
+		div = clk / (hz*2) - 1;
+
+		if (div > 255)
+			div = 255;
+
+		dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
+			div, hz, clk / (2 * (div + 1)));
+
+		cs->hz = hz;
+		cs->div = div;
+		PDEBUG("cs div: %u\n", cs->div);
+	}
+
+	return 0;
+}
+
+static int ak98_spi_setupxfer(struct spi_device *spi,
+				 struct spi_transfer *t)
+{
+	struct ak98_spi_devstate *cs = spi->controller_state;
+	struct ak98_spi *hw = to_hw(spi);
+	int ret;
+	//PDEBUG("Entering %s\n", __FUNCTION__);
+	ret = ak98_spi_update_state(spi, t);
+	//PDEBUG("cs->div: %u\n", cs->div);
+	if (!ret)//cs->div
+		iowrite32(cs->div << 8 | cs->spcon, hw->regs + AK98_SPICON);
+
+	return ret;
+}
+
+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
+
+static int ak98_spi_setup(struct spi_device *spi)
+{
+	struct ak98_spi_devstate *cs = spi->controller_state;
+	struct ak98_spi *hw = to_hw(spi);
+	int ret;
+
+	//PDEBUG("Entering %s %u %u %u\n", __FUNCTION__, spi->max_speed_hz, spi->mode, spi->chip_select);
+	/* allocate settings on the first call */
+	if (!cs) 
+	{
+		cs = kzalloc(sizeof(struct ak98_spi_devstate), GFP_KERNEL);
+		if (!cs) 
+		{
+			dev_err(&spi->dev, "no memory for controller state\n");
+			return -ENOMEM;
+		}
+
+		cs->spcon = DFT_CON;
+		cs->hz = -1;
+		cs->div = DFT_DIV;
+		spi->controller_state = cs;
+	}
+
+	if (spi->mode & ~(hw->pdata->mode_bits)) {
+		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
+			spi->mode & ~(hw->pdata->mode_bits));
+		return -EINVAL;
+	}
+	/* initialise the state from the device */
+	ret = ak98_spi_update_state(spi, NULL);
+	if (ret)
+		return ret;
+
+	spin_lock(&hw->bitbang.lock);
+	if (!hw->bitbang.busy) {
+		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
+		/* need to ndelay for 0.5 clocktick ? */
+	}
+	spin_unlock(&hw->bitbang.lock);
+
+	return 0;
+}
+
+static void ak98_spi_cleanup(struct spi_device *spi)
+{
+	kfree(spi->controller_state);
+}
+
+static void ak98_set_spi_irq(struct ak98_spi *hw, int enable)
+{	
+	u32 spiint = AK98_SPIINT_TRANSF | AK98_SPIINT_TXFULL | AK98_SPIINT_RXFULL; 
+	if (enable)
+		iowrite32(spiint, hw->regs + AK98_SPIINT);
+	else
+		iowrite32(0, hw->regs + AK98_SPIINT);	
+}
+
+
+static inline unsigned int hw_txdword(struct ak98_spi *hw, int count)
+{
+	u32 val = 0;
+	int i = 0;
+	while (i<4)
+	{
+		#if 0
+		val = (val << 8) | hw->tx[count+i];
+		#else
+		val = val | (hw->tx[count+i] << i*8);
+		#endif
+		i++;
+	}
+	return val;
+}
+
+static int ak98_spi_readCPU(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak98_spi *hw = to_hw(spi);
+
+	//u32 read_4_nbr = hw->len/4;
+	u32 frac_nbr = hw->len%4;
+	u32 status, val;
+	u32 off_set = 0;
+	u8 *buff = hw->rx;
+	int i;
+	u32 to=0;
+	
+
+	if (hw->len >= 64*1024)
+	{
+		printk("Too much to be read...\n");
+		return -EINVAL;
+	}
+	PDEBUG("read CPU...\n");
+	PDEBUG("%u  %u read CPU...\n", read_4_nbr, frac_nbr);
+	//set read only
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(AK98_SPICON_ARRM);
+	val |= AK98_SPICON_TGDM;
+	if (t->cs_change == 0)
+		val |= FORCE_CS;
+	iowrite32(val, hw->regs + AK98_SPICON);
+	udelay(10);
+
+	//set data count, and the the master will rise clk
+	iowrite32(hw->len, hw->regs + AK98_SPICNT);
+	udelay(10);
+	
+	
+	while(1)
+	{
+		status = ioread32(hw->regs + AK98_SPISTA);	
+		
+		
+		if ( (status & AK98_SPISTA_TRANSF) == AK98_SPISTA_TRANSF)
+		{
+			if (status & AK98_SPISTA_RXFULL)
+			{
+				PDEBUG("RXFULL\n");
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff + off_set) = val;
+				off_set += 4;
+				PDEBUG("%x\n", val);
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff + off_set) = val;
+				off_set += 4;
+				PDEBUG("%x\n", val);
+			}
+			else if (status & AK98_SPISTA_RXHFULL)
+			{
+				PDEBUG("RXHFULL\n");
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff + off_set) = val;
+				off_set += 4;
+			}
+			if (frac_nbr != 0)
+			{
+				val = ioread32(hw->regs + AK98_SPIIN);
+				printk("-------------%x\n", val);
+				for (i=0; i<frac_nbr; i++)
+				{
+					*(buff+off_set+i) = (val >> i*8) & 0xff;
+				}
+			}
+			break;
+		}
+		else
+		{
+			if ( (status & AK98_SPISTA_RXHFULL) == AK98_SPISTA_RXHFULL)
+			{
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff + off_set) = val;
+				off_set += 4;
+			}
+			else
+			{
+				if (to++ > 10 * 1000000)
+				{
+					PDEBUG("master read timeout...\n");
+					return off_set;
+				}
+			}
+		}	
+	}
+	if (off_set + frac_nbr != hw->len)
+		PDEBUG("read wasn't finished...\n");
+	
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(FORCE_CS);
+	iowrite32(val, hw->regs + AK98_SPICON);
+	
+	return hw->len;
+	
+}
+
+static int ak98_spi_writeCPU(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak98_spi *hw = to_hw(spi);
+
+	u32 tran_4_nbr = hw->len/4;
+	u32 frac_nbr = hw->len%4;
+	u32 status, val;
+	u32 off_set = 0;
+	const u8 *buff = hw->tx;
+	int i;
+	u32 to = 0;
+
+
+	PDEBUG("write... %u  %u\n", tran_4_nbr, frac_nbr);
+	if (hw->len >= 64*1024)
+	{
+		printk("Too much to be send...\n");
+		return -EINVAL;
+	}
+	//set transfer only
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(AK98_SPICON_TGDM);
+	val |= AK98_SPICON_ARRM;
+	if (t->cs_change == 0)
+		val |= FORCE_CS;
+
+	iowrite32(val, hw->regs + AK98_SPICON);
+	udelay(10);
+	//set data count, and the the master will rise clk
+	iowrite32(hw->len, hw->regs + AK98_SPICNT);
+	udelay(10);
+	
+	for (i=0; i<tran_4_nbr; i++)
+	{
+		while(1)
+		{
+			status = ioread32(hw->regs + AK98_SPISTA);
+			if ((status & AK98_SPISTA_TXHEMP) == AK98_SPISTA_TXHEMP)
+				break;
+		}
+		iowrite32(*(volatile u32 *)(buff + off_set), hw->regs + AK98_SPIOUT);
+		off_set += 4;
+	}
+
+	if (frac_nbr != 0)
+	{
+		val = 0;
+		while(1)
+		{
+			status = ioread32(hw->regs + AK98_SPISTA);
+			if ((status & AK98_SPISTA_TXHEMP) == AK98_SPISTA_TXHEMP)
+				break;
+			if (to++ > 31 * 2000000)
+			{
+				printk("SPI master write timeout...\n");
+				to = 0;
+				return off_set;
+			}
+		}
+		
+		for (i=0; i<frac_nbr; i++)
+		{
+			val |= (*(buff + off_set + i) << (i*8));
+		}
+		PDEBUG("-----%x -----\n", val);
+		iowrite32(val, hw->regs + AK98_SPIOUT);		
+	}
+
+	//wait transfer finish
+	while (1)
+	{
+		PDEBUG("wait...\n");
+		status = ioread32(hw->regs + AK98_SPISTA);		
+		if ((status & AK98_SPISTA_TRANSF) == AK98_SPISTA_TRANSF)
+			break;
+		if (to++ > 10 * 1000000)
+		{
+			printk("Master transfer timeout...\n");	
+			return off_set;
+		}
+			
+	}
+
+	if (off_set + frac_nbr != hw->len)
+		PDEBUG("write wasn't finished...\n");
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(FORCE_CS);
+	iowrite32(val, hw->regs + AK98_SPICON);
+	
+	return hw->len;
+}
+
+static int ak98_spi_duplexCPU(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak98_spi *hw = to_hw(spi);
+	u32 tran_4_nbr = hw->len/4;
+	u32 frac_nbr = hw->len%4;
+	u32 status, val;
+	u32 off_set_read = 0, off_set_write = 0;
+	const u8 *buff_tx = hw->tx;
+	u8 *buff_rx = hw->rx;
+	int i = 0, j;
+	u32 to_read = 0, to_write = 0, to = 0;
+
+	PDEBUG("duplex...\n");
+	PDEBUG("tran_4_nbr:%u  frac_nbr:%u\n", tran_4_nbr, frac_nbr);
+	
+	if (hw->len >= MAX_LEN)
+	{
+		printk("Too much to be read and send...\n");
+		return -EINVAL;
+	}
+
+	//close ARRM and TGDM
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(AK98_SPICON_ARRM | AK98_SPICON_TGDM);
+	//whether #CS signal keep low
+	if (t->cs_change == 0)
+		val |= FORCE_CS;
+	
+	iowrite32(val, hw->regs + AK98_SPICON);
+	
+	udelay(10);
+	//set data count, and the the master will rise clk
+	iowrite32(hw->len, hw->regs + AK98_SPICNT);
+	
+	udelay(10);
+	
+	while(1)
+	{
+		//write 4 bytes first, and then read 4 bytes
+		if (i<tran_4_nbr)
+		{
+			while(1)
+			{
+				status = ioread32(hw->regs + AK98_SPISTA);
+				if ((status & AK98_SPISTA_TXHEMP) == AK98_SPISTA_TXHEMP)
+				{
+					PDEBUG("TX HEMP...\n");
+					break;
+				}
+				else
+				{
+					if(to_write++ > TRANS_TIMEOUT)
+					{
+						PDEBUG("master transfer timeout...\n");
+						goto SPI_TRANS_TIMEOUT;
+					}
+				}
+			}			
+			iowrite32(*(volatile u32 *)(buff_tx + off_set_write), hw->regs + AK98_SPIOUT);
+			off_set_write += 4;
+			i++;
+		}
+		//write not finished
+		else if (off_set_write < hw->len)
+		{			
+			PDEBUG("write frac...\n");
+			to_write = 0;
+			val = 0;
+			if (frac_nbr != 0)
+			{
+				while(1)
+				{
+					status = ioread32(hw->regs + AK98_SPISTA);
+					if ((status & AK98_SPISTA_TXHEMP) == AK98_SPISTA_TXHEMP)
+						break;
+					if (to_write++ > TRANS_TIMEOUT)
+					{
+						printk("SPI master write timeout...\n");						
+						goto SPI_TRANS_TIMEOUT;
+					}
+				}
+					
+				for (j=0; j<frac_nbr; j++)
+				{
+					PDEBUG("[%d]:%x ", off_set_write+j, *(buff_tx+off_set_write+j));
+					val |= (*(buff_tx + off_set_write + j) << (j*8));
+				}
+				PDEBUG("\nval: %x", val);
+				PDEBUG("\n\n");
+
+				iowrite32(val, hw->regs + AK98_SPIOUT); 
+				off_set_write += frac_nbr;
+			}
+		}
+
+		
+		//read
+		status = ioread32(hw->regs + AK98_SPISTA);			
+		
+		if ( (status & AK98_SPISTA_TRANSF) == AK98_SPISTA_TRANSF)
+		{
+			if (status & AK98_SPISTA_RXFULL)
+			{
+				PDEBUG("RXFULL\n");
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff_rx + off_set_read) = val;
+				off_set_read += 4;
+				PDEBUG("%x\n", val);
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff_rx + off_set_read) = val;
+				off_set_read += 4;
+				PDEBUG("%x\n", val);
+			}
+			else if (status & AK98_SPISTA_RXHFULL)
+			{
+				PDEBUG("RXHFULL\n");
+
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff_rx + off_set_read) = val;
+				off_set_read += 4;
+			}
+			if (frac_nbr != 0)
+			{
+				PDEBUG("read frac...\n");
+				val = ioread32(hw->regs + AK98_SPIIN);
+				PDEBUG("read ... %x\n", val);
+				for (j=0; j<frac_nbr; j++)
+				{
+					*(buff_rx+off_set_read+j) = (val >> j*8) & 0xff;
+					PDEBUG("%x ", *(buff_rx+off_set_read+j));
+				}
+			}
+			break;
+		}
+		else
+		{
+			if ( (status & AK98_SPISTA_RXHFULL) == AK98_SPISTA_RXHFULL)
+			{
+				PDEBUG("RX HFULL...\n");
+
+				val = ioread32(hw->regs + AK98_SPIIN);
+				*(volatile u32 *)(buff_rx + off_set_read) = val;
+				PDEBUG("rx hfull .. %x\n", val);
+				PDEBUG("[0]%x [1]%x [2]%x [3]%x\n", buff_rx[0], buff_rx[1], buff_rx[2], buff_rx[3]);
+				off_set_read += 4;
+			}
+			else
+			{
+				if (to_read++ > READ_TIMEOUT)
+				{
+					PDEBUG("master read timeout...\n");
+					goto SPI_READ_TIMEOUT;
+				}
+			}
+		}	
+	}
+	
+	val = ioread32(hw->regs + AK98_SPICON);
+	val &= ~(FORCE_CS);
+	iowrite32(val, hw->regs + AK98_SPICON);
+	
+	return hw->len;
+	SPI_TRANS_TIMEOUT:
+	SPI_READ_TIMEOUT:
+		val = ioread32(hw->regs + AK98_SPICON);
+		val &= ~(FORCE_CS);		
+		iowrite32(val, hw->regs + AK98_SPICON);
+		
+		return off_set_read > off_set_write ? off_set_read: off_set_write;		
+	
+}
+
+
+static int ak98_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
+{
+	struct ak98_spi *hw = to_hw(spi);
+	
+	PDEBUG("txrx: tx %p, rx %p, len %d\n",
+		t->tx_buf, t->rx_buf, t->len);
+	
+	dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
+		t->tx_buf, t->rx_buf, t->len);
+
+	hw->tx = t->tx_buf;
+	hw->rx = t->rx_buf;
+	hw->len = t->len;
+	hw->count = 0;
+	
+	//spi_reg_print(hw);
+	//ak98_prepare_transfer(spi, t);
+	
+	if (hw->tx && hw->rx)
+	{
+		PDEBUG("Duplex transfer\n");
+		return ak98_spi_duplexCPU(spi, t);
+	}
+	if (hw->tx)
+	{
+		PDEBUG("write only...\n");
+		return ak98_spi_writeCPU(spi, t);
+	}
+	if (hw->rx)
+	{
+		PDEBUG("read only...\n");
+		return ak98_spi_readCPU(spi, t);
+	}
+	
+	return 0;
+}
+
+
+
+static irqreturn_t ak98_spi_irq(int irq, void *dev)
+{
+
+	struct ak98_spi *hw = dev;
+	PDEBUG("Entering %s  %u %u\n", __FUNCTION__, hw->count, hw->len);
+	
+ irq_done:
+	return IRQ_HANDLED;
+}
+
+
+static void ak98_spi_initialsetup(struct ak98_spi *hw)
+{
+	/* for the moment, permanently enable the clock */
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	clk_enable(hw->clk);
+
+	/* program defaults into the registers */
+
+	iowrite32(DFT_DIV<<8 | DFT_CON, hw->regs + AK98_SPICON);
+	ak98_set_spi_irq(hw, 0);
+	
+	if (hw->pdata) 
+	{
+		if (hw->pdata->gpio_setup)
+			hw->pdata->gpio_setup(hw->pdata, 1);
+	}
+}
+
+static int __init ak98_spi_probe(struct platform_device *pdev)
+{
+	struct ak98_spi_info *pdata;
+	struct ak98_spi *hw;
+	struct spi_master *master;
+	struct resource *res;
+	int err = 0;
+
+	PDEBUG("Entering %s\n", __FUNCTION__);
+	master = spi_alloc_master(&pdev->dev, sizeof(struct ak98_spi));
+	if (master == NULL) 
+	{
+		dev_err(&pdev->dev, "No memory for spi_master\n");
+		err = -ENOMEM;
+		goto err_nomem;
+	}
+
+	hw = spi_master_get_devdata(master);
+	memset(hw, 0, sizeof(struct ak98_spi));
+
+	hw->master = spi_master_get(master);
+	hw->pdata = pdata = pdev->dev.platform_data;
+	hw->dev = &pdev->dev;
+
+	if (pdata == NULL) 
+	{
+		dev_err(&pdev->dev, "No platform data supplied\n");
+		err = -ENOENT;
+		goto err_no_pdata;
+	}
+
+	platform_set_drvdata(pdev, hw);
+	init_completion(&hw->done);
+
+	/* setup the master state. */
+
+	/* the spi->mode bits understood by this driver: */
+	master->mode_bits = hw->pdata->mode_bits;
+
+	master->num_chipselect = hw->pdata->num_cs;
+	master->bus_num = pdata->bus_num;
+
+	/* setup the state for the bitbang driver */
+
+	hw->bitbang.master         = hw->master;
+	hw->bitbang.setup_transfer = ak98_spi_setupxfer;
+	hw->bitbang.chipselect     = ak98_spi_chipsel;
+	hw->bitbang.txrx_bufs      = ak98_spi_txrx;
+
+	hw->master->setup  = ak98_spi_setup;
+	hw->master->cleanup = ak98_spi_cleanup;
+
+	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
+
+	/* find and map our resources */
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+		err = -ENOENT;
+		goto err_no_iores;
+	}
+
+	hw->ioarea = request_mem_region(res->start, resource_size(res),
+					pdev->name);
+
+	if (hw->ioarea == NULL) {
+		dev_err(&pdev->dev, "Cannot reserve region\n");
+		err = -ENXIO;
+		goto err_no_iores;
+	}
+
+	hw->regs = ioremap(res->start, resource_size(res));
+	if (hw->regs == NULL) {
+		dev_err(&pdev->dev, "Cannot map IO\n");
+		err = -ENXIO;
+		goto err_no_iomap;
+	}
+
+	hw->irq = platform_get_irq(pdev, 0);
+	if (hw->irq < 0) {
+		dev_err(&pdev->dev, "No IRQ specified\n");
+		err = -ENOENT;
+		goto err_no_irq;
+	}
+
+	err = request_irq(hw->irq, ak98_spi_irq, 0, pdev->name, hw);
+	if (err) {
+		dev_err(&pdev->dev, "Cannot claim IRQ\n");
+		goto err_no_irq;
+	}
+
+	hw->clk = clk_get(&pdev->dev, pdata->clk_name);
+
+	PDEBUG("%s: %lu  \n", hw->clk->name, clk_get_rate(hw->clk));
+	if (IS_ERR(hw->clk)) {
+		dev_err(&pdev->dev, "No clock for device\n");
+		err = PTR_ERR(hw->clk);
+		goto err_no_clk;
+	}
+
+	/* setup any gpio we can */
+
+	ak98_spi_initialsetup(hw);
+
+	/* register our spi controller */
+
+	err = spi_bitbang_start(&hw->bitbang);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register SPI master\n");
+		goto err_register;
+	}
+
+	return 0;
+
+ err_register:
+	//if (hw->set_cs == ak98_spi_gpiocs)
+	//	gpio_free(pdata->pin_cs);
+
+	clk_disable(hw->clk);
+	clk_put(hw->clk);
+
+ err_no_clk:
+	free_irq(hw->irq, hw);
+
+ err_no_irq:
+	iounmap(hw->regs);
+
+ err_no_iomap:
+	release_resource(hw->ioarea);
+	kfree(hw->ioarea);
+
+ err_no_iores:
+ err_no_pdata:
+	spi_master_put(hw->master);
+
+ err_nomem:
+	return err;
+}
+
+static int __exit ak98_spi_remove(struct platform_device *dev)
+{
+	struct ak98_spi *hw = platform_get_drvdata(dev);
+
+	platform_set_drvdata(dev, NULL);
+
+	spi_unregister_master(hw->master);
+
+	clk_disable(hw->clk);
+	clk_put(hw->clk);
+
+	free_irq(hw->irq, hw);
+	iounmap(hw->regs);
+
+	//if (hw->set_cs == ak98_spi_gpiocs)
+	//	gpio_free(hw->pdata->pin_cs);
+
+	release_resource(hw->ioarea);
+	kfree(hw->ioarea);
+
+	spi_master_put(hw->master);
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+
+static int ak98_spi_suspend(struct device *dev)
+{
+	struct ak98_spi *hw = platform_get_drvdata(to_platform_device(dev));
+
+	if (hw->pdata && hw->pdata->gpio_setup)
+		hw->pdata->gpio_setup(hw->pdata, 0);
+
+	clk_disable(hw->clk);
+	return 0;
+}
+
+static int ak98_spi_resume(struct device *dev)
+{
+	struct ak98_spi *hw = platform_get_drvdata(to_platform_device(dev));
+
+	ak98_spi_initialsetup(hw);
+	return 0;
+}
+
+static struct dev_pm_ops ak98_spi_pmops = {
+	.suspend	= ak98_spi_suspend,
+	.resume		= ak98_spi_resume,
+};
+
+#define AK98_SPI_PMOPS &ak98_spi_pmops
+#else
+#define AK98_SPI_PMOPS NULL
+#endif /* CONFIG_PM */
+
+MODULE_ALIAS("platform:ak98-spi");
+static struct platform_driver ak98_spi_driver = {
+	.remove		= __exit_p(ak98_spi_remove),
+	.driver		= {
+		.name	= "ak98-spi",
+		.owner	= THIS_MODULE,
+		.pm	= AK98_SPI_PMOPS,
+	},
+};
+
+static int __init ak98_spi_init(void)
+{
+		PDEBUG("AK98 SPI Driver, (c) 2011 ANYKA\n");
+        return platform_driver_probe(&ak98_spi_driver, ak98_spi_probe);
+}
+
+static void __exit ak98_spi_exit(void)
+{
+        platform_driver_unregister(&ak98_spi_driver);
+}
+
+module_init(ak98_spi_init);
+module_exit(ak98_spi_exit);
+
+MODULE_DESCRIPTION("AK98 SPI Driver");
+MODULE_AUTHOR("ANYKA");
+MODULE_LICENSE("GPL");
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 8cbf1aebea2..b516268957d 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_RTL8192E)		+= rtl8192e/
 obj-$(CONFIG_INPUT_MIMIO)	+= mimio/
 obj-$(CONFIG_TRANZPORT)		+= frontier/
 obj-$(CONFIG_ANDROID)		+= android/
-obj-$(CONFIG_ANDROID)		+= dream/
+obj-$(CONFIG_STAGING_DREAM)	+= dream/
 obj-$(CONFIG_DST)		+= dst/
 obj-$(CONFIG_POHMELFS)		+= pohmelfs/
 obj-$(CONFIG_B3DFG)		+= b3dfg/
diff --git a/drivers/staging/android/Kconfig b/drivers/staging/android/Kconfig
index eb675635ae6..24719499237 100644
--- a/drivers/staging/android/Kconfig
+++ b/drivers/staging/android/Kconfig
@@ -2,7 +2,6 @@ menu "Android"
 
 config ANDROID
 	bool "Android Drivers"
-	depends on BROKEN
 	default N
 	---help---
 	  Enable support for various drivers needed on the Android platform
diff --git a/drivers/staging/android/binder.c b/drivers/staging/android/binder.c
index 99010d4b304..17e5c24eae1 100644
--- a/drivers/staging/android/binder.c
+++ b/drivers/staging/android/binder.c
@@ -46,6 +46,7 @@ static struct proc_dir_entry *binder_proc_dir_entry_proc;
 static struct binder_node *binder_context_mgr_node;
 static uid_t binder_context_mgr_uid = -1;
 static int binder_last_id;
+static struct workqueue_struct *binder_deferred_workqueue;
 
 static int binder_read_proc_proc(char *page, char **start, off_t off,
 				 int count, int *eof, void *data);
@@ -3025,11 +3026,14 @@ static void binder_deferred_release(struct binder_proc *proc)
 		int i;
 		for (i = 0; i < proc->buffer_size / PAGE_SIZE; i++) {
 			if (proc->pages[i]) {
+				void *page_addr = proc->buffer + i * PAGE_SIZE;
 				binder_debug(BINDER_DEBUG_BUFFER_ALLOC,
 					     "binder_release: %d: "
 					     "page %d at %p not freed\n",
 					     proc->pid, i,
-					     proc->buffer + i * PAGE_SIZE);
+					     page_addr);
+				unmap_kernel_range((unsigned long)page_addr,
+					PAGE_SIZE);
 				__free_page(proc->pages[i]);
 				page_count++;
 			}
@@ -3099,7 +3103,7 @@ binder_defer_work(struct binder_proc *proc, enum binder_deferred_state defer)
 	if (hlist_unhashed(&proc->deferred_work_node)) {
 		hlist_add_head(&proc->deferred_work_node,
 				&binder_deferred_list);
-		schedule_work(&binder_deferred_work);
+		queue_work(binder_deferred_workqueue, &binder_deferred_work);
 	}
 	mutex_unlock(&binder_deferred_lock);
 }
@@ -3727,6 +3731,10 @@ static int __init binder_init(void)
 {
 	int ret;
 
+	binder_deferred_workqueue = create_singlethread_workqueue("binder");
+	if (!binder_deferred_workqueue)
+		return -ENOMEM;
+
 	binder_proc_dir_entry_root = proc_mkdir("binder", NULL);
 	if (binder_proc_dir_entry_root)
 		binder_proc_dir_entry_proc = proc_mkdir("proc",
diff --git a/drivers/staging/android/logger.c b/drivers/staging/android/logger.c
index 6c10b456c6c..15b2e97002a 100644
--- a/drivers/staging/android/logger.c
+++ b/drivers/staging/android/logger.c
@@ -17,6 +17,7 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
@@ -556,6 +557,7 @@ static struct logger_log VAR = { \
 DEFINE_LOGGER_DEVICE(log_main, LOGGER_LOG_MAIN, 64*1024)
 DEFINE_LOGGER_DEVICE(log_events, LOGGER_LOG_EVENTS, 256*1024)
 DEFINE_LOGGER_DEVICE(log_radio, LOGGER_LOG_RADIO, 64*1024)
+DEFINE_LOGGER_DEVICE(log_system, LOGGER_LOG_SYSTEM, 64*1024)
 
 static struct logger_log *get_log_from_minor(int minor)
 {
@@ -565,6 +567,8 @@ static struct logger_log *get_log_from_minor(int minor)
 		return &log_events;
 	if (log_radio.misc.minor == minor)
 		return &log_radio;
+	if (log_system.misc.minor == minor)
+		return &log_system;
 	return NULL;
 }
 
@@ -601,6 +605,10 @@ static int __init logger_init(void)
 	if (unlikely(ret))
 		goto out;
 
+	ret = init_log(&log_system);
+	if (unlikely(ret))
+		goto out;
+
 out:
 	return ret;
 }
diff --git a/drivers/staging/android/logger.h b/drivers/staging/android/logger.h
index a562434d741..2cb06e9d8f9 100644
--- a/drivers/staging/android/logger.h
+++ b/drivers/staging/android/logger.h
@@ -32,6 +32,7 @@ struct logger_entry {
 
 #define LOGGER_LOG_RADIO	"log_radio"	/* radio-related messages */
 #define LOGGER_LOG_EVENTS	"log_events"	/* system/hardware events */
+#define LOGGER_LOG_SYSTEM	"log_system"	/* system/framework messages */
 #define LOGGER_LOG_MAIN		"log_main"	/* everything else */
 
 #define LOGGER_ENTRY_MAX_LEN		(4*1024)
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index 935d281a201..39d5e6502b2 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -34,6 +34,7 @@
 #include <linux/mm.h>
 #include <linux/oom.h>
 #include <linux/sched.h>
+#include <linux/notifier.h>
 
 static uint32_t lowmem_debug_level = 2;
 static int lowmem_adj[6] = {
@@ -51,12 +52,32 @@ static size_t lowmem_minfree[6] = {
 };
 static int lowmem_minfree_size = 4;
 
+static struct task_struct *lowmem_deathpending;
+
 #define lowmem_print(level, x...)			\
 	do {						\
 		if (lowmem_debug_level >= (level))	\
 			printk(x);			\
 	} while (0)
 
+static int
+task_notify_func(struct notifier_block *self, unsigned long val, void *data);
+
+static struct notifier_block task_nb = {
+	.notifier_call	= task_notify_func,
+};
+
+static int
+task_notify_func(struct notifier_block *self, unsigned long val, void *data)
+{
+	struct task_struct *task = data;
+	if (task == lowmem_deathpending) {
+		lowmem_deathpending = NULL;
+		task_free_unregister(&task_nb);
+	}
+	return NOTIFY_OK;
+}
+
 static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 {
 	struct task_struct *p;
@@ -71,6 +92,16 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 	int other_free = global_page_state(NR_FREE_PAGES);
 	int other_file = global_page_state(NR_FILE_PAGES);
 
+	/*
+	 * If we already have a death outstanding, then
+	 * bail out right away; indicating to vmscan
+	 * that we have nothing further to offer on
+	 * this pass.
+	 *
+	 */
+	if (lowmem_deathpending)
+		return 0;
+
 	if (lowmem_adj_size < array_size)
 		array_size = lowmem_adj_size;
 	if (lowmem_minfree_size < array_size)
@@ -100,15 +131,17 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 	read_lock(&tasklist_lock);
 	for_each_process(p) {
 		struct mm_struct *mm;
+		struct signal_struct *sig;
 		int oom_adj;
 
 		task_lock(p);
 		mm = p->mm;
-		if (!mm) {
+		sig = p->signal;
+		if (!mm || !sig) {
 			task_unlock(p);
 			continue;
 		}
-		oom_adj = mm->oom_adj;
+		oom_adj = sig->oom_adj;
 		if (oom_adj < min_adj) {
 			task_unlock(p);
 			continue;
@@ -134,6 +167,8 @@ static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
 		lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n",
 			     selected->pid, selected->comm,
 			     selected_oom_adj, selected_tasksize);
+		lowmem_deathpending = selected;
+		task_free_register(&task_nb);
 		force_sig(SIGKILL, selected);
 		rem -= selected_tasksize;
 	}
diff --git a/drivers/staging/android/ram_console.c b/drivers/staging/android/ram_console.c
index 8f18a59744c..53f736b0ec8 100644
--- a/drivers/staging/android/ram_console.c
+++ b/drivers/staging/android/ram_console.c
@@ -146,6 +146,14 @@ static struct console ram_console = {
 	.index	= -1,
 };
 
+void ram_console_enable_console(int enabled)
+{
+	if (enabled)
+		ram_console.flags |= CON_ENABLED;
+	else
+		ram_console.flags &= ~CON_ENABLED;
+}
+
 static void __init
 ram_console_save_old(struct ram_console_buffer *buffer, char *dest)
 {
@@ -404,7 +412,7 @@ static int __init ram_console_late_init(void)
 #ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
 console_initcall(ram_console_early_init);
 #else
-module_init(ram_console_module_init);
+postcore_initcall(ram_console_module_init);
 #endif
 late_initcall(ram_console_late_init);
 
diff --git a/drivers/staging/android/timed_gpio.c b/drivers/staging/android/timed_gpio.c
index be7cdaa783a..a646107da26 100644
--- a/drivers/staging/android/timed_gpio.c
+++ b/drivers/staging/android/timed_gpio.c
@@ -106,10 +106,17 @@ static int timed_gpio_probe(struct platform_device *pdev)
 		gpio_dat->dev.name = cur_gpio->name;
 		gpio_dat->dev.get_time = gpio_get_time;
 		gpio_dat->dev.enable = gpio_enable;
-		ret = timed_output_dev_register(&gpio_dat->dev);
+		ret = gpio_request(cur_gpio->gpio, cur_gpio->name);
+		if (ret >= 0) {
+			ret = timed_output_dev_register(&gpio_dat->dev);
+			if (ret < 0)
+				gpio_free(cur_gpio->gpio);
+		}
 		if (ret < 0) {
-			for (j = 0; j < i; j++)
+			for (j = 0; j < i; j++) {
 				timed_output_dev_unregister(&gpio_data[i].dev);
+				gpio_free(gpio_data[i].gpio);
+			}
 			kfree(gpio_data);
 			return ret;
 		}
@@ -131,8 +138,10 @@ static int timed_gpio_remove(struct platform_device *pdev)
 	struct timed_gpio_data *gpio_data = platform_get_drvdata(pdev);
 	int i;
 
-	for (i = 0; i < pdata->num_gpios; i++)
+	for (i = 0; i < pdata->num_gpios; i++) {
 		timed_output_dev_unregister(&gpio_data[i].dev);
+		gpio_free(gpio_data[i].gpio);
+	}
 
 	kfree(gpio_data);
 
diff --git a/drivers/staging/android/timed_output.c b/drivers/staging/android/timed_output.c
index 62e79180421..f373422308e 100644
--- a/drivers/staging/android/timed_output.c
+++ b/drivers/staging/android/timed_output.c
@@ -41,7 +41,9 @@ static ssize_t enable_store(
 	struct timed_output_dev *tdev = dev_get_drvdata(dev);
 	int value;
 
-	sscanf(buf, "%d", &value);
+	if (sscanf(buf, "%d", &value) != 1)
+		return -EINVAL;
+
 	tdev->enable(tdev, value);
 
 	return size;
diff --git a/drivers/switch/Kconfig b/drivers/switch/Kconfig
new file mode 100644
index 00000000000..52385914b9a
--- /dev/null
+++ b/drivers/switch/Kconfig
@@ -0,0 +1,15 @@
+menuconfig SWITCH
+	tristate "Switch class support"
+	help
+	  Say Y here to enable switch class support. This allows
+	  monitoring switches by userspace via sysfs and uevent.
+
+if SWITCH
+
+config SWITCH_GPIO
+	tristate "GPIO Swith support"
+	depends on GENERIC_GPIO
+	help
+	  Say Y here to enable GPIO based switch support.
+
+endif # SWITCH
diff --git a/drivers/switch/Makefile b/drivers/switch/Makefile
new file mode 100644
index 00000000000..f7606ed4a71
--- /dev/null
+++ b/drivers/switch/Makefile
@@ -0,0 +1,4 @@
+# Switch Class Driver
+obj-$(CONFIG_SWITCH)		+= switch_class.o
+obj-$(CONFIG_SWITCH_GPIO)	+= switch_gpio.o
+
diff --git a/drivers/switch/switch_class.c b/drivers/switch/switch_class.c
new file mode 100644
index 00000000000..e05fc259114
--- /dev/null
+++ b/drivers/switch/switch_class.c
@@ -0,0 +1,174 @@
+/*
+ *  drivers/switch/switch_class.c
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/err.h>
+#include <linux/switch.h>
+
+struct class *switch_class;
+static atomic_t device_count;
+
+static ssize_t state_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct switch_dev *sdev = (struct switch_dev *)
+		dev_get_drvdata(dev);
+
+	if (sdev->print_state) {
+		int ret = sdev->print_state(sdev, buf);
+		if (ret >= 0)
+			return ret;
+	}
+	return sprintf(buf, "%d\n", sdev->state);
+}
+
+static ssize_t name_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct switch_dev *sdev = (struct switch_dev *)
+		dev_get_drvdata(dev);
+
+	if (sdev->print_name) {
+		int ret = sdev->print_name(sdev, buf);
+		if (ret >= 0)
+			return ret;
+	}
+	return sprintf(buf, "%s\n", sdev->name);
+}
+
+static DEVICE_ATTR(state, S_IRUGO | S_IWUSR, state_show, NULL);
+static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, name_show, NULL);
+
+void switch_set_state(struct switch_dev *sdev, int state)
+{
+	char name_buf[120];
+	char state_buf[120];
+	char *prop_buf;
+	char *envp[3];
+	int env_offset = 0;
+	int length;
+
+	if (sdev->state != state) {
+		sdev->state = state;
+
+		prop_buf = (char *)get_zeroed_page(GFP_KERNEL);
+		if (prop_buf) {
+			length = name_show(sdev->dev, NULL, prop_buf);
+			if (length > 0) {
+				if (prop_buf[length - 1] == '\n')
+					prop_buf[length - 1] = 0;
+				snprintf(name_buf, sizeof(name_buf),
+					"SWITCH_NAME=%s", prop_buf);
+				envp[env_offset++] = name_buf;
+			}
+			length = state_show(sdev->dev, NULL, prop_buf);
+			if (length > 0) {
+				if (prop_buf[length - 1] == '\n')
+					prop_buf[length - 1] = 0;
+				snprintf(state_buf, sizeof(state_buf),
+					"SWITCH_STATE=%s", prop_buf);
+				envp[env_offset++] = state_buf;
+			}
+			envp[env_offset] = NULL;
+			kobject_uevent_env(&sdev->dev->kobj, KOBJ_CHANGE, envp);
+			free_page((unsigned long)prop_buf);
+		} else {
+			printk(KERN_ERR "out of memory in switch_set_state\n");
+			kobject_uevent(&sdev->dev->kobj, KOBJ_CHANGE);
+		}
+	}
+}
+EXPORT_SYMBOL_GPL(switch_set_state);
+
+static int create_switch_class(void)
+{
+	if (!switch_class) {
+		switch_class = class_create(THIS_MODULE, "switch");
+		if (IS_ERR(switch_class))
+			return PTR_ERR(switch_class);
+		atomic_set(&device_count, 0);
+	}
+
+	return 0;
+}
+
+int switch_dev_register(struct switch_dev *sdev)
+{
+	int ret;
+
+	if (!switch_class) {
+		ret = create_switch_class();
+		if (ret < 0)
+			return ret;
+	}
+
+	sdev->index = atomic_inc_return(&device_count);
+	sdev->dev = device_create(switch_class, NULL,
+		MKDEV(0, sdev->index), NULL, sdev->name);
+	if (IS_ERR(sdev->dev))
+		return PTR_ERR(sdev->dev);
+
+	ret = device_create_file(sdev->dev, &dev_attr_state);
+	if (ret < 0)
+		goto err_create_file_1;
+	ret = device_create_file(sdev->dev, &dev_attr_name);
+	if (ret < 0)
+		goto err_create_file_2;
+
+	dev_set_drvdata(sdev->dev, sdev);
+	sdev->state = 0;
+	return 0;
+
+err_create_file_2:
+	device_remove_file(sdev->dev, &dev_attr_state);
+err_create_file_1:
+	device_destroy(switch_class, MKDEV(0, sdev->index));
+	printk(KERN_ERR "switch: Failed to register driver %s\n", sdev->name);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(switch_dev_register);
+
+void switch_dev_unregister(struct switch_dev *sdev)
+{
+	device_remove_file(sdev->dev, &dev_attr_name);
+	device_remove_file(sdev->dev, &dev_attr_state);
+	device_destroy(switch_class, MKDEV(0, sdev->index));
+	dev_set_drvdata(sdev->dev, NULL);
+}
+EXPORT_SYMBOL_GPL(switch_dev_unregister);
+
+static int __init switch_class_init(void)
+{
+	return create_switch_class();
+}
+
+static void __exit switch_class_exit(void)
+{
+	class_destroy(switch_class);
+}
+
+module_init(switch_class_init);
+module_exit(switch_class_exit);
+
+MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
+MODULE_DESCRIPTION("Switch class driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/switch/switch_gpio.c b/drivers/switch/switch_gpio.c
new file mode 100644
index 00000000000..b5f98ca0b2e
--- /dev/null
+++ b/drivers/switch/switch_gpio.c
@@ -0,0 +1,171 @@
+/*
+ *  drivers/switch/switch_gpio.c
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/switch.h>
+#include <linux/workqueue.h>
+#include <linux/gpio.h>
+
+struct gpio_switch_data {
+	struct switch_dev sdev;
+	unsigned gpio;
+	const char *name_on;
+	const char *name_off;
+	const char *state_on;
+	const char *state_off;
+	int irq;
+	struct work_struct work;
+};
+
+static void gpio_switch_work(struct work_struct *work)
+{
+	int state;
+	struct gpio_switch_data	*data =
+		container_of(work, struct gpio_switch_data, work);
+
+	state = gpio_get_value(data->gpio);
+	switch_set_state(&data->sdev, state);
+}
+
+static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
+{
+	struct gpio_switch_data *switch_data =
+	    (struct gpio_switch_data *)dev_id;
+
+	schedule_work(&switch_data->work);
+	return IRQ_HANDLED;
+}
+
+static ssize_t switch_gpio_print_state(struct switch_dev *sdev, char *buf)
+{
+	struct gpio_switch_data	*switch_data =
+		container_of(sdev, struct gpio_switch_data, sdev);
+	const char *state;
+	if (switch_get_state(sdev))
+		state = switch_data->state_on;
+	else
+		state = switch_data->state_off;
+
+	if (state)
+		return sprintf(buf, "%s\n", state);
+	return -1;
+}
+
+static int gpio_switch_probe(struct platform_device *pdev)
+{
+	struct gpio_switch_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_switch_data *switch_data;
+	int ret = 0;
+
+	if (!pdata)
+		return -EBUSY;
+
+	switch_data = kzalloc(sizeof(struct gpio_switch_data), GFP_KERNEL);
+	if (!switch_data)
+		return -ENOMEM;
+
+	switch_data->sdev.name = pdata->name;
+	switch_data->gpio = pdata->gpio;
+	switch_data->name_on = pdata->name_on;
+	switch_data->name_off = pdata->name_off;
+	switch_data->state_on = pdata->state_on;
+	switch_data->state_off = pdata->state_off;
+	switch_data->sdev.print_state = switch_gpio_print_state;
+
+    ret = switch_dev_register(&switch_data->sdev);
+	if (ret < 0)
+		goto err_switch_dev_register;
+
+	ret = gpio_request(switch_data->gpio, pdev->name);
+	if (ret < 0)
+		goto err_request_gpio;
+
+	ret = gpio_direction_input(switch_data->gpio);
+	if (ret < 0)
+		goto err_set_gpio_input;
+
+	INIT_WORK(&switch_data->work, gpio_switch_work);
+
+	switch_data->irq = gpio_to_irq(switch_data->gpio);
+	if (switch_data->irq < 0) {
+		ret = switch_data->irq;
+		goto err_detect_irq_num_failed;
+	}
+
+	ret = request_irq(switch_data->irq, gpio_irq_handler,
+			  IRQF_TRIGGER_LOW, pdev->name, switch_data);
+	if (ret < 0)
+		goto err_request_irq;
+
+	/* Perform initial detection */
+	gpio_switch_work(&switch_data->work);
+
+	return 0;
+
+err_request_irq:
+err_detect_irq_num_failed:
+err_set_gpio_input:
+	gpio_free(switch_data->gpio);
+err_request_gpio:
+    switch_dev_unregister(&switch_data->sdev);
+err_switch_dev_register:
+	kfree(switch_data);
+
+	return ret;
+}
+
+static int __devexit gpio_switch_remove(struct platform_device *pdev)
+{
+	struct gpio_switch_data *switch_data = platform_get_drvdata(pdev);
+
+	cancel_work_sync(&switch_data->work);
+	gpio_free(switch_data->gpio);
+    switch_dev_unregister(&switch_data->sdev);
+	kfree(switch_data);
+
+	return 0;
+}
+
+static struct platform_driver gpio_switch_driver = {
+	.probe		= gpio_switch_probe,
+	.remove		= __devexit_p(gpio_switch_remove),
+	.driver		= {
+		.name	= "switch-gpio",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init gpio_switch_init(void)
+{
+	return platform_driver_register(&gpio_switch_driver);
+}
+
+static void __exit gpio_switch_exit(void)
+{
+	platform_driver_unregister(&gpio_switch_driver);
+}
+
+module_init(gpio_switch_init);
+module_exit(gpio_switch_exit);
+
+MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
+MODULE_DESCRIPTION("GPIO Switch driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/uio/Kconfig b/drivers/uio/Kconfig
index 8aa1955f35e..a69a49ae8d8 100644
--- a/drivers/uio/Kconfig
+++ b/drivers/uio/Kconfig
@@ -12,6 +12,15 @@ menuconfig UIO
 
 if UIO
 
+config UIODMA
+	bool "DMA support for user-space IO"
+	help
+	  UIO-DMA exposes existing DMA API provided by the Linux kernel to
+	  the user-space applications. It also provides methods for allocating
+	  and managing memory areas suitable for user-space DMA operations.
+
+	  If you don't know what to do here, say N.
+
 config UIO_CIF
 	tristate "generic Hilscher CIF Card driver"
 	depends on PCI
@@ -94,4 +103,13 @@ config UIO_PCI_GENERIC
 	  primarily, for virtualization scenarios.
 	  If you compile this as a module, it will be called uio_pci_generic.
 
+config UIO_AK98_VCODEC
+	tristate "Anyka Ak98 Video Codec support"
+	depends on ARCH_AK98
+	help
+	  This driver supports Video HW Codec on Anyka Ak98 SoC.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called uio_ak98_vcodec.
+
 endif
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index 73b2e751672..4bd8205fbd9 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_UIO)	+= uio.o
+obj-$(CONFIG_UIODMA)	+= uio-dma.o
 obj-$(CONFIG_UIO_CIF)	+= uio_cif.o
 obj-$(CONFIG_UIO_PDRV)	+= uio_pdrv.o
 obj-$(CONFIG_UIO_PDRV_GENIRQ)	+= uio_pdrv_genirq.o
@@ -6,3 +7,4 @@ obj-$(CONFIG_UIO_SMX)	+= uio_smx.o
 obj-$(CONFIG_UIO_AEC)	+= uio_aec.o
 obj-$(CONFIG_UIO_SERCOS3)	+= uio_sercos3.o
 obj-$(CONFIG_UIO_PCI_GENERIC)	+= uio_pci_generic.o
+obj-$(CONFIG_UIO_AK98_VCODEC)	+= uio_ak98_vcodec.o
diff --git a/drivers/uio/uio-dma.c b/drivers/uio/uio-dma.c
new file mode 100644
index 00000000000..8cfa5d96195
--- /dev/null
+++ b/drivers/uio/uio-dma.c
@@ -0,0 +1,869 @@
+/*
+   UIO-DMA kernel backend 
+   Copyright (C) 2009 Qualcomm Inc. All rights reserved.
+   Written by Max Krasnyansky <maxk@qualcommm.com>
+
+   The UIO-DMA is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The UIO-DMA is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/sysctl.h>
+#include <linux/wait.h>
+#include <linux/miscdevice.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/file.h>
+#include <asm/io.h>
+
+#include <linux/uio-dma.h>
+
+#ifdef DBG
+#define UIO_DMA_DBG(args...) printk(KERN_DEBUG "uio-dma: " args)
+#else
+#define UIO_DMA_DBG(args...)
+#endif
+
+#define UIO_DMA_INFO(args...) printk(KERN_INFO "uio-dma: " args)
+#define UIO_DMA_ERR(args...)  printk(KERN_ERR  "uio-dma: " args)
+
+#define VERSION "2.0"
+
+char uio_dma_driver_name[]    = "uio-dma";
+char uio_dma_driver_string[]  = "UIO DMA kernel backend";
+char uio_dma_driver_version[] = VERSION;
+char uio_dma_copyright[]      = "Copyright (c) 2009 Qualcomm Inc. Written by Max Krasnyansky <maxk@qualcomm.com>";
+
+/* List of active devices */
+static struct list_head uio_dma_dev_list;
+static struct mutex     uio_dma_dev_mutex;
+static uint32_t         uio_dma_dev_nextid;
+
+/* 
+ * DMA device.
+ * Holds a reference to 'struct device' and a list of DMA mappings
+ */
+struct uio_dma_device {
+	struct list_head  list;
+	struct list_head  mappings;
+	struct mutex      mutex;
+	atomic_t          refcount;
+	struct device    *device;
+	uint32_t          id;
+};
+
+/*
+ * DMA area.
+ * Describes a chunk of DMAable memory.
+ * Attached to a DMA context.
+ */
+struct uio_dma_area {
+	struct list_head  list;
+	atomic_t          refcount;
+	unsigned long     mmap_offset;
+	unsigned long     size;
+	unsigned int      chunk_size;
+	unsigned int      chunk_count;
+	uint8_t           cache;
+	void             *addr[0];
+};
+
+/*
+ * DMA mapping.
+ * Attached to a device.
+ * Holds a reference to an area.
+ */
+struct uio_dma_mapping {
+	struct list_head     list;
+	struct uio_dma_area *area;
+	unsigned int         direction;
+	uint64_t             dmaddr[0];
+};
+
+/*
+ * DMA context. 
+ * Attached to a fd. 
+ */
+struct uio_dma_context {
+	struct mutex      mutex;
+	struct list_head  areas;
+};
+
+static void uio_dma_mapping_del(struct uio_dma_device *ud, struct uio_dma_mapping *m);
+
+/* ---- Devices ---- */
+static void uio_dma_device_lock(struct uio_dma_device *ud)
+{
+	mutex_lock(&ud->mutex);
+}
+
+static void uio_dma_device_unlock(struct uio_dma_device *ud)
+{
+	mutex_unlock(&ud->mutex);
+}
+
+/*
+ * Drop all mappings on this device
+ */
+static void __drop_dev_mappings(struct uio_dma_device *ud)
+{
+	struct uio_dma_mapping *m, *n;
+	list_for_each_entry_safe(m, n, &ud->mappings, list)
+		uio_dma_mapping_del(ud, m);
+}
+
+/*
+ * Free the last reference to the UIO DMA device.
+ * Drops all mappings and releases 'struct device'.
+ */
+static void uio_dma_device_free(struct uio_dma_device *ud)
+{
+	__drop_dev_mappings(ud);
+
+	UIO_DMA_DBG("freed device. %s\n", dev_name(ud->device));
+	put_device(ud->device);
+	kfree(ud);
+}
+
+static struct uio_dma_device *uio_dma_device_get(struct uio_dma_device *ud)
+{
+	atomic_inc(&ud->refcount);
+	return ud;
+}
+
+static void uio_dma_device_put(struct uio_dma_device *ud)
+{
+	if (atomic_dec_and_test(&ud->refcount))
+		uio_dma_device_free(ud);
+}
+
+/*
+ * Lookup UIO DMA device based by id.
+ * Must be called under uio_dma_dev_mutex.
+ * Increments device refcount if found.
+ */
+static struct uio_dma_device* __device_lookup(uint32_t id)
+{
+	struct uio_dma_device *ud;
+	list_for_each_entry(ud, &uio_dma_dev_list, list) {
+		if (ud->id == id)
+			return uio_dma_device_get(ud);
+	}
+	return NULL;
+}
+
+/*
+ * Lookup device by uio dma id.
+ * Caller must drop the reference to the returned
+ * device when it's done with it.
+ */
+static struct uio_dma_device* uio_dma_device_lookup(uint32_t id)
+{
+	struct uio_dma_device *ud;
+	mutex_lock(&uio_dma_dev_mutex);
+	ud = __device_lookup(id);
+	mutex_unlock(&uio_dma_dev_mutex);
+	return ud;
+}
+
+/**
+ * Open UIO DMA device (UIO driver interface).
+ * UIO driver calls this function to allocate new device id 
+ * which can then be used by user space to create DMA mappings.
+ */
+int uio_dma_device_open(struct device *dev, uint32_t *id)
+{
+	struct uio_dma_device *ud = kzalloc(sizeof(*ud), GFP_KERNEL);
+	if (!ud)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&ud->mappings);
+	mutex_init(&ud->mutex);
+	atomic_set(&ud->refcount, 1);
+
+	ud->device = get_device(dev);
+	if (!ud->device) {
+		kfree(ud);
+		return -ENODEV;
+	}
+
+	mutex_lock(&uio_dma_dev_mutex);
+	ud->id = uio_dma_dev_nextid++;
+	list_add(&ud->list, &uio_dma_dev_list);
+	mutex_unlock(&uio_dma_dev_mutex);
+
+	*id = ud->id;
+
+	UIO_DMA_DBG("added device. id %u %s\n", *id, dev_name(dev));
+        return 0;
+}
+EXPORT_SYMBOL(uio_dma_device_open);
+
+/**
+ * Close UIO DMA device (UIO driver interface).
+ * UIO driver calls this function when the device is closed.
+ * All current mappings are destroyed.
+ */
+int uio_dma_device_close(uint32_t id)
+{
+	struct uio_dma_device *ud;
+
+	// This can race with uio_dma_mapping_add(), which is perfectly save. 
+	// Mappings will be cleaned up when uio_dma_mapping_add() releases 
+	// the reference.
+
+	mutex_lock(&uio_dma_dev_mutex);
+	ud = __device_lookup(id);
+	if (!ud) {
+		UIO_DMA_DBG("removing bad device. id %u\n", id);
+		mutex_unlock(&uio_dma_dev_mutex);
+		return -ENOENT;
+	}
+
+	list_del(&ud->list);
+	uio_dma_device_put(ud);
+	mutex_unlock(&uio_dma_dev_mutex);
+
+	UIO_DMA_DBG("removed device. id %u %s\n", id, dev_name(ud->device));
+
+	uio_dma_device_put(ud);
+	return 0;
+}
+EXPORT_SYMBOL(uio_dma_device_close);
+
+/* ---- Areas ---- */
+static inline struct page *__last_page(void *addr, unsigned long size)
+{
+	return virt_to_page(addr + (PAGE_SIZE << get_order(size)) - 1);
+}
+
+/*
+ * Release DMA area.
+ * Called only after all references to this area have been dropped.
+ */
+static void uio_dma_area_free(struct uio_dma_area *area)
+{
+	struct page *page, *last;
+	int i;
+
+	UIO_DMA_DBG("area free. %p mmap_offset %lu\n", area, area->mmap_offset);
+
+	for (i=0; i < area->chunk_count; i++) {
+		last = __last_page(area->addr[i], area->chunk_size);
+		for (page = virt_to_page(area->addr[i]); page <= last; page++)
+			ClearPageReserved(page);
+
+		free_pages((unsigned long) area->addr[i], get_order(area->chunk_size));
+	}
+
+	kfree(area);
+}
+
+/*
+ * Allocate new DMA area.
+ */
+static struct uio_dma_area *uio_dma_area_alloc(uint64_t dma_mask, unsigned int memnode, 
+		unsigned int cache, unsigned int chunk_size, unsigned int chunk_count)
+{
+	struct uio_dma_area *area;
+	struct page *page, *last;
+	int i, gfp;
+
+	area = kzalloc(sizeof(*area) + sizeof(void *) * chunk_count, GFP_KERNEL);
+	if (!area)
+		return NULL;
+
+	UIO_DMA_DBG("area alloc. area %p chunk_size %u chunk_count %u\n", 
+		area, chunk_size, chunk_count);
+
+	gfp = GFP_KERNEL | __GFP_NOWARN;
+	if (dma_mask < DMA_64BIT_MASK) {
+		if (dma_mask < DMA_32BIT_MASK)
+			gfp |= GFP_DMA;
+		else
+			gfp |= GFP_DMA32;
+	}
+
+	atomic_set(&area->refcount, 1);
+
+	area->chunk_size  = chunk_size;
+	area->chunk_count = chunk_count;
+	area->size = chunk_size * chunk_count;
+	area->cache = cache;
+
+	for (i=0; i < chunk_count; i++) {
+		page = alloc_pages_node(memnode, gfp, get_order(chunk_size));
+		if (!page) {
+			area->chunk_count = i;
+			uio_dma_area_free(area);
+			return NULL;
+		}
+
+		area->addr[i] = page_address(page);
+
+		last = __last_page(area->addr[i], chunk_size);
+		for (; page <= last; page++)
+			SetPageReserved(page);
+	}
+
+	return area;
+}
+
+static struct uio_dma_area *uio_dma_area_get(struct uio_dma_area *area)
+{
+	atomic_inc(&area->refcount);
+	return area;
+}
+
+static void uio_dma_area_put(struct uio_dma_area *area)
+{
+	if (atomic_dec_and_test(&area->refcount))
+		uio_dma_area_free(area);
+}
+
+/*
+ * Look up DMA area by offset.
+ * Must be called under context mutex.
+ */
+static struct uio_dma_area *uio_dma_area_lookup(struct uio_dma_context *uc, uint64_t offset)
+{
+	struct uio_dma_area *area;
+
+	UIO_DMA_DBG("area lookup. context %p offset %llu\n", uc, (unsigned long long) offset);
+
+	list_for_each_entry(area, &uc->areas, list) {
+		if (area->mmap_offset == offset)
+			return area;
+	}
+
+	return NULL;
+}
+
+/* ---- Mappings ---- */
+
+/*
+ * Delete DMA mapping.
+ * Must be called under device mutex.
+ */
+static void uio_dma_mapping_del(struct uio_dma_device *ud, struct uio_dma_mapping *m)
+{
+	unsigned int i;
+
+	UIO_DMA_DBG("mapping del. device %s mapping %p area %p\n",
+		dev_name(ud->device), m, m->area);
+
+	for (i=0; i < m->area->chunk_count; i++)
+ 		dma_unmap_single(ud->device, m->dmaddr[i], m->area->chunk_size, m->direction);
+	list_del(&m->list);
+
+	uio_dma_area_put(m->area);
+	kfree(m);
+}
+
+/*
+ * Add new DMA mapping.
+ * Must be called under device mutex.
+ */
+static int uio_dma_mapping_add(struct uio_dma_device *ud, struct uio_dma_area *area, 
+				unsigned int dir, struct uio_dma_mapping **map)
+{
+	struct uio_dma_mapping *m;
+	int i, n, err;
+
+	m = kzalloc(sizeof(*m) + sizeof(dma_addr_t) * area->chunk_count, GFP_KERNEL);
+	if (!m)
+		return -ENOMEM;
+
+	UIO_DMA_DBG("maping add. device %s area %p chunk_size %u chunk_count %u\n",
+			dev_name(ud->device), area, area->chunk_size, area->chunk_count);
+
+	m->area      = uio_dma_area_get(area);
+	m->direction = dir;
+	for (i=0; i < area->chunk_count; i++) {
+        	m->dmaddr[i] = dma_map_single(ud->device, area->addr[i], area->chunk_size, dir);
+        	if (!m->dmaddr[i]) {
+			err = -EBADSLT;
+			goto failed;
+		}
+		UIO_DMA_DBG("maped. device %s area %p chunk #%u dmaddr %llx\n",
+				dev_name(ud->device), area, i,
+				(unsigned long long) m->dmaddr[i]);
+	}
+
+	list_add(&m->list, &ud->mappings);
+
+	*map = m;
+	return 0;
+
+failed:
+	for (n = 0; n < i; n++)
+ 		dma_unmap_single(ud->device, m->dmaddr[n], m->area->chunk_size, dir);
+	uio_dma_area_put(m->area);
+	kfree(m);
+	return err;
+}
+
+/*
+ * Look up DMA mapping by area and direction.
+ * Must be called under device mutex.
+ */
+static struct uio_dma_mapping *uio_dma_mapping_lookup(
+		struct uio_dma_device *ud, struct uio_dma_area *area,
+		unsigned int dir)
+{
+	struct uio_dma_mapping *m;
+
+	UIO_DMA_DBG("mapping lookup. device %s area %p dir %u\n",
+				dev_name(ud->device), area, dir);
+
+	list_for_each_entry(m, &ud->mappings, list) {
+		if (m->area == area && m->direction == dir)
+			return m;
+	}
+
+	return NULL;
+}
+
+/* ---- Context ---- */
+static void uio_dma_context_lock(struct uio_dma_context *uc)
+{
+	mutex_lock(&uc->mutex);
+}
+
+static void uio_dma_context_unlock(struct uio_dma_context *uc)
+{
+	mutex_unlock(&uc->mutex);
+}
+
+/* ---- User interface ---- */
+
+/*
+ * Make sure new area (offset & size) does not everlap with
+ * the existing areas and return list_head to append new area to.
+ * Must be called under context mutex.
+ */
+static struct list_head *append_to(struct uio_dma_context *uc, 
+					uint64_t *offset, unsigned int size)
+{
+	unsigned long start, end, astart, aend;
+	struct uio_dma_area *area;
+	struct list_head *last;
+
+	start = *offset;
+	end   = start + size;
+
+	UIO_DMA_DBG("adding area. context %p start %lu end %lu\n", uc, start, end);
+
+	last  = &uc->areas;
+
+	list_for_each_entry(area, &uc->areas, list) {
+		astart = area->mmap_offset;
+		aend   = astart + area->size;
+
+		UIO_DMA_DBG("checking area. context %p start %lu end %lu\n", uc, astart, aend);
+
+		/* Since the list is sorted we know at this point that 
+ 		 * new area goes before this one. */
+		if (end <= astart)
+			break;
+
+		last = &area->list;
+
+		if ((start >= astart && start < aend) ||
+				(end > astart && end <= aend)) {
+			/* Found overlap. Set start to the end of the current
+ 			 * area and keep looking. */
+			start = aend;
+			end   = start + size;
+			continue;
+		}
+	}
+
+	*offset = start;
+	return last;
+}
+
+static int uio_dma_cmd_alloc(struct uio_dma_context *uc, void __user *argp)
+{
+	struct uio_dma_alloc_req req;
+	struct uio_dma_area *area;
+	struct list_head *where;
+	unsigned long size;
+
+	if (copy_from_user(&req, argp, sizeof(req)))
+		return -EFAULT;
+
+	if (!req.chunk_size || !req.chunk_count)
+		return -EINVAL; 
+
+	req.chunk_size = roundup(req.chunk_size, PAGE_SIZE);
+	size = req.chunk_size * req.chunk_count;
+
+	UIO_DMA_DBG("alloc req enter. context %p offset %llu chunk_size %u chunk_count %u (total %lu)\n",
+		uc, (unsigned long long) req.mmap_offset, req.chunk_size, req.chunk_count, size);
+
+	where = append_to(uc, &req.mmap_offset, size);
+	if (!where)
+		return -EBUSY;
+
+	area = uio_dma_area_alloc(req.dma_mask, req.memnode, req.cache, req.chunk_size, req.chunk_count);
+	if (!area)
+		return -ENOMEM;
+
+	/* Add to the context */
+	area->mmap_offset = req.mmap_offset;
+	list_add(&area->list, where);
+
+	if (copy_to_user(argp, &req, sizeof(req))) {
+		list_del(&area->list);
+		uio_dma_area_put(area);
+		return EFAULT;
+	}
+
+	UIO_DMA_DBG("alloc req exit. context %p offset %llu size %lu mask %llx node %u\n", uc,
+		(unsigned long long) area->mmap_offset, area->size,
+		(unsigned long long) req.dma_mask, req.memnode);
+	return 0;
+}
+
+static int uio_dma_cmd_free(struct uio_dma_context *uc, void __user *argp)
+{
+	struct uio_dma_free_req req;
+	struct uio_dma_area *area;
+
+	if (copy_from_user(&req, argp, sizeof(req)))
+		return -EFAULT;
+
+	UIO_DMA_DBG("free req. context %p offset %llu\n", uc, req.mmap_offset);
+
+	area = uio_dma_area_lookup(uc, req.mmap_offset);
+	if (!area)
+		return -ENOENT;
+
+	list_del(&area->list);
+	uio_dma_area_put(area);
+
+	return 0;
+}
+
+static int uio_dma_cmd_map(struct uio_dma_context *uc, void __user *argp)
+{
+	struct uio_dma_map_req req;
+	struct uio_dma_mapping *m;
+	struct uio_dma_area *area;
+	struct uio_dma_device *ud;
+	int err;
+
+	if (copy_from_user(&req, argp, sizeof(req)))
+		return -EFAULT;
+
+	UIO_DMA_DBG("map req. context %p offset %llu devid %u\n", uc, req.mmap_offset, req.devid);
+
+	area = uio_dma_area_lookup(uc, req.mmap_offset);
+	if (!area)
+		return -ENOENT;
+
+	if (req.chunk_count < area->chunk_count)
+		return -EINVAL;
+
+	ud = uio_dma_device_lookup(req.devid);
+	if (!ud)
+		return -ENODEV;
+	uio_dma_device_lock(ud);
+
+	m = uio_dma_mapping_lookup(ud, area, req.direction);
+	if (m) {
+		err = -EALREADY;
+		goto out;
+	}
+
+	err = uio_dma_mapping_add(ud, area, req.direction, &m);
+	if (err)
+		goto out;
+
+	req.chunk_count = area->chunk_count;
+	req.chunk_size  = area->chunk_size;
+
+	if (copy_to_user(argp, &req, sizeof(req)))
+		goto fault;
+
+	/* Copy dma addresses */
+	if (copy_to_user(argp + sizeof(req), m->dmaddr, sizeof(uint64_t) * area->chunk_count))
+		goto fault;
+
+	err = 0;
+	goto out;
+
+fault:
+	err = EFAULT;
+	uio_dma_mapping_del(ud, m);
+out:
+	uio_dma_device_unlock(ud);
+	uio_dma_device_put(ud);
+	return err;
+}
+
+static int uio_dma_cmd_unmap(struct uio_dma_context *uc, void __user *argp)
+{
+	struct uio_dma_unmap_req req;
+	struct uio_dma_area *area;
+	struct uio_dma_mapping *m;
+	struct uio_dma_device *ud;
+	int err;
+
+	if (copy_from_user(&req, argp, sizeof(req)))
+		return -EFAULT;
+
+	UIO_DMA_DBG("map req. context %p offset %llu devid %u\n", uc, req.mmap_offset, req.devid);
+
+	area = uio_dma_area_lookup(uc, req.mmap_offset);
+	if (!area)
+		return -ENOENT;
+
+	ud = uio_dma_device_lookup(req.devid);
+	if (!ud)
+		return -ENODEV;
+	uio_dma_device_lock(ud);
+
+	err = -ENOENT;
+	m = uio_dma_mapping_lookup(ud, area, req.direction);
+	if (m) {
+		uio_dma_mapping_del(ud, m);
+		err = 0;
+	}
+
+	uio_dma_device_unlock(ud);
+	uio_dma_device_put(ud);
+	return err;
+}
+
+static long uio_dma_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct uio_dma_context *uc = file->private_data;
+	void __user * argp = (void __user *) arg;
+	int err;
+
+	UIO_DMA_DBG("ioctl. context %p cmd %d arg %lu\n", uc, cmd, arg);
+	if (!uc)
+		return -EBADFD;
+
+	uio_dma_context_lock(uc);
+
+	switch (cmd) {
+	case UIO_DMA_ALLOC:
+		err = uio_dma_cmd_alloc(uc, argp);
+		break;
+
+	case UIO_DMA_MAP:
+		err = uio_dma_cmd_map(uc, argp);
+		break;
+
+	case UIO_DMA_UNMAP:
+		err = uio_dma_cmd_unmap(uc, argp);
+		break;
+
+	case UIO_DMA_FREE:
+		err = uio_dma_cmd_free(uc, argp);
+		break;
+
+	default:
+		err = -EINVAL;
+		break;
+	};
+
+	uio_dma_context_unlock(uc);
+	return err;
+}
+
+static void __drop_ctx_areas(struct uio_dma_context *uc)
+{
+	struct uio_dma_area *area, *n;
+	list_for_each_entry_safe(area, n, &uc->areas, list)
+		uio_dma_area_put(area);
+}
+
+static int uio_dma_close(struct inode *inode, struct file *file)
+{
+	struct uio_dma_context *uc = file->private_data;
+	if (!uc)
+		return 0;
+
+	UIO_DMA_DBG("closed context %p\n", uc);
+
+	__drop_ctx_areas(uc);
+
+	file->private_data = NULL;
+	kfree(uc);
+	return 0;
+}
+
+static int uio_dma_open(struct inode *inode, struct file * file)
+{
+	struct uio_dma_context *uc;
+	
+	/* Allocate new context */
+	uc = kzalloc(sizeof(*uc), GFP_KERNEL);
+	if (!uc)
+		return -ENOMEM;
+
+	mutex_init(&uc->mutex);
+	INIT_LIST_HEAD(&uc->areas);
+
+	file->private_data = uc;
+
+	UIO_DMA_DBG("created context %p\n", uc);
+	return 0;
+}
+
+static unsigned int uio_dma_poll(struct file *file, poll_table *wait)
+{  
+	return -ENOSYS;
+}
+
+static ssize_t uio_dma_read(struct file * file, char __user * buf, 
+			    size_t count, loff_t *pos)
+{
+	return -ENOSYS;
+}
+
+static ssize_t uio_dma_write(struct file * file, const char __user * buf,
+			     size_t count, loff_t *pos)
+{
+	return -ENOSYS;
+}
+
+static void uio_dma_vm_open(struct vm_area_struct *vma)
+{
+}
+
+static void uio_dma_vm_close(struct vm_area_struct *vma)
+{
+}
+
+static int uio_dma_vm_fault(struct vm_area_struct *area, 
+			struct vm_fault *fdata)
+{
+	return VM_FAULT_SIGBUS;
+}
+
+static struct vm_operations_struct uio_dma_mmap_ops = {
+	.open   = uio_dma_vm_open,
+	.close  = uio_dma_vm_close,
+	.fault  = uio_dma_vm_fault
+};
+
+static int uio_dma_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct uio_dma_context *uc = file->private_data;
+	struct uio_dma_area *area;
+
+	unsigned long start  = vma->vm_start;
+	unsigned long size   = vma->vm_end - vma->vm_start;
+	unsigned long offset = vma->vm_pgoff * PAGE_SIZE;
+	unsigned long pfn;
+	int i;
+
+	if (!uc)
+		return -EBADFD;
+
+	UIO_DMA_DBG("mmap. context %p start %lu size %lu offset %lu\n", uc, start, size, offset);
+
+	// Find an area that matches the offset and mmap it.
+	area = uio_dma_area_lookup(uc, offset);	
+	if (!area)
+		return -ENOENT;
+
+	// We do not do partial mappings, sorry
+	if (area->size != size)
+		return -EOVERFLOW;
+
+	switch (area->cache) {
+	case UIO_DMA_CACHE_DISABLE:
+		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+		break;
+
+	case UIO_DMA_CACHE_WRITECOMBINE:
+		#ifdef pgprot_writecombine
+		vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+		#endif
+		break;
+
+	default:
+		/* Leave as is */
+		break;
+	}
+
+	for (i=0; i < area->chunk_count; i++) {
+		pfn = page_to_pfn(virt_to_page(area->addr[i]));
+		if (remap_pfn_range(vma, start, pfn, area->chunk_size, vma->vm_page_prot))
+			return -EIO;
+
+		start += area->chunk_size;
+	}
+
+	vma->vm_ops = &uio_dma_mmap_ops;
+	return 0;
+}
+
+static struct file_operations uio_dma_fops = {
+	.owner	 = THIS_MODULE,
+	.llseek  = no_llseek,
+	.read	 = uio_dma_read,
+	.write	 = uio_dma_write,
+	.poll	 = uio_dma_poll,
+	.open	 = uio_dma_open,
+	.release = uio_dma_close,
+	.mmap	 = uio_dma_mmap,
+	.unlocked_ioctl = uio_dma_ioctl,
+};
+
+static struct miscdevice uio_dma_miscdev = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "uio-dma",
+	.fops = &uio_dma_fops,
+};
+
+int uio_dma_init_module(void)
+{
+	int err;
+
+	INIT_LIST_HEAD(&uio_dma_dev_list);
+	mutex_init(&uio_dma_dev_mutex);
+
+	printk(KERN_INFO "%s - version %s\n", uio_dma_driver_string, uio_dma_driver_version);
+	printk(KERN_INFO "%s\n", uio_dma_copyright);
+
+	err = misc_register(&uio_dma_miscdev);
+	if (err) {
+		UIO_DMA_ERR("failed to register misc device\n");
+		return err;
+	}
+
+	return err;
+}
+
+void uio_dma_exit_module(void)
+{
+	misc_deregister(&uio_dma_miscdev);
+}
+
+EXPORT_SYMBOL(uio_dma_init_module);
+EXPORT_SYMBOL(uio_dma_exit_module);
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
index e941367dd28..0fa7bfae251 100644
--- a/drivers/uio/uio.c
+++ b/drivers/uio/uio.c
@@ -519,6 +519,19 @@ static int uio_release(struct inode *inode, struct file *filep)
 	return ret;
 }
 
+static long uio_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+{
+	struct uio_listener *listener = filep->private_data;
+	struct uio_device *idev = listener->dev;
+	int ret;
+
+	ret = EINVAL;
+	if (idev->info->ioctl)
+		ret = idev->info->ioctl(idev->info, cmd, arg);
+
+	return ret;
+}
+
 static unsigned int uio_poll(struct file *filep, poll_table *wait)
 {
 	struct uio_listener *listener = filep->private_data;
@@ -739,6 +752,7 @@ static const struct file_operations uio_fops = {
 	.mmap		= uio_mmap,
 	.poll		= uio_poll,
 	.fasync		= uio_fasync,
+	.unlocked_ioctl = uio_ioctl,
 };
 
 static int uio_major_init(void)
@@ -868,8 +882,20 @@ int __uio_register_device(struct module *owner,
 			goto err_request_irq;
 	}
 
+#ifdef CONFIG_UIODMA
+	if (idev->info->use_dma) {
+		ret = uio_dma_device_open(idev->dev, &(idev->info->dma_dev_id));
+		if (ret)
+			goto err_open_dma;
+	}
+#endif
+
 	return 0;
 
+#ifdef CONFIG_UIODMA
+err_open_dma:
+	free_irq(idev->info->irq, idev);
+#endif
 err_request_irq:
 	uio_dev_del_attributes(idev);
 err_uio_dev_add_attributes:
@@ -900,6 +926,11 @@ void uio_unregister_device(struct uio_info *info)
 
 	uio_free_minor(idev);
 
+#ifdef CONFIG_UIODMA
+	if (info->use_dma)
+		uio_dma_device_close(info->dma_dev_id);
+#endif
+
 	if (info->irq >= 0)
 		free_irq(info->irq, idev);
 
@@ -916,11 +947,18 @@ EXPORT_SYMBOL_GPL(uio_unregister_device);
 
 static int __init uio_init(void)
 {
+#ifdef CONFIG_UIODMA
+	return uio_dma_init_module();
+#else
 	return 0;
+#endif
 }
 
 static void __exit uio_exit(void)
 {
+#ifdef CONFIG_UIODMA
+	uio_dma_exit_module();
+#endif
 }
 
 module_init(uio_init)
diff --git a/drivers/uio/uio_ak98_vcodec.c b/drivers/uio/uio_ak98_vcodec.c
new file mode 100644
index 00000000000..ca22ae1f9da
--- /dev/null
+++ b/drivers/uio/uio_ak98_vcodec.c
@@ -0,0 +1,230 @@
+/*
+ * drivers/uio/uio_ak98_vcodec.c
+ *
+ * Userspace I/O driver for anyka ak98 soc video hardware codec.
+ * Based on uio_pdrv.c by Uwe Kleine-Koenig,
+ *
+ * Copyright (C) 2011 by Anyka Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
+#include <linux/semaphore.h>
+#include <asm/uaccess.h>
+
+#include <linux/akuio_driver.h>
+#include <mach/reg.h>
+
+#define DRIVER_NAME "uio_ak98_vcodec"
+
+const unsigned VIDEO_IRQ_MASK = (1 << IRQ_H264_DECODER) | (1 << IRQ_RMVB) \
+  | (1 << IRQ_MPEG2) | (1 << IRQ_JPEG) | (1 << IRQ_MOTIONESTIMATION) | (1 << IRQ_HUFFMAN);
+const int MASK_BITS_NUM = sizeof(VIDEO_IRQ_MASK) * 8;
+
+struct uio_platdata {
+	struct uio_info *uioinfo;
+	struct semaphore vcodec_sem;
+};
+
+static irqreturn_t ak98_vcodec_irq_handler(int irq, void *dev_id)
+{
+	struct uio_platdata *pdata = dev_id;
+	int i;
+
+	for (i = 0; i < MASK_BITS_NUM; i++)
+	{
+		if ((1 << i) & VIDEO_IRQ_MASK)
+			disable_irq_nosync(i);
+	}
+
+	up (&(pdata->vcodec_sem));
+
+	return IRQ_HANDLED;
+}
+
+static int uio_ak98_vcodec_ioctl(struct uio_info *uioinfo, unsigned int cmd, unsigned long arg)
+{
+	struct uio_platdata *pdata = uioinfo->priv;
+	int err;
+
+	switch (cmd) {
+	case AKUIO_SYSREG_WRITE:
+	{
+		struct akuio_sysreg_write_t reg_write;
+
+		if (copy_from_user(&reg_write, (void __user *)arg, sizeof(struct akuio_sysreg_write_t)))
+			return -EFAULT;
+
+		ak98_sys_ctrl_reg_set(reg_write.paddr, reg_write.mask, reg_write.val);
+
+		err = 0;
+	}
+	break;
+
+	case AKUIO_WAIT_IRQ:
+	{
+		int i;
+
+		for (i = 0; i < MASK_BITS_NUM; i++)
+		{
+			if ((1 << i) & VIDEO_IRQ_MASK)
+				enable_irq(i);
+		}
+
+		down (&pdata->vcodec_sem);
+		err = 0;
+	}
+	break;
+
+	default:
+		err = -EINVAL;
+		break;
+	};
+
+	return err;
+}
+
+static int uio_ak98_vcodec_open(struct uio_info *uioinfo, struct inode *inode)
+{
+	struct uio_platdata *pdata = uioinfo->priv;
+	int i;
+
+	init_MUTEX_LOCKED(&(pdata->vcodec_sem));
+
+	for (i = 0; i < MASK_BITS_NUM; i++)
+	{
+		if ((1 << i) & VIDEO_IRQ_MASK) {
+			request_irq(i, ak98_vcodec_irq_handler, IRQF_DISABLED, "AK98 VIDEO HW CODEC", pdata);
+			disable_irq_nosync(i);
+		}
+	}
+
+	return 0;
+}
+
+static int uio_ak98_vcodec_release(struct uio_info *uioinfo, struct inode *inode)
+{
+	struct uio_platdata *pdata = uioinfo->priv;
+	int i;
+
+	for (i = 0; i < MASK_BITS_NUM; i++)
+	{
+		if ((1 << i) & VIDEO_IRQ_MASK)
+			free_irq(i, pdata);
+	}
+
+	return 0;
+}
+
+static int uio_ak98_vcodec_probe(struct platform_device *pdev)
+{
+	struct uio_info *uioinfo = pdev->dev.platform_data;
+	struct uio_platdata *pdata;
+	struct uio_mem *uiomem;
+	int ret = -ENODEV;
+	int i;
+
+	if (!uioinfo || !uioinfo->name || !uioinfo->version) {
+		dev_dbg(&pdev->dev, "%s: err_uioinfo\n", __func__);
+		goto err_uioinfo;
+	}
+
+	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+	if (!pdata) {
+		ret = -ENOMEM;
+		dev_dbg(&pdev->dev, "%s: err_alloc_pdata\n", __func__);
+		goto err_alloc_pdata;
+	}
+
+	pdata->uioinfo = uioinfo;
+
+	uiomem = &uioinfo->mem[0];
+
+	for (i = 0; i < pdev->num_resources; ++i) {
+		struct resource *r = &pdev->resource[i];
+
+		if (r->flags != IORESOURCE_MEM)
+			continue;
+
+		if (uiomem >= &uioinfo->mem[MAX_UIO_MAPS]) {
+			dev_warn(&pdev->dev, "device has more than "
+					__stringify(MAX_UIO_MAPS)
+					" I/O memory resources.\n");
+			break;
+		}
+
+		uiomem->memtype = UIO_MEM_PHYS;
+		uiomem->addr = r->start;
+		uiomem->size = r->end - r->start + 1;
+		++uiomem;
+	}
+
+	while (uiomem < &uioinfo->mem[MAX_UIO_MAPS]) {
+		uiomem->size = 0;
+		++uiomem;
+	}
+
+	/* irq */
+	pdata->uioinfo->irq = UIO_IRQ_CUSTOM;
+
+	/* file handle */
+	pdata->uioinfo->open = uio_ak98_vcodec_open;
+	pdata->uioinfo->release = uio_ak98_vcodec_release;
+	pdata->uioinfo->ioctl = uio_ak98_vcodec_ioctl;
+
+	pdata->uioinfo->priv = pdata;
+
+	ret = uio_register_device(&pdev->dev, pdata->uioinfo);
+
+	if (ret) {
+		kfree(pdata);
+err_alloc_pdata:
+err_uioinfo:
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, pdata);
+
+	return 0;
+}
+
+static int uio_ak98_vcodec_remove(struct platform_device *pdev)
+{
+	struct uio_platdata *pdata = platform_get_drvdata(pdev);
+
+	uio_unregister_device(pdata->uioinfo);
+
+	kfree(pdata);
+
+	return 0;
+}
+
+static struct platform_driver uio_ak98_vcodec = {
+	.probe = uio_ak98_vcodec_probe,
+	.remove = uio_ak98_vcodec_remove,
+	.driver = {
+		.name = DRIVER_NAME,
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init uio_ak98_vcodec_init(void)
+{
+	return platform_driver_register(&uio_ak98_vcodec);
+}
+
+static void __exit uio_ak98_vcodec_exit(void)
+{
+	platform_driver_unregister(&uio_ak98_vcodec);
+}
+module_init(uio_ak98_vcodec_init);
+module_exit(uio_ak98_vcodec_exit);
+
+MODULE_AUTHOR("Jacky Lau");
+MODULE_DESCRIPTION("Userspace driver for anyka ak98 video hw codec");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index be3c9b80bc9..8b5b94afd5f 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_USB_UHCI_HCD)	+= host/
 obj-$(CONFIG_USB_FHCI_HCD)	+= host/
 obj-$(CONFIG_USB_XHCI_HCD)	+= host/
 obj-$(CONFIG_USB_SL811_HCD)	+= host/
+obj-$(CONFIG_USB_AK98_FS_HCD)	+= host/
 obj-$(CONFIG_USB_ISP1362_HCD)	+= host/
 obj-$(CONFIG_USB_U132_HCD)	+= host/
 obj-$(CONFIG_USB_R8A66597_HCD)	+= host/
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 34de475f016..4facb7f24fd 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -1707,9 +1707,21 @@ void usb_hcd_reset_endpoint(struct usb_device *udev,
 {
 	struct usb_hcd *hcd = bus_to_hcd(udev->bus);
 
-	if (hcd->driver->endpoint_reset)
+	if (hcd->driver->endpoint_reset) {
+#ifdef CONFIG_ARCH_AK98
+		int epnum = usb_endpoint_num(&ep->desc);
+		int is_out = usb_endpoint_dir_out(&ep->desc);
+		int is_control = usb_endpoint_xfer_control(&ep->desc);
+
+		usb_settoggle(udev, epnum, is_out, 0);
+		if (is_control)
+			usb_settoggle(udev, epnum, !is_out, 0);
+		if (udev != hcd->self.root_hub)
+			hcd->driver->endpoint_reset(hcd, ep);
+#else
 		hcd->driver->endpoint_reset(hcd, ep);
-	else {
+#endif
+	} else {
 		int epnum = usb_endpoint_num(&ep->desc);
 		int is_out = usb_endpoint_dir_out(&ep->desc);
 		int is_control = usb_endpoint_xfer_control(&ep->desc);
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index a18e3c5dd82..e8795c85e59 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -504,6 +504,8 @@ config USB_LANGWELL
 	default USB_GADGET
 	select USB_GADGET_SELECTED
 
+source "drivers/usb/gadget/ak88-udc/Kconfig"
+source "drivers/usb/gadget/ak98-udc/Kconfig"
 
 #
 # LAST -- dummy/emulated controller
@@ -780,6 +782,48 @@ config USB_G_PRINTER
 	  For more information, see Documentation/usb/gadget_printer.txt
 	  which includes sample code for accessing the device file.
 
+config USB_ANDROID
+	boolean "Android Gadget"
+	depends on SWITCH
+	help
+	  The Android gadget driver supports multiple USB functions.
+	  The functions can be configured via a board file and may be
+	  enabled and disabled dynamically.
+
+config USB_ANDROID_ACM
+	boolean "Android gadget ACM serial function"
+	depends on USB_ANDROID
+	help
+	  Provides ACM serial function for android gadget driver.
+
+config USB_ANDROID_ADB
+	boolean "Android gadget adb function"
+	depends on USB_ANDROID
+	help
+	  Provides adb function for android gadget driver.
+
+config USB_ANDROID_MASS_STORAGE
+	boolean "Android gadget mass storage function"
+	depends on USB_ANDROID && SWITCH
+	help
+	  Provides USB mass storage function for android gadget driver.
+
+config USB_ANDROID_RNDIS
+	boolean "Android gadget RNDIS ethernet function"
+	depends on USB_ANDROID
+	help
+	  Provides RNDIS ethernet function for android gadget driver.
+
+config USB_ANDROID_RNDIS_WCEIS
+        boolean "Use Windows Internet Sharing Class/SubClass/Protocol"
+        depends on USB_ANDROID_RNDIS
+        help
+         Causes the driver to look like a Windows-compatible Internet
+         Sharing device, so Windows auto-detects it.
+
+         If you enable this option, the device is no longer CDC ethernet
+         compatible.
+
 config USB_CDC_COMPOSITE
 	tristate "CDC Composite Device (Ethernet and ACM)"
 	depends on NET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 9d7b87c52e9..78ea5b836c1 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_USB_FSL_QE)	+= fsl_qe_udc.o
 obj-$(CONFIG_USB_CI13XXX)	+= ci13xxx_udc.o
 obj-$(CONFIG_USB_S3C_HSOTG)	+= s3c-hsotg.o
 obj-$(CONFIG_USB_LANGWELL)	+= langwell_udc.o
+obj-$(CONFIG_USB_AK88)		+= ak88-udc/
+obj-y						+= ak98-udc/
 
 #
 # USB gadget drivers
@@ -51,4 +53,9 @@ obj-$(CONFIG_USB_G_SERIAL)	+= g_serial.o
 obj-$(CONFIG_USB_G_PRINTER)	+= g_printer.o
 obj-$(CONFIG_USB_MIDI_GADGET)	+= g_midi.o
 obj-$(CONFIG_USB_CDC_COMPOSITE) += g_cdc.o
+obj-$(CONFIG_USB_ANDROID)	+= android.o
+obj-$(CONFIG_USB_ANDROID_ACM)	+= f_acm.o u_serial.o
+obj-$(CONFIG_USB_ANDROID_ADB)	+= f_adb.o
+obj-$(CONFIG_USB_ANDROID_MASS_STORAGE)	+= f_mass_storage.o
+obj-$(CONFIG_USB_ANDROID_RNDIS)	+= f_rndis.o u_ether.o
 
diff --git a/drivers/usb/gadget/ak88-udc/Kconfig b/drivers/usb/gadget/ak88-udc/Kconfig
new file mode 100644
index 00000000000..60c3fcb06f3
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/Kconfig
@@ -0,0 +1,13 @@
+config USB_GADGET_AK88
+	boolean "AK88 USB Device Port"
+	depends on ARCH_AK88
+	select USB_GADGET_SELECTED
+	select USB_GADGET_DUALSPEED
+	help
+	  AK88 OTG device support
+
+config USB_AK88
+	tristate
+	depends on USB_GADGET_AK88
+	default USB_GADGET
+
diff --git a/drivers/usb/gadget/ak88-udc/Makefile b/drivers/usb/gadget/ak88-udc/Makefile
new file mode 100644
index 00000000000..f3b2b4c3958
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/Makefile
@@ -0,0 +1,6 @@
+
+
+obj-$(CONFIG_USB_AK88)	+= ak88_udc.o
+obj-y					+= ak88_usbburn.o
+
+
diff --git a/drivers/usb/gadget/ak88-udc/ak88_l2.c b/drivers/usb/gadget/ak88-udc/ak88_l2.c
new file mode 100644
index 00000000000..b31e59e8909
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_l2.c
@@ -0,0 +1,215 @@
+/*
+ * support l2 dma
+ * 09-09-10 16:46:47
+ */
+
+#include <mach/ak880x_addr.h>
+
+#define UDC_L2_ENABLE
+//#undef UDC_L2_ENABLE
+
+#include <mach/l2.h>
+
+/* #define L2_BASE_ADDR	0x2002c000	//L2 PA*/
+#define L2_BASE_ADDR	AK88_VA_L2CTRL	//L2 VA
+/* #define L2_BUF_MEM_BASE_ADDR	    	0x48000000  //L2 Buffer start address */
+#define	L2_DMA_ADDR	AK88_L2CTRL_REG(0x00)
+#define	L2_DMA_CNT	AK88_L2CTRL_REG(0x40)
+#define	L2_DMA_REQ	AK88_L2CTRL_REG(0x80)
+#define	L2_FRAC_ADDR	AK88_L2CTRL_REG(0x84)
+#define	L2_COMBUF_CFG	AK88_L2CTRL_REG(0x88)
+#define	L2_UARTBUF_CFG	AK88_L2CTRL_REG(0x8c)
+#define	L2_ASSIGN_REG1	AK88_L2CTRL_REG(0x90)
+#define	L2_ASSIGN_REG2	AK88_L2CTRL_REG(0x94)
+#define	L2_LDMA_CFG	AK88_L2CTRL_REG(0x98)
+#define	L2_INT_ENA	AK88_L2CTRL_REG(0x9c)
+#define	L2_STAT_REG1	AK88_L2CTRL_REG(0xa0)
+#define	L2_STAT_REG2	AK88_L2CTRL_REG(0xa8)
+
+#define L2_SD_BUFX	2 /* assign l2 buf2 to sd */ 
+#define L2_USB_EP2	6 /* 4&&5 for nand */ 
+#define L2_USB_EP3	7
+
+#define l2_write(reg, val) __raw_writel((val), (reg))
+#define l2_read(reg)	__raw_readl(reg)
+
+#include "ak88_udc.h"
+/* anyka */
+#define T_VOID void
+#define T_U8	unsigned char
+#define T_U16	unsigned short
+#define T_U32	unsigned int
+#define ak_inl(reg)		__raw_readl(reg)
+#define ak_outl(reg_value, reg)	__raw_writel((reg_value), (reg))
+#define BUF2MEM                0
+#define MEM2BUF                1
+#define REG8(reg)	(*(volatile unsigned char *)(udc->baseaddr + reg))
+#define REG32(reg)	(*(volatile unsigned int *)(udc->baseaddr + reg))
+
+#ifdef UDC_L2_ENABLE
+static void usb_l2_init(int buf_id, int is_in)
+{
+}
+#else
+T_VOID L2_ClrComBufFlag(T_U8 buf_id)
+{
+    T_U32 reg_value;
+
+    if (buf_id<=7)
+    {
+        reg_value = ak_inl(L2_COMBUF_CFG);
+        reg_value |= 1<<(buf_id + 24);
+        ak_outl(reg_value, L2_COMBUF_CFG);
+    }
+    else
+    {
+        reg_value = ak_inl(L2_UARTBUF_CFG);
+        reg_value |= (1<<(buf_id + 16));
+        ak_outl(reg_value, L2_UARTBUF_CFG);
+    }
+}
+
+T_VOID L2_SetComBufFlag(T_U8 buf_id)
+{       
+    T_U32 reg_value;        
+
+    //select the buf and set the buf full
+    reg_value = ak_inl(L2_UARTBUF_CFG);
+    reg_value &= (~0xff);
+    reg_value |= ( buf_id | (1<<3) | (8<<4) );
+    ak_outl(reg_value, L2_UARTBUF_CFG);
+    
+    //printf("L2_BUF_STATE1 = %x\n", *(volatile unsigned int*)(L2_BUF_STATE) );
+    
+    //deselect the buf
+    reg_value = ak_inl(L2_UARTBUF_CFG);
+    reg_value &= (~0xff);
+    ak_outl(reg_value, L2_UARTBUF_CFG);
+
+    //printf("L2_BUF_STATE2 = %x\n", *(volatile unsigned int*)(L2_BUF_STATE) );
+}
+
+T_U8 L2_ComBufFlag(T_U8 buf_id)
+{
+    return (T_U8)((ak_inl(L2_STAT_REG1)>>(buf_id<<2))&0xf);
+}
+
+T_VOID L2_ComBufTranData(T_U32 ram_addr, T_U8 buf_id, T_U32 tran_byte, T_U8 tran_dir)
+{
+    T_U32 tran_nbr = tran_byte>>6;
+    T_U32 fraction_nbr = tran_byte%64;
+    T_U32 buf_addr;
+    T_U32 reg_value;
+    T_U32 reg_id;     
+    int timeout;
+
+
+    if (tran_dir == MEM2BUF)    //from SDRAM to L2
+    {
+		timeout = 5000;
+        while((L2_ComBufFlag(buf_id)==8) && timeout)
+		{ timeout--; }
+    }
+    
+    if (tran_nbr)
+    {
+		reg_value = ram_addr & 0xfffffff;    
+        reg_id = (T_U32)L2_DMA_ADDR + (buf_id<<2);    
+        ak_outl(reg_value, reg_id);
+
+        reg_value = tran_nbr & 0xff;    
+        reg_id = (T_U32)L2_DMA_CNT + (buf_id<<2);    
+        outw((T_U16)reg_value, reg_id);
+
+        reg_value = ak_inl(L2_COMBUF_CFG);
+		if (tran_dir)
+            reg_value |= (1<<(8+buf_id));
+		else
+	    	reg_value &= ~(1 << (8 + buf_id));
+        ak_outl(reg_value, L2_COMBUF_CFG);
+
+        reg_value = ak_inl(L2_DMA_REQ);
+		reg_value &= ~((1<<9)|(((T_U32)0xffff)<<16));        //clear other buf req
+        reg_value |= (1<< (24 + buf_id));
+        ak_outl(reg_value, L2_DMA_REQ);
+
+		timeout = 5000;
+		while(ak_inl(L2_DMA_REQ)&(1<<(24+buf_id)) && timeout)    //wait dma finish
+		{ timeout--; }
+    }
+    
+    if (fraction_nbr)
+    {
+        reg_value = ak_inl(L2_FRAC_ADDR);
+        reg_value &= ~0xfffffff;
+        reg_value |= ((ram_addr+(tran_nbr<<6))&0xfffffff);
+        ak_outl(reg_value, L2_FRAC_ADDR);
+        
+        buf_addr = ((buf_id&0x7 )<<3) | (tran_nbr&0x7);
+        reg_value = ak_inl(L2_DMA_REQ);
+        reg_value &= ~((0x7f<<1)|(0x3f<<10));
+        reg_value &= ~((1<<9)|(((T_U32)0xffff)<<16));        //clear other buf req    
+     
+        if (tran_dir)
+        {
+			if (fraction_nbr & 0x1)
+				reg_value |= (1<<9)|(1<<8)|(buf_addr<<1)|(fraction_nbr << 10);
+			else
+				reg_value |= (1<<9)|(1<<8)|(buf_addr<<1)|((fraction_nbr - 1)<< 10);
+        }
+		else {
+			reg_value &= ~(1 << 8);
+			reg_value |= (1<<9)|(buf_addr<<1)|((fraction_nbr-1)<< 10);    
+		}
+                    
+        ak_outl(reg_value, L2_DMA_REQ);
+
+		timeout = 5000;
+		while(ak_inl(L2_DMA_REQ)&(1<<9) && timeout)        //wait dma finish
+		{ timeout--; }
+    }
+}
+
+/* is_in:1 ==> ep2   
+ * is_in:0 ==> ep3
+ */
+static void usb_l2_init(int buf_id, int is_in)
+{
+	unsigned int regval;
+
+	regval = ak_inl(L2_DMA_REQ);
+	regval |= 0x1;
+	ak_outl(regval, L2_DMA_REQ);
+	regval = l2_read(L2_COMBUF_CFG);
+	regval |= ((1<<buf_id) | (1<<(16+buf_id)));
+	l2_write(L2_COMBUF_CFG, regval);
+
+	regval = l2_read(L2_ASSIGN_REG1);
+	if (is_in) {
+		regval &= ~(0x7<<0); /* ep2 */ 
+		l2_write(L2_ASSIGN_REG1, regval | (buf_id));
+	} else { 
+		regval &= ~(0x7<<3); /* ep3 */ 
+		l2_write(L2_ASSIGN_REG1, regval | (buf_id<<3));
+	}
+
+	regval = l2_read(L2_COMBUF_CFG);
+	l2_write(L2_COMBUF_CFG, regval | 0x1<<(buf_id+24));
+}
+
+static void usb_l2_ep2(int buf_id, unsigned int buf, dma_addr_t phys, unsigned int len, int is_in)
+{
+	L2_ClrComBufFlag(buf_id);
+
+	L2_ComBufTranData(phys, buf_id, len, is_in);
+
+	L2_SetComBufFlag(buf_id);
+}
+
+static void usb_l2_ep3(int buf_id, unsigned char *buf, dma_addr_t phys, unsigned int len, int is_in)
+{
+	L2_SetComBufFlag(buf_id);
+	
+	L2_ComBufTranData(phys, buf_id, len, is_in);
+}
+#endif
diff --git a/drivers/usb/gadget/ak88-udc/ak88_udc.c b/drivers/usb/gadget/ak88-udc/ak88_udc.c
new file mode 100644
index 00000000000..75a58a3bee7
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_udc.c
@@ -0,0 +1,1441 @@
+/*
+ * ak880x_udc -- driver for ak7801 USB peripheral controller
+ * Features
+ * The USB 2.0 HS OTG has following features:
+ *      •   compliant with USB Specification Version 2.0 (HS) and On-The-Go supplement to
+ *	  the USB 2.0 specification
+ *      •   operating as the host in point-to-point communications with another USB function
+ *	  or as a function controller for a USB peripheral
+ *      •   supporting UTMI+ Level 2 Transceiver Interface
+ *      •   4 Transmit/Receive endpoints in addition to Endpoint 0
+ *      •   3 DMA channels
+ *
+ * 09-11-14 10:45:03
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/workqueue.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/gpio.h>
+#include <asm/dma-mapping.h>
+
+#include "ak88_udc.h"
+
+#if 0
+#define dbg(fmt, arg...) printk("%s(%d): " fmt "\n", __func__, __LINE__, ##arg)
+#else
+#define dbg(fmt, arg...) {}
+#endif
+
+static const char ep0name[] = "ep0";
+static const char driver_name[] = "ak880x_udc";
+
+#define udc_readb(reg)	__raw_readb(udc->baseaddr + (reg))
+#define udc_readw(reg)	__raw_readw(udc->baseaddr + (reg))
+#define udc_readl(reg)	__raw_readl(udc->baseaddr + (reg))
+#define udc_writeb(reg, val) __raw_writeb(val, udc->baseaddr + (reg))
+#define udc_writew(reg, val) __raw_writew(val, udc->baseaddr + (reg))
+#define udc_writel(reg, val) __raw_writel(val, udc->baseaddr + (reg))
+
+extern struct mutex nand_lock;
+static struct ak880x_udc controller;
+/* static struct ak880x_udc *udc = &controller; */
+struct workqueue_struct *ep_wqueue;
+
+#include "ak88_l2.c"
+
+volatile int usb_detect;
+volatile int usb_exist;
+EXPORT_SYMBOL(usb_detect);
+EXPORT_SYMBOL(usb_exist);
+
+#if 1
+static void ep_irq_enable(struct ak880x_udc *udc)
+{
+	if (udc->ep[0].irq_enable) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<0));
+
+	if (udc->ep[1].irq_enable)
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<1));
+
+	if (udc->ep[2].irq_enable) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<2));
+	
+	if (udc->ep[3].irq_enable)
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<3));
+}
+
+static void ep_irq_disable(struct ak880x_udc *udc)
+{
+	udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<0));
+	udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<1));
+	udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<2));
+	udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<3));
+}
+#else
+#define	ep_irq_enable(udc)	local_irq_enable()
+#define	ep_irq_disable(udc)	local_irq_disable()
+#endif
+
+static inline void reset_usbcontroller()
+{
+	rCLK_CON |= (0x1<<21);
+	rCLK_CON &= ~(0x1<<21);
+}
+
+static inline void *l2_memcpy(void *dest, const void *src, size_t count)
+{
+	volatile unsigned int *tmp = dest;
+	const unsigned int *s = src;
+	
+#if 0
+	count = EP0_FIFO_SIZE;
+#else
+	count += 3;
+#endif
+	count = count / sizeof(int);
+	while (count--) 
+		*tmp++ = *s++;
+
+	return dest;
+}
+
+#define USB_ENABLE_DMA              (1)
+#define USB_DIRECTION_RX            (0<<1)
+#define USB_DIRECTION_TX            (1<<1)
+#define USB_DMA_MODE1               (1<<2)
+#define USB_DMA_MODE0               (0<<2)
+#define USB_DMA_INT_ENABLE          (1<<3)
+#define USB_DMA_INT_DISABLE         (0<<3)
+#define USB_DMA_BUS_ERROR           (1<<8)
+#define USB_DMA_BUS_MODE0           (0<<9)
+#define USB_DMA_BUS_MODE1           (1<<9)
+#define USB_DMA_BUS_MODE2           (2<<9)
+#define USB_DMA_BUS_MODE3           (3<<9)
+#define DMA_CHANNEL1_INT          	(1)
+#define USB_EP0_INDEX             	(0)
+#define USB_EP1_INDEX             	(1 << 0)
+#define USB_EP2_INDEX             	(1 << 1)
+#define USB_EP3_INDEX             	((1 << 1)|(1 << 0))
+#define USB_EP4_INDEX             	(1 << 2)
+#define USB_EP5_INDEX             	((1 << 2)|(1 << 0))
+#define USB_EP6_INDEX             	((1 << 2)|(1 << 1))
+#define USB_EP7_INDEX             	((1 << 2)|(1 << 1)|(1 << 0))
+#include "./ak88_usbudc.h"
+static void usb_dma_send_mode0(struct ak880x_udc *udc, T_U8 EP_index, T_U32 addr, T_U32 count)
+{
+	int timeout;
+    T_U32 usb_dma_int;
+    
+    REG8(USB_REG_INDEX) = EP_index;
+    
+    REG8(USB_REG_TXCSR2) =  USB_TXCSR_MODE1;
+    
+    REG32(USB_DMA_ADDR1) = addr;
+    REG32(USB_DMA_COUNT1) = count; 
+    //akprintf(C3, M_DRVSYS, "USB_DMA_COUNT_1 = %x\n", inl(USB_DMA_COUNT_1));
+    REG32(USB_DMA_CNTL_1) = (USB_ENABLE_DMA | USB_DIRECTION_TX
+					       | USB_DMA_INT_ENABLE | (USB_EP2_INDEX<<4) |
+						USB_DMA_BUS_MODE3);
+						
+    //akprintf(C3, M_DRVSYS, "USB_DMA_CNTL_1 = %x\n", inl(USB_DMA_CNTL_1));                                                                          
+    timeout = 5000;
+    while(1)
+    {
+		usb_dma_int = REG32(USB_DMA_INTR);
+		if(((usb_dma_int & DMA_CHANNEL1_INT)  == DMA_CHANNEL1_INT) && timeout)
+		{
+			timeout--;
+			break;
+		}
+	} 
+}
+
+static void done(struct ak880x_ep *ep, struct ak880x_request *req, int status)
+{
+	unsigned	 stopped = ep->stopped;
+	struct ak880x_udc *udc = ep->udc;
+
+	list_del_init(&req->queue);
+        /*
+	 * if (req->req.status == -EINPROGRESS)
+	 *         req->req.status = status;
+	 * else
+	 *         status = req->req.status;
+         */
+	req->req.status = status;
+	if (status && status != -ESHUTDOWN) {
+		dbg("%s done req(0x%p), status %d\n", ep->ep.name, req, status);
+	}
+
+	ep->stopped = 1;
+	req->req.complete(&ep->ep, &req->req);
+	/* ep->stopped = stopped; */
+	ep->stopped = 1;
+	dbg("%s done, req.status(%d)", ep->ep.name, req->req.status);
+	/* printk("I am done, req.status(%d)\n", req->req.status); */
+}
+
+static int write_ep0_fifo(struct ak880x_ep *ep, struct ak880x_request *req)
+{
+	int i;
+	unsigned total, count, is_last;
+	struct ak880x_udc *udc = ep->udc;
+
+	total = req->req.length - req->req.actual;
+
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count <= ep->ep.maxpacket) || !req->req.zero;
+	}
+
+	dbg("is_last(%d), count(%d), total(%d), actual(%d), length(%d)", 
+			is_last, count, total, req->req.actual, req->req.length);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	if (count == 0) {
+		dbg(" count == 0 ");
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+		done(ep, req, 0);
+		return 1;
+	}
+
+	udc_writel(USB_BUFFER_FORBIDDEN, udc_readl(USB_BUFFER_FORBIDDEN) | 0x1);
+	for (i = 0; i < count; i++) {
+		udc_writeb(USB_EP0_FIFO, 0);
+	}
+
+	l2_memcpy((void *)EP0_L2_ADDR, req->req.buf + req->req.actual, count);
+	udc_writel(USB_EP0_NUM, count&0x7f); /* 7bits */ 
+	udc_writel(USB_PREREAD_START, udc_readl(USB_PREREAD_START) | 0x1);
+	if (is_last) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+	} else {
+		udc_writeb(USB_CTRL_1, 0x1<<1);
+	}
+	udc_writel(USB_BUFFER_FORBIDDEN, udc_readl(USB_BUFFER_FORBIDDEN) & ~0x1);
+
+	req->req.actual += count;
+	if (is_last) 
+		done(ep, req, 0);
+
+	ep->done = is_last;
+	return is_last;
+	/* return 1; */
+}
+
+#if 0
+static int read_ep0_fifo(struct ak880x_ep *ep, struct ak880x_request *req)
+{
+	struct ak880x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr;
+	unsigned int count, bufferspace, is_done;
+
+	buf = req->req.buf + req->req.actual;
+	bufferspace = req->req.length - req->req.actual;
+	dbg("req.length(%d), req.actual(%d)", req->req.length, req->req.actual);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	csr = udc_readb(USB_CTRL_1);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting ep0-out data");
+		return 0;
+	}
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("rxcount(0) end");
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		return 0;
+	}
+	if (count > bufferspace) {
+		dbg("%s count(%d), bufferspace(%d), buffer overflow\n", 
+				 ep->ep.name, count, bufferspace);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	memcpy(buf, (void *)EP0_L2_ADDR, count);
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+	if (is_done) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6); /* clear rx flag */ 
+		done(ep, req, 0);
+	}
+	else
+		udc_writeb(USB_CTRL_1, 0x1<<6); /* clear rx flag */ 
+
+	return is_done;
+}
+#endif
+
+static int write_ep1_fifo(struct ak880x_ep *ep, struct ak880x_request *req)
+{
+	return 1;
+}
+
+static int write_ep2_fifo(struct ak880x_ep *ep, struct ak880x_request *req) /* ep2 */ 
+{
+	struct ak880x_udc *udc = ep->udc;
+	unsigned total, count, is_last;
+	unsigned char *buf;
+	dma_addr_t phys;
+
+	total = req->req.length - req->req.actual;
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count <= ep->ep.maxpacket) || !req->req.zero;
+	}
+	dbg("total(%d), count(%d), is_last(%d)", total, count, is_last);
+
+	if (count == 0) { /* not support command */ 
+		dbg("count == 0\n");
+		ep->done = 1;
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1, 0x1);
+		return 0;
+	}
+	udc_writeb(USB_EP_INDEX, 2);
+	udc_writel(USB_BUFFER_FORBIDDEN, udc_readl(USB_BUFFER_FORBIDDEN) | (0x1<<1));
+
+	while (udc_readw(USB_CTRL_1) & 0x1)
+		;
+	buf = req->req.buf + req->req.actual;
+	phys = ep->bufphys;
+	memcpy_toio((volatile void *)(ep->bufaddr), buf, count);
+#ifdef UDC_L2_ENABLE
+	ak88_l2_clr_status(udc->ep[2].l2_buf_id);
+	ak88_l2_combuf_dma(phys, udc->ep[2].l2_buf_id, count, MEM2BUF, false);
+	ak88_l2_combuf_wait_dma_finish(udc->ep[2].l2_buf_id);
+
+	ak88_l2_set_status(udc->ep[2].l2_buf_id, 8);
+#else
+	/* l2 xfer */
+	usb_l2_ep2(L2_USB_EP2, (unsigned int)ep->bufaddr, phys, count, ep->is_in);
+#endif
+
+	usb_dma_send_mode0(udc, 2, (unsigned int)buf, count);
+	
+	udc_writel(USB_EP2_NUM, count);
+	udc_writel(USB_PREREAD_START, udc_readl(USB_PREREAD_START) | (0x1<<1));
+	udc_writeb(USB_CTRL_1, 0x1);
+
+	udc_writel(USB_BUFFER_FORBIDDEN, udc_readl(USB_BUFFER_FORBIDDEN) & ~0x1);
+
+	req->req.actual += count;
+	/* wait a tx complete int */
+        /*
+	 * if (is_last)
+	 *         done(ep, req, 0);
+         */
+
+	/* return is_last; */
+	ep->done = is_last;
+
+#if 0
+	while (udc_readw(USB_CTRL_1) & 0x1)
+		;
+#endif
+	//printk("%x\n", udc_readw(USB_CTRL_1));
+	//udelay(300);
+
+	return 0;
+}
+
+static int read_ep3_fifo(struct ak880x_ep *ep, struct ak880x_request *req) /* ep3 */ 
+{
+	struct ak880x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr;
+	unsigned int count, bufferspace, is_done;
+	dma_addr_t phys;
+
+	bufferspace = req->req.length - req->req.actual;
+
+	udc_writeb(USB_EP_INDEX, 2);
+	while (udc_readw(USB_CTRL_1) & 0x1)
+		;
+	udc_writeb(USB_EP_INDEX, 3);
+	csr = udc_readb(USB_CTRL_2);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting bulkout data");
+		return 0;
+	}
+
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)",
+				csr, count, bufferspace);
+		dbg("what happened??");
+		goto stall;
+	} else if (count > ep->ep.maxpacket)
+		count = ep->ep.maxpacket;
+
+	if (count > bufferspace) {
+		dbg("%s buffer overflow\n", ep->ep.name);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)", csr, count, bufferspace);
+
+	buf = req->req.buf + req->req.actual;
+	phys = ep->bufphys;
+
+#ifdef UDC_L2_ENABLE
+	ak88_l2_set_status(udc->ep[3].l2_buf_id, 8);
+
+	ak88_l2_combuf_dma(phys, udc->ep[3].l2_buf_id, count, BUF2MEM, false);
+	ak88_l2_combuf_wait_dma_finish(udc->ep[3].l2_buf_id);
+#else
+	/* l2 xfer */
+	usb_l2_ep3(L2_USB_EP3, buf, phys, count, 0);
+#endif
+
+	memcpy_fromio(buf, (volatile void *)(ep->bufaddr), count);
+	
+stall:
+	udc_writeb(USB_CTRL_2, csr & ~0x1);
+	/* udc_writeb(USB_EP_INDEX, 3); */
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+
+	ep->done = is_done;
+	if (is_done) {
+		done(ep, req, 0);
+	}
+
+
+	return is_done;
+}
+
+static int ak880x_get_frame(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+static int ak880x_wakeup(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+
+static int ak880x_pullup(struct usb_gadget *gadget, int is_on)
+{
+	dbg("is_on(%d)", is_on);
+
+	return 0;
+}
+static int ak880x_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	dbg("");
+	return 0;
+}
+static int ak880x_set_selfpowered(struct usb_gadget *gadget, int is_on)
+{
+	dbg("");
+	return 0;
+}
+static const struct usb_gadget_ops ak880x_udc_ops = {
+	.get_frame		= ak880x_get_frame,
+	.wakeup			= ak880x_wakeup,
+	.set_selfpowered	= ak880x_set_selfpowered,
+	.vbus_session		= ak880x_vbus_session,
+	.pullup			= ak880x_pullup,
+};
+
+static void ep2_work(struct work_struct *work)
+{
+	struct ak880x_request *req = NULL;
+	struct ak880x_udc *udc = &controller;
+	struct ak880x_ep *ep = &udc->ep[2];
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak880x_request, queue);
+
+	mutex_lock(&nand_lock);
+	if (req)
+		req->status = write_ep2_fifo(ep, req);
+	else
+		dbg("something happend");
+	mutex_unlock(&nand_lock);
+}
+
+static void ep3_work(struct work_struct *work)
+{
+	struct ak880x_request *req = NULL;
+	struct ak880x_udc *udc = &controller;
+	struct ak880x_ep *ep = &udc->ep[3];
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak880x_request, queue);
+
+	mutex_lock(&nand_lock);
+	if (req)
+		req->status = read_ep3_fifo(ep, req);
+	else
+		dbg("something happend");
+	mutex_unlock(&nand_lock);
+}
+
+static int ak880x_ep_enable(struct usb_ep *_ep,
+				const struct usb_endpoint_descriptor *desc)
+{
+	struct ak880x_ep *ep = container_of(_ep, struct ak880x_ep, ep);
+	struct ak880x_udc *udc = ep->udc;
+	int tmp, maxpacket;
+
+	if (!_ep || !ep
+			|| !desc || ep->desc
+			|| _ep->name == ep0name
+			|| desc->bDescriptorType != USB_DT_ENDPOINT
+			|| (maxpacket = le16_to_cpu(desc->wMaxPacketSize)) == 0
+			|| maxpacket > ep->maxpacket) {
+		dbg("bad ep or descriptor");
+		dbg("%p, %p, %p, %p", _ep, ep, desc, ep->desc);
+		return -EINVAL;
+	}
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		dbg("bogus udcice state\n");
+		return -ESHUTDOWN;
+	}
+
+	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	switch (tmp) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		dbg("only one control endpoint\n");
+		return -EINVAL;
+	case USB_ENDPOINT_XFER_INT:
+		if (maxpacket > EP1_FIFO_SIZE)
+			dbg("maxpacket too large");
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		switch (maxpacket) {
+		case 8:
+		case 16:
+		case 32:
+		case 64:
+		case 512: /* for usb20 */ 
+			break;
+		default:
+			dbg("bogus maxpacket %d\n", maxpacket);
+			return -EINVAL;
+		}
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		dbg("USB_ENDPOINT_XFER_ISOC");
+		break;
+	}
+	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
+	/* ep->stopped = 0; */
+	ep->stopped = 1;
+	ep->desc = (struct usb_endpoint_descriptor *)desc;
+
+	dbg("%s, maxpacket(%d), desc->bEndpointAddress (0x%x) is_in(%d)",
+		       	_ep->name, maxpacket, desc->bEndpointAddress, ep->is_in);
+	
+	ep_irq_disable(udc);
+	if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 -- int */ 
+		dbg("");
+		udc_writeb(USB_EP_INDEX, 1);
+		udc_writeb(USB_CTRL_1+1, 0);
+		udc_writew(USB_RX_MAX, 64);
+	} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 -- tx */ 
+		dbg("");
+		INIT_WORK(&ep->work, ep2_work);
+		usb_l2_init(L2_USB_EP2, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1+1, 1<<5);
+		udc_writew(USB_TX_MAX, 512);
+	} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 -- rx */ 
+		dbg("");
+		INIT_WORK(&ep->work, ep3_work);
+		usb_l2_init(L2_USB_EP3, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 3);
+		udc_writeb(USB_CTRL_1+1, 0);
+		udc_writew(USB_RX_MAX, 512);
+		udc_writeb(USB_CTRL_2, udc_readb(USB_CTRL_2) & ~(0x1));
+	} else {
+		printk("Invalid ep");
+		return -EINVAL;
+	}
+
+	ep->irq_enable = 1;
+
+	ep_irq_enable(udc);
+
+	return 0;
+}
+
+static int ak880x_ep_disable (struct usb_ep * _ep)
+{
+	struct ak880x_ep *ep = container_of(_ep, struct ak880x_ep, ep);
+	struct ak880x_udc *udc = ep->udc;
+	struct ak880x_request *req;
+
+	if (ep == &ep->udc->ep[0]) /* ep0 */ 
+		return -EINVAL;
+
+	dbg("%s", _ep->name);
+	ep_irq_disable(udc);
+
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct ak880x_request, queue);
+		done(ep, req, -ESHUTDOWN);
+	}
+
+	ep->irq_enable = 0;
+	ep->stopped = 1;
+	ep->desc = NULL;
+	ep_irq_enable(udc);
+	return 0;
+}
+
+static struct usb_request *
+	ak880x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+	struct ak880x_request *req;
+
+	dbg("%s", _ep->name);
+	req = kzalloc(sizeof (struct ak880x_request), gfp_flags);
+	if (!req)
+		return NULL;
+
+	INIT_LIST_HEAD(&req->queue);
+	return &req->req;
+}
+
+static void ak880x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak880x_request *req;
+
+	dbg("%s", _ep->name);
+	req = container_of(_req, struct ak880x_request, req);
+	WARN_ON(!list_empty(&req->queue));
+	kfree(req);
+}
+
+static int ak880x_ep_queue(struct usb_ep *_ep,
+			struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct ak880x_request	*req;
+	struct ak880x_ep	*ep;
+	struct ak880x_udc	*udc;
+	int			status;
+
+	req = container_of(_req, struct ak880x_request, req);
+	ep = container_of(_ep, struct ak880x_ep, ep);
+
+	if (!_req || !_req->complete
+			|| !_req->buf || !list_empty(&req->queue)) {
+		/* dbg("%s invalid request", _ep->name); */
+		printk("%s invalid request\n", _ep->name);
+		return -EINVAL;
+	}
+
+        /*
+	 * if (!_ep || (!ep->desc)) {
+	 *         dbg("invalid ep\n");
+	 *         return -EINVAL;
+	 * }
+         */
+
+	udc = ep->udc;
+
+	if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		/* dbg("invalid device\n"); */
+		printk("invalid device\n");
+		return -EINVAL;
+	}
+
+	_req->status = -EINPROGRESS;
+	_req->actual = 0;
+
+	ep_irq_disable(udc);
+
+	ep->stopped = 0;
+	dbg("%s queue is_in(%d)", ep->ep.name, ep->is_in);
+	if (list_empty(&ep->queue) && !ep->stopped) {
+		if (ep->ep.name == ep0name) {
+			if (ep->is_in) {
+				dbg("ep0 req(0x%p)", req);
+				list_add_tail(&req->queue, &ep->queue);
+				status = write_ep0_fifo(ep, req);
+			} else {
+#if 1
+				dbg("why?");
+                                /*
+				 * udc_writeb(USB_EP_INDEX, 0);
+				 * udc_writeb(USB_CTRL_1, 0x1<<6); [> To clear the RxPktRdy Bit <] 
+				 * udc_writeb(USB_CTRL_1, 0x1<<3); [> data end <]
+                                 */
+				ep->stopped = 1;
+				status = 1;
+#else
+				status = read_ep0_fifo(ep, req); /* ??? */
+#endif
+			}
+		} else {
+			list_add_tail(&req->queue, &ep->queue);
+			if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 */ 
+				dbg("ep1");
+				status = write_ep1_fifo(ep, req);
+			} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 */ 
+				queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 */ 
+				queue_work(ep_wqueue, &ep->work);
+			} else {
+				printk("Invalid ep");
+				status = -EINVAL;
+				goto stall;
+			}
+		}
+	} else {
+		status = 0;
+		list_add_tail(&req->queue, &ep->queue);
+		dbg("waiting for %s int", ep->ep.name);
+	}
+
+stall:
+
+	ep_irq_enable(udc);
+	/* return (status < 0) ? status : 0; */
+	return 0;
+}
+
+
+static int ak880x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak880x_ep	*ep;
+	struct ak880x_request	*req;
+
+	dbg("dequeue");
+
+	ep = container_of(_ep, struct ak880x_ep, ep);
+	if (!_ep || ep->ep.name == ep0name)
+		return -EINVAL;
+
+	list_for_each_entry (req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req)
+		return -EINVAL;
+
+	done(ep, req, -ECONNRESET);
+	return 0;
+}
+
+static int ak880x_ep_set_halt(struct usb_ep *_ep, int value)
+{
+	struct ak880x_ep	*ep = container_of(_ep, struct ak880x_ep, ep);
+	struct ak880x_udc	*udc = ep->udc;
+	u32 __iomem	*creg;
+	u32		csr;
+	int		status = 0;
+
+	dbg("");
+	/* something have to do */
+	/* ep->stopped = value ? 1 : 0; */
+
+	return 0;
+}
+
+static const struct usb_ep_ops ak880x_ep_ops = {
+	.enable		= ak880x_ep_enable,
+	.disable	= ak880x_ep_disable,
+	.alloc_request	= ak880x_ep_alloc_request,
+	.free_request	= ak880x_ep_free_request,
+	.queue		= ak880x_ep_queue,
+	.dequeue	= ak880x_ep_dequeue,
+	.set_halt	= ak880x_ep_set_halt,
+	// there's only imprecise fifo status reporting
+};
+
+static struct ak880x_udc controller = {
+	.gadget = {
+		.ops	= &ak880x_udc_ops,
+		.ep0	= &controller.ep[0].ep,
+		.name	= driver_name,
+		.dev	= {
+		       .init_name = "gadget",
+		}
+	},
+	.ep[0] = {
+		.ep = {
+			.name		= ep0name,//ep_name[0],
+			.ops		= &ak880x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP0_FIFO_SIZE,
+	},
+	.ep[1] = {
+		.ep = {
+			.name	= "ep1-int",//ep_name[1],
+			.ops	= &ak880x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP1_FIFO_SIZE,
+	},
+	.ep[2] = {
+		.ep = {
+			.name	= "ep2in-bulk",//ep_name[2],
+			.ops	= &ak880x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP2_FIFO_SIZE,
+	},
+	.ep[3] = {
+		.ep = {
+			/* could actually do bulk too */
+			.name	= "ep3out-bulk",//ep_name[3],
+			.ops	= &ak880x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP3_FIFO_SIZE,
+	},
+	.ep[4] = {
+		.ep = {
+			.name	= "ep4-iso",//ep_name[4],
+			.ops	= &ak880x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP4_FIFO_SIZE,
+	},
+};
+
+static void handle_setup(struct ak880x_udc *udc, struct ak880x_ep *ep)
+{
+	unsigned rxcount;
+	struct usb_ctrlrequest creq;
+	int status = 0;
+	int timeout;
+
+#if 0
+	int regval, csr;
+	struct ak880x_ep *ep0 = &udc->ep[0];
+	struct ak880x_request *req;
+
+	if (!list_empty(&ep0->queue)) {
+		req = list_entry(ep0->queue.next, struct ak880x_request, queue);
+		dbg("ep0 req waiting");
+	} else {
+		req = NULL;
+	}
+#endif
+
+	rxcount = udc_readw(USB_EP_COUNT);
+	if (rxcount == 0) {
+		dbg("rxcount(0) end");
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		return;
+	}
+	memcpy(&creq, (void *)EP0_L2_ADDR, sizeof(creq));
+	udc_writeb(USB_CTRL_1, 0x1<<6); /* clear rx flag */ 
+	dbg("rxcount(%d), brequesttype(0x%x), brequest(0x%x)",
+			rxcount, creq.bRequestType, creq.bRequest);
+
+	(creq.bRequestType & USB_DIR_IN) ? (ep->is_in = 1) : (ep->is_in = 0);
+
+	switch (creq.bRequest) {
+		case USB_REQ_SET_ADDRESS:
+			/* udc->addr = 0; */
+			dbg("USB_REQ_SET_ADDRESS(%d)", creq.wValue);
+			/* udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3); */
+			udc_writeb(USB_CTRL_1, 0x1<<3);
+			timeout = 5000;
+			 /* waiting for next interrupt */ 
+			while (!(udc_readb(USB_INTERRUPT_1) & 0x1) && timeout) {timeout--;}
+			udc_writeb(USB_FUNCTION_ADDR, creq.wValue);
+			udc->addr = creq.wValue;
+			break;
+		default:
+			if (udc->driver)  
+				status = udc->driver->setup(&udc->gadget, &creq);
+			 else 
+				status = -ENODEV;
+	}
+	if (status < 0) {
+		dbg("stall, status(%d)", status);
+		if (status = -EOPNOTSUPP) {
+			dbg("What will happened");
+			/* udc_writeb(USB_CTRL_1,  0x1<<3); */
+		}
+                /*
+		 * udc_writew(USB_CTRL_1,  0x1<<8); [> flush fifo <]
+		 * udc_writeb(USB_CTRL_1,  0x1<<5); [> stall <]
+                 */
+	} else if (status == (999 + 256)) { /* delayed status ???*/
+		dbg("delayed, status(%d)", status);
+                /*
+		 * udc_writeb(USB_CTRL_1,  0x1<<8); [> flush fifo <]
+		 * udc_writeb(USB_CTRL_1,  0x1<<5); [> stall <]
+                 */
+
+		/* udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3); */
+	}
+
+}
+
+static void handle_ep0(struct ak880x_udc *udc)
+{
+	int csr;
+	struct ak880x_ep *ep0 = &udc->ep[0];
+	struct ak880x_request *req = NULL;
+	if (!list_empty(&ep0->queue)) 
+		req = list_entry(ep0->queue.next, struct ak880x_request, queue);
+#if 0
+	struct ak880x_request *req;
+
+	if (!list_empty(&ep0->queue)) {
+		req = list_entry(ep0->queue.next, struct ak880x_request, queue);
+		dbg("ep0 req waiting");
+	} else {
+		req = NULL;
+	}
+#endif
+
+	udc_writeb(USB_EP_INDEX, 0);
+	csr = udc_readb(USB_CTRL_1);
+	dbg("csr(0x%x)", csr);
+	if (csr == 0) { /* tx int */ 
+		dbg(" This is a tx interrupt");
+		if (!ep0->done && req) {
+			dbg("linux ep0 overrun??");
+			dbg("ep0 req(0x%p)", req);
+			write_ep0_fifo(ep0, req); /* usb20 for linux */ 
+		}
+		return;
+	}
+
+	if (csr & 0x1<<3) {
+		dbg("data end");
+	} 
+	if (csr & 0x1<<4) {
+		dbg("A control transaction ends before the DataEnd bit has been set");
+		udc_writeb(USB_CTRL_1, 0x1<<7);
+		/* do something else? */
+	}
+	if (csr & 0x1<<0) {
+		dbg("A data packet has been received");
+                /*
+		 * if (req) 
+		 *         read_ep0_fifo(ep0, req);
+		 * else
+                 */
+		handle_setup(udc, ep0);
+	} else if (~csr & 0x1<<1) {
+		dbg("The CPU has not loaded a data packet into the FIFO");
+	} else {
+		dbg("what is it?");
+	}
+
+        /*
+	 * if (csr & 0x1<<2) {
+	 *         dbg("A STALL handshake has been transmitted");
+	 *         udc_writeb(USB_CTRL_1, 0);
+	 * }
+         */
+}
+
+/* not ep0 */
+static void handle_ep(struct ak880x_ep *ep)
+{
+	struct ak880x_request *req;
+	struct ak880x_udc *udc = ep->udc;
+	unsigned int csr;
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next,
+			struct ak880x_request, queue);
+	else {
+		dbg("%s: no req waiting", ep->ep.name);
+		req = NULL;
+	}
+	
+	if (!strcmp(ep->ep.name, udc->ep[1].ep.name)) { /* ep1 */ 
+		dbg("ep1");
+	} else if (ep->is_in) { /* ep2 */ 
+
+		udc_writeb(USB_EP_INDEX, 2);
+		csr = udc_readb(USB_CTRL_1);
+		dbg("ep2 csr(0x%x), req(0x%p)", csr, req);
+
+                /*
+		 * if ((csr & 0x1) && req) {
+		 *         write_ep2_fifo(ep, req);
+		 * }
+                 */
+		/* udc_writeb(USB_CTRL_1, 0x1); */
+		if (csr & 0x1<<2) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<2));
+		}
+		if (csr & 0x1<<5) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<5));
+		}
+
+		if (req) {
+			if (ep->done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					req = list_entry(ep->queue.next, struct ak880x_request, queue);
+					queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				queue_work(ep_wqueue, &ep->work);
+			}
+
+		}
+	} else { /* ep3 */ 
+		udc_writeb(USB_EP_INDEX, 3);
+		csr = udc_readb(USB_CTRL_2);
+		dbg("ep3 csr(0x%x)", csr);
+
+		udc_writeb(USB_EP_INDEX, 3);
+		if (req && (csr & 0x1<<1))
+		{
+			//printk("sb1 %d\n", udc_readw(USB_EP_COUNT));
+			queue_work(ep_wqueue, &ep->work);
+		}
+		//else if ((csr & 0x2) == 0)
+			//printk("sb2 %d\n", udc_readw(USB_EP_COUNT));
+	}
+}
+
+static void udc_disconnect(struct ak880x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i;
+
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak880x_ep *ep = &udc->ep[i];
+		struct ak880x_request *req;
+
+		ep->stopped = 1;
+
+		// terminer chaque requete dans la queue
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak880x_request, queue);
+			done(ep, req, -ESHUTDOWN);
+		}
+	}
+
+	if (driver)
+		driver->disconnect(&udc->gadget);
+
+	udc_reinit(udc);
+}
+
+static void udc_reset(struct ak880x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i;
+
+#ifdef USB_11
+	udc_writel(USB_MODE_STATUS, 1);
+	udc_writew(USB_POWER_CTRL, 0);
+#else
+	udc_writel(USB_MODE_STATUS, 0);
+	udc_writew(USB_POWER_CTRL, 0x1<<5);
+#endif
+
+	udc_writeb(USB_FUNCTION_ADDR, 0);
+	udc_writeb(USB_INTERRUPT_USB, ~(0x1<<3));
+	udc_writeb(USB_INTERRUPT_TX, 0x1<<0); /* ep0 */ 
+	udc->ep[0].irq_enable = 1;
+	
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak880x_ep *ep = &udc->ep[i];
+		struct ak880x_request *req;
+
+		ep->stopped = 1;
+
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak880x_request, queue);
+			done(ep, req, -ECONNRESET);
+		}
+	}
+
+}
+
+static irqreturn_t udc_irqhandler(int irq, void *_udc)
+{
+	struct ak880x_udc *udc = _udc;
+	short status_1, status_2;
+	char status_int;
+
+	status_int = udc_readb(USB_INTERRUPT_COMM);
+	if (status_int & 0x1<<2) {
+		/* dbg("status_int(0x%x), reset", status_int);	 */
+		printk("\n\nstatus_int(0x%x), reset\n\n", status_int);	
+		if (usb_detect) {
+			usb_exist = 1;
+			usb_detect = 0;
+			if (!udc->driver) {
+				udc_enable(udc, 0);
+				return IRQ_HANDLED;
+			}
+		}
+#ifdef USB_11
+		udc->gadget.speed = USB_SPEED_FULL;
+#else
+		udc->gadget.speed = USB_SPEED_HIGH;
+#endif
+		udc_reset(udc);
+		goto done;
+	} else if(status_int & 0x1<<1) { /* resume */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("resume");
+		goto done;
+	} else if(status_int & 0x1<<0) { /* suspend */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("suspend");
+		udc_disconnect(udc);
+		goto done;
+	}
+
+	status_1 = udc_readb(USB_INTERRUPT_1);
+	status_2 = udc_readb(USB_INTERRUPT_2);
+	dbg("status_int(0x%x), status_1(0x%x), status_2(0x%x)", status_int, status_1, status_2);
+	if (status_1 & 0x1<<0) {
+		handle_ep0(udc);
+	}
+	if (status_1 & 0x1<<2) {
+		dbg("endpoint2");
+		handle_ep(&udc->ep[2]);
+	}
+	if (status_1 & 0x1<<4) {
+		dbg("endpoint4");
+		handle_ep(&udc->ep[4]);
+	}
+
+	if (status_2 & 0x1<<1) {
+		dbg("endpoint 1");
+		handle_ep(&udc->ep[1]);
+	}
+	if (status_2 & 0x1<<3) {
+		dbg("endpoint3");
+		handle_ep(&udc->ep[3]);
+	}
+done:
+	return IRQ_HANDLED;
+}
+
+void udc_enable(struct ak880x_udc *udc, int enable)
+{
+	if (enable) {
+		reset_usbcontroller();
+		clk_enable(udc->clk);
+		rMULFUN_CON &= ~0x7;
+		rMULFUN_CON |= 6;
+#ifdef USB_11
+		udc_writel(USB_MODE_STATUS, 1);
+		udc_writew(USB_POWER_CTRL, 0);
+#else
+		udc_writel(USB_MODE_STATUS, 0);
+		udc_writew(USB_POWER_CTRL, 0x1<<5);
+#endif
+	} else {
+		rMULFUN_CON &= ~0x7;
+		clk_disable(udc->clk);
+		reset_usbcontroller();
+	}
+}
+
+int usb_gadget_register_driver (struct usb_gadget_driver *driver)
+{
+	struct ak880x_udc	*udc = &controller;
+	int		retval;
+
+	if (!driver
+			|| driver->speed < USB_SPEED_FULL
+			|| !driver->bind
+			|| !driver->setup) {
+		dbg("bad parameter.\n");
+		return -EINVAL;
+	}
+
+	if (udc->driver) {
+		dbg("UDC already has a gadget driver\n");
+		return -EBUSY;
+	}
+
+	udc->driver = driver;
+	udc->gadget.dev.driver = &driver->driver;
+	//udc->gadget.dev.driver_data = &driver->driver;
+	udc->enabled = 1;
+
+	retval = driver->bind(&udc->gadget);
+	if (retval) {
+		dbg("driver->bind() returned %d\n", retval);
+		udc->driver = NULL;
+		udc->gadget.dev.driver = NULL;
+		//udc->gadget.dev.driver_data = NULL;
+		udc->enabled = 0;
+		return retval;
+	}
+
+	local_irq_disable();
+	udc_enable(udc, 1);
+	local_irq_enable();
+
+	dbg("bound to %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
+{
+	struct ak880x_udc *udc = &controller;
+
+	if (!driver || driver != udc->driver || !driver->unbind)
+		return -EINVAL;
+
+	local_irq_disable();
+	udc_enable(udc, 0);
+	local_irq_enable();
+
+	driver->unbind(&udc->gadget);
+	udc->gadget.dev.driver = NULL;
+	//udc->gadget.dev.driver_data = NULL;
+	udc->driver = NULL;
+
+
+	dbg("unbound from %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL (usb_gadget_unregister_driver);
+
+
+static void udc_reinit(struct ak880x_udc *udc)
+{
+	u32 i;
+
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+	INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak880x_ep *ep = &udc->ep[i];
+
+		if (i != 0)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+		ep->desc = NULL;
+		/* ep->stopped = 0; */
+		ep->stopped = 1;
+		ep->ep.maxpacket = ep->maxpacket;
+		// initialiser une queue par endpoint
+		INIT_LIST_HEAD(&ep->queue);
+	}
+}
+
+static int __init ak880x_udc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ak880x_udc *udc = &controller;
+	struct resource	*res;
+	int retval;
+
+	if (pdev->num_resources < 2) {
+		dbg("invalid num_resources\n");
+		return -ENODEV;
+	}
+	if ((pdev->resource[0].flags != IORESOURCE_MEM)
+			|| (pdev->resource[1].flags != IORESOURCE_IRQ)) {
+		dbg("invalid resource type\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	if (!request_mem_region(res->start,
+			res->end - res->start + 1,
+			driver_name)) {
+		dbg("someone's using UDC memory\n");
+		return -EBUSY;
+	}
+
+	udc->baseaddr = ioremap_nocache(res->start, res->end - res->start + 1);
+	if (!udc->baseaddr) {
+		retval = -ENOMEM;
+		goto fail0a;
+	}
+	/* init software state */
+	udc->gadget.dev.parent = dev;
+	udc->enabled = 0;
+
+	udc_reinit(udc);
+
+	/* get interface and function clocks */
+	udc->clk = clk_get(dev, "udc_clk");
+	if (IS_ERR(udc->clk)) {
+		dbg("clocks missing\n");
+		retval = -ENODEV;
+		/* NOTE: we "know" here that refcounts on these are NOPs */
+		goto fail0b;
+	}
+
+	retval = device_register(&udc->gadget.dev);
+	if (retval < 0)
+		goto fail0b;
+
+	ep_wqueue = create_workqueue("ak880x_udc");
+	/* request UDC and maybe VBUS irqs */
+	udc->mcu_irq = platform_get_irq(pdev, 0);
+
+	reset_usbcontroller();
+	retval = request_irq(udc->mcu_irq, udc_irqhandler,
+			IRQF_DISABLED, driver_name, udc);
+	if (retval < 0) {
+		dbg("request irq %d failed\n", udc->mcu_irq);
+		goto fail1;
+	}
+	platform_set_drvdata(pdev, udc);
+
+	dbg("Build at %s %s", __DATE__, __TIME__);
+
+	/* for g_serial.ko */
+	udc->ep[2].bufaddr = dma_alloc_coherent(NULL, 512, &udc->ep[2].bufphys, DMA_TO_DEVICE);
+	udc->ep[3].bufaddr = dma_alloc_coherent(NULL, 512, &udc->ep[3].bufphys, DMA_FROM_DEVICE);
+
+#ifdef UDC_L2_ENABLE
+		/* USB slave L2 buffer initialization */
+		udc->ep[2].l2_buf_id = ak88_l2_alloc(ADDR_USB_BULKOUT);
+		udc->ep[3].l2_buf_id = ak88_l2_alloc(ADDR_USB_BULKIN);
+#endif
+
+	return 0;
+
+	free_irq(udc->mcu_irq, udc);
+fail1:
+	device_unregister(&udc->gadget.dev);
+fail0b:
+	iounmap(udc->baseaddr);
+fail0a:
+	release_mem_region(res->start, res->end - res->start + 1);
+	dbg("%s probe failed, %d\n", driver_name, retval);
+	return retval;
+}
+
+static int __exit ak880x_udc_remove(struct platform_device *pdev)
+{
+	struct ak880x_udc *udc = platform_get_drvdata(pdev);
+	struct resource *res;
+
+	if (udc->driver)
+		return -EBUSY;
+
+	free_irq(udc->mcu_irq, udc);
+	device_unregister(&udc->gadget.dev);
+
+	destroy_workqueue(ep_wqueue);
+
+	iounmap(udc->baseaddr);
+
+#ifdef UDC_L2_ENABLE
+		/* USB slave L2 buffer initialization */
+	ak88_l2_free(ADDR_USB_BULKIN);
+	ak88_l2_free(ADDR_USB_BULKOUT);
+#endif
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res->end - res->start + 1);
+
+	return 0;
+}
+
+static void ak880x_udc_shutdown(struct platform_device *dev)
+{
+}
+
+#ifdef CONFIG_PM
+static int ak880x_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	struct ak880x_udc *udc = platform_get_drvdata(pdev);
+
+	return 0;
+}
+
+static int ak880x_udc_resume(struct platform_device *pdev)
+{
+	struct ak880x_udc *udc = platform_get_drvdata(pdev);
+
+	/* something to do */
+
+	return 0;
+}
+#else
+#define	ak880x_udc_suspend	NULL
+#define	ak880x_udc_resume	NULL
+#endif
+
+static struct platform_driver ak880x_udc_driver = {
+	.remove		= __exit_p(ak880x_udc_remove),
+	.shutdown	= ak880x_udc_shutdown,
+	.suspend	= ak880x_udc_suspend,
+	.resume		= ak880x_udc_resume,
+	.driver		= {
+		.name	= (char *) driver_name,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init udc_init_module(void)
+{
+	printk("AK880X UDC Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_probe(&ak880x_udc_driver, ak880x_udc_probe);
+}
+module_init(udc_init_module);
+
+static void __exit udc_exit_module(void)
+{
+	platform_driver_unregister(&ak880x_udc_driver);
+}
+module_exit(udc_exit_module);
+
+MODULE_DESCRIPTION("AK880X udc driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak880x_udc");
diff --git a/drivers/usb/gadget/ak88-udc/ak88_udc.h b/drivers/usb/gadget/ak88-udc/ak88_udc.h
new file mode 100644
index 00000000000..f4c2112292d
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_udc.h
@@ -0,0 +1,133 @@
+#ifndef _AK88_UDC_H
+#define _AK88_UDC_H
+
+/* ak880x usb register */
+#define USB_FUNCTION_ADDR	0x0
+#define USB_POWER_CTRL		0x1
+#define USB_INTERRUPT_1		0x2
+#define USB_INTERRUPT_2		0x4
+#define USB_INTERRUPT_TX	0x6
+#define USB_INTERRUPT_RX	0x8
+#define USB_INTERRUPT_COMM	0xA
+#define USB_INTERRUPT_USB	0xB
+#define USB_FRAME_NUM		0xC
+#define USB_EP_INDEX		0xE
+#define USB_TEST_MODE		0xF
+#define USB_TX_MAX		0x10
+#define USB_CTRL_1		0x12
+#define USB_RX_MAX		0x14
+#define USB_CTRL_2		0x16
+#define USB_EP_COUNT		0x18
+#define USB_CFG_INFO		0x1F
+#define USB_EP0_FIFO		0x20
+#define USB_EP1_FIFO		0x24
+#define USB_EP2_FIFO		0x28
+#define USB_EP3_FIFO		0x2C
+#define USB_EP4_FIFO		0x30
+#define USB_DEVICE_CTRL		0x60
+#define USB_DMA_INTR		0x200
+#define USB_DMA_CTRL1		0x204
+#define USB_DMA_CTRL2		0x214
+#define USB_DMA_CTRL3		0x224
+#define USB_DMA_ADDR1		0x208
+#define USB_DMA_ADDR2		0x218
+#define USB_DMA_ADDR3		0x228
+#define USB_DMA_COUNT1		0x20C
+#define USB_DMA_COUNT2		0x21C
+#define USB_DMA_COUNT3		0x22C
+#define USB_EP0_NUM		0x330
+#define USB_EP2_NUM		0x334
+#define USB_BUFFER_FORBIDDEN	0x338
+#define USB_PREREAD_START	0x33C
+#define USB_ADDR_CHANGE		0x340
+#define USB_MODE_STATUS		0x344
+
+
+// #define USB_11 [> usb1.1 <]   
+
+#define EP0_FIFO_SIZE		64  /* control, not 64byte? */ 
+#define EP1_FIFO_SIZE		64 /* interrupt */ 
+#define EP4_FIFO_SIZE		512 /* iso */ 
+#ifdef USB_11 /* USB_SPEED_FULL */ 
+#define EP2_FIFO_SIZE		64 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		64 /* ep2 out bulk */ 
+#else /* USB_SPEED_HIGH */ 
+#define EP2_FIFO_SIZE		512 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		512 /* ep2 out bulk */ 
+#endif
+
+
+#define EP0_L2_ADDR		(AK88_VA_L2MEM + 0x1500) /* L2 buffer17 for otg control transfer */
+
+struct ak880x_request;
+
+struct ak880x_ep {
+	struct usb_ep		ep;
+	struct usb_gadget	*gadget;
+	struct usb_endpoint_descriptor *desc;
+
+	struct list_head	queue;
+
+	struct work_struct	work;
+	struct ak880x_request	*req; /* req be about to handle */ 
+
+	struct ak880x_udc	*udc;
+	int			maxpacket;
+	volatile int		done;
+	unsigned int		bufaddr;
+	dma_addr_t		bufphys;
+
+	unsigned		irq_enable;
+	volatile unsigned	stopped;
+	// unsigned		stopped:1;
+	unsigned		is_in:1;
+	unsigned		is_iso:1;
+	// unsigned		fifo_bank:1;
+	u8			l2_buf_id;
+};
+
+struct ak880x_request {
+	struct list_head	queue;		/* ep's requests */
+	struct usb_request	req;
+	int			status;
+};
+
+enum ep0_status {
+        EP0_IDLE,
+        EP0_IN_DATA_PHASE,
+        EP0_OUT_DATA_PHASE,
+        EP0_END_XFER,
+        EP0_STALL,
+};
+
+struct usb_l2 {
+	void *buf;
+	dma_addr_t phys;
+};
+
+static const char * const ep_name[] = {
+	"ep0", "ep1-int", "ep2in-bulk", "ep3out-bulk", "ep4-iso",
+};
+
+#define ENDPOINTS_NUM ARRAY_SIZE(ep_name)
+
+struct ak880x_udc {
+	struct usb_gadget		gadget;
+	struct usb_gadget_driver	*driver;
+
+	struct ak880x_ep	ep[ENDPOINTS_NUM];
+	enum ep0_status		ep0_status;
+
+	void __iomem		*baseaddr;
+
+	unsigned int	mcu_irq;
+	unsigned int	dma_irq;
+	struct clk	*clk;
+	char		addr;   /* assigned device address */ 
+	int		enabled;
+};
+
+static void udc_reinit(struct ak880x_udc *udc);
+static void udc_enable(struct ak880x_udc *udc, int enable);
+static void done(struct ak880x_ep *ep, struct ak880x_request *req, int status);
+#endif
diff --git a/drivers/usb/gadget/ak88-udc/ak88_usbburn.c b/drivers/usb/gadget/ak88-udc/ak88_usbburn.c
new file mode 100644
index 00000000000..e92160eddd9
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_usbburn.c
@@ -0,0 +1,314 @@
+/*
+ * ak880_usbburn -- driver for ak88/ak98 USB burntool;
+ * Features
+ * AUTHOR Zhang Jingyuan
+ * 10-09-27 16:28:08
+ */
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/cdev.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <asm/uaccess.h>
+#include <linux/module.h>
+#include <linux/device.h>
+
+#include <mach/ak880x_addr.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#define BUFFER_SIZE (1<<17)
+#define DEVICE_NAME "ak88_usbburn"
+
+#define AK_USBBURN_STALL		0
+#define AK_USBBURN_STATUS		1	
+
+unsigned int sense_data;
+struct semaphore sense_data_lock;
+
+EXPORT_SYMBOL(sense_data);
+EXPORT_SYMBOL(sense_data_lock);
+
+static int major = 0;
+struct usbburn_dev {
+	struct cdev cdev;
+	wait_queue_head_t rq_rbuf, wq_rbuf;	/* read and write queues for rbuf */
+	wait_queue_head_t rq_wbuf, wq_wbuf;	/* read and write queues for wbuf */
+	void *rbuf;	/* This buffer is used for user reading */
+	size_t rlen; /* The length of rbuf */
+	void *wbuf;	/* This buffer is used for user writing */
+	size_t wlen; /* The length of wbuf */
+	struct semaphore r_sem, w_sem;	/* mutual exclusion semaphore for rbuf and wbuf; */
+	int r_stall; /* The flag of stop of rbuf */
+	int w_stall; /* The flag of sotp of wbuf */
+} *b_dev;
+struct class *usbburn_class;
+
+static int ak88_usbburn_open(struct inode *inode, struct file *file)
+{
+
+	return 0;
+}
+
+static int ak88_usbburn_close(struct inode *inode, struct file *file)
+{
+	printk("ak88_usbburn device is closed\n");
+
+	return 0;
+}
+
+ssize_t ak88_usbburn_read(struct file *filp, char __user *buf,
+				size_t count, loff_t *f_pos)
+{
+	/*
+	 * count is used to record the number of data to read;
+	 * count1 is used to record the total number of data been read,
+	 * readn is used to record the number of data been read each time.
+	 */
+	size_t count1 = 0, readn;
+
+	while (count != 0) /* when the all data has been read, return. */
+	{
+		down(&b_dev->r_sem); /* before access the rbuf member of b_dev, down the r_sem */
+		while (b_dev->rbuf == NULL) { /* when there is no data to read, sleep to wait. */
+			up(&b_dev->r_sem); /* up the r_sem */
+			wait_event(b_dev->rq_rbuf, b_dev->rbuf != NULL); /* to sleep until some data is coming. */
+			down(&b_dev->r_sem);
+		}
+		readn = min(count, b_dev->rlen);
+
+		/* copy the data to user space */
+		if (copy_to_user(buf + count1, b_dev->rbuf, readn)) {
+			up(&b_dev->r_sem);
+			return -EFAULT;
+		}
+		count1 += readn;
+		count -= readn;
+
+		/* the number of data which has been read is less than b_dev->rlen */
+		if (readn < b_dev->rlen) {
+			b_dev->rbuf += readn;
+			b_dev->rlen -= readn;
+			up(&b_dev->r_sem);
+		} else { /* wake up the wq_rbuf if the all data in rbuf has been read. */
+			b_dev->rbuf = NULL;
+			up(&b_dev->r_sem);
+			wake_up(&b_dev->wq_rbuf);
+
+			/* if the r_stall is set, return */
+			if (b_dev->r_stall == 1) {
+				b_dev->r_stall = 0;
+				break;
+			}
+		}
+	}
+
+	return count1;
+}
+
+int usbburn_write(void *buf, size_t count)
+{
+	down(&b_dev->r_sem); /* down the r_sem before access the rbuf member of b_dev. */
+	b_dev->rbuf = buf;
+	b_dev->rlen = count;
+
+	/* sleep until the all data in rbuf has been read. */
+	while (b_dev->rbuf != NULL) {
+		up(&b_dev->r_sem);
+		wake_up(&b_dev->rq_rbuf);
+		wait_event(b_dev->wq_rbuf, b_dev->rbuf == NULL);
+		down(&b_dev->r_sem);
+	}
+	up(&b_dev->r_sem);
+
+	return count;
+}
+EXPORT_SYMBOL(usbburn_write);
+
+ssize_t ak88_usbburn_write(struct file *filp, const char __user *buf,
+				size_t count, loff_t *f_pos)
+{
+	/*
+	 * count is used to record the number of data to write;
+	 * count1 is used to record the total number of data been written,
+	 * written is used to record the number of data been written each time.
+	 */
+	size_t count1 = 0, written;
+
+	while (count != 0) {
+		down(&b_dev->w_sem); /* before access the wbuf member of b_dev, down the w_sem. */
+		while (b_dev->wbuf == NULL) {
+			up(&b_dev->w_sem); /* up the w_sem. */
+			wait_event(b_dev->wq_wbuf, b_dev->wbuf != NULL); /* sleep until wbuf can be written. */
+			down(&b_dev->w_sem);
+		}
+		written = min(count, b_dev->wlen);
+
+		/* copy the user space buffer to the kernel. */
+		if (copy_from_user(b_dev->wbuf, buf + count1, written)) {
+			up(&b_dev->w_sem);
+			return -EFAULT;
+		}
+		count1 += written;
+		count -= written;
+
+		/* if written if less than b_dev->wlen. */
+		if (written < b_dev->wlen) {
+			b_dev->wbuf += written;
+			b_dev->wlen -= written;
+
+			/* if w_stall is set, wake up the rq_buf and return. */
+			if (b_dev->w_stall == 1) {
+				b_dev->wbuf = NULL;
+				b_dev->wlen = written;
+				b_dev->r_stall = 0;
+				up(&b_dev->w_sem);
+				wake_up(&b_dev->rq_wbuf);
+				break;
+			}
+			up(&b_dev->w_sem);
+		} else { /* wake up rq_wbuf if the wbuf is full written. */
+			b_dev->wbuf = NULL;
+			up(&b_dev->w_sem);
+			wake_up(&b_dev->rq_wbuf);
+		}
+	}
+
+	return count1;
+}
+
+int usbburn_read(void *buf, size_t count)
+{
+	down(&b_dev->w_sem);
+	b_dev->wbuf = buf;
+	b_dev->wlen = count;
+
+	/* sleep until wbuf has been written. */
+	while (b_dev->wbuf != NULL) {
+		up(&b_dev->w_sem);
+		wake_up(&b_dev->wq_wbuf);
+		wait_event(b_dev->rq_wbuf, b_dev->wbuf == NULL);
+		down(&b_dev->w_sem);
+	}
+	count = b_dev->wlen;
+	up(&b_dev->w_sem);
+
+	return count;
+}
+EXPORT_SYMBOL(usbburn_read);
+
+int ak88_usbburn_ioctl(struct inode *inode, struct file *filp,
+		              unsigned int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case AK_USBBURN_STALL:
+		down(&b_dev->w_sem);
+		b_dev->w_stall = 1; /*set the w_stall flag for wbuf. */
+		up(&b_dev->w_sem);
+		break;
+	case AK_USBBURN_STATUS:
+		sense_data = arg;
+		up(&sense_data_lock);
+		break;
+	default:
+		break;
+	}
+	
+	return 0;
+}
+
+void usbburn_ioctl(void)
+{
+	down(&b_dev->r_sem);
+	b_dev->r_stall = 1; /*set the r_stall flag for rbuf. */
+	up(&b_dev->r_sem);
+}
+EXPORT_SYMBOL(usbburn_ioctl);
+
+/* The file operation for the usbburn device.*/
+static struct file_operations ak88_usbburn_fops = {
+	.owner  =   THIS_MODULE,
+	.read = ak88_usbburn_read,
+	.write = ak88_usbburn_write,
+	.ioctl = ak88_usbburn_ioctl,
+	.open   =   ak88_usbburn_open,     
+	.release   =   ak88_usbburn_close,
+};
+
+int __init ak88_usbburn_init(void)
+{
+	int ret = 0;
+	dev_t dev = MKDEV(major, 0);
+	
+	/* allocate the burn device. */
+	b_dev = kmalloc(sizeof(*b_dev), GFP_KERNEL);
+	if (unlikely (!b_dev)) {
+		ret = -ENOMEM;
+		goto out1;
+	}
+	memset(b_dev, 0, sizeof(*b_dev));
+
+	/* Register device major, and accept a dynamic number. */
+	if (major)
+		ret = register_chrdev_region(dev, 1, DEVICE_NAME);
+	else {
+		ret = alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME);
+		major = MAJOR(dev);
+	}
+	if (ret < 0)
+		goto out1;
+	
+	cdev_init(&b_dev->cdev, &ak88_usbburn_fops);
+	b_dev->cdev.owner = THIS_MODULE;
+	ret = cdev_add(&b_dev->cdev, dev, 1);
+	/* Fail gracefully if need be */
+	if (ret) {
+		printk(KERN_NOTICE "Error %d adding ak88_usbburn_dev", ret);
+		goto out1;
+	}
+
+	usbburn_class = class_create(THIS_MODULE, "usbburn");
+	if (IS_ERR(usbburn_class)) {
+		ret = PTR_ERR(usbburn_class);
+		goto out2;
+	}
+	device_create(usbburn_class, NULL, dev, NULL,"ak88_usbburn");
+
+	init_waitqueue_head(&b_dev->rq_rbuf);
+	init_waitqueue_head(&b_dev->wq_rbuf);
+	init_waitqueue_head(&b_dev->rq_wbuf);
+	init_waitqueue_head(&b_dev->wq_wbuf);
+
+	sema_init(&b_dev->r_sem, 1);
+	sema_init(&b_dev->w_sem, 1);
+
+	memset(&sense_data_lock, 0, sizeof(sense_data_lock));
+	sema_init(&sense_data_lock, 0);
+
+	return ret;
+out2:
+	cdev_del(&b_dev->cdev);
+out1:
+	kfree(b_dev);
+
+	return ret;
+}
+
+void __exit ak88_usbburn_exit(void)
+{
+	device_destroy(usbburn_class, MKDEV(major, 0));
+	class_destroy(usbburn_class);
+	cdev_del(&b_dev->cdev);
+	kfree(b_dev);
+	unregister_chrdev_region(MKDEV(major, 0), 1);
+}
+
+module_init(ak88_usbburn_init);
+module_exit(ak88_usbburn_exit);
+
+MODULE_DESCRIPTION("AK88 usbburn driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/usb/gadget/ak88-udc/ak88_usbburn.h b/drivers/usb/gadget/ak88-udc/ak88_usbburn.h
new file mode 100644
index 00000000000..8582d4323d0
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_usbburn.h
@@ -0,0 +1,14 @@
+#ifndef __AK88_USBBURN__
+#define __AK88_USBBURN__
+
+extern int sense_data;
+
+extern struct semaphore sense_data_lock;
+
+extern int usbburn_write(void *buf, size_t count);
+
+extern int usbburn_read(void *buf, size_t count);
+
+extern void usbburn_ioctl(void);
+
+#endif
diff --git a/drivers/usb/gadget/ak88-udc/ak88_usbudc.h b/drivers/usb/gadget/ak88-udc/ak88_usbudc.h
new file mode 100644
index 00000000000..fa234594478
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/ak88_usbudc.h
@@ -0,0 +1,73 @@
+#ifndef __USB_REG_H
+#define __USB_REG_H
+/** USB controller register*/
+#define USB_BASE_ADDR	(0)
+
+#define USB_FIFO_EP0                (USB_BASE_ADDR + 0x0020)
+
+#define USB_REG_FADDR               (USB_BASE_ADDR + 0x0000)
+#define USB_REG_POWER               (USB_BASE_ADDR + 0x0001)
+#define USB_REG_INTRTX1             (USB_BASE_ADDR + 0x0002)
+#define USB_REG_INTRTX2             (USB_BASE_ADDR + 0x0003)
+#define USB_REG_INTRRX1             (USB_BASE_ADDR + 0x0004)
+#define USB_REG_INTRRX2           	(USB_BASE_ADDR + 0x0005)
+#define USB_REG_INTRTX1E          	(USB_BASE_ADDR + 0x0006)
+#define USB_REG_INTRTX2E          	(USB_BASE_ADDR + 0x0007)
+#define USB_REG_INTRRX1E          	(USB_BASE_ADDR + 0x0008)
+#define USB_REG_INTRRX2E          	(USB_BASE_ADDR + 0x0009)
+#define USB_REG_INTRUSB           	(USB_BASE_ADDR + 0x000A)
+#define USB_REG_INTRUSBE          	(USB_BASE_ADDR + 0x000B)
+#define USB_REG_FRAME1            	(USB_BASE_ADDR + 0x000C)
+#define USB_REG_FRAME2            	(USB_BASE_ADDR + 0x000D)
+#define USB_REG_INDEX             	(USB_BASE_ADDR + 0x000E)
+#define USB_REG_TESEMODE          	(USB_BASE_ADDR + 0x000F)
+#define USB_REG_DEVCTL            	(USB_BASE_ADDR + 0x0060)
+#define USB_REG_TXMAXP0           	(USB_BASE_ADDR + 0x0010)
+#define USB_REG_TXMAXP1           	(USB_BASE_ADDR + 0x0010)
+#define USB_REG_CSR0              	(USB_BASE_ADDR + 0x0012)
+#define USB_REG_TXCSR1            	(USB_BASE_ADDR + 0x0012)
+#define USB_REG_CSR02             	(USB_BASE_ADDR + 0x0013)
+#define USB_REG_TXCSR2            	(USB_BASE_ADDR + 0x0013)
+#define USB_REG_RXMAXP1           	(USB_BASE_ADDR + 0x0014)
+#define USB_REG_RXMAXP2           	(USB_BASE_ADDR + 0x0015)
+#define USB_REG_RXCSR1            	(USB_BASE_ADDR + 0x0016)
+#define USB_REG_RXCSR2            	(USB_BASE_ADDR + 0x0017)
+#define USB_REG_COUNT0            	(USB_BASE_ADDR + 0x0018)
+#define USB_REG_RXCOUNT1          	(USB_BASE_ADDR + 0x0018)
+#define USB_REG_RXCOUNT2          	(USB_BASE_ADDR + 0x0019)
+#define USB_REG_TXTYPE            	(USB_BASE_ADDR + 0x001A)
+#define USB_REG_RXTYPE            	(USB_BASE_ADDR + 0x001C)
+#define USB_REG_RXINTERVAL        	(USB_BASE_ADDR + 0x001D)
+#define USB_REG_NAKLIMIT0         	(USB_BASE_ADDR + 0x001B)
+					
+#define	USB_EP0_TX_COUNT		  	(USB_BASE_ADDR + 0x0330)
+#define	USB_EP2_TX_COUNT		  	(USB_BASE_ADDR + 0x0334)
+					
+#define	USB_FORBID_WRITE_REG	  	(USB_BASE_ADDR + 0x0338)
+					
+#define	USB_START_PRE_READ_REG	  	(USB_BASE_ADDR + 0x033C)
+#define	USB_FS_SPEED_REG		  	(USB_BASE_ADDR + 0x0344)
+
+
+/**  USB DMA */                   	
+// #define USB_DMA_INTR              	(USB_BASE_ADDR + 0x0200)
+#define USB_DMA_CNTL_1            	(USB_BASE_ADDR + 0x0204)
+#define USB_DMA_ADDR_1            	(USB_BASE_ADDR + 0x0208)
+#define USB_DMA_COUNT_1           	(USB_BASE_ADDR + 0x020c)
+#define USB_DMA_CNTL_2            	(USB_BASE_ADDR + 0x0214)
+#define USB_DMA_ADDR_2            	(USB_BASE_ADDR + 0x0218)
+#define USB_DMA_COUNT_2           	(USB_BASE_ADDR + 0x021c)
+
+/* usb control and status register */
+#define USB_REG_RXCSR1_RXSTALL    	(1 << 6)
+#define USB_REG_RXCSR1_REQPKT     	(1 << 5)
+
+#define USB_TXCSR_AUTOSET          	(0x80)
+#define USB_TXCSR_ISO              	(0x40)
+#define USB_TXCSR_MODE1            	(0x20)
+#define USB_TXCSR_DMAREQENABLE     	(0x10)
+#define USB_TXCSR_FRCDATATOG       	(0x8)
+#define USB_TXCSR_DMAREQMODE1      	(0x4)
+#define USB_TXCSR_DMAREQMODE0      	(0x0)
+
+#endif
diff --git a/drivers/usb/gadget/ak88-udc/anyka_usbburn.c b/drivers/usb/gadget/ak88-udc/anyka_usbburn.c
new file mode 100644
index 00000000000..18897d231e2
--- /dev/null
+++ b/drivers/usb/gadget/ak88-udc/anyka_usbburn.c
@@ -0,0 +1,176 @@
+#include "ak88_usbburn.h"
+
+static int check_anyka_command(struct fsg_dev *fsg, int needs_medium)
+{
+	struct lun		*curlun;
+
+	fsg->residue = fsg->usb_amount_left = fsg->data_size;
+
+	/* Check the LUN */
+	if (fsg->lun >= 0 && fsg->lun < fsg->nluns) {
+		fsg->curlun = curlun = &fsg->luns[fsg->lun];
+		curlun->sense_data = SS_NO_SENSE;
+		curlun->sense_data_info = 0;
+		curlun->info_valid = 0;
+	} else {
+		fsg->curlun = curlun = NULL;
+		fsg->bad_lun_okay = 0;
+
+		DBG(fsg, "unsupported LUN %d\n", fsg->lun);
+		return -EINVAL;
+	}
+
+	if (curlun && !backing_file_is_open(curlun) && needs_medium) {
+		curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int do_anyka_read(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	int			rc;
+	u32			amount_left;
+	unsigned int		amount;
+	ssize_t nread;
+
+	/* Carry out the file reads */
+	amount_left = fsg->data_size_from_cmnd;
+	if (unlikely(amount_left == 0))
+		return -EIO;		// No default reply
+
+	for (;;) {
+
+		/* Figure out how much we need to read:
+		 * Try to read the remaining amount.
+		 * But don't read more than the buffer size.
+		 * And don't try to read past the end of the file.
+		 * Finally, if we're not at a page boundary, don't read past
+		 *	the next page.
+		 * If this means reading 0 then we were asked to read past
+		 *	the end of file. */
+		amount = min((unsigned int) amount_left, mod_data.buflen);
+
+		/* Wait for the next buffer to become available */
+		bh = fsg->next_buffhd_to_fill;
+		while (bh->state != BUF_STATE_EMPTY) {
+			rc = sleep_thread(fsg);
+			if (rc)
+				return rc;
+		}
+
+		nread = usbburn_read(bh->buf + nread, amount);
+
+		amount_left  -= nread;
+		fsg->residue -= nread;
+		bh->inreq->length = nread;
+		bh->state = BUF_STATE_FULL;
+
+		if (nread < amount)
+			break;
+		if (amount_left == 0)
+			break;		// No more left to read
+
+		/* Send this buffer and go read some more */
+		bh->inreq->zero = 0;
+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
+				&bh->inreq_busy, &bh->state);
+		fsg->next_buffhd_to_fill = bh->next;
+	}
+
+	return -EIO;		// No default reply
+}
+
+static int do_anyka_write(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	struct fsg_buffhd	*bh;
+	int			get_some_more;
+	u32			amount_left_to_req, amount_left_to_write;
+	loff_t			file_offset;
+	unsigned int		amount;
+	ssize_t			nwritten;
+	int			rc;
+
+	/* Carry out the file writes */
+	get_some_more = 1;
+	file_offset = 0;
+	amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
+
+	while (amount_left_to_write > 0) {
+
+		/* Queue a request for more data from the host */
+		bh = fsg->next_buffhd_to_fill;
+		if (bh->state == BUF_STATE_EMPTY && get_some_more) {
+
+			amount = min(amount_left_to_req, mod_data.buflen);
+
+			/* Get the next buffer */
+			fsg->usb_amount_left -= amount;
+			amount_left_to_req -= amount;
+			if (amount_left_to_req == 0)
+				get_some_more = 0;
+
+			/* amount is always divisible by 512, hence by
+			 * the bulk-out maxpacket size */
+			bh->outreq->length = bh->bulk_out_intended_length =
+					amount;
+			bh->outreq->short_not_ok = 1;
+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
+					&bh->outreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+			continue;
+		}
+
+		/* Write the received data to the backing file */
+		bh = fsg->next_buffhd_to_drain;
+		if (bh->state == BUF_STATE_EMPTY && !get_some_more)
+			break;			// We stopped early
+		if (bh->state == BUF_STATE_FULL) {
+			smp_rmb();
+			fsg->next_buffhd_to_drain = bh->next;
+			bh->state = BUF_STATE_EMPTY;
+
+			/* Did something go wrong with the transfer? */
+			if (bh->outreq->status != 0) {
+				curlun->sense_data = SS_COMMUNICATION_FAILURE;
+				// curlun->sense_data_info = file_offset >> 9;
+				curlun->info_valid = 1;
+				break;
+			}
+
+			amount = bh->outreq->actual;
+			if (fsg->data_size_from_cmnd - file_offset < amount) {
+				LERROR(curlun,
+	"write %u @ %llu beyond end %llu\n",
+	amount, (unsigned long long) file_offset,
+	(unsigned long long) curlun->file_length);
+				amount = curlun->file_length - file_offset;
+			}
+
+			/* Perform the write */
+			nwritten = 0;
+			nwritten = usbburn_write(bh->buf + nwritten, amount);
+
+			file_offset += nwritten;
+			amount_left_to_write -= nwritten;
+			fsg->residue -= nwritten;
+
+			/* Did the host decide to stop early? */
+			if (bh->outreq->actual != bh->outreq->length) {
+				fsg->short_packet_received = 1;
+				break;
+			}
+			continue;
+		}
+
+		/* Wait for something to happen */
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	return -EIO;		// No default reply
+}
diff --git a/drivers/usb/gadget/ak98-udc/Kconfig b/drivers/usb/gadget/ak98-udc/Kconfig
new file mode 100644
index 00000000000..5cc1daaec20
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/Kconfig
@@ -0,0 +1,27 @@
+config USB_GADGET_AK98_PRODUCER
+	boolean "AK98 USB Device Port for PRODUCER"
+	depends on ARCH_AK98
+	select USB_GADGET_SELECTED
+	select USB_GADGET_DUALSPEED
+	help
+	  AK98 OTG device support for producer
+
+if USB_GADGET_AK98_PRODUCER
+config USB_AK98_PRODUCER
+	tristate
+	default m
+endif
+
+config USB_GADGET_AK98
+	boolean "AK98 USB Device Port"
+	depends on ARCH_AK98
+	select USB_GADGET_SELECTED
+	select USB_GADGET_DUALSPEED
+	help
+	  AK98 OTG device support
+
+if USB_GADGET_AK98
+config USB_AK98
+	tristate
+	default y 
+endif
diff --git a/drivers/usb/gadget/ak98-udc/Makefile b/drivers/usb/gadget/ak98-udc/Makefile
new file mode 100644
index 00000000000..40ea27b18ee
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/Makefile
@@ -0,0 +1,9 @@
+
+obj-$(CONFIG_USB_AK98_PRODUCER)	+= ak98_udc_full.o
+obj-$(CONFIG_USB_AK98_PRODUCER)	+= ak98_udc.o
+ifdef CONFIG_USB_FILE_STORAGE
+obj-y	+= ak98_usbburn.o
+endif
+
+obj-$(CONFIG_USB_AK98)	+= ak98_udc.o
+
diff --git a/drivers/usb/gadget/ak98-udc/ak98_udc.c b/drivers/usb/gadget/ak98-udc/ak98_udc.c
new file mode 100644
index 00000000000..493257486fc
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_udc.c
@@ -0,0 +1,2146 @@
+/*
+ * ak980x_udc -- driver for ak980x USB peripheral controller
+ * Features
+ * The USB 2.0 HS OTG has following features:
+ *      •   compliant with USB Specification Version 2.0 (HS) and On-The-Go supplement to
+ *	  the USB 2.0 specification
+ *      •   operating as the host in point-to-point communications with another USB function
+ *	  or as a function controller for a USB peripheral
+ *      •   supporting UTMI+ Level 2 Transceiver Interface
+ *      •   4 Transmit/Receive endpoints in addition to Endpoint 0
+ *      •   3 DMA channels
+ * AUTHOR ANYKA Zhang Jingyuan
+ * 09-11-14 10:45:03
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/workqueue.h>
+#include <linux/dma-mapping.h>
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+#include <linux/ak98_freq_policy.h>
+#endif
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/gpio.h>
+#include <asm/dma-mapping.h>
+
+#include <mach/regs-comm.h>
+#include <mach/l2.h>
+
+#include "ak98_udc.h"
+
+#define AK98_UDC_EPS 5
+
+
+#if 0
+#define dbg(fmt, arg...) printk("%s(%d): " fmt "\n", __func__, __LINE__, ##arg)
+#else
+#define dbg(fmt, arg...)
+#endif
+
+static const char ep0name[] = "ep0";
+static const char driver_name[] = "ak98_udc";
+
+#define udc_readb(reg)	__raw_readb(udc->baseaddr + (reg))
+#define udc_readw(reg)	__raw_readw(udc->baseaddr + (reg))
+#define udc_readl(reg)	__raw_readl(udc->baseaddr + (reg))
+#define udc_writeb(reg, val) __raw_writeb(val, udc->baseaddr + (reg))
+#define udc_writew(reg, val) __raw_writew(val, udc->baseaddr + (reg))
+#define udc_writel(reg, val) __raw_writel(val, udc->baseaddr + (reg))
+
+static struct ak980x_udc controller;
+/* static struct ak980x_udc *udc = &controller; */
+struct workqueue_struct *ep_wqueue;
+
+volatile int usb_detect;
+volatile int usb_exist;
+EXPORT_SYMBOL(usb_detect);
+EXPORT_SYMBOL(usb_exist);
+
+unsigned int dma_rx;
+unsigned int dma_tx;
+dma_addr_t phys_rx;
+dma_addr_t phys_tx;
+
+static volatile char flag = 0;
+static u32 start = 0;
+
+static void ep_irq_enable(struct usb_ep *_ep)
+{
+	static struct ak980x_udc *udc = &controller;
+	
+	if (strcmp(_ep->name, udc->ep[1].ep.name))
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<1));
+
+	if (strcmp(_ep->name, udc->ep[2].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<2));
+	
+	if (strcmp(_ep->name, udc->ep[3].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<3));
+
+	if (strcmp(_ep->name, udc->ep[4].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<4));
+	
+	if (strcmp(_ep->name, udc->ep[5].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<5));
+}
+
+static void ep_irq_disable(struct usb_ep *_ep)
+{
+	static struct ak980x_udc *udc = &controller;
+	
+	if (strcmp(_ep->name, udc->ep[1].ep.name))
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<1));
+
+	if (strcmp(_ep->name, udc->ep[2].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<2));
+	
+	if (strcmp(_ep->name, udc->ep[3].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<3));
+
+	if (strcmp(_ep->name, udc->ep[4].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<4));
+	
+	if (strcmp(_ep->name, udc->ep[5].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<5));
+}
+
+static inline void reset_usbcontroller(void)
+{
+	rCLK_CON1 |= (0x1<<31);
+	rCLK_CON1 &= ~(0x1<<31);
+}
+
+static void done(struct ak980x_ep *ep, struct ak980x_request *req, int status)
+{
+	unsigned	 stopped = ep->stopped;
+	//struct ak980x_udc *udc = ep->udc;
+
+	list_del_init(&req->queue);
+
+	if (likely (req->req.status == -EINPROGRESS))
+		req->req.status = status;
+	else
+		status = req->req.status;
+
+	ep->stopped = 1;
+	req->req.complete(&ep->ep, &req->req);
+	ep->stopped = stopped;
+
+	dbg("%s done, req.status(%d)", ep->ep.name, req->req.status);
+}
+
+static int write_ep0_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	int i;
+	unsigned total, count, is_last;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+
+	total = req->req.length - req->req.actual;
+
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count < ep->ep.maxpacket) || !req->req.zero;
+	}
+
+	dbg("is_last(%d), count(%d), total(%d), actual(%d), length(%d)", 
+			is_last, count, total, req->req.actual, req->req.length);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	if (count == 0) {
+		dbg(" count == 0 ");
+		udc_writel(USB_EP0_NUM, count&0x7f);
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+		return 1;
+	}
+
+	buf = req->req.buf + req->req.actual;
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP0_FIFO, buf[i]);
+
+	udc_writel(USB_EP0_NUM, count&0x7f); /* 7bits */ 
+	if (is_last) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+	} else {
+		udc_writeb(USB_CTRL_1, 0x1<<1);
+	}
+
+	req->req.actual += count;
+	if (is_last) {
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+	}
+
+	ep->done = is_last;
+	return is_last;
+	/* return 1; */
+}
+
+static int read_ep0_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	int i;
+	unsigned total, count, is_last;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+
+	total = req->req.length - req->req.actual;
+
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count < ep->ep.maxpacket) || !req->req.zero;
+	}
+
+	dbg("is_last(%d), count(%d), total(%d), actual(%d), length(%d)", 
+			is_last, count, total, req->req.actual, req->req.length);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	if (count == 0) {
+		dbg(" count == 0 ");
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+		return 1;
+	}
+
+	buf = req->req.buf + req->req.actual;
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP0_FIFO);
+ 
+	if (is_last) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+	} else {
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+	}
+
+	req->req.actual += count;
+	if (is_last) {
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+	}
+
+	ep->done = is_last;
+	return is_last;
+	/* return 1; */
+}
+
+
+static int write_ep1_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	return 1;
+}
+
+static int write_ep2_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep2 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned total, count, is_last;
+	unsigned char *buf;
+	//dma_addr_t phys;
+	int dma = 0, i;
+
+	total = req->req.length - req->req.actual;
+	if (ep->ep.maxpacket <= total) {
+		count = ep->ep.maxpacket;
+		is_last = (total == ep->ep.maxpacket) && !req->req.zero;
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+		dma = 1;
+#endif
+#endif
+	} else {
+		count = total;
+		is_last = count < ep->ep.maxpacket;
+		dma = 0;
+	}
+	dbg("total(%d), count(%d), is_last(%d)", total, count, is_last);
+
+	if (count == 0) { /* not support command */ 
+		dbg("count == 0\n");
+		ep->done = 1;
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1, 0x1);
+		return 0;
+	}
+	udc_writeb(USB_EP_INDEX, 2);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (dma == 1) {
+		dma_tx = total - (total % ep->ep.maxpacket);
+		phys_tx = dma_map_single(NULL, buf, dma_tx, DMA_TO_DEVICE);
+		if (phys_tx == 0) {
+			printk("tx dma_map_single error!\n");
+			goto cpu;
+		}
+
+		udc_writeb(USB_CTRL_1_2, (1<<2) | (1<<4) | (1<<5) | (1<<7));
+		
+		//send data to l2
+		ak98_l2_clr_status(ep->l2_buf_id);
+		ak98_l2_combuf_dma(phys_tx, ep->l2_buf_id, dma_tx, MEM2BUF, false);
+		udc_writel(USB_DMA_ADDR1, 0x70000000);
+		udc_writel(USB_DMA_COUNT1, dma_tx);
+		udc_writel(USB_DMA_CTRL1, (USB_ENABLE_DMA | USB_DIRECTION_TX | USB_DMA_MODE1 | USB_DMA_INT_ENABLE| (USB_EP2_INDEX<<4) | USB_DMA_BUS_MODE3));
+		
+		ep->done = 0;
+		return 0;
+	}
+#endif
+#endif
+
+cpu:
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP2_FIFO, buf[i]);
+
+	udc_writeb(USB_CTRL_1, 0x1);
+
+	req->req.actual += count;
+	/* wait a tx complete int */
+        /*
+	 * if (is_last)
+	 *         done(ep, req, 0);
+         */
+
+	/* return is_last; */
+	ep->done = is_last;
+
+	return 0;
+}
+
+static int read_ep3_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep3 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr, i;
+	unsigned int count, bufferspace, is_done;
+	//dma_addr_t phys;
+
+	if (flag == 1)
+		return 0;
+
+	bufferspace = req->req.length - req->req.actual;
+
+	udc_writeb(USB_EP_INDEX, 3);
+	csr = udc_readb(USB_CTRL_2);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting bulkout data");
+		return 0;
+	}
+
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)",
+				csr, count, bufferspace);
+		dbg("what happened??");
+		goto stall;
+	} else if (count > ep->ep.maxpacket)
+		count = ep->ep.maxpacket;
+
+	if (count > bufferspace) {
+		dbg("%s buffer overflow\n", ep->ep.name);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)", csr, count, bufferspace);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP3_FIFO);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	dma_rx = bufferspace - count;
+	if (dma_rx >= ep->ep.maxpacket) {
+		dma_rx -= (dma_rx % ep->ep.maxpacket);
+		
+		buf = req->req.buf + req->req.actual + count;
+		phys_rx = dma_map_single(NULL, buf, dma_rx, DMA_FROM_DEVICE);
+		if (phys_rx == 0) {
+			printk("rx dma_map_single error!\n");
+			goto stall;
+		}
+
+		req->req.actual += count;
+		flag = 1;
+		udc_writeb(USB_CTRL_2_2, udc_readb(USB_CTRL_2_2) | (1<<3) | (1<<5) | (1<<7));
+		ak98_l2_combuf_dma(phys_rx, ep->l2_buf_id, dma_rx, BUF2MEM, false);
+		udc_writel(USB_DMA_ADDR2, 0x71000000);
+		udc_writel(USB_DMA_COUNT2, dma_rx);
+		udc_writel(USB_DMA_CTRL2, (USB_ENABLE_DMA|USB_DIRECTION_RX|USB_DMA_MODE1|USB_DMA_INT_ENABLE|(USB_EP3_INDEX<<4)|USB_DMA_BUS_MODE3));
+		udc_writeb(USB_EP_INDEX, 3);
+		udc_writeb(USB_CTRL_2, csr & ~0x1);
+		ep->done = 0;
+
+		return 0;
+	}
+#endif
+#endif
+	
+stall:
+	udc_writeb(USB_CTRL_2, csr & ~0x1);
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+
+	ep->done = is_done;
+	if (is_done) {
+		done(ep, req, 0);
+	}
+
+	return is_done;
+}
+
+static int write_ep4_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep4 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned total, count, is_last;
+	unsigned char *buf;
+	//dma_addr_t phys;
+	int dma = 0, i;
+
+	total = req->req.length - req->req.actual;
+	if (ep->ep.maxpacket <= total) {
+		count = ep->ep.maxpacket;
+		is_last = (total == ep->ep.maxpacket) && !req->req.zero;
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+		dma = 1;
+#endif
+#endif
+	} else {
+		count = total;
+		is_last = count < ep->ep.maxpacket;
+		dma = 0;
+	}
+	dbg("total(%d), count(%d), is_last(%d)", total, count, is_last);
+
+	if (count == 0) { /* not support command */ 
+		dbg("count == 0\n");
+		ep->done = 1;
+		udc_writeb(USB_EP_INDEX, 4);
+		udc_writeb(USB_CTRL_1, 0x1);
+		return 0;
+	}
+	udc_writeb(USB_EP_INDEX, 4);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (dma == 1) {
+		dma_tx = total - (total % ep->ep.maxpacket);
+		phys_tx = dma_map_single(NULL, buf, dma_tx, DMA_TO_DEVICE);
+		if (phys_tx == 0) {
+			printk("tx dma_map_single error!\n");
+			goto cpu;
+		}
+
+		udc_writeb(USB_CTRL_1_2, (1<<2) | (1<<4) | (1<<5) | (1<<7));
+		
+		//send data to l2
+		ak98_l2_clr_status(ep->l2_buf_id);
+		ak98_l2_combuf_dma(phys_tx, ep->l2_buf_id, dma_tx, MEM2BUF, false);
+		udc_writel(USB_DMA_ADDR3, 0x72000000);
+		udc_writel(USB_DMA_COUNT3, dma_tx);
+		udc_writel(USB_DMA_CTRL3, (USB_ENABLE_DMA | USB_DIRECTION_TX | USB_DMA_MODE1 | USB_DMA_INT_ENABLE| (USB_EP4_INDEX<<4) | USB_DMA_BUS_MODE3));
+		
+		ep->done = 0;
+		return 0;
+	}
+#endif
+#endif
+
+cpu:
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP4_FIFO, buf[i]);
+
+	udc_writeb(USB_CTRL_1, 0x1);
+
+	req->req.actual += count;
+	/* wait a tx complete int */
+        /*
+	 * if (is_last)
+	 *         done(ep, req, 0);
+         */
+
+	/* return is_last; */
+	ep->done = is_last;
+
+	return 0;
+}
+
+static int read_ep5_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep5 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr, i;
+	unsigned int count, bufferspace, is_done;
+	//dma_addr_t phys;
+
+	if (flag == 1)
+		return 0;
+
+	bufferspace = req->req.length - req->req.actual;
+
+	udc_writeb(USB_EP_INDEX, 5);
+	csr = udc_readb(USB_CTRL_2);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting bulkout data");
+		return 0;
+	}
+
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)",
+				csr, count, bufferspace);
+		dbg("what happened??");
+		goto stall;
+	} else if (count > ep->ep.maxpacket)
+		count = ep->ep.maxpacket;
+
+	if (count > bufferspace) {
+		dbg("%s buffer overflow\n", ep->ep.name);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)", csr, count, bufferspace);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP5_FIFO);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	dma_rx = bufferspace - count;
+	if (dma_rx >= ep->ep.maxpacket) {
+		dma_rx -= (dma_rx % ep->ep.maxpacket);
+		
+		buf = req->req.buf + req->req.actual + count;
+		phys_rx = dma_map_single(NULL, buf, dma_rx, DMA_FROM_DEVICE);
+		if (phys_rx == 0) {
+			printk("rx dma_map_single error!\n");
+			goto stall;
+		}
+
+		req->req.actual += count;
+		flag = 1;
+		udc_writeb(USB_CTRL_2_2, udc_readb(USB_CTRL_2_2) | (1<<3) | (1<<5) | (1<<7));
+		ak98_l2_combuf_dma(phys_rx, ep->l2_buf_id, dma_rx, BUF2MEM, false);
+		udc_writel(USB_DMA_ADDR4, 0x73000000);
+		udc_writel(USB_DMA_COUNT4, dma_rx);
+		udc_writel(USB_DMA_CTRL4, (USB_ENABLE_DMA|USB_DIRECTION_RX|USB_DMA_MODE1|USB_DMA_INT_ENABLE|(USB_EP5_INDEX<<4)|USB_DMA_BUS_MODE3));
+		udc_writeb(USB_EP_INDEX, 5);
+		udc_writeb(USB_CTRL_2, csr & ~0x1);
+		ep->done = 0;
+
+		return 0;
+	}
+#endif
+#endif
+	
+stall:
+	udc_writeb(USB_CTRL_2, csr & ~0x1);
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+
+	ep->done = is_done;
+	if (is_done) {
+		done(ep, req, 0);
+	}
+
+	return is_done;
+}
+
+static int ak980x_get_frame(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+static int ak980x_wakeup(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+
+static int ak980x_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct ak980x_udc *udc = &controller;
+	
+	dbg("is_on(%d)", is_on);
+
+	if (is_on) {
+		clk_enable(udc->clk);
+		
+		rMULFUN_CON1 &= ~0x7;
+		rMULFUN_CON1 |= 0x6;
+	}
+	else {
+		rMULFUN_CON1 &= ~0x7;
+		
+		clk_disable(udc->clk);
+
+		reset_usbcontroller();
+	}
+
+	return 0;
+}
+
+static int ak980x_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	dbg("");
+	return 0;
+}
+
+static int ak980x_set_selfpowered(struct usb_gadget *gadget, int value)
+{
+	struct ak980x_udc *udc = &controller;
+
+	dbg("%d", value);
+	if (value)
+		udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
+	else
+		udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
+	
+	return 0;
+}
+static const struct usb_gadget_ops ak980x_udc_ops = {
+	.get_frame		= ak980x_get_frame,
+	.wakeup			= ak980x_wakeup,
+	.set_selfpowered	= ak980x_set_selfpowered,
+	.vbus_session		= ak980x_vbus_session,
+	.pullup			= ak980x_pullup,
+};
+
+static void ep2_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[2];
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = write_ep2_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep3_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[3];
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = read_ep3_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep4_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[4];
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = write_ep4_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep5_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[5];
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = read_ep5_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static int ak980x_ep_enable(struct usb_ep *_ep,
+				const struct usb_endpoint_descriptor *desc)
+{
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	struct ak980x_udc *udc = ep->udc;
+	int tmp, maxpacket;
+	unsigned long flags;
+
+	if (!_ep || !ep
+			|| !desc || ep->desc
+			|| _ep->name == ep0name
+			|| desc->bDescriptorType != USB_DT_ENDPOINT
+			|| (maxpacket = le16_to_cpu(desc->wMaxPacketSize)) == 0
+			|| maxpacket > ep->maxpacket) {
+		dbg("bad ep or descriptor");
+		dbg("%p, %p, %p, %p", _ep, ep, desc, ep->desc);
+		return -EINVAL;
+	}
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		dbg("bogus udcice state\n");
+		return -ESHUTDOWN;
+	}
+	
+	local_irq_save (flags);
+
+	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	switch (tmp) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		dbg("only one control endpoint\n");
+		return -EINVAL;
+	case USB_ENDPOINT_XFER_INT:
+		if (maxpacket > EP1_FIFO_SIZE)
+			dbg("maxpacket too large");
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		switch (maxpacket) {
+		case 8:
+		case 16:
+		case 32:
+		case 64:
+		case 512: /* for usb20 */
+			_ep->maxpacket = maxpacket & 0x7ff;
+			break;
+		default:
+			dbg("bogus maxpacket %d\n", maxpacket);
+			return -EINVAL;
+		}
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		dbg("USB_ENDPOINT_XFER_ISOC");
+		break;
+	}
+	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
+
+	ep->stopped = 0;
+	ep->desc = (struct usb_endpoint_descriptor *)desc;
+
+	dbg("%s, maxpacket(%d), desc->bEndpointAddress (0x%x) is_in(%d)",
+		       	_ep->name, maxpacket, desc->bEndpointAddress, ep->is_in);
+	
+	if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 -- int */ 
+		dbg("");
+		udc_writeb(USB_EP_INDEX, 1);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 64);
+	} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 -- tx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep2_work);
+		//usb_l2_init(L2_USB_EP2, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1, (1<<3) | (1<<6));
+		udc_writeb(USB_CTRL_1_2, 1<<5);
+		udc_writew(USB_TX_MAX, 512);
+	} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 -- rx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep3_work);
+		//usb_l2_init(L2_USB_EP3, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 3);
+		udc_writeb(USB_CTRL_1, 1<<6);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 512);
+		udc_writeb(USB_CTRL_2, udc_readb(USB_CTRL_2) & ~(0x1));
+		udc_writeb(USB_CTRL_2, (1<<4) | (1<<7));
+		udc_writeb(USB_CTRL_2_2, 0);
+	} else if (!strcmp(_ep->name, udc->ep[4].ep.name)) { /* ep4 -- tx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep4_work);
+		//usb_l2_init(L2_USB_EP2, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 4);
+		udc_writeb(USB_CTRL_1, (1<<3) | (1<<6));
+		udc_writeb(USB_CTRL_1_2, 1<<5);
+		udc_writew(USB_TX_MAX, 512);
+	} else if (!strcmp(_ep->name, udc->ep[5].ep.name)){ /* ep5 -- rx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep5_work);
+		//usb_l2_init(L2_USB_EP3, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 5);
+		udc_writeb(USB_CTRL_1, 1<<6);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 512);
+		udc_writeb(USB_CTRL_2, udc_readb(USB_CTRL_2) & ~(0x1));
+		udc_writeb(USB_CTRL_2, (1<<4) | (1<<7));
+		udc_writeb(USB_CTRL_2_2, 0);
+	} else {
+		printk("Invalid ep");
+		return -EINVAL;
+	}
+
+	ep_irq_enable(_ep);
+	local_irq_restore (flags);
+
+	return 0;
+}
+
+static int ak980x_ep_disable (struct usb_ep * _ep)
+{
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	struct ak980x_request *req;
+	unsigned long flags;
+
+	if (!_ep || !ep->desc) {
+		dbg("%s not enabled\n",
+			_ep ? ep->ep.name : NULL);
+		return -EINVAL;
+	}
+	
+	local_irq_save(flags);
+	dbg("%s", _ep->name);
+	ep->desc = NULL;
+	ep->stopped = 1;
+	
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+		done(ep, req, -ESHUTDOWN);
+	}
+	ep_irq_disable(_ep);
+	local_irq_restore(flags);
+	
+	return 0;
+}
+
+static struct usb_request *
+	ak980x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+	struct ak980x_request *req;
+
+	dbg("%s", _ep->name);
+	req = kzalloc(sizeof (struct ak980x_request), gfp_flags);
+	if (!req)
+		return NULL;
+
+	INIT_LIST_HEAD(&req->queue);
+	return &req->req;
+}
+
+static void ak980x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak980x_request *req;
+
+	dbg("%s", _ep->name);
+	req = container_of(_req, struct ak980x_request, req);
+	WARN_ON(!list_empty(&req->queue));
+	kfree(req);
+}
+
+static int ak980x_ep_queue(struct usb_ep *_ep,
+			struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct ak980x_request	*req;
+	struct ak980x_ep	*ep;
+	struct ak980x_udc	*udc;
+	int			status = 0;
+	unsigned long flags;
+
+	req = container_of(_req, struct ak980x_request, req);
+	ep = container_of(_ep, struct ak980x_ep, ep);
+	
+	if (!_ep || (!ep->desc && ep->ep.name != ep0name)) {
+		dbg("invalid ep\n");
+		return -EINVAL;
+	}
+
+	udc = ep->udc;
+	if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		/* dbg("invalid device\n"); */
+		printk("invalid device\n");
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+
+	if (!_req || !_req->complete
+			|| !_req->buf || !list_empty(&req->queue)) {
+		/* dbg("%s invalid request", _ep->name); */
+		printk("%s invalid request\n", _ep->name);
+		local_irq_restore(flags);
+		return -EINVAL;
+	}
+
+	_req->status = -EINPROGRESS;
+	_req->actual = 0;
+
+	dbg("%s queue is_in(%d)", ep->ep.name, ep->is_in);
+	if (list_empty(&ep->queue) && !ep->stopped) {
+		if (ep->ep.name == ep0name) {
+			udc_writeb(USB_EP_INDEX, 0);
+			
+			switch (udc->ep0state) {
+			case EP0_IN_DATA_PHASE:
+				if ((udc_readb(USB_CTRL_1) & (1 << 1)) == 0
+						&& write_ep0_fifo(ep, req)) {
+					udc->ep0state = EP0_IDLE;
+					req = NULL;
+				}
+				break;
+
+			case EP0_OUT_DATA_PHASE:
+				if ((!_req->length) ||
+					((udc_readb(USB_CTRL_1) & (1 << 0))
+					&& read_ep0_fifo(ep, req))) {
+					udc->ep0state = EP0_IDLE;
+					req = NULL;
+				}
+				break;
+				
+			default:
+				local_irq_restore(flags);
+				return -EL2HLT;
+			}
+			if (req)
+				list_add_tail(&req->queue, &ep->queue);
+		} else {
+			list_add_tail(&req->queue, &ep->queue);
+			if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 */ 
+				dbg("ep1");
+				status = write_ep1_fifo(ep, req);
+			} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 */ 			
+				udc_writeb(USB_EP_INDEX, 2);
+				if ((udc_readb(USB_CTRL_1) & 1) == 0)
+					queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 */ 
+				udc_writeb(USB_EP_INDEX, 3);
+				if (udc_readb(USB_CTRL_2) & 1)
+					queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[4].ep.name)) { /* ep4 */ 
+				udc_writeb(USB_EP_INDEX, 4);
+				if ((udc_readb(USB_CTRL_1) & 1) == 0)
+				queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[5].ep.name)){ /* ep5 */ 
+				udc_writeb(USB_EP_INDEX, 5);
+				if (udc_readb(USB_CTRL_2) & 1)
+					queue_work(ep_wqueue, &ep->work);
+			} else {
+				printk("Invalid ep");
+				status = -EINVAL;
+				goto stall;
+			}
+		}
+	} else {
+		status = 0;
+		list_add_tail(&req->queue, &ep->queue);
+		dbg("waiting for %s int", ep->ep.name);
+	}
+
+stall:
+	local_irq_restore(flags);
+	/* return (status < 0) ? status : 0; */
+	return status;
+}
+
+
+static int ak980x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak980x_ep	*ep;
+	struct ak980x_request	*req;
+	unsigned long flags;
+	struct ak980x_udc *udc = &controller;
+	
+	dbg("dequeue");
+
+	if (!udc->driver)
+		return -ESHUTDOWN;
+
+	ep = container_of(_ep, struct ak980x_ep, ep);
+	if (!_ep || !_req)
+		return -EINVAL;
+	
+	local_irq_save(flags);
+	list_for_each_entry (req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req) {
+		local_irq_restore(flags);
+		return -EINVAL;
+	}
+
+	done(ep, req, -ECONNRESET);
+	local_irq_restore(flags);
+	
+	return 0;
+}
+
+static int ak980x_ep_set_halt(struct usb_ep *_ep, int value)
+{	
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	unsigned int csr = 0;
+	unsigned long		flags;
+	struct ak980x_udc *udc = &controller;
+
+	if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+		dbg("inval 2");
+		return -EINVAL;
+	}
+
+	local_irq_save (flags);
+
+	if ((ep->ep.name == ep0name) && value) {
+		udc_writeb(USB_EP_INDEX, 0);
+		udc_writeb(USB_CTRL_1, 1<<5);
+		udc_writeb(USB_CTRL_1, 1<<6 | 1<<3);
+	} else if (ep->is_in) { /* ep2 or ep4*/ 
+		if (!strcmp(ep->ep.name, udc->ep[2].ep.name))
+			udc_writeb(USB_EP_INDEX, 2);
+		else
+			udc_writeb(USB_EP_INDEX, 4);
+
+		csr = udc_readw(USB_CTRL_1);
+		if (value)
+			udc_writew(USB_CTRL_1, csr | 1<<4);
+		else {
+			csr &= ~(1<<4 | 1<<5);
+			udc_writew(USB_CTRL_1, csr);
+			csr |= 1<<6;
+			udc_writew(USB_CTRL_1, csr);
+		}
+	} else { /* ep3 or ep5*/
+		if (!strcmp(ep->ep.name, udc->ep[3].ep.name))
+			udc_writeb(USB_EP_INDEX, 3);
+		else
+			udc_writeb(USB_EP_INDEX, 5);
+		csr = udc_readw(USB_CTRL_2);
+		if (value)
+			udc_writew(USB_CTRL_2, csr | 1<<5);
+		else {
+			csr &= ~(1<<5 | 1<<6);
+			udc_writew(USB_CTRL_2, csr);
+			csr |= 1<<7;
+			udc_writew(USB_CTRL_2, csr);
+		}
+	}
+
+	ep->stopped= value ? 1 : 0;
+	local_irq_restore (flags);
+
+	return 0;
+}
+
+static const struct usb_ep_ops ak980x_ep_ops = {
+	.enable		= ak980x_ep_enable,
+	.disable	= ak980x_ep_disable,
+	.alloc_request	= ak980x_ep_alloc_request,
+	.free_request	= ak980x_ep_free_request,
+	.queue		= ak980x_ep_queue,
+	.dequeue	= ak980x_ep_dequeue,
+	.set_halt	= ak980x_ep_set_halt,
+	// there's only imprecise fifo status reporting
+};
+
+static void nop_release(struct device *dev)
+{
+			/* nothing to free */
+}
+
+static struct ak980x_udc controller = {
+	.gadget = {
+		.ops	= &ak980x_udc_ops,
+		.ep0	= &controller.ep[0].ep,
+		.name	= driver_name,
+		.dev	= {
+		       .init_name = "gadget",
+			   .release = nop_release,
+		}
+	},
+	.ep[0] = {
+		.ep = {
+			.name		= ep0name,//ep_name[0],
+			.ops		= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP0_FIFO_SIZE,
+	},
+	.ep[1] = {
+		.ep = {
+			.name	= "ep1-int",//ep_name[1],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP1_FIFO_SIZE,
+	},
+	.ep[2] = {
+		.ep = {
+			.name	= "ep2in-bulk",//ep_name[2],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP2_FIFO_SIZE,
+	},
+	.ep[3] = {
+		.ep = {
+			/* could actually do bulk too */
+			.name	= "ep3out-bulk",//ep_name[3],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP3_FIFO_SIZE,
+	},
+	.ep[4] = {
+		.ep = {
+			.name	= "ep4in-bulk",//ep_name[4],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP4_FIFO_SIZE,
+	},
+	.ep[5] = {
+		.ep = {
+			.name	= "ep5out-bulk",//ep_name[5],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP5_FIFO_SIZE,
+	},
+};
+
+/**
+ * ak98_udc_process_req_status - process request GET_STATUS
+ * @udc: The device state
+ * @ctrl: USB control request
+ */
+static int ak980x_udc_get_status(struct ak980x_udc *udc,
+					struct usb_ctrlrequest *ctrl)
+{
+	u16 status = 0;
+	u8 ep_num = ctrl->wIndex & 0x7F;
+	u8 is_in = ctrl->wIndex & USB_DIR_IN;
+
+	switch (ctrl->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		status = udc->devstatus;
+		break;
+
+	case USB_RECIP_INTERFACE:
+		/* currently, the data result should be zero */
+		break;
+
+	case USB_RECIP_ENDPOINT:
+		if (ep_num > 5 || ctrl->wLength > 2)
+			return 1;
+
+		if (ep_num == 0) {
+			udc_writeb(USB_EP_INDEX, 0);
+			status = udc_readb(USB_CTRL_1);
+			status = status & (1<<5);
+		} else {
+			udc_writeb(USB_EP_INDEX, ep_num);
+			if (is_in) {
+				status = udc_readb(USB_CTRL_1);
+				status = status & (1<<4);
+			} else {
+				status = udc_readb(USB_CTRL_2);
+				status = status & (1<<5);
+			}
+		}
+
+		status = status ? 1 : 0;
+		break;
+	default:
+		return 1;
+	}
+
+	udc_writeb(USB_EP0_FIFO, status & 0xff);
+	udc_writeb(USB_EP0_FIFO, status >> 8);
+
+	udc_writel(USB_EP0_NUM, 2); /* 7bits */ 
+	udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+
+	udc->ep0state = EP0_END_XFER;
+
+	return 0;
+}
+
+static void ak980x_udc_handle_ep0_idle(struct ak980x_udc *udc,
+					struct ak980x_ep *ep, u32 ep0csr)
+{
+	struct usb_ctrlrequest crq;
+	int i, len, ret, tmp, timeout;
+	unsigned char *buf;
+
+	/* start control request? */
+	if (!(ep0csr & 1))
+		return;
+
+	//s3c2410_udc_nuke(dev, ep, -EPROTO);
+
+	len = udc_readw(USB_EP_COUNT);
+	buf = (unsigned char *)&crq;
+	if (len > sizeof(struct usb_ctrlrequest))
+		len = sizeof(struct usb_ctrlrequest);
+	for (i = 0; i < len; i++)
+		buf[i] = udc_readb(USB_EP0_FIFO);
+	if (len != sizeof(crq)) {
+		dbg("setup begin: fifo READ ERROR"
+			" wanted %d bytes got %d. Stalling out...",
+			sizeof(crq), len);
+		udc_writeb(USB_CTRL_1, 1<<5);
+		return;
+	}
+
+	dbg("bRequest = %d bRequestType %d wLength = %d",
+		crq.bRequest, crq.bRequestType, crq.wLength);
+
+	/* cope with automagic for some standard requests. */
+	udc->req_std = (crq.bRequestType & USB_TYPE_MASK)
+		== USB_TYPE_STANDARD;
+	udc->req_config = 0;
+	udc->req_pending = 1;
+
+	switch (crq.bRequest) {
+	case USB_REQ_SET_CONFIGURATION:
+		dbg("USB_REQ_SET_CONFIGURATION ... ");
+
+		if (crq.bRequestType == USB_RECIP_DEVICE) {
+			udc->req_config = 1;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		}
+		break;
+
+	case USB_REQ_SET_INTERFACE:
+		dbg("USB_REQ_SET_INTERFACE ... ");
+
+		if (crq.bRequestType == USB_RECIP_INTERFACE) {
+			udc->req_config = 1;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		}
+		break;
+
+	case USB_REQ_SET_ADDRESS:
+		dbg("USB_REQ_SET_ADDRESS ... ");
+		if (crq.bRequestType == USB_RECIP_DEVICE) {
+			tmp = crq.wValue & 0x7F;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+			timeout = 20000;
+			/* waiting for next interrupt */ 
+			while (!(udc_readb(USB_INTERRUPT_1) & 0x1) && timeout) {timeout--;}
+			udc_writeb(USB_FUNCTION_ADDR, tmp);
+			udc->addr = tmp;
+			return;
+		}
+		break;
+
+	case USB_REQ_GET_STATUS:
+		dbg("USB_REQ_GET_STATUS ...");
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (udc->req_std) {
+			if (ak980x_udc_get_status(udc, &crq)) {
+				return;
+			}
+		}
+		break;
+
+	case USB_REQ_CLEAR_FEATURE:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (crq.bRequestType != USB_RECIP_ENDPOINT)
+			break;
+
+		if (crq.wValue != USB_ENDPOINT_HALT || crq.wLength != 0)
+			break;
+
+		ak980x_ep_set_halt(&udc->ep[crq.wIndex & 0x7f].ep, 0);
+		udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3);
+		
+		return;
+
+	case USB_REQ_SET_FEATURE:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (crq.bRequestType != USB_RECIP_ENDPOINT)
+			break;
+
+		if (crq.wValue != USB_ENDPOINT_HALT || crq.wLength != 0)
+			break;
+
+		ak980x_ep_set_halt(&udc->ep[crq.wIndex & 0x7f].ep, 1);
+		udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3);
+		return;
+
+	default:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+		break;
+	}
+
+	if (crq.bRequestType & USB_DIR_IN)
+		udc->ep0state = EP0_IN_DATA_PHASE;
+	else
+		udc->ep0state = EP0_OUT_DATA_PHASE;
+	
+	ret = udc->driver->setup(&udc->gadget, &crq);
+	if (ret < 0) {
+		if (udc->req_config) {
+			dbg("config change %02x fail %d?",
+				crq.bRequest, ret);
+			return;
+		}
+
+		if (ret == -EOPNOTSUPP)
+			dbg("Operation not supported");
+		else
+			dbg("udc->driver->setup failed. (%d)", ret);
+		
+		udc_writeb(USB_CTRL_1, 1<<5);
+		udc_writeb(USB_CTRL_1, 1<<3 | 1<<6);
+		udc->ep0state = EP0_IDLE;
+		/* deferred i/o == no response yet */
+	} else if (udc->req_pending) {
+		dbg("dev->req_pending... what now?");
+		udc->req_pending=0;
+	}
+
+	dbg("ep0state %s", ep0states[udc->ep0state]);
+}
+
+static void handle_ep0(struct ak980x_udc *udc)
+{
+	int csr, error = 0;
+	struct ak980x_ep *ep0 = &udc->ep[0];
+	struct ak980x_request *req = NULL;
+
+	if (!list_empty(&ep0->queue)) 
+		req = list_entry(ep0->queue.next, struct ak980x_request, queue);
+	
+	udc_writeb(USB_EP_INDEX, 0);
+	csr = udc_readb(USB_CTRL_1);
+	dbg("csr(0x%x)", csr);
+
+	if (csr & 0x1<<3) {
+		dbg("data end");
+	} 
+	if (csr & 0x1<<4) {
+		dbg("A control transaction ends before the DataEnd bit has been set");
+		udc_writeb(USB_CTRL_1, 0x1<<7);
+		/* do something else? */
+		udc->ep0state = EP0_IDLE;
+		error = 1;
+	}
+	if (csr & 0x1<<2) {
+		udc_writeb(USB_CTRL_1, udc_readb(USB_CTRL_1) & ~(1 << 2));
+		udc->ep0state = EP0_IDLE;
+		error = 1;
+	}
+	switch (udc->ep0state) {
+	case EP0_IDLE:
+		ak980x_udc_handle_ep0_idle(udc, ep0, csr);
+		break;
+
+	case EP0_IN_DATA_PHASE:			/* GET_DESCRIPTOR etc */
+		dbg("EP0_IN_DATA_PHASE ... what now?");
+		if (!(csr & (1<<1)) && req && error == 0)
+			write_ep0_fifo(ep0, req);
+		break;
+
+	case EP0_OUT_DATA_PHASE:		/* SET_DESCRIPTOR etc */
+		dbg("EP0_OUT_DATA_PHASE ... what now?");
+		if ((csr & (1<<0)) && req)
+			read_ep0_fifo(ep0, req);
+		break;
+
+	case EP0_END_XFER:
+		dbg("EP0_END_XFER ... what now?");
+		udc->ep0state = EP0_IDLE;
+		break;
+
+	case EP0_STALL:
+		dbg("EP0_STALL ... what now?");
+		udc->ep0state = EP0_IDLE;
+		break;
+	}
+}
+
+/* not ep0 */
+static void handle_ep(struct ak980x_ep *ep)
+{
+	struct ak980x_request *req;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned int csr;
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next,
+			struct ak980x_request, queue);
+	else {
+		dbg("%s: no req waiting", ep->ep.name);
+		req = NULL;
+	}
+	
+	if (!strcmp(ep->ep.name, udc->ep[1].ep.name)) { /* ep1 */ 
+		dbg("ep1");
+	} else if (ep->is_in) { /* ep2 or ep4*/ 
+
+		if (!strcmp(ep->ep.name, udc->ep[2].ep.name))
+			udc_writeb(USB_EP_INDEX, 2);
+		else
+			udc_writeb(USB_EP_INDEX, 4);
+
+		csr = udc_readb(USB_CTRL_1);
+		dbg("ep2 or ep4 csr(0x%x), req(0x%p)", csr, req);
+
+                /*
+		 * if ((csr & 0x1) && req) {
+		 *         write_ep2_fifo(ep, req);
+		 * }
+                 */
+		/* udc_writeb(USB_CTRL_1, 0x1); */
+		if (csr & 0x1<<2) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<2));
+		}
+		if (csr & 0x1<<5) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<5));
+			return;
+		}
+
+		if (req) {
+			if (ep->done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					req = list_entry(ep->queue.next, struct ak980x_request, queue);
+					if ((csr & 1) == 0)
+						queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				if ((csr & 1) == 0)
+					queue_work(ep_wqueue, &ep->work);
+			}
+
+		}
+	} else { /* ep3 or ep 5*/ 
+		if (!strcmp(ep->ep.name, udc->ep[3].ep.name))
+			udc_writeb(USB_EP_INDEX, 3);
+		else
+			udc_writeb(USB_EP_INDEX, 5);
+
+		csr = udc_readb(USB_CTRL_2);
+		dbg("ep3 or ep5 csr(0x%x)", csr);
+
+		if (csr & 0x1<<6) {
+			udc_writeb(USB_CTRL_2, csr & ~(0x1<<6));
+		}
+		if (req && (csr & 0x1<<0))
+			queue_work(ep_wqueue, &ep->work);
+	}
+}
+
+static void udc_disconnect(struct ak980x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i;
+
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+		struct ak980x_request *req;
+
+		ep->stopped = 1;
+
+		// terminer chaque requete dans la queue
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+			done(ep, req, -ESHUTDOWN);
+		}
+	}
+
+	if (driver)
+		driver->disconnect(&udc->gadget);
+
+	udc_reinit(udc);
+}
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+static void ak98_udc_fun(void *data)
+{
+	struct ak980x_udc *udc = data;
+	
+	msleep(500);
+
+	clk_enable(udc->clk);
+	rMULFUN_CON1 &= ~0x7;
+	rMULFUN_CON1 |= 0x6;
+}
+#endif
+	
+static void udc_reset(struct ak980x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i ,temp;
+
+	//printk("%x\n", udc_readb(USB_INTERRUPT_USB)); /* ep0 */ 
+#ifdef USB_11
+	udc_writeb(USB_POWER_CTRL, 0);
+	udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) | 0x1);
+#else
+	udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) & (~0x1));
+	udc_writeb(USB_POWER_CTRL, 0x1<<5);
+#endif
+
+	udc_writeb(USB_FUNCTION_ADDR, 0);
+	udc_writeb(USB_INTERRUPT_USB, ~(0x1<<3));
+	udc_writeb(USB_INTERRUPT_TX, 0x1<<0); /* ep0 */ 
+	
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	temp = udc_readw(USB_INTERRUPT_COMM);
+	temp = udc_readw(USB_INTERRUPT_1);
+	temp = udc_readw(USB_INTERRUPT_2);
+
+	udc->ep0state = EP0_IDLE;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+		struct ak980x_request *req;
+
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+			done(ep, req, -ECONNRESET);
+		}
+	}
+}
+
+static irqreturn_t udc_irqhandler(int irq, void *_udc)
+{
+	struct ak980x_udc *udc = _udc;
+	short status_1, status_2;
+	char status_int;
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (start == 0) {
+		start = 1;
+		rMULFUN_CON1 &= ~0x7;
+		clk_disable(udc->clk);
+		reset_usbcontroller();
+		printk("ak98_request_hold_mode NORMAL_MODE_CLOCK_5\n");
+		ak98_request_hold_mode(NORMAL_MODE_CLOCK_5, ak98_udc_fun, udc);
+		return IRQ_HANDLED;
+	}
+#endif
+
+	status_int = udc_readb(USB_INTERRUPT_COMM);
+	if (status_int & 0x1<<2) {
+		/* dbg("status_int(0x%x), reset", status_int);	 */
+		printk("\n\nstatus_int(0x%x), reset\n\n", status_int);
+		if (usb_detect) {
+			usb_exist = 1;
+			usb_detect = 0;
+			if (!udc->driver) {
+				panic("If you see this, come to find Zhang Jingyuan\n");
+				udc_enable(udc, 0);
+				return IRQ_HANDLED;
+			}
+		}
+#ifdef USB_11
+		udc->gadget.speed = USB_SPEED_FULL;
+#else
+		udc->gadget.speed = USB_SPEED_HIGH;
+#endif
+		udc_reset(udc);
+		goto done;
+	} else if(status_int & 0x1<<1) { /* resume */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("resume");
+		goto done;
+	} else if(status_int & 0x1<<0) { /* suspend */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("suspend");
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+		if (start == 1) {
+			start = 0;
+			printk("ak98_release_hold_mode NORMAL_MODE_CLOCK_5\n");
+			ak98_release_hold_mode(NORMAL_MODE_CLOCK_5);
+		}
+#endif
+		udc_disconnect(udc);
+		goto done;
+	}
+
+	status_1 = udc_readb(USB_INTERRUPT_1);
+	status_2 = udc_readb(USB_INTERRUPT_2);
+	dbg("status_int(0x%x), status_1(0x%x), status_2(0x%x)", status_int, status_1, status_2);
+	if (status_1 & 0x1<<0) {
+		handle_ep0(udc);
+	}
+	if (status_1 & 0x1<<2) {
+		dbg("endpoint2");
+		handle_ep(&udc->ep[2]);
+	}
+	if (status_1 & 0x1<<4) {
+		dbg("endpoint4");
+		handle_ep(&udc->ep[4]);
+	}
+
+	if (status_2 & 0x1<<1) {
+		dbg("endpoint 1");
+		handle_ep(&udc->ep[1]);
+	}
+	if (status_2 & 0x1<<3) {
+		dbg("endpoint3");
+		handle_ep(&udc->ep[3]);
+	}
+	if (status_2 & 0x1<<5) {
+		dbg("endpoint5");
+		handle_ep(&udc->ep[5]);
+	}
+
+done:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t udc_dmahandler(int irq, void *_udc)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = _udc;
+	struct ak980x_ep *ep;
+	unsigned int is_done = 0;
+
+	u32 usb_dma_int = udc_readl(USB_DMA_INTR);
+	
+	if ((usb_dma_int & DMA_CHANNEL1_INT) == DMA_CHANNEL1_INT) {
+		ep = &udc->ep[2];
+		udc_writeb(USB_EP_INDEX, USB_EP2_INDEX);
+		udc_writeb(USB_CTRL_1_2, USB_TXCSR_MODE1);
+        udc_writel(USB_DMA_CTRL1, 0);
+
+        ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_tx == req->req.length - req->req.actual && !req->req.zero) 
+				is_done = 1;
+			req->req.actual += dma_tx;
+			ep->done = is_done;
+			if (is_done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				queue_work(ep_wqueue, &ep->work);
+			}
+			dma_unmap_single(NULL, phys_tx, dma_tx, DMA_TO_DEVICE);
+			dma_tx = 0;
+
+			req->status = is_done;
+		}
+		else
+			dbg("something happend");
+	}
+	
+	if ((usb_dma_int & DMA_CHANNEL2_INT) == DMA_CHANNEL2_INT) {
+		ep = &udc->ep[3];
+
+		udc_writeb(USB_EP_INDEX, USB_EP3_INDEX);
+		udc_writeb(USB_CTRL_2_2, 0);
+		udc_writel(USB_DMA_CTRL2, 0);
+		
+		ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		req = NULL;
+		is_done = 0;
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_rx == req->req.length - req->req.actual)
+				is_done = 1;
+			req->req.actual += dma_rx;
+			ep->done = is_done;
+			if (is_done)
+				done(ep, req, 0);
+			dma_unmap_single(NULL, phys_rx, dma_rx, DMA_FROM_DEVICE);
+			req->status = is_done;
+			dma_rx = 0;
+
+			flag = 0;
+		}
+		else
+			dbg("something happend");
+	}
+
+	if ((usb_dma_int & DMA_CHANNEL3_INT) == DMA_CHANNEL3_INT) {
+		ep = &udc->ep[4];
+		udc_writeb(USB_EP_INDEX, USB_EP4_INDEX);
+		udc_writeb(USB_CTRL_1_2, USB_TXCSR_MODE1);
+        udc_writel(USB_DMA_CTRL1, 0);
+
+        ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_tx == req->req.length - req->req.actual && !req->req.zero) 
+				is_done = 1;
+			req->req.actual += dma_tx;
+			ep->done = is_done;
+			if (is_done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				queue_work(ep_wqueue, &ep->work);
+			}
+			dma_unmap_single(NULL, phys_tx, dma_tx, DMA_TO_DEVICE);
+			dma_tx = 0;
+
+			req->status = is_done;
+		}
+		else
+			dbg("something happend");
+	}
+	
+	if ((usb_dma_int & DMA_CHANNEL4_INT) == DMA_CHANNEL4_INT) {
+		ep = &udc->ep[5];
+
+		udc_writeb(USB_EP_INDEX, USB_EP5_INDEX);
+		udc_writeb(USB_CTRL_2_2, 0);
+		udc_writel(USB_DMA_CTRL2, 0);
+		
+		ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		req = NULL;
+		is_done = 0;
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_rx == req->req.length - req->req.actual)
+				is_done = 1;
+			req->req.actual += dma_rx;
+			ep->done = is_done;
+			if (is_done)
+				done(ep, req, 0);
+			dma_unmap_single(NULL, phys_rx, dma_rx, DMA_FROM_DEVICE);
+			req->status = is_done;
+			dma_rx = 0;
+
+			flag = 0;
+		}
+		else
+			dbg("something happend");
+	}
+
+	return IRQ_HANDLED;
+}
+
+void udc_enable(struct ak980x_udc *udc, int enable)
+{
+	if (enable) {
+		reset_usbcontroller();
+		clk_enable(udc->clk);
+		rMULFUN_CON1 &= ~0x7;
+		rMULFUN_CON1 |= 6;
+#ifdef USB_11
+		udc_writeb(USB_POWER_CTRL, 0);
+		udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) | 0x1);
+#else
+		udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) & (~0x1));
+		udc_writeb(USB_POWER_CTRL, 0x1<<5);
+#endif
+
+	} else {
+		rMULFUN_CON1 &= ~0x7;
+		clk_disable(udc->clk);
+		reset_usbcontroller();
+	}
+}
+
+int usb_gadget_register_driver (struct usb_gadget_driver *driver)
+{
+	struct ak980x_udc	*udc = &controller;
+	int		retval;
+
+	if (!driver
+			|| driver->speed < USB_SPEED_FULL
+			|| !driver->bind
+			|| !driver->setup) {
+		dbg("bad parameter.\n");
+		return -EINVAL;
+	}
+
+	if (udc->driver) {
+		dbg("UDC already has a gadget driver\n");
+		return -EBUSY;
+	}
+
+	udc->driver = driver;
+	udc->gadget.dev.driver = &driver->driver;
+
+	retval = driver->bind(&udc->gadget);
+	if (retval) {
+		dbg("driver->bind() returned %d\n", retval);
+		udc->driver = NULL;
+		udc->gadget.dev.driver = NULL;
+
+		return retval;
+	}
+
+	//local_irq_disable();
+	disable_irq(udc->mcu_irq);
+	udc_enable(udc, 1);
+	//local_irq_enable();
+	enable_irq(udc->mcu_irq);
+
+	dbg("bound to %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
+{
+	struct ak980x_udc *udc = &controller;
+
+	if (!driver || driver != udc->driver || !driver->unbind)
+		return -EINVAL;
+	
+	driver->unbind(&udc->gadget);
+	udc->gadget.dev.driver = NULL;
+	//udc->gadget.dev.driver_data = NULL;
+	udc->driver = NULL;
+	
+	//local_irq_disable();
+	disable_irq(udc->mcu_irq);
+	
+	cancel_work_sync(&udc->ep[2].work);
+	cancel_work_sync(&udc->ep[3].work);
+	cancel_work_sync(&udc->ep[4].work);
+	cancel_work_sync(&udc->ep[5].work);
+
+	flush_workqueue(ep_wqueue);
+	
+	udc_enable(udc, 0);
+	//local_irq_enable();
+	enable_irq(udc->mcu_irq);
+
+	dbg("unbound from %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL (usb_gadget_unregister_driver);
+
+static void udc_reinit(struct ak980x_udc *udc)
+{
+	u32 i;
+
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+	INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
+	udc->ep0state = EP0_IDLE;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+
+		if (i != 0)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+		ep->desc = NULL;
+		/* ep->stopped = 0; */
+		ep->stopped = 0;
+		ep->ep.maxpacket = ep->maxpacket;
+		// initialiser une queue par endpoint
+		INIT_LIST_HEAD(&ep->queue);
+	}
+}
+
+static int __init ak980x_udc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ak980x_udc *udc = &controller;
+	struct resource	*res;
+	int retval;
+
+	if (pdev->num_resources < 2) {
+		dbg("invalid num_resources\n");
+		return -ENODEV;
+	}
+	if ((pdev->resource[0].flags != IORESOURCE_MEM)
+			|| (pdev->resource[1].flags != IORESOURCE_IRQ)) {
+		dbg("invalid resource type\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	if (!request_mem_region(res->start,
+			res->end - res->start + 1,
+			driver_name)) {
+		dbg("someone's using UDC memory\n");
+		return -EBUSY;
+	}
+
+	udc->baseaddr = ioremap_nocache(res->start, res->end - res->start + 1);
+	if (!udc->baseaddr) {
+		retval = -ENOMEM;
+		goto fail0a;
+	}
+	/* init software state */
+	udc->gadget.dev.parent = dev;
+
+	udc_reinit(udc);
+
+	/* get interface and function clocks */
+	udc->clk = clk_get(dev, "udc_clk");
+	if (IS_ERR(udc->clk)) {
+		dbg("clocks missing\n");
+		retval = -ENODEV;
+		/* NOTE: we "know" here that refcounts on these are NOPs */
+		goto fail0b;
+	}
+
+	retval = device_register(&udc->gadget.dev);
+	if (retval < 0)
+		goto fail0b;
+
+	ep_wqueue = create_workqueue("ak980x_udc");
+	/* request UDC and maybe VBUS irqs */
+	udc->mcu_irq = platform_get_irq(pdev, 0);
+
+	reset_usbcontroller();
+	retval = request_irq(udc->mcu_irq, udc_irqhandler,
+			IRQF_DISABLED, driver_name, udc);
+	if (retval < 0) {
+		dbg("request irq %d failed\n", udc->mcu_irq);
+		goto fail1;
+	}
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* request DMA irqs */
+	udc->dma_irq = platform_get_irq(pdev, 1);
+	retval = request_irq(udc->dma_irq, udc_dmahandler,
+			IRQF_DISABLED, driver_name, udc);
+	if (retval < 0) {
+		dbg("request irq %d failed\n", udc->dma_irq);
+		goto fail1;
+	}
+#endif
+#endif
+
+	platform_set_drvdata(pdev, udc);
+
+	dbg("Build at %s %s", __DATE__, __TIME__);
+
+	/* for g_serial.ko */
+	//udc->ep[2].bufaddr = dma_alloc_coherent(NULL, 16384, &udc->ep[2].bufphys, DMA_TO_DEVICE);
+	//udc->ep[3].bufaddr = dma_alloc_coherent(NULL, 16384, &udc->ep[3].bufphys, DMA_FROM_DEVICE);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* USB slave L2 buffer initialization */
+	udc->ep[2].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP2);
+	udc->ep[3].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP3);
+	udc->ep[4].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP4);
+	udc->ep[5].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP5);
+#endif
+#endif
+
+	INIT_WORK(&udc->ep[2].work, ep2_work);
+	INIT_WORK(&udc->ep[3].work, ep3_work);
+	INIT_WORK(&udc->ep[4].work, ep4_work);
+	INIT_WORK(&udc->ep[5].work, ep5_work);
+
+	return 0;
+
+	free_irq(udc->mcu_irq, udc);
+fail1:
+	device_unregister(&udc->gadget.dev);
+fail0b:
+	iounmap(udc->baseaddr);
+fail0a:
+	release_mem_region(res->start, res->end - res->start + 1);
+	dbg("%s probe failed, %d\n", driver_name, retval);
+	
+	return retval;
+}
+
+static int __exit ak980x_udc_remove(struct platform_device *pdev)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+	struct resource *res;
+
+	if (udc->driver)
+		return -EBUSY;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	free_irq(udc->dma_irq, udc);
+#endif
+#endif
+	free_irq(udc->mcu_irq, udc);
+	device_unregister(&udc->gadget.dev);
+
+	destroy_workqueue(ep_wqueue);
+
+	iounmap(udc->baseaddr);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* USB slave L2 buffer initialization */
+	ak98_l2_free(ADDR_USB_EP2);
+	ak98_l2_free(ADDR_USB_EP3);
+	ak98_l2_free(ADDR_USB_EP4);
+	ak98_l2_free(ADDR_USB_EP5);
+#endif
+#endif
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res->end - res->start + 1);
+
+	return 0;
+}
+
+static void ak980x_udc_shutdown(struct platform_device *dev)
+{
+}
+
+#ifdef CONFIG_PM
+static int ak980x_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+
+	cancel_work_sync(&udc->ep[2].work);
+	cancel_work_sync(&udc->ep[3].work);
+	cancel_work_sync(&udc->ep[4].work);
+	cancel_work_sync(&udc->ep[5].work);
+
+	flush_workqueue(ep_wqueue);
+
+	rMULFUN_CON1 &= ~0x7;
+		
+	clk_disable(udc->clk);
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+		if (start == 1) {
+			start = 0;
+			printk("ak98_release_hold_mode2 NORMAL_MODE_CLOCK_5\n");
+			ak98_release_hold_mode(NORMAL_MODE_CLOCK_5);
+		}
+#endif
+	
+	reset_usbcontroller();
+	
+	udc_disconnect(udc);
+	
+	return 0;
+}
+
+static int ak980x_udc_resume(struct platform_device *pdev)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+
+	/* something to do */
+	clk_enable(udc->clk);
+
+	rMULFUN_CON1 &= ~0x7;
+	rMULFUN_CON1 |= 0x6;
+	
+	return 0;
+}
+#else
+#define	ak980x_udc_suspend	NULL
+#define	ak980x_udc_resume	NULL
+#endif
+
+static struct platform_driver ak980x_udc_driver = {
+	.remove		= __exit_p(ak980x_udc_remove),
+	.shutdown	= ak980x_udc_shutdown,
+	.suspend	= ak980x_udc_suspend,
+	.resume		= ak980x_udc_resume,
+	.driver		= {
+		.name	= (char *) driver_name,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init udc_init_module(void)
+{
+	printk("AK980X UDC Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_probe(&ak980x_udc_driver, ak980x_udc_probe);
+}
+module_init(udc_init_module);
+
+static void __exit udc_exit_module(void)
+{
+	platform_driver_unregister(&ak980x_udc_driver);
+}
+module_exit(udc_exit_module);
+
+MODULE_DESCRIPTION("AK980X udc driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak980x_udc");
diff --git a/drivers/usb/gadget/ak98-udc/ak98_udc.h b/drivers/usb/gadget/ak98-udc/ak98_udc.h
new file mode 100644
index 00000000000..cff5d08ec8d
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_udc.h
@@ -0,0 +1,184 @@
+#ifndef _AK98_UDC_H
+#define _AK98_UDC_H
+
+/* ak980x usb register */
+#define USB_FUNCTION_ADDR	0x0
+#define USB_POWER_CTRL		0x1
+#define USB_INTERRUPT_1		0x2
+#define USB_INTERRUPT_2		0x4
+#define USB_INTERRUPT_TX	0x6
+#define USB_INTERRUPT_RX	0x8
+#define USB_INTERRUPT_COMM	0xA
+#define USB_INTERRUPT_USB	0xB
+#define USB_FRAME_NUM		0xC
+#define USB_EP_INDEX		0xE
+#define USB_TEST_MODE		0xF
+#define USB_TX_MAX			0x10
+#define USB_CTRL_1			0x12
+#define USB_CTRL_1_2		0x13
+#define USB_RX_MAX			0x14
+#define USB_CTRL_2			0x16
+#define USB_CTRL_2_2		0x17
+#define USB_EP_COUNT		0x18
+#define USB_CFG_INFO		0x1F
+#define USB_EP0_FIFO		0x20
+#define USB_EP1_FIFO		0x24
+#define USB_EP2_FIFO		0x28
+#define USB_EP3_FIFO		0x2C
+#define USB_EP4_FIFO		0x30
+#define USB_EP5_FIFO		0x34
+#define USB_DEVICE_CTRL		0x60
+#define USB_DMA_INTR		0x200
+#define USB_DMA_CTRL1		0x204
+#define USB_DMA_CTRL2		0x214
+#define USB_DMA_CTRL3		0x224
+#define USB_DMA_CTRL4		0x234
+#define USB_DMA_ADDR1		0x208
+#define USB_DMA_ADDR2		0x218
+#define USB_DMA_ADDR3		0x228
+#define USB_DMA_ADDR4		0x238
+#define USB_DMA_COUNT1		0x20C
+#define USB_DMA_COUNT2		0x21C
+#define USB_DMA_COUNT3		0x22C
+#define USB_DMA_COUNT4		0x23C
+#define USB_EP0_NUM			0x330
+#define USB_EP2_NUM			0x334
+#define USB_MODE_STATUS		0x344
+
+#define USB_ENABLE_DMA              (1)
+#define USB_DIRECTION_RX            (0<<1)
+#define USB_DIRECTION_TX            (1<<1)
+#define USB_DMA_MODE1               (1<<2)
+#define USB_DMA_MODE0               (0<<2)
+#define USB_DMA_INT_ENABLE          (1<<3)
+#define USB_DMA_INT_DISABLE         (0<<3)
+#define USB_DMA_BUS_ERROR           (1<<8)
+#define USB_DMA_BUS_MODE0           (0<<9)
+#define USB_DMA_BUS_MODE1           (1<<9)
+#define USB_DMA_BUS_MODE2           (2<<9)
+#define USB_DMA_BUS_MODE3           (3<<9)
+#define DMA_CHANNEL1_INT          	(1)
+#define DMA_CHANNEL2_INT          	(2)
+#define DMA_CHANNEL3_INT          	(4)
+#define DMA_CHANNEL4_INT          	(8)
+#define USB_EP0_INDEX             	(0)
+#define USB_EP1_INDEX             	(1 << 0)
+#define USB_EP2_INDEX             	(1 << 1)
+#define USB_EP3_INDEX             	((1 << 1)|(1 << 0))
+#define USB_EP4_INDEX             	(1 << 2)
+#define USB_EP5_INDEX             	((1 << 2)|(1 << 0))
+#define USB_EP6_INDEX             	((1 << 2)|(1 << 1))
+
+// #define USB_11 [> usb1.1 <]   
+
+#define EP1_FIFO_SIZE		64 /* interrupt */ 
+//#define EP4_FIFO_SIZE		512 /* iso */ 
+#ifdef USB_11 /* USB_SPEED_FULL */ 
+#define EP0_FIFO_SIZE		16  /* control, not 64byte? */ 
+#define EP2_FIFO_SIZE		64 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		64 /* ep3 out bulk */ 
+#define EP4_FIFO_SIZE		64 /* ep4 in bulk */ 
+#define EP5_FIFO_SIZE		64 /* ep5 out bulk */ 
+#else /* USB_SPEED_HIGH */ 
+#define EP0_FIFO_SIZE		64  /* control, not 64byte? */ 
+#define EP2_FIFO_SIZE		512 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		512 /* ep3 out bulk */ 
+#define EP4_FIFO_SIZE		512 /* ep4 in bulk */ 
+#define EP5_FIFO_SIZE		512 /* ep5 out bulk */ 
+#endif
+
+#define EP0_L2_ADDR		(AK98_VA_L2MEM + 0x1500) /* L2 buffer17 for otg control transfer */
+
+#define USB_TXCSR_AUTOSET          	(0x80)
+#define USB_TXCSR_ISO              	(0x40)
+#define USB_TXCSR_MODE1            	(0x20)
+#define USB_TXCSR_DMAREQENABLE     	(0x10)
+#define USB_TXCSR_FRCDATATOG       	(0x8)
+#define USB_TXCSR_DMAREQMODE1      	(0x4)
+#define USB_TXCSR_DMAREQMODE0      	(0x0)
+
+struct ak980x_request;
+
+struct ak980x_ep {
+	struct usb_ep		ep;
+	struct usb_gadget	*gadget;
+	struct usb_endpoint_descriptor *desc;
+
+	struct list_head	queue;
+
+	struct work_struct	work;
+	struct ak980x_request	*req; /* req be about to handle */ 
+
+	struct ak980x_udc	*udc;
+	int			maxpacket;
+	volatile int		done;
+	unsigned int		bufaddr;
+	dma_addr_t		bufphys;
+
+	unsigned		irq_enable;
+	volatile unsigned	stopped;
+	// unsigned		stopped:1;
+	unsigned		is_in:1;
+	unsigned		is_iso:1;
+	// unsigned		fifo_bank:1;
+	u8			l2_buf_id;
+};
+
+struct ak980x_request {
+	struct list_head	queue;		/* ep's requests */
+	struct usb_request	req;
+	int			status;
+};
+
+enum ep0_status {
+        EP0_IDLE,
+        EP0_IN_DATA_PHASE,
+        EP0_OUT_DATA_PHASE,
+        EP0_END_XFER,
+        EP0_STALL,
+};
+
+static const char *ep0states[]= {
+        "EP0_IDLE",
+        "EP0_IN_DATA_PHASE",
+        "EP0_OUT_DATA_PHASE",
+        "EP0_END_XFER",
+        "EP0_STALL",
+};
+
+struct usb_l2 {
+	void *buf;
+	dma_addr_t phys;
+};
+
+static const char * const ep_name[] = {
+	"ep0", "ep1-int", "ep2in-bulk", "ep3out-bulk", "ep4in-bulk", "ep5out-bulk",
+};
+
+#define ENDPOINTS_NUM ARRAY_SIZE(ep_name)
+
+struct ak980x_udc {
+	struct usb_gadget		gadget;
+	struct usb_gadget_driver	*driver;
+
+	struct ak980x_ep	ep[ENDPOINTS_NUM];
+	enum ep0_status		ep0_status;
+
+	void __iomem		*baseaddr;
+
+	unsigned int	mcu_irq;
+	unsigned int	dma_irq;
+	struct clk	*clk;
+	char		addr;   /* assigned device address */ 
+	u16			devstatus;
+	int			ep0state;
+	unsigned			req_std : 1;
+	unsigned			req_config : 1;
+	unsigned			req_pending : 1;
+};
+
+static void udc_reinit(struct ak980x_udc *udc);
+static void udc_enable(struct ak980x_udc *udc, int enable);
+static void done(struct ak980x_ep *ep, struct ak980x_request *req, int status);
+
+#endif
diff --git a/drivers/usb/gadget/ak98-udc/ak98_udc_full.c b/drivers/usb/gadget/ak98-udc/ak98_udc_full.c
new file mode 100644
index 00000000000..8a6c7d91799
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_udc_full.c
@@ -0,0 +1,2151 @@
+/*
+ * ak980x_udc -- driver for ak980x USB peripheral controller
+ * Features
+ * The USB 2.0 HS OTG has following features:
+ *      •   compliant with USB Specification Version 2.0 (HS) and On-The-Go supplement to
+ *	  the USB 2.0 specification
+ *      •   operating as the host in point-to-point communications with another USB function
+ *	  or as a function controller for a USB peripheral
+ *      •   supporting UTMI+ Level 2 Transceiver Interface
+ *      •   4 Transmit/Receive endpoints in addition to Endpoint 0
+ *      •   3 DMA channels
+ * AUTHOR ANYKA Zhang Jingyuan
+ * 09-11-14 10:45:03
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/proc_fs.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/workqueue.h>
+#include <linux/dma-mapping.h>
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+#include <linux/ak98_freq_policy.h>
+#endif
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/gpio.h>
+#include <asm/dma-mapping.h>
+
+#include <mach/regs-comm.h>
+#include <mach/l2.h>
+
+#include "ak98_udc_full.h"
+
+#define AK98_UDC_EPS 5
+
+
+#if 0
+#define dbg(fmt, arg...) printk("%s(%d): " fmt "\n", __func__, __LINE__, ##arg)
+#else
+#define dbg(fmt, arg...)
+#endif
+
+static const char ep0name[] = "ep0";
+static const char driver_name[] = "ak98_udc";
+
+#define udc_readb(reg)	__raw_readb(udc->baseaddr + (reg))
+#define udc_readw(reg)	__raw_readw(udc->baseaddr + (reg))
+#define udc_readl(reg)	__raw_readl(udc->baseaddr + (reg))
+#define udc_writeb(reg, val) __raw_writeb(val, udc->baseaddr + (reg))
+#define udc_writew(reg, val) __raw_writew(val, udc->baseaddr + (reg))
+#define udc_writel(reg, val) __raw_writel(val, udc->baseaddr + (reg))
+
+static struct ak980x_udc controller;
+/* static struct ak980x_udc *udc = &controller; */
+struct workqueue_struct *ep_wqueue;
+
+volatile int usb_detect;
+volatile int usb_exist;
+EXPORT_SYMBOL(usb_detect);
+EXPORT_SYMBOL(usb_exist);
+
+unsigned int dma_rx;
+unsigned int dma_tx;
+dma_addr_t phys_rx;
+dma_addr_t phys_tx;
+
+static volatile char flag = 0;
+static u32 start = 0;
+
+static void ep_irq_enable(struct usb_ep *_ep)
+{
+	static struct ak980x_udc *udc = &controller;
+	
+	if (strcmp(_ep->name, udc->ep[1].ep.name))
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<1));
+
+	if (strcmp(_ep->name, udc->ep[2].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<2));
+	
+	if (strcmp(_ep->name, udc->ep[3].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<3));
+
+	if (strcmp(_ep->name, udc->ep[4].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) | (0x1<<4));
+	
+	if (strcmp(_ep->name, udc->ep[5].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) | (0x1<<5));
+}
+
+static void ep_irq_disable(struct usb_ep *_ep)
+{
+	static struct ak980x_udc *udc = &controller;
+	
+	if (strcmp(_ep->name, udc->ep[1].ep.name))
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<1));
+
+	if (strcmp(_ep->name, udc->ep[2].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<2));
+	
+	if (strcmp(_ep->name, udc->ep[3].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<3));
+
+	if (strcmp(_ep->name, udc->ep[4].ep.name)) 
+		udc_writew(USB_INTERRUPT_TX, udc_readw(USB_INTERRUPT_TX) & ~(0x1<<4));
+	
+	if (strcmp(_ep->name, udc->ep[5].ep.name)) 
+		udc_writew(USB_INTERRUPT_RX, udc_readw(USB_INTERRUPT_RX) & ~(0x1<<5));
+}
+
+static inline void reset_usbcontroller(void)
+{
+	rCLK_CON1 |= (0x1<<31);
+	rCLK_CON1 &= ~(0x1<<31);
+}
+
+static void done(struct ak980x_ep *ep, struct ak980x_request *req, int status)
+{
+	unsigned	 stopped = ep->stopped;
+	//struct ak980x_udc *udc = ep->udc;
+
+	list_del_init(&req->queue);
+
+	if (likely (req->req.status == -EINPROGRESS))
+		req->req.status = status;
+	else
+		status = req->req.status;
+
+	ep->stopped = 1;
+	req->req.complete(&ep->ep, &req->req);
+	ep->stopped = stopped;
+
+	dbg("%s done, req.status(%d)", ep->ep.name, req->req.status);
+}
+
+static int write_ep0_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	int i;
+	unsigned total, count, is_last;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+
+	total = req->req.length - req->req.actual;
+
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count < ep->ep.maxpacket) || !req->req.zero;
+	}
+
+	dbg("is_last(%d), count(%d), total(%d), actual(%d), length(%d)", 
+			is_last, count, total, req->req.actual, req->req.length);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	if (count == 0) {
+		dbg(" count == 0 ");
+		udc_writel(USB_EP0_NUM, count&0x7f);
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+		return 1;
+	}
+
+	buf = req->req.buf + req->req.actual;
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP0_FIFO, buf[i]);
+
+	udc_writel(USB_EP0_NUM, count&0x7f); /* 7bits */ 
+	if (is_last) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+	} else {
+		udc_writeb(USB_CTRL_1, 0x1<<1);
+	}
+
+	req->req.actual += count;
+	if (is_last) {
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+	}
+
+	ep->done = is_last;
+	return is_last;
+	/* return 1; */
+}
+
+static int read_ep0_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	int i;
+	unsigned total, count, is_last;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+
+	total = req->req.length - req->req.actual;
+
+	if (ep->ep.maxpacket < total) {
+		count = ep->ep.maxpacket;
+		is_last = 0;
+	} else {
+		count = total;
+		is_last = (count < ep->ep.maxpacket) || !req->req.zero;
+	}
+
+	dbg("is_last(%d), count(%d), total(%d), actual(%d), length(%d)", 
+			is_last, count, total, req->req.actual, req->req.length);
+
+	udc_writeb(USB_EP_INDEX, 0);
+	if (count == 0) {
+		dbg(" count == 0 ");
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+		return 1;
+	}
+
+	buf = req->req.buf + req->req.actual;
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP0_FIFO);
+ 
+	if (is_last) {
+		udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+	} else {
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+	}
+
+	req->req.actual += count;
+	if (is_last) {
+		udc->ep0state = EP0_IDLE;
+		done(ep, req, 0);
+	}
+
+	ep->done = is_last;
+	return is_last;
+	/* return 1; */
+}
+
+
+static int write_ep1_fifo(struct ak980x_ep *ep, struct ak980x_request *req)
+{
+	return 1;
+}
+
+static int write_ep2_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep2 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned total, count, is_last;
+	unsigned char *buf;
+	//dma_addr_t phys;
+	int dma = 0, i;
+
+	total = req->req.length - req->req.actual;
+	if (ep->ep.maxpacket <= total) {
+		count = ep->ep.maxpacket;
+		is_last = (total == ep->ep.maxpacket) && !req->req.zero;
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+		dma = 1;
+#endif
+#endif
+	} else {
+		count = total;
+		is_last = count < ep->ep.maxpacket;
+		dma = 0;
+	}
+	dbg("total(%d), count(%d), is_last(%d)", total, count, is_last);
+
+	if (count == 0) { /* not support command */ 
+		dbg("count == 0\n");
+		ep->done = 1;
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1, 0x1);
+		return 0;
+	}
+	udc_writeb(USB_EP_INDEX, 2);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (dma == 1) {
+		dma_tx = total - (total % ep->ep.maxpacket);
+		phys_tx = dma_map_single(NULL, buf, dma_tx, DMA_TO_DEVICE);
+		if (phys_tx == 0) {
+			printk("tx dma_map_single error!\n");
+			goto cpu;
+		}
+
+		udc_writeb(USB_CTRL_1_2, (1<<2) | (1<<4) | (1<<5) | (1<<7));
+		
+		//send data to l2
+		ak98_l2_clr_status(ep->l2_buf_id);
+		ak98_l2_combuf_dma(phys_tx, ep->l2_buf_id, dma_tx, MEM2BUF, false);
+		udc_writel(USB_DMA_ADDR1, 0x70000000);
+		udc_writel(USB_DMA_COUNT1, dma_tx);
+		udc_writel(USB_DMA_CTRL1, (USB_ENABLE_DMA | USB_DIRECTION_TX | USB_DMA_MODE1 | USB_DMA_INT_ENABLE| (USB_EP2_INDEX<<4) | USB_DMA_BUS_MODE3));
+		
+		ep->done = 0;
+		return 0;
+	}
+#endif
+#endif
+
+cpu:
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP2_FIFO, buf[i]);
+
+	udc_writeb(USB_CTRL_1, 0x1);
+
+	req->req.actual += count;
+	/* wait a tx complete int */
+        /*
+	 * if (is_last)
+	 *         done(ep, req, 0);
+         */
+
+	/* return is_last; */
+	ep->done = is_last;
+
+	return 0;
+}
+
+static int read_ep3_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep3 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr, i;
+	unsigned int count, bufferspace, is_done;
+	//dma_addr_t phys;
+
+	if (flag == 1)
+		return 0;
+
+	bufferspace = req->req.length - req->req.actual;
+
+	udc_writeb(USB_EP_INDEX, 3);
+	csr = udc_readb(USB_CTRL_2);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting bulkout data");
+		return 0;
+	}
+
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)",
+				csr, count, bufferspace);
+		dbg("what happened??");
+		goto stall;
+	} else if (count > ep->ep.maxpacket)
+		count = ep->ep.maxpacket;
+
+	if (count > bufferspace) {
+		dbg("%s buffer overflow\n", ep->ep.name);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)", csr, count, bufferspace);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP3_FIFO);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	dma_rx = bufferspace - count;
+	if (dma_rx >= ep->ep.maxpacket) {
+		dma_rx -= (dma_rx % ep->ep.maxpacket);
+		
+		buf = req->req.buf + req->req.actual + count;
+		phys_rx = dma_map_single(NULL, buf, dma_rx, DMA_FROM_DEVICE);
+		if (phys_rx == 0) {
+			printk("rx dma_map_single error!\n");
+			goto stall;
+		}
+
+		req->req.actual += count;
+		flag = 1;
+		udc_writeb(USB_CTRL_2_2, udc_readb(USB_CTRL_2_2) | (1<<3) | (1<<5) | (1<<7));
+		ak98_l2_combuf_dma(phys_rx, ep->l2_buf_id, dma_rx, BUF2MEM, false);
+		udc_writel(USB_DMA_ADDR2, 0x71000000);
+		udc_writel(USB_DMA_COUNT2, dma_rx);
+		udc_writel(USB_DMA_CTRL2, (USB_ENABLE_DMA|USB_DIRECTION_RX|USB_DMA_MODE1|USB_DMA_INT_ENABLE|(USB_EP3_INDEX<<4)|USB_DMA_BUS_MODE3));
+		udc_writeb(USB_EP_INDEX, 3);
+		udc_writeb(USB_CTRL_2, csr & ~0x1);
+		ep->done = 0;
+
+		return 0;
+	}
+#endif
+#endif
+	
+stall:
+	udc_writeb(USB_CTRL_2, csr & ~0x1);
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+
+	ep->done = is_done;
+	if (is_done) {
+		done(ep, req, 0);
+	}
+
+	return is_done;
+}
+
+static int write_ep4_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep4 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned total, count, is_last;
+	unsigned char *buf;
+	//dma_addr_t phys;
+	int dma = 0, i;
+
+	total = req->req.length - req->req.actual;
+	if (ep->ep.maxpacket <= total) {
+		count = ep->ep.maxpacket;
+		is_last = (total == ep->ep.maxpacket) && !req->req.zero;
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+		dma = 1;
+#endif
+#endif
+	} else {
+		count = total;
+		is_last = count < ep->ep.maxpacket;
+		dma = 0;
+	}
+	dbg("total(%d), count(%d), is_last(%d)", total, count, is_last);
+
+	if (count == 0) { /* not support command */ 
+		dbg("count == 0\n");
+		ep->done = 1;
+		udc_writeb(USB_EP_INDEX, 4);
+		udc_writeb(USB_CTRL_1, 0x1);
+		return 0;
+	}
+	udc_writeb(USB_EP_INDEX, 4);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (dma == 1) {
+		dma_tx = total - (total % ep->ep.maxpacket);
+		phys_tx = dma_map_single(NULL, buf, dma_tx, DMA_TO_DEVICE);
+		if (phys_tx == 0) {
+			printk("tx dma_map_single error!\n");
+			goto cpu;
+		}
+
+		udc_writeb(USB_CTRL_1_2, (1<<2) | (1<<4) | (1<<5) | (1<<7));
+		
+		//send data to l2
+		ak98_l2_clr_status(ep->l2_buf_id);
+		ak98_l2_combuf_dma(phys_tx, ep->l2_buf_id, dma_tx, MEM2BUF, false);
+		udc_writel(USB_DMA_ADDR3, 0x72000000);
+		udc_writel(USB_DMA_COUNT3, dma_tx);
+		udc_writel(USB_DMA_CTRL3, (USB_ENABLE_DMA | USB_DIRECTION_TX | USB_DMA_MODE1 | USB_DMA_INT_ENABLE| (USB_EP4_INDEX<<4) | USB_DMA_BUS_MODE3));
+		
+		ep->done = 0;
+		return 0;
+	}
+#endif
+#endif
+
+cpu:
+	for (i = 0; i < count; i++)
+		udc_writeb(USB_EP4_FIFO, buf[i]);
+
+	udc_writeb(USB_CTRL_1, 0x1);
+
+	req->req.actual += count;
+	/* wait a tx complete int */
+        /*
+	 * if (is_last)
+	 *         done(ep, req, 0);
+         */
+
+	/* return is_last; */
+	ep->done = is_last;
+
+	return 0;
+}
+
+static int read_ep5_fifo(struct ak980x_ep *ep, struct ak980x_request *req) /* ep5 */ 
+{
+	struct ak980x_udc *udc = ep->udc;
+	unsigned char *buf;
+	unsigned int csr, i;
+	unsigned int count, bufferspace, is_done;
+	//dma_addr_t phys;
+
+	if (flag == 1)
+		return 0;
+
+	bufferspace = req->req.length - req->req.actual;
+
+	udc_writeb(USB_EP_INDEX, 5);
+	csr = udc_readb(USB_CTRL_2);
+	if ((csr & 0x1) == 0) {
+		dbg("waiting bulkout data");
+		return 0;
+	}
+
+	count = udc_readw(USB_EP_COUNT);
+	if (count == 0) {
+		dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)",
+				csr, count, bufferspace);
+		dbg("what happened??");
+		goto stall;
+	} else if (count > ep->ep.maxpacket)
+		count = ep->ep.maxpacket;
+
+	if (count > bufferspace) {
+		dbg("%s buffer overflow\n", ep->ep.name);
+		req->req.status = -EOVERFLOW;
+		count = bufferspace;
+	}
+	dbg("USB_CTRL_2(0x%x), USB_EP_COUNT(%d), bufferspace(%d)", csr, count, bufferspace);
+
+	buf = req->req.buf + req->req.actual;
+	//phys = ep->bufphys;
+
+	for (i = 0; i < count; i++)
+		buf[i] = udc_readb(USB_EP5_FIFO);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	dma_rx = bufferspace - count;
+	if (dma_rx >= ep->ep.maxpacket) {
+		dma_rx -= (dma_rx % ep->ep.maxpacket);
+		
+		buf = req->req.buf + req->req.actual + count;
+		phys_rx = dma_map_single(NULL, buf, dma_rx, DMA_FROM_DEVICE);
+		if (phys_rx == 0) {
+			printk("rx dma_map_single error!\n");
+			goto stall;
+		}
+
+		req->req.actual += count;
+		flag = 1;
+		udc_writeb(USB_CTRL_2_2, udc_readb(USB_CTRL_2_2) | (1<<3) | (1<<5) | (1<<7));
+		ak98_l2_combuf_dma(phys_rx, ep->l2_buf_id, dma_rx, BUF2MEM, false);
+		udc_writel(USB_DMA_ADDR4, 0x73000000);
+		udc_writel(USB_DMA_COUNT4, dma_rx);
+		udc_writel(USB_DMA_CTRL4, (USB_ENABLE_DMA|USB_DIRECTION_RX|USB_DMA_MODE1|USB_DMA_INT_ENABLE|(USB_EP5_INDEX<<4)|USB_DMA_BUS_MODE3));
+		udc_writeb(USB_EP_INDEX, 5);
+		udc_writeb(USB_CTRL_2, csr & ~0x1);
+		ep->done = 0;
+
+		return 0;
+	}
+#endif
+#endif
+	
+stall:
+	udc_writeb(USB_CTRL_2, csr & ~0x1);
+
+	req->req.actual += count;
+	is_done = (count < ep->ep.maxpacket);
+	if (count == bufferspace)
+		is_done = 1;
+
+	ep->done = is_done;
+	if (is_done) {
+		done(ep, req, 0);
+	}
+
+	return is_done;
+}
+
+static int ak980x_get_frame(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+static int ak980x_wakeup(struct usb_gadget *gadget)
+{
+	dbg("");
+	return 0;
+}
+
+static int ak980x_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct ak980x_udc *udc = &controller;
+	
+	dbg("is_on(%d)", is_on);
+
+	if (is_on) {
+		clk_enable(udc->clk);
+		
+		rMULFUN_CON1 &= ~0x7;
+		rMULFUN_CON1 |= 0x6;
+	}
+	else {
+		rMULFUN_CON1 &= ~0x7;
+		
+		clk_disable(udc->clk);
+
+		reset_usbcontroller();
+	}
+
+	return 0;
+}
+
+static int ak980x_vbus_session(struct usb_gadget *gadget, int is_active)
+{
+	dbg("");
+	return 0;
+}
+
+static int ak980x_set_selfpowered(struct usb_gadget *gadget, int value)
+{
+	struct ak980x_udc *udc = &controller;
+
+	dbg("%d", value);
+	if (value)
+		udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
+	else
+		udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
+	
+	return 0;
+}
+static const struct usb_gadget_ops ak980x_udc_ops = {
+	.get_frame		= ak980x_get_frame,
+	.wakeup			= ak980x_wakeup,
+	.set_selfpowered	= ak980x_set_selfpowered,
+	.vbus_session		= ak980x_vbus_session,
+	.pullup			= ak980x_pullup,
+};
+
+static void ep2_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[2];
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = write_ep2_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep3_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[3];
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = read_ep3_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep4_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[4];
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = write_ep4_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static void ep5_work(struct work_struct *work)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = &controller;
+	struct ak980x_ep *ep = &udc->ep[5];
+	unsigned long flags;
+	
+	local_irq_save(flags);
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+	if (req)
+		req->status = read_ep5_fifo(ep, req);
+	else
+		dbg("something happend");
+	local_irq_restore(flags);
+}
+
+static int ak980x_ep_enable(struct usb_ep *_ep,
+				const struct usb_endpoint_descriptor *desc)
+{
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	struct ak980x_udc *udc = ep->udc;
+	int tmp, maxpacket;
+	unsigned long flags;
+
+	if (!_ep || !ep
+			|| !desc || ep->desc
+			|| _ep->name == ep0name
+			|| desc->bDescriptorType != USB_DT_ENDPOINT
+			|| (maxpacket = le16_to_cpu(desc->wMaxPacketSize)) == 0
+			|| maxpacket > ep->maxpacket) {
+		dbg("bad ep or descriptor");
+		dbg("%p, %p, %p, %p", _ep, ep, desc, ep->desc);
+		return -EINVAL;
+	}
+
+	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		dbg("bogus udcice state\n");
+		return -ESHUTDOWN;
+	}
+	
+	local_irq_save (flags);
+
+	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+	switch (tmp) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		dbg("only one control endpoint\n");
+		return -EINVAL;
+	case USB_ENDPOINT_XFER_INT:
+		if (maxpacket > EP1_FIFO_SIZE)
+			dbg("maxpacket too large");
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+		switch (maxpacket) {
+		case 8:
+		case 16:
+		case 32:
+		case 64:
+		case 512: /* for usb20 */
+			_ep->maxpacket = maxpacket & 0x7ff;
+			break;
+		default:
+			dbg("bogus maxpacket %d\n", maxpacket);
+			return -EINVAL;
+		}
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		dbg("USB_ENDPOINT_XFER_ISOC");
+		break;
+	}
+	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
+
+	ep->stopped = 0;
+	ep->desc = (struct usb_endpoint_descriptor *)desc;
+
+	dbg("%s, maxpacket(%d), desc->bEndpointAddress (0x%x) is_in(%d)",
+		       	_ep->name, maxpacket, desc->bEndpointAddress, ep->is_in);
+	
+	if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 -- int */ 
+		dbg("");
+		udc_writeb(USB_EP_INDEX, 1);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 64);
+	} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 -- tx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep2_work);
+		//usb_l2_init(L2_USB_EP2, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 2);
+		udc_writeb(USB_CTRL_1, (1<<3) | (1<<6));
+		udc_writeb(USB_CTRL_1_2, 1<<5);
+		udc_writew(USB_TX_MAX, 512);
+	} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 -- rx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep3_work);
+		//usb_l2_init(L2_USB_EP3, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 3);
+		udc_writeb(USB_CTRL_1, 1<<6);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 512);
+		udc_writeb(USB_CTRL_2, udc_readb(USB_CTRL_2) & ~(0x1));
+		udc_writeb(USB_CTRL_2, (1<<4) | (1<<7));
+		udc_writeb(USB_CTRL_2_2, 0);
+	} else if (!strcmp(_ep->name, udc->ep[4].ep.name)) { /* ep4 -- tx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep4_work);
+		//usb_l2_init(L2_USB_EP2, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 4);
+		udc_writeb(USB_CTRL_1, (1<<3) | (1<<6));
+		udc_writeb(USB_CTRL_1_2, 1<<5);
+		udc_writew(USB_TX_MAX, 512);
+	} else if (!strcmp(_ep->name, udc->ep[5].ep.name)){ /* ep5 -- rx */ 
+		dbg("");
+		//INIT_WORK(&ep->work, ep5_work);
+		//usb_l2_init(L2_USB_EP3, ep->is_in);
+		udc_writeb(USB_EP_INDEX, 5);
+		udc_writeb(USB_CTRL_1, 1<<6);
+		udc_writeb(USB_CTRL_1_2, 0);
+		udc_writew(USB_RX_MAX, 512);
+		udc_writeb(USB_CTRL_2, udc_readb(USB_CTRL_2) & ~(0x1));
+		udc_writeb(USB_CTRL_2, (1<<4) | (1<<7));
+		udc_writeb(USB_CTRL_2_2, 0);
+	} else {
+		printk("Invalid ep");
+		return -EINVAL;
+	}
+
+	ep_irq_enable(_ep);
+	local_irq_restore (flags);
+
+	return 0;
+}
+
+static int ak980x_ep_disable (struct usb_ep * _ep)
+{
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	struct ak980x_request *req;
+	unsigned long flags;
+
+	if (!_ep || !ep->desc) {
+		dbg("%s not enabled\n",
+			_ep ? ep->ep.name : NULL);
+		return -EINVAL;
+	}
+	
+	local_irq_save(flags);
+	dbg("%s", _ep->name);
+	ep->desc = NULL;
+	ep->stopped = 1;
+	
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct ak980x_request, queue);
+		done(ep, req, -ESHUTDOWN);
+	}
+	ep_irq_disable(_ep);
+	local_irq_restore(flags);
+	
+	return 0;
+}
+
+static struct usb_request *
+	ak980x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+	struct ak980x_request *req;
+
+	dbg("%s", _ep->name);
+	req = kzalloc(sizeof (struct ak980x_request), gfp_flags);
+	if (!req)
+		return NULL;
+
+	INIT_LIST_HEAD(&req->queue);
+	return &req->req;
+}
+
+static void ak980x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak980x_request *req;
+
+	dbg("%s", _ep->name);
+	req = container_of(_req, struct ak980x_request, req);
+	WARN_ON(!list_empty(&req->queue));
+	kfree(req);
+}
+
+static int ak980x_ep_queue(struct usb_ep *_ep,
+			struct usb_request *_req, gfp_t gfp_flags)
+{
+	struct ak980x_request	*req;
+	struct ak980x_ep	*ep;
+	struct ak980x_udc	*udc;
+	int			status = 0;
+	unsigned long flags;
+
+	req = container_of(_req, struct ak980x_request, req);
+	ep = container_of(_ep, struct ak980x_ep, ep);
+	
+	if (!_ep || (!ep->desc && ep->ep.name != ep0name)) {
+		dbg("invalid ep\n");
+		return -EINVAL;
+	}
+
+	udc = ep->udc;
+	if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
+		/* dbg("invalid device\n"); */
+		printk("invalid device\n");
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+
+	if (!_req || !_req->complete
+			|| !_req->buf || !list_empty(&req->queue)) {
+		/* dbg("%s invalid request", _ep->name); */
+		printk("%s invalid request\n", _ep->name);
+		local_irq_restore(flags);
+		return -EINVAL;
+	}
+
+	_req->status = -EINPROGRESS;
+	_req->actual = 0;
+
+	dbg("%s queue is_in(%d)", ep->ep.name, ep->is_in);
+	if (list_empty(&ep->queue) && !ep->stopped) {
+		if (ep->ep.name == ep0name) {
+			udc_writeb(USB_EP_INDEX, 0);
+			
+			switch (udc->ep0state) {
+			case EP0_IN_DATA_PHASE:
+				if ((udc_readb(USB_CTRL_1) & (1 << 1)) == 0
+						&& write_ep0_fifo(ep, req)) {
+					udc->ep0state = EP0_IDLE;
+					req = NULL;
+				}
+				break;
+
+			case EP0_OUT_DATA_PHASE:
+				if ((!_req->length) ||
+					((udc_readb(USB_CTRL_1) & (1 << 0))
+					&& read_ep0_fifo(ep, req))) {
+					udc->ep0state = EP0_IDLE;
+					req = NULL;
+				}
+				break;
+				
+			default:
+				local_irq_restore(flags);
+				return -EL2HLT;
+			}
+			if (req)
+				list_add_tail(&req->queue, &ep->queue);
+		} else {
+			list_add_tail(&req->queue, &ep->queue);
+			if (!strcmp(_ep->name, udc->ep[1].ep.name)) { /* ep1 */ 
+				dbg("ep1");
+				status = write_ep1_fifo(ep, req);
+			} else if (!strcmp(_ep->name, udc->ep[2].ep.name)) { /* ep2 */ 			
+				udc_writeb(USB_EP_INDEX, 2);
+				if ((udc_readb(USB_CTRL_1) & 1) == 0)
+					queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[3].ep.name)){ /* ep3 */ 
+				udc_writeb(USB_EP_INDEX, 3);
+				if (udc_readb(USB_CTRL_2) & 1)
+					queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[4].ep.name)) { /* ep4 */ 
+				udc_writeb(USB_EP_INDEX, 4);
+				if ((udc_readb(USB_CTRL_1) & 1) == 0)
+				queue_work(ep_wqueue, &ep->work);
+			} else if (!strcmp(_ep->name, udc->ep[5].ep.name)){ /* ep5 */ 
+				udc_writeb(USB_EP_INDEX, 5);
+				if (udc_readb(USB_CTRL_2) & 1)
+					queue_work(ep_wqueue, &ep->work);
+			} else {
+				printk("Invalid ep");
+				status = -EINVAL;
+				goto stall;
+			}
+		}
+	} else {
+		status = 0;
+		list_add_tail(&req->queue, &ep->queue);
+		dbg("waiting for %s int", ep->ep.name);
+	}
+
+stall:
+	local_irq_restore(flags);
+	/* return (status < 0) ? status : 0; */
+	return status;
+}
+
+
+static int ak980x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+	struct ak980x_ep	*ep;
+	struct ak980x_request	*req;
+	unsigned long flags;
+	struct ak980x_udc *udc = &controller;
+	
+	dbg("dequeue");
+
+	if (!udc->driver)
+		return -ESHUTDOWN;
+
+	ep = container_of(_ep, struct ak980x_ep, ep);
+	if (!_ep || !_req)
+		return -EINVAL;
+	
+	local_irq_save(flags);
+	list_for_each_entry (req, &ep->queue, queue) {
+		if (&req->req == _req)
+			break;
+	}
+	if (&req->req != _req) {
+		local_irq_restore(flags);
+		return -EINVAL;
+	}
+
+	done(ep, req, -ECONNRESET);
+	local_irq_restore(flags);
+	
+	return 0;
+}
+
+static int ak980x_ep_set_halt(struct usb_ep *_ep, int value)
+{	
+	struct ak980x_ep *ep = container_of(_ep, struct ak980x_ep, ep);
+	unsigned int csr = 0;
+	unsigned long		flags;
+	struct ak980x_udc *udc = &controller;
+
+	if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+		dbg("inval 2");
+		return -EINVAL;
+	}
+
+	local_irq_save (flags);
+
+	if ((ep->ep.name == ep0name) && value) {
+		udc_writeb(USB_EP_INDEX, 0);
+		udc_writeb(USB_CTRL_1, 1<<5);
+		udc_writeb(USB_CTRL_1, 1<<6 | 1<<3);
+	} else if (ep->is_in) { /* ep2 or ep4*/ 
+		if (!strcmp(ep->ep.name, udc->ep[2].ep.name))
+			udc_writeb(USB_EP_INDEX, 2);
+		else
+			udc_writeb(USB_EP_INDEX, 4);
+
+		csr = udc_readw(USB_CTRL_1);
+		if (value)
+			udc_writew(USB_CTRL_1, csr | 1<<4);
+		else {
+			csr &= ~(1<<4 | 1<<5);
+			udc_writew(USB_CTRL_1, csr);
+			csr |= 1<<6;
+			udc_writew(USB_CTRL_1, csr);
+		}
+	} else { /* ep3 or ep5*/
+		if (!strcmp(ep->ep.name, udc->ep[3].ep.name))
+			udc_writeb(USB_EP_INDEX, 3);
+		else
+			udc_writeb(USB_EP_INDEX, 5);
+		csr = udc_readw(USB_CTRL_2);
+		if (value)
+			udc_writew(USB_CTRL_2, csr | 1<<5);
+		else {
+			csr &= ~(1<<5 | 1<<6);
+			udc_writew(USB_CTRL_2, csr);
+			csr |= 1<<7;
+			udc_writew(USB_CTRL_2, csr);
+		}
+	}
+
+	ep->stopped= value ? 1 : 0;
+	local_irq_restore (flags);
+
+	return 0;
+}
+
+static const struct usb_ep_ops ak980x_ep_ops = {
+	.enable		= ak980x_ep_enable,
+	.disable	= ak980x_ep_disable,
+	.alloc_request	= ak980x_ep_alloc_request,
+	.free_request	= ak980x_ep_free_request,
+	.queue		= ak980x_ep_queue,
+	.dequeue	= ak980x_ep_dequeue,
+	.set_halt	= ak980x_ep_set_halt,
+	// there's only imprecise fifo status reporting
+};
+
+static void nop_release(struct device *dev)
+{
+			/* nothing to free */
+}
+
+static struct ak980x_udc controller = {
+	.gadget = {
+		.ops	= &ak980x_udc_ops,
+		.ep0	= &controller.ep[0].ep,
+		.name	= driver_name,
+		.dev	= {
+		       .init_name = "gadget",
+			   .release = nop_release,
+		}
+	},
+	.ep[0] = {
+		.ep = {
+			.name		= ep0name,//ep_name[0],
+			.ops		= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP0_FIFO_SIZE,
+	},
+	.ep[1] = {
+		.ep = {
+			.name	= "ep1-int",//ep_name[1],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP1_FIFO_SIZE,
+	},
+	.ep[2] = {
+		.ep = {
+			.name	= "ep2in-bulk",//ep_name[2],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP2_FIFO_SIZE,
+	},
+	.ep[3] = {
+		.ep = {
+			/* could actually do bulk too */
+			.name	= "ep3out-bulk",//ep_name[3],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP3_FIFO_SIZE,
+	},
+	.ep[4] = {
+		.ep = {
+			.name	= "ep4in-bulk",//ep_name[4],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP4_FIFO_SIZE,
+	},
+	.ep[5] = {
+		.ep = {
+			.name	= "ep5out-bulk",//ep_name[5],
+			.ops	= &ak980x_ep_ops,
+		},
+		.udc		= &controller,
+		.maxpacket	= EP5_FIFO_SIZE,
+	},
+};
+
+/**
+ * ak98_udc_process_req_status - process request GET_STATUS
+ * @udc: The device state
+ * @ctrl: USB control request
+ */
+static int ak980x_udc_get_status(struct ak980x_udc *udc,
+					struct usb_ctrlrequest *ctrl)
+{
+	u16 status = 0;
+	u8 ep_num = ctrl->wIndex & 0x7F;
+	u8 is_in = ctrl->wIndex & USB_DIR_IN;
+
+	switch (ctrl->bRequestType & USB_RECIP_MASK) {
+	case USB_RECIP_DEVICE:
+		status = udc->devstatus;
+		break;
+
+	case USB_RECIP_INTERFACE:
+		/* currently, the data result should be zero */
+		break;
+
+	case USB_RECIP_ENDPOINT:
+		if (ep_num > 5 || ctrl->wLength > 2)
+			return 1;
+
+		if (ep_num == 0) {
+			udc_writeb(USB_EP_INDEX, 0);
+			status = udc_readb(USB_CTRL_1);
+			status = status & (1<<5);
+		} else {
+			udc_writeb(USB_EP_INDEX, ep_num);
+			if (is_in) {
+				status = udc_readb(USB_CTRL_1);
+				status = status & (1<<4);
+			} else {
+				status = udc_readb(USB_CTRL_2);
+				status = status & (1<<5);
+			}
+		}
+
+		status = status ? 1 : 0;
+		break;
+	default:
+		return 1;
+	}
+
+	udc_writeb(USB_EP0_FIFO, status & 0xff);
+	udc_writeb(USB_EP0_FIFO, status >> 8);
+
+	udc_writel(USB_EP0_NUM, 2); /* 7bits */ 
+	udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<1);
+
+	udc->ep0state = EP0_END_XFER;
+
+	return 0;
+}
+
+static void ak980x_udc_handle_ep0_idle(struct ak980x_udc *udc,
+					struct ak980x_ep *ep, u32 ep0csr)
+{
+	struct usb_ctrlrequest crq;
+	int i, len, ret, tmp, timeout;
+	unsigned char *buf;
+
+	/* start control request? */
+	if (!(ep0csr & 1))
+		return;
+
+	//s3c2410_udc_nuke(dev, ep, -EPROTO);
+
+	len = udc_readw(USB_EP_COUNT);
+	buf = (unsigned char *)&crq;
+	if (len > sizeof(struct usb_ctrlrequest))
+		len = sizeof(struct usb_ctrlrequest);
+	for (i = 0; i < len; i++)
+		buf[i] = udc_readb(USB_EP0_FIFO);
+	if (len != sizeof(crq)) {
+		dbg("setup begin: fifo READ ERROR"
+			" wanted %d bytes got %d. Stalling out...",
+			sizeof(crq), len);
+		udc_writeb(USB_CTRL_1, 1<<5);
+		return;
+	}
+
+	dbg("bRequest = %d bRequestType %d wLength = %d",
+		crq.bRequest, crq.bRequestType, crq.wLength);
+
+	/* cope with automagic for some standard requests. */
+	udc->req_std = (crq.bRequestType & USB_TYPE_MASK)
+		== USB_TYPE_STANDARD;
+	udc->req_config = 0;
+	udc->req_pending = 1;
+
+	switch (crq.bRequest) {
+	case USB_REQ_SET_CONFIGURATION:
+		dbg("USB_REQ_SET_CONFIGURATION ... ");
+
+		if (crq.bRequestType == USB_RECIP_DEVICE) {
+			udc->req_config = 1;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		}
+		break;
+
+	case USB_REQ_SET_INTERFACE:
+		dbg("USB_REQ_SET_INTERFACE ... ");
+
+		if (crq.bRequestType == USB_RECIP_INTERFACE) {
+			udc->req_config = 1;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+		}
+		break;
+
+	case USB_REQ_SET_ADDRESS:
+		dbg("USB_REQ_SET_ADDRESS ... ");
+		if (crq.bRequestType == USB_RECIP_DEVICE) {
+			tmp = crq.wValue & 0x7F;
+			udc_writeb(USB_CTRL_1, 0x1<<3 | 0x1<<6);
+			timeout = 20000;
+			/* waiting for next interrupt */ 
+			while (!(udc_readb(USB_INTERRUPT_1) & 0x1) && timeout) {timeout--;}
+			udc_writeb(USB_FUNCTION_ADDR, tmp);
+			udc->addr = tmp;
+			return;
+		}
+		break;
+
+	case USB_REQ_GET_STATUS:
+		dbg("USB_REQ_GET_STATUS ...");
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (udc->req_std) {
+			if (ak980x_udc_get_status(udc, &crq)) {
+				return;
+			}
+		}
+		break;
+
+	case USB_REQ_CLEAR_FEATURE:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (crq.bRequestType != USB_RECIP_ENDPOINT)
+			break;
+
+		if (crq.wValue != USB_ENDPOINT_HALT || crq.wLength != 0)
+			break;
+
+		ak980x_ep_set_halt(&udc->ep[crq.wIndex & 0x7f].ep, 0);
+		udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3);
+		
+		return;
+
+	case USB_REQ_SET_FEATURE:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+
+		if (crq.bRequestType != USB_RECIP_ENDPOINT)
+			break;
+
+		if (crq.wValue != USB_ENDPOINT_HALT || crq.wLength != 0)
+			break;
+
+		ak980x_ep_set_halt(&udc->ep[crq.wIndex & 0x7f].ep, 1);
+		udc_writeb(USB_CTRL_1, 0x1<<6 | 0x1<<3);
+		return;
+
+	default:
+		udc_writeb(USB_CTRL_1, 0x1<<6);
+		break;
+	}
+
+	if (crq.bRequestType & USB_DIR_IN)
+		udc->ep0state = EP0_IN_DATA_PHASE;
+	else
+		udc->ep0state = EP0_OUT_DATA_PHASE;
+	
+	ret = udc->driver->setup(&udc->gadget, &crq);
+	if (ret < 0) {
+		if (udc->req_config) {
+			dbg("config change %02x fail %d?",
+				crq.bRequest, ret);
+			return;
+		}
+
+		if (ret == -EOPNOTSUPP)
+			dbg("Operation not supported");
+		else
+			dbg("udc->driver->setup failed. (%d)", ret);
+		
+		udc_writeb(USB_CTRL_1, 1<<5);
+		udc_writeb(USB_CTRL_1, 1<<3 | 1<<6);
+		udc->ep0state = EP0_IDLE;
+		/* deferred i/o == no response yet */
+	} else if (udc->req_pending) {
+		dbg("dev->req_pending... what now?");
+		udc->req_pending=0;
+	}
+
+	dbg("ep0state %s", ep0states[udc->ep0state]);
+}
+
+static void handle_ep0(struct ak980x_udc *udc)
+{
+	int csr, error = 0;
+	struct ak980x_ep *ep0 = &udc->ep[0];
+	struct ak980x_request *req = NULL;
+
+	if (!list_empty(&ep0->queue)) 
+		req = list_entry(ep0->queue.next, struct ak980x_request, queue);
+	
+	udc_writeb(USB_EP_INDEX, 0);
+	csr = udc_readb(USB_CTRL_1);
+	dbg("csr(0x%x)", csr);
+
+	if (csr & 0x1<<3) {
+		dbg("data end");
+	} 
+	if (csr & 0x1<<4) {
+		dbg("A control transaction ends before the DataEnd bit has been set");
+		udc_writeb(USB_CTRL_1, 0x1<<7);
+		/* do something else? */
+		udc->ep0state = EP0_IDLE;
+		error = 1;
+	}
+	if (csr & 0x1<<2) {
+		udc_writeb(USB_CTRL_1, udc_readb(USB_CTRL_1) & ~(1 << 2));
+		udc->ep0state = EP0_IDLE;
+		error = 1;
+	}
+	switch (udc->ep0state) {
+	case EP0_IDLE:
+		ak980x_udc_handle_ep0_idle(udc, ep0, csr);
+		break;
+
+	case EP0_IN_DATA_PHASE:			/* GET_DESCRIPTOR etc */
+		dbg("EP0_IN_DATA_PHASE ... what now?");
+		if (!(csr & (1<<1)) && req && error == 0)
+			write_ep0_fifo(ep0, req);
+		break;
+
+	case EP0_OUT_DATA_PHASE:		/* SET_DESCRIPTOR etc */
+		dbg("EP0_OUT_DATA_PHASE ... what now?");
+		if ((csr & (1<<0)) && req)
+			read_ep0_fifo(ep0, req);
+		break;
+
+	case EP0_END_XFER:
+		dbg("EP0_END_XFER ... what now?");
+		udc->ep0state = EP0_IDLE;
+		break;
+
+	case EP0_STALL:
+		dbg("EP0_STALL ... what now?");
+		udc->ep0state = EP0_IDLE;
+		break;
+	}
+}
+
+/* not ep0 */
+static void handle_ep(struct ak980x_ep *ep)
+{
+	struct ak980x_request *req;
+	struct ak980x_udc *udc = ep->udc;
+	unsigned int csr;
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next,
+			struct ak980x_request, queue);
+	else {
+		dbg("%s: no req waiting", ep->ep.name);
+		req = NULL;
+	}
+	
+	if (!strcmp(ep->ep.name, udc->ep[1].ep.name)) { /* ep1 */ 
+		dbg("ep1");
+	} else if (ep->is_in) { /* ep2 or ep4*/ 
+
+		if (!strcmp(ep->ep.name, udc->ep[2].ep.name))
+			udc_writeb(USB_EP_INDEX, 2);
+		else
+			udc_writeb(USB_EP_INDEX, 4);
+
+		csr = udc_readb(USB_CTRL_1);
+		dbg("ep2 or ep4 csr(0x%x), req(0x%p)", csr, req);
+
+                /*
+		 * if ((csr & 0x1) && req) {
+		 *         write_ep2_fifo(ep, req);
+		 * }
+                 */
+		/* udc_writeb(USB_CTRL_1, 0x1); */
+		if (csr & 0x1<<2) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<2));
+		}
+		if (csr & 0x1<<5) {
+			udc_writeb(USB_CTRL_1, csr & ~(0x1<<5));
+			return;
+		}
+
+		if (req) {
+			if (ep->done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					req = list_entry(ep->queue.next, struct ak980x_request, queue);
+					if ((csr & 1) == 0)
+						queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				if ((csr & 1) == 0)
+					queue_work(ep_wqueue, &ep->work);
+			}
+
+		}
+	} else { /* ep3 or ep 5*/ 
+		if (!strcmp(ep->ep.name, udc->ep[3].ep.name))
+			udc_writeb(USB_EP_INDEX, 3);
+		else
+			udc_writeb(USB_EP_INDEX, 5);
+
+		csr = udc_readb(USB_CTRL_2);
+		dbg("ep3 or ep5 csr(0x%x)", csr);
+
+		if (csr & 0x1<<6) {
+			udc_writeb(USB_CTRL_2, csr & ~(0x1<<6));
+		}
+		if (req && (csr & 0x1<<0))
+			queue_work(ep_wqueue, &ep->work);
+	}
+}
+
+static void udc_disconnect(struct ak980x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i;
+
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+		struct ak980x_request *req;
+
+		ep->stopped = 1;
+
+		// terminer chaque requete dans la queue
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+			done(ep, req, -ESHUTDOWN);
+		}
+	}
+
+	if (driver)
+		driver->disconnect(&udc->gadget);
+
+	udc_reinit(udc);
+}
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+static void ak98_udc_fun(void *data)
+{
+	struct ak980x_udc *udc = data;
+	
+	msleep(500);
+
+	clk_enable(udc->clk);
+	rMULFUN_CON1 &= ~0x7;
+	rMULFUN_CON1 |= 0x6;
+}
+#endif
+	
+static void udc_reset(struct ak980x_udc *udc)
+{
+	struct usb_gadget_driver *driver = udc->driver;
+	int i ,temp;
+
+	//printk("%x\n", udc_readb(USB_INTERRUPT_USB)); /* ep0 */ 
+#ifdef USB_11
+	udc_writeb(USB_POWER_CTRL, 0);
+	udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) | 0x1);
+#else
+	udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) & (~0x1));
+	udc_writeb(USB_POWER_CTRL, 0x1<<5);
+#endif
+
+	udc_writeb(USB_FUNCTION_ADDR, 0);
+	udc_writeb(USB_INTERRUPT_USB, ~(0x1<<3));
+	udc_writeb(USB_INTERRUPT_TX, 0x1<<0); /* ep0 */ 
+	
+	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
+		driver = NULL;
+
+	temp = udc_readw(USB_INTERRUPT_COMM);
+	temp = udc_readw(USB_INTERRUPT_1);
+	temp = udc_readw(USB_INTERRUPT_2);
+
+	udc->ep0state = EP0_IDLE;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+		struct ak980x_request *req;
+
+		if (list_empty(&ep->queue))
+			continue;
+
+		while (!list_empty(&ep->queue)) {
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+			done(ep, req, -ECONNRESET);
+		}
+	}
+}
+
+static irqreturn_t udc_irqhandler(int irq, void *_udc)
+{
+	struct ak980x_udc *udc = _udc;
+	short status_1, status_2;
+	char status_int;
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+	if (start == 0) {
+		start = 1;
+		rMULFUN_CON1 &= ~0x7;
+		clk_disable(udc->clk);
+		reset_usbcontroller();
+		printk("ak98_request_hold_mode NORMAL_MODE_CLOCK_5\n");
+		ak98_request_hold_mode(NORMAL_MODE_CLOCK_5, ak98_udc_fun, udc);
+		return IRQ_HANDLED;
+	}
+#endif
+
+	status_int = udc_readb(USB_INTERRUPT_COMM);
+	if (status_int & 0x1<<2) {
+		/* dbg("status_int(0x%x), reset", status_int);	 */
+		printk("\n\nstatus_int(0x%x), reset\n\n", status_int);
+		if (usb_detect) {
+			usb_exist = 1;
+			usb_detect = 0;
+			if (!udc->driver) {
+				panic("If you see this, come to find Zhang Jingyuan\n");
+				udc_enable(udc, 0);
+				return IRQ_HANDLED;
+			}
+		}
+#ifdef USB_11
+		udc->gadget.speed = USB_SPEED_FULL;
+#else
+		udc->gadget.speed = USB_SPEED_HIGH;
+#endif
+		udc_reset(udc);
+		goto done;
+	} else if(status_int & 0x1<<1) { /* resume */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("resume");
+		goto done;
+	} else if(status_int & 0x1<<0) { /* suspend */ 
+		dbg("status_int(0x%x)", status_int);	
+		dbg("suspend");
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+		if (start == 1) {
+			start = 0;
+			printk("ak98_release_hold_mode NORMAL_MODE_CLOCK_5\n");
+			ak98_release_hold_mode(NORMAL_MODE_CLOCK_5);
+		}
+#endif
+		udc_disconnect(udc);
+		goto done;
+	}
+
+	status_1 = udc_readb(USB_INTERRUPT_1);
+	status_2 = udc_readb(USB_INTERRUPT_2);
+	dbg("status_int(0x%x), status_1(0x%x), status_2(0x%x)", status_int, status_1, status_2);
+	if (status_1 & 0x1<<0) {
+		handle_ep0(udc);
+	}
+	if (status_1 & 0x1<<2) {
+		dbg("endpoint2");
+		handle_ep(&udc->ep[2]);
+	}
+	if (status_1 & 0x1<<4) {
+		dbg("endpoint4");
+		handle_ep(&udc->ep[4]);
+	}
+
+	if (status_2 & 0x1<<1) {
+		dbg("endpoint 1");
+		handle_ep(&udc->ep[1]);
+	}
+	if (status_2 & 0x1<<3) {
+		dbg("endpoint3");
+		handle_ep(&udc->ep[3]);
+	}
+	if (status_2 & 0x1<<5) {
+		dbg("endpoint5");
+		handle_ep(&udc->ep[5]);
+	}
+
+done:
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t udc_dmahandler(int irq, void *_udc)
+{
+	struct ak980x_request *req = NULL;
+	struct ak980x_udc *udc = _udc;
+	struct ak980x_ep *ep;
+	unsigned int is_done = 0;
+
+	u32 usb_dma_int = udc_readl(USB_DMA_INTR);
+	
+	if ((usb_dma_int & DMA_CHANNEL1_INT) == DMA_CHANNEL1_INT) {
+		ep = &udc->ep[2];
+		udc_writeb(USB_EP_INDEX, USB_EP2_INDEX);
+		udc_writeb(USB_CTRL_1_2, USB_TXCSR_MODE1);
+        udc_writel(USB_DMA_CTRL1, 0);
+
+        ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_tx == req->req.length - req->req.actual && !req->req.zero) 
+				is_done = 1;
+			req->req.actual += dma_tx;
+			ep->done = is_done;
+			if (is_done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				queue_work(ep_wqueue, &ep->work);
+			}
+			dma_unmap_single(NULL, phys_tx, dma_tx, DMA_TO_DEVICE);
+			dma_tx = 0;
+
+			req->status = is_done;
+		}
+		else
+			dbg("something happend");
+	}
+	
+	if ((usb_dma_int & DMA_CHANNEL2_INT) == DMA_CHANNEL2_INT) {
+		ep = &udc->ep[3];
+
+		udc_writeb(USB_EP_INDEX, USB_EP3_INDEX);
+		udc_writeb(USB_CTRL_2_2, 0);
+		udc_writel(USB_DMA_CTRL2, 0);
+		
+		ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		req = NULL;
+		is_done = 0;
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_rx == req->req.length - req->req.actual)
+				is_done = 1;
+			req->req.actual += dma_rx;
+			ep->done = is_done;
+			if (is_done)
+				done(ep, req, 0);
+			dma_unmap_single(NULL, phys_rx, dma_rx, DMA_FROM_DEVICE);
+			req->status = is_done;
+			dma_rx = 0;
+
+			flag = 0;
+		}
+		else
+			dbg("something happend");
+	}
+
+	if ((usb_dma_int & DMA_CHANNEL3_INT) == DMA_CHANNEL3_INT) {
+		ep = &udc->ep[4];
+		udc_writeb(USB_EP_INDEX, USB_EP4_INDEX);
+		udc_writeb(USB_CTRL_1_2, USB_TXCSR_MODE1);
+        udc_writel(USB_DMA_CTRL1, 0);
+
+        ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_tx == req->req.length - req->req.actual && !req->req.zero) 
+				is_done = 1;
+			req->req.actual += dma_tx;
+			ep->done = is_done;
+			if (is_done) {
+				done(ep, req, 0);
+				if (!list_empty(&ep->queue)) {
+					dbg("do next queue");
+					queue_work(ep_wqueue, &ep->work);
+				}
+			} else {
+				queue_work(ep_wqueue, &ep->work);
+			}
+			dma_unmap_single(NULL, phys_tx, dma_tx, DMA_TO_DEVICE);
+			dma_tx = 0;
+
+			req->status = is_done;
+		}
+		else
+			dbg("something happend");
+	}
+	
+	if ((usb_dma_int & DMA_CHANNEL4_INT) == DMA_CHANNEL4_INT) {
+		ep = &udc->ep[5];
+
+		udc_writeb(USB_EP_INDEX, USB_EP5_INDEX);
+		udc_writeb(USB_CTRL_2_2, 0);
+		udc_writel(USB_DMA_CTRL2, 0);
+		
+		ak98_l2_combuf_wait_dma_finish(ep->l2_buf_id);
+
+		req = NULL;
+		is_done = 0;
+		if (!list_empty(&ep->queue))
+			req = list_entry(ep->queue.next, struct ak980x_request, queue);
+
+		if (req) {
+			if (dma_rx == req->req.length - req->req.actual)
+				is_done = 1;
+			req->req.actual += dma_rx;
+			ep->done = is_done;
+			if (is_done)
+				done(ep, req, 0);
+			dma_unmap_single(NULL, phys_rx, dma_rx, DMA_FROM_DEVICE);
+			req->status = is_done;
+			dma_rx = 0;
+
+			flag = 0;
+		}
+		else
+			dbg("something happend");
+	}
+
+	return IRQ_HANDLED;
+}
+
+void udc_enable(struct ak980x_udc *udc, int enable)
+{
+	if (enable) {
+		reset_usbcontroller();
+		clk_enable(udc->clk);
+		rMULFUN_CON1 &= ~0x7;
+		rMULFUN_CON1 |= 6;
+#ifdef USB_11
+		udc_writeb(USB_POWER_CTRL, 0);
+		udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) | 0x1);
+#else
+		udc_writel(USB_MODE_STATUS, udc_readl(USB_MODE_STATUS) & (~0x1));
+		udc_writeb(USB_POWER_CTRL, 0x1<<5);
+#endif
+
+	} else {
+		rMULFUN_CON1 &= ~0x7;
+		clk_disable(udc->clk);
+		reset_usbcontroller();
+	}
+}
+
+int usb_gadget_register_driver (struct usb_gadget_driver *driver)
+{
+	struct ak980x_udc	*udc = &controller;
+	int		retval;
+
+	if (!driver
+			|| driver->speed < USB_SPEED_FULL
+			|| !driver->bind
+			|| !driver->setup) {
+		dbg("bad parameter.\n");
+		return -EINVAL;
+	}
+
+	if (udc->driver) {
+		dbg("UDC already has a gadget driver\n");
+		return -EBUSY;
+	}
+
+	udc->driver = driver;
+	udc->gadget.dev.driver = &driver->driver;
+
+	retval = driver->bind(&udc->gadget);
+	if (retval) {
+		dbg("driver->bind() returned %d\n", retval);
+		udc->driver = NULL;
+		udc->gadget.dev.driver = NULL;
+
+		return retval;
+	}
+
+	//local_irq_disable();
+	disable_irq(udc->mcu_irq);
+	udc_enable(udc, 1);
+	//local_irq_enable();
+	enable_irq(udc->mcu_irq);
+
+	dbg("bound to %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
+{
+	struct ak980x_udc *udc = &controller;
+
+	if (!driver || driver != udc->driver || !driver->unbind)
+		return -EINVAL;
+	
+	driver->unbind(&udc->gadget);
+	udc->gadget.dev.driver = NULL;
+	//udc->gadget.dev.driver_data = NULL;
+	udc->driver = NULL;
+	
+	//local_irq_disable();
+	disable_irq(udc->mcu_irq);
+	
+	cancel_work_sync(&udc->ep[2].work);
+	cancel_work_sync(&udc->ep[3].work);
+	cancel_work_sync(&udc->ep[4].work);
+	cancel_work_sync(&udc->ep[5].work);
+
+	flush_workqueue(ep_wqueue);
+	
+	udc_enable(udc, 0);
+	//local_irq_enable();
+	enable_irq(udc->mcu_irq);
+
+	dbg("unbound from %s\n", driver->driver.name);
+	return 0;
+}
+EXPORT_SYMBOL (usb_gadget_unregister_driver);
+
+static void udc_reinit(struct ak980x_udc *udc)
+{
+	u32 i;
+
+	INIT_LIST_HEAD(&udc->gadget.ep_list);
+	INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
+	udc->ep0state = EP0_IDLE;
+
+	for (i = 0; i < ENDPOINTS_NUM; i++) {
+		struct ak980x_ep *ep = &udc->ep[i];
+
+		if (i != 0)
+			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+		ep->desc = NULL;
+		/* ep->stopped = 0; */
+		ep->stopped = 0;
+		ep->ep.maxpacket = ep->maxpacket;
+		// initialiser une queue par endpoint
+		INIT_LIST_HEAD(&ep->queue);
+	}
+}
+
+static int __init ak980x_udc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ak980x_udc *udc = &controller;
+	struct resource	*res;
+	int retval;
+
+	if (pdev->num_resources < 2) {
+		dbg("invalid num_resources\n");
+		return -ENODEV;
+	}
+	if ((pdev->resource[0].flags != IORESOURCE_MEM)
+			|| (pdev->resource[1].flags != IORESOURCE_IRQ)) {
+		dbg("invalid resource type\n");
+		return -ENODEV;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	if (!request_mem_region(res->start,
+			res->end - res->start + 1,
+			driver_name)) {
+		dbg("someone's using UDC memory\n");
+		return -EBUSY;
+	}
+
+	udc->baseaddr = ioremap_nocache(res->start, res->end - res->start + 1);
+	if (!udc->baseaddr) {
+		retval = -ENOMEM;
+		goto fail0a;
+	}
+	/* init software state */
+	udc->gadget.dev.parent = dev;
+
+	udc_reinit(udc);
+
+	/* get interface and function clocks */
+	udc->clk = clk_get(dev, "udc_clk");
+	if (IS_ERR(udc->clk)) {
+		dbg("clocks missing\n");
+		retval = -ENODEV;
+		/* NOTE: we "know" here that refcounts on these are NOPs */
+		goto fail0b;
+	}
+
+	retval = device_register(&udc->gadget.dev);
+	if (retval < 0)
+		goto fail0b;
+
+	ep_wqueue = create_workqueue("ak980x_udc");
+	/* request UDC and maybe VBUS irqs */
+	udc->mcu_irq = platform_get_irq(pdev, 0);
+
+	local_irq_disable();
+	rIRQ_MASK &= ~(1UL << 25);
+	rCLK_CON1 |= (1UL << 15);
+	rMULFUN_CON1 &= ~0x7;
+	udc_writeb(USB_POWER_CTRL, 0);
+	reset_usbcontroller();
+	local_irq_enable();
+	retval = request_irq(udc->mcu_irq, udc_irqhandler,
+			IRQF_DISABLED, driver_name, udc);
+	if (retval < 0) {
+		dbg("request irq %d failed\n", udc->mcu_irq);
+		goto fail1;
+	}
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* request DMA irqs */
+	udc->dma_irq = platform_get_irq(pdev, 1);
+	retval = request_irq(udc->dma_irq, udc_dmahandler,
+			IRQF_DISABLED, driver_name, udc);
+	if (retval < 0) {
+		dbg("request irq %d failed\n", udc->dma_irq);
+		goto fail1;
+	}
+#endif
+#endif
+	platform_set_drvdata(pdev, udc);
+
+	dbg("Build at %s %s", __DATE__, __TIME__);
+
+	/* for g_serial.ko */
+	//udc->ep[2].bufaddr = dma_alloc_coherent(NULL, 16384, &udc->ep[2].bufphys, DMA_TO_DEVICE);
+	//udc->ep[3].bufaddr = dma_alloc_coherent(NULL, 16384, &udc->ep[3].bufphys, DMA_FROM_DEVICE);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* USB slave L2 buffer initialization */
+	udc->ep[2].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP2);
+	udc->ep[3].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP3);
+	udc->ep[4].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP4);
+	udc->ep[5].l2_buf_id = ak98_l2_alloc(ADDR_USB_EP5);
+#endif
+#endif
+
+	INIT_WORK(&udc->ep[2].work, ep2_work);
+	INIT_WORK(&udc->ep[3].work, ep3_work);
+	INIT_WORK(&udc->ep[4].work, ep4_work);
+	INIT_WORK(&udc->ep[5].work, ep5_work);
+
+	return 0;
+
+	free_irq(udc->mcu_irq, udc);
+fail1:
+	device_unregister(&udc->gadget.dev);
+fail0b:
+	iounmap(udc->baseaddr);
+fail0a:
+	release_mem_region(res->start, res->end - res->start + 1);
+	dbg("%s probe failed, %d\n", driver_name, retval);
+	
+	return retval;
+}
+
+static int __exit ak980x_udc_remove(struct platform_device *pdev)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+	struct resource *res;
+
+	if (udc->driver)
+		return -EBUSY;
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	free_irq(udc->dma_irq, udc);
+#endif
+#endif
+	free_irq(udc->mcu_irq, udc);
+	device_unregister(&udc->gadget.dev);
+
+	destroy_workqueue(ep_wqueue);
+
+	iounmap(udc->baseaddr);
+
+#ifndef USB_11
+#ifdef CONFIG_USB_GADGET_AK98_PRODUCER
+	/* USB slave L2 buffer initialization */
+	ak98_l2_free(ADDR_USB_EP2);
+	ak98_l2_free(ADDR_USB_EP3);
+	ak98_l2_free(ADDR_USB_EP4);
+	ak98_l2_free(ADDR_USB_EP5);
+#endif
+#endif
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res->end - res->start + 1);
+
+	return 0;
+}
+
+static void ak980x_udc_shutdown(struct platform_device *dev)
+{
+}
+
+#ifdef CONFIG_PM
+static int ak980x_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+
+	cancel_work_sync(&udc->ep[2].work);
+	cancel_work_sync(&udc->ep[3].work);
+	cancel_work_sync(&udc->ep[4].work);
+	cancel_work_sync(&udc->ep[5].work);
+
+	flush_workqueue(ep_wqueue);
+
+	rMULFUN_CON1 &= ~0x7;
+		
+	clk_disable(udc->clk);
+
+#ifndef CONFIG_USB_GADGET_AK98_PRODUCER
+		if (start == 1) {
+			start = 0;
+			printk("ak98_release_hold_mode2 NORMAL_MODE_CLOCK_5\n");
+			ak98_release_hold_mode(NORMAL_MODE_CLOCK_5);
+		}
+#endif
+	
+	reset_usbcontroller();
+	
+	udc_disconnect(udc);
+	
+	return 0;
+}
+
+static int ak980x_udc_resume(struct platform_device *pdev)
+{
+	struct ak980x_udc *udc = platform_get_drvdata(pdev);
+
+	/* something to do */
+	clk_enable(udc->clk);
+
+	rMULFUN_CON1 &= ~0x7;
+	rMULFUN_CON1 |= 0x6;
+	
+	return 0;
+}
+#else
+#define	ak980x_udc_suspend	NULL
+#define	ak980x_udc_resume	NULL
+#endif
+
+static struct platform_driver ak980x_udc_driver = {
+	.remove		= __exit_p(ak980x_udc_remove),
+	.shutdown	= ak980x_udc_shutdown,
+	.suspend	= ak980x_udc_suspend,
+	.resume		= ak980x_udc_resume,
+	.driver		= {
+		.name	= (char *) driver_name,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init udc_init_module(void)
+{
+	printk("AK980X UDC Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_probe(&ak980x_udc_driver, ak980x_udc_probe);
+}
+module_init(udc_init_module);
+
+static void __exit udc_exit_module(void)
+{
+	platform_driver_unregister(&ak980x_udc_driver);
+}
+module_exit(udc_exit_module);
+
+MODULE_DESCRIPTION("AK980X udc driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak980x_udc");
diff --git a/drivers/usb/gadget/ak98-udc/ak98_udc_full.h b/drivers/usb/gadget/ak98-udc/ak98_udc_full.h
new file mode 100644
index 00000000000..20a0fad7606
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_udc_full.h
@@ -0,0 +1,184 @@
+#ifndef _AK98_UDC_H
+#define _AK98_UDC_H
+
+/* ak980x usb register */
+#define USB_FUNCTION_ADDR	0x0
+#define USB_POWER_CTRL		0x1
+#define USB_INTERRUPT_1		0x2
+#define USB_INTERRUPT_2		0x4
+#define USB_INTERRUPT_TX	0x6
+#define USB_INTERRUPT_RX	0x8
+#define USB_INTERRUPT_COMM	0xA
+#define USB_INTERRUPT_USB	0xB
+#define USB_FRAME_NUM		0xC
+#define USB_EP_INDEX		0xE
+#define USB_TEST_MODE		0xF
+#define USB_TX_MAX			0x10
+#define USB_CTRL_1			0x12
+#define USB_CTRL_1_2		0x13
+#define USB_RX_MAX			0x14
+#define USB_CTRL_2			0x16
+#define USB_CTRL_2_2		0x17
+#define USB_EP_COUNT		0x18
+#define USB_CFG_INFO		0x1F
+#define USB_EP0_FIFO		0x20
+#define USB_EP1_FIFO		0x24
+#define USB_EP2_FIFO		0x28
+#define USB_EP3_FIFO		0x2C
+#define USB_EP4_FIFO		0x30
+#define USB_EP5_FIFO		0x34
+#define USB_DEVICE_CTRL		0x60
+#define USB_DMA_INTR		0x200
+#define USB_DMA_CTRL1		0x204
+#define USB_DMA_CTRL2		0x214
+#define USB_DMA_CTRL3		0x224
+#define USB_DMA_CTRL4		0x234
+#define USB_DMA_ADDR1		0x208
+#define USB_DMA_ADDR2		0x218
+#define USB_DMA_ADDR3		0x228
+#define USB_DMA_ADDR4		0x238
+#define USB_DMA_COUNT1		0x20C
+#define USB_DMA_COUNT2		0x21C
+#define USB_DMA_COUNT3		0x22C
+#define USB_DMA_COUNT4		0x23C
+#define USB_EP0_NUM			0x330
+#define USB_EP2_NUM			0x334
+#define USB_MODE_STATUS		0x344
+
+#define USB_ENABLE_DMA              (1)
+#define USB_DIRECTION_RX            (0<<1)
+#define USB_DIRECTION_TX            (1<<1)
+#define USB_DMA_MODE1               (1<<2)
+#define USB_DMA_MODE0               (0<<2)
+#define USB_DMA_INT_ENABLE          (1<<3)
+#define USB_DMA_INT_DISABLE         (0<<3)
+#define USB_DMA_BUS_ERROR           (1<<8)
+#define USB_DMA_BUS_MODE0           (0<<9)
+#define USB_DMA_BUS_MODE1           (1<<9)
+#define USB_DMA_BUS_MODE2           (2<<9)
+#define USB_DMA_BUS_MODE3           (3<<9)
+#define DMA_CHANNEL1_INT          	(1)
+#define DMA_CHANNEL2_INT          	(2)
+#define DMA_CHANNEL3_INT          	(4)
+#define DMA_CHANNEL4_INT          	(8)
+#define USB_EP0_INDEX             	(0)
+#define USB_EP1_INDEX             	(1 << 0)
+#define USB_EP2_INDEX             	(1 << 1)
+#define USB_EP3_INDEX             	((1 << 1)|(1 << 0))
+#define USB_EP4_INDEX             	(1 << 2)
+#define USB_EP5_INDEX             	((1 << 2)|(1 << 0))
+#define USB_EP6_INDEX             	((1 << 2)|(1 << 1))
+
+#define USB_11 [> usb1.1 <]   
+
+#define EP1_FIFO_SIZE		64 /* interrupt */ 
+//#define EP4_FIFO_SIZE		512 /* iso */ 
+#ifdef USB_11 /* USB_SPEED_FULL */ 
+#define EP0_FIFO_SIZE		16  /* control, not 64byte? */ 
+#define EP2_FIFO_SIZE		64 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		64 /* ep3 out bulk */ 
+#define EP4_FIFO_SIZE		64 /* ep4 in bulk */ 
+#define EP5_FIFO_SIZE		64 /* ep5 out bulk */ 
+#else /* USB_SPEED_HIGH */ 
+#define EP0_FIFO_SIZE		64  /* control, not 64byte? */ 
+#define EP2_FIFO_SIZE		512 /* ep2 in bulk */ 
+#define EP3_FIFO_SIZE		512 /* ep3 out bulk */ 
+#define EP4_FIFO_SIZE		512 /* ep4 in bulk */ 
+#define EP5_FIFO_SIZE		512 /* ep5 out bulk */ 
+#endif
+
+#define EP0_L2_ADDR		(AK98_VA_L2MEM + 0x1500) /* L2 buffer17 for otg control transfer */
+
+#define USB_TXCSR_AUTOSET          	(0x80)
+#define USB_TXCSR_ISO              	(0x40)
+#define USB_TXCSR_MODE1            	(0x20)
+#define USB_TXCSR_DMAREQENABLE     	(0x10)
+#define USB_TXCSR_FRCDATATOG       	(0x8)
+#define USB_TXCSR_DMAREQMODE1      	(0x4)
+#define USB_TXCSR_DMAREQMODE0      	(0x0)
+
+struct ak980x_request;
+
+struct ak980x_ep {
+	struct usb_ep		ep;
+	struct usb_gadget	*gadget;
+	struct usb_endpoint_descriptor *desc;
+
+	struct list_head	queue;
+
+	struct work_struct	work;
+	struct ak980x_request	*req; /* req be about to handle */ 
+
+	struct ak980x_udc	*udc;
+	int			maxpacket;
+	volatile int		done;
+	unsigned int		bufaddr;
+	dma_addr_t		bufphys;
+
+	unsigned		irq_enable;
+	volatile unsigned	stopped;
+	// unsigned		stopped:1;
+	unsigned		is_in:1;
+	unsigned		is_iso:1;
+	// unsigned		fifo_bank:1;
+	u8			l2_buf_id;
+};
+
+struct ak980x_request {
+	struct list_head	queue;		/* ep's requests */
+	struct usb_request	req;
+	int			status;
+};
+
+enum ep0_status {
+        EP0_IDLE,
+        EP0_IN_DATA_PHASE,
+        EP0_OUT_DATA_PHASE,
+        EP0_END_XFER,
+        EP0_STALL,
+};
+
+static const char *ep0states[]= {
+        "EP0_IDLE",
+        "EP0_IN_DATA_PHASE",
+        "EP0_OUT_DATA_PHASE",
+        "EP0_END_XFER",
+        "EP0_STALL",
+};
+
+struct usb_l2 {
+	void *buf;
+	dma_addr_t phys;
+};
+
+static const char * const ep_name[] = {
+	"ep0", "ep1-int", "ep2in-bulk", "ep3out-bulk", "ep4in-bulk", "ep5out-bulk",
+};
+
+#define ENDPOINTS_NUM ARRAY_SIZE(ep_name)
+
+struct ak980x_udc {
+	struct usb_gadget		gadget;
+	struct usb_gadget_driver	*driver;
+
+	struct ak980x_ep	ep[ENDPOINTS_NUM];
+	enum ep0_status		ep0_status;
+
+	void __iomem		*baseaddr;
+
+	unsigned int	mcu_irq;
+	unsigned int	dma_irq;
+	struct clk	*clk;
+	char		addr;   /* assigned device address */ 
+	u16			devstatus;
+	int			ep0state;
+	unsigned			req_std : 1;
+	unsigned			req_config : 1;
+	unsigned			req_pending : 1;
+};
+
+static void udc_reinit(struct ak980x_udc *udc);
+static void udc_enable(struct ak980x_udc *udc, int enable);
+static void done(struct ak980x_ep *ep, struct ak980x_request *req, int status);
+
+#endif
diff --git a/drivers/usb/gadget/ak98-udc/ak98_usbburn.c b/drivers/usb/gadget/ak98-udc/ak98_usbburn.c
new file mode 100644
index 00000000000..85def398eee
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_usbburn.c
@@ -0,0 +1,324 @@
+/*
+ * ak980_usbburn -- driver for ak88/ak98 USB burntool;
+ * Features
+ * AUTHOR Zhang Jingyuan
+ * 10-09-27 16:28:08
+ */
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/cdev.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <asm/uaccess.h>
+#include <linux/module.h>
+#include <linux/device.h>
+
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#define DEVICE_NAME "ak98_usbburn"
+
+#define AK_USBBURN_STALL		0
+#define AK_USBBURN_STATUS		1	
+
+unsigned int sense_data;
+struct semaphore sense_data_lock;
+
+EXPORT_SYMBOL(sense_data);
+EXPORT_SYMBOL(sense_data_lock);
+
+static int major = 0;
+struct usbburn_dev {
+	struct cdev cdev;
+	wait_queue_head_t rq_rbuf, wq_rbuf;	/* read and write queues for rbuf */
+	wait_queue_head_t rq_wbuf, wq_wbuf;	/* read and write queues for wbuf */
+	void *rbuf;	/* This buffer is used for user reading */
+	size_t rlen; /* The length of rbuf */
+	void *wbuf;	/* This buffer is used for user writing */
+	size_t wlen; /* The length of wbuf */
+	struct semaphore r_sem, w_sem;	/* mutual exclusion semaphore for rbuf and wbuf; */
+	int r_stall; /* The flag of stop of rbuf */
+	int w_stall; /* The flag of sotp of wbuf */
+} *b_dev;
+struct class *usbburn_class;
+
+static int ak98_usbburn_open(struct inode *inode, struct file *file)
+{
+
+	return 0;
+}
+
+static int ak98_usbburn_close(struct inode *inode, struct file *file)
+{
+	printk("ak98_usbburn device is closed\n");
+
+	return 0;
+}
+
+ssize_t ak98_usbburn_read(struct file *filp, char __user *buf,
+				size_t count, loff_t *f_pos)
+{
+	/*
+	 * count is used to record the number of data to read;
+	 * count1 is used to record the total number of data been read,
+	 * readn is used to record the number of data been read each time.
+	 */
+	size_t count1 = 0, readn;
+
+	while (count != 0) /* when the all data has been read, return. */
+	{
+		down(&b_dev->r_sem); /* before access the rbuf member of b_dev, down the r_sem */
+		while (b_dev->rbuf == NULL) { /* when there is no data to read, sleep to wait. */
+			up(&b_dev->r_sem); /* up the r_sem */
+			wait_event(b_dev->rq_rbuf, b_dev->rbuf != NULL); /* to sleep until some data is coming. */
+			down(&b_dev->r_sem);
+		}
+		readn = min(count, b_dev->rlen);
+
+		/* copy the data to user space */
+		if (copy_to_user(buf + count1, b_dev->rbuf, readn)) {
+			up(&b_dev->r_sem);
+			return -EFAULT;
+		}
+		count1 += readn;
+		count -= readn;
+
+		/* the number of data which has been read is less than b_dev->rlen */
+		if (readn < b_dev->rlen) {
+			b_dev->rbuf += readn;
+			b_dev->rlen -= readn;
+			up(&b_dev->r_sem);
+		} else { /* wake up the wq_rbuf if the all data in rbuf has been read. */
+			b_dev->rbuf = NULL;
+			up(&b_dev->r_sem);
+			wake_up(&b_dev->wq_rbuf);
+
+			/* if the r_stall is set, return */
+			if (b_dev->r_stall == 1) {
+				b_dev->r_stall = 0;
+				break;
+			}
+		}
+	}
+
+	return count1;
+}
+
+int usbburn_write(void *buf, size_t count)
+{
+	down(&b_dev->r_sem); /* down the r_sem before access the rbuf member of b_dev. */
+	b_dev->rbuf = buf;
+	b_dev->rlen = count;
+
+	/* sleep until the all data in rbuf has been read. */
+	while (b_dev->rbuf != NULL) {
+		up(&b_dev->r_sem);
+		wake_up(&b_dev->rq_rbuf);
+		wait_event(b_dev->wq_rbuf, b_dev->rbuf == NULL);
+		down(&b_dev->r_sem);
+	}
+	up(&b_dev->r_sem);
+
+	return count;
+}
+EXPORT_SYMBOL(usbburn_write);
+
+ssize_t ak98_usbburn_write(struct file *filp, const char __user *buf,
+				size_t count, loff_t *f_pos)
+{
+	/*
+	 * count is used to record the number of data to write;
+	 * count1 is used to record the total number of data been written,
+	 * written is used to record the number of data been written each time.
+	 */
+	size_t count1 = 0, written;
+
+	while (count != 0) {
+		down(&b_dev->w_sem); /* before access the wbuf member of b_dev, down the w_sem. */
+		while (b_dev->wbuf == NULL) {
+			up(&b_dev->w_sem); /* up the w_sem. */
+			wait_event(b_dev->wq_wbuf, b_dev->wbuf != NULL); /* sleep until wbuf can be written. */
+			down(&b_dev->w_sem);
+		}
+		written = min(count, b_dev->wlen);
+
+		/* copy the user space buffer to the kernel. */
+		if (copy_from_user(b_dev->wbuf, buf + count1, written)) {
+			up(&b_dev->w_sem);
+			return -EFAULT;
+		}
+		count1 += written;
+		count -= written;
+
+		/* if written if less than b_dev->wlen. */
+		if (written < b_dev->wlen) {
+			b_dev->wbuf += written;
+			b_dev->wlen -= written;
+
+			/* if w_stall is set, wake up the rq_buf and return. */
+			if (b_dev->w_stall == 1) {
+				b_dev->wbuf = NULL;
+				b_dev->wlen = written;
+				b_dev->r_stall = 0;
+				up(&b_dev->w_sem);
+				wake_up(&b_dev->rq_wbuf);
+				break;
+			}
+			up(&b_dev->w_sem);
+		} else { /* wake up rq_wbuf if the wbuf is full written. */
+			b_dev->wbuf = NULL;
+			up(&b_dev->w_sem);
+			wake_up(&b_dev->rq_wbuf);
+		}
+	}
+
+	return count1;
+}
+
+int usbburn_read(void *buf, size_t count)
+{
+	down(&b_dev->w_sem);
+	b_dev->wbuf = buf;
+	b_dev->wlen = count;
+
+	/* sleep until wbuf has been written. */
+	while (b_dev->wbuf != NULL) {
+		up(&b_dev->w_sem);
+		wake_up(&b_dev->wq_wbuf);
+		wait_event(b_dev->rq_wbuf, b_dev->wbuf == NULL);
+		down(&b_dev->w_sem);
+	}
+	count = b_dev->wlen;
+	up(&b_dev->w_sem);
+
+	return count;
+}
+EXPORT_SYMBOL(usbburn_read);
+
+int ak98_usbburn_ioctl(struct inode *inode, struct file *filp,
+		              unsigned int cmd, unsigned long arg)
+{
+	switch (cmd) {
+	case AK_USBBURN_STALL:
+		down(&b_dev->w_sem);
+		b_dev->w_stall = 1; /*set the w_stall flag for wbuf. */
+		up(&b_dev->w_sem);
+		break;
+	case AK_USBBURN_STATUS:
+		sense_data = arg;
+		up(&sense_data_lock);
+		break;
+	default:
+		break;
+	}
+	
+	return 0;
+}
+
+void usbburn_ioctl(void)
+{
+	down(&b_dev->r_sem);
+	b_dev->r_stall = 1; /*set the r_stall flag for rbuf. */
+	up(&b_dev->r_sem);
+}
+EXPORT_SYMBOL(usbburn_ioctl);
+
+/* The file operation for the usbburn device.*/
+static struct file_operations ak98_usbburn_fops = {
+	.owner  =   THIS_MODULE,
+	.read = ak98_usbburn_read,
+	.write = ak98_usbburn_write,
+	.ioctl = ak98_usbburn_ioctl,
+	.open   =   ak98_usbburn_open,     
+	.release   =   ak98_usbburn_close,
+};
+
+int __init ak98_usbburn_init(void)
+{
+	int ret = 0;
+	struct device *device;
+	dev_t dev = MKDEV(major, 0);
+	
+	/* allocate the burn device. */
+	b_dev = kmalloc(sizeof(*b_dev), GFP_KERNEL);
+	if (unlikely (!b_dev)) {
+		ret = -ENOMEM;
+		printk("error, out of memory\n");
+		goto out1;
+	}
+	memset(b_dev, 0, sizeof(*b_dev));
+
+	/* Register device major, and accept a dynamic number. */
+	if (major)
+		ret = register_chrdev_region(dev, 1, DEVICE_NAME);
+	else {
+		ret = alloc_chrdev_region(&dev, 0, 1, DEVICE_NAME);
+		major = MAJOR(dev);
+	}
+	if (ret < 0) {
+		printk("register chrdev major and minor number failed\n");
+		goto out1;
+	}
+	
+	cdev_init(&b_dev->cdev, &ak98_usbburn_fops);
+	b_dev->cdev.owner = THIS_MODULE;
+	ret = cdev_add(&b_dev->cdev, dev, 1);
+	/* Fail gracefully if need be */
+	if (ret) {
+		printk("Error %d adding ak98_usbburn_dev", ret);
+		goto out1;
+	}
+
+	usbburn_class = class_create(THIS_MODULE, "usbburn");
+	if (IS_ERR(usbburn_class)) {
+		ret = PTR_ERR(usbburn_class);
+		printk("create usbburn class failed\n");
+		goto out2;
+	}
+	device = device_create(usbburn_class, NULL, dev, NULL,"ak98_usbburn");
+	if (IS_ERR(device)) {
+		printk("ak98_usbburn chrdev create failed! %x\n", ret);
+		ret = PTR_ERR(device);
+		goto out2;
+	}
+	else
+		printk("ak98_usbburn chrdev create success!\n");
+
+	init_waitqueue_head(&b_dev->rq_rbuf);
+	init_waitqueue_head(&b_dev->wq_rbuf);
+	init_waitqueue_head(&b_dev->rq_wbuf);
+	init_waitqueue_head(&b_dev->wq_wbuf);
+
+	sema_init(&b_dev->r_sem, 1);
+	sema_init(&b_dev->w_sem, 1);
+
+	memset(&sense_data_lock, 0, sizeof(sense_data_lock));
+	sema_init(&sense_data_lock, 0);
+
+	return ret;
+out2:
+	cdev_del(&b_dev->cdev);
+out1:
+	kfree(b_dev);
+
+	return ret;
+}
+
+void __exit ak98_usbburn_exit(void)
+{
+	device_destroy(usbburn_class, MKDEV(major, 0));
+	class_destroy(usbburn_class);
+	cdev_del(&b_dev->cdev);
+	kfree(b_dev);
+	unregister_chrdev_region(MKDEV(major, 0), 1);
+}
+
+module_init(ak98_usbburn_init);
+module_exit(ak98_usbburn_exit);
+
+MODULE_DESCRIPTION("AK98 usbburn driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/usb/gadget/ak98-udc/ak98_usbburn.h b/drivers/usb/gadget/ak98-udc/ak98_usbburn.h
new file mode 100644
index 00000000000..1e4dbc577d9
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/ak98_usbburn.h
@@ -0,0 +1,14 @@
+#ifndef __AK98_USBBURN__
+#define __AK98_USBBURN__
+
+extern int sense_data;
+
+extern struct semaphore sense_data_lock;
+
+extern int usbburn_write(void *buf, size_t count);
+
+extern int usbburn_read(void *buf, size_t count);
+
+extern void usbburn_ioctl(void);
+
+#endif
diff --git a/drivers/usb/gadget/ak98-udc/anyka_usbburn.c b/drivers/usb/gadget/ak98-udc/anyka_usbburn.c
new file mode 100644
index 00000000000..abb4fc5c2d0
--- /dev/null
+++ b/drivers/usb/gadget/ak98-udc/anyka_usbburn.c
@@ -0,0 +1,176 @@
+#include "ak98_usbburn.h"
+
+static int check_anyka_command(struct fsg_dev *fsg, int needs_medium)
+{
+	struct lun		*curlun;
+
+	fsg->residue = fsg->usb_amount_left = fsg->data_size;
+
+	/* Check the LUN */
+	if (fsg->lun >= 0 && fsg->lun < fsg->nluns) {
+		fsg->curlun = curlun = &fsg->luns[fsg->lun];
+		curlun->sense_data = SS_NO_SENSE;
+		curlun->sense_data_info = 0;
+		curlun->info_valid = 0;
+	} else {
+		fsg->curlun = curlun = NULL;
+		fsg->bad_lun_okay = 0;
+
+		DBG(fsg, "unsupported LUN %d\n", fsg->lun);
+		return -EINVAL;
+	}
+
+	if (curlun && !backing_file_is_open(curlun) && needs_medium) {
+		curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int do_anyka_read(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	int			rc;
+	u32			amount_left;
+	unsigned int		amount;
+	ssize_t nread;
+
+	/* Carry out the file reads */
+	amount_left = fsg->data_size_from_cmnd;
+	if (unlikely(amount_left == 0))
+		return -EIO;		// No default reply
+
+	for (;;) {
+
+		/* Figure out how much we need to read:
+		 * Try to read the remaining amount.
+		 * But don't read more than the buffer size.
+		 * And don't try to read past the end of the file.
+		 * Finally, if we're not at a page boundary, don't read past
+		 *	the next page.
+		 * If this means reading 0 then we were asked to read past
+		 *	the end of file. */
+		amount = min((unsigned int) amount_left, mod_data.buflen);
+
+		/* Wait for the next buffer to become available */
+		bh = fsg->next_buffhd_to_fill;
+		while (bh->state != BUF_STATE_EMPTY) {
+			rc = sleep_thread(fsg);
+			if (rc)
+				return rc;
+		}
+
+		nread = usbburn_read(bh->buf + nread, amount);
+
+		amount_left  -= nread;
+		fsg->residue -= nread;
+		bh->inreq->length = nread;
+		bh->state = BUF_STATE_FULL;
+
+		if (nread < amount)
+			break;
+		if (amount_left == 0)
+			break;		// No more left to read
+
+		/* Send this buffer and go read some more */
+		bh->inreq->zero = 0;
+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
+				&bh->inreq_busy, &bh->state);
+		fsg->next_buffhd_to_fill = bh->next;
+	}
+
+	return -EIO;		// No default reply
+}
+
+static int do_anyka_write(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	struct fsg_buffhd	*bh;
+	int			get_some_more;
+	u32			amount_left_to_req, amount_left_to_write;
+	loff_t			file_offset;
+	unsigned int		amount;
+	ssize_t			nwritten;
+	int			rc;
+
+	/* Carry out the file writes */
+	get_some_more = 1;
+	file_offset = 0;
+	amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
+
+	while (amount_left_to_write > 0) {
+
+		/* Queue a request for more data from the host */
+		bh = fsg->next_buffhd_to_fill;
+		if (bh->state == BUF_STATE_EMPTY && get_some_more) {
+
+			amount = min(amount_left_to_req, mod_data.buflen);
+
+			/* Get the next buffer */
+			fsg->usb_amount_left -= amount;
+			amount_left_to_req -= amount;
+			if (amount_left_to_req == 0)
+				get_some_more = 0;
+
+			/* amount is always divisible by 512, hence by
+			 * the bulk-out maxpacket size */
+			bh->outreq->length = bh->bulk_out_intended_length =
+					amount;
+			bh->outreq->short_not_ok = 1;
+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
+					&bh->outreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+			continue;
+		}
+
+		/* Write the received data to the backing file */
+		bh = fsg->next_buffhd_to_drain;
+		if (bh->state == BUF_STATE_EMPTY && !get_some_more)
+			break;			// We stopped early
+		if (bh->state == BUF_STATE_FULL) {
+			smp_rmb();
+			fsg->next_buffhd_to_drain = bh->next;
+			bh->state = BUF_STATE_EMPTY;
+
+			/* Did something go wrong with the transfer? */
+			if (bh->outreq->status != 0) {
+				curlun->sense_data = SS_COMMUNICATION_FAILURE;
+				// curlun->sense_data_info = file_offset >> 9;
+				curlun->info_valid = 1;
+				break;
+			}
+
+			amount = bh->outreq->actual;
+			if (fsg->data_size_from_cmnd - file_offset < amount) {
+				LERROR(curlun,
+	"write %u @ %llu beyond end %llu\n",
+	amount, (unsigned long long) file_offset,
+	(unsigned long long) curlun->file_length);
+				amount = curlun->file_length - file_offset;
+			}
+
+			/* Perform the write */
+			nwritten = 0;
+			nwritten = usbburn_write(bh->buf + nwritten, amount);
+
+			file_offset += nwritten;
+			amount_left_to_write -= nwritten;
+			fsg->residue -= nwritten;
+
+			/* Did the host decide to stop early? */
+			if (bh->outreq->actual != bh->outreq->length) {
+				fsg->short_packet_received = 1;
+				break;
+			}
+			continue;
+		}
+
+		/* Wait for something to happen */
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	return -EIO;		// No default reply
+}
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
new file mode 100644
index 00000000000..4d1c3fbecfe
--- /dev/null
+++ b/drivers/usb/gadget/android.c
@@ -0,0 +1,430 @@
+/*
+ * Gadget Driver for Android
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* #define DEBUG */
+/* #define VERBOSE_DEBUG */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/utsname.h>
+#include <linux/platform_device.h>
+
+#include <linux/usb/android_composite.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/composite.h>
+#include <linux/usb/gadget.h>
+
+#include "gadget_chips.h"
+
+/*
+ * Kbuild is not very cooperative with respect to linking separately
+ * compiled library objects into one module.  So for now we won't use
+ * separate compilation ... ensuring init/exit sections work to shrink
+ * the runtime footprint, and giving us at least some parts of what
+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
+ */
+#include "usbstring.c"
+#include "config.c"
+#include "epautoconf.c"
+#include "composite.c"
+
+MODULE_AUTHOR("Mike Lockwood");
+MODULE_DESCRIPTION("Android Composite USB Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+
+static const char longname[] = "Gadget Android";
+
+/* Default vendor and product IDs, overridden by platform data */
+#define VENDOR_ID		0x18D1
+#define PRODUCT_ID		0x0001
+
+struct android_dev {
+	struct usb_composite_dev *cdev;
+	struct usb_configuration *config;
+	int num_products;
+	struct android_usb_product *products;
+	int num_functions;
+	char **functions;
+
+	int product_id;
+	int version;
+};
+
+static struct android_dev *_android_dev;
+
+/* string IDs are assigned dynamically */
+
+#define STRING_MANUFACTURER_IDX		0
+#define STRING_PRODUCT_IDX		1
+#define STRING_SERIAL_IDX		2
+
+/* String Table */
+static struct usb_string strings_dev[] = {
+	/* These dummy values should be overridden by platform data */
+	[STRING_MANUFACTURER_IDX].s = "Android",
+	[STRING_PRODUCT_IDX].s = "Android",
+	[STRING_SERIAL_IDX].s = "0123456789ABCDEF",
+	{  }			/* end of list */
+};
+
+static struct usb_gadget_strings stringtab_dev = {
+	.language	= 0x0409,	/* en-us */
+	.strings	= strings_dev,
+};
+
+static struct usb_gadget_strings *dev_strings[] = {
+	&stringtab_dev,
+	NULL,
+};
+
+static struct usb_device_descriptor device_desc = {
+	.bLength              = sizeof(device_desc),
+	.bDescriptorType      = USB_DT_DEVICE,
+	.bcdUSB               = __constant_cpu_to_le16(0x0200),
+	.bDeviceClass         = USB_CLASS_PER_INTERFACE,
+	.idVendor             = __constant_cpu_to_le16(VENDOR_ID),
+	.idProduct            = __constant_cpu_to_le16(PRODUCT_ID),
+	.bcdDevice            = __constant_cpu_to_le16(0xffff),
+	.bNumConfigurations   = 1,
+};
+
+static struct list_head _functions = LIST_HEAD_INIT(_functions);
+static int _registered_function_count = 0;
+
+void android_usb_set_connected(int connected)
+{
+	if (_android_dev && _android_dev->cdev && _android_dev->cdev->gadget) {
+		if (connected)
+			usb_gadget_connect(_android_dev->cdev->gadget);
+		else
+			usb_gadget_disconnect(_android_dev->cdev->gadget);
+	}
+}
+
+static struct android_usb_function *get_function(const char *name)
+{
+	struct android_usb_function	*f;
+	list_for_each_entry(f, &_functions, list) {
+		if (!strcmp(name, f->name))
+			return f;
+	}
+	return 0;
+}
+
+static void bind_functions(struct android_dev *dev)
+{
+	struct android_usb_function	*f;
+	char **functions = dev->functions;
+	int i;
+
+	for (i = 0; i < dev->num_functions; i++) {
+		char *name = *functions++;
+		f = get_function(name);
+		if (f)
+			f->bind_config(dev->config);
+		else
+			printk(KERN_ERR "function %s not found in bind_functions\n", name);
+	}
+}
+
+static int __init android_bind_config(struct usb_configuration *c)
+{
+	struct android_dev *dev = _android_dev;
+
+	printk(KERN_DEBUG "android_bind_config\n");
+	dev->config = c;
+
+	/* bind our functions if they have all registered */
+	if (_registered_function_count == dev->num_functions)
+		bind_functions(dev);
+
+	return 0;
+}
+
+static int android_setup_config(struct usb_configuration *c,
+		const struct usb_ctrlrequest *ctrl);
+
+static struct usb_configuration android_config_driver = {
+	.label		= "android",
+	.bind		= android_bind_config,
+	.setup		= android_setup_config,
+	.bConfigurationValue = 1,
+	.bmAttributes	= USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
+	.bMaxPower	= 0xFA, /* 500ma */
+};
+
+static int android_setup_config(struct usb_configuration *c,
+		const struct usb_ctrlrequest *ctrl)
+{
+	int i;
+	int ret = -EOPNOTSUPP;
+
+	for (i = 0; i < android_config_driver.next_interface_id; i++) {
+		if (android_config_driver.interface[i]->setup) {
+			ret = android_config_driver.interface[i]->setup(
+				android_config_driver.interface[i], ctrl);
+			if (ret >= 0)
+				return ret;
+		}
+	}
+	return ret;
+}
+
+static int product_has_function(struct android_usb_product *p,
+		struct usb_function *f)
+{
+	char **functions = p->functions;
+	int count = p->num_functions;
+	const char *name = f->name;
+	int i;
+
+	for (i = 0; i < count; i++) {
+		if (!strcmp(name, *functions++))
+			return 1;
+	}
+	return 0;
+}
+
+static int product_matches_functions(struct android_usb_product *p)
+{
+	struct usb_function		*f;
+	list_for_each_entry(f, &android_config_driver.functions, list) {
+		if (product_has_function(p, f) == !!f->disabled)
+			return 0;
+	}
+	return 1;
+}
+
+static int get_product_id(struct android_dev *dev)
+{
+	struct android_usb_product *p = dev->products;
+	int count = dev->num_products;
+	int i;
+
+	if (p) {
+		for (i = 0; i < count; i++, p++) {
+			if (product_matches_functions(p))
+				return p->product_id;
+		}
+	}
+	/* use default product ID */
+	return dev->product_id;
+}
+
+static int __init android_bind(struct usb_composite_dev *cdev)
+{
+	struct android_dev *dev = _android_dev;
+	struct usb_gadget	*gadget = cdev->gadget;
+	int			gcnum, id, product_id, ret;
+
+	printk(KERN_INFO "android_bind\n");
+
+	/* Allocate string descriptor numbers ... note that string
+	 * contents can be overridden by the composite_dev glue.
+	 */
+	id = usb_string_id(cdev);
+	if (id < 0)
+		return id;
+	strings_dev[STRING_MANUFACTURER_IDX].id = id;
+	device_desc.iManufacturer = id;
+
+	id = usb_string_id(cdev);
+	if (id < 0)
+		return id;
+	strings_dev[STRING_PRODUCT_IDX].id = id;
+	device_desc.iProduct = id;
+
+	id = usb_string_id(cdev);
+	if (id < 0)
+		return id;
+	strings_dev[STRING_SERIAL_IDX].id = id;
+	device_desc.iSerialNumber = id;
+
+	if (gadget->ops->wakeup)
+		android_config_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+
+	/* register our configuration */
+	ret = usb_add_config(cdev, &android_config_driver);
+	if (ret) {
+		printk(KERN_ERR "usb_add_config failed\n");
+		return ret;
+	}
+
+	gcnum = usb_gadget_controller_number(gadget);
+	if (gcnum >= 0)
+		device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum);
+	else {
+		/* gadget zero is so simple (for now, no altsettings) that
+		 * it SHOULD NOT have problems with bulk-capable hardware.
+		 * so just warn about unrcognized controllers -- don't panic.
+		 *
+		 * things like configuration and altsetting numbering
+		 * can need hardware-specific attention though.
+		 */
+		pr_warning("%s: controller '%s' not recognized\n",
+			longname, gadget->name);
+		device_desc.bcdDevice = __constant_cpu_to_le16(0x9999);
+	}
+
+	usb_gadget_set_selfpowered(gadget);
+	dev->cdev = cdev;
+	product_id = get_product_id(dev);
+	device_desc.idProduct = __constant_cpu_to_le16(product_id);
+	cdev->desc.idProduct = device_desc.idProduct;
+
+	return 0;
+}
+
+static struct usb_composite_driver android_usb_driver = {
+	.name		= "android_usb",
+	.dev		= &device_desc,
+	.strings	= dev_strings,
+	.bind		= android_bind,
+	.enable_function = android_enable_function,
+};
+
+void android_register_function(struct android_usb_function *f)
+{
+	struct android_dev *dev = _android_dev;
+
+	printk(KERN_INFO "android_register_function %s\n", f->name);
+	list_add_tail(&f->list, &_functions);
+	_registered_function_count++;
+
+	/* bind our functions if they have all registered
+	 * and the main driver has bound.
+	 */
+	if (dev && dev->config && _registered_function_count == dev->num_functions)
+		bind_functions(dev);
+}
+
+void android_enable_function(struct usb_function *f, int enable)
+{
+	struct android_dev *dev = _android_dev;
+	int disable = !enable;
+	int product_id;
+
+	if (!!f->disabled != disable) {
+		usb_function_set_enabled(f, !disable);
+
+#ifdef CONFIG_USB_ANDROID_RNDIS
+		if (!strcmp(f->name, "rndis")) {
+			struct usb_function		*func;
+
+			/* We need to specify the COMM class in the device descriptor
+			 * if we are using RNDIS.
+			 */
+			if (enable)
+#ifdef CONFIG_USB_ANDROID_RNDIS_WCEIS
+				dev->cdev->desc.bDeviceClass = USB_CLASS_WIRELESS_CONTROLLER;
+#else
+				dev->cdev->desc.bDeviceClass = USB_CLASS_COMM;
+#endif
+			else
+				dev->cdev->desc.bDeviceClass = USB_CLASS_PER_INTERFACE;
+
+			/* Windows does not support other interfaces when RNDIS is enabled,
+			 * so we disable UMS when RNDIS is on.
+			 */
+			list_for_each_entry(func, &android_config_driver.functions, list) {
+				if (!strcmp(func->name, "usb_mass_storage")) {
+					usb_function_set_enabled(func, !enable);
+					break;
+				}
+			}
+		}
+#endif
+
+		product_id = get_product_id(dev);
+		device_desc.idProduct = __constant_cpu_to_le16(product_id);
+		if (dev->cdev)
+			dev->cdev->desc.idProduct = device_desc.idProduct;
+		usb_composite_force_reset(dev->cdev);
+	}
+}
+
+static int __init android_probe(struct platform_device *pdev)
+{
+	struct android_usb_platform_data *pdata = pdev->dev.platform_data;
+	struct android_dev *dev = _android_dev;
+
+	printk(KERN_INFO "android_probe pdata: %p\n", pdata);
+
+	if (pdata) {
+		dev->products = pdata->products;
+		dev->num_products = pdata->num_products;
+		dev->functions = pdata->functions;
+		dev->num_functions = pdata->num_functions;
+		if (pdata->vendor_id)
+			device_desc.idVendor =
+				__constant_cpu_to_le16(pdata->vendor_id);
+		if (pdata->product_id) {
+			dev->product_id = pdata->product_id;
+			device_desc.idProduct =
+				__constant_cpu_to_le16(pdata->product_id);
+		}
+		if (pdata->version)
+			dev->version = pdata->version;
+
+		if (pdata->product_name)
+			strings_dev[STRING_PRODUCT_IDX].s = pdata->product_name;
+		if (pdata->manufacturer_name)
+			strings_dev[STRING_MANUFACTURER_IDX].s =
+					pdata->manufacturer_name;
+		if (pdata->serial_number)
+			strings_dev[STRING_SERIAL_IDX].s = pdata->serial_number;
+	}
+
+	return usb_composite_register(&android_usb_driver);
+}
+
+static struct platform_driver android_platform_driver = {
+	.driver = { .name = "android_usb", },
+	.probe = android_probe,
+};
+
+static int __init init(void)
+{
+	struct android_dev *dev;
+
+	printk(KERN_INFO "android init\n");
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	/* set default values, which should be overridden by platform data */
+	dev->product_id = PRODUCT_ID;
+	_android_dev = dev;
+
+	return platform_driver_register(&android_platform_driver);
+}
+module_init(init);
+
+static void __exit cleanup(void)
+{
+	usb_composite_unregister(&android_usb_driver);
+	platform_driver_unregister(&android_platform_driver);
+	kfree(_android_dev);
+	_android_dev = NULL;
+}
+module_exit(cleanup);
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index d05397ec8a1..ec83040cd44 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -71,6 +71,59 @@ MODULE_PARM_DESC(iSerialNumber, "SerialNumber string");
 
 /*-------------------------------------------------------------------------*/
 
+static ssize_t enable_show(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct usb_function *f = dev_get_drvdata(dev);
+	return sprintf(buf, "%d\n", !f->disabled);
+}
+
+static ssize_t enable_store(
+		struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t size)
+{
+	struct usb_function *f = dev_get_drvdata(dev);
+	struct usb_composite_driver	*driver = f->config->cdev->driver;
+	int value;
+
+	sscanf(buf, "%d", &value);
+	if (driver->enable_function)
+		driver->enable_function(f, value);
+	else
+		usb_function_set_enabled(f, value);
+
+	return size;
+}
+
+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, enable_show, enable_store);
+
+void usb_function_set_enabled(struct usb_function *f, int enabled)
+{
+	f->disabled = !enabled;
+	kobject_uevent(&f->dev->kobj, KOBJ_CHANGE);
+}
+
+
+void usb_composite_force_reset(struct usb_composite_dev *cdev)
+{
+	unsigned long			flags;
+
+	spin_lock_irqsave(&cdev->lock, flags);
+	/* force reenumeration */
+	if (cdev && cdev->gadget &&
+			cdev->gadget->speed != USB_SPEED_UNKNOWN) {
+		/* avoid sending a disconnect switch event until after we disconnect */
+		cdev->mute_switch = 1;
+		spin_unlock_irqrestore(&cdev->lock, flags);
+
+		usb_gadget_disconnect(cdev->gadget);
+		msleep(10);
+		usb_gadget_connect(cdev->gadget);
+	} else {
+		spin_unlock_irqrestore(&cdev->lock, flags);
+	}
+}
+
 /**
  * usb_add_function() - add a function to a configuration
  * @config: the configuration
@@ -88,15 +141,30 @@ MODULE_PARM_DESC(iSerialNumber, "SerialNumber string");
 int __init usb_add_function(struct usb_configuration *config,
 		struct usb_function *function)
 {
+	struct usb_composite_dev	*cdev = config->cdev;
 	int	value = -EINVAL;
+	int index;
 
-	DBG(config->cdev, "adding '%s'/%p to config '%s'/%p\n",
+	DBG(cdev, "adding '%s'/%p to config '%s'/%p\n",
 			function->name, function,
 			config->label, config);
 
 	if (!function->set_alt || !function->disable)
 		goto done;
 
+	index = atomic_inc_return(&cdev->driver->function_count);
+	function->dev = device_create(cdev->driver->class, NULL,
+		MKDEV(0, index), NULL, function->name);
+	if (IS_ERR(function->dev))
+		return PTR_ERR(function->dev);
+
+	value = device_create_file(function->dev, &dev_attr_enable);
+	if (value < 0) {
+		device_destroy(cdev->driver->class, MKDEV(0, index));
+		return value;
+	}
+	dev_set_drvdata(function->dev, function);
+
 	function->config = config;
 	list_add_tail(&function->list, &config->functions);
 
@@ -122,7 +190,7 @@ int __init usb_add_function(struct usb_configuration *config,
 
 done:
 	if (value)
-		DBG(config->cdev, "adding '%s'/%p --> %d\n",
+		DBG(cdev, "adding '%s'/%p --> %d\n",
 				function->name, function, value);
 	return value;
 }
@@ -232,17 +300,19 @@ static int config_buf(struct usb_configuration *config,
 		enum usb_device_speed speed, void *buf, u8 type)
 {
 	struct usb_config_descriptor	*c = buf;
+	struct usb_interface_descriptor *intf;
 	void				*next = buf + USB_DT_CONFIG_SIZE;
 	int				len = USB_BUFSIZ - USB_DT_CONFIG_SIZE;
 	struct usb_function		*f;
 	int				status;
+	int				interfaceCount = 0;
+	u8 *dest;
 
 	/* write the config descriptor */
 	c = buf;
 	c->bLength = USB_DT_CONFIG_SIZE;
 	c->bDescriptorType = type;
-	/* wTotalLength is written later */
-	c->bNumInterfaces = config->next_interface_id;
+	/* wTotalLength and bNumInterfaces are written later */
 	c->bConfigurationValue = config->bConfigurationValue;
 	c->iConfiguration = config->iConfiguration;
 	c->bmAttributes = USB_CONFIG_ATT_ONE | config->bmAttributes;
@@ -261,23 +331,40 @@ static int config_buf(struct usb_configuration *config,
 	/* add each function's descriptors */
 	list_for_each_entry(f, &config->functions, list) {
 		struct usb_descriptor_header **descriptors;
+		struct usb_descriptor_header *descriptor;
 
 		if (speed == USB_SPEED_HIGH)
 			descriptors = f->hs_descriptors;
 		else
 			descriptors = f->descriptors;
-		if (!descriptors)
+		if (f->disabled || !descriptors || descriptors[0] == NULL)
 			continue;
 		status = usb_descriptor_fillbuf(next, len,
 			(const struct usb_descriptor_header **) descriptors);
 		if (status < 0)
 			return status;
+
+		/* set interface numbers dynamically */
+		dest = next;
+		while ((descriptor = *descriptors++) != NULL) {
+			intf = (struct usb_interface_descriptor *)dest;
+			if (intf->bDescriptorType == USB_DT_INTERFACE) {
+				/* don't increment bInterfaceNumber for alternate settings */
+				if (intf->bAlternateSetting == 0)
+					intf->bInterfaceNumber = interfaceCount++;
+				else
+					intf->bInterfaceNumber = interfaceCount - 1;
+			}
+			dest += intf->bLength;
+		}
+
 		len -= status;
 		next += status;
 	}
 
 	len = next - buf;
 	c->wTotalLength = cpu_to_le16(len);
+	c->bNumInterfaces = interfaceCount;
 	return len;
 }
 
@@ -421,6 +508,8 @@ static int set_config(struct usb_composite_dev *cdev,
 
 		if (!f)
 			break;
+		if (f->disabled)
+			continue;
 
 		result = f->set_alt(f, tmp, 0);
 		if (result < 0) {
@@ -436,6 +525,8 @@ static int set_config(struct usb_composite_dev *cdev,
 	power = c->bMaxPower ? (2 * c->bMaxPower) : CONFIG_USB_GADGET_VBUS_DRAW;
 done:
 	usb_gadget_vbus_draw(gadget, power);
+
+	schedule_work(&cdev->switch_work);
 	return result;
 }
 
@@ -756,11 +847,11 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
 	case USB_REQ_GET_CONFIGURATION:
 		if (ctrl->bRequestType != USB_DIR_IN)
 			goto unknown;
-		if (cdev->config)
+		if (cdev->config) {
 			*(u8 *)req->buf = cdev->config->bConfigurationValue;
-		else
+			value = min(w_length, (u16) 1);
+		} else
 			*(u8 *)req->buf = 0;
-		value = min(w_length, (u16) 1);
 		break;
 
 	/* function drivers must handle get/set altsetting; if there's
@@ -810,6 +901,9 @@ unknown:
 		 */
 		if ((ctrl->bRequestType & USB_RECIP_MASK)
 				== USB_RECIP_INTERFACE) {
+			if (cdev->config == NULL)
+				return value;
+
 			f = cdev->config->interface[intf];
 			if (f && f->setup)
 				value = f->setup(f, ctrl);
@@ -824,6 +918,25 @@ unknown:
 				value = c->setup(c, ctrl);
 		}
 
+		/* If the vendor request is not processed (value < 0),
+		 * call all device registered configure setup callbacks
+		 * to process it.
+		 * This is used to handle the following cases:
+		 * - vendor request is for the device and arrives before
+		 * setconfiguration.
+		 * - Some devices are required to handle vendor request before
+		 * setconfiguration such as MTP, USBNET.
+		 */
+
+		if (value < 0) {
+			struct usb_configuration        *cfg;
+
+			list_for_each_entry(cfg, &cdev->configs, list) {
+			if (cfg && cfg->setup)
+				value = cfg->setup(cfg, ctrl);
+			}
+		}
+
 		goto done;
 	}
 
@@ -855,6 +968,11 @@ static void composite_disconnect(struct usb_gadget *gadget)
 	spin_lock_irqsave(&cdev->lock, flags);
 	if (cdev->config)
 		reset_config(cdev);
+
+	if (cdev->mute_switch)
+		cdev->mute_switch = 0;
+	else
+		schedule_work(&cdev->switch_work);
 	spin_unlock_irqrestore(&cdev->lock, flags);
 }
 
@@ -904,6 +1022,8 @@ composite_unbind(struct usb_gadget *gadget)
 		kfree(cdev->req->buf);
 		usb_ep_free_request(gadget->ep0, cdev->req);
 	}
+
+	switch_dev_unregister(&cdev->sdev);
 	kfree(cdev);
 	set_gadget_data(gadget, NULL);
 	composite = NULL;
@@ -931,6 +1051,19 @@ string_override(struct usb_gadget_strings **tab, u8 id, const char *s)
 	}
 }
 
+static void
+composite_switch_work(struct work_struct *data)
+{
+	struct usb_composite_dev	*cdev =
+		container_of(data, struct usb_composite_dev, switch_work);
+	struct usb_configuration *config = cdev->config;
+
+	if (config)
+		switch_set_state(&cdev->sdev, config->bConfigurationValue);
+	else
+		switch_set_state(&cdev->sdev, 0);
+}
+
 static int __init composite_bind(struct usb_gadget *gadget)
 {
 	struct usb_composite_dev	*cdev;
@@ -974,6 +1107,12 @@ static int __init composite_bind(struct usb_gadget *gadget)
 	if (status < 0)
 		goto fail;
 
+	cdev->sdev.name = "usb_configuration";
+	status = switch_dev_register(&cdev->sdev);
+	if (status < 0)
+		goto fail;
+	INIT_WORK(&cdev->switch_work, composite_switch_work);
+
 	cdev->desc = *composite->dev;
 	cdev->desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
 
@@ -1048,6 +1187,23 @@ composite_resume(struct usb_gadget *gadget)
 	}
 }
 
+static int
+composite_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+	struct usb_function *f = dev_get_drvdata(dev);
+
+	if (!f) {
+		/* this happens when the device is first created */
+		return 0;
+	}
+
+	if (add_uevent_var(env, "FUNCTION=%s", f->name))
+		return -ENOMEM;
+	if (add_uevent_var(env, "ENABLED=%d", !f->disabled))
+		return -ENOMEM;
+	return 0;
+}
+
 /*-------------------------------------------------------------------------*/
 
 static struct usb_gadget_driver composite_driver = {
@@ -1093,6 +1249,11 @@ int __init usb_composite_register(struct usb_composite_driver *driver)
 	composite_driver.driver.name = driver->name;
 	composite = driver;
 
+	driver->class = class_create(THIS_MODULE, "usb_composite");
+	if (IS_ERR(driver->class))
+		return PTR_ERR(driver->class);
+	driver->class->dev_uevent = composite_uevent;
+
 	return usb_gadget_register_driver(&composite_driver);
 }
 
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index 7953948bfe4..68c74a2ba0c 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -14,6 +14,7 @@
 
 #include <linux/kernel.h>
 #include <linux/device.h>
+#include <linux/usb/android_composite.h>
 
 #include "u_serial.h"
 #include "gadget_chips.h"
@@ -384,10 +385,10 @@ static int acm_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
 			usb_ep_disable(acm->notify);
 		} else {
 			VDBG(cdev, "init acm ctrl interface %d\n", intf);
-			acm->notify_desc = ep_choose(cdev->gadget,
-					acm->hs.notify,
-					acm->fs.notify);
 		}
+		acm->notify_desc = ep_choose(cdev->gadget,
+				acm->hs.notify,
+				acm->fs.notify);
 		usb_ep_enable(acm->notify, acm->notify_desc);
 		acm->notify->driver_data = acm;
 
@@ -397,11 +398,11 @@ static int acm_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
 			gserial_disconnect(&acm->port);
 		} else {
 			DBG(cdev, "activate acm ttyGS%d\n", acm->port_num);
-			acm->port.in_desc = ep_choose(cdev->gadget,
-					acm->hs.in, acm->fs.in);
-			acm->port.out_desc = ep_choose(cdev->gadget,
-					acm->hs.out, acm->fs.out);
 		}
+		acm->port.in_desc = ep_choose(cdev->gadget,
+				acm->hs.in, acm->fs.in);
+		acm->port.out_desc = ep_choose(cdev->gadget,
+				acm->hs.out, acm->fs.out);
 		gserial_connect(&acm->port, acm->port_num);
 
 	} else
@@ -761,3 +762,28 @@ int __init acm_bind_config(struct usb_configuration *c, u8 port_num)
 		kfree(acm);
 	return status;
 }
+
+#ifdef CONFIG_USB_ANDROID_ACM
+
+int acm_function_bind_config(struct usb_configuration *c)
+{
+	int ret = acm_bind_config(c, 0);
+	if (ret == 0)
+		gserial_setup(c->cdev->gadget, 1);
+	return ret;
+}
+
+static struct android_usb_function acm_function = {
+	.name = "acm",
+	.bind_config = acm_function_bind_config,
+};
+
+static int __init init(void)
+{
+	printk(KERN_INFO "f_acm init\n");
+	android_register_function(&acm_function);
+	return 0;
+}
+module_init(init);
+
+#endif /* CONFIG_USB_ANDROID_ACM */
diff --git a/drivers/usb/gadget/f_adb.c b/drivers/usb/gadget/f_adb.c
new file mode 100644
index 00000000000..a0b0774b955
--- /dev/null
+++ b/drivers/usb/gadget/f_adb.c
@@ -0,0 +1,655 @@
+/*
+ * Gadget Driver for Android ADB
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* #define DEBUG */
+/* #define VERBOSE_DEBUG */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+
+#include <linux/usb/android_composite.h>
+
+#define BULK_BUFFER_SIZE           4096
+
+/* number of tx requests to allocate */
+#define TX_REQ_MAX 4
+
+static const char shortname[] = "android_adb";
+
+struct adb_dev {
+	struct usb_function function;
+	struct usb_composite_dev *cdev;
+	spinlock_t lock;
+
+	struct usb_ep *ep_in;
+	struct usb_ep *ep_out;
+
+	int online;
+	int error;
+
+	atomic_t read_excl;
+	atomic_t write_excl;
+	atomic_t open_excl;
+
+	struct list_head tx_idle;
+
+	wait_queue_head_t read_wq;
+	wait_queue_head_t write_wq;
+	struct usb_request *rx_req;
+	int rx_done;
+};
+
+static struct usb_interface_descriptor adb_interface_desc = {
+	.bLength                = USB_DT_INTERFACE_SIZE,
+	.bDescriptorType        = USB_DT_INTERFACE,
+	.bInterfaceNumber       = 0,
+	.bNumEndpoints          = 2,
+	.bInterfaceClass        = 0xFF,
+	.bInterfaceSubClass     = 0x42,
+	.bInterfaceProtocol     = 1,
+};
+
+static struct usb_endpoint_descriptor adb_highspeed_in_desc = {
+	.bLength                = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType        = USB_DT_ENDPOINT,
+	.bEndpointAddress       = USB_DIR_IN,
+	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize         = __constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor adb_highspeed_out_desc = {
+	.bLength                = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType        = USB_DT_ENDPOINT,
+	.bEndpointAddress       = USB_DIR_OUT,
+	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize         = __constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor adb_fullspeed_in_desc = {
+	.bLength                = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType        = USB_DT_ENDPOINT,
+	.bEndpointAddress       = USB_DIR_IN,
+	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usb_endpoint_descriptor adb_fullspeed_out_desc = {
+	.bLength                = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType        = USB_DT_ENDPOINT,
+	.bEndpointAddress       = USB_DIR_OUT,
+	.bmAttributes           = USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usb_descriptor_header *fs_adb_descs[] = {
+	(struct usb_descriptor_header *) &adb_interface_desc,
+	(struct usb_descriptor_header *) &adb_fullspeed_in_desc,
+	(struct usb_descriptor_header *) &adb_fullspeed_out_desc,
+	NULL,
+};
+
+static struct usb_descriptor_header *hs_adb_descs[] = {
+	(struct usb_descriptor_header *) &adb_interface_desc,
+	(struct usb_descriptor_header *) &adb_highspeed_in_desc,
+	(struct usb_descriptor_header *) &adb_highspeed_out_desc,
+	NULL,
+};
+
+
+/* temporary variable used between adb_open() and adb_gadget_bind() */
+static struct adb_dev *_adb_dev;
+
+static atomic_t adb_enable_excl;
+
+static inline struct adb_dev *func_to_dev(struct usb_function *f)
+{
+	return container_of(f, struct adb_dev, function);
+}
+
+
+static struct usb_request *adb_request_new(struct usb_ep *ep, int buffer_size)
+{
+	struct usb_request *req = usb_ep_alloc_request(ep, GFP_KERNEL);
+	if (!req)
+		return NULL;
+
+	/* now allocate buffers for the requests */
+	req->buf = kmalloc(buffer_size, GFP_KERNEL);
+	if (!req->buf) {
+		usb_ep_free_request(ep, req);
+		return NULL;
+	}
+
+	return req;
+}
+
+static void adb_request_free(struct usb_request *req, struct usb_ep *ep)
+{
+	if (req) {
+		kfree(req->buf);
+		usb_ep_free_request(ep, req);
+	}
+}
+
+static inline int _lock(atomic_t *excl)
+{
+	if (atomic_inc_return(excl) == 1) {
+		return 0;
+	} else {
+		atomic_dec(excl);
+		return -1;
+	}
+}
+
+static inline void _unlock(atomic_t *excl)
+{
+	atomic_dec(excl);
+}
+
+/* add a request to the tail of a list */
+void req_put(struct adb_dev *dev, struct list_head *head,
+		struct usb_request *req)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->lock, flags);
+	list_add_tail(&req->list, head);
+	spin_unlock_irqrestore(&dev->lock, flags);
+}
+
+/* remove a request from the head of a list */
+struct usb_request *req_get(struct adb_dev *dev, struct list_head *head)
+{
+	unsigned long flags;
+	struct usb_request *req;
+
+	spin_lock_irqsave(&dev->lock, flags);
+	if (list_empty(head)) {
+		req = 0;
+	} else {
+		req = list_first_entry(head, struct usb_request, list);
+		list_del(&req->list);
+	}
+	spin_unlock_irqrestore(&dev->lock, flags);
+	return req;
+}
+
+static void adb_complete_in(struct usb_ep *ep, struct usb_request *req)
+{
+	struct adb_dev *dev = _adb_dev;
+
+	if (req->status != 0)
+		dev->error = 1;
+
+	req_put(dev, &dev->tx_idle, req);
+
+	wake_up(&dev->write_wq);
+}
+
+static void adb_complete_out(struct usb_ep *ep, struct usb_request *req)
+{
+	struct adb_dev *dev = _adb_dev;
+
+	dev->rx_done = 1;
+	if (req->status != 0)
+		dev->error = 1;
+
+	wake_up(&dev->read_wq);
+}
+
+static int __init create_bulk_endpoints(struct adb_dev *dev,
+				struct usb_endpoint_descriptor *in_desc,
+				struct usb_endpoint_descriptor *out_desc)
+{
+	struct usb_composite_dev *cdev = dev->cdev;
+	struct usb_request *req;
+	struct usb_ep *ep;
+	int i;
+
+	DBG(cdev, "create_bulk_endpoints dev: %p\n", dev);
+
+	ep = usb_ep_autoconfig(cdev->gadget, in_desc);
+	if (!ep) {
+		DBG(cdev, "usb_ep_autoconfig for ep_in failed\n");
+		return -ENODEV;
+	}
+	DBG(cdev, "usb_ep_autoconfig for ep_in got %s\n", ep->name);
+	ep->driver_data = dev;		/* claim the endpoint */
+	dev->ep_in = ep;
+
+	ep = usb_ep_autoconfig(cdev->gadget, out_desc);
+	if (!ep) {
+		DBG(cdev, "usb_ep_autoconfig for ep_out failed\n");
+		return -ENODEV;
+	}
+	DBG(cdev, "usb_ep_autoconfig for adb ep_out got %s\n", ep->name);
+	ep->driver_data = dev;		/* claim the endpoint */
+	dev->ep_out = ep;
+
+	/* now allocate requests for our endpoints */
+	req = adb_request_new(dev->ep_out, BULK_BUFFER_SIZE);
+	if (!req)
+		goto fail;
+	req->complete = adb_complete_out;
+	dev->rx_req = req;
+
+	for (i = 0; i < TX_REQ_MAX; i++) {
+		req = adb_request_new(dev->ep_in, BULK_BUFFER_SIZE);
+		if (!req)
+			goto fail;
+		req->complete = adb_complete_in;
+		req_put(dev, &dev->tx_idle, req);
+	}
+
+	return 0;
+
+fail:
+	printk(KERN_ERR "adb_bind() could not allocate requests\n");
+	return -1;
+}
+
+static ssize_t adb_read(struct file *fp, char __user *buf,
+				size_t count, loff_t *pos)
+{
+	struct adb_dev *dev = fp->private_data;
+	struct usb_composite_dev *cdev = dev->cdev;
+	struct usb_request *req;
+	int r = count, xfer;
+	int ret;
+
+	DBG(cdev, "adb_read(%d)\n", count);
+
+	if (count > BULK_BUFFER_SIZE)
+		return -EINVAL;
+
+	if (_lock(&dev->read_excl))
+		return -EBUSY;
+
+	/* we will block until we're online */
+	while (!(dev->online || dev->error)) {
+		DBG(cdev, "adb_read: waiting for online state\n");
+		ret = wait_event_interruptible(dev->read_wq,
+				(dev->online || dev->error));
+		if (ret < 0) {
+			_unlock(&dev->read_excl);
+			return ret;
+		}
+	}
+	if (dev->error) {
+		r = -EIO;
+		goto done;
+	}
+
+requeue_req:
+	/* queue a request */
+	req = dev->rx_req;
+	req->length = count;
+	dev->rx_done = 0;
+	ret = usb_ep_queue(dev->ep_out, req, GFP_ATOMIC);
+	if (ret < 0) {
+		DBG(cdev, "adb_read: failed to queue req %p (%d)\n", req, ret);
+		r = -EIO;
+		dev->error = 1;
+		goto done;
+	} else {
+		DBG(cdev, "rx %p queue\n", req);
+	}
+
+	/* wait for a request to complete */
+	ret = wait_event_interruptible(dev->read_wq, dev->rx_done);
+	if (ret < 0) {
+		dev->error = 1;
+		r = ret;
+		goto done;
+	}
+	if (!dev->error) {
+		/* If we got a 0-len packet, throw it back and try again. */
+		if (req->actual == 0)
+			goto requeue_req;
+
+		DBG(cdev, "rx %p %d\n", req, req->actual);
+		xfer = (req->actual < count) ? req->actual : count;
+		if (copy_to_user(buf, req->buf, xfer))
+			r = -EFAULT;
+	} else
+		r = -EIO;
+
+done:
+	_unlock(&dev->read_excl);
+	DBG(cdev, "adb_read returning %d\n", r);
+	return r;
+}
+
+static ssize_t adb_write(struct file *fp, const char __user *buf,
+				 size_t count, loff_t *pos)
+{
+	struct adb_dev *dev = fp->private_data;
+	struct usb_composite_dev *cdev = dev->cdev;
+	struct usb_request *req = 0;
+	int r = count, xfer;
+	int ret;
+
+	DBG(cdev, "adb_write(%d)\n", count);
+
+	if (_lock(&dev->write_excl))
+		return -EBUSY;
+
+	while (count > 0) {
+		if (dev->error) {
+			DBG(cdev, "adb_write dev->error\n");
+			r = -EIO;
+			break;
+		}
+
+		/* get an idle tx request to use */
+		req = 0;
+		ret = wait_event_interruptible(dev->write_wq,
+			((req = req_get(dev, &dev->tx_idle)) || dev->error));
+
+		if (ret < 0) {
+			r = ret;
+			break;
+		}
+
+		if (req != 0) {
+			if (count > BULK_BUFFER_SIZE)
+				xfer = BULK_BUFFER_SIZE;
+			else
+				xfer = count;
+			if (copy_from_user(req->buf, buf, xfer)) {
+				r = -EFAULT;
+				break;
+			}
+
+			req->length = xfer;
+			ret = usb_ep_queue(dev->ep_in, req, GFP_ATOMIC);
+			if (ret < 0) {
+				DBG(cdev, "adb_write: xfer error %d\n", ret);
+				dev->error = 1;
+				r = -EIO;
+				break;
+			}
+
+			buf += xfer;
+			count -= xfer;
+
+			/* zero this so we don't try to free it on error exit */
+			req = 0;
+		}
+	}
+
+	if (req)
+		req_put(dev, &dev->tx_idle, req);
+
+	_unlock(&dev->write_excl);
+	DBG(cdev, "adb_write returning %d\n", r);
+	return r;
+}
+
+static int adb_open(struct inode *ip, struct file *fp)
+{
+	printk(KERN_INFO "adb_open\n");
+	if (_lock(&_adb_dev->open_excl))
+		return -EBUSY;
+
+	fp->private_data = _adb_dev;
+
+	/* clear the error latch */
+	_adb_dev->error = 0;
+
+	return 0;
+}
+
+static int adb_release(struct inode *ip, struct file *fp)
+{
+	printk(KERN_INFO "adb_release\n");
+	_unlock(&_adb_dev->open_excl);
+	return 0;
+}
+
+/* file operations for ADB device /dev/android_adb */
+static struct file_operations adb_fops = {
+	.owner = THIS_MODULE,
+	.read = adb_read,
+	.write = adb_write,
+	.open = adb_open,
+	.release = adb_release,
+};
+
+static struct miscdevice adb_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = shortname,
+	.fops = &adb_fops,
+};
+
+static int adb_enable_open(struct inode *ip, struct file *fp)
+{
+	if (atomic_inc_return(&adb_enable_excl) != 1) {
+		atomic_dec(&adb_enable_excl);
+		return -EBUSY;
+	}
+
+	printk(KERN_INFO "enabling adb\n");
+	android_enable_function(&_adb_dev->function, 1);
+
+	return 0;
+}
+
+static int adb_enable_release(struct inode *ip, struct file *fp)
+{
+	printk(KERN_INFO "disabling adb\n");
+	android_enable_function(&_adb_dev->function, 0);
+	atomic_dec(&adb_enable_excl);
+	return 0;
+}
+
+static const struct file_operations adb_enable_fops = {
+	.owner =   THIS_MODULE,
+	.open =    adb_enable_open,
+	.release = adb_enable_release,
+};
+
+static struct miscdevice adb_enable_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "android_adb_enable",
+	.fops = &adb_enable_fops,
+};
+
+static int
+adb_function_bind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct usb_composite_dev *cdev = c->cdev;
+	struct adb_dev	*dev = func_to_dev(f);
+	int			id;
+	int			ret;
+
+	dev->cdev = cdev;
+	DBG(cdev, "adb_function_bind dev: %p\n", dev);
+
+	/* allocate interface ID(s) */
+	id = usb_interface_id(c, f);
+	if (id < 0)
+		return id;
+	adb_interface_desc.bInterfaceNumber = id;
+
+	/* allocate endpoints */
+	ret = create_bulk_endpoints(dev, &adb_fullspeed_in_desc,
+			&adb_fullspeed_out_desc);
+	if (ret)
+		return ret;
+
+	/* support high speed hardware */
+	if (gadget_is_dualspeed(c->cdev->gadget)) {
+		adb_highspeed_in_desc.bEndpointAddress =
+			adb_fullspeed_in_desc.bEndpointAddress;
+		adb_highspeed_out_desc.bEndpointAddress =
+			adb_fullspeed_out_desc.bEndpointAddress;
+	}
+
+	DBG(cdev, "%s speed %s: IN/%s, OUT/%s\n",
+			gadget_is_dualspeed(c->cdev->gadget) ? "dual" : "full",
+			f->name, dev->ep_in->name, dev->ep_out->name);
+	return 0;
+}
+
+static void
+adb_function_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct adb_dev	*dev = func_to_dev(f);
+	struct usb_request *req;
+
+	spin_lock_irq(&dev->lock);
+
+	adb_request_free(dev->rx_req, dev->ep_out);
+	while ((req = req_get(dev, &dev->tx_idle)))
+		adb_request_free(req, dev->ep_in);
+
+	dev->online = 0;
+	dev->error = 1;
+	spin_unlock_irq(&dev->lock);
+
+	misc_deregister(&adb_device);
+	misc_deregister(&adb_enable_device);
+	kfree(_adb_dev);
+	_adb_dev = NULL;
+}
+
+static int adb_function_set_alt(struct usb_function *f,
+		unsigned intf, unsigned alt)
+{
+	struct adb_dev	*dev = func_to_dev(f);
+	struct usb_composite_dev *cdev = f->config->cdev;
+	int ret;
+
+	DBG(cdev, "adb_function_set_alt intf: %d alt: %d\n", intf, alt);
+	ret = usb_ep_enable(dev->ep_in,
+			ep_choose(cdev->gadget,
+				&adb_highspeed_in_desc,
+				&adb_fullspeed_in_desc));
+	if (ret)
+		return ret;
+	ret = usb_ep_enable(dev->ep_out,
+			ep_choose(cdev->gadget,
+				&adb_highspeed_out_desc,
+				&adb_fullspeed_out_desc));
+	if (ret) {
+		usb_ep_disable(dev->ep_in);
+		return ret;
+	}
+	dev->online = 1;
+
+	/* readers may be blocked waiting for us to go online */
+	wake_up(&dev->read_wq);
+	return 0;
+}
+
+static void adb_function_disable(struct usb_function *f)
+{
+	struct adb_dev	*dev = func_to_dev(f);
+	struct usb_composite_dev	*cdev = dev->cdev;
+
+	DBG(cdev, "adb_function_disable\n");
+	dev->online = 0;
+	dev->error = 1;
+	usb_ep_disable(dev->ep_in);
+	usb_ep_disable(dev->ep_out);
+
+	/* readers may be blocked waiting for us to go online */
+	wake_up(&dev->read_wq);
+
+	VDBG(cdev, "%s disabled\n", dev->function.name);
+}
+
+static int adb_bind_config(struct usb_configuration *c)
+{
+	struct adb_dev *dev;
+	int ret;
+
+	printk(KERN_INFO "adb_bind_config\n");
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	spin_lock_init(&dev->lock);
+
+	init_waitqueue_head(&dev->read_wq);
+	init_waitqueue_head(&dev->write_wq);
+
+	atomic_set(&dev->open_excl, 0);
+	atomic_set(&dev->read_excl, 0);
+	atomic_set(&dev->write_excl, 0);
+
+	INIT_LIST_HEAD(&dev->tx_idle);
+
+	dev->cdev = c->cdev;
+	dev->function.name = "adb";
+	dev->function.descriptors = fs_adb_descs;
+	dev->function.hs_descriptors = hs_adb_descs;
+	dev->function.bind = adb_function_bind;
+	dev->function.unbind = adb_function_unbind;
+	dev->function.set_alt = adb_function_set_alt;
+	dev->function.disable = adb_function_disable;
+
+	/* start disabled */
+	dev->function.disabled = 1;
+
+	/* _adb_dev must be set before calling usb_gadget_register_driver */
+	_adb_dev = dev;
+
+	ret = misc_register(&adb_device);
+	if (ret)
+		goto err1;
+	ret = misc_register(&adb_enable_device);
+	if (ret)
+		goto err2;
+
+	ret = usb_add_function(c, &dev->function);
+	if (ret)
+		goto err3;
+
+	return 0;
+
+err3:
+	misc_deregister(&adb_enable_device);
+err2:
+	misc_deregister(&adb_device);
+err1:
+	kfree(dev);
+	printk(KERN_ERR "adb gadget driver failed to initialize\n");
+	return ret;
+}
+
+static struct android_usb_function adb_function = {
+	.name = "adb",
+	.bind_config = adb_bind_config,
+};
+
+static int __init init(void)
+{
+	printk(KERN_INFO "f_adb init\n");
+	android_register_function(&adb_function);
+	return 0;
+}
+module_init(init);
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
new file mode 100644
index 00000000000..72a6a1087aa
--- /dev/null
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -0,0 +1,3019 @@
+/*
+ * drivers/usb/gadget/f_mass_storage.c
+ *
+ * Function Driver for USB Mass Storage
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * Based heavily on the file_storage gadget driver in
+ * drivers/usb/gadget/file_storage.c and licensed under the same terms:
+ *
+ * Copyright (C) 2003-2007 Alan Stern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* #define DEBUG */
+/* #define VERBOSE_DEBUG */
+/* #define DUMP_MSGS */
+
+
+#include <linux/blkdev.h>
+#include <linux/completion.h>
+#include <linux/dcache.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/fcntl.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/kref.h>
+#include <linux/kthread.h>
+#include <linux/limits.h>
+#include <linux/rwsem.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/switch.h>
+#include <linux/freezer.h>
+#include <linux/utsname.h>
+#include <linux/wakelock.h>
+#include <linux/platform_device.h>
+
+#include <linux/usb.h>
+#include <linux/usb_usual.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/android_composite.h>
+
+#include "gadget_chips.h"
+
+
+#define BULK_BUFFER_SIZE           4096
+
+/* flush after every 4 meg of writes to avoid excessive block level caching */
+#define MAX_UNFLUSHED_BYTES (4 * 1024 * 1024)
+
+/*-------------------------------------------------------------------------*/
+
+#define DRIVER_NAME		"usb_mass_storage"
+#define MAX_LUNS		8
+
+static const char shortname[] = DRIVER_NAME;
+
+#ifdef DEBUG
+#define LDBG(lun, fmt, args...) \
+	dev_dbg(&(lun)->dev , fmt , ## args)
+#define MDBG(fmt,args...) \
+	printk(KERN_DEBUG DRIVER_NAME ": " fmt , ## args)
+#else
+#define LDBG(lun, fmt, args...) \
+	do { } while (0)
+#define MDBG(fmt,args...) \
+	do { } while (0)
+#undef VERBOSE_DEBUG
+#undef DUMP_MSGS
+#endif /* DEBUG */
+
+#ifdef VERBOSE_DEBUG
+#define VLDBG	LDBG
+#else
+#define VLDBG(lun, fmt, args...) \
+	do { } while (0)
+#endif /* VERBOSE_DEBUG */
+
+#define LERROR(lun, fmt, args...) \
+	dev_err(&(lun)->dev , fmt , ## args)
+#define LWARN(lun, fmt, args...) \
+	dev_warn(&(lun)->dev , fmt , ## args)
+#define LINFO(lun, fmt, args...) \
+	dev_info(&(lun)->dev , fmt , ## args)
+
+#define MINFO(fmt,args...) \
+	printk(KERN_INFO DRIVER_NAME ": " fmt , ## args)
+
+#undef DBG
+#undef VDBG
+#undef ERROR
+#undef WARNING
+#undef INFO
+#define DBG(d, fmt, args...) \
+	dev_dbg(&(d)->cdev->gadget->dev , fmt , ## args)
+#define VDBG(d, fmt, args...) \
+	dev_vdbg(&(d)->cdev->gadget->dev , fmt , ## args)
+#define ERROR(d, fmt, args...) \
+	dev_err(&(d)->cdev->gadget->dev , fmt , ## args)
+#define WARNING(d, fmt, args...) \
+	dev_warn(&(d)->cdev->gadget->dev , fmt , ## args)
+#define INFO(d, fmt, args...) \
+	dev_info(&(d)->cdev->gadget->dev , fmt , ## args)
+
+
+/*-------------------------------------------------------------------------*/
+
+/* Bulk-only data structures */
+
+/* Command Block Wrapper */
+struct bulk_cb_wrap {
+	__le32	Signature;		/* Contains 'USBC' */
+	u32	Tag;			/* Unique per command id */
+	__le32	DataTransferLength;	/* Size of the data */
+	u8	Flags;			/* Direction in bit 7 */
+	u8	Lun;			/* LUN (normally 0) */
+	u8	Length;			/* Of the CDB, <= MAX_COMMAND_SIZE */
+	u8	CDB[16];		/* Command Data Block */
+};
+
+#define USB_BULK_CB_WRAP_LEN	31
+#define USB_BULK_CB_SIG		0x43425355	/* Spells out USBC */
+#define USB_BULK_IN_FLAG	0x80
+
+/* Command Status Wrapper */
+struct bulk_cs_wrap {
+	__le32	Signature;		/* Should = 'USBS' */
+	u32	Tag;			/* Same as original command */
+	__le32	Residue;		/* Amount not transferred */
+	u8	Status;			/* See below */
+};
+
+#define USB_BULK_CS_WRAP_LEN	13
+#define USB_BULK_CS_SIG		0x53425355	/* Spells out 'USBS' */
+#define USB_STATUS_PASS		0
+#define USB_STATUS_FAIL		1
+#define USB_STATUS_PHASE_ERROR	2
+
+/* Bulk-only class specific requests */
+#define USB_BULK_RESET_REQUEST		0xff
+#define USB_BULK_GET_MAX_LUN_REQUEST	0xfe
+
+/* Length of a SCSI Command Data Block */
+#define MAX_COMMAND_SIZE	16
+
+/* SCSI commands that we recognize */
+#define SC_FORMAT_UNIT			0x04
+#define SC_INQUIRY			0x12
+#define SC_MODE_SELECT_6		0x15
+#define SC_MODE_SELECT_10		0x55
+#define SC_MODE_SENSE_6			0x1a
+#define SC_MODE_SENSE_10		0x5a
+#define SC_PREVENT_ALLOW_MEDIUM_REMOVAL	0x1e
+#define SC_READ_6			0x08
+#define SC_READ_10			0x28
+#define SC_READ_12			0xa8
+#define SC_READ_CAPACITY		0x25
+#define SC_READ_FORMAT_CAPACITIES	0x23
+#define SC_RELEASE			0x17
+#define SC_REQUEST_SENSE		0x03
+#define SC_RESERVE			0x16
+#define SC_SEND_DIAGNOSTIC		0x1d
+#define SC_START_STOP_UNIT		0x1b
+#define SC_SYNCHRONIZE_CACHE		0x35
+#define SC_TEST_UNIT_READY		0x00
+#define SC_VERIFY			0x2f
+#define SC_WRITE_6			0x0a
+#define SC_WRITE_10			0x2a
+#define SC_WRITE_12			0xaa
+
+/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */
+#define SS_NO_SENSE				0
+#define SS_COMMUNICATION_FAILURE		0x040800
+#define SS_INVALID_COMMAND			0x052000
+#define SS_INVALID_FIELD_IN_CDB			0x052400
+#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE	0x052100
+#define SS_LOGICAL_UNIT_NOT_SUPPORTED		0x052500
+#define SS_MEDIUM_NOT_PRESENT			0x023a00
+#define SS_MEDIUM_REMOVAL_PREVENTED		0x055302
+#define SS_NOT_READY_TO_READY_TRANSITION	0x062800
+#define SS_RESET_OCCURRED			0x062900
+#define SS_SAVING_PARAMETERS_NOT_SUPPORTED	0x053900
+#define SS_UNRECOVERED_READ_ERROR		0x031100
+#define SS_WRITE_ERROR				0x030c02
+#define SS_WRITE_PROTECTED			0x072700
+
+#define SK(x)		((u8) ((x) >> 16))	/* Sense Key byte, etc. */
+#define ASC(x)		((u8) ((x) >> 8))
+#define ASCQ(x)		((u8) (x))
+
+
+/*-------------------------------------------------------------------------*/
+
+struct lun {
+	struct file	*filp;
+	loff_t		file_length;
+	loff_t		num_sectors;
+	unsigned int unflushed_bytes;
+
+	unsigned int	ro : 1;
+	unsigned int	prevent_medium_removal : 1;
+	unsigned int	registered : 1;
+	unsigned int	info_valid : 1;
+
+	u32		sense_data;
+	u32		sense_data_info;
+	u32		unit_attention_data;
+
+	struct device	dev;
+};
+
+#define backing_file_is_open(curlun)	((curlun)->filp != NULL)
+
+
+static struct lun *dev_to_lun(struct device *dev)
+{
+	return container_of(dev, struct lun, dev);
+}
+
+/* Big enough to hold our biggest descriptor */
+#define EP0_BUFSIZE	256
+
+/* Number of buffers we will use.  2 is enough for double-buffering */
+#define NUM_BUFFERS	2
+
+enum fsg_buffer_state {
+	BUF_STATE_EMPTY = 0,
+	BUF_STATE_FULL,
+	BUF_STATE_BUSY
+};
+
+struct fsg_buffhd {
+	void				*buf;
+	enum fsg_buffer_state		state;
+	struct fsg_buffhd		*next;
+
+	/* The NetChip 2280 is faster, and handles some protocol faults
+	 * better, if we don't submit any short bulk-out read requests.
+	 * So we will record the intended request length here. */
+	unsigned int			bulk_out_intended_length;
+
+	struct usb_request		*inreq;
+	int				inreq_busy;
+	struct usb_request		*outreq;
+	int				outreq_busy;
+};
+
+enum fsg_state {
+	/* This one isn't used anywhere */
+	FSG_STATE_COMMAND_PHASE = -10,
+
+	FSG_STATE_DATA_PHASE,
+	FSG_STATE_STATUS_PHASE,
+
+	FSG_STATE_IDLE = 0,
+	FSG_STATE_ABORT_BULK_OUT,
+	FSG_STATE_RESET,
+	FSG_STATE_CONFIG_CHANGE,
+	FSG_STATE_EXIT,
+	FSG_STATE_TERMINATED
+};
+
+enum data_direction {
+	DATA_DIR_UNKNOWN = 0,
+	DATA_DIR_FROM_HOST,
+	DATA_DIR_TO_HOST,
+	DATA_DIR_NONE
+};
+
+struct fsg_dev {
+	struct usb_function function;
+	struct usb_composite_dev *cdev;
+
+	/* optional "usb_mass_storage" platform device */
+	struct platform_device *pdev;
+
+	/* lock protects: state and all the req_busy's */
+	spinlock_t		lock;
+
+	/* filesem protects: backing files in use */
+	struct rw_semaphore	filesem;
+
+	/* reference counting: wait until all LUNs are released */
+	struct kref		ref;
+
+	unsigned int		bulk_out_maxpacket;
+	enum fsg_state		state;		/* For exception handling */
+
+	u8			config, new_config;
+
+	unsigned int		running : 1;
+	unsigned int		bulk_in_enabled : 1;
+	unsigned int		bulk_out_enabled : 1;
+	unsigned int		phase_error : 1;
+	unsigned int		short_packet_received : 1;
+	unsigned int		bad_lun_okay : 1;
+
+	unsigned long		atomic_bitflags;
+#define REGISTERED		0
+#define CLEAR_BULK_HALTS	1
+#define SUSPENDED		2
+
+	struct usb_ep		*bulk_in;
+	struct usb_ep		*bulk_out;
+
+	struct fsg_buffhd	*next_buffhd_to_fill;
+	struct fsg_buffhd	*next_buffhd_to_drain;
+	struct fsg_buffhd	buffhds[NUM_BUFFERS];
+
+	int			thread_wakeup_needed;
+	struct completion	thread_notifier;
+	struct task_struct	*thread_task;
+
+	int			cmnd_size;
+	u8			cmnd[MAX_COMMAND_SIZE];
+	enum data_direction	data_dir;
+	u32			data_size;
+	u32			data_size_from_cmnd;
+	u32			tag;
+	unsigned int		lun;
+	u32			residue;
+	u32			usb_amount_left;
+
+	unsigned int		nluns;
+	struct lun		*luns;
+	struct lun		*curlun;
+
+	u32				buf_size;
+	const char		*vendor;
+	const char		*product;
+	int				release;
+
+	struct switch_dev sdev;
+
+	struct wake_lock wake_lock;
+};
+
+static inline struct fsg_dev *func_to_dev(struct usb_function *f)
+{
+	return container_of(f, struct fsg_dev, function);
+}
+
+static int exception_in_progress(struct fsg_dev *fsg)
+{
+	return (fsg->state > FSG_STATE_IDLE);
+}
+
+/* Make bulk-out requests be divisible by the maxpacket size */
+static void set_bulk_out_req_length(struct fsg_dev *fsg,
+		struct fsg_buffhd *bh, unsigned int length)
+{
+	unsigned int	rem;
+
+	bh->bulk_out_intended_length = length;
+	rem = length % fsg->bulk_out_maxpacket;
+	if (rem > 0)
+		length += fsg->bulk_out_maxpacket - rem;
+	bh->outreq->length = length;
+}
+
+static struct fsg_dev			*the_fsg;
+
+static void	close_backing_file(struct fsg_dev *fsg, struct lun *curlun);
+static void	close_all_backing_files(struct fsg_dev *fsg);
+static int fsync_sub(struct lun *curlun);
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DUMP_MSGS
+
+static void dump_msg(struct fsg_dev *fsg, const char *label,
+		const u8 *buf, unsigned int length)
+{
+	if (length < 512) {
+		DBG(fsg, "%s, length %u:\n", label, length);
+		print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET,
+				16, 1, buf, length, 0);
+	}
+}
+
+static void dump_cdb(struct fsg_dev *fsg)
+{}
+
+#else
+
+static void dump_msg(struct fsg_dev *fsg, const char *label,
+		const u8 *buf, unsigned int length)
+{}
+
+#ifdef VERBOSE_DEBUG
+
+static void dump_cdb(struct fsg_dev *fsg)
+{
+	print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE,
+			16, 1, fsg->cmnd, fsg->cmnd_size, 0);
+}
+
+#else
+
+static void dump_cdb(struct fsg_dev *fsg)
+{}
+
+#endif /* VERBOSE_DEBUG */
+#endif /* DUMP_MSGS */
+
+
+/*-------------------------------------------------------------------------*/
+
+/* Routines for unaligned data access */
+
+static u16 get_be16(u8 *buf)
+{
+	return ((u16) buf[0] << 8) | ((u16) buf[1]);
+}
+
+static u32 get_be32(u8 *buf)
+{
+	return ((u32) buf[0] << 24) | ((u32) buf[1] << 16) |
+			((u32) buf[2] << 8) | ((u32) buf[3]);
+}
+
+static void put_be16(u8 *buf, u16 val)
+{
+	buf[0] = val >> 8;
+	buf[1] = val;
+}
+
+static void put_be32(u8 *buf, u32 val)
+{
+	buf[0] = val >> 24;
+	buf[1] = val >> 16;
+	buf[2] = val >> 8;
+	buf[3] = val & 0xff;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * DESCRIPTORS ... most are static, but strings and (full) configuration
+ * descriptors are built on demand.  Also the (static) config and interface
+ * descriptors are adjusted during fsg_bind().
+ */
+
+/* There is only one interface. */
+
+static struct usb_interface_descriptor
+intf_desc = {
+	.bLength =		sizeof intf_desc,
+	.bDescriptorType =	USB_DT_INTERFACE,
+
+	.bNumEndpoints =	2,		/* Adjusted during fsg_bind() */
+	.bInterfaceClass =	USB_CLASS_MASS_STORAGE,
+	.bInterfaceSubClass =	US_SC_SCSI,
+	.bInterfaceProtocol =	US_PR_BULK,
+};
+
+/* Three full-speed endpoint descriptors: bulk-in, bulk-out,
+ * and interrupt-in. */
+
+static struct usb_endpoint_descriptor
+fs_bulk_in_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bEndpointAddress =	USB_DIR_IN,
+	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	/* wMaxPacketSize set by autoconfiguration */
+};
+
+static struct usb_endpoint_descriptor
+fs_bulk_out_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	.bEndpointAddress =	USB_DIR_OUT,
+	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	/* wMaxPacketSize set by autoconfiguration */
+};
+
+static struct usb_descriptor_header *fs_function[] = {
+	(struct usb_descriptor_header *) &intf_desc,
+	(struct usb_descriptor_header *) &fs_bulk_in_desc,
+	(struct usb_descriptor_header *) &fs_bulk_out_desc,
+	NULL,
+};
+#define FS_FUNCTION_PRE_EP_ENTRIES	2
+
+
+static struct usb_endpoint_descriptor
+hs_bulk_in_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	/* bEndpointAddress copied from fs_bulk_in_desc during fsg_bind() */
+	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor
+hs_bulk_out_desc = {
+	.bLength =		USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType =	USB_DT_ENDPOINT,
+
+	/* bEndpointAddress copied from fs_bulk_out_desc during fsg_bind() */
+	.bmAttributes =		USB_ENDPOINT_XFER_BULK,
+	.wMaxPacketSize =	__constant_cpu_to_le16(512),
+	.bInterval =		1,	/* NAK every 1 uframe */
+};
+
+
+static struct usb_descriptor_header *hs_function[] = {
+	(struct usb_descriptor_header *) &intf_desc,
+	(struct usb_descriptor_header *) &hs_bulk_in_desc,
+	(struct usb_descriptor_header *) &hs_bulk_out_desc,
+	NULL,
+};
+
+/* Maxpacket and other transfer characteristics vary by speed. */
+static struct usb_endpoint_descriptor *
+ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs,
+		struct usb_endpoint_descriptor *hs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* These routines may be called in process context or in_irq */
+
+/* Caller must hold fsg->lock */
+static void wakeup_thread(struct fsg_dev *fsg)
+{
+	/* Tell the main thread that something has happened */
+	fsg->thread_wakeup_needed = 1;
+	if (fsg->thread_task)
+		wake_up_process(fsg->thread_task);
+}
+
+
+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
+{
+	unsigned long		flags;
+
+	DBG(fsg, "raise_exception %d\n", (int)new_state);
+	/* Do nothing if a higher-priority exception is already in progress.
+	 * If a lower-or-equal priority exception is in progress, preempt it
+	 * and notify the main thread by sending it a signal. */
+	spin_lock_irqsave(&fsg->lock, flags);
+	if (fsg->state <= new_state) {
+		fsg->state = new_state;
+		if (fsg->thread_task)
+			send_sig_info(SIGUSR1, SEND_SIG_FORCED,
+					fsg->thread_task);
+	}
+	spin_unlock_irqrestore(&fsg->lock, flags);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* Bulk and interrupt endpoint completion handlers.
+ * These always run in_irq. */
+
+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	struct fsg_dev		*fsg = ep->driver_data;
+	struct fsg_buffhd	*bh = req->context;
+	unsigned long		flags;
+
+	if (req->status || req->actual != req->length)
+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
+				req->status, req->actual, req->length);
+
+	/* Hold the lock while we update the request and buffer states */
+	smp_wmb();
+	spin_lock_irqsave(&fsg->lock, flags);
+	bh->inreq_busy = 0;
+	bh->state = BUF_STATE_EMPTY;
+	wakeup_thread(fsg);
+	spin_unlock_irqrestore(&fsg->lock, flags);
+}
+
+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	struct fsg_dev		*fsg = ep->driver_data;
+	struct fsg_buffhd	*bh = req->context;
+	unsigned long		flags;
+
+	dump_msg(fsg, "bulk-out", req->buf, req->actual);
+	if (req->status || req->actual != bh->bulk_out_intended_length)
+		DBG(fsg, "%s --> %d, %u/%u\n", __func__,
+				req->status, req->actual,
+				bh->bulk_out_intended_length);
+
+	/* Hold the lock while we update the request and buffer states */
+	smp_wmb();
+	spin_lock_irqsave(&fsg->lock, flags);
+	bh->outreq_busy = 0;
+	bh->state = BUF_STATE_FULL;
+	wakeup_thread(fsg);
+	spin_unlock_irqrestore(&fsg->lock, flags);
+}
+
+static int fsg_function_setup(struct usb_function *f,
+					const struct usb_ctrlrequest *ctrl)
+{
+	struct fsg_dev	*fsg = func_to_dev(f);
+	struct usb_composite_dev *cdev = fsg->cdev;
+	int			value = -EOPNOTSUPP;
+	u16			w_index = le16_to_cpu(ctrl->wIndex);
+	u16			w_value = le16_to_cpu(ctrl->wValue);
+	u16			w_length = le16_to_cpu(ctrl->wLength);
+
+	DBG(fsg, "fsg_function_setup\n");
+	/* Handle Bulk-only class-specific requests */
+	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) {
+	DBG(fsg, "USB_TYPE_CLASS\n");
+		switch (ctrl->bRequest) {
+		case USB_BULK_RESET_REQUEST:
+			if (ctrl->bRequestType != (USB_DIR_OUT |
+					USB_TYPE_CLASS | USB_RECIP_INTERFACE))
+				break;
+			if (w_index != 0 || w_value != 0) {
+				value = -EDOM;
+				break;
+			}
+
+			/* Raise an exception to stop the current operation
+			 * and reinitialize our state. */
+			DBG(fsg, "bulk reset request\n");
+			raise_exception(fsg, FSG_STATE_RESET);
+			value = 0;
+			break;
+
+		case USB_BULK_GET_MAX_LUN_REQUEST:
+			if (ctrl->bRequestType != (USB_DIR_IN |
+					USB_TYPE_CLASS | USB_RECIP_INTERFACE))
+				break;
+			if (w_index != 0 || w_value != 0) {
+				value = -EDOM;
+				break;
+			}
+			VDBG(fsg, "get max LUN\n");
+			*(u8 *)cdev->req->buf = fsg->nluns - 1;
+			value = 1;
+			break;
+		}
+	}
+
+		/* respond with data transfer or status phase? */
+		if (value >= 0) {
+			int rc;
+			cdev->req->zero = value < w_length;
+			cdev->req->length = value;
+			rc = usb_ep_queue(cdev->gadget->ep0, cdev->req, GFP_ATOMIC);
+			if (rc < 0)
+				printk("%s setup response queue error\n", __func__);
+		}
+
+	if (value == -EOPNOTSUPP)
+		VDBG(fsg,
+			"unknown class-specific control req "
+			"%02x.%02x v%04x i%04x l%u\n",
+			ctrl->bRequestType, ctrl->bRequest,
+			le16_to_cpu(ctrl->wValue), w_index, w_length);
+	return value;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* All the following routines run in process context */
+
+
+/* Use this for bulk or interrupt transfers, not ep0 */
+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
+		struct usb_request *req, int *pbusy,
+		enum fsg_buffer_state *state)
+{
+	int	rc;
+	unsigned long		flags;
+
+	DBG(fsg, "start_transfer req: %p, req->buf: %p\n", req, req->buf);
+	if (ep == fsg->bulk_in)
+		dump_msg(fsg, "bulk-in", req->buf, req->length);
+
+	spin_lock_irqsave(&fsg->lock, flags);
+	*pbusy = 1;
+	*state = BUF_STATE_BUSY;
+	spin_unlock_irqrestore(&fsg->lock, flags);
+	rc = usb_ep_queue(ep, req, GFP_KERNEL);
+	if (rc != 0) {
+		*pbusy = 0;
+		*state = BUF_STATE_EMPTY;
+
+		/* We can't do much more than wait for a reset */
+
+		/* Note: currently the net2280 driver fails zero-length
+		 * submissions if DMA is enabled. */
+		if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
+						req->length == 0))
+			WARN(fsg, "error in submission: %s --> %d\n",
+				(ep == fsg->bulk_in ? "bulk-in" : "bulk-out"),
+				rc);
+	}
+}
+
+
+static int sleep_thread(struct fsg_dev *fsg)
+{
+	int	rc = 0;
+
+	/* Wait until a signal arrives or we are woken up */
+	for (;;) {
+		try_to_freeze();
+		set_current_state(TASK_INTERRUPTIBLE);
+		if (signal_pending(current)) {
+			rc = -EINTR;
+			break;
+		}
+		if (fsg->thread_wakeup_needed)
+			break;
+		schedule();
+	}
+	__set_current_state(TASK_RUNNING);
+	fsg->thread_wakeup_needed = 0;
+	return rc;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int do_read(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	u32			lba;
+	struct fsg_buffhd	*bh;
+	int			rc;
+	u32			amount_left;
+	loff_t			file_offset, file_offset_tmp;
+	unsigned int		amount;
+	unsigned int		partial_page;
+	ssize_t			nread;
+
+	/* Get the starting Logical Block Address and check that it's
+	 * not too big */
+	if (fsg->cmnd[0] == SC_READ_6)
+		lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+	else {
+		lba = get_be32(&fsg->cmnd[2]);
+
+		/* We allow DPO (Disable Page Out = don't save data in the
+		 * cache) and FUA (Force Unit Access = don't read from the
+		 * cache), but we don't implement them. */
+		if ((fsg->cmnd[1] & ~0x18) != 0) {
+			curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+			return -EINVAL;
+		}
+	}
+	if (lba >= curlun->num_sectors) {
+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+		return -EINVAL;
+	}
+	file_offset = ((loff_t) lba) << 9;
+
+	/* Carry out the file reads */
+	amount_left = fsg->data_size_from_cmnd;
+	if (unlikely(amount_left == 0))
+		return -EIO;		/* No default reply */
+
+	for (;;) {
+
+		/* Figure out how much we need to read:
+		 * Try to read the remaining amount.
+		 * But don't read more than the buffer size.
+		 * And don't try to read past the end of the file.
+		 * Finally, if we're not at a page boundary, don't read past
+		 *	the next page.
+		 * If this means reading 0 then we were asked to read past
+		 *	the end of file. */
+		amount = min((unsigned int) amount_left,
+				(unsigned int)fsg->buf_size);
+		amount = min((loff_t) amount,
+				curlun->file_length - file_offset);
+		partial_page = file_offset & (PAGE_CACHE_SIZE - 1);
+		if (partial_page > 0)
+			amount = min(amount, (unsigned int) PAGE_CACHE_SIZE -
+					partial_page);
+
+		/* Wait for the next buffer to become available */
+		bh = fsg->next_buffhd_to_fill;
+		while (bh->state != BUF_STATE_EMPTY) {
+			rc = sleep_thread(fsg);
+			if (rc)
+				return rc;
+		}
+
+		/* If we were asked to read past the end of file,
+		 * end with an empty buffer. */
+		if (amount == 0) {
+			curlun->sense_data =
+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+			curlun->sense_data_info = file_offset >> 9;
+			curlun->info_valid = 1;
+			bh->inreq->length = 0;
+			bh->state = BUF_STATE_FULL;
+			break;
+		}
+
+		/* Perform the read */
+		file_offset_tmp = file_offset;
+		nread = vfs_read(curlun->filp,
+				(char __user *) bh->buf,
+				amount, &file_offset_tmp);
+		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
+				(unsigned long long) file_offset,
+				(int) nread);
+		if (signal_pending(current))
+			return -EINTR;
+
+		if (nread < 0) {
+			LDBG(curlun, "error in file read: %d\n",
+					(int) nread);
+			nread = 0;
+		} else if (nread < amount) {
+			LDBG(curlun, "partial file read: %d/%u\n",
+					(int) nread, amount);
+			nread -= (nread & 511);	/* Round down to a block */
+		}
+		file_offset  += nread;
+		amount_left  -= nread;
+		fsg->residue -= nread;
+		bh->inreq->length = nread;
+		bh->state = BUF_STATE_FULL;
+
+		/* If an error occurred, report it and its position */
+		if (nread < amount) {
+			curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
+			curlun->sense_data_info = file_offset >> 9;
+			curlun->info_valid = 1;
+			break;
+		}
+
+		if (amount_left == 0)
+			break;		/* No more left to read */
+
+		/* Send this buffer and go read some more */
+		start_transfer(fsg, fsg->bulk_in, bh->inreq,
+				&bh->inreq_busy, &bh->state);
+		fsg->next_buffhd_to_fill = bh->next;
+	}
+
+	return -EIO;		/* No default reply */
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int do_write(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	u32			lba;
+	struct fsg_buffhd	*bh;
+	int			get_some_more;
+	u32			amount_left_to_req, amount_left_to_write;
+	loff_t			usb_offset, file_offset, file_offset_tmp;
+	unsigned int		amount;
+	unsigned int		partial_page;
+	ssize_t			nwritten;
+	int			rc;
+
+	if (curlun->ro) {
+		curlun->sense_data = SS_WRITE_PROTECTED;
+		return -EINVAL;
+	}
+	curlun->filp->f_flags &= ~O_SYNC;	/* Default is not to wait */
+
+	/* Get the starting Logical Block Address and check that it's
+	 * not too big */
+	if (fsg->cmnd[0] == SC_WRITE_6)
+		lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+	else {
+		lba = get_be32(&fsg->cmnd[2]);
+
+		/* We allow DPO (Disable Page Out = don't save data in the
+		 * cache) and FUA (Force Unit Access = write directly to the
+		 * medium).  We don't implement DPO; we implement FUA by
+		 * performing synchronous output. */
+		if ((fsg->cmnd[1] & ~0x18) != 0) {
+			curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+			return -EINVAL;
+		}
+		if (fsg->cmnd[1] & 0x08)	/* FUA */
+			curlun->filp->f_flags |= O_SYNC;
+	}
+	if (lba >= curlun->num_sectors) {
+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+		return -EINVAL;
+	}
+
+	/* Carry out the file writes */
+	get_some_more = 1;
+	file_offset = usb_offset = ((loff_t) lba) << 9;
+	amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
+
+	while (amount_left_to_write > 0) {
+
+		/* Queue a request for more data from the host */
+		bh = fsg->next_buffhd_to_fill;
+		if (bh->state == BUF_STATE_EMPTY && get_some_more) {
+
+			/* Figure out how much we want to get:
+			 * Try to get the remaining amount.
+			 * But don't get more than the buffer size.
+			 * And don't try to go past the end of the file.
+			 * If we're not at a page boundary,
+			 *	don't go past the next page.
+			 * If this means getting 0, then we were asked
+			 *	to write past the end of file.
+			 * Finally, round down to a block boundary. */
+			amount = min(amount_left_to_req, (u32)fsg->buf_size);
+			amount = min((loff_t) amount, curlun->file_length -
+					usb_offset);
+			partial_page = usb_offset & (PAGE_CACHE_SIZE - 1);
+			if (partial_page > 0)
+				amount = min(amount,
+	(unsigned int) PAGE_CACHE_SIZE - partial_page);
+
+			if (amount == 0) {
+				get_some_more = 0;
+				curlun->sense_data =
+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+				curlun->sense_data_info = usb_offset >> 9;
+				curlun->info_valid = 1;
+				continue;
+			}
+			amount -= (amount & 511);
+			if (amount == 0) {
+
+				/* Why were we were asked to transfer a
+				 * partial block? */
+				get_some_more = 0;
+				continue;
+			}
+
+			/* Get the next buffer */
+			usb_offset += amount;
+			fsg->usb_amount_left -= amount;
+			amount_left_to_req -= amount;
+			if (amount_left_to_req == 0)
+				get_some_more = 0;
+
+			/* amount is always divisible by 512, hence by
+			 * the bulk-out maxpacket size */
+			bh->outreq->length = bh->bulk_out_intended_length =
+					amount;
+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
+					&bh->outreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+			continue;
+		}
+
+		/* Write the received data to the backing file */
+		bh = fsg->next_buffhd_to_drain;
+		if (bh->state == BUF_STATE_EMPTY && !get_some_more)
+			break;			/* We stopped early */
+		if (bh->state == BUF_STATE_FULL) {
+			smp_rmb();
+			fsg->next_buffhd_to_drain = bh->next;
+			bh->state = BUF_STATE_EMPTY;
+
+			/* Did something go wrong with the transfer? */
+			if (bh->outreq->status != 0) {
+				curlun->sense_data = SS_COMMUNICATION_FAILURE;
+				curlun->sense_data_info = file_offset >> 9;
+				curlun->info_valid = 1;
+				break;
+			}
+
+			amount = bh->outreq->actual;
+			if (curlun->file_length - file_offset < amount) {
+				LERROR(curlun,
+	"write %u @ %llu beyond end %llu\n",
+	amount, (unsigned long long) file_offset,
+	(unsigned long long) curlun->file_length);
+				amount = curlun->file_length - file_offset;
+			}
+
+			/* Perform the write */
+			file_offset_tmp = file_offset;
+			nwritten = vfs_write(curlun->filp,
+					(char __user *) bh->buf,
+					amount, &file_offset_tmp);
+			VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
+					(unsigned long long) file_offset,
+					(int) nwritten);
+			if (signal_pending(current))
+				return -EINTR;		/* Interrupted! */
+
+			if (nwritten < 0) {
+				LDBG(curlun, "error in file write: %d\n",
+						(int) nwritten);
+				nwritten = 0;
+			} else if (nwritten < amount) {
+				LDBG(curlun, "partial file write: %d/%u\n",
+						(int) nwritten, amount);
+				nwritten -= (nwritten & 511);
+						/* Round down to a block */
+			}
+			file_offset += nwritten;
+			amount_left_to_write -= nwritten;
+			fsg->residue -= nwritten;
+
+#ifdef MAX_UNFLUSHED_BYTES
+			curlun->unflushed_bytes += nwritten;
+			if (curlun->unflushed_bytes >= MAX_UNFLUSHED_BYTES) {
+				fsync_sub(curlun);
+				curlun->unflushed_bytes = 0;
+			}
+#endif
+			/* If an error occurred, report it and its position */
+			if (nwritten < amount) {
+				curlun->sense_data = SS_WRITE_ERROR;
+				curlun->sense_data_info = file_offset >> 9;
+				curlun->info_valid = 1;
+				break;
+			}
+
+			/* Did the host decide to stop early? */
+			if (bh->outreq->actual != bh->outreq->length) {
+				fsg->short_packet_received = 1;
+				break;
+			}
+			continue;
+		}
+
+		/* Wait for something to happen */
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	return -EIO;		/* No default reply */
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* Sync the file data, don't bother with the metadata.
+ * The caller must own fsg->filesem.
+ * This code was copied from fs/buffer.c:sys_fdatasync(). */
+static int fsync_sub(struct lun *curlun)
+{
+	struct file	*filp = curlun->filp;
+	struct inode	*inode;
+	int		rc, err;
+
+	if (curlun->ro || !filp)
+		return 0;
+	if (!filp->f_op->fsync)
+		return -EINVAL;
+
+	inode = filp->f_path.dentry->d_inode;
+	mutex_lock(&inode->i_mutex);
+	rc = filemap_fdatawrite(inode->i_mapping);
+	err = filp->f_op->fsync(filp, filp->f_path.dentry, 1);
+	if (!rc)
+		rc = err;
+	err = filemap_fdatawait(inode->i_mapping);
+	if (!rc)
+		rc = err;
+	mutex_unlock(&inode->i_mutex);
+	VLDBG(curlun, "fdatasync -> %d\n", rc);
+	return rc;
+}
+
+static void fsync_all(struct fsg_dev *fsg)
+{
+	int	i;
+
+	for (i = 0; i < fsg->nluns; ++i)
+		fsync_sub(&fsg->luns[i]);
+}
+
+static int do_synchronize_cache(struct fsg_dev *fsg)
+{
+	struct lun	*curlun = fsg->curlun;
+	int		rc;
+
+	/* We ignore the requested LBA and write out all file's
+	 * dirty data buffers. */
+	rc = fsync_sub(curlun);
+	if (rc)
+		curlun->sense_data = SS_WRITE_ERROR;
+	return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static void invalidate_sub(struct lun *curlun)
+{
+	struct file	*filp = curlun->filp;
+	struct inode	*inode = filp->f_path.dentry->d_inode;
+	unsigned long	rc;
+
+	rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
+	VLDBG(curlun, "invalidate_inode_pages -> %ld\n", rc);
+}
+
+static int do_verify(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	u32			lba;
+	u32			verification_length;
+	struct fsg_buffhd	*bh = fsg->next_buffhd_to_fill;
+	loff_t			file_offset, file_offset_tmp;
+	u32			amount_left;
+	unsigned int		amount;
+	ssize_t			nread;
+
+	/* Get the starting Logical Block Address and check that it's
+	 * not too big */
+	lba = get_be32(&fsg->cmnd[2]);
+	if (lba >= curlun->num_sectors) {
+		curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+		return -EINVAL;
+	}
+
+	/* We allow DPO (Disable Page Out = don't save data in the
+	 * cache) but we don't implement it. */
+	if ((fsg->cmnd[1] & ~0x10) != 0) {
+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+		return -EINVAL;
+	}
+
+	verification_length = get_be16(&fsg->cmnd[7]);
+	if (unlikely(verification_length == 0))
+		return -EIO;		/* No default reply */
+
+	/* Prepare to carry out the file verify */
+	amount_left = verification_length << 9;
+	file_offset = ((loff_t) lba) << 9;
+
+	/* Write out all the dirty buffers before invalidating them */
+	fsync_sub(curlun);
+	if (signal_pending(current))
+		return -EINTR;
+
+	invalidate_sub(curlun);
+	if (signal_pending(current))
+		return -EINTR;
+
+	/* Just try to read the requested blocks */
+	while (amount_left > 0) {
+
+		/* Figure out how much we need to read:
+		 * Try to read the remaining amount, but not more than
+		 * the buffer size.
+		 * And don't try to read past the end of the file.
+		 * If this means reading 0 then we were asked to read
+		 * past the end of file. */
+		amount = min((unsigned int) amount_left,
+				(unsigned int)fsg->buf_size);
+		amount = min((loff_t) amount,
+				curlun->file_length - file_offset);
+		if (amount == 0) {
+			curlun->sense_data =
+					SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
+			curlun->sense_data_info = file_offset >> 9;
+			curlun->info_valid = 1;
+			break;
+		}
+
+		/* Perform the read */
+		file_offset_tmp = file_offset;
+		nread = vfs_read(curlun->filp,
+				(char __user *) bh->buf,
+				amount, &file_offset_tmp);
+		VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
+				(unsigned long long) file_offset,
+				(int) nread);
+		if (signal_pending(current))
+			return -EINTR;
+
+		if (nread < 0) {
+			LDBG(curlun, "error in file verify: %d\n",
+					(int) nread);
+			nread = 0;
+		} else if (nread < amount) {
+			LDBG(curlun, "partial file verify: %d/%u\n",
+					(int) nread, amount);
+			nread -= (nread & 511);	/* Round down to a sector */
+		}
+		if (nread == 0) {
+			curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
+			curlun->sense_data_info = file_offset >> 9;
+			curlun->info_valid = 1;
+			break;
+		}
+		file_offset += nread;
+		amount_left -= nread;
+	}
+	return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	u8	*buf = (u8 *) bh->buf;
+
+	if (!fsg->curlun) {		/* Unsupported LUNs are okay */
+		fsg->bad_lun_okay = 1;
+		memset(buf, 0, 36);
+		buf[0] = 0x7f;		/* Unsupported, no device-type */
+		return 36;
+	}
+
+	memset(buf, 0, 8);	/* Non-removable, direct-access device */
+
+	buf[1] = 0x80;	/* set removable bit */
+	buf[2] = 2;		/* ANSI SCSI level 2 */
+	buf[3] = 2;		/* SCSI-2 INQUIRY data format */
+	buf[4] = 31;		/* Additional length */
+				/* No special options */
+	sprintf(buf + 8, "%-8s%-16s%04x", fsg->vendor,
+			fsg->product, fsg->release);
+	return 36;
+}
+
+
+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	struct lun	*curlun = fsg->curlun;
+	u8		*buf = (u8 *) bh->buf;
+	u32		sd, sdinfo;
+	int		valid;
+
+	/*
+	 * From the SCSI-2 spec., section 7.9 (Unit attention condition):
+	 *
+	 * If a REQUEST SENSE command is received from an initiator
+	 * with a pending unit attention condition (before the target
+	 * generates the contingent allegiance condition), then the
+	 * target shall either:
+	 *   a) report any pending sense data and preserve the unit
+	 *	attention condition on the logical unit, or,
+	 *   b) report the unit attention condition, may discard any
+	 *	pending sense data, and clear the unit attention
+	 *	condition on the logical unit for that initiator.
+	 *
+	 * FSG normally uses option a); enable this code to use option b).
+	 */
+#if 0
+	if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
+		curlun->sense_data = curlun->unit_attention_data;
+		curlun->unit_attention_data = SS_NO_SENSE;
+	}
+#endif
+
+	if (!curlun) {		/* Unsupported LUNs are okay */
+		fsg->bad_lun_okay = 1;
+		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
+		sdinfo = 0;
+		valid = 0;
+	} else {
+		sd = curlun->sense_data;
+		sdinfo = curlun->sense_data_info;
+		valid = curlun->info_valid << 7;
+		curlun->sense_data = SS_NO_SENSE;
+		curlun->sense_data_info = 0;
+		curlun->info_valid = 0;
+	}
+
+	memset(buf, 0, 18);
+	buf[0] = valid | 0x70;			/* Valid, current error */
+	buf[2] = SK(sd);
+	put_be32(&buf[3], sdinfo);		/* Sense information */
+	buf[7] = 18 - 8;			/* Additional sense length */
+	buf[12] = ASC(sd);
+	buf[13] = ASCQ(sd);
+	return 18;
+}
+
+
+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	struct lun	*curlun = fsg->curlun;
+	u32		lba = get_be32(&fsg->cmnd[2]);
+	int		pmi = fsg->cmnd[8];
+	u8		*buf = (u8 *) bh->buf;
+
+	/* Check the PMI and LBA fields */
+	if (pmi > 1 || (pmi == 0 && lba != 0)) {
+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+		return -EINVAL;
+	}
+
+	put_be32(&buf[0], curlun->num_sectors - 1);	/* Max logical block */
+	put_be32(&buf[4], 512);				/* Block length */
+	return 8;
+}
+
+
+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	struct lun	*curlun = fsg->curlun;
+	int		mscmnd = fsg->cmnd[0];
+	u8		*buf = (u8 *) bh->buf;
+	u8		*buf0 = buf;
+	int		pc, page_code;
+	int		changeable_values, all_pages;
+	int		valid_page = 0;
+	int		len, limit;
+
+	if ((fsg->cmnd[1] & ~0x08) != 0) {		/* Mask away DBD */
+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+		return -EINVAL;
+	}
+	pc = fsg->cmnd[2] >> 6;
+	page_code = fsg->cmnd[2] & 0x3f;
+	if (pc == 3) {
+		curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
+		return -EINVAL;
+	}
+	changeable_values = (pc == 1);
+	all_pages = (page_code == 0x3f);
+
+	/* Write the mode parameter header.  Fixed values are: default
+	 * medium type, no cache control (DPOFUA), and no block descriptors.
+	 * The only variable value is the WriteProtect bit.  We will fill in
+	 * the mode data length later. */
+	memset(buf, 0, 8);
+	if (mscmnd == SC_MODE_SENSE_6) {
+		buf[2] = (curlun->ro ? 0x80 : 0x00);		/* WP, DPOFUA */
+		buf += 4;
+		limit = 255;
+	} else {			/* SC_MODE_SENSE_10 */
+		buf[3] = (curlun->ro ? 0x80 : 0x00);		/* WP, DPOFUA */
+		buf += 8;
+		limit = 65535;
+	}
+
+	/* No block descriptors */
+
+	/* Disabled to workaround USB reset problems with a Vista host.
+	 */
+#if 0
+	/* The mode pages, in numerical order.  The only page we support
+	 * is the Caching page. */
+	if (page_code == 0x08 || all_pages) {
+		valid_page = 1;
+		buf[0] = 0x08;		/* Page code */
+		buf[1] = 10;		/* Page length */
+		memset(buf+2, 0, 10);	/* None of the fields are changeable */
+
+		if (!changeable_values) {
+			buf[2] = 0x04;	/* Write cache enable, */
+					/* Read cache not disabled */
+					/* No cache retention priorities */
+			put_be16(&buf[4], 0xffff);  /* Don't disable prefetch */
+					/* Minimum prefetch = 0 */
+			put_be16(&buf[8], 0xffff);  /* Maximum prefetch */
+			/* Maximum prefetch ceiling */
+			put_be16(&buf[10], 0xffff);
+		}
+		buf += 12;
+	}
+#else
+	valid_page = 1;
+#endif
+
+	/* Check that a valid page was requested and the mode data length
+	 * isn't too long. */
+	len = buf - buf0;
+	if (!valid_page || len > limit) {
+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+		return -EINVAL;
+	}
+
+	/*  Store the mode data length */
+	if (mscmnd == SC_MODE_SENSE_6)
+		buf0[0] = len - 1;
+	else
+		put_be16(buf0, len - 2);
+	return len;
+}
+
+static int do_start_stop(struct fsg_dev *fsg)
+{
+	struct lun	*curlun = fsg->curlun;
+	int		loej, start;
+
+	/* int immed = fsg->cmnd[1] & 0x01; */
+	loej = fsg->cmnd[4] & 0x02;
+	start = fsg->cmnd[4] & 0x01;
+
+	if (loej) {
+		/* eject request from the host */
+		if (backing_file_is_open(curlun)) {
+			close_backing_file(fsg, curlun);
+			curlun->unit_attention_data = SS_MEDIUM_NOT_PRESENT;
+		}
+	}
+
+	return 0;
+}
+
+static int do_prevent_allow(struct fsg_dev *fsg)
+{
+	struct lun	*curlun = fsg->curlun;
+	int		prevent;
+
+	prevent = fsg->cmnd[4] & 0x01;
+	if ((fsg->cmnd[4] & ~0x01) != 0) {		/* Mask away Prevent */
+		curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+		return -EINVAL;
+	}
+
+	if (curlun->prevent_medium_removal && !prevent)
+		fsync_sub(curlun);
+	curlun->prevent_medium_removal = prevent;
+	return 0;
+}
+
+
+static int do_read_format_capacities(struct fsg_dev *fsg,
+			struct fsg_buffhd *bh)
+{
+	struct lun	*curlun = fsg->curlun;
+	u8		*buf = (u8 *) bh->buf;
+
+	buf[0] = buf[1] = buf[2] = 0;
+	buf[3] = 8;	/* Only the Current/Maximum Capacity Descriptor */
+	buf += 4;
+
+	put_be32(&buf[0], curlun->num_sectors);	/* Number of blocks */
+	put_be32(&buf[4], 512);				/* Block length */
+	buf[4] = 0x02;					/* Current capacity */
+	return 12;
+}
+
+
+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	struct lun	*curlun = fsg->curlun;
+
+	/* We don't support MODE SELECT */
+	curlun->sense_data = SS_INVALID_COMMAND;
+	return -EINVAL;
+}
+
+
+/*-------------------------------------------------------------------------*/
+#if 0
+static int write_zero(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	int			rc;
+
+	DBG(fsg, "write_zero\n");
+	/* Wait for the next buffer to become available */
+	bh = fsg->next_buffhd_to_fill;
+	while (bh->state != BUF_STATE_EMPTY) {
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	bh->inreq->length = 0;
+	start_transfer(fsg, fsg->bulk_in, bh->inreq,
+			&bh->inreq_busy, &bh->state);
+
+	fsg->next_buffhd_to_fill = bh->next;
+	return 0;
+}
+#endif
+
+static int throw_away_data(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	u32			amount;
+	int			rc;
+
+	DBG(fsg, "throw_away_data\n");
+	while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
+			fsg->usb_amount_left > 0) {
+
+		/* Throw away the data in a filled buffer */
+		if (bh->state == BUF_STATE_FULL) {
+			smp_rmb();
+			bh->state = BUF_STATE_EMPTY;
+			fsg->next_buffhd_to_drain = bh->next;
+
+			/* A short packet or an error ends everything */
+			if (bh->outreq->actual != bh->outreq->length ||
+					bh->outreq->status != 0) {
+				raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
+				return -EINTR;
+			}
+			continue;
+		}
+
+		/* Try to submit another request if we need one */
+		bh = fsg->next_buffhd_to_fill;
+		if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
+			amount = min(fsg->usb_amount_left, (u32) fsg->buf_size);
+
+			/* amount is always divisible by 512, hence by
+			 * the bulk-out maxpacket size */
+			bh->outreq->length = bh->bulk_out_intended_length =
+					amount;
+			start_transfer(fsg, fsg->bulk_out, bh->outreq,
+					&bh->outreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+			fsg->usb_amount_left -= amount;
+			continue;
+		}
+
+		/* Otherwise wait for something to happen */
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+	return 0;
+}
+
+
+static int finish_reply(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh = fsg->next_buffhd_to_fill;
+	int			rc = 0;
+
+	switch (fsg->data_dir) {
+	case DATA_DIR_NONE:
+		break;			/* Nothing to send */
+
+	case DATA_DIR_UNKNOWN:
+		rc = -EINVAL;
+		break;
+
+	/* All but the last buffer of data must have already been sent */
+	case DATA_DIR_TO_HOST:
+		if (fsg->data_size == 0)
+			;		/* Nothing to send */
+
+		/* If there's no residue, simply send the last buffer */
+		else if (fsg->residue == 0) {
+			start_transfer(fsg, fsg->bulk_in, bh->inreq,
+					&bh->inreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+		} else {
+			start_transfer(fsg, fsg->bulk_in, bh->inreq,
+					&bh->inreq_busy, &bh->state);
+			fsg->next_buffhd_to_fill = bh->next;
+#if 0
+			/* this is unnecessary, and was causing problems with MacOS */
+			if (bh->inreq->length > 0)
+				write_zero(fsg);
+#endif
+		}
+		break;
+
+	/* We have processed all we want from the data the host has sent.
+	 * There may still be outstanding bulk-out requests. */
+	case DATA_DIR_FROM_HOST:
+		if (fsg->residue == 0)
+			;		/* Nothing to receive */
+
+		/* Did the host stop sending unexpectedly early? */
+		else if (fsg->short_packet_received) {
+			raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
+			rc = -EINTR;
+		}
+
+		/* We haven't processed all the incoming data.  Even though
+		 * we may be allowed to stall, doing so would cause a race.
+		 * The controller may already have ACK'ed all the remaining
+		 * bulk-out packets, in which case the host wouldn't see a
+		 * STALL.  Not realizing the endpoint was halted, it wouldn't
+		 * clear the halt -- leading to problems later on. */
+#if 0
+		fsg_set_halt(fsg, fsg->bulk_out);
+		raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
+		rc = -EINTR;
+#endif
+
+		/* We can't stall.  Read in the excess data and throw it
+		 * all away. */
+		else
+			rc = throw_away_data(fsg);
+		break;
+	}
+	return rc;
+}
+
+
+static int send_status(struct fsg_dev *fsg)
+{
+	struct lun		*curlun = fsg->curlun;
+	struct fsg_buffhd	*bh;
+	int			rc;
+	u8			status = USB_STATUS_PASS;
+	u32			sd, sdinfo = 0;
+	struct bulk_cs_wrap	*csw;
+
+	DBG(fsg, "send_status\n");
+	/* Wait for the next buffer to become available */
+	bh = fsg->next_buffhd_to_fill;
+	while (bh->state != BUF_STATE_EMPTY) {
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+
+	if (curlun) {
+		sd = curlun->sense_data;
+		sdinfo = curlun->sense_data_info;
+	} else if (fsg->bad_lun_okay)
+		sd = SS_NO_SENSE;
+	else
+		sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
+
+	if (fsg->phase_error) {
+		DBG(fsg, "sending phase-error status\n");
+		status = USB_STATUS_PHASE_ERROR;
+		sd = SS_INVALID_COMMAND;
+	} else if (sd != SS_NO_SENSE) {
+		DBG(fsg, "sending command-failure status\n");
+		status = USB_STATUS_FAIL;
+		VDBG(fsg, "  sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
+				"  info x%x\n",
+				SK(sd), ASC(sd), ASCQ(sd), sdinfo);
+	}
+
+	csw = bh->buf;
+
+	/* Store and send the Bulk-only CSW */
+	csw->Signature = __constant_cpu_to_le32(USB_BULK_CS_SIG);
+	csw->Tag = fsg->tag;
+	csw->Residue = cpu_to_le32(fsg->residue);
+	csw->Status = status;
+
+	bh->inreq->length = USB_BULK_CS_WRAP_LEN;
+	start_transfer(fsg, fsg->bulk_in, bh->inreq,
+			&bh->inreq_busy, &bh->state);
+
+	fsg->next_buffhd_to_fill = bh->next;
+	return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* Check whether the command is properly formed and whether its data size
+ * and direction agree with the values we already have. */
+static int check_command(struct fsg_dev *fsg, int cmnd_size,
+		enum data_direction data_dir, unsigned int mask,
+		int needs_medium, const char *name)
+{
+	int			i;
+	int			lun = fsg->cmnd[1] >> 5;
+	static const char	dirletter[4] = {'u', 'o', 'i', 'n'};
+	char			hdlen[20];
+	struct lun		*curlun;
+
+	hdlen[0] = 0;
+	if (fsg->data_dir != DATA_DIR_UNKNOWN)
+		sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
+				fsg->data_size);
+	VDBG(fsg, "SCSI command: %s;  Dc=%d, D%c=%u;  Hc=%d%s\n",
+			name, cmnd_size, dirletter[(int) data_dir],
+			fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
+
+	/* We can't reply at all until we know the correct data direction
+	 * and size. */
+	if (fsg->data_size_from_cmnd == 0)
+		data_dir = DATA_DIR_NONE;
+	if (fsg->data_dir == DATA_DIR_UNKNOWN) {	/* CB or CBI */
+		fsg->data_dir = data_dir;
+		fsg->data_size = fsg->data_size_from_cmnd;
+
+	} else {					/* Bulk-only */
+		if (fsg->data_size < fsg->data_size_from_cmnd) {
+
+			/* Host data size < Device data size is a phase error.
+			 * Carry out the command, but only transfer as much
+			 * as we are allowed. */
+			DBG(fsg, "phase error 1\n");
+			fsg->data_size_from_cmnd = fsg->data_size;
+			fsg->phase_error = 1;
+		}
+	}
+	fsg->residue = fsg->usb_amount_left = fsg->data_size;
+
+	/* Conflicting data directions is a phase error */
+	if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
+		fsg->phase_error = 1;
+		DBG(fsg, "phase error 2\n");
+		return -EINVAL;
+	}
+
+	/* Verify the length of the command itself */
+	if (cmnd_size != fsg->cmnd_size) {
+
+		/* Special case workaround: MS-Windows issues REQUEST_SENSE
+		 * and INQUIRY commands with cbw->Length == 12 (it should be 6). */
+		if ((fsg->cmnd[0] == SC_REQUEST_SENSE && fsg->cmnd_size == 12)
+		 || (fsg->cmnd[0] == SC_INQUIRY && fsg->cmnd_size == 12))
+			cmnd_size = fsg->cmnd_size;
+		else {
+			fsg->phase_error = 1;
+			return -EINVAL;
+		}
+	}
+
+	/* Check that the LUN values are consistent */
+	if (fsg->lun != lun)
+		DBG(fsg, "using LUN %d from CBW, "
+				"not LUN %d from CDB\n",
+				fsg->lun, lun);
+
+	/* Check the LUN */
+	if (fsg->lun >= 0 && fsg->lun < fsg->nluns) {
+		fsg->curlun = curlun = &fsg->luns[fsg->lun];
+		if (fsg->cmnd[0] != SC_REQUEST_SENSE) {
+			curlun->sense_data = SS_NO_SENSE;
+			curlun->sense_data_info = 0;
+			curlun->info_valid = 0;
+		}
+	} else {
+		fsg->curlun = curlun = NULL;
+		fsg->bad_lun_okay = 0;
+
+		/* INQUIRY and REQUEST SENSE commands are explicitly allowed
+		 * to use unsupported LUNs; all others may not. */
+		if (fsg->cmnd[0] != SC_INQUIRY &&
+				fsg->cmnd[0] != SC_REQUEST_SENSE) {
+			DBG(fsg, "unsupported LUN %d\n", fsg->lun);
+			return -EINVAL;
+		}
+	}
+
+	/* If a unit attention condition exists, only INQUIRY and
+	 * REQUEST SENSE commands are allowed; anything else must fail. */
+	if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
+			fsg->cmnd[0] != SC_INQUIRY &&
+			fsg->cmnd[0] != SC_REQUEST_SENSE) {
+		curlun->sense_data = curlun->unit_attention_data;
+		curlun->unit_attention_data = SS_NO_SENSE;
+		return -EINVAL;
+	}
+
+	/* Check that only command bytes listed in the mask are non-zero */
+	fsg->cmnd[1] &= 0x1f;			/* Mask away the LUN */
+	for (i = 1; i < cmnd_size; ++i) {
+		if (fsg->cmnd[i] && !(mask & (1 << i))) {
+			if (curlun)
+				curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
+			DBG(fsg, "SS_INVALID_FIELD_IN_CDB\n");
+			return -EINVAL;
+		}
+	}
+
+	/* If the medium isn't mounted and the command needs to access
+	 * it, return an error. */
+	if (curlun && !backing_file_is_open(curlun) && needs_medium) {
+		curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
+		DBG(fsg, "SS_MEDIUM_NOT_PRESENT\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+
+static int do_scsi_command(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	int			rc;
+	int			reply = -EINVAL;
+	int			i;
+	static char		unknown[16];
+
+	dump_cdb(fsg);
+
+	/* Wait for the next buffer to become available for data or status */
+	bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
+	while (bh->state != BUF_STATE_EMPTY) {
+		rc = sleep_thread(fsg);
+		if (rc)
+			return rc;
+	}
+	fsg->phase_error = 0;
+	fsg->short_packet_received = 0;
+
+	down_read(&fsg->filesem);	/* We're using the backing file */
+	switch (fsg->cmnd[0]) {
+
+	case SC_INQUIRY:
+		fsg->data_size_from_cmnd = fsg->cmnd[4];
+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
+				(1<<4), 0,
+				"INQUIRY")) == 0)
+			reply = do_inquiry(fsg, bh);
+		break;
+
+	case SC_MODE_SELECT_6:
+		fsg->data_size_from_cmnd = fsg->cmnd[4];
+		if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
+				(1<<1) | (1<<4), 0,
+				"MODE SELECT(6)")) == 0)
+			reply = do_mode_select(fsg, bh);
+		break;
+
+	case SC_MODE_SELECT_10:
+		fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+		if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
+				(1<<1) | (3<<7), 0,
+				"MODE SELECT(10)")) == 0)
+			reply = do_mode_select(fsg, bh);
+		break;
+
+	case SC_MODE_SENSE_6:
+		fsg->data_size_from_cmnd = fsg->cmnd[4];
+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
+				(1<<1) | (1<<2) | (1<<4), 0,
+				"MODE SENSE(6)")) == 0)
+			reply = do_mode_sense(fsg, bh);
+		break;
+
+	case SC_MODE_SENSE_10:
+		fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+				(1<<1) | (1<<2) | (3<<7), 0,
+				"MODE SENSE(10)")) == 0)
+			reply = do_mode_sense(fsg, bh);
+		break;
+
+	case SC_PREVENT_ALLOW_MEDIUM_REMOVAL:
+		fsg->data_size_from_cmnd = 0;
+		if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
+				(1<<4), 0,
+				"PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
+			reply = do_prevent_allow(fsg);
+		break;
+
+	case SC_READ_6:
+		i = fsg->cmnd[4];
+		fsg->data_size_from_cmnd = (i == 0 ? 256 : i) << 9;
+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
+				(7<<1) | (1<<4), 1,
+				"READ(6)")) == 0)
+			reply = do_read(fsg);
+		break;
+
+	case SC_READ_10:
+		fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+				(1<<1) | (0xf<<2) | (3<<7), 1,
+				"READ(10)")) == 0)
+			reply = do_read(fsg);
+		break;
+
+	case SC_READ_12:
+		fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+		if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST,
+				(1<<1) | (0xf<<2) | (0xf<<6), 1,
+				"READ(12)")) == 0)
+			reply = do_read(fsg);
+		break;
+
+	case SC_READ_CAPACITY:
+		fsg->data_size_from_cmnd = 8;
+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+				(0xf<<2) | (1<<8), 1,
+				"READ CAPACITY")) == 0)
+			reply = do_read_capacity(fsg, bh);
+		break;
+
+	case SC_READ_FORMAT_CAPACITIES:
+		fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+		if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
+				(3<<7), 1,
+				"READ FORMAT CAPACITIES")) == 0)
+			reply = do_read_format_capacities(fsg, bh);
+		break;
+
+	case SC_REQUEST_SENSE:
+		fsg->data_size_from_cmnd = fsg->cmnd[4];
+		if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
+				(1<<4), 0,
+				"REQUEST SENSE")) == 0)
+			reply = do_request_sense(fsg, bh);
+		break;
+
+	case SC_START_STOP_UNIT:
+		fsg->data_size_from_cmnd = 0;
+		if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
+				(1<<1) | (1<<4), 0,
+				"START-STOP UNIT")) == 0)
+			reply = do_start_stop(fsg);
+		break;
+
+	case SC_SYNCHRONIZE_CACHE:
+		fsg->data_size_from_cmnd = 0;
+		if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
+				(0xf<<2) | (3<<7), 1,
+				"SYNCHRONIZE CACHE")) == 0)
+			reply = do_synchronize_cache(fsg);
+		break;
+
+	case SC_TEST_UNIT_READY:
+		fsg->data_size_from_cmnd = 0;
+		reply = check_command(fsg, 6, DATA_DIR_NONE,
+				0, 1,
+				"TEST UNIT READY");
+		break;
+
+	/* Although optional, this command is used by MS-Windows.  We
+	 * support a minimal version: BytChk must be 0. */
+	case SC_VERIFY:
+		fsg->data_size_from_cmnd = 0;
+		if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
+				(1<<1) | (0xf<<2) | (3<<7), 1,
+				"VERIFY")) == 0)
+			reply = do_verify(fsg);
+		break;
+
+	case SC_WRITE_6:
+		i = fsg->cmnd[4];
+		fsg->data_size_from_cmnd = (i == 0 ? 256 : i) << 9;
+		if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
+				(7<<1) | (1<<4), 1,
+				"WRITE(6)")) == 0)
+			reply = do_write(fsg);
+		break;
+
+	case SC_WRITE_10:
+		fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+		if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
+				(1<<1) | (0xf<<2) | (3<<7), 1,
+				"WRITE(10)")) == 0)
+			reply = do_write(fsg);
+		break;
+
+	case SC_WRITE_12:
+		fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+		if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST,
+				(1<<1) | (0xf<<2) | (0xf<<6), 1,
+				"WRITE(12)")) == 0)
+			reply = do_write(fsg);
+		break;
+
+	/* Some mandatory commands that we recognize but don't implement.
+	 * They don't mean much in this setting.  It's left as an exercise
+	 * for anyone interested to implement RESERVE and RELEASE in terms
+	 * of Posix locks. */
+	case SC_FORMAT_UNIT:
+	case SC_RELEASE:
+	case SC_RESERVE:
+	case SC_SEND_DIAGNOSTIC:
+		/* Fall through */
+
+	default:
+		fsg->data_size_from_cmnd = 0;
+		sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
+		if ((reply = check_command(fsg, fsg->cmnd_size,
+				DATA_DIR_UNKNOWN, 0xff, 0, unknown)) == 0) {
+			fsg->curlun->sense_data = SS_INVALID_COMMAND;
+			reply = -EINVAL;
+		}
+		break;
+	}
+	up_read(&fsg->filesem);
+
+	VDBG(fsg, "reply: %d, fsg->data_size_from_cmnd: %d\n",
+			reply, fsg->data_size_from_cmnd);
+	if (reply == -EINTR || signal_pending(current))
+		return -EINTR;
+
+	/* Set up the single reply buffer for finish_reply() */
+	if (reply == -EINVAL)
+		reply = 0;		/* Error reply length */
+	if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
+		reply = min((u32) reply, fsg->data_size_from_cmnd);
+		bh->inreq->length = reply;
+		bh->state = BUF_STATE_FULL;
+		fsg->residue -= reply;
+	}				/* Otherwise it's already set */
+
+	return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
+{
+	struct usb_request	*req = bh->outreq;
+	struct bulk_cb_wrap	*cbw = req->buf;
+
+	/* Was this a real packet? */
+	if (req->status)
+		return -EINVAL;
+
+	/* Is the CBW valid? */
+	if (req->actual != USB_BULK_CB_WRAP_LEN ||
+			cbw->Signature != __constant_cpu_to_le32(
+				USB_BULK_CB_SIG)) {
+		DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
+				req->actual,
+				le32_to_cpu(cbw->Signature));
+		return -EINVAL;
+	}
+
+	/* Is the CBW meaningful? */
+	if (cbw->Lun >= MAX_LUNS || cbw->Flags & ~USB_BULK_IN_FLAG ||
+			cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
+		DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
+				"cmdlen %u\n",
+				cbw->Lun, cbw->Flags, cbw->Length);
+		return -EINVAL;
+	}
+
+	/* Save the command for later */
+	fsg->cmnd_size = cbw->Length;
+	memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
+	if (cbw->Flags & USB_BULK_IN_FLAG)
+		fsg->data_dir = DATA_DIR_TO_HOST;
+	else
+		fsg->data_dir = DATA_DIR_FROM_HOST;
+	fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
+	if (fsg->data_size == 0)
+		fsg->data_dir = DATA_DIR_NONE;
+	fsg->lun = cbw->Lun;
+	fsg->tag = cbw->Tag;
+	return 0;
+}
+
+
+static int get_next_command(struct fsg_dev *fsg)
+{
+	struct fsg_buffhd	*bh;
+	int			rc = 0;
+
+	/* Wait for the next buffer to become available */
+	bh = fsg->next_buffhd_to_fill;
+	while (bh->state != BUF_STATE_EMPTY) {
+		rc = sleep_thread(fsg);
+		if (rc) {
+			usb_ep_dequeue(fsg->bulk_out, bh->outreq);
+			bh->outreq_busy = 0;
+			bh->state = BUF_STATE_EMPTY;
+			return rc;
+		}
+	}
+
+	/* Queue a request to read a Bulk-only CBW */
+	set_bulk_out_req_length(fsg, bh, USB_BULK_CB_WRAP_LEN);
+	start_transfer(fsg, fsg->bulk_out, bh->outreq,
+			&bh->outreq_busy, &bh->state);
+
+	/* We will drain the buffer in software, which means we
+	 * can reuse it for the next filling.  No need to advance
+	 * next_buffhd_to_fill. */
+
+	/* Wait for the CBW to arrive */
+	while (bh->state != BUF_STATE_FULL) {
+		rc = sleep_thread(fsg);
+		if (rc) {
+			usb_ep_dequeue(fsg->bulk_out, bh->outreq);
+			bh->outreq_busy = 0;
+			bh->state = BUF_STATE_EMPTY;
+			return rc;
+		}
+	}
+	smp_rmb();
+	rc = received_cbw(fsg, bh);
+	bh->state = BUF_STATE_EMPTY;
+
+	return rc;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *d)
+{
+	int	rc;
+
+	DBG(fsg, "usb_ep_enable %s\n", ep->name);
+	ep->driver_data = fsg;
+	rc = usb_ep_enable(ep, d);
+	if (rc)
+		ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
+	return rc;
+}
+
+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
+		struct usb_request **preq)
+{
+	*preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
+	if (*preq)
+		return 0;
+	ERROR(fsg, "can't allocate request for %s\n", ep->name);
+	return -ENOMEM;
+}
+
+/*
+ * Reset interface setting and re-init endpoint state (toggle etc).
+ * Call with altsetting < 0 to disable the interface.  The only other
+ * available altsetting is 0, which enables the interface.
+ */
+static int do_set_interface(struct fsg_dev *fsg, int altsetting)
+{
+	struct usb_composite_dev *cdev = fsg->cdev;
+	int	rc = 0;
+	int	i;
+	const struct usb_endpoint_descriptor	*d;
+
+	if (fsg->running)
+		DBG(fsg, "reset interface\n");
+reset:
+	 /* Disable the endpoints */
+	if (fsg->bulk_in_enabled) {
+		DBG(fsg, "usb_ep_disable %s\n", fsg->bulk_in->name);
+		usb_ep_disable(fsg->bulk_in);
+		fsg->bulk_in_enabled = 0;
+	}
+	if (fsg->bulk_out_enabled) {
+		DBG(fsg, "usb_ep_disable %s\n", fsg->bulk_out->name);
+		usb_ep_disable(fsg->bulk_out);
+		fsg->bulk_out_enabled = 0;
+	}
+
+	/* Deallocate the requests */
+	for (i = 0; i < NUM_BUFFERS; ++i) {
+		struct fsg_buffhd *bh = &fsg->buffhds[i];
+		if (bh->inreq) {
+			usb_ep_free_request(fsg->bulk_in, bh->inreq);
+			bh->inreq = NULL;
+		}
+		if (bh->outreq) {
+			usb_ep_free_request(fsg->bulk_out, bh->outreq);
+			bh->outreq = NULL;
+		}
+	}
+
+
+	fsg->running = 0;
+	if (altsetting < 0 || rc != 0)
+		return rc;
+
+	DBG(fsg, "set interface %d\n", altsetting);
+
+	/* Enable the endpoints */
+	d = ep_desc(cdev->gadget, &fs_bulk_in_desc, &hs_bulk_in_desc);
+	if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
+		goto reset;
+	fsg->bulk_in_enabled = 1;
+
+	d = ep_desc(cdev->gadget, &fs_bulk_out_desc, &hs_bulk_out_desc);
+	if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
+		goto reset;
+	fsg->bulk_out_enabled = 1;
+	fsg->bulk_out_maxpacket = le16_to_cpu(d->wMaxPacketSize);
+
+	/* Allocate the requests */
+	for (i = 0; i < NUM_BUFFERS; ++i) {
+		struct fsg_buffhd	*bh = &fsg->buffhds[i];
+
+		rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq);
+		if (rc != 0)
+			goto reset;
+		rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq);
+		if (rc != 0)
+			goto reset;
+		bh->inreq->buf = bh->outreq->buf = bh->buf;
+		bh->inreq->context = bh->outreq->context = bh;
+		bh->inreq->complete = bulk_in_complete;
+		bh->outreq->complete = bulk_out_complete;
+	}
+
+	fsg->running = 1;
+	for (i = 0; i < fsg->nluns; ++i)
+		fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
+
+	return rc;
+}
+
+static void adjust_wake_lock(struct fsg_dev *fsg)
+{
+	int ums_active = 0;
+	int i;
+	unsigned long		flags;
+
+	spin_lock_irqsave(&fsg->lock, flags);
+
+	if (fsg->config) {
+		for (i = 0; i < fsg->nluns; ++i) {
+			if (backing_file_is_open(&fsg->luns[i]))
+				ums_active = 1;
+		}
+	}
+
+	if (ums_active)
+		wake_lock(&fsg->wake_lock);
+	else
+		wake_unlock(&fsg->wake_lock);
+
+	spin_unlock_irqrestore(&fsg->lock, flags);
+}
+
+/*
+ * Change our operational configuration.  This code must agree with the code
+ * that returns config descriptors, and with interface altsetting code.
+ *
+ * It's also responsible for power management interactions.  Some
+ * configurations might not work with our current power sources.
+ * For now we just assume the gadget is always self-powered.
+ */
+static int do_set_config(struct fsg_dev *fsg, u8 new_config)
+{
+	int	rc = 0;
+
+	/* Disable the single interface */
+	if (fsg->config != 0) {
+		DBG(fsg, "reset config\n");
+		fsg->config = 0;
+		rc = do_set_interface(fsg, -1);
+	}
+
+	/* Enable the interface */
+	if (new_config != 0) {
+		fsg->config = new_config;
+		if ((rc = do_set_interface(fsg, 0)) != 0)
+			fsg->config = 0;	// Reset on errors
+	}
+
+	switch_set_state(&fsg->sdev, new_config);
+	adjust_wake_lock(fsg);
+	return rc;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static void handle_exception(struct fsg_dev *fsg)
+{
+	siginfo_t		info;
+	int			sig;
+	int			i;
+	int			num_active;
+	struct fsg_buffhd	*bh;
+	enum fsg_state		old_state;
+	u8			new_config;
+	struct lun		*curlun;
+	int			rc;
+	unsigned long		flags;
+
+	DBG(fsg, "handle_exception state: %d\n", (int)fsg->state);
+	/* Clear the existing signals.  Anything but SIGUSR1 is converted
+	 * into a high-priority EXIT exception. */
+	for (;;) {
+		sig = dequeue_signal_lock(current, &current->blocked, &info);
+		if (!sig)
+			break;
+		if (sig != SIGUSR1) {
+			if (fsg->state < FSG_STATE_EXIT)
+				DBG(fsg, "Main thread exiting on signal\n");
+			raise_exception(fsg, FSG_STATE_EXIT);
+		}
+	}
+
+	/* Cancel all the pending transfers */
+	for (i = 0; i < NUM_BUFFERS; ++i) {
+		bh = &fsg->buffhds[i];
+		if (bh->inreq_busy)
+			usb_ep_dequeue(fsg->bulk_in, bh->inreq);
+		if (bh->outreq_busy)
+			usb_ep_dequeue(fsg->bulk_out, bh->outreq);
+	}
+
+	/* Wait until everything is idle */
+	for (;;) {
+		num_active = 0;
+		for (i = 0; i < NUM_BUFFERS; ++i) {
+			bh = &fsg->buffhds[i];
+			num_active += bh->outreq_busy;
+		}
+		if (num_active == 0)
+			break;
+		if (sleep_thread(fsg))
+			return;
+	}
+
+	/*
+	* Do NOT flush the fifo after set_interface()
+	* Otherwise, it results in some data being lost
+	*/
+	if ((fsg->state != FSG_STATE_CONFIG_CHANGE) ||
+		(fsg->new_config != 1))   {
+		/* Clear out the controller's fifos */
+		if (fsg->bulk_in_enabled)
+			usb_ep_fifo_flush(fsg->bulk_in);
+		if (fsg->bulk_out_enabled)
+			usb_ep_fifo_flush(fsg->bulk_out);
+	}
+	/* Reset the I/O buffer states and pointers, the SCSI
+	 * state, and the exception.  Then invoke the handler. */
+	spin_lock_irqsave(&fsg->lock, flags);
+
+	for (i = 0; i < NUM_BUFFERS; ++i) {
+		bh = &fsg->buffhds[i];
+		bh->state = BUF_STATE_EMPTY;
+	}
+	fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
+			&fsg->buffhds[0];
+
+	new_config = fsg->new_config;
+	old_state = fsg->state;
+
+	if (old_state == FSG_STATE_ABORT_BULK_OUT)
+		fsg->state = FSG_STATE_STATUS_PHASE;
+	else {
+		for (i = 0; i < fsg->nluns; ++i) {
+			curlun = &fsg->luns[i];
+			curlun->prevent_medium_removal = 0;
+			curlun->sense_data = curlun->unit_attention_data =
+					SS_NO_SENSE;
+			curlun->sense_data_info = 0;
+			curlun->info_valid = 0;
+		}
+		fsg->state = FSG_STATE_IDLE;
+	}
+	spin_unlock_irqrestore(&fsg->lock, flags);
+
+	/* Carry out any extra actions required for the exception */
+	switch (old_state) {
+	default:
+		break;
+
+	case FSG_STATE_ABORT_BULK_OUT:
+		DBG(fsg, "FSG_STATE_ABORT_BULK_OUT\n");
+		spin_lock_irqsave(&fsg->lock, flags);
+		if (fsg->state == FSG_STATE_STATUS_PHASE)
+			fsg->state = FSG_STATE_IDLE;
+		spin_unlock_irqrestore(&fsg->lock, flags);
+		break;
+
+	case FSG_STATE_RESET:
+		/* really not much to do here */
+		break;
+
+	case FSG_STATE_CONFIG_CHANGE:
+		rc = do_set_config(fsg, new_config);
+		if (new_config == 0) {
+			/* We're using the backing file */
+			down_read(&fsg->filesem);
+			fsync_all(fsg);
+			up_read(&fsg->filesem);
+		}
+		break;
+
+	case FSG_STATE_EXIT:
+	case FSG_STATE_TERMINATED:
+		do_set_config(fsg, 0);			/* Free resources */
+		spin_lock_irqsave(&fsg->lock, flags);
+		fsg->state = FSG_STATE_TERMINATED;	/* Stop the thread */
+		spin_unlock_irqrestore(&fsg->lock, flags);
+		break;
+	}
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int fsg_main_thread(void *fsg_)
+{
+	struct fsg_dev		*fsg = fsg_;
+	unsigned long		flags;
+
+	/* Allow the thread to be killed by a signal, but set the signal mask
+	 * to block everything but INT, TERM, KILL, and USR1. */
+	allow_signal(SIGINT);
+	allow_signal(SIGTERM);
+	allow_signal(SIGKILL);
+	allow_signal(SIGUSR1);
+
+	/* Allow the thread to be frozen */
+	set_freezable();
+
+	/* Arrange for userspace references to be interpreted as kernel
+	 * pointers.  That way we can pass a kernel pointer to a routine
+	 * that expects a __user pointer and it will work okay. */
+	set_fs(get_ds());
+
+	/* The main loop */
+	while (fsg->state != FSG_STATE_TERMINATED) {
+		if (exception_in_progress(fsg) || signal_pending(current)) {
+			handle_exception(fsg);
+			continue;
+		}
+
+		if (!fsg->running) {
+			sleep_thread(fsg);
+			continue;
+		}
+
+		if (get_next_command(fsg))
+			continue;
+
+		spin_lock_irqsave(&fsg->lock, flags);
+		if (!exception_in_progress(fsg))
+			fsg->state = FSG_STATE_DATA_PHASE;
+		spin_unlock_irqrestore(&fsg->lock, flags);
+
+		if (do_scsi_command(fsg) || finish_reply(fsg))
+			continue;
+
+		spin_lock_irqsave(&fsg->lock, flags);
+		if (!exception_in_progress(fsg))
+			fsg->state = FSG_STATE_STATUS_PHASE;
+		spin_unlock_irqrestore(&fsg->lock, flags);
+
+		if (send_status(fsg))
+			continue;
+
+		spin_lock_irqsave(&fsg->lock, flags);
+		if (!exception_in_progress(fsg))
+			fsg->state = FSG_STATE_IDLE;
+		spin_unlock_irqrestore(&fsg->lock, flags);
+	}
+
+	spin_lock_irqsave(&fsg->lock, flags);
+	fsg->thread_task = NULL;
+	spin_unlock_irqrestore(&fsg->lock, flags);
+
+	/* In case we are exiting because of a signal, unregister the
+	 * gadget driver and close the backing file. */
+	if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
+		close_all_backing_files(fsg);
+
+	/* Let the unbind and cleanup routines know the thread has exited */
+	complete_and_exit(&fsg->thread_notifier, 0);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* If the next two routines are called while the gadget is registered,
+ * the caller must own fsg->filesem for writing. */
+
+static int open_backing_file(struct fsg_dev *fsg, struct lun *curlun,
+	const char *filename)
+{
+	int				ro;
+	struct file			*filp = NULL;
+	int				rc = -EINVAL;
+	struct inode			*inode = NULL;
+	loff_t				size;
+	loff_t				num_sectors;
+
+	/* R/W if we can, R/O if we must */
+	ro = curlun->ro;
+	if (!ro) {
+		filp = filp_open(filename, O_RDWR | O_LARGEFILE, 0);
+		if (-EROFS == PTR_ERR(filp))
+			ro = 1;
+	}
+	if (ro)
+		filp = filp_open(filename, O_RDONLY | O_LARGEFILE, 0);
+	if (IS_ERR(filp)) {
+		LINFO(curlun, "unable to open backing file: %s\n", filename);
+		return PTR_ERR(filp);
+	}
+
+	if (!(filp->f_mode & FMODE_WRITE))
+		ro = 1;
+
+	if (filp->f_path.dentry)
+		inode = filp->f_path.dentry->d_inode;
+	if (inode && S_ISBLK(inode->i_mode)) {
+		if (bdev_read_only(inode->i_bdev))
+			ro = 1;
+	} else if (!inode || !S_ISREG(inode->i_mode)) {
+		LINFO(curlun, "invalid file type: %s\n", filename);
+		goto out;
+	}
+
+	/* If we can't read the file, it's no good.
+	 * If we can't write the file, use it read-only. */
+	if (!filp->f_op || !(filp->f_op->read || filp->f_op->aio_read)) {
+		LINFO(curlun, "file not readable: %s\n", filename);
+		goto out;
+	}
+	if (!(filp->f_op->write || filp->f_op->aio_write))
+		ro = 1;
+
+	size = i_size_read(inode->i_mapping->host);
+	if (size < 0) {
+		LINFO(curlun, "unable to find file size: %s\n", filename);
+		rc = (int) size;
+		goto out;
+	}
+	num_sectors = size >> 9;	/* File size in 512-byte sectors */
+	if (num_sectors == 0) {
+		LINFO(curlun, "file too small: %s\n", filename);
+		rc = -ETOOSMALL;
+		goto out;
+	}
+
+	get_file(filp);
+	curlun->ro = ro;
+	curlun->filp = filp;
+	curlun->file_length = size;
+	curlun->unflushed_bytes = 0;
+	curlun->num_sectors = num_sectors;
+	LDBG(curlun, "open backing file: %s size: %lld num_sectors: %lld\n",
+			filename, size, num_sectors);
+	rc = 0;
+	adjust_wake_lock(fsg);
+
+out:
+	filp_close(filp, current->files);
+	return rc;
+}
+
+
+static void close_backing_file(struct fsg_dev *fsg, struct lun *curlun)
+{
+	if (curlun->filp) {
+		int rc;
+
+		/*
+		 * XXX: San: Ugly hack here added to ensure that
+		 * our pages get synced to disk.
+		 * Also drop caches here just to be extra-safe
+		 */
+		rc = vfs_fsync(curlun->filp, curlun->filp->f_path.dentry, 1);
+		if (rc < 0)
+			printk(KERN_ERR "ums: Error syncing data (%d)\n", rc);
+		/* drop_pagecache and drop_slab are no longer available */
+		/* drop_pagecache(); */
+		/* drop_slab(); */
+
+		LDBG(curlun, "close backing file\n");
+		fput(curlun->filp);
+		curlun->filp = NULL;
+		adjust_wake_lock(fsg);
+	}
+}
+
+static void close_all_backing_files(struct fsg_dev *fsg)
+{
+	int	i;
+
+	for (i = 0; i < fsg->nluns; ++i)
+		close_backing_file(fsg, &fsg->luns[i]);
+}
+
+static ssize_t show_file(struct device *dev, struct device_attribute *attr,
+		char *buf)
+{
+	struct lun	*curlun = dev_to_lun(dev);
+	struct fsg_dev	*fsg = dev_get_drvdata(dev);
+	char		*p;
+	ssize_t		rc;
+
+	down_read(&fsg->filesem);
+	if (backing_file_is_open(curlun)) {	/* Get the complete pathname */
+		p = d_path(&curlun->filp->f_path, buf, PAGE_SIZE - 1);
+		if (IS_ERR(p))
+			rc = PTR_ERR(p);
+		else {
+			rc = strlen(p);
+			memmove(buf, p, rc);
+			buf[rc] = '\n';		/* Add a newline */
+			buf[++rc] = 0;
+		}
+	} else {				/* No file, return 0 bytes */
+		*buf = 0;
+		rc = 0;
+	}
+	up_read(&fsg->filesem);
+	return rc;
+}
+
+static ssize_t store_file(struct device *dev, struct device_attribute *attr,
+		const char *buf, size_t count)
+{
+	struct lun	*curlun = dev_to_lun(dev);
+	struct fsg_dev	*fsg = dev_get_drvdata(dev);
+	int		rc = 0;
+
+	DBG(fsg, "store_file: \"%s\"\n", buf);
+#if 0
+	/* disabled because we need to allow closing the backing file if the media was removed */
+	if (curlun->prevent_medium_removal && backing_file_is_open(curlun)) {
+		LDBG(curlun, "eject attempt prevented\n");
+		return -EBUSY;				/* "Door is locked" */
+	}
+#endif
+
+	/* Remove a trailing newline */
+	if (count > 0 && buf[count-1] == '\n')
+		((char *) buf)[count-1] = 0;
+
+	/* Eject current medium */
+	down_write(&fsg->filesem);
+	if (backing_file_is_open(curlun)) {
+		close_backing_file(fsg, curlun);
+		curlun->unit_attention_data = SS_MEDIUM_NOT_PRESENT;
+	}
+
+	/* Load new medium */
+	if (count > 0 && buf[0]) {
+		rc = open_backing_file(fsg, curlun, buf);
+		if (rc == 0)
+			curlun->unit_attention_data =
+					SS_NOT_READY_TO_READY_TRANSITION;
+	}
+	up_write(&fsg->filesem);
+	return (rc < 0 ? rc : count);
+}
+
+
+static DEVICE_ATTR(file, 0444, show_file, store_file);
+
+/*-------------------------------------------------------------------------*/
+
+static void fsg_release(struct kref *ref)
+{
+	struct fsg_dev	*fsg = container_of(ref, struct fsg_dev, ref);
+
+	kfree(fsg->luns);
+	kfree(fsg);
+}
+
+static void lun_release(struct device *dev)
+{
+	struct fsg_dev	*fsg = dev_get_drvdata(dev);
+
+	kref_put(&fsg->ref, fsg_release);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+static int __init fsg_alloc(void)
+{
+	struct fsg_dev		*fsg;
+
+	fsg = kzalloc(sizeof *fsg, GFP_KERNEL);
+	if (!fsg)
+		return -ENOMEM;
+	spin_lock_init(&fsg->lock);
+	init_rwsem(&fsg->filesem);
+	kref_init(&fsg->ref);
+	init_completion(&fsg->thread_notifier);
+
+	the_fsg = fsg;
+	return 0;
+}
+
+static ssize_t print_switch_name(struct switch_dev *sdev, char *buf)
+{
+	return sprintf(buf, "%s\n", DRIVER_NAME);
+}
+
+static ssize_t print_switch_state(struct switch_dev *sdev, char *buf)
+{
+	struct fsg_dev	*fsg = container_of(sdev, struct fsg_dev, sdev);
+	return sprintf(buf, "%s\n", (fsg->config ? "online" : "offline"));
+}
+
+static void
+fsg_function_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct fsg_dev	*fsg = func_to_dev(f);
+	int			i;
+	struct lun		*curlun;
+
+	DBG(fsg, "fsg_function_unbind\n");
+	clear_bit(REGISTERED, &fsg->atomic_bitflags);
+
+	/* Unregister the sysfs attribute files and the LUNs */
+	for (i = 0; i < fsg->nluns; ++i) {
+		curlun = &fsg->luns[i];
+		if (curlun->registered) {
+			device_remove_file(&curlun->dev, &dev_attr_file);
+			device_unregister(&curlun->dev);
+			curlun->registered = 0;
+		}
+	}
+
+	/* If the thread isn't already dead, tell it to exit now */
+	if (fsg->state != FSG_STATE_TERMINATED) {
+		raise_exception(fsg, FSG_STATE_EXIT);
+		wait_for_completion(&fsg->thread_notifier);
+
+		/* The cleanup routine waits for this completion also */
+		complete(&fsg->thread_notifier);
+	}
+
+	/* Free the data buffers */
+	for (i = 0; i < NUM_BUFFERS; ++i)
+		kfree(fsg->buffhds[i].buf);
+	switch_dev_unregister(&fsg->sdev);
+}
+
+static int
+fsg_function_bind(struct usb_configuration *c, struct usb_function *f)
+{
+	struct usb_composite_dev *cdev = c->cdev;
+	struct fsg_dev	*fsg = func_to_dev(f);
+	int			rc;
+	int			i;
+	int			id;
+	struct lun		*curlun;
+	struct usb_ep		*ep;
+	char			*pathbuf, *p;
+
+	fsg->cdev = cdev;
+	DBG(fsg, "fsg_function_bind\n");
+
+	dev_attr_file.attr.mode = 0644;
+
+	/* Find out how many LUNs there should be */
+	i = fsg->nluns;
+	if (i == 0)
+		i = 1;
+	if (i > MAX_LUNS) {
+		ERROR(fsg, "invalid number of LUNs: %d\n", i);
+		rc = -EINVAL;
+		goto out;
+	}
+
+	/* Create the LUNs, open their backing files, and register the
+	 * LUN devices in sysfs. */
+	fsg->luns = kzalloc(i * sizeof(struct lun), GFP_KERNEL);
+	if (!fsg->luns) {
+		rc = -ENOMEM;
+		goto out;
+	}
+	fsg->nluns = i;
+
+	for (i = 0; i < fsg->nluns; ++i) {
+		curlun = &fsg->luns[i];
+		curlun->ro = 0;
+		curlun->dev.release = lun_release;
+		/* use "usb_mass_storage" platform device as parent if available */
+		if (fsg->pdev)
+			curlun->dev.parent = &fsg->pdev->dev;
+		else
+			curlun->dev.parent = &cdev->gadget->dev;
+		dev_set_drvdata(&curlun->dev, fsg);
+		dev_set_name(&curlun->dev,"lun%d", i);
+
+		rc = device_register(&curlun->dev);
+		if (rc != 0) {
+			INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
+			goto out;
+		}
+		rc = device_create_file(&curlun->dev, &dev_attr_file);
+		if (rc != 0) {
+			ERROR(fsg, "device_create_file failed: %d\n", rc);
+			device_unregister(&curlun->dev);
+			goto out;
+		}
+		curlun->registered = 1;
+		kref_get(&fsg->ref);
+	}
+
+	/* allocate interface ID(s) */
+	id = usb_interface_id(c, f);
+	if (id < 0)
+		return id;
+	intf_desc.bInterfaceNumber = id;
+
+	ep = usb_ep_autoconfig(cdev->gadget, &fs_bulk_in_desc);
+	if (!ep)
+		goto autoconf_fail;
+	ep->driver_data = fsg;		/* claim the endpoint */
+	fsg->bulk_in = ep;
+
+	ep = usb_ep_autoconfig(cdev->gadget, &fs_bulk_out_desc);
+	if (!ep)
+		goto autoconf_fail;
+	ep->driver_data = fsg;		/* claim the endpoint */
+	fsg->bulk_out = ep;
+
+	rc = -ENOMEM;
+
+	if (gadget_is_dualspeed(cdev->gadget)) {
+		/* Assume endpoint addresses are the same for both speeds */
+		hs_bulk_in_desc.bEndpointAddress =
+				fs_bulk_in_desc.bEndpointAddress;
+		hs_bulk_out_desc.bEndpointAddress =
+				fs_bulk_out_desc.bEndpointAddress;
+
+		f->hs_descriptors = hs_function;
+	}
+
+	/* Allocate the data buffers */
+	for (i = 0; i < NUM_BUFFERS; ++i) {
+		struct fsg_buffhd	*bh = &fsg->buffhds[i];
+
+		/* Allocate for the bulk-in endpoint.  We assume that
+		 * the buffer will also work with the bulk-out (and
+		 * interrupt-in) endpoint. */
+		bh->buf = kmalloc(fsg->buf_size, GFP_KERNEL);
+		if (!bh->buf)
+			goto out;
+		bh->next = bh + 1;
+	}
+	fsg->buffhds[NUM_BUFFERS - 1].next = &fsg->buffhds[0];
+
+	fsg->thread_task = kthread_create(fsg_main_thread, fsg,
+			shortname);
+	if (IS_ERR(fsg->thread_task)) {
+		rc = PTR_ERR(fsg->thread_task);
+		ERROR(fsg, "kthread_create failed: %d\n", rc);
+		goto out;
+	}
+
+	INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
+
+	pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
+	for (i = 0; i < fsg->nluns; ++i) {
+		curlun = &fsg->luns[i];
+		if (backing_file_is_open(curlun)) {
+			p = NULL;
+			if (pathbuf) {
+				p = d_path(&curlun->filp->f_path,
+					   pathbuf, PATH_MAX);
+				if (IS_ERR(p))
+					p = NULL;
+			}
+			LINFO(curlun, "ro=%d, file: %s\n",
+					curlun->ro, (p ? p : "(error)"));
+		}
+	}
+	kfree(pathbuf);
+
+	set_bit(REGISTERED, &fsg->atomic_bitflags);
+
+	/* Tell the thread to start working */
+	wake_up_process(fsg->thread_task);
+	return 0;
+
+autoconf_fail:
+	ERROR(fsg, "unable to autoconfigure all endpoints\n");
+	rc = -ENOTSUPP;
+
+out:
+	DBG(fsg, "fsg_function_bind failed: %d\n", rc);
+	fsg->state = FSG_STATE_TERMINATED;	/* The thread is dead */
+	fsg_function_unbind(c, f);
+	close_all_backing_files(fsg);
+	return rc;
+}
+
+static int fsg_function_set_alt(struct usb_function *f,
+		unsigned intf, unsigned alt)
+{
+	struct fsg_dev	*fsg = func_to_dev(f);
+	DBG(fsg, "fsg_function_set_alt intf: %d alt: %d\n", intf, alt);
+	fsg->new_config = 1;
+	raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
+	return 0;
+}
+
+static void fsg_function_disable(struct usb_function *f)
+{
+	struct fsg_dev	*fsg = func_to_dev(f);
+	DBG(fsg, "fsg_function_disable\n");
+	fsg->new_config = 0;
+	raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
+}
+
+static int __init fsg_probe(struct platform_device *pdev)
+{
+	struct usb_mass_storage_platform_data *pdata = pdev->dev.platform_data;
+	struct fsg_dev *fsg = the_fsg;
+
+	fsg->pdev = pdev;
+	printk(KERN_INFO "fsg_probe pdata: %p\n", pdata);
+
+	if (pdata) {
+		if (pdata->vendor)
+			fsg->vendor = pdata->vendor;
+
+		if (pdata->product)
+			fsg->product = pdata->product;
+
+		if (pdata->release)
+			fsg->release = pdata->release;
+		fsg->nluns = pdata->nluns;
+	}
+
+	return 0;
+}
+
+static struct platform_driver fsg_platform_driver = {
+	.driver = { .name = "usb_mass_storage", },
+	.probe = fsg_probe,
+};
+
+int mass_storage_bind_config(struct usb_configuration *c)
+{
+	int		rc;
+	struct fsg_dev	*fsg;
+
+	printk(KERN_INFO "mass_storage_bind_config\n");
+	rc = fsg_alloc();
+	if (rc)
+		return rc;
+	fsg = the_fsg;
+
+	spin_lock_init(&fsg->lock);
+	init_rwsem(&fsg->filesem);
+	kref_init(&fsg->ref);
+	init_completion(&fsg->thread_notifier);
+
+	the_fsg->buf_size = BULK_BUFFER_SIZE;
+	the_fsg->sdev.name = DRIVER_NAME;
+	the_fsg->sdev.print_name = print_switch_name;
+	the_fsg->sdev.print_state = print_switch_state;
+	rc = switch_dev_register(&the_fsg->sdev);
+	if (rc < 0)
+		goto err_switch_dev_register;
+
+	rc = platform_driver_register(&fsg_platform_driver);
+	if (rc != 0)
+		goto err_platform_driver_register;
+
+	wake_lock_init(&the_fsg->wake_lock, WAKE_LOCK_SUSPEND,
+			   "usb_mass_storage");
+
+	fsg->cdev = c->cdev;
+	fsg->function.name = shortname;
+	fsg->function.descriptors = fs_function;
+	fsg->function.bind = fsg_function_bind;
+	fsg->function.unbind = fsg_function_unbind;
+	fsg->function.setup = fsg_function_setup;
+	fsg->function.set_alt = fsg_function_set_alt;
+	fsg->function.disable = fsg_function_disable;
+
+	rc = usb_add_function(c, &fsg->function);
+	if (rc != 0)
+		goto err_usb_add_function;
+
+
+	return 0;
+
+err_usb_add_function:
+	wake_lock_destroy(&the_fsg->wake_lock);
+	platform_driver_unregister(&fsg_platform_driver);
+err_platform_driver_register:
+	switch_dev_unregister(&the_fsg->sdev);
+err_switch_dev_register:
+	kref_put(&the_fsg->ref, fsg_release);
+
+	return rc;
+}
+
+static struct android_usb_function mass_storage_function = {
+	.name = "usb_mass_storage",
+	.bind_config = mass_storage_bind_config,
+};
+
+static int __init init(void)
+{
+	printk(KERN_INFO "f_mass_storage init\n");
+	android_register_function(&mass_storage_function);
+	return 0;
+}
+module_init(init);
+
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index c9966cc07d3..8486ade79e4 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -23,8 +23,9 @@
 /* #define VERBOSE_DEBUG */
 
 #include <linux/kernel.h>
-#include <linux/device.h>
+#include <linux/platform_device.h>
 #include <linux/etherdevice.h>
+#include <linux/usb/android_composite.h>
 
 #include <asm/atomic.h>
 
@@ -126,9 +127,16 @@ static struct usb_interface_descriptor rndis_control_intf __initdata = {
 	/* .bInterfaceNumber = DYNAMIC */
 	/* status endpoint is optional; this could be patched later */
 	.bNumEndpoints =	1,
+#ifdef CONFIG_USB_ANDROID_RNDIS_WCEIS
+	/* "Wireless" RNDIS; auto-detected by Windows */
+	.bInterfaceClass =	USB_CLASS_WIRELESS_CONTROLLER,
+	.bInterfaceSubClass = 1,
+	.bInterfaceProtocol =	3,
+#else
 	.bInterfaceClass =	USB_CLASS_COMM,
 	.bInterfaceSubClass =   USB_CDC_SUBCLASS_ACM,
 	.bInterfaceProtocol =   USB_CDC_ACM_PROTO_VENDOR,
+#endif
 	/* .iInterface = DYNAMIC */
 };
 
@@ -284,6 +292,10 @@ static struct usb_gadget_strings *rndis_strings[] = {
 	NULL,
 };
 
+#ifdef CONFIG_USB_ANDROID_RNDIS
+static struct usb_ether_platform_data *rndis_pdata;
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static struct sk_buff *rndis_add_header(struct gether *port,
@@ -467,10 +479,10 @@ static int rndis_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
 			usb_ep_disable(rndis->notify);
 		} else {
 			VDBG(cdev, "init rndis ctrl %d\n", intf);
-			rndis->notify_desc = ep_choose(cdev->gadget,
-					rndis->hs.notify,
-					rndis->fs.notify);
 		}
+		rndis->notify_desc = ep_choose(cdev->gadget,
+				rndis->hs.notify,
+				rndis->fs.notify);
 		usb_ep_enable(rndis->notify, rndis->notify_desc);
 		rndis->notify->driver_data = rndis;
 
@@ -484,11 +496,11 @@ static int rndis_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
 
 		if (!rndis->port.in) {
 			DBG(cdev, "init rndis\n");
-			rndis->port.in = ep_choose(cdev->gadget,
-					rndis->hs.in, rndis->fs.in);
-			rndis->port.out = ep_choose(cdev->gadget,
-					rndis->hs.out, rndis->fs.out);
 		}
+		rndis->port.in = ep_choose(cdev->gadget,
+				rndis->hs.in, rndis->fs.in);
+		rndis->port.out = ep_choose(cdev->gadget,
+				rndis->hs.out, rndis->fs.out);
 
 		/* Avoid ZLPs; they can be troublesome. */
 		rndis->port.is_zlp_ok = false;
@@ -686,11 +698,12 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
 	rndis_set_param_medium(rndis->config, NDIS_MEDIUM_802_3, 0);
 	rndis_set_host_mac(rndis->config, rndis->ethaddr);
 
-#if 0
-// FIXME
-	if (rndis_set_param_vendor(rndis->config, vendorID,
-				manufacturer))
-		goto fail0;
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	if (rndis_pdata) {
+		if (rndis_set_param_vendor(rndis->config, rndis_pdata->vendorID,
+					rndis_pdata->vendorDescr))
+			goto fail;
+	}
 #endif
 
 	/* NOTE:  all that is done without knowing or caring about
@@ -825,6 +838,11 @@ int __init rndis_bind_config(struct usb_configuration *c, u8 ethaddr[ETH_ALEN])
 	rndis->port.func.setup = rndis_setup;
 	rndis->port.func.disable = rndis_disable;
 
+#ifdef CONFIG_USB_ANDROID_RNDIS
+	/* start disabled */
+	rndis->port.func.disabled = 1;
+#endif
+
 	status = usb_add_function(c, &rndis->port.func);
 	if (status) {
 		kfree(rndis);
@@ -833,3 +851,54 @@ fail:
 	}
 	return status;
 }
+
+#ifdef CONFIG_USB_ANDROID_RNDIS
+#include "rndis.c"
+
+static int __init rndis_probe(struct platform_device *pdev)
+{
+	rndis_pdata = pdev->dev.platform_data;
+	return 0;
+}
+
+static struct platform_driver rndis_platform_driver = {
+	.driver = { .name = "rndis", },
+	.probe = rndis_probe,
+};
+
+int rndis_function_bind_config(struct usb_configuration *c)
+{
+	int ret;
+
+	if (!rndis_pdata) {
+		printk(KERN_ERR "rndis_pdata null in rndis_function_bind_config\n");
+		return -1;
+	}
+
+	printk(KERN_INFO
+		"rndis_function_bind_config MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
+		rndis_pdata->ethaddr[0], rndis_pdata->ethaddr[1],
+		rndis_pdata->ethaddr[2], rndis_pdata->ethaddr[3],
+		rndis_pdata->ethaddr[4], rndis_pdata->ethaddr[5]);
+
+	ret = gether_setup(c->cdev->gadget, rndis_pdata->ethaddr);
+	if (ret == 0)
+		ret = rndis_bind_config(c, rndis_pdata->ethaddr);
+	return ret;
+}
+
+static struct android_usb_function rndis_function = {
+	.name = "rndis",
+	.bind_config = rndis_function_bind_config,
+};
+
+static int __init init(void)
+{
+	printk(KERN_INFO "f_rndis init\n");
+	platform_driver_register(&rndis_platform_driver);
+	android_register_function(&rndis_function);
+	return 0;
+}
+module_init(init);
+
+#endif /* CONFIG_USB_ANDROID_RNDIS */
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 1e6aa504d58..a6c1657f2fa 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -375,7 +375,7 @@ static struct {
 	.vendor			= DRIVER_VENDOR_ID,
 	.product		= DRIVER_PRODUCT_ID,
 	.release		= 0xffff,	// Use controller chip type
-	.buflen			= 16384,
+	.buflen			= 65536,
 	};
 
 
@@ -398,6 +398,12 @@ MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
 module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
 MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
 
+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
+MODULE_PARM_DESC(vendor, "USB Vendor ID");
+
+module_param_named(product, mod_data.product, ushort, S_IRUGO);
+MODULE_PARM_DESC(product, "USB Product ID");
+
 
 /* In the non-TEST version, only the module parameters listed above
  * are available. */
@@ -521,6 +527,11 @@ struct interrupt_data {
 #define SC_WRITE_10			0x2a
 #define SC_WRITE_12			0xaa
 
+//modified by anyka Zhang Jingyuan
+#define SCSI_EXT_USB_UPDATE		0xcc
+#define SCSI_ANYKA_UBOOT		0xf1
+//end of modified by anyka Zhang Jingyuan
+
 /* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */
 #define SS_NO_SENSE				0
 #define SS_COMMUNICATION_FAILURE		0x040800
@@ -1861,6 +1872,7 @@ static int do_write(struct fsg_dev *fsg)
 	return -EIO;		// No default reply
 }
 
+#include "ak98-udc/anyka_usbburn.c"		//modified by anyka Zhang Jingyuan
 
 /*-------------------------------------------------------------------------*/
 
@@ -3031,6 +3043,30 @@ static int do_scsi_command(struct fsg_dev *fsg)
 			reply = do_write(fsg);
 		break;
 
+	//modified by anyka Zhang Jingyuan
+	case SCSI_EXT_USB_UPDATE:
+		fsg->data_size_from_cmnd = 0;
+		reply = check_command(fsg, 16, DATA_DIR_NONE,
+				0xffff, 1,
+				"SCSI EXT USB UPDATE");
+		reply = usbburn_write(fsg->cmnd, 16 + 8);
+		break;
+
+	case SCSI_ANYKA_UBOOT:
+		fsg->data_size_from_cmnd = fsg->data_size;
+		if ((reply = check_anyka_command(fsg, 1)) == 0)
+			reply = usbburn_write(fsg->cmnd, 16 + 8);
+		if (fsg->data_size_from_cmnd > 0) {
+			if (fsg->data_dir == DATA_DIR_TO_HOST)
+				reply = do_anyka_read(fsg);
+			else
+				reply = do_anyka_write(fsg);
+		}
+		down(&sense_data_lock);
+		fsg->curlun->sense_data = sense_data;
+		break;
+	//end of modified by anyka Zhang Jingyuan
+
 	/* Some mandatory commands that we recognize but don't implement.
 	 * They don't mean much in this setting.  It's left as an exercise
 	 * for anyone interested to implement RESERVE and RELEASE in terms
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index f2d270b202f..c2f735c818d 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -179,6 +179,12 @@
 #define	gadget_is_r8a66597(g)	0
 #endif
 
+#if defined(CONFIG_USB_GADGET_AK98) || defined(CONFIG_USB_GADGET_AK98_PRODUCER)
+#define gadget_is_ak980x(g)	!strcmp("ak98_udc", (g)->name)
+#else
+#define gadget_is_ak980x(g)	0
+#endif
+
 
 /**
  * usb_gadget_controller_number - support bcdDevice id convention
@@ -247,6 +253,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x24;
 	else if (gadget_is_r8a66597(gadget))
 		return 0x25;
+	else if (gadget_is_ak980x(gadget))
+		return 0x26;
 	return -ENOENT;
 }
 
diff --git a/drivers/usb/gadget/u_ether.c b/drivers/usb/gadget/u_ether.c
index 2fc02bd9584..a082dd5a3e9 100644
--- a/drivers/usb/gadget/u_ether.c
+++ b/drivers/usb/gadget/u_ether.c
@@ -941,7 +941,6 @@ void gether_disconnect(struct gether *link)
 	struct eth_dev		*dev = link->ioport;
 	struct usb_request	*req;
 
-	WARN_ON(!dev);
 	if (!dev)
 		return;
 
diff --git a/drivers/usb/gadget/u_ether.h b/drivers/usb/gadget/u_ether.h
index 91b39ffdf6e..82b30b5de26 100644
--- a/drivers/usb/gadget/u_ether.h
+++ b/drivers/usb/gadget/u_ether.h
@@ -112,7 +112,7 @@ int geth_bind_config(struct usb_configuration *c, u8 ethaddr[ETH_ALEN]);
 int ecm_bind_config(struct usb_configuration *c, u8 ethaddr[ETH_ALEN]);
 int eem_bind_config(struct usb_configuration *c);
 
-#ifdef CONFIG_USB_ETH_RNDIS
+#if defined(CONFIG_USB_ETH_RNDIS) || defined(CONFIG_USB_ANDROID_RNDIS)
 
 int rndis_bind_config(struct usb_configuration *c, u8 ethaddr[ETH_ALEN]);
 
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 9b43b226817..b87a32d88ff 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -332,6 +332,19 @@ config USB_SL811_HCD
 	  To compile this driver as a module, choose M here: the
 	  module will be called sl811-hcd.
 
+config USB_AK98_FS_HCD
+	tristate "AK98 USB Full Speed HCD support"
+	depends on USB
+	---help---
+	  The AK98XX chips inner USB full speed host controllers. Enable this
+	  option if your board has this chip. If unsure, say N.
+
+	  This driver does not support isochronous transfers.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called ak98-fs-hcd.
+
+
 config USB_SL811_CS
 	tristate "CF/PCMCIA support for SL811HS HCD"
 	depends on USB_SL811_HCD && PCMCIA
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index f58b2494c44..d14bbc4f3b0 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_USB_UHCI_HCD)	+= uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)	+= fhci.o
 obj-$(CONFIG_USB_XHCI_HCD)	+= xhci.o
 obj-$(CONFIG_USB_SL811_HCD)	+= sl811-hcd.o
+obj-$(CONFIG_USB_AK98_FS_HCD)	+= ak98-fs-hcd.o
 obj-$(CONFIG_USB_SL811_CS)	+= sl811_cs.o
 obj-$(CONFIG_USB_U132_HCD)	+= u132-hcd.o
 obj-$(CONFIG_USB_R8A66597_HCD)	+= r8a66597-hcd.o
diff --git a/drivers/usb/host/ak98-fs-hcd.c b/drivers/usb/host/ak98-fs-hcd.c
new file mode 100644
index 00000000000..25e5f3ebb1d
--- /dev/null
+++ b/drivers/usb/host/ak98-fs-hcd.c
@@ -0,0 +1,1854 @@
+/*
+ * AK98xx FS HCD (Full-Speed Host Controller Driver) for USB.
+ *
+ * Derived from the SL811 HCD, rewritten for AK98FS HCD.
+ * Copyright (C) 2010 ANYKA LTD.
+ *
+ * Periodic scheduling is based on Roman's OHCI code
+ * 	Copyright (C) 1999 Roman Weissgaerber
+ *
+ * The AK98FS Host controller handles host side USB. For Documentation,
+ * refer to chapter 22 USB Controllers of AK98xx Mobile Multimedia Application
+ * Processor Programmer's Guide.
+ *
+ */
+
+/*
+ * Status:  Enumeration of USB Optical Mouse, USB Keyboard, USB Flash Disk, Ralink 2070/3070 USB WiFi OK.
+ *          Pass basic test with USB Optical Mouse/USB Keyboard/USB Flash Disk.
+ *          Ralink 2070/3070 USB WiFI Scanning/WEP basic test OK. Full Functions TBD.
+ *
+ * TODO:
+ * - Use up to 6 active queues of FS HC(for now only 2 queues: EP0 & EPX(1-6))
+ * - USB Suspend/Resume support
+ * - Use urb->iso_frame_desc[] with ISO transfers
+ * - Optimize USB FIFO data transfer/receive(4B->2B->1B)
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/usb.h>
+#include <linux/usb/ak98fsh.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+
+#include "../core/hcd.h"
+#include "ak98-fs-hcd.h"
+
+#include <mach/ak880x_addr.h>
+#include <mach/regs-comm.h>
+#include <mach/clock.h>
+#include <mach/gpio.h>
+
+#ifdef AK98FS_DEBUG
+const char *trans_desc[4] = { "ISO", "INT", "CNTL", "BULK"};
+const char *xfer_name[4] = { "CNTL", "ISO", "BULK", "INT" };
+#endif
+
+MODULE_DESCRIPTION("AK98HS USB Full Speed Host Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ak98-fs-hcd");
+
+#define DRIVER_VERSION	"16 Dec 2010"
+
+static const char hcd_name[] = "ak98-fs-hcd";
+
+static u8 ep_fifos[] = { FIFO_EP0, FIFO_EP1, FIFO_EP2, FIFO_EP3, FIFO_EP4, FIFO_EP5, FIFO_EP6 };
+struct ak98fsh_epfifo_mapping ak98fsh_epfifo_mapping;
+static int period_epfifo;
+
+static void usbhost_reset(void);
+
+
+static void port_power(struct ak98fsh *ak98fsh, int is_on)
+{
+	/*ak98 usb host is self power currently.*/
+	struct usb_hcd	*hcd = ak98fsh_to_hcd(ak98fsh);
+
+	/* hub is inactive unless the port is powered */
+	if (is_on) {
+		if (ak98fsh->port_status & (1 << USB_PORT_FEAT_POWER))
+			return;
+
+		ak98fsh->port_status = (1 << USB_PORT_FEAT_POWER);
+	} else {
+		ak98fsh->port_status = 0;
+		hcd->state = HC_STATE_HALT;
+	}
+
+	if (ak98fsh->board && ak98fsh->board->port_power) {
+		/* switch VBUS, at 500mA unless hub power budget gets set */
+		HDBG("power %s\n", is_on ? "on" : "off");
+		ak98fsh->board->port_power(hcd->self.controller, is_on);
+	}
+
+	/* reset as thoroughly as we can */
+	if (ak98fsh->board && ak98fsh->board->reset)
+		ak98fsh->board->reset(hcd->self.controller);
+	else {
+		/*softreset the usb host controller.*/
+		usbhost_reset();
+	}
+
+	// if !is_on, put into lowpower mode now
+
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* This is a PIO-only HCD.  Queueing appends URBs to the endpoint's queue,
+ * and may start I/O.  Endpoint queues are scanned during completion irq
+ * handlers (one per packet: ACK, NAK, faults, etc) and urb cancellation.
+ *
+ * Using an external DMA engine to copy a packet at a time could work,
+ * though setup/teardown costs may be too big to make it worthwhile.
+ */
+
+/* SETUP starts a new control request.  Devices are not allowed to
+ * STALL or NAK these; they must cancel any pending control requests.
+ */
+static void setup_packet(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb
+)
+{
+	int	i;
+	unsigned int fifo_val;
+	u8	len;
+	unsigned char *buf = urb->setup_packet;
+
+	HDBG("Packet: Setup Packet (EP %d)\n", ep->epnum);
+
+	len = sizeof(struct usb_ctrlrequest);
+
+	fsh_index_writeb(0, 0, CTLSTS_EP_TXL);
+	fsh_writeb(usb_pipedevice(urb->pipe), UR_FUNADDR);
+	for (i = 0; i < len; i += 4) {
+		fifo_val = (*(buf+i) | ( *(buf+i+1)<<8 )
+				   | ( *(buf+i+2)<<16 ) | ( *(buf+i+3)<<24 ));
+		fsh_writel(fifo_val, FIFO_EP0);
+	}
+	fsh_index_writeb(0, 0x08 | 0x02, CTLSTS_EP_TXL);
+
+	ep->length = 0;
+}
+
+/* STATUS finishes control requests, often after IN or OUT data packets */
+static void status_packet(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb
+)
+{
+	int			do_out;
+	int			epfifo;
+
+	HDBG("Packet: Status Packet (EP %d)\n", ep->epnum);
+
+	do_out = urb->transfer_buffer_length && usb_pipein(urb->pipe);
+	if (!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, !usb_pipein(urb->pipe), &epfifo))
+		BUG();	/* Impossible, USB Device Endpoint *MUST* have been mapped to EPFIFO */
+	
+	fsh_writeb(usb_pipedevice(urb->pipe), UR_FUNADDR);
+
+	if (do_out) {
+		fsh_index_writeb(epfifo, 0x42, CTLSTS_EP_TXL);
+	} else {
+		fsh_index_writeb(epfifo, 0x60, CTLSTS_EP_TXL);
+	}
+		
+	ep->length = 0;
+}
+
+/* IN packets can be used with any type of endpoint. here we just
+ * start the transfer, data from the peripheral may arrive later.
+ * urb->iso_frame_desc is currently ignored here...
+ */
+static void in_packet(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb
+)
+{
+	int			epfifo;
+	u8			len;
+	unsigned int		pipe = urb->pipe;
+
+	HDBG("Packet: IN Packet (EP %d), Length=%d,ep->maxpacket=%d\n",
+		ep->epnum, urb->transfer_buffer_length - urb->actual_length, ep->maxpacket);
+
+	/* avoid losing data on overflow */
+	len = ep->maxpacket;
+
+	fsh_writeb(usb_pipedevice(urb->pipe), UR_FUNADDR);
+	if (ep->epnum == 0) {
+		fsh_index_writeb(0, 1 << 5, CTLSTS_EP_TXL);
+	} else {
+		int eptype = 0;
+		if (!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, 0, &epfifo))
+			BUG();	/* Impossible, USB Device Endpoint *MUST* have been mapped to EPFIFO */
+		if (usb_pipeisoc(pipe)) {
+			eptype = 1;
+		} else if (usb_pipeint(pipe)) {
+			eptype = 3;
+		} else if (usb_pipebulk(pipe)) {
+			eptype = 2;
+		} else BUG();
+#ifndef DYNAMIC_EPFIFO
+		set_epx_rx_type(epfifo, ep->epnum, eptype);
+		set_epx_rx_mode(epfifo);
+#endif
+		fsh_index_writeb(epfifo, 1 << 5, CTLSTS_EP_RXL);
+	}
+
+	ep->length = min_t(u32, len,
+			urb->transfer_buffer_length - urb->actual_length);
+}
+
+/* OUT packets can be used with any type of endpoint.
+ * urb->iso_frame_desc is currently ignored here...
+ */
+static void out_packet(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb
+)
+{
+	int i;
+	int			epfifo;
+	unsigned char		*buf;
+	u8			len;
+	unsigned int		pipe = urb->pipe;
+
+	HDBG("Packet: OUT Packet (EP %d), Length=%d\n", ep->epnum, urb->transfer_buffer_length - urb->actual_length);
+
+	buf = (unsigned char *)(urb->transfer_buffer + urb->actual_length);
+	prefetch(buf);
+
+	len = min_t(u32, ep->maxpacket,
+			urb->transfer_buffer_length - urb->actual_length);
+
+	if (!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, 1, &epfifo))
+		BUG();	/* Impossible, USB Device Endpoint *MUST* have been mapped to EPFIFO */
+	fsh_index_writeb(epfifo, 0, CTLSTS_EP_TXL);
+	fsh_writeb(usb_pipedevice(pipe), UR_FUNADDR);
+	for (i = 0; i < len; i ++) {
+		fsh_writeb(buf[i], ep_fifos[epfifo]);
+	}
+	if (ep->epnum == 0) {
+		fsh_index_writeb(0, 0x02, CTLSTS_EP_TXL);
+	} else {
+#ifndef DYNAMIC_EPFIFO
+		int eptype = 0;
+
+		if (usb_pipeisoc(pipe)) {
+			eptype = 1;
+		} else if (usb_pipeint(pipe)) {
+			eptype = 3;
+		} else if (usb_pipebulk(pipe)) {
+			eptype = 2;
+		} else BUG();
+		set_epx_tx_type(epfifo, ep->epnum, eptype);
+		set_epx_tx_mode(epfifo);
+#endif
+		fsh_index_writeb(epfifo, 1 << 0, CTLSTS_EP_TXL);
+	}
+
+	ep->length = len;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* caller updates on-chip enables later */
+static inline void sofirq_on(struct ak98fsh *ak98fsh)
+{
+    unsigned int regval;
+
+    regval = fsh_readb(UR_INTECOM);
+    regval |= 1<<3;
+    fsh_writeb(regval, UR_INTECOM);
+}
+
+static inline void sofirq_off(struct ak98fsh *ak98fsh)
+{
+    unsigned int regval;
+
+    regval = fsh_readb(UR_INTECOM);
+    regval &= ~(1<<3);
+    fsh_writeb(regval, UR_INTECOM);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static struct ak98fsh_ep *start_ep0(struct ak98fsh *ak98fsh)
+{
+	struct ak98fsh_ep	*ep;
+	struct urb		*urb;
+	
+	/* use endpoint at schedule head */
+	if (ak98fsh->next_async_ep0)
+		ep = ak98fsh->next_async_ep0;
+	else if (!list_empty(&ak98fsh->async_ep0)) {
+		ep = container_of(ak98fsh->async_ep0.next,
+				struct ak98fsh_ep, schedule);
+	} else {
+		/* could set up the first fullspeed periodic
+		 * transfer for the next frame ...
+		 */
+		return NULL;
+	}
+
+	if (ep->schedule.next == &ak98fsh->async_ep0)
+		ak98fsh->next_async_ep0 = NULL;
+	else
+		ak98fsh->next_async_ep0 = container_of(ep->schedule.next,
+			struct ak98fsh_ep, schedule);
+
+	if (unlikely(list_empty(&ep->hep->urb_list))) {
+		HDBG("empty %p queue?\n", ep);
+		return NULL;
+	}
+
+	urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
+
+	switch (ep->nextpid) {
+	case USB_PID_IN:
+		in_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_OUT:
+		out_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_SETUP:
+		setup_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_ACK:		/* for control status */
+		status_packet(ak98fsh, ep, urb);
+		break;
+	default:
+		HDBG("bad ep%p pid %02x\n", ep, ep->nextpid);
+		ep = NULL;
+	}
+	return ep;
+}
+
+
+/* pick the next endpoint for a transaction, and issue it.
+ * frames start with periodic transfers (after whatever is pending
+ * from the previous frame), and the rest of the time is async
+ * transfers, scheduled round-robin.
+ */
+static struct ak98fsh_ep *start_epx(struct ak98fsh *ak98fsh, int epfifo)
+{
+	struct ak98fsh_ep	*ep;
+	struct urb		*urb;
+
+	
+	/* use endpoint at schedule head */
+	if (ak98fsh->next_periodic) {
+		ep = ak98fsh->next_periodic;
+		ak98fsh->next_periodic = ep->next;
+	} else {
+		if (ak98fsh->next_async_epx[epfifo-1])
+			ep = ak98fsh->next_async_epx[epfifo-1];
+		else if (!list_empty(&ak98fsh->async_epx[epfifo-1])) {
+			ep = container_of(ak98fsh->async_epx[epfifo-1].next,
+					struct ak98fsh_ep, schedule);
+
+		} else {
+			/* could set up the first fullspeed periodic
+			 * transfer for the next frame ...
+			 */
+			return NULL;
+		}
+
+		if (ep->schedule.next == &ak98fsh->async_epx[epfifo-1])
+			ak98fsh->next_async_epx[epfifo-1] = NULL;
+		else {
+			ak98fsh->next_async_epx[epfifo-1] = container_of(ep->schedule.next,
+					struct ak98fsh_ep, schedule);
+		}
+	}
+
+	if (unlikely(list_empty(&ep->hep->urb_list))) {
+		HDBG("empty %p queue?\n", ep);
+		return NULL;
+	}
+	urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
+	switch (ep->nextpid) {
+	case USB_PID_IN:
+		in_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_OUT:
+		out_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_SETUP:
+		setup_packet(ak98fsh, ep, urb);
+		break;
+	case USB_PID_ACK:		
+		status_packet(ak98fsh, ep, urb);
+		break;
+	default:
+		HDBG("bad ep%p pid %02x\n", ep, ep->nextpid);
+		ep = NULL;
+	}
+	return ep;
+}
+
+#define MIN_JIFFIES	((msecs_to_jiffies(2) > 1) ? msecs_to_jiffies(2) : 2)
+
+static inline void start_transfer_ep0(struct ak98fsh *ak98fsh)
+{
+	if (ak98fsh->port_status & (1 << USB_PORT_FEAT_SUSPEND))
+		return;
+	if (ak98fsh->active_ep0 == NULL) {
+		ak98fsh->active_ep0 = start_ep0(ak98fsh);
+		if (ak98fsh->active_ep0 != NULL)
+			ak98fsh->jiffies_ep0 = jiffies + MIN_JIFFIES;
+	}
+}
+
+static inline void start_transfer_epx(struct ak98fsh *ak98fsh, int epfifo)
+{
+	if (ak98fsh->port_status & (1 << USB_PORT_FEAT_SUSPEND))
+		return;
+	if (ak98fsh->active_epx[epfifo-1] == NULL) {
+		ak98fsh->active_epx[epfifo-1] = start_epx(ak98fsh, epfifo);
+		if (ak98fsh->active_epx[epfifo-1] != NULL)
+			ak98fsh->jiffies_epx[epfifo-1] = jiffies + MIN_JIFFIES;
+	}
+}
+
+static inline void start_transfer(struct ak98fsh *ak98fsh, int epfifo)
+{
+	if(epfifo == 0)
+		start_transfer_ep0(ak98fsh);
+	else
+		start_transfer_epx(ak98fsh, epfifo);
+}
+
+static void finish_request_ep0(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb,
+	int			status
+) __releases(ak98fsh->lock) __acquires(ak98fsh->lock)
+{
+	VDBG("Finishing EP0 URB Request...\n");
+
+	if (usb_pipecontrol(urb->pipe))
+		ep->nextpid = USB_PID_SETUP;
+
+	usb_hcd_unlink_urb_from_ep(ak98fsh_to_hcd(ak98fsh), urb);
+	spin_unlock(&ak98fsh->lock);
+	usb_hcd_giveback_urb(ak98fsh_to_hcd(ak98fsh), urb, status);
+	spin_lock(&ak98fsh->lock);
+
+	/* leave active endpoints in the schedule */
+	if (!list_empty(&ep->hep->urb_list))
+		return;
+
+	/* async deschedule? */
+	if (!list_empty(&ep->schedule)) {
+		list_del_init(&ep->schedule);
+		if (ep == ak98fsh->next_async_ep0)
+			ak98fsh->next_async_ep0 = NULL;
+		return;
+	}
+}
+
+
+static void finish_request_epx(
+	struct ak98fsh		*ak98fsh,
+	struct ak98fsh_ep	*ep,
+	struct urb		*urb,
+	int			status
+) __releases(ak98fsh->lock) __acquires(ak98fsh->lock)
+{
+	unsigned		i;
+	int		epfifo;
+	int is_out;
+	unsigned int		pipe = urb->pipe;
+
+	is_out = !usb_pipein(pipe);
+
+	VDBG("Finishing EPx URB Request...\n");
+
+	if (usb_pipecontrol(urb->pipe))
+		ep->nextpid = USB_PID_SETUP;
+
+	usb_hcd_unlink_urb_from_ep(ak98fsh_to_hcd(ak98fsh), urb);
+	spin_unlock(&ak98fsh->lock);
+	usb_hcd_giveback_urb(ak98fsh_to_hcd(ak98fsh), urb, status);
+	spin_lock(&ak98fsh->lock);
+
+	/* leave active endpoints in the schedule */
+	if (!list_empty(&ep->hep->urb_list))
+		return;
+
+	/* async deschedule? */
+	if(epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, is_out, &epfifo) && !list_empty(&ep->schedule)) {
+		list_del_init(&ep->schedule);
+		if (ep == ak98fsh->next_async_epx[epfifo-1]) {
+			ak98fsh->next_async_epx[epfifo-1] = NULL;
+			}
+		return;
+	}
+
+	/* periodic deschedule */
+	VDBG("deschedule qh%d/%p branch %d\n", ep->period, ep, ep->branch);
+	for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
+		struct ak98fsh_ep	*temp;
+		struct ak98fsh_ep	**prev = &ak98fsh->periodic[i];
+
+		while (*prev && ((temp = *prev) != ep))
+			prev = &temp->next;
+		if (*prev)
+			*prev = ep->next;
+		ak98fsh->load[i] -= ep->load;
+	}
+	ep->branch = PERIODIC_SIZE;
+	ak98fsh->periodic_count--;
+	ak98fsh_to_hcd(ak98fsh)->self.bandwidth_allocated
+		-= ep->load / ep->period;
+	if (ep == ak98fsh->next_periodic)
+		ak98fsh->next_periodic = ep->next;
+
+	/* we might turn SOFs back on again for the async schedule */
+	if (ak98fsh->periodic_count == 0)
+		sofirq_off(ak98fsh);
+}
+
+static void
+done(struct ak98fsh *ak98fsh, struct ak98fsh_ep *ep)
+{
+	int 			i;
+	int			err_occurred = 0;
+	int			epfifo;
+	u8			status;
+	struct urb		*urb;
+	unsigned int		pipe;
+	int			is_out;
+	int			urbstat = -EINPROGRESS;
+
+	if (unlikely(!ep)) {
+		return;
+	}
+
+	urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
+	pipe = urb->pipe;
+	is_out = !usb_pipein(pipe);
+	if (!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, is_out, &epfifo))
+		BUG();	/* Impossible, USB Device Endpoint *MUST* have been mapped to EPFIFO */
+
+	status = fsh_index_readw(epfifo, CTLSTS_EP_TXL);
+
+	if (status & 0x80) {
+		if (!ep->period)
+			ep->nak_count++;
+		ep->error_count = 0;
+		err_occurred = 1;
+	}
+
+	if (((epfifo == 0) && (status & 0x04)) || ((epfifo != 0) && (status & 0x10))) {
+		ep->nak_count = ep->error_count = 0;
+		urbstat = -EPIPE;
+		err_occurred = 1;
+	}
+
+	if (((epfifo == 0) && (status & 0x10)) ||
+		((epfifo != 0) && (status & 0x04) && (usb_pipeint(pipe) || usb_pipebulk(pipe)))) {
+		urbstat = -EPROTO;
+		ep->error_count = 0;
+		err_occurred = 1;
+	}
+
+	if (err_occurred) {
+		if (epfifo == 0)
+			fsh_index_writew(0, 0, CTLSTS_EP_TXL);
+		else if (is_out)
+			fsh_index_writew(epfifo, 0, CTLSTS_EP_TXL);
+		else
+			fsh_index_writew(epfifo, 0, CTLSTS_EP_RXL);
+	} else {
+		struct usb_device	*udev = urb->dev;
+		int			len;
+		unsigned char		*buf;
+
+		/* urb->iso_frame_desc is currently ignored here... */
+
+		ep->nak_count = ep->error_count = 0;
+		switch (ep->nextpid) {
+		case USB_PID_OUT:
+			urb->actual_length += ep->length;
+			usb_dotoggle(udev, ep->epnum, 1);
+			if (urb->actual_length
+					== urb->transfer_buffer_length) {
+				if (usb_pipecontrol(urb->pipe)) {
+					VDBG("NEXT Packet: Status Packet.\n");
+					ep->nextpid = USB_PID_ACK;
+				}
+
+				/* some bulk protocols terminate OUT transfers
+				 * by a short packet, using ZLPs not padding.
+				 */
+				else if (ep->length < ep->maxpacket
+						|| !(urb->transfer_flags
+							& URB_ZERO_PACKET))
+					urbstat = 0;
+			}
+			break;
+		case USB_PID_IN:
+			buf = urb->transfer_buffer + urb->actual_length;
+			prefetchw(buf);
+			len = fsh_index_readw(epfifo, EP_COUNT);
+			if (len > ep->length) {
+				printk("   USB_PID_IN(OverFlow): len=%d, ep->length=%d\n",
+					len, ep->length);
+				len = ep->length;
+				urbstat = -EOVERFLOW;
+			}
+			urb->actual_length += len;
+			for (i = 0; i < len; i++)
+				*buf++ = fsh_readb(ep_fifos[epfifo]);
+			if (ep->epnum == 0) {
+				u8 regval = fsh_index_readb(epfifo, CTLSTS_EP_TXL);
+				regval &= ~(1 << 0);
+				fsh_index_writeb(epfifo, regval, CTLSTS_EP_TXL);
+			} else {
+				u8 regval = fsh_index_readb(epfifo, CTLSTS_EP_RXL);
+				regval &= ~(1 << 0);
+				fsh_index_writeb(epfifo, regval, CTLSTS_EP_RXL);
+			}
+				
+			usb_dotoggle(udev, ep->epnum, 0);
+			if (urbstat == -EINPROGRESS &&
+					(len < ep->maxpacket ||
+						urb->actual_length ==
+						urb->transfer_buffer_length)) {
+				if (usb_pipecontrol(urb->pipe)) {
+					VDBG("NEXT Packet: Status Packet.\n");
+					ep->nextpid = USB_PID_ACK;
+				}
+				else
+					urbstat = 0;
+			}
+			break;
+		case USB_PID_SETUP:
+			if (urb->transfer_buffer_length == urb->actual_length) {
+				VDBG("NEXT Packet: Status Packet.\n");
+				ep->nextpid = USB_PID_ACK;
+			}
+			else if (usb_pipeout(urb->pipe)) {
+				VDBG("NEXT Packet: OUT Packet.\n");
+				usb_settoggle(udev, 0, 1, 1);
+				ep->nextpid = USB_PID_OUT;
+			} else {
+				VDBG("NEXT Packet: IN Packet.\n");
+				usb_settoggle(udev, 0, 0, 1);
+				ep->nextpid = USB_PID_IN;
+			}
+			break;
+		case USB_PID_ACK:
+			if (!is_out) {
+				u8 regval = fsh_index_readb(epfifo, CTLSTS_EP_RXL);
+				regval &= ~(1 << 0);
+				fsh_index_writeb(epfifo, regval, CTLSTS_EP_RXL);
+			}
+			urbstat = 0;
+			break;
+		}
+
+	}
+
+	if (urbstat != -EINPROGRESS || urb->unlinked) {
+		if (ep->epnum == 0)
+			finish_request_ep0(ak98fsh, ep, urb, urbstat);
+		else
+			finish_request_epx(ak98fsh, ep, urb, urbstat);
+	}
+}
+
+static irqreturn_t ak98fsh_irq(struct usb_hcd *hcd)
+{
+	struct ak98fsh	*ak98fsh = hcd_to_ak98fsh(hcd);
+	irqreturn_t	ret = IRQ_NONE;
+	struct urb *urb;
+	unsigned int pipe;
+	int is_out;
+	struct ak98fsh_ep *ep;
+	int epnum[MAX_EP_NUM + 1] = { 0 };
+	int epfifo = 0;
+	int i;
+	unsigned index = 0;
+	
+	char rINTCOM;
+	unsigned short rINTTX, rINTRX;
+	
+	spin_lock(&ak98fsh->lock);
+	
+	/*Read & Clear all interrupt status.*/
+	rINTCOM = fsh_readb(UR_INTCOM);
+	rINTTX = fsh_readw(UR_INTTX);
+	rINTRX = fsh_readw(UR_INTRX);
+	
+	if (rINTTX & 0x1) {
+		epnum[0] = 1;
+		done(ak98fsh, ak98fsh->active_ep0);
+		ak98fsh->active_ep0 = NULL;
+		ak98fsh->stat_ep0++;
+	}
+	
+	for(i=0; i<MAX_EP_NUM; i++)
+		if((rINTTX & (1<<(i+1))) || (rINTRX & (1<<(i+1)))) {
+			epnum[i + 1] = 1;
+			done(ak98fsh, ak98fsh->active_epx[i]);
+			ak98fsh->active_epx[i] = NULL;
+			ak98fsh->stat_epx[i]++;
+	}
+
+	if (rINTCOM & INTR_SOF) { 
+		index = ak98fsh->frame++ & (PERIODIC_SIZE - 1);
+		ak98fsh->stat_sof++;
+
+		/* be graceful about almost-inevitable periodic schedule
+		 * overruns:  continue the previous frame's transfers iff
+		 * this one has nothing scheduled.
+		 */
+		if (ak98fsh->next_periodic) {
+			ak98fsh->stat_overrun++;
+		}
+		if (ak98fsh->periodic[index]) {
+			ak98fsh->next_periodic = ak98fsh->periodic[index];
+			}
+	}
+
+	/* manages debouncing and wakeup */
+	if(rINTCOM & (INTR_CONNECTED | INTR_DISCONNECTED)) {
+		if (rINTCOM & INTR_CONNECTED) {
+			//printk("USB: Device Connected!!\n");
+			ak98fsh->stat_insrmv = 1;
+		} else {
+			//printk("USB: Device Disconnected!!\n");
+			period_epfifo = 0;
+			ak98fsh->stat_insrmv = 0;
+		}
+
+		/* most stats are reset for each VBUS session */
+		ak98fsh->stat_wake = 0;
+		ak98fsh->stat_sof = 0;
+		ak98fsh->stat_ep0 = 0;
+		for(i=0; i<MAX_EP_NUM; i++)
+			ak98fsh->stat_epx[i] = 0;
+		ak98fsh->stat_lost = 0;
+
+		/* usbcore nukes other pending transactions on disconnect */
+		if (ak98fsh->active_ep0) {
+			VDBG("Finishing EP0 Active URBs...\n");
+			ep = ak98fsh->active_ep0;
+			urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
+			pipe = urb->pipe;
+			is_out = !usb_pipein(pipe);
+			epfifo = 0;
+			fsh_index_writeb(epfifo, 0, CTLSTS_EP_TXL);
+			fsh_index_writeb(epfifo, 1 << 0, CTLSTS_EP_TXH);
+
+			finish_request_ep0(ak98fsh, ak98fsh->active_ep0,
+				container_of(ak98fsh->active_ep0
+						->hep->urb_list.next,
+					struct urb, urb_list),
+				-ESHUTDOWN);
+			ak98fsh->active_ep0 = NULL;
+		}
+
+		for(i=0; i<MAX_EP_NUM; i++) 
+			if (ak98fsh->active_epx[i]) {
+				VDBG("Finishing EPx Active URBs...\n");
+				ep = ak98fsh->active_epx[i];
+				urb = container_of(ep->hep->urb_list.next, struct urb, urb_list);
+				pipe = urb->pipe;
+				is_out = !usb_pipein(pipe);
+				//epnum = ep->epnum;
+				if (!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, is_out, &epfifo))
+					BUG();
+				if (is_out) {
+					fsh_index_writeb(epfifo, 1 << 3, CTLSTS_EP_TXL);
+				} else {
+					fsh_index_writeb(epfifo, 1 << 4, CTLSTS_EP_RXL);
+				}
+
+				finish_request_epx(ak98fsh, ak98fsh->active_epx[i],
+					container_of(ak98fsh->active_epx[i]
+							->hep->urb_list.next,
+						struct urb, urb_list),
+					-ESHUTDOWN);
+				ak98fsh->active_epx[i] = NULL;
+			}
+
+		/* port status seems weird until after reset, so
+		 * force the reset and make khubd clean up later.
+		 */
+		if (rINTCOM & INTR_CONNECTED) {
+			ak98fsh->port_status |= 1 << USB_PORT_FEAT_CONNECTION;
+			ak98fsh->port_status |= 1 << USB_PORT_FEAT_C_CONNECTION;
+		} else {
+			ak98fsh->port_status &= ~(1 << USB_PORT_FEAT_CONNECTION);
+			ak98fsh->port_status |= 1 << USB_PORT_FEAT_C_CONNECTION;
+			init_epfifo_mapping(&ak98fsh_epfifo_mapping);
+			reset_endpoints();
+		}
+	}
+
+	if (rINTCOM & INTR_RESUME) {
+		if (ak98fsh->port_status & (1 << USB_PORT_FEAT_SUSPEND)) {
+			HDBG("wakeup\n");
+			ak98fsh->port_status |= 1 << USB_PORT_FEAT_C_SUSPEND;
+			ak98fsh->stat_wake++;
+		}
+		rINTCOM &= ~(INTR_RESUME);
+	}
+
+	if (ak98fsh->port_status & (1 << USB_PORT_FEAT_ENABLE)) {
+		if (epnum[0]) {
+			start_transfer(ak98fsh, 0);
+			ret = IRQ_HANDLED;
+		}
+		if((rINTCOM & INTR_SOF) && ak98fsh->periodic[index] && period_epfifo){
+			start_transfer(ak98fsh, period_epfifo);
+			ret = IRQ_HANDLED;
+		}
+		for(i = 0; i < MAX_EP_NUM; i++) {
+			if(epnum[i + 1]) {
+				start_transfer(ak98fsh, i + 1);
+				ret = IRQ_HANDLED;
+			}
+		}
+	}
+
+	if(ak98fsh->periodic_count == 0 && list_empty(&ak98fsh->async_ep0)) {
+			for(i = 0; i < MAX_EP_NUM; i++) {
+					if(!list_empty(&ak98fsh->async_epx[i]))
+							break;
+			}
+			if(i == MAX_EP_NUM)
+					sofirq_off(ak98fsh);
+	}
+
+	spin_unlock(&ak98fsh->lock);
+	
+	return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* usb 1.1 says max 90% of a frame is available for periodic transfers.
+ * this driver doesn't promise that much since it's got to handle an
+ * IRQ per packet; irq handling latencies also use up that time.
+ *
+ * NOTE:  the periodic schedule is a sparse tree, with the load for
+ * each branch minimized.  see fig 3.5 in the OHCI spec for example.
+ */
+#define	MAX_PERIODIC_LOAD	500	/* out of 1000 usec */
+
+static int balance(struct ak98fsh *ak98fsh, u16 period, u16 load)
+{
+	int	i, branch = -ENOSPC;
+
+	/* search for the least loaded schedule branch of that period
+	 * which has enough bandwidth left unreserved.
+	 */
+	for (i = 0; i < period ; i++) {
+		if (branch < 0 || ak98fsh->load[branch] > ak98fsh->load[i]) {
+			int	j;
+
+			for (j = i; j < PERIODIC_SIZE; j += period) {
+				if ((ak98fsh->load[j] + load)
+						> MAX_PERIODIC_LOAD)
+					break;
+			}
+			if (j < PERIODIC_SIZE)
+				continue;
+			branch = i;
+		}
+	}
+	return branch;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int ak98fsh_urb_enqueue(
+	struct usb_hcd		*hcd,
+	struct urb		*urb,
+	gfp_t			mem_flags
+) {
+	struct ak98fsh		*ak98fsh = hcd_to_ak98fsh(hcd);
+	struct usb_device	*udev = urb->dev;
+	unsigned int		pipe = urb->pipe;
+	int			is_out = !usb_pipein(pipe);
+	int			type = usb_pipetype(pipe);
+	int			epnum = usb_pipeendpoint(pipe);
+#ifdef DYNAMIC_EPFIFO
+	int			epfifo = 0;
+#endif
+	struct ak98fsh_ep	*ep = NULL;
+	unsigned long		flags;
+	int			i;
+	int			retval;
+	struct usb_host_endpoint	*hep = urb->ep;
+
+	VDBG("Enqueue: Direction=%s, Type=%s, EP Num=%d, urb=%p\n",
+		is_out ? "OUT" : "IN", trans_desc[type], epnum, urb);
+
+	if (type == PIPE_ISOCHRONOUS)
+		return -ENOSPC;
+
+#ifdef DYNAMIC_EPFIFO
+	spin_lock_irqsave(&ak98fsh_epfifo_mapping.lock,flags);
+	if (!__is_epnum_mapped(&ak98fsh_epfifo_mapping, epnum, is_out)) {
+		if (!__map_epnum_to_epfifo(&ak98fsh_epfifo_mapping, epnum, is_out, &epfifo)) {
+			spin_unlock_irqrestore(&ak98fsh_epfifo_mapping.lock, flags);
+			return -ENOSPC;
+		}
+		if (epnum != 0) {
+			int eptype = 0;
+
+			if (usb_pipeisoc(pipe)) {
+				eptype = 1;
+			} else if (usb_pipeint(pipe)) {
+				eptype = 3;
+			} else if (usb_pipebulk(pipe)) {
+				eptype = 2;
+			} else BUG();
+
+			if (is_out) {
+				disable_epx_tx_interrupt(epfifo);
+				set_epx_tx_type(epfifo, epnum, eptype);
+				fsh_index_writew(epfifo, hep->desc.wMaxPacketSize, MaxPackSz_TX);
+				fsh_index_writeb(epfifo, 0, NAK_TO_EP0);	/* Tx Interval */
+				clear_epx_tx_data_toggle(epfifo);
+				set_epx_tx_mode(epfifo);
+				flush_epx_tx_fifo(epfifo);
+				enable_epx_tx_interrupt(epfifo);
+			} else {
+				disable_epx_rx_interrupt(epfifo);
+				set_epx_rx_type(epfifo, epnum, eptype);
+				fsh_index_writew(epfifo, hep->desc.wMaxPacketSize, MaxPackSz_RX);
+				fsh_index_writeb(epfifo, 0, NAK_TO_EP0);	/* Tx Interval */
+				if (usb_endpoint_xfer_isoc(&hep->desc) || usb_endpoint_xfer_int(&hep->desc))
+					fsh_index_writeb(epfifo, hep->desc.bInterval, RX_INTVAL);
+				else
+					fsh_index_writeb(epfifo, 0, RX_INTVAL);
+				set_epx_rx_mode(epfifo);
+				clear_epx_rx_data_toggle(epfifo);
+				flush_epx_rx_fifo(epfifo);
+				enable_epx_rx_interrupt(epfifo);
+			}
+		}
+	} else {
+		if(!epnum_to_epfifo(&ak98fsh_epfifo_mapping, epnum, is_out, &epfifo))
+			BUG();
+	}
+
+	spin_unlock_irqrestore(&ak98fsh_epfifo_mapping.lock, flags);
+#endif
+
+	/* avoid all allocations within spinlocks */
+	if (!hep->hcpriv)
+		ep = kzalloc(sizeof *ep, mem_flags);
+
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+
+	/* don't submit to a dead or disabled port */
+	if (!(ak98fsh->port_status & (1 << USB_PORT_FEAT_ENABLE))
+			|| !HC_IS_RUNNING(hcd->state)) {
+		retval = -ENODEV;
+		kfree(ep);
+		goto fail_not_linked;
+	}
+
+	retval = usb_hcd_link_urb_to_ep(hcd, urb);
+	if (retval) {
+		kfree(ep);
+		goto fail_not_linked;
+	}
+
+	if (hep->hcpriv) {
+		kfree(ep);
+		ep = hep->hcpriv;
+	} else if (!ep) {
+		retval = -ENOMEM;
+		goto fail;
+	} else {
+		INIT_LIST_HEAD(&ep->schedule);
+		ep->udev = udev;
+		ep->epnum = epnum;
+		ep->maxpacket = usb_maxpacket(udev, urb->pipe, is_out);
+		usb_settoggle(udev, epnum, is_out, 0);
+
+		if (type == PIPE_CONTROL)
+			ep->nextpid = USB_PID_SETUP;
+		else if (is_out)
+			ep->nextpid = USB_PID_OUT;
+		else
+			ep->nextpid = USB_PID_IN;
+
+		if (ep->maxpacket > H_MAXPACKET) {
+			/* iso packets up to 240 bytes could work... */
+			HDBG("dev %d ep%d maxpacket %d\n",
+				udev->devnum, epnum, ep->maxpacket);
+			retval = -EINVAL;
+			goto fail;
+		}
+
+		switch (type) {
+		case PIPE_ISOCHRONOUS:
+		case PIPE_INTERRUPT:
+			if (urb->interval > PERIODIC_SIZE)
+				urb->interval = PERIODIC_SIZE;
+			ep->period = urb->interval;
+			ep->branch = PERIODIC_SIZE;
+			ep->load = usb_calc_bus_time(udev->speed, !is_out,
+				(type == PIPE_ISOCHRONOUS),
+				usb_maxpacket(udev, pipe, is_out))
+					/ 1000;
+			period_epfifo = epfifo;
+			break;
+		}
+
+		ep->hep = hep;
+		hep->hcpriv = ep;
+	}
+
+	/* maybe put endpoint into schedule */
+	switch (type) {
+	case PIPE_CONTROL:
+	case PIPE_BULK:
+		if (list_empty(&ep->schedule)) {
+			if (epnum == 0) 
+				list_add_tail(&ep->schedule, &ak98fsh->async_ep0);
+			else 
+				list_add_tail(&ep->schedule, &ak98fsh->async_epx[epfifo-1]);
+		}
+		break;
+	case PIPE_ISOCHRONOUS:
+	case PIPE_INTERRUPT:
+		urb->interval = ep->period;
+		if (ep->branch < PERIODIC_SIZE) {
+			/* NOTE:  the phase is correct here, but the value
+			 * needs offsetting by the transfer queue depth.
+			 * All current drivers ignore start_frame, so this
+			 * is unlikely to ever matter...
+			 */
+			urb->start_frame = (ak98fsh->frame & (PERIODIC_SIZE - 1))
+						+ ep->branch;
+			break;
+		}
+
+		retval = balance(ak98fsh, ep->period, ep->load);
+		if (retval < 0)
+			goto fail;
+		ep->branch = retval;
+		retval = 0;
+		urb->start_frame = (ak98fsh->frame & (PERIODIC_SIZE - 1))
+					+ ep->branch;
+
+		/* sort each schedule branch by period (slow before fast)
+		 * to share the faster parts of the tree without needing
+		 * dummy/placeholder nodes
+		 */
+		VDBG("schedule qh%d/%p branch %d\n", ep->period, ep, ep->branch);
+		for (i = ep->branch; i < PERIODIC_SIZE; i += ep->period) {
+			struct ak98fsh_ep	**prev = &ak98fsh->periodic[i];
+			struct ak98fsh_ep	*here = *prev;
+
+			while (here && ep != here) {
+				if (ep->period > here->period)
+					break;
+				prev = &here->next;
+				here = *prev;
+			}
+			if (ep != here) {
+				ep->next = here;
+				*prev = ep;
+			}
+			ak98fsh->load[i] += ep->load;
+		}
+		ak98fsh->periodic_count++;
+		hcd->self.bandwidth_allocated += ep->load / ep->period;
+		sofirq_on(ak98fsh);
+	}
+
+
+	urb->hcpriv = hep;
+	start_transfer(ak98fsh, epfifo);
+
+fail:
+	if (retval)
+		usb_hcd_unlink_urb_from_ep(hcd, urb);
+fail_not_linked:
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+	return retval;
+}
+
+static int ak98fsh_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+{
+	struct ak98fsh		*ak98fsh = hcd_to_ak98fsh(hcd);
+	struct usb_host_endpoint *hep;
+	unsigned long		flags;
+	struct ak98fsh_ep	*ep;
+	int			retval, i;
+	unsigned int		pipe = urb->pipe;
+	int			is_out = !usb_pipein(pipe);
+	int			epfifo = 0;
+	
+	VDBG("Dequeue: Direction=%s, Type=%s, EP Num=%d, urb=%p\n",
+		is_out ? "OUT" : "IN", trans_desc[usb_pipetype(pipe)], usb_pipeendpoint(pipe), urb);
+
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+
+	retval = usb_hcd_check_unlink_urb(hcd, urb, status);
+
+	if (retval) {
+		printk("Dequeue: check and unlink urb failed!\n");
+		goto fail;
+	}
+
+	hep = urb->hcpriv;
+	ep = hep->hcpriv;
+	if (ep) {
+		/* finish right away if this urb can't be active ...
+		 * note that some drivers wrongly expect delays
+		 */
+		if (ep->hep->urb_list.next != &urb->urb_list) {
+			/* not front of queue?  never active */
+
+		/* for active transfers, we expect an IRQ */
+		} else if (ak98fsh->active_ep0 == ep) {
+			if (time_before_eq(ak98fsh->jiffies_ep0, jiffies)) {
+				epfifo = 0;
+				fsh_index_writeb(epfifo, 0, CTLSTS_EP_TXL);
+				fsh_index_writeb(epfifo, 1 << 0, CTLSTS_EP_TXH);
+				ak98fsh->active_ep0 = NULL;
+			} else
+				urb = NULL;
+		} else {
+			for(i=0; i<MAX_EP_NUM; i++) {
+				if(ak98fsh->active_epx[i] == ep) {
+					if(time_before_eq(ak98fsh->jiffies_epx[i], jiffies)) {
+						if(!epnum_to_epfifo(&ak98fsh_epfifo_mapping, ep->epnum, is_out, &epfifo))
+							BUG();
+						if (is_out) {
+							fsh_index_writeb(epfifo, 1 << 3, CTLSTS_EP_TXL);
+						} else {
+							fsh_index_writeb(epfifo, 1 << 4, CTLSTS_EP_RXL);
+						}
+						ak98fsh->active_epx[i] = NULL;
+					} else
+						urb = NULL;
+				}
+			}
+			/* front of queue for inactive endpoint */
+		}
+
+		if (urb) {
+			if (ak98fsh->active_ep0 == ep)
+				finish_request_ep0(ak98fsh, ep, urb, 0);
+			else
+				finish_request_epx(ak98fsh, ep, urb, 0);
+		} else {
+			HDBG("dequeue, urb %p active ; wait4irq\n", urb);
+		}
+	} else
+		retval = -EINVAL;
+ fail:
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+	return retval;
+}
+
+static void
+ak98fsh_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+{
+	struct ak98fsh		*ak98fsh = hcd_to_ak98fsh(hcd);
+	int			epnum = usb_endpoint_num(&hep->desc);
+	unsigned long		flags;
+
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+
+	HDBG("Resetting EP %d, Type=%s, Dir=%s\n",
+		epnum, xfer_name[usb_endpoint_type(&hep->desc)], usb_endpoint_dir_out(&hep->desc)? "OUT" : "IN");
+
+	if (epnum == 0) {
+		fsh_index_writeb(0, 0, NAK_TO_EP0);
+		fsh_index_writew(0, 0, CTLSTS_EP_TXL);
+		flush_ep0_fifo();
+		enable_ep0_interrupt();
+	} else {
+#ifndef DYNAMIC_EPFIFO
+		int eptype = usb_endpoint_type(&hep->desc);
+		int is_out = usb_endpoint_dir_out(&hep->desc);
+		if (is_out) {
+			disable_epx_tx_interrupt(epnum);
+			set_epx_tx_type(epnum, epnum, eptype);
+			fsh_index_writew(epnum, hep->desc.wMaxPacketSize, MaxPackSz_TX);
+			fsh_index_writeb(epnum, 0, NAK_TO_EP0);	/* Tx Interval */
+			clear_epx_tx_data_toggle(epnum);
+			set_epx_tx_mode(epnum);
+			flush_epx_tx_fifo(epnum);
+			enable_epx_tx_interrupt(epnum);
+		} else {
+			disable_epx_rx_interrupt(epnum);
+			set_epx_rx_type(epnum, epnum, eptype);
+			fsh_index_writew(epnum, hep->desc.wMaxPacketSize, MaxPackSz_RX);
+			fsh_index_writeb(epnum, 0, NAK_TO_EP0);	/* Tx Interval */
+			if (usb_endpoint_xfer_isoc(&hep->desc) || usb_endpoint_xfer_int(&hep->desc))
+				fsh_index_writeb(epnum, hep->desc.bInterval, RX_INTVAL);
+			else
+				fsh_index_writeb(epnum, 0, RX_INTVAL);
+			set_epx_rx_mode(epnum);
+			clear_epx_rx_data_toggle(epnum);
+			flush_epx_rx_fifo(epnum);
+			enable_epx_rx_interrupt(epnum);
+		}
+#endif
+	}
+
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+}
+
+static void
+ak98fsh_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
+{
+	struct ak98fsh_ep	*ep = hep->hcpriv;
+#ifdef DYNAMIC_EPFIFO
+	int			epnum = usb_endpoint_num(&hep->desc);
+	int			is_out = usb_endpoint_dir_out(&hep->desc);
+#endif
+	int			epfifo = 0;
+
+
+	if (!ep) {
+		return;
+	}
+#ifdef DYNAMIC_EPFIFO
+	if (is_epnum_mapped(&ak98fsh_epfifo_mapping, epnum, is_out)) {
+#else
+	if (1) {
+#endif
+		disable_ep_interrupt(epfifo);
+		flush_ep_fifo(epfifo);
+	}
+	/* assume we'd just wait for the irq */
+	if (!list_empty(&hep->urb_list))
+		msleep(3);
+	if (!list_empty(&hep->urb_list))
+		HDBG("ep %p not empty?\n", ep);
+
+	kfree(ep);
+	hep->hcpriv = NULL;
+
+}
+
+static int
+ak98fsh_get_frame(struct usb_hcd *hcd)
+{
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+
+	/* wrong except while periodic transfers are scheduled;
+	 * never matches the on-the-wire frame;
+	 * subject to overruns.
+	 */
+	return ak98fsh->frame;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* the virtual root hub timer IRQ checks for hub status */
+static int
+ak98fsh_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+	unsigned long flags;
+
+	/* non-SMP HACK: use root hub timer as i/o watchdog
+	 * this seems essential when SOF IRQs aren't in use...
+	 */
+	local_irq_save(flags);
+	if (!timer_pending(&ak98fsh->timer)) {
+		if (ak98fsh_irq( /* ~0, */ hcd) != IRQ_NONE)
+			ak98fsh->stat_lost++;
+	}
+	local_irq_restore(flags);
+
+	if (!(ak98fsh->port_status & (0xffff << 16))) {
+		return 0;
+	}
+
+	/* tell khubd port 1 changed */
+	*buf = (1 << 1);
+
+	return 1;
+}
+
+static void
+ak98fsh_hub_descriptor (
+	struct ak98fsh *ak98fsh,
+	struct usb_hub_descriptor	*desc
+) {
+	u16		temp = 0;
+
+	desc->bDescriptorType = 0x29;
+	desc->bHubContrCurrent = 0;
+
+	desc->bNbrPorts = 1;
+	desc->bDescLength = 9;
+
+	/* per-port power switching (gang of one!), or none */
+	desc->bPwrOn2PwrGood = 0;
+
+	/* no overcurrent errors detection/handling */
+	temp |= 0x0010; 
+
+	desc->wHubCharacteristics = cpu_to_le16(temp);
+
+	/* two bitmaps:  ports removable, and legacy PortPwrCtrlMask */
+	desc->bitmap[0] = 0 << 1; 
+	desc->bitmap[1] = ~0;
+}
+
+static void
+ak98fsh_timer(unsigned long _ak98fsh)
+{
+	struct ak98fsh *ak98fsh = (void *) _ak98fsh;
+	unsigned long	flags;
+	const u32	mask = (1 << USB_PORT_FEAT_CONNECTION)
+				| (1 << USB_PORT_FEAT_ENABLE);
+
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+
+	if (ak98fsh->port_status & USB_PORT_STAT_RESET) {
+		ak98fsh->port_status = (1 << USB_PORT_FEAT_C_RESET)
+				| (1 << USB_PORT_FEAT_POWER);
+		ak98fsh->port_status |= mask;
+		
+		if (ak98fsh->port_status & (1 << USB_PORT_FEAT_CONNECTION)) {
+			if (fsh_readb(DEV_CTL_REG) & (1 << 5))
+				ak98fsh->port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
+			else if ((fsh_readb(DEV_CTL_REG) & (1 << 6))) {
+			} else {
+				/* Plug-in & plug-out quickly could lead to this... */
+				ak98fsh->port_status &= ~mask;
+			}
+		}
+	} else {
+		/* NOT IMPLEMENTED YET */
+		BUG();
+	}
+	
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+
+}
+
+static int
+ak98fsh_hub_control(
+	struct usb_hcd	*hcd,
+	u16		typeReq,
+	u16		wValue,
+	u16		wIndex,
+	char		*buf,
+	u16		wLength
+) {
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+	int		retval = 0;
+	unsigned long	flags;
+	char reg8val;
+
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+	
+	switch (typeReq) {
+	case ClearHubFeature:
+	case SetHubFeature:
+		switch (wValue) {
+		case C_HUB_OVER_CURRENT:
+		case C_HUB_LOCAL_POWER:
+			break;
+		default:
+			goto error;
+		}
+		break;
+	case ClearPortFeature:
+		if (wIndex != 1 || wLength != 0)
+			goto error;
+		switch (wValue) {
+		case USB_PORT_FEAT_ENABLE:
+			HDBG("ClearPortFeature: USB_PORT_FEAT_ENABLE\n");
+			ak98fsh->port_status &= (1 << USB_PORT_FEAT_POWER);
+			break;
+		case USB_PORT_FEAT_SUSPEND:
+			HDBG("ClearPortFeature: USB_PORT_FEAT_SUSPEND\n");
+			if (!(ak98fsh->port_status & (1 << USB_PORT_FEAT_SUSPEND)))
+				break;
+
+			/* 20 msec of resume/K signaling, other irqs blocked */
+			HDBG("    start resume...\n");
+			fsh_writeb(0x0, UR_INTECOM); 
+			reg8val = fsh_readb(UR_PWM); 
+			reg8val |= 1<<2;
+			fsh_writeb(reg8val, UR_PWM);
+			
+			mod_timer(&ak98fsh->timer, jiffies
+					+ msecs_to_jiffies(20));
+			break;
+		case USB_PORT_FEAT_POWER:
+			port_power(ak98fsh, 0);
+			break;
+		case USB_PORT_FEAT_C_ENABLE:
+		case USB_PORT_FEAT_C_SUSPEND:
+		case USB_PORT_FEAT_C_CONNECTION:
+			break;
+		case USB_PORT_FEAT_C_OVER_CURRENT:
+		case USB_PORT_FEAT_C_RESET:
+			break;
+		default:
+			goto error;
+		}
+		ak98fsh->port_status &= ~(1 << wValue);
+		break;
+	case GetHubDescriptor:
+		ak98fsh_hub_descriptor(ak98fsh, (struct usb_hub_descriptor *) buf);
+		break;
+	case GetHubStatus:
+		put_unaligned_le32(0, buf);
+		break;
+	case GetPortStatus:
+		if (wIndex != 1)
+			goto error;
+		put_unaligned_le32(ak98fsh->port_status, buf);
+		break;
+	case SetPortFeature:
+		if (wIndex != 1 || wLength != 0)
+			goto error;
+		switch (wValue) {
+		case USB_PORT_FEAT_SUSPEND:
+			HDBG("    USB_PORT_FEAT_SUSPEND\n");
+			if (ak98fsh->port_status & (1 << USB_PORT_FEAT_RESET))
+				goto error;
+			if (!(ak98fsh->port_status & (1 << USB_PORT_FEAT_ENABLE)))
+				goto error;
+			/*to suspend the usb host controller.*/
+			reg8val = fsh_readb(UR_PWM);
+			reg8val |= 1<<1;
+			fsh_writeb(reg8val, UR_PWM);
+			break;
+		case USB_PORT_FEAT_POWER: 
+			HDBG("    USB_PORT_FEAT_POWER\n");
+			port_power(ak98fsh, 1);
+			break;
+		case USB_PORT_FEAT_RESET:
+			HDBG("    USB_PORT_FEAT_RESET, Port Status=0x%08X\n", ak98fsh->port_status);
+			if (ak98fsh->port_status & (1 << USB_PORT_FEAT_SUSPEND)) {
+				HDBG("    USB_PORT_FEAT_SUSPEND ....\n");
+				goto error;
+			}
+			if (!(ak98fsh->port_status & (1 << USB_PORT_FEAT_POWER))) {
+				HDBG("    USB_PORT_FEAT_POWER NOT SET.\n");
+				break;
+			}
+			clear_all_interrupts();
+
+			/* 50 msec of reset/SE0 signaling, irqs blocked */
+			/*reset device.*/
+			reg8val = fsh_readb(UR_PWM);
+			reg8val |= 0x08;
+			fsh_writeb(reg8val, UR_PWM);
+			mdelay(30);
+			reg8val &= ~(0x08);
+			fsh_writeb(reg8val, UR_PWM);
+
+			fsh_writeb(0xF7, UR_INTECOM);
+
+			ak98fsh->port_status |= (1 << USB_PORT_FEAT_RESET);
+			mod_timer(&ak98fsh->timer, jiffies + msecs_to_jiffies(50));
+			break;
+		default:
+			goto error;
+		}
+
+		ak98fsh->port_status |= 1 << wValue;
+		break;
+error:
+		/* "protocol stall" on error */
+		retval = -EPIPE;
+	}
+
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+	return retval;
+}
+
+#ifdef	CONFIG_PM
+
+static int
+ak98fsh_bus_suspend(struct usb_hcd *hcd)
+{
+	u8 reg;
+	unsigned long flags;
+
+	msleep(10);
+	local_irq_save(flags);
+	reg = fsh_readb(UR_PWM);
+	reg |= (1 << 1);
+	fsh_writeb(reg, UR_PWM);
+	local_irq_restore(flags);
+	msleep(20);
+	return 0;
+}
+
+static int
+ak98fsh_bus_resume(struct usb_hcd *hcd)
+{
+	u8 reg;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	reg = fsh_readb(UR_PWM);
+	reg |= (1 << 2);
+	fsh_writeb(reg, UR_PWM);
+	local_irq_restore(flags);
+	msleep(20);
+	local_irq_save(flags);
+	reg = fsh_readb(UR_PWM);
+	reg &= ~(1 << 2);
+	fsh_writeb(reg, UR_PWM);
+	local_irq_restore(flags);
+	msleep(100);
+	return 0;
+}
+
+#else
+
+#define	ak98fsh_bus_suspend	NULL
+#define	ak98fsh_bus_resume	NULL
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+static void disable_clock(void)
+{
+	/*disenable working clock of usb2.0 FS host controller.*/
+	rCLK_CON2 |= 1<<1; 
+	/*close 60M pll1 for usb2.0 fs host.*/
+	rMULFUN_CON1 |= 1<<7; 
+}
+
+static void
+ak98fsh_stop(struct usb_hcd *hcd)
+{
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+	unsigned long	flags;
+
+	del_timer_sync(&hcd->rh_timer);
+	disable_clock();
+	
+	spin_lock_irqsave(&ak98fsh->lock, flags);
+	port_power(ak98fsh, 0);
+	spin_unlock_irqrestore(&ak98fsh->lock, flags);
+}
+
+static void enable_clock(void)
+{
+	/*enable the related working clocks.*/
+	rCLK_CON2 &= ~(1<<1); 
+
+	/*Then open usb module 60M PLL1.*/
+	rMULFUN_CON1 &= (~((0x1<<3)|(3<<6))); 
+}
+
+static void usbhost_reset(void)
+{
+	/*softreset the usb host controller.*/
+	rCLK_CON2 |= 1<<17;
+	mdelay(20);
+	rCLK_CON2 &= ~(1<<17);
+
+	/*To reset the 60M PLL of usb module.*/
+	rMULFUN_CON1 |= 1<<6; 
+	mdelay(20);
+	rMULFUN_CON1 &= ~(1<<6); 
+}
+
+
+static int
+ak98fsh_start(struct usb_hcd *hcd)
+{
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+
+	/*after reset usbhc, set stat to running.*/
+	hcd->state = HC_STATE_RUNNING;
+	
+	/* chip has been reset, VBUS power is off */
+	port_power(ak98fsh, 1);
+	enable_clock();
+	
+	fsh_writeb(0x0, UR_INTECOM);
+	fsh_writew(0x0, UR_INTETX);
+	fsh_writew(0x0, UR_INTERX);
+
+	fsh_writeb(0x0, UR_INDEX);
+
+	/*enable the bus.*/
+	rMULFUN_CON1 &= ~(1<<3); 
+	msleep(1);
+		
+	/* start fs host session*/ 
+	fsh_writeb(0x1, DEV_CTL_REG);
+
+	clear_all_interrupts();
+	fsh_writeb(0x0, UR_FUNADDR);
+
+	reset_endpoints();
+	fsh_writeb(0xF7, UR_INTECOM);
+	
+	return 0;
+}
+
+static struct hc_driver ak98fsh_hc_driver = {
+	.description		= hcd_name,
+	.product_desc 		= "Anyka AK98 USB Full Speed Host Controller",
+	.hcd_priv_size 		= sizeof(struct ak98fsh),
+
+	/*
+	 * generic hardware linkage
+	 */
+	.irq			= ak98fsh_irq,
+	.flags			= HCD_USB11 | HCD_MEMORY,
+
+	/* Basic lifecycle operations */
+	.start			= ak98fsh_start,
+	.stop			= ak98fsh_stop,
+
+	/*
+	 * managing i/o requests and associated device resources
+	 */
+	.urb_enqueue		= ak98fsh_urb_enqueue,
+	.urb_dequeue		= ak98fsh_urb_dequeue,
+	.endpoint_reset		= ak98fsh_endpoint_reset,
+	.endpoint_disable	= ak98fsh_endpoint_disable,
+
+	/*
+	 * periodic schedule support
+	 */
+	.get_frame_number	= ak98fsh_get_frame,
+
+	/*
+	 * root hub support
+	 */
+	.hub_status_data	= ak98fsh_hub_status_data,
+	.hub_control		= ak98fsh_hub_control,
+	.bus_suspend		= ak98fsh_bus_suspend,
+	.bus_resume		= ak98fsh_bus_resume,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __devexit
+ak98fsh_remove(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct ak98fsh *ak98fsh = hcd_to_ak98fsh(hcd);
+	struct resource		*res;
+
+	usb_remove_hcd(hcd);
+
+	/* some platforms may use IORESOURCE_IO */
+	res = platform_get_resource(dev, IORESOURCE_MEM, 1);
+	if (res)
+		iounmap(ak98fsh->data_reg);
+
+	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if (res)
+		iounmap(ak98fsh->addr_reg);
+
+	usb_put_hcd(hcd);
+	return 0;
+}
+
+static int __devinit
+ak98fsh_probe(struct platform_device *dev)
+{
+	struct usb_hcd *hcd;
+	struct ak98fsh *ak98fsh;
+	struct resource		*addr;
+	int			irq;
+	void __iomem		*addr_reg;
+	int			retval;
+	u8			ioaddr = 0;
+	unsigned long		irqflags;
+	int i, j;
+
+	/* basic sanity checks first.  board-specific init logic should
+	 * have initialized these three resources and probably board
+	 * specific platform_data.  we don't probe for IRQs, and do only
+	 * minimal sanity checking.
+	 */
+	irq = platform_get_irq(dev, 0);
+	if (irq <= 0) {
+			dev_err(&dev->dev,
+				"Found HC with no IRQ. Check %s setup!\n",
+				dev_name(&dev->dev));
+			retval = -ENODEV;
+			goto err_nodev;
+	}
+
+	addr = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	if(!addr) { 
+		addr = platform_get_resource(dev, IORESOURCE_IO, 0);
+		if(!addr)
+			return -ENODEV;
+		ioaddr = 1;
+		addr_reg = (void __iomem *) (unsigned long) addr->start;
+	} else {
+		addr_reg = ioremap(addr->start, 1);
+		if (addr_reg == NULL) {
+			retval = -ENOMEM;
+			goto err_nomem;
+		}
+	}
+	
+	/* allocate and initialize hcd */
+	hcd = usb_create_hcd(&ak98fsh_hc_driver, &dev->dev, dev_name(&dev->dev));
+	if (!hcd) {
+		retval = -ENOMEM;
+		goto err_nomem;
+	}
+	
+	hcd->rsrc_start = addr->start;
+	ak98fsh = hcd_to_ak98fsh(hcd);
+
+	spin_lock_init(&ak98fsh->lock);
+	INIT_LIST_HEAD(&ak98fsh->async_ep0);
+	for(i=0; i<MAX_EP_NUM; i++)
+		INIT_LIST_HEAD(&ak98fsh->async_epx[i]);
+	ak98fsh->board = dev->dev.platform_data;
+	init_timer(&ak98fsh->timer);
+	ak98fsh->timer.function = ak98fsh_timer;
+	ak98fsh->timer.data = (unsigned long) ak98fsh;
+	ak98fsh->addr_reg = 0;
+	ak98fsh->data_reg = 0;
+	ak98fsh->active_ep0 = NULL;
+	for(j=0; j<MAX_EP_NUM; j++)
+		ak98fsh->active_epx[j] = NULL;
+	spin_lock_irq(&ak98fsh->lock);
+	port_power(ak98fsh, 0);
+	spin_unlock_irq(&ak98fsh->lock);
+	msleep(200);
+
+	/* The chip's IRQ is level triggered, active high.  A requirement
+	 * for platform device setup is to cope with things like signal
+	 * inverters (e.g. CF is active low) or working only with edge
+	 * triggers (e.g. most ARM CPUs).  Initial driver stress testing
+	 * was on a system with single edge triggering, so most sorts of
+	 * triggering arrangement should work.
+	 *
+	 * Use resource IRQ flags if set by platform device setup.
+	 */
+	irqflags = IRQF_SHARED;
+	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | irqflags);
+	if (retval != 0)
+		goto err_addhcd;
+
+	init_epfifo_mapping(&ak98fsh_epfifo_mapping);
+
+	printk("AK98 USB FS Controller Driver Initialized\n");
+
+	return retval;
+
+ err_addhcd:
+	usb_put_hcd(hcd);
+ err_nomem:
+ err_nodev:
+	printk("Failed to initialize AK98 USB FS Controller Driver\n");
+
+	return retval;
+}
+
+#ifdef	CONFIG_PM
+
+/* for this device there's no useful distinction between the controller
+ * and its root hub, except that the root hub only gets direct PM calls
+ * when CONFIG_USB_SUSPEND is enabled.
+ */
+
+static int
+ak98fsh_suspend(struct platform_device *dev, pm_message_t state)
+{
+	int		retval = 0;
+
+	switch (state.event) {
+	case PM_EVENT_FREEZE:
+		break;
+	case PM_EVENT_SUSPEND:
+	case PM_EVENT_HIBERNATE:
+	case PM_EVENT_PRETHAW:		/* explicitly discard hw state */
+		break;
+	}
+	return retval;
+}
+
+static int
+ak98fsh_resume(struct platform_device *dev)
+{
+	return 0;
+}
+
+#else
+
+#define	ak98fsh_suspend	NULL
+#define	ak98fsh_resume	NULL
+
+#endif
+
+
+struct platform_driver ak98fsh_driver = {
+	.probe =	ak98fsh_probe,
+	.remove =	__devexit_p(ak98fsh_remove),
+
+	.suspend =	ak98fsh_suspend,
+	.resume =	ak98fsh_resume,
+	.driver = {
+		.name =	(char *) hcd_name,
+		.owner = THIS_MODULE,
+	},
+};
+EXPORT_SYMBOL(ak98fsh_driver);
+
+/*-------------------------------------------------------------------------*/
+
+static int __init ak98fsh_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	return platform_driver_register(&ak98fsh_driver);
+}
+module_init(ak98fsh_init);
+
+static void __exit ak98fsh_cleanup(void)
+{
+	platform_driver_unregister(&ak98fsh_driver);
+}
+module_exit(ak98fsh_cleanup);
diff --git a/drivers/usb/host/ak98-fs-hcd.h b/drivers/usb/host/ak98-fs-hcd.h
new file mode 100644
index 00000000000..cfee88bfe42
--- /dev/null
+++ b/drivers/usb/host/ak98-fs-hcd.h
@@ -0,0 +1,766 @@
+/*
+ * AK98HS register declarations and HCD data structures
+ */
+
+#ifndef __AK98_FS_HCD_H
+
+#include <mach/map.h>
+#include <mach/gpio.h>
+
+//#define AK98FS_DEBUG
+#define AK98FS_VERBOSE_DEBUG
+
+/*
+ * Enable DYNAMIC_EPFIFO when you want dynamic endpoint fifo to be allocated to USB device.
+ * For example, if a USB Flash disk has EP 1 + Bulk In / Bulk Out, using DYNAMIC_EPFIFO will
+ * cause EPFIFO 1 <--> Flash Disk EP 1/Bulk In, EPFIFO 2 <--> Flash Disk EP 1/Bulk Out, else
+ * only EPFIFO 1 <--> Flash Disk EP 1 + Bulk In / Bulk Out (Tx/Rx mode will be set on
+ * in_packet() and out_packet())
+ */
+#define DYNAMIC_EPFIFO
+
+#define USBFS_BASE_ADDR (AK98_VA_USB + 0x0800)
+	 
+	 /*Control registers.*/
+#define UR_FUNADDR	0x00		/*Function address register. ---8bit*/
+#define UR_PWM 		0x01 		/* Usb power control register .---8bit*/
+#define UR_INTTX 	0x02		/*Usb TX ep interrupt control register.---16bit */
+#define UR_INTRX 	0x04		/*Usb RX ep interrupt control register.--16bit */
+#define UR_INTETX 	0x06		/*To enable the TX ep interrupt register.--16bit */
+#define UR_INTERX 	0x08		/*To enable the RX ep interrupt register.--16bit */
+#define UR_INTCOM 	0x0a		/*Common usb interrupt register. ---8bit*/
+#define UR_INTECOM	0x0b		/*To enable the common usb interrupt register. --8bit*/
+#define UR_FRMNUM	0x0c		/*Frame number register. ---16bit*/
+#define UR_INDEX	0x0e		/*Index the selected ep control/status register.--8bit */
+#define UR_TESTM	0x0f		/*Test mode enbale for usb2.0 register. --8bit*/
+	 
+	 /*Endpoint Contrl/Status Registers.*/
+#define MaxPackSz_TX	0x10	/*Max packet size for TX EPx.  --16bit*/
+#define CTLSTS_EP_TXL	0x12	/*Contrl & status for TX EPx.--8bit*/
+#define CTLSTS_EP_TXH	0x13	/*Contrl & status for TX EPx.--8bit*/
+#define MaxPackSz_RX	0x14	/*Max packet size for RX EPx.---16bit*/
+#define CTLSTS_EP_RXL	0x16	/*Contrl & status for RX EPx.  --8bit*/
+#define CTLSTS_EP_RXH	0x17	/*Contrl & status for RX EPx.  --8bit*/
+
+#define EP_COUNT		0x18	/*Number of bytes in endpoint X FIFO.--16bit*/
+#define TX_EP_TYPE		0x1a	/*endpoint type for TX endpoint.--8bit*/
+#define NAK_TO_EP0		0x1b	/*NAK response timeout on EP0.--8bit*/
+#define RX_EP_TYPE		0x1c	/*endpoint type for RX endpoint.---8bit*/
+#define RX_INTVAL		0x1d	/*polling interal for RX endpoint.---8bit*/
+#define CFG_FIFO_SZ		0x1f	/*core configuration & FIFO size.---8bit*/
+	 
+	 /*FIFO 32bit registers.Can read write 8bit, 16bit, 32bit.*/
+#define FIFO_EP0		0x20	/*FIFO for EP0.*/
+#define FIFO_EP1		0x24	/*FIFO for EP1.*/
+#define FIFO_EP2		0x28	/*FIFO for EP2.*/
+#define FIFO_EP3		0x2c	/*FIFO for EP3.*/
+#define FIFO_EP4		0x30	/*FIFO for EP4.*/
+#define FIFO_EP5		0x34	/*FIFO for EP5.*/
+#define FIFO_EP6		0x38	/*FIFO for EP6.*/
+
+	 
+	 /*DMA controler registers.*/
+#define USB_DMA_ADDR (AK88_VA_USB + 0x0A00)
+#define DMA_INTR_STAT	0x0		/*DMA interrupt status.*/
+#define DMA_CTRL_REG1	0x04	/*DMA channel 1 control.*/
+#define DMA_CTRL_REG2	0x14	/*DMA channel 2 control.*/
+#define DMA_CTRL_REG3	0x24	/*DMA channel 3 control.*/
+#define DMA_CTRL_REG4	0x34	/*DMA channel 4 control.*/
+#define DMA_CTRL_REG5	0x44	/*DMA channel 5 control.*/
+#define DMA_CTRL_REG6	0x54	/*DMA channel 6 control.*/
+	 
+#define DMA_ADDR_REG1	0x08	/*DMA channel 1 AHB memory address.*/
+#define DMA_ADDR_REG2	0x18	/*DMA channel 2 AHB memory address.*/
+#define DMA_ADDR_REG3	0x28	/*DMA channel 3 AHB memory address.*/
+#define DMA_ADDR_REG4	0x38	/*DMA channel 4 AHB memory address.*/
+#define DMA_ADDR_REG5	0x48	/*DMA channel 5 AHB memory address.*/
+#define DMA_ADDR_REG6	0x58	/*DMA channel 6 AHB memory address.*/
+	 
+#define DMA_CUNT_REG1	0x0c	/*DMA channel 1 byte count.*/
+#define DMA_CUNT_REG2	0x1c	/*DMA channel 2 byte count.*/
+#define DMA_CUNT_REG3	0x2c	/*DMA channel 3 byte count.*/
+#define DMA_CUNT_REG4	0x3c	/*DMA channel 4 byte count.*/
+#define DMA_CUNT_REG5	0x4c	/*DMA channel 5 byte count.*/
+#define DMA_CUNT_REG6	0x5c	/*DMA channel 6 byte count.*/
+	 
+#define DEV_CTL_REG		0x60	/*Device control register.*/
+	 
+	 /*Interrupt types.*/
+#define INTR_CONNECTED	0x10	/*Connected interrupt .*/
+#define INTR_DISCONNECTED	0x20	/*Connected interrupt .*/
+#define INTR_SESION_RQ		0x40    /*Session interrupt.*/
+#define INTR_RESUME		0x02	/* Resume interrupt */
+#define INTR_SOF		0x08    /*Session interrupt.*/
+
+/*====================================*/
+#define H_MAXPACKET	64		/* bytes in fifo */
+
+#define MAX_EP_NUM	(6)
+
+/*-------------------------------------------------------------------------*/
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+struct ak98fsh {
+	spinlock_t		lock;
+	void __iomem		*addr_reg;
+	void __iomem		*data_reg;
+	struct ak98_platform_data	*board;
+	struct proc_dir_entry	*pde;
+
+	unsigned long		stat_insrmv;
+	unsigned long		stat_wake;
+	unsigned long		stat_sof;
+	unsigned long		stat_ep0;
+	unsigned long		stat_epx[MAX_EP_NUM];
+	unsigned long		stat_lost;
+	unsigned long		stat_overrun;
+
+	/* sw model */
+	struct timer_list	timer;
+	struct ak98fsh_ep	*next_periodic;
+	struct ak98fsh_ep	*next_async_ep0;
+	struct ak98fsh_ep	*next_async_epx[MAX_EP_NUM];
+
+	struct ak98fsh_ep	*active_ep0;
+	struct ak98fsh_ep	*active_epx[MAX_EP_NUM];
+	unsigned long		jiffies_ep0;
+	unsigned long		jiffies_epx[MAX_EP_NUM];
+
+	u32			port_status;
+	u16			frame;
+
+	/* async schedule: control, bulk */
+	struct list_head	async_ep0;
+	struct list_head	async_epx[MAX_EP_NUM];
+
+	/* periodic schedule: interrupt, iso */
+	u16			load[PERIODIC_SIZE];
+	struct ak98fsh_ep	*periodic[PERIODIC_SIZE];
+	unsigned		periodic_count;
+};
+
+static inline struct ak98fsh *hcd_to_ak98fsh(struct usb_hcd *hcd)
+{
+	return (struct ak98fsh *) (hcd->hcd_priv);
+}
+
+static inline struct usb_hcd *ak98fsh_to_hcd(struct ak98fsh *ak98fsh)
+{
+	return container_of((void *) ak98fsh, struct usb_hcd, hcd_priv);
+}
+
+struct ak98fsh_ep {
+	struct usb_host_endpoint *hep;
+	struct usb_device	*udev;
+
+	u8			maxpacket;
+	u8			epnum;
+	u8			nextpid;
+
+	u16			error_count;
+	u16			nak_count;
+	u16			length;		/* of current packet */
+
+	/* periodic schedule */
+	u16			period;
+	u16			branch;
+	u16			load;
+	struct ak98fsh_ep	*next;
+
+	/* async schedule */
+	struct list_head	schedule;
+};
+
+/*-------------------------------------------------------------------------*/
+/*
+ * AK98 Full Speed Register Access Routines:
+ * Part I: Common Registers Access(Do NOT use INDEX register)
+ * Part II: Index Registers Access
+ */
+
+/*
+ * Part I: Common Registers Access - Just use USBFS_BASE_ADDR as base address plus offset
+ */
+#define fsh_readb(reg)		__raw_readb(USBFS_BASE_ADDR + (reg))
+#define fsh_writeb(val, reg)	__raw_writeb(val, USBFS_BASE_ADDR + (reg))
+
+#define fsh_readw(reg)		__raw_readw(USBFS_BASE_ADDR + (reg))
+#define fsh_writew(val, reg)	__raw_writew(val, USBFS_BASE_ADDR + (reg))
+
+#define fsh_readl(reg)		__raw_readl(USBFS_BASE_ADDR + (reg))
+#define fsh_writel(val, reg)	__raw_writel(val, USBFS_BASE_ADDR + (reg))
+
+/*
+ * Part II: Index Registers Access - Spinlock+IRQ protection
+ */
+static DEFINE_SPINLOCK(fsh_reg_lock);
+static inline unsigned char fsh_index_readb(int epindex, int reg)
+{
+	unsigned long flags;
+	unsigned char val;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	val = fsh_readb(reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+
+	return val;
+}
+
+static inline void fsh_index_writeb(int epindex, unsigned char val, int reg)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	fsh_writeb(val, reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline unsigned short fsh_index_readw(int epindex, int reg)
+{
+	unsigned long flags;
+	unsigned short val;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	val = fsh_readw(reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+
+	return val;
+
+}
+
+static inline void fsh_index_writew(int epindex, unsigned short val, int reg)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	fsh_writew(val, reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline unsigned long fsh_index_readl(int epindex, int reg)
+{
+	unsigned long flags;
+	unsigned long val;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	val = fsh_readl(reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+
+	return val;
+}
+
+static inline void fsh_index_writel(int epindex, unsigned long val, int reg)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(epindex, UR_INDEX);
+	fsh_writel(val, reg);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+
+}
+
+
+#ifdef AK98FS_DEBUG
+#define HDBG(stuff...) printk("USBFS: " stuff)
+#else
+#define HDBG(fmt, args...) do{}while(0)
+#endif 
+
+#ifdef AK98FS_VERBOSE_DEBUG
+#define VDBG	HDBG
+#else
+#define VDBG(fmt, args...) do{}while(0)
+#endif 
+
+#define ERR(stuff...) printk(KERN_ERR "USBFS: " stuff)
+
+#ifdef AK98FS_VERBOSE_DEBUG
+static inline void dump_registers(void)
+{
+	int i;
+
+	printk("USBFS: FADDR=%d, IntrTXE=%x, IntrRXE=%x, IntrUSBE=%x, DevCtl=%x\n",
+		fsh_readb(UR_FUNADDR), fsh_readw(UR_INTETX), fsh_readw(UR_INTERX),
+		fsh_readb(UR_INTECOM), fsh_readw(DEV_CTL_REG));
+	for (i = 0; i < MAX_EP_NUM + 1; i++) {
+		printk("  EP%d:",i );
+		printk(" NAK_TO_EP=%x, RX_TYPE=%x, TX_TYPE=%x, TXMAXP=%x, " \
+			"RXMAXP=%x, RXCSR=%x, TXCSR=%x, RXINTERVAL=%x\n",
+			fsh_index_readb(i, NAK_TO_EP0), fsh_index_readb(i, RX_EP_TYPE), fsh_index_readb(i, TX_EP_TYPE),
+			fsh_index_readw(i, MaxPackSz_TX), fsh_index_readw(i, MaxPackSz_RX),
+			fsh_index_readw(i, CTLSTS_EP_RXL), fsh_index_readw(i, CTLSTS_EP_TXL),
+			fsh_index_readw(i, RX_INTVAL));
+	}
+}
+#else
+static inline void dump_registers(void)
+{
+}
+#endif
+
+static inline void flush_ep0_fifo(void)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(0, UR_INDEX);
+	if (fsh_readb(CTLSTS_EP_TXL) & ((1 << 0) | (1 << 1)))
+		fsh_writeb(1 << 0, CTLSTS_EP_TXH);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline void flush_epx_tx_fifo(int i)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(i, UR_INDEX);
+	if (fsh_readb(CTLSTS_EP_TXL) & (1 << 0))
+		fsh_writeb(1 << 3, CTLSTS_EP_TXL);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+
+}
+
+static inline void flush_epx_rx_fifo(int i)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(i, UR_INDEX);
+	if (fsh_readb(CTLSTS_EP_RXL) & (1 << 0))
+		fsh_writeb(1 << 4, CTLSTS_EP_RXL);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline void flush_epx_fifo(int i)
+{
+	flush_epx_tx_fifo(i);
+	flush_epx_rx_fifo(i);
+}
+
+static inline void flush_ep_fifo(int i)
+{
+	if (i == 0)
+		flush_ep0_fifo();
+	else
+		flush_epx_fifo(i);
+}
+
+static inline void set_epx_rx_mode(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(i, UR_INDEX);
+	regval = fsh_readb(CTLSTS_EP_TXH);
+	regval &= ~(1 << 5);
+	fsh_writeb(regval, CTLSTS_EP_TXH);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline void set_epx_tx_mode(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	spin_lock_irqsave(&fsh_reg_lock, flags);
+
+	fsh_writeb(i, UR_INDEX);
+	regval = fsh_readb(CTLSTS_EP_TXH);
+	regval |= (1 << 5);
+	fsh_writeb(regval, CTLSTS_EP_TXH);
+
+	spin_unlock_irqrestore(&fsh_reg_lock, flags);
+}
+
+static inline void clear_epx_tx_data_toggle(int i)
+{
+	fsh_index_writeb(i, 1 << 6, CTLSTS_EP_TXL);
+}
+
+static inline void clear_epx_rx_data_toggle(int i)
+{
+	fsh_index_writeb(i, 1 << 7, CTLSTS_EP_RXL);
+}
+
+/*
+ * Valid types:
+ *   1 - Isochronous
+ *   2 - Bulk
+ *   3 - Interrupt
+ * Invalid type:
+ *   0 - Illegal
+ */
+static inline void set_epx_tx_type(int i, int epnum, int type)
+{
+	BUG_ON(i < 0 || i > MAX_EP_NUM);
+	BUG_ON(type < 0 || type > 3);
+
+	fsh_index_writeb(i, type << 4 | epnum, TX_EP_TYPE);
+}
+
+static inline void set_epx_rx_type(int i, int epnum, int type)
+{
+	BUG_ON(i < 0 || i > MAX_EP_NUM);
+	BUG_ON(type < 0 || type > 3);
+
+	fsh_index_writeb(i, type << 4 | epnum, RX_EP_TYPE);
+}
+
+static inline void enable_ep0_interrupt(void)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTETX);
+	regval |= (1 << 0);
+	fsh_writeb(regval, UR_INTETX);
+
+	local_irq_restore(flags);
+}
+
+static inline void enable_epx_tx_interrupt(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTETX);
+	regval |= (1 << i);
+	fsh_writeb(regval, UR_INTETX);
+
+	local_irq_restore(flags);
+}
+
+static inline void enable_epx_rx_interrupt(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTERX);
+	regval |= (1 << i);
+	fsh_writeb(regval, UR_INTERX);
+
+	local_irq_restore(flags);
+}
+
+static inline void disable_ep0_interrupt(void)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTETX);
+	regval &= ~(1 << 0);
+	fsh_writeb(regval, UR_INTETX);
+
+	local_irq_restore(flags);
+}
+
+static inline void disable_epx_tx_interrupt(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTETX);
+	regval &= ~(1 << i);
+	fsh_writeb(regval, UR_INTETX);
+
+	local_irq_restore(flags);
+}
+
+static inline void disable_epx_rx_interrupt(int i)
+{
+	u8 regval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	regval = fsh_readb(UR_INTERX);
+	regval &= ~(1 << i);
+	fsh_writeb(regval, UR_INTERX);
+
+	local_irq_restore(flags);
+}
+
+static inline void disable_epx_interrupt(int i)
+{
+	disable_epx_tx_interrupt(i);
+	disable_epx_rx_interrupt(i);
+}
+
+static inline void disable_ep_interrupt(int i)
+{
+	BUG_ON(i < 0 || i > MAX_EP_NUM);
+
+	if (i == 0) {
+		disable_ep0_interrupt();
+	} else {
+		disable_epx_interrupt(i);
+	}
+}
+
+static inline void clear_all_interrupts(void)
+{
+	fsh_readb(UR_INTCOM);
+	fsh_readw(UR_INTTX);
+	fsh_readw(UR_INTRX);
+}
+
+static inline void reset_endpoint(int i)
+{
+	BUG_ON(i < 0 || i > MAX_EP_NUM);
+
+	disable_ep_interrupt(i);
+	if (i == 0) {
+		flush_ep0_fifo();
+	} else {
+		flush_epx_fifo(i);
+		set_epx_rx_type(i, 0, 0);
+		set_epx_tx_type(i, 0, 0);
+	}
+}
+
+static inline void reset_endpoints(void)
+{
+	int i;
+
+	for (i = 0; i < MAX_EP_NUM + 1; i++) {
+		reset_endpoint(i);
+	}
+}
+
+
+
+
+struct epfifo_mapping {
+	int	epfifo;		/* AK98 FSH HC EP FIFO number: 1 ~ 6 */
+	int	used;		/* 0 - Unused, 1 - used */
+	int	epnum;		/* USB Device endpoint number: 1 ~ 16 */
+	int	direction;	/* 0 - In, 1 - Out */
+};
+
+struct ak98fsh_epfifo_mapping {
+	spinlock_t lock;
+	struct epfifo_mapping mapping[MAX_EP_NUM];
+};
+
+static inline void dump_epfifo_mapping(struct ak98fsh_epfifo_mapping *ak98_mapping)
+{
+	int i;
+	struct epfifo_mapping *mapping;
+
+	for (i = 0; i < MAX_EP_NUM; i++) {
+		mapping = &ak98_mapping->mapping[i];
+		printk("EPFIFO %d: %s, Device EP NO. %d, Direction %s\n",
+			mapping->epfifo, mapping->used ? "Allocated" : "Free",
+			mapping->epnum, mapping->direction ? "OUT" : "IN");
+	}
+
+}
+
+static inline void init_epfifo_mapping(struct ak98fsh_epfifo_mapping *ak98_mapping)
+{
+	int i;
+	struct epfifo_mapping *mapping;
+
+	spin_lock_init(&ak98_mapping->lock);
+	
+	for (i = 0; i < MAX_EP_NUM; i++) {
+		mapping = &ak98_mapping->mapping[i];
+		mapping->epfifo = i + 1;	/* EPFIFO 1~6 is used by AK98 FS HCD */
+		mapping->used = 0;
+		mapping->epnum = 0;
+		mapping->direction = 0;
+	}
+}
+
+static inline bool __is_epnum_mapped(struct ak98fsh_epfifo_mapping *ak98_mapping,
+	int epnum, int direction)
+{
+	int i;
+	struct epfifo_mapping *mapping;
+
+	if(epnum == 0)
+		return true;
+
+	for (i = 0; i < MAX_EP_NUM; i++) {
+		mapping = &ak98_mapping->mapping[i];
+		if (mapping->used && (mapping->epnum == epnum) && (mapping->direction == direction)) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static inline bool is_epnum_mapped(struct ak98fsh_epfifo_mapping *ak98_mapping,
+	int epnum, int direction)
+{
+	bool ret;
+	unsigned long flags;
+
+	BUG_ON(ak98_mapping == NULL);
+
+	if(epnum == 0)
+		return true;
+
+	spin_lock_irqsave(&ak98_mapping->lock, flags);
+
+	ret = __is_epnum_mapped(ak98_mapping, epnum, direction);
+
+	spin_unlock_irqrestore(&ak98_mapping->lock, flags);
+
+	return ret;
+
+}
+
+static inline bool __map_epnum_to_epfifo(struct ak98fsh_epfifo_mapping *ak98_mapping,
+	int epnum, int direction, int *epfifo)
+{
+	int i;
+	struct epfifo_mapping *mapping;
+
+	if (__is_epnum_mapped(ak98_mapping, epnum, direction))
+		return false;
+
+	for (i = 0; i < MAX_EP_NUM; i++) {
+		mapping = &ak98_mapping->mapping[i];
+		if (!mapping->used) {
+			mapping->used = 1;
+			mapping->epnum = epnum;
+			mapping->direction = direction;
+			*epfifo = mapping->epfifo;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static inline bool map_epnum_to_epfifo(struct ak98fsh_epfifo_mapping *ak98_mapping,
+	int epnum, int direction, int *epfifo)
+{
+	bool ret;
+	unsigned long flags;
+
+	BUG_ON(ak98_mapping == NULL);
+
+	if (is_epnum_mapped(ak98_mapping, epnum, direction))
+		return false;
+
+	spin_lock_irqsave(&ak98_mapping->lock, flags);
+	
+	ret = __map_epnum_to_epfifo(ak98_mapping, epnum, direction, epfifo);
+
+	spin_unlock_irqrestore(&ak98_mapping->lock, flags);
+
+	return ret;
+}
+
+#ifdef DYNAMIC_EPFIFO
+static inline bool epfifo_to_epnum(struct ak98fsh_epfifo_mapping *ak98_mapping, int epfifo, int *epnum, int *direction)
+{
+	int ret;
+	unsigned long flags;
+	struct epfifo_mapping *mapping;
+
+	ret = false;
+
+	spin_lock_irqsave(&ak98_mapping->lock, flags);
+
+	mapping = &ak98_mapping->mapping[epfifo];
+	if (mapping->used) {
+		*epnum = mapping->epnum;
+		*direction = mapping->direction;
+		ret = true;
+	} else {
+		*epnum = 0;
+		*direction = 0;
+		ret = false;
+	}
+
+	spin_unlock_irqrestore(&ak98_mapping->lock, flags);
+
+	return ret;
+}
+
+static inline bool epnum_to_epfifo(struct ak98fsh_epfifo_mapping *ak98_mapping, int epnum, int direction, int *epfifo)
+{
+	int i;
+	unsigned long flags;
+	struct epfifo_mapping *mapping;
+
+	if (epnum == 0) {
+		*epfifo = 0;
+		return true;
+	}
+
+	spin_lock_irqsave(&ak98_mapping->lock, flags);
+
+	for (i = 0; i < MAX_EP_NUM; i++) {
+		mapping = &ak98_mapping->mapping[i];
+		if (mapping->used && (mapping->epnum == epnum) && (mapping->direction == direction)) {
+			*epfifo = mapping->epfifo;
+			spin_unlock_irqrestore(&ak98_mapping->lock, flags);
+			return true;
+		}
+	}
+
+	spin_unlock_irqrestore(&ak98_mapping->lock, flags);
+
+	return false;
+}
+#else
+static inline bool epfifo_to_epnum(struct ak98fsh_epfifo_mapping *ak98_mapping, int epfifo, int *epnum, int *direction)
+{
+	*epnum = epfifo;
+	*direction  = 0;	/* Useless, since 1 EPFIFO could be mapped to 1 device ep/in + out */
+	return true;
+}
+
+static inline bool epnum_to_epfifo(struct ak98fsh_epfifo_mapping *ak98_mapping, int epnum, int direction, int *epfifo)
+{
+	*epfifo = epnum;
+	return true;
+}
+#endif
+
+#endif /* __AK98_FS_HCD_H */
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 188e1ba3b69..33aff0902e9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2160,6 +2160,46 @@ config FB_BROADSHEET
 	  and could also have been called by other names when coupled with
 	  a bridge adapter.
 
+config FB_AK98
+	tristate "Anyka AK98 LCD framebuffer support"
+	depends on FB && ARCH_AK98
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	---help---
+	  Frame buffer driver for the built-in LCD controller in the Anyka
+	  AK98 SoC.
+
+	  This driver is also available as a module ( = code which can be
+	  inserted and removed from the running kernel whenever you want). The
+	  module will be called ak98fb. If you want to compile it as a module,
+	  say M here and read <file:Documentation/kbuild/modules.txt>.
+
+	  If unsure, say N.
+
+choice
+	prompt "LCD panels for AK98 Athena board"
+	depends on FB_AK98
+
+config LCD_PANEL_QD043003C0_40
+	bool "Qiaodian QD043003C0-40 4.3\" 480x272 TFT LCD Panel"
+
+config LCD_PANEL_AT043TN24
+	bool "InnoLux AT043TN24 4.3\" 480x272 TFT LCD Panel"
+
+config LCD_PANEL_A050VW01_V5
+	bool "AUO A050VW01-V5 5\" WVGA TFT LCD Panel"
+
+config LCD_PANEL_LW700AT9009
+	bool "ChiMei LW700AT9009 7\" WVGA TFT LCD Panel"
+
+config LCD_PANEL_AT070TN92
+	bool "InnoLux AT070TN92 7\" WVGA TFT LCD Panel"
+
+endchoice
+
+source "drivers/video/ak88-fb/Kconfig"
+
 source "drivers/video/omap/Kconfig"
 
 source "drivers/video/backlight/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 80232e12488..f3f93f900a5 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -139,6 +139,8 @@ obj-$(CONFIG_FB_BF54X_LQ043)	  += bf54x-lq043fb.o
 obj-$(CONFIG_FB_BFIN_T350MCQB)	  += bfin-t350mcqb-fb.o
 obj-$(CONFIG_FB_MX3)		  += mx3fb.o
 obj-$(CONFIG_FB_DA8XX)		  += da8xx-fb.o
+obj-$(CONFIG_FB_AK98)		  += ak98fb.o ak_logo.o
+obj-$(CONFIG_FB_AK88)		  += ak88-fb/
 
 # the test framebuffer is last
 obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
diff --git a/drivers/video/ak88-fb/Kconfig b/drivers/video/ak88-fb/Kconfig
new file mode 100644
index 00000000000..132916e64cf
--- /dev/null
+++ b/drivers/video/ak88-fb/Kconfig
@@ -0,0 +1,23 @@
+
+
+config FB_AK88
+    tristate "AK88 LCD framebuffer support"
+    depends on FB && ARCH_AK88
+    select FB_CFB_FILLRECT
+    select FB_CFB_COPYAREA
+    select FB_CFB_IMAGEBLIT
+    help
+      Frame buffer driver for the built-in LCD controller in the AK88
+      processor.
+
+      If unsure, Say N.
+
+config FB_AK88_DEBUG
+    bool "AK88 lcd debug messages"
+    depends on FB_AK88
+    help
+      Turn on debugging messages. Note that you set/unset at run time
+      through sysfs.
+
+
+
diff --git a/drivers/video/ak88-fb/Makefile b/drivers/video/ak88-fb/Makefile
new file mode 100644
index 00000000000..f7c10d88d46
--- /dev/null
+++ b/drivers/video/ak88-fb/Makefile
@@ -0,0 +1,4 @@
+
+#obj-$(CONFIG_FB_AK88)          += ak88_fb.o
+obj-$(CONFIG_FB_AK88)       += ak88_lcdfb.o
+
diff --git a/drivers/video/ak88-fb/ak8801fb.h b/drivers/video/ak88-fb/ak8801fb.h
new file mode 100644
index 00000000000..8ac9d7676af
--- /dev/null
+++ b/drivers/video/ak88-fb/ak8801fb.h
@@ -0,0 +1,24 @@
+/*
+ */
+
+#ifndef __AK88FB_H_
+#define __AK88FB_H_
+
+struct ak880xfb_info {
+	struct device		*dev;
+	struct clk		*clk;
+	
+	struct resource		*mem;
+	void __iomem		*io;
+	void __iomem		*irq_base;
+	
+	//struct ak7801fb_hw	regs;
+
+	unsigned int		palette_ready;
+	
+	/* keep these registers in case we need to re-write palette */
+	u32			palette_buffer[256];
+	u32			pseudo_pal[16];
+};
+
+#endif
diff --git a/drivers/video/ak88-fb/ak88_fb.c b/drivers/video/ak88-fb/ak88_fb.c
new file mode 100644
index 00000000000..f164d4ffca3
--- /dev/null
+++ b/drivers/video/ak88-fb/ak88_fb.c
@@ -0,0 +1,473 @@
+/*
+ * linux/drivers/video/ak880xfb.c
+ * 
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/div64.h>
+
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#include <mach/map.h>
+#include <mach/ak880x_addr.h>
+#include <mach/gpio.h>
+
+#define lcd_set_bit(reg, set_mask, clr_mask)  \
+	do {                                        \
+		unsigned long val = 0;                  \
+		val = (reg);                            \
+		val &= ~(clr_mask);                     \
+		val |= (set_mask);                      \
+		reg = val;                              \
+	} while(0)
+
+/* Debugging stuff */
+#ifdef CONFIG_FB_AK88_DEBUG
+static int debug	= 1;
+#else
+static int debug	= 0;
+#endif
+
+#define dprintk(msg...)	if (debug) { printk(KERN_DEBUG "ak880xfb: " msg); }
+
+#define	AUTO_REFRESH 0
+#define	STOP_AUTO 1
+#define	MANUAL_REFRESH 2
+
+#define FIFO_ALARM_STAT (1<<18)
+#define ALERT_VALID_STAT (1<<17)
+#define MPU_DISPLAY_OK_STAT (1<<2)
+
+#define	LCD_M			0
+#define	LCD_S			1
+#define	LCD_MPU_CMD		0
+#define	LCD_MPU_DATA	1
+
+
+#define MAIN_LCD_MPU_CMD				0x00000000	//master LCD command
+#define MAIN_LCD_MPU_DATA				0x00080000	//master LCD data
+#define SUB_LCD_MPU_CMD					0x00040000	//slaver LCD command
+#define SUB_LCD_MPU_DATA				0x000C0000	//slaver LCD data
+
+
+
+struct fb_info *fbinfo;
+static unsigned long save[53];
+static unsigned long blank;
+
+unsigned char			lcd_auto_refresh = 0 ;
+unsigned int			refresh_count = 0 ;
+unsigned int			pseudo_pal[16];
+
+
+
+void index_out(unsigned int lcd, unsigned short reg_index)
+{
+	rLCD_COMM2 = (MAIN_LCD_MPU_CMD|reg_index);
+}
+
+
+static void data_out(unsigned int lcd, unsigned short reg_data)
+{
+	rLCD_COMM2 = MAIN_LCD_MPU_DATA|reg_data;
+}
+
+static void lcd_write_reg( unsigned short index, unsigned short data )
+{
+	int lcd =0;
+	index_out(lcd, index);
+	udelay(100);
+	data_out(lcd, data);
+}
+
+
+
+void lcd_set_mode(unsigned int IF_Sel, unsigned int Disply_Color_Sel, 
+		unsigned int Bus_Sel, unsigned int W_Len1, unsigned int W_Len2)
+{
+	unsigned int mode = 0;
+	unsigned int A0_polarity = 1;
+
+	if (IF_Sel == 0x00)
+	{
+		IF_Sel = 0x2;
+	}
+	else if (IF_Sel == 0x01) 
+	{
+		IF_Sel = 0x3; 
+	}
+	else if (IF_Sel == 0x02)
+	{
+		IF_Sel = 0x1; 
+	}
+	else
+	{
+		return;
+	}
+
+	W_Len1 &= 0x7f;
+	W_Len2 &= 0x1f;
+
+	lcd_set_bit(rLCD_COMM1, 0, 1<<4);
+	lcd_set_bit(rLCD_COMM1, 0, 3<<5);
+	lcd_set_bit(rLCD_COMM1, IF_Sel<<5, 0);
+	lcd_set_bit(rLCD_COMM1, 0, 1<<15);
+
+	mode = 0;
+	mode |=  (Bus_Sel << 14);
+	mode |=  (Disply_Color_Sel << 13);
+	mode |=  (W_Len1 << 6);
+	mode |=  (W_Len2 << 1);
+	mode |=  A0_polarity;
+	rLCD_MPUIFCON = mode;
+}
+
+
+void start_dma(void)
+{
+#if defined( CONFIG_LCD_HX8352 )
+	*(volatile unsigned int *)(AK88_VA_DISPLAY + 0x00B4) =  0x2c; //LCD_REG_CONFIG_REG
+#else
+	*(volatile unsigned int *)(AK88_VA_DISPLAY + 0x00B4) =  0x22; //LCD_REG_CONFIG_REG
+#endif
+}
+
+
+void display_refresh(void)
+{
+	*(volatile unsigned int*)(AK88_VA_DISPLAY + 0x00B8) = ( 1<<3 | 0<<2 | 0 );
+}
+
+
+static struct timer_list lcd_refresh_timer;
+
+static void jiffies_timer(unsigned long data)
+{
+	int delay = HZ/20;
+
+	if(blank == 0)
+	{
+		start_dma();
+		display_refresh();
+		mod_timer(&lcd_refresh_timer, jiffies + delay);
+	}
+}
+
+
+
+static int ak880xfb_check_var(struct fb_var_screeninfo *var,
+			       struct fb_info *info)
+{
+	var->transp.msb_right    = 0;
+	var->transp.offset    = 0;
+	var->transp.length = 0;
+	return 0;
+}
+
+
+static void ak880xfb_activate_var(struct fb_info *info)
+{
+}
+
+
+static int ak880xfb_set_par(struct fb_info *info)
+{
+	struct fb_var_screeninfo *var = &info->var;
+	return 0;
+}
+
+
+static int ak880xfb_setcolreg(unsigned regno,
+			       unsigned red, unsigned green, unsigned blue,
+			       unsigned transp, struct fb_info *info)
+{
+
+	unsigned int val;
+	return 0;
+}
+
+
+
+void ILI9481_CPT_Initial_Code( unsigned int lcd ) 
+{ 
+	index_out(lcd,0x11);
+	mdelay(20);
+	index_out( lcd, 0xd0 );
+	data_out( lcd, 0x07 );
+	data_out( lcd, 0x42 );
+	data_out( lcd, 0x0c );
+	mdelay(10); 
+	index_out( lcd, 0xd1 );
+	data_out( lcd, 0x00 );
+	data_out( lcd, 0x12 );
+	data_out( lcd, 0x14 );
+	mdelay(10);
+	index_out( lcd, 0xd2 );
+	data_out( lcd, 0x01 );
+	data_out( lcd, 0x00 );
+	index_out( lcd, 0xc0 );
+	data_out( lcd, 0x14 );
+	data_out( lcd, 0x3c );
+	data_out( lcd, 0x3c );
+	data_out( lcd, 0x02 );
+	data_out( lcd, 0x11 );
+	index_out( lcd, 0xc5 );
+	data_out( lcd, 0x03 );
+	index_out( lcd, 0x3a );
+	data_out( lcd, 0x55 );
+	index_out(lcd,0xC8);
+	data_out(lcd,0x00);
+	data_out(lcd,0x32);
+	data_out(lcd,0x25);
+	data_out(lcd,0x15);
+	data_out(lcd,0x08);
+	data_out(lcd,0x05);
+	data_out(lcd,0x25);
+	data_out(lcd,0x54);
+	data_out(lcd,0x77);
+	data_out(lcd,0x51);
+	data_out(lcd,0x07);
+	data_out(lcd,0x08);
+	index_out(lcd,0xF3);
+	data_out(lcd,0x24); 
+	data_out(lcd,0x1A); 
+	index_out(lcd,0xF7);
+	data_out(lcd,0xC0);
+	data_out(lcd,0x01);
+	index_out(lcd,0x36);
+	data_out(lcd,0x08);
+	index_out(lcd,0x2A);
+	data_out(lcd,0x00);
+	data_out(lcd,0x00);
+	data_out(lcd,0x01);
+	data_out(lcd,0x3F);
+	index_out(lcd,0x2B);
+	data_out(lcd,0x00);
+	data_out(lcd,0x00);
+	data_out(lcd,0x00);
+	data_out(lcd,0xEF);
+	mdelay(50);
+	index_out(lcd,0x29);
+}
+
+
+void start_lcd(void)
+{
+	if(blank == 0)
+	{
+		ILI9481_CPT_Initial_Code(0);
+		start_dma();
+		display_refresh();
+		mod_timer(&lcd_refresh_timer, jiffies + HZ/20);
+	}
+	else
+		blank = 4;
+}
+
+
+static int ak880xfb_blank(int blank_mode, struct fb_info *info)
+{
+	blank = blank_mode;
+	start_lcd();
+	return 0;
+}
+
+
+static int ak880xfb_debug_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
+}
+
+
+static int ak880xfb_debug_store(struct device *dev,
+				 struct device_attribute *attr,
+				 const char *buf, size_t len)
+{
+	if (len < 1)
+		return -EINVAL;
+	return len;
+}
+
+
+
+static struct fb_ops ak880xfb_ops = {
+	.owner		= THIS_MODULE,
+	.fb_check_var	= ak880xfb_check_var,
+	.fb_set_par	= ak880xfb_set_par,
+	.fb_blank	= ak880xfb_blank,
+	.fb_setcolreg	= ak880xfb_setcolreg,
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+};
+
+
+static int __init ak880xfb_map_video_memory(struct fb_info *info)
+{
+	info->screen_base = ioremap(0x33f00000, 240*320*2) ;
+	info->screen_size = 240*320*2;
+
+	return 0;
+}
+
+static inline void ak880xfb_unmap_video_memory(struct fb_info *info)
+{
+	iounmap( info->screen_base ) ;
+}
+
+
+static char driver_name[] = "ak880xfb";
+
+static int __init ak880xfb_probe(struct platform_device *pdev)
+{
+	int ret;
+	int i = 0, logo_len = 0 ;
+	unsigned short * logo_p = NULL ;
+
+	init_timer(&lcd_refresh_timer);
+	lcd_refresh_timer.function = jiffies_timer ;
+
+	fbinfo = framebuffer_alloc(0, &pdev->dev);
+	if (!fbinfo)
+		return -ENOMEM;
+
+	strcpy(fbinfo->fix.id, driver_name);
+	fbinfo->fbops			= &ak880xfb_ops;
+	fbinfo->flags			= FBINFO_FLAG_DEFAULT;
+	fbinfo->fix.type		= FB_TYPE_PACKED_PIXELS;
+	fbinfo->var.activate		= FB_ACTIVATE_NOW;
+	fbinfo->pseudo_palette		= &pseudo_pal;
+
+#if defined( CONFIG_LCD_HX8352 )
+	fbinfo->var.xres		= 320;
+	fbinfo->var.yres		= 240;
+	fbinfo->var.bits_per_pixel	= 16;
+
+	fbinfo->var.red.offset		= 11;
+	fbinfo->var.green.offset	= 5;
+	fbinfo->var.blue.offset		= 0;
+	fbinfo->var.transp.offset	= 0;
+	fbinfo->var.red.length		= 5;
+	fbinfo->var.green.length	= 6;
+	fbinfo->var.blue.length		= 5;
+	fbinfo->var.transp.length	= 0;
+	fbinfo->fix.smem_len		= 320*240*16/8 ;
+	fbinfo->fix.line_length		=  320*16/8 ;
+	fbinfo->fix.visual		= FB_VISUAL_TRUECOLOR;
+
+#else
+	fbinfo->var.xres		= 240;
+	fbinfo->var.yres		= 320;
+	fbinfo->var.bits_per_pixel	= 16;
+
+	fbinfo->var.red.offset		= 11;
+	fbinfo->var.green.offset	= 5;
+	fbinfo->var.blue.offset		= 0;
+	fbinfo->var.transp.offset	= 0;
+	fbinfo->var.red.length		= 5;
+	fbinfo->var.green.length	= 6;
+	fbinfo->var.blue.length		= 5;
+	fbinfo->var.transp.length	= 0;
+	fbinfo->fix.smem_len		= 240*320*16/8 ;
+	fbinfo->fix.line_length		=  240*16/8 ;
+	fbinfo->fix.visual		= FB_VISUAL_TRUECOLOR;
+#endif
+
+	ret = ak880xfb_map_video_memory(fbinfo);
+	if (ret) {
+		printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
+		ret = -ENOMEM;
+		goto dealloc_fb;
+	}
+	fbinfo->fix.smem_start = 0x30000000 + 0x3f00000 ;
+
+#if 0
+	logo_len = sizeof(newplus_logo) ;
+	logo_p = (unsigned short *)fbinfo->screen_base ;
+	for(i=0; i<logo_len/2; i++ )
+		*(logo_p + i ) = 0x00;//newplus_logo[i] ;
+#endif
+
+	lcd_auto_refresh = 1 ;
+	refresh_count = 0 ;
+	start_dma();
+	display_refresh();
+
+	ret = register_framebuffer(fbinfo);
+	if (ret < 0) {
+		printk(KERN_ERR "Failed to register framebuffer device: %d\n",
+			ret);
+		goto free_video_memory;
+	}
+
+	printk(KERN_INFO "fb%d: %s frame buffer device\n",
+		fbinfo->node, fbinfo->fix.id);
+
+	printk("register_framebuffer\n") ;
+	return 0;
+
+free_video_memory:
+	ak880xfb_unmap_video_memory(fbinfo);
+dealloc_fb:
+	platform_set_drvdata(pdev, NULL);
+	framebuffer_release(fbinfo);
+	if( timer_pending( &lcd_refresh_timer ) )
+		del_timer( &lcd_refresh_timer ) ;
+	return ret;
+	return 0;
+}
+
+
+static int ak880xfb_remove(struct platform_device *pdev)
+{
+	if( timer_pending( &lcd_refresh_timer ) )
+		del_timer( &lcd_refresh_timer ) ;
+	return 0;
+}
+
+
+static struct platform_driver ak880xfb_driver = {
+	.probe		= ak880xfb_probe,
+	.remove		= ak880xfb_remove,
+	.driver		= {
+		.name	= "ak880x-lcd",
+		.owner	= THIS_MODULE,
+	},
+};
+
+int __init ak880xfb_init(void)
+{
+	printk("AK88 Framebuffer Driver, (c) 2010 ANYKA\n");
+
+	return platform_driver_register(&ak880xfb_driver);
+}
+
+static void __exit ak880xfb_cleanup(void)
+{
+	platform_driver_unregister(&ak880xfb_driver);
+}
+
+module_init(ak880xfb_init);
+module_exit(ak880xfb_cleanup);
+
+MODULE_AUTHOR("anyka");
+MODULE_DESCRIPTION("Framebuffer driver for the ak880x");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/ak88-fb/ak88_lcdfb.c b/drivers/video/ak88-fb/ak88_lcdfb.c
new file mode 100644
index 00000000000..3fd42418edf
--- /dev/null
+++ b/drivers/video/ak88-fb/ak88_lcdfb.c
@@ -0,0 +1,919 @@
+/*
+ *  Driver for AK88 LCD Controller
+ *
+ *  Copyright (C) 2010 Anyka Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/backlight.h>
+
+
+#include <video/anyka_lcdc.h>
+
+#include <mach/map.h>
+#include <mach/devices_ak880x.h>
+#include <mach/lib_lcd.h>
+#include <mach/ak880x_freq.h>
+#include <mach/clock.h>
+#include <mach/ak880x_addr.h>
+
+
+#define	ANYKA_LCDFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
+					 | FBINFO_PARTIAL_PAN_OK \
+					 | FBINFO_HWACCEL_YPAN)
+
+static wait_queue_head_t wq;
+
+ 
+void init_backlight(struct anyka_lcdfb_info *sinfo)
+{
+	dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
+}
+
+static void exit_backlight(struct anyka_lcdfb_info *sinfo)
+{
+}
+
+ 
+static void init_contrast(struct anyka_lcdfb_info *sinfo)
+{
+	/* have some default contrast/backlight settings */
+	printk("init_contrast()\n");
+
+	bsplcd_set_panel_power(1);	//pullup TFT_VGH_L and TFT_AVDD
+
+	baselcd_set_panel_backlight(1);
+
+}
+
+static struct fb_fix_screeninfo anyka_lcdfb_fix __initdata = {
+	.type = FB_TYPE_PACKED_PIXELS,	//defined in linux/fb.h
+	.visual = FB_VISUAL_TRUECOLOR,
+	.xpanstep = 0,		/* zero if no hardware panning  */
+	.ypanstep = 1,		/* zero if no hardware panning  */
+	.ywrapstep = 0,		//?? I don't know what it means /* zero if no hardware ywrap    */
+	.accel = FB_ACCEL_NONE,	/* no hardware accelerator     */
+};
+
+unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+{
+	unsigned long value;
+
+	value = xres;
+	//assume ak880x use TFT PANEL
+
+	return value;
+}
+
+static void anyka_lcdfb_stop_nowait(struct anyka_lcdfb_info *sinfo)
+{
+//stop refresh
+//shouldn't write any command for AK88
+
+
+}
+
+
+void anyka_lcdfb_stop(struct anyka_lcdfb_info *sinfo)
+{
+	anyka_lcdfb_stop_nowait(sinfo);
+
+	/* Wait for DMA engine to become idle... */
+	msleep(10);
+
+}
+
+void anyka_lcdfb_start(struct anyka_lcdfb_info *sinfo)
+{
+//start refresh
+	LCD_IF_MODE if_mode = LCD_IF_RGB;
+
+	lcd_rgb_set_interface(if_mode);
+
+	lcd_rgb_start_refresh();	
+
+	baselcd_set_panel_backlight(1);
+
+
+	mdelay(1000);
+	printk("anyka_lcdfb_start()\n");
+
+}
+
+static void anyka_lcdfb_update_dma(struct fb_info *info,
+				   struct fb_var_screeninfo *var)
+{
+	struct fb_fix_screeninfo *fix = &info->fix;
+	unsigned long dma_addr;
+
+	dma_addr = (fix->smem_start + var->yoffset * fix->line_length
+		    + var->xoffset * var->bits_per_pixel / 8);
+
+	dma_addr &= ~3UL;
+
+	/* Set framebuffer DMA base address and pixel offset */
+
+	lcd_fb_init_ram(dma_addr, var->xres, var->yres);
+
+	lcd_controller_fastdma();
+
+	printk("anyka_lcdfb_update_dma()\n");
+
+}
+
+static inline void anyka_lcdfb_free_video_memory(struct anyka_lcdfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+
+	dma_free_writecombine(info->device, info->fix.smem_len,
+			      info->screen_base, info->fix.smem_start);
+
+	printk("anyka_lcdfb_free_video_memory()\n");
+
+}
+
+/**
+ *	anyka_lcdfb_alloc_video_memory - Allocate framebuffer memory
+ *	@sinfo: the frame buffer to allocate memory for
+ * 	
+ * 	This function is called only from the anyka_lcdfb_probe()
+ * 	so no locking by fb_info->mm_lock around smem_len setting is needed.
+ */
+static int anyka_lcdfb_alloc_video_memory(struct anyka_lcdfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+	struct fb_var_screeninfo *var = &info->var;
+	unsigned int smem_len;
+
+	smem_len = (var->xres_virtual * var->yres_virtual
+		    * ((var->bits_per_pixel + 7) / 8));
+	info->fix.smem_len = max(smem_len, sinfo->smem_len);
+
+	info->screen_base =
+	    dma_alloc_writecombine(info->device, info->fix.smem_len,
+				   (dma_addr_t *) & info->fix.smem_start,
+				   GFP_KERNEL);
+
+	//fix.smem_start : dma address ,the address that be wrote to register
+
+	if (!info->screen_base) {
+		return -ENOMEM;
+	}
+
+	printk("anyka_lcdfb_alloc_video_memory()\n");
+
+	return 0;
+}
+
+static const struct fb_videomode *anyka_lcdfb_choose_mode(struct
+							  fb_var_screeninfo
+							  *var,
+							  struct fb_info *info)
+{
+	struct fb_videomode varfbmode;
+	const struct fb_videomode *fbmode = NULL;
+
+	fb_var_to_videomode(&varfbmode, var);
+	fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
+	if (fbmode)
+		fb_videomode_to_var(var, fbmode);
+
+	printk("anyka_lcdfb_choose_mode()\n");
+	return fbmode;
+}
+
+/**
+ *      anyka_lcdfb_check_var - Validates a var passed in.
+ *      @var: frame buffer variable screen structure
+ *      @info: frame buffer structure that represents a single frame buffer
+ *
+ *	Checks to see if the hardware supports the state requested by
+ *	var passed in. This function does not alter the hardware
+ *	state!!!  This means the data stored in struct fb_info and
+ *	struct anyka_lcdfb_info do not change. This includes the var
+ *	inside of struct fb_info.  Do NOT change these. This function
+ *	can be called on its own if we intent to only test a mode and
+ *	not actually set it. The stuff in modedb.c is a example of
+ *	this. If the var passed in is slightly off by what the
+ *	hardware can support then we alter the var PASSED in to what
+ *	we can do. If the hardware doesn't support mode change a
+ *	-EINVAL will be returned by the upper layers. You don't need
+ *	to implement this function then. If you hardware doesn't
+ *	support changing the resolution then this function is not
+ *	needed. In this case the driver would just provide a var that
+ *	represents the static state the screen is in.
+ *
+ *	Returns negative errno on error, or zero on success.
+ */
+static int anyka_lcdfb_check_var(struct fb_var_screeninfo *var,
+				 struct fb_info *info)
+{
+	struct device *dev = info->device;
+	struct anyka_lcdfb_info *sinfo = info->par;
+	unsigned long clk_value_hz;
+
+	//clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+
+ 	//clk_value_hz = ak880x_asicfreq_get();	//124MHZ
+	clk_value_hz = (unsigned long)clk_get_rate(clk_get(NULL,"asic_clk"));
+ 
+	dev_dbg(dev, "%s:\n", __func__);
+
+ 
+	if (!(var->pixclock && var->bits_per_pixel)) {
+		/* choose a suitable mode if possible */
+		if (!anyka_lcdfb_choose_mode(var, info)) {
+			dev_err(dev, "needed value not specified\n");
+			printk("error:needed value not specified\n");
+			return -EINVAL;
+		}
+	}
+
+ 
+	if ((var->pixclock) > clk_value_hz) {
+		//dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
+		printk("%lu Hz pixel clock is too fast\n",
+		       (unsigned long)var->pixclock);
+		return -EINVAL;
+	}
+
+	/* Do not allow to have real resoulution larger than virtual */
+	if (var->xres > var->xres_virtual)
+		var->xres_virtual = var->xres;
+
+	if (var->yres > var->yres_virtual)
+		var->yres_virtual = var->yres;
+
+	/* Force same alignment for each line */
+	var->xres = (var->xres + 3) & ~3UL;
+	var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
+
+	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
+	var->transp.msb_right = 0;
+	var->transp.offset = var->transp.length = 0;
+	var->xoffset = var->yoffset = 0;
+
+ 
+	if (info->fix.smem_len) {
+		unsigned int smem_len = (var->xres_virtual * var->yres_virtual
+					 * ((var->bits_per_pixel + 7) / 8));
+		if (smem_len > info->fix.smem_len)
+			return -EINVAL;
+	}
+
+	/* Saturate vertical and horizontal timings at maximum values */
+	var->vsync_len = min_t(u32, var->vsync_len,0x3fU + 1);
+	var->upper_margin = min_t(u32, var->upper_margin, 0xffU);
+	var->lower_margin = min_t(u32, var->lower_margin, 0xffU);
+	var->right_margin = min_t(u32, var->right_margin, 0x7ffU + 1);
+	var->hsync_len = min_t(u32, var->hsync_len, 0x3fU + 1);
+	var->left_margin = min_t(u32, var->left_margin, 0xffU + 1);
+
+	/* Some parameters can't be zero */
+	var->vsync_len = max_t(u32, var->vsync_len, 1);
+	var->right_margin = max_t(u32, var->right_margin, 1);
+	var->hsync_len = max_t(u32, var->hsync_len, 1);
+	var->left_margin = max_t(u32, var->left_margin, 1);
+
+ 
+	switch (var->bits_per_pixel) {
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		var->red.offset = var->green.offset = var->blue.offset = 0;
+		var->red.length = var->green.length = var->blue.length
+		    = var->bits_per_pixel;
+		break;
+	case 15:
+	case 16:
+		if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_RGB) {
+			/* RGB:565 mode */
+			var->red.offset = 11;
+			var->blue.offset = 0;
+			var->green.length = 6;
+		} else if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_RGB555) {
+			var->red.offset = 10;
+			var->blue.offset = 0;
+			var->green.length = 5;
+		} else {
+			/* BGR:555 mode */
+			var->red.offset = 0;
+			var->blue.offset = 10;
+			var->green.length = 5;
+		}
+		var->green.offset = 5;
+		var->red.length = var->blue.length = 5;
+		break;
+	case 32:
+		var->transp.offset = 24;
+		var->transp.length = 8;
+		/* fall through */
+	case 24:
+		if (sinfo->lcd_wiring_mode == ANYKA_LCDC_WIRING_RGB) {
+			/* RGB:888 mode */
+			var->red.offset = 16;
+			var->blue.offset = 0;
+		} else {
+			/* BGR:888 mode */
+			var->red.offset = 0;
+			var->blue.offset = 16;
+		}
+		var->green.offset = 8;
+		var->red.length = var->green.length = var->blue.length = 8;
+		break;
+	default:
+		dev_err(dev, "color depth %d not supported\n",
+			var->bits_per_pixel);
+		return -EINVAL;
+	}
+
+	#if 0
+	printk("check_var()/var->red.offset=%d,var->blue.offset=%d,var->green.offset=%d,var->red.length=%d,var->blue.length=%d,var->green.length=%d\n",\
+	     var->red.offset, var->blue.offset, var->green.offset,\
+	     var->red.length, var->blue.length, var->green.length);
+	#endif
+	
+	return 0;
+}
+
+/*
+ * LCD reset sequence
+ */
+static void anyka_lcdfb_reset(struct anyka_lcdfb_info *sinfo)
+{
+	might_sleep();
+
+	baselcd_reset_controller();	//controler reset
+
+	baselcd_reset_panel();	//panel reset
+}
+
+/**
+ *      anyka_lcdfb_set_par - Alters the hardware state.
+ *      @info: frame buffer structure that represents a single frame buffer
+ *
+ *	Using the fb_var_screeninfo in fb_info we set the resolution
+ *	of the this particular framebuffer. This function alters the
+ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
+ *	not alter var in fb_info since we are using that data. This
+ *	means we depend on the data in var inside fb_info to be
+ *	supported by the hardware.  anyka_lcdfb_check_var is always called
+ *	before anyka_lcdfb_set_par to ensure this.  Again if you can't
+ *	change the resolution you don't need this function.
+ *
+ */
+static int anyka_lcdfb_set_par(struct fb_info *info)
+{
+	struct anyka_lcdfb_info *sinfo = info->par;
+	unsigned long value;
+	unsigned long clk_value_hz;
+	unsigned long bits_per_line;
+	unsigned long pix_factor = 1;
+	u32 asic_freq;
+	LCD_IF_MODE if_mode = LCD_IF_RGB;
+
+ 	asic_freq = (unsigned long)clk_get_rate(clk_get(NULL,"asic_clk"));
+ 
+	might_sleep();
+
+	baselcd_reset_controller();
+
+
+
+	//dev_dbg(info->device, "%s:\n", __func__);
+	printk("%s:\n", __func__);
+	//dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
+	printk("  * resolution: %ux%u (%ux%u virtual)\n",
+	       info->var.xres, info->var.yres,
+	       info->var.xres_virtual, info->var.yres_virtual);
+
+	anyka_lcdfb_stop_nowait(sinfo);
+
+	if (info->var.bits_per_pixel == 1)
+		info->fix.visual = FB_VISUAL_MONO01;
+	else if (info->var.bits_per_pixel <= 8)
+		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+	else
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
+
+	bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
+	info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
+
+	/* Re-initialize the DMA engine... */
+	dev_dbg(info->device, "  * update DMA engine\n");
+	anyka_lcdfb_update_dma(info, &info->var);
+
+	/* ...set frame size and burst length = 8 words (?) */
+	value =
+	    (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
+
+	/* Now, the LCDC core... */
+
+	/* Set pixel clock */
+
+	//clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
+	//clk_value_hz = ak880x_asicfreq_get();
+	clk_value_hz = (unsigned long)clk_get_rate(clk_get(NULL,"asic_clk"));
+ 
+	value = DIV_ROUND_UP(clk_value_hz / 1000, (info->var.pixclock) / 1000);
+
+	if (value < pix_factor) {
+		dev_notice(info->device, "Bypassing pixel clock divider\n");		
+	} else {
+
+		lcd_rgb_set_pclk(asic_freq /*124 MHZ */ ,
+				 info->var.pixclock /*30 MHZ */ );
+	}
+
+
+	lcd_rgb_set_pclk(asic_freq, info->var.pixclock);
+
+
+	//printk("lcd_fb_set_timing()\n");
+	lcd_fb_set_timing(sinfo, asic_freq);
+
+
+	lcd_rgb_set_interface(if_mode);
+
+	lcd_rgb_start_refresh();
+
+	baselcd_set_panel_backlight(1);
+
+
+	//dev_dbg(info->device, "  * DONE\n");
+
+	return 0;
+}
+
+static inline unsigned int chan_to_field(unsigned int chan,
+					 const struct fb_bitfield *bf)
+{
+	chan &= 0xffff;
+	chan >>= 16 - bf->length;
+	return chan << bf->offset;
+}
+
+/**
+ *  	anyka_lcdfb_setcolreg - Optional function. Sets a color register.
+ *      @regno: Which register in the CLUT we are programming
+ *      @red: The red value which can be up to 16 bits wide
+ *	@green: The green value which can be up to 16 bits wide
+ *	@blue:  The blue value which can be up to 16 bits wide.
+ *	@transp: If supported the alpha value which can be up to 16 bits wide.
+ *      @info: frame buffer info structure
+ *
+ *  	Set a single color register. The values supplied have a 16 bit
+ *  	magnitude which needs to be scaled in this function for the hardware.
+ *	Things to take into consideration are how many color registers, if
+ *	any, are supported with the current color visual. With truecolor mode
+ *	no color palettes are supported. Here a psuedo palette is created
+ *	which we store the value in pseudo_palette in struct fb_info. For
+ *	pseudocolor mode we have a limited color palette. To deal with this
+ *	we can program what color is displayed for a particular pixel value.
+ *	DirectColor is similar in that we can program each color field. If
+ *	we have a static colormap we don't need to implement this function.
+ *
+ *	Returns negative errno on error, or zero on success. In an
+ *	ideal world, this would have been the case, but as it turns
+ *	out, the other drivers return 1 on failure, so that's what
+ *	we're going to do.
+ */
+static int anyka_lcdfb_setcolreg(unsigned int regno, unsigned int red,
+				 unsigned int green, unsigned int blue,
+				 unsigned int transp, struct fb_info *info)
+{
+	return 0;
+}
+
+static int anyka_lcdfb_pan_display(struct fb_var_screeninfo *var,
+				   struct fb_info *info)
+{
+	dev_dbg(info->device, "%s\n", __func__);
+
+	anyka_lcdfb_update_dma(info, var);
+
+	return 0;
+}
+
+static struct fb_ops anyka_lcdfb_ops = {
+	.owner = THIS_MODULE,
+	.fb_check_var = anyka_lcdfb_check_var,
+	.fb_set_par = anyka_lcdfb_set_par,
+	.fb_setcolreg = anyka_lcdfb_setcolreg,
+	.fb_pan_display = anyka_lcdfb_pan_display,
+	.fb_fillrect = cfb_fillrect,
+	.fb_copyarea = cfb_copyarea,
+	.fb_imageblit = cfb_imageblit,
+};
+
+irqreturn_t anyka_lcdfb_interrupt(int irq, void *dev_id)
+{
+	struct anyka_lcdfb_info *sfb = dev_id;
+
+	if(lcd_controller_isrefreshok())
+		wake_up_interruptible(&wq);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * LCD controller task (to reset the LCD)
+ */
+static void anyka_lcdfb_task(struct work_struct *work)
+{
+	struct anyka_lcdfb_info *sinfo =
+	    container_of(work, struct anyka_lcdfb_info, task);
+
+	anyka_lcdfb_reset(sinfo);
+}
+
+static int __init anyka_lcdfb_init_fbinfo(struct anyka_lcdfb_info *sinfo)
+{
+	struct fb_info *info = sinfo->info;
+	int ret = 0;
+
+	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
+
+	dev_info(info->device,
+		 "%luKiB frame buffer at %08lx (mapped at %p)\n",
+		 (unsigned long)info->fix.smem_len / 1024,
+		 (unsigned long)info->fix.smem_start, info->screen_base);
+
+	/* Allocate colormap */
+	ret = fb_alloc_cmap(&info->cmap, 256, 0);
+	if (ret < 0)
+		dev_err(info->device, "Alloc color map failed\n");
+
+	return ret;
+}
+
+void anyka_lcdfb_start_clock(struct anyka_lcdfb_info *sinfo)
+{
+
+	//open power clock
+//#define AK88_POWER_CLOCK    (AK88_VA_SYS+0x000C)   //0xF000000C
+//bit[3], 0 = to enable display controller working clock
+//        1 = to disable display controller working clock
+
+	//open LCD controller clock
+	//AKCLR_BITS(1UL<<3, AK88_POWER_CLOCK);  //0x0800000C
+
+	lcd_controller_start_clock();
+
+	printk("anyka_lcdfb_start_clock()\n");
+}
+
+static void anyka_lcdfb_stop_clock(struct anyka_lcdfb_info *sinfo)
+{
+
+	lcd_controller_stop_clock();	
+
+	printk("anyka_lcdfb_stop_clock()\n");
+}
+
+static int __init anyka_lcdfb_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fb_info *info;
+	struct anyka_lcdfb_info *sinfo;
+	struct anyka_lcdfb_info *pdata_sinfo;
+	struct fb_videomode fbmode;
+	struct resource *regs = NULL;
+	struct resource *map = NULL;
+	int ret;
+	u32 asic_freq;
+ 
+  	asic_freq = (unsigned long)clk_get_rate(clk_get(NULL,"asic_clk"));
+ 
+	dev_dbg(dev, "%s BEGIN\n", __func__);
+
+	ret = -ENOMEM;
+
+	set_ahb_priority();
+
+	baselcd_controller_init(1);
+
+	info = framebuffer_alloc(sizeof(struct anyka_lcdfb_info), dev);
+
+	if (!info) {
+		dev_err(dev, "cannot allocate memory\n");
+		goto out;
+	}
+
+	sinfo = info->par;
+
+	if (dev->platform_data) {
+
+		pdata_sinfo = (struct anyka_lcdfb_info *)dev->platform_data;
+		sinfo->default_bpp = pdata_sinfo->default_bpp;
+
+		sinfo->default_monspecs = pdata_sinfo->default_monspecs;
+		sinfo->anyka_lcdfb_power_control =
+		    pdata_sinfo->anyka_lcdfb_power_control;
+		sinfo->guard_time = pdata_sinfo->guard_time;
+		sinfo->smem_len = pdata_sinfo->smem_len;
+		sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
+		sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
+
+		printk("anyka_lcdfb_probe()/lcd_panel is:%s\n",sinfo->default_monspecs->modedb->name);
+
+	} else {
+		dev_err(dev, "cannot get default configuration\n");
+		goto free_info;
+	}
+	sinfo->info = info;
+	sinfo->pdev = pdev;
+
+	strcpy(info->fix.id, sinfo->pdev->name);
+	info->flags = ANYKA_LCDFB_FBINFO_DEFAULT;
+	info->pseudo_palette = sinfo->pseudo_palette;
+	info->fbops = &anyka_lcdfb_ops;
+
+	memcpy(&info->monspecs, sinfo->default_monspecs,
+	       sizeof(info->monspecs));
+
+	info->fix = anyka_lcdfb_fix;
+
+
+	ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
+			   info->monspecs.modedb_len, info->monspecs.modedb,
+			   sinfo->default_bpp);
+	if (!ret) {
+		dev_err(dev, "no suitable video mode found\n");
+		goto stop_clk;
+	}
+	info->var.yres_virtual = info->var.yres * 2;
+	printk("%s: %ux%u, %ux%u\n", __func__, info->var.xres, info->var.yres,
+	       info->var.xres_virtual, info->var.yres_virtual);
+
+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!regs) {
+		dev_err(dev, "resources unusable\n");
+		ret = -ENXIO;
+		goto stop_clk;
+	}
+
+	sinfo->irq_base = platform_get_irq(pdev, 0);
+	if (sinfo->irq_base < 0) {
+		dev_err(dev, "unable to get irq\n");
+		ret = sinfo->irq_base;
+		goto stop_clk;
+	}
+
+	/* Initialize video memory */
+	map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (map) {
+		/* use a pre-allocated memory buffer */
+		info->fix.smem_start = map->start;
+		info->fix.smem_len = map->end - map->start + 1;
+		if (!request_mem_region(info->fix.smem_start,
+					info->fix.smem_len, pdev->name)) {
+			ret = -EBUSY;
+			goto stop_clk;
+		}
+
+		info->screen_base =
+		    ioremap(info->fix.smem_start, info->fix.smem_len);
+		if (!info->screen_base)
+			goto release_intmem;
+
+		/*
+		 * Don't clear the framebuffer -- someone may have set
+		 * up a splash image.
+		 */
+	} else {
+		/* alocate memory buffer */
+		ret = anyka_lcdfb_alloc_video_memory(sinfo);
+		if (ret < 0) {
+			dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
+			goto stop_clk;
+		}
+	}
+
+	/* LCDC registers */
+	info->fix.mmio_start = regs->start;
+	info->fix.mmio_len = regs->end - regs->start + 1;
+
+	if (!request_mem_region(info->fix.mmio_start,
+				info->fix.mmio_len, pdev->name)) {
+		ret = -EBUSY;
+		goto free_fb;
+	}
+
+	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);	//ioremap get vitual address.
+	if (!sinfo->mmio) {
+		dev_err(dev, "cannot map LCDC registers\n");
+		goto release_mem;
+	}
+
+	/* Initialize PWM for contrast or backlight ("off") */
+	init_contrast(sinfo);
+
+	/* interrupt */
+
+	init_waitqueue_head(&wq); 
+	
+	ret =
+	    request_irq(sinfo->irq_base, anyka_lcdfb_interrupt, 0, pdev->name,
+			info);
+	if (ret) {
+		dev_err(dev, "request_irq failed: %d\n", ret);
+		goto unmap_mmio;
+	}
+
+	/* Some operations on the LCDC might sleep and
+	 * require a preemptible task context */
+	INIT_WORK(&sinfo->task, anyka_lcdfb_task);
+
+	ret = anyka_lcdfb_init_fbinfo(sinfo);
+
+	if (ret < 0) {
+		dev_err(dev, "init fbinfo failed: %d\n", ret);
+		goto unregister_irqs;
+	}
+
+	/*
+	 * This makes sure that our colour bitfield
+	 * descriptors are correctly initialised.
+	 */
+	anyka_lcdfb_check_var(&info->var, info);
+
+	ret = fb_set_var(info, &info->var);
+	if (ret) {
+		dev_warn(dev, "unable to set display parameters\n");
+		printk("unable to set display parameters\n");
+		goto free_cmap;
+	}
+
+	dev_set_drvdata(dev, info);
+
+	/*
+	 * Tell the world that we're ready to go
+	 */
+	ret = register_framebuffer(info);
+	if (ret < 0) {
+		dev_err(dev, "failed to register framebuffer device: %d\n",
+			ret);
+		goto reset_drvdata;
+	}
+
+	/* add selected videomode to modelist */
+	fb_var_to_videomode(&fbmode, &info->var);
+	fb_add_videomode(&fbmode, &info->modelist);
+
+	/* Power up the LCDC screen */
+	if (sinfo->anyka_lcdfb_power_control)
+		sinfo->anyka_lcdfb_power_control(1);
+
+	dev_info(dev,
+		 "fb%d: Anyka LCDC at info->fix.mmio_start=0x%08lx (sinfo->mmio=mapped at %p), irq %lu\n",
+		 info->node, info->fix.mmio_start, sinfo->mmio,
+		 (unsigned long)sinfo->irq_base);
+
+	return 0;
+
+ reset_drvdata:
+	dev_set_drvdata(dev, NULL);
+ free_cmap:
+	fb_dealloc_cmap(&info->cmap);
+ unregister_irqs:
+	cancel_work_sync(&sinfo->task);
+	free_irq(sinfo->irq_base, info);
+ unmap_mmio:
+	exit_backlight(sinfo);
+	iounmap(sinfo->mmio);
+ release_mem:
+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+ free_fb:
+	if (map)
+		iounmap(info->screen_base);
+	else
+		anyka_lcdfb_free_video_memory(sinfo);
+
+ release_intmem:
+	if (map)
+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+ stop_clk:
+	anyka_lcdfb_stop_clock(sinfo);
+ free_info:
+	framebuffer_release(info);
+ out:
+	dev_dbg(dev, "%s FAILED\n", __func__);
+	return ret;
+}
+
+static int __exit anyka_lcdfb_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fb_info *info = dev_get_drvdata(dev);
+	struct anyka_lcdfb_info *sinfo;
+
+	if (!info || !info->par)
+		return 0;
+	sinfo = info->par;
+
+	cancel_work_sync(&sinfo->task);
+	exit_backlight(sinfo);
+	if (sinfo->anyka_lcdfb_power_control)
+		sinfo->anyka_lcdfb_power_control(0);
+	unregister_framebuffer(info);
+	anyka_lcdfb_stop_clock(sinfo);
+	clk_put(sinfo->lcdc_clk);
+	if (sinfo->bus_clk)
+		clk_put(sinfo->bus_clk);
+	fb_dealloc_cmap(&info->cmap);
+	free_irq(sinfo->irq_base, info);
+	iounmap(sinfo->mmio);
+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
+
+	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
+		iounmap(info->screen_base);
+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
+	} else {
+ 		anyka_lcdfb_free_video_memory(sinfo);
+	}
+
+	dev_set_drvdata(dev, NULL);
+	framebuffer_release(info);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int anyka_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	struct fb_info *info = platform_get_drvdata(pdev);
+ 	struct anyka_lcdfb_info *sinfo = info->par;
+
+	/*
+	 * We don't want to handle interrupts while the clock is
+	 * stopped. It may take forever.
+	 */
+
+	if (sinfo->anyka_lcdfb_power_control)
+		sinfo->anyka_lcdfb_power_control(0);
+
+	anyka_lcdfb_stop(sinfo);
+	anyka_lcdfb_stop_clock(sinfo);
+
+	return 0;
+}
+
+static int anyka_lcdfb_resume(struct platform_device *pdev)
+{
+	struct fb_info *info = platform_get_drvdata(pdev);
+	struct anyka_lcdfb_info *sinfo = info->par;
+
+	anyka_lcdfb_start_clock(sinfo);
+	anyka_lcdfb_start(sinfo);
+	if (sinfo->anyka_lcdfb_power_control)
+		sinfo->anyka_lcdfb_power_control(1);
+
+	return 0;
+}
+
+#else
+#define anyka_lcdfb_suspend	NULL
+#define anyka_lcdfb_resume	NULL
+#endif
+
+static struct platform_driver anyka_lcdfb_driver = {
+	.remove = __exit_p(anyka_lcdfb_remove),
+	.suspend = anyka_lcdfb_suspend,
+	.resume = anyka_lcdfb_resume,
+
+	.driver = {
+		   .name = "anyka_lcdfb",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init anyka_lcdfb_init(void)
+{
+	return platform_driver_probe(&anyka_lcdfb_driver, anyka_lcdfb_probe);
+}
+
+static void __exit anyka_lcdfb_exit(void)
+{
+	platform_driver_unregister(&anyka_lcdfb_driver);
+}
+
+module_init(anyka_lcdfb_init);
+module_exit(anyka_lcdfb_exit);
+
+MODULE_DESCRIPTION("AK88 LCD Controller framebuffer driver");
+MODULE_AUTHOR("Anyka");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/ak98fb.c b/drivers/video/ak98fb.c
new file mode 100755
index 00000000000..03560b1a4ca
--- /dev/null
+++ b/drivers/video/ak98fb.c
@@ -0,0 +1,2094 @@
+#define DEBUG
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/random.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <linux/console.h>
+#include <linux/anyka_cpufreq.h>
+#include <linux/cpufreq.h>
+
+#include <linux/fb.h>
+
+#include <mach/gpio.h>
+
+#include "ak98fb.h"
+#include <linux/akfb.h>
+
+#define MPU_PCLK (11*1000*1000)	/* 11M pclk for mpu panel */
+
+static struct aklcd_rgb_panel bsp_rgb_panel =
+#if defined CONFIG_LCD_PANEL_QD043003C0_40
+{"QD043003C0-40", PANEL_PROGRESS, RGB24BITS, SEQ_RGB, \
+ 1, 43-1, 480, 8, 10, 12-10, 272, 4, TV_UNIT_TH, 9*1000*1000,     \
+ POL_POSITIVE, POL_NEGATIVE, POL_NEGATIVE, POL_POSITIVE};
+#elif defined CONFIG_LCD_PANEL_AT043TN24
+/* only support DE mode */
+{"AT043TN24", PANEL_PROGRESS, RGB24BITS, SEQ_RGB, \
+ 45, 0, 480, 0, 8, 0, 272, 0, TV_UNIT_TH, 9*1000*1000,     \
+ POL_POSITIVE, POL_NEGATIVE, POL_NEGATIVE, POL_POSITIVE};
+#elif defined CONFIG_LCD_PANEL_A050VW01_V5
+/* only support DE mode */
+{"A050VW01-V5", PANEL_PROGRESS, RGB24BITS, SEQ_RGB, \
+ 128, 0, 800, 0, 45, 0, 480, 0, TV_UNIT_TH, 30*1000*1000,     \
+ POL_POSITIVE, POL_NEGATIVE, POL_NEGATIVE, POL_POSITIVE};
+#elif defined CONFIG_LCD_PANEL_LW700AT9009
+{"LW700AT9009", PANEL_PROGRESS, RGB24BITS, SEQ_RGB, \
+ 128, 216-128, 800, 1056-216-800, 2, 35-2, 480, 525-35-480, TV_UNIT_TH, 33260*1000, \
+ POL_POSITIVE, POL_NEGATIVE, POL_NEGATIVE, POL_POSITIVE};
+#elif defined CONFIG_LCD_PANEL_AT070TN92
+{"AT070TN92", PANEL_PROGRESS, RGB24BITS, SEQ_RGB, \
+ 1, 46-1, 800, 210, 1, 23-1, 480, 22, TV_UNIT_TH, 33300*1000, \
+ POL_POSITIVE, POL_NEGATIVE, POL_NEGATIVE, POL_POSITIVE};
+#else
+#error "Must specified a LCD panel"
+#endif
+
+
+struct reg {
+	void* addr;		/* virtual address of register */
+	const char *name;
+};
+
+static struct reg aklcd_reg_list[] = {
+	{AK98_CLKRST_CTRL1,     "clock & reset control register 1"},
+	{AK98_SRDPIN_CTRL1,     "shared pin control register 1"},
+	{AK98_SRDPIN_CTRL2,     "shared pin control register 2"},
+	{AK98_PUPD2,            "pullup/pulldown register 2"},
+	{AK98_PUPD3,            "pullup/pulldown register 3"},
+	{AK98_PUPD4,            "pullup/pulldown register 4"},
+
+	{AK98_AHB_PRIORITY1,    "AHB Priority register 1"},
+	{AK98_AHB_PRIORITY2,    "AHB Priority register 2"},
+
+	{AK98_LCD_CMD1,         "LCD command register 1"},
+	{AK98_LCD_RESET,        "LCD reset register"},
+	{AK98_RGBIF_CTRL1,      "LCD RGB interface control 1"},
+	{AK98_RGBIF_CTRL2,      "LCD RGB interface control 2"},
+	{AK98_RGB_VPAGE_SIZE,   "LCD virtual page size"},
+	{AK98_RGB_VPAGE_OFFSET, "LCD virtual page offset"},
+	{AK98_BG_COLOR,         "LCD background color"},
+	{AK98_RGBIF_CTRL3,      "LCD RGB interface control 3"},
+	{AK98_RGBIF_CTRL4,      "LCD RGB interface control 4"},
+	{AK98_RGBIF_CTRL5,      "LCD RGB interface control 5"},
+	{AK98_RGBIF_CTRL6,      "LCD RGB interface control 6"},
+	{AK98_RGBIF_CTRL7,      "LCD RGB interface control 7"},
+	{AK98_RGBIF_CTRL8,      "LCD RGB interface control 8"},
+	{AK98_RGBIF_CTRL9,      "LCD RGB interface control 9"},
+	{AK98_RGB_OFFSET,       "LCD RGB image offset"},
+	{AK98_RGB_SIZE,         "LCD RGB image size"},
+	{AK98_DISP_SIZE,        "LCD display size"},
+	{AK98_LCD_CMD2,         "LCD command register 2"},
+	{AK98_LCD_OPER,         "LCD operation register"},
+	{AK98_LCD_STATUS,       "LCD status register"},
+	{AK98_LCD_INT_ENAB,     "LCD interrupt enable register"},
+	{AK98_LCD_SOFT_CTRL,    "LCD software control register"},
+	{AK98_LCD_CLKCONF,      "LCD clock config register"},
+
+	{AK98_OV1_YADDR,        "LCD overlay 1 y address"},
+	{AK98_OV1_UADDR,        "LCD overlay 1 u address"},
+	{AK98_OV1_VADDR,        "LCD overlay 1 v address"},
+	{AK98_OV1_HORI_CONF,    "LCD overlay 1 horizontal config"},
+	{AK98_OV1_VERT_CONF,    "LCD overlay 1 vertical config"},
+	{AK98_OV1_SCALER,       "LCD overlay 1 scaler register"},
+	{AK98_OV1_DISP_CONF,    "LCD overlay 1 display config"},
+	{AK98_OV1_VPAGE_SIZE,   "LCD overlay 1 virtual page size"},
+	{AK98_OV1_VPAGE_OFFSET, "LCD overlay 1 virtual page offset"},
+
+	{AK98_OV2_YADDR,        "LCD overlay 2 y address"},
+	{AK98_OV2_UADDR,        "LCD overlay 2 u address"},
+	{AK98_OV2_VADDR,        "LCD overlay 2 v address"},
+	{AK98_OV2_HORI_CONF,    "LCD overlay 2 horizontal config"},
+	{AK98_OV2_VERT_CONF,    "LCD overlay 2 vertical config"},
+	{AK98_OV2_SCALER,       "LCD overlay 2 scaler register"},
+	{AK98_OV2_DISP_CONF,    "LCD overlay 2 display config"},
+	
+	{TVOUT_CHROMA_FREQ_REG,   "TVOUT_CHROMA_FREQ_REG"},
+	{TVOUT_CTRL_REG1,         "TVOUT_CTRL_REG1"},
+	{TVOUT_PARA_CONFIG_REG1,  "TVOUT_PARA_CONFIG_REG1"},
+	{TVOUT_PARA_CONFIG_REG2,  "TVOUT_PARA_CONFIG_REG2"},
+	{TVOUT_PARA_CONFIG_REG3,  "TVOUT_PARA_CONFIG_REG3"},
+	{TVOUT_PARA_CONFIG_REG4,  "TVOUT_PARA_CONFIG_REG4"},
+	{TVOUT_PARA_CONFIG_REG5,  "TVOUT_PARA_CONFIG_REG5"},
+	{TVOUT_PARA_CONFIG_REG6,  "TVOUT_PARA_CONFIG_REG6"},
+	{TVOUT_CTRL_REG2,         "TVOUT_CTRL_REG2"},
+};
+
+static void ak_dump_regs(struct reg *reg_list, int n, const struct device *dev)
+{
+	int i;
+
+	dev_dbg(dev, "dump registers\n");
+	for (i = 0; i < n; i++) {
+		dev_dbg(dev, "0x%p - 0x%08x - %s\n", reg_list[i].addr,
+			__raw_readl(reg_list[i].addr), reg_list[i].name);
+	}
+}
+
+/********************
+ * hardware setting
+ ********************/
+static inline void aklcd_reset(void)
+{
+	lcd_set_reg(1, AK98_CLKRST_CTRL1, 27, 27);
+	mdelay(1);
+	lcd_set_reg(0, AK98_CLKRST_CTRL1, 27, 27);
+}
+
+static inline void aklcd_enable(void)
+{
+	lcd_set_reg(0, AK98_CLKRST_CTRL1, 11, 11);
+	mdelay(1);
+	aklcd_reset();
+}
+
+static inline void aklcd_disable(void)
+{
+	lcd_set_reg(1, AK98_CLKRST_CTRL1, 11, 11);
+}
+
+static void aklcd_set_power(bool enable)
+{
+	#if 1
+	/* power control */
+	ak98_gpio_pullup(AK98_GPIO_102, AK98_PULLUP_ENABLE);
+	ak98_gpio_cfgpin(AK98_GPIO_102, AK98_GPIO_DIR_OUTPUT);
+	ak98_gpio_pullup(AK98_GPIO_103, AK98_PULLUP_ENABLE);
+	ak98_gpio_cfgpin(AK98_GPIO_103, AK98_GPIO_DIR_OUTPUT);
+	if (enable) {
+			ak98_gpio_setpin(AK98_GPIO_103, 0);
+			ak98_gpio_setpin(AK98_GPIO_102, 0);
+			mdelay(2);
+		ak98_gpio_setpin(AK98_GPIO_102, 1);
+			mdelay(40);
+		ak98_gpio_setpin(AK98_GPIO_103, 1);
+		/* reset panel
+		lcd_set_reg(0, AK98_LCD_RESET, 1, 1);
+		mdelay(1);
+		lcd_set_reg(1, AK98_LCD_RESET, 1, 1);*/
+	} else {
+			ak98_gpio_setpin(AK98_GPIO_103, 0);
+		ak98_gpio_setpin(AK98_GPIO_102, 0);
+	}
+	#endif
+}
+
+static void aklcd_start_tvout_clk(void)
+{
+	/* enable DAC */
+	lcd_set_reg(0, AK98_MULTIFUNC_CTRL_REG1, 21, 21);
+	/* enable 27MCLK */
+	lcd_set_reg(1, AK98_MULTIFUNC_CTRL_REG1, 28, 28);
+}
+
+static void aklcd_stop_tvout_clk(void)
+{
+	/* disable DAC */
+	lcd_set_reg(1, AK98_MULTIFUNC_CTRL_REG1, 21, 21);
+	/* disable 27MHz clk */
+	lcd_set_reg(0, AK98_MULTIFUNC_CTRL_REG1, 28, 28);
+}
+
+static void aklcd_start_pclk(int typical_pclk,
+			     const struct device *dev)
+{
+	unsigned int pll_clk;
+	unsigned int main_clk;
+	unsigned int pclk;	/* panel clock */
+	int pclk_div;
+
+	/* Panel clock (pclk):
+	   pclk = main_clk / ((pclk_div+1)*2);   (main_clk is the CLK168M in  datasheet)
+	*/
+	pll_clk = (lcd_get_reg(AK98_CLK_DIV1, 5, 0) * 4 + 180) * 1000 * 1000;
+	dev_dbg(dev, "pll_clk = %i\n", pll_clk);
+	main_clk = pll_clk / (lcd_get_reg(AK98_CLK_DIV1, 20, 17) + 1);
+	dev_dbg(dev, "main_clk = %i\n", main_clk);
+
+	dev_dbg(dev, "typical_pclk = %i\n", typical_pclk);
+	/* find the first pclk which closest match the typical panel clock */
+	for (pclk_div = ((1<<7)-1); pclk_div >= 0; pclk_div--) {
+		pclk = main_clk / ((pclk_div+1)*2);
+		if (pclk >= typical_pclk) break;
+	}
+	/* if the pclk override the typical panel clock 10%, reduce pclk */
+	if ((pclk - typical_pclk) > typical_pclk/10)
+		pclk_div++;
+
+	dev_dbg(dev, "pclk = %i (pclk_div = %i)\n", main_clk / ((pclk_div+1)*2), pclk_div);
+
+#if 1
+	__raw_writel((1 << 8 | (pclk_div << 1) | 1), AK98_LCD_CLKCONF);
+#else
+	lcd_set_reg(pclk_div, AK98_LCD_CLKCONF, 7, 1);
+	lcd_set_reg(1, AK98_LCD_CLKCONF, 8, 8);
+	lcd_set_reg(1, AK98_LCD_CLKCONF, 0, 0);
+	dev_dbg(dev, "AK98_LCD_CLKCONF: 0x%08x\n", __raw_readl(AK98_LCD_CLKCONF));
+#endif
+}
+
+static void aklcd_stop_pclk(void)
+{
+	__raw_writel(1, AK98_LCD_CLKCONF);
+}
+
+static void aklcd_start_refresh(enum aklcd_if if_type,
+				int pclk_freq,
+				const struct device *dev)
+{
+	/* start refresh */
+	switch(if_type) {
+	case DISP_IF_MPU:
+		aklcd_start_pclk (MPU_PCLK, dev);
+		lcd_set_reg(1, AK98_LCD_OPER, 3, 3);
+		break;
+	case DISP_IF_RGB:
+		aklcd_start_pclk (pclk_freq, dev);
+		lcd_set_reg(1, AK98_LCD_OPER, 2, 2);
+		break;
+	case DISP_IF_TVOUT:
+		aklcd_start_tvout_clk ();
+		lcd_set_reg(1, AK98_LCD_OPER, 1, 1);
+		break;
+	}
+}
+
+static void aklcd_stop_refresh(enum aklcd_if if_type,
+			       const struct device *dev)
+{
+	switch(if_type) {
+	case DISP_IF_MPU:
+	case DISP_IF_RGB:
+		/* stop sync signal */
+		lcd_set_reg(1, AK98_LCD_OPER, 0, 0);
+		/* stop pclk signal */
+		aklcd_stop_pclk();
+		break;
+	case DISP_IF_TVOUT:
+		lcd_set_reg(1, AK98_LCD_OPER, 0, 0);
+		aklcd_stop_tvout_clk ();
+		break;
+	}
+}
+
+static void aklcd_set_rgb_panel(const struct aklcd_rgb_panel *panel,
+				const struct device *dev)
+{
+	int h_total_period;
+	int v_total_period;
+
+	dev_info(dev, "set rgb panel: %s\n", panel->name);
+
+	/* set display interface */
+	lcd_set_reg(DISP_IF_RGB, AK98_LCD_CMD1, 6, 5);
+
+	/* RGB panel type */
+	lcd_set_reg(panel->panel_mode, AK98_RGBIF_CTRL1, 20, 20);
+	lcd_set_reg(panel->data_width, AK98_RGBIF_CTRL1, 22, 21);
+	lcd_set_reg(panel->data_seq, AK98_LCD_CMD1, 12, 12);
+
+#if 0
+	__raw_writel(0, AK98_RGBIF_CTRL3);
+	__raw_writel(0, AK98_RGBIF_CTRL4);
+	__raw_writel(0, AK98_RGBIF_CTRL5);
+	__raw_writel(0, AK98_RGBIF_CTRL6);
+	__raw_writel(0, AK98_RGBIF_CTRL7);
+	__raw_writel(0, AK98_RGBIF_CTRL8);
+	__raw_writel(0, AK98_RGBIF_CTRL9);
+#endif
+
+	/* Horizontal Timing */
+	lcd_set_reg(panel->thpw, AK98_RGBIF_CTRL3, 23, 12);
+	lcd_set_reg(panel->thbp, AK98_RGBIF_CTRL4, 23, 12);
+	lcd_set_reg(panel->thd,  AK98_RGBIF_CTRL4, 11, 0);
+	lcd_set_reg(panel->thfp, AK98_RGBIF_CTRL5, 24, 13);
+	h_total_period = panel->thpw + panel->thbp + panel->thd + panel->thfp;
+	lcd_set_reg(h_total_period, AK98_RGBIF_CTRL5, 12, 0);
+
+	/* Vertical Timing */
+	lcd_set_reg(panel->tvpw, AK98_RGBIF_CTRL3, 11, 0);
+	lcd_set_reg(panel->tvbp, AK98_RGBIF_CTRL6, 11, 0);
+	lcd_set_reg(panel->tvd,  AK98_RGBIF_CTRL8, 26, 15);
+	lcd_set_reg(panel->tvfp, AK98_RGBIF_CTRL7, 23, 12);
+	v_total_period = panel->tvpw + panel->tvbp + panel->tvd + panel->tvfp;
+	lcd_set_reg(v_total_period, AK98_RGBIF_CTRL9, 12, 0);
+	lcd_set_reg(panel->tv_unit, AK98_RGBIF_CTRL8, 0, 0);
+
+	dev_dbg(dev, "H: %i, %i, %i, %i, %i  V:%i, %i, %i, %i, %i\n",
+		panel->thpw, panel->thbp, panel->thd, panel->thfp, h_total_period,
+		panel->tvpw, panel->tvbp, panel->tvd, panel->tvfp, v_total_period);
+
+
+	/* Set signals' polarity */
+	if (panel->pclk_pol == POL_POSITIVE)
+		lcd_set_reg(1, AK98_LCD_CMD1, 4, 4);
+	else
+		lcd_set_reg(0, AK98_LCD_CMD1, 4, 4);
+	if (panel->hsync_pol == POL_POSITIVE)
+		lcd_set_reg(0, AK98_RGBIF_CTRL1, 2, 2);
+	else
+		lcd_set_reg(1, AK98_RGBIF_CTRL1, 2, 2);
+	if (panel->vsync_pol == POL_POSITIVE)
+		lcd_set_reg(0, AK98_RGBIF_CTRL1, 1, 1);
+	else
+		lcd_set_reg(1, AK98_RGBIF_CTRL1, 1, 1);
+	if (panel->vogate_pol == POL_POSITIVE)
+		lcd_set_reg(0, AK98_RGBIF_CTRL1, 0, 0);
+	else
+		lcd_set_reg(1, AK98_RGBIF_CTRL1, 0, 0);
+
+	/* Configure pins: set shared-pins, and disable pullup function(for energy saving) */
+	//ak98_gpio_pullup(AK98_LCD_PINS, AK98_PULLUP_DISABLE);
+
+	if (panel->data_width == RGB24BITS) {
+		lcd_set_reg(1, AK98_SRDPIN_CTRL1, 26, 26); /* 8 */
+		ak98_gpio_pullup(AK98_GPIO_61, AK98_PULLUP_DISABLE);
+		lcd_set_reg(1, AK98_SRDPIN_CTRL1, 25, 25); /* 9-15 */
+		ak98_gpio_pullup(AK98_GPIO_62, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_63, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_64, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_65, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_66, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_67, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_68, AK98_PULLUP_DISABLE);
+
+		lcd_set_reg(1, AK98_SRDPIN_CTRL1, 27, 27); /* 16-17 */
+		ak98_gpio_pullup(AK98_GPIO_69, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_70, AK98_PULLUP_DISABLE);
+
+		lcd_set_reg(1, AK98_SRDPIN_CTRL2, 8, 8); /* 18-23 */
+		ak98_gpio_pullup(AK98_GPIO_84, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_85, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_86, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_87, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_88, AK98_PULLUP_DISABLE);
+		ak98_gpio_pullup(AK98_GPIO_89, AK98_PULLUP_DISABLE);
+	}
+}
+
+#if 0
+static void aklcd_set_mpu_panel(const struct aklcd_mpu_panel *panel)
+{
+}
+#endif
+
+static void aklcd_get_tvout_dst_params(struct aklcd_overlay_channel *ov1_channel, enum ak_tvout_mode tvmode)
+{
+    unsigned int max_width, max_height, disp_left, disp_top;
+    unsigned int dst_width, dst_height, dst_left, dst_top;
+    unsigned int src_width, src_height;
+    
+	if (PAL == tvmode) {
+		max_width  = TV_PAL_DISP_WIDTH;
+		max_height = TV_PAL_DISP_HEIGHT*2;
+		disp_left = TV_PAL_DISP_LEFT;
+		disp_top = TV_PAL_DISP_TOP;
+	} else {
+		max_width  = TV_NTSC_DISP_WIDTH;
+		max_height = TV_NTSC_DISP_HEIGHT*2;
+		disp_left = TV_NTSC_DISP_LEFT;
+		disp_top = TV_NTSC_DISP_TOP;
+	}
+    src_width  = ov1_channel->src_width;
+    src_height = ov1_channel->src_height;
+
+	dst_width = max_width;
+	dst_height = (dst_width * src_height) / src_width;
+
+	if (dst_height > max_height) {
+		dst_height = max_height;
+		dst_width = (dst_height * src_width) / src_height;
+	}
+
+	if (dst_width == max_width) {
+		dst_left = disp_left;
+		dst_top = disp_top*2 + (max_height - dst_height)/2;
+	} else {		/* dst_height == max_height */
+		dst_top = disp_top*2;
+		dst_left = disp_left + (max_width - dst_width)/2;
+	}
+
+	dst_height /= 2;
+	dst_top /= 2;
+	
+	//2 multipler
+	dst_width &= ~1;
+	dst_height &= ~1;
+	dst_left &= ~1;
+	dst_top &= ~1;
+	
+	ov1_channel->disp_left = dst_left;
+	ov1_channel->disp_top  = dst_top;
+	ov1_channel->dst_width = dst_width;
+	ov1_channel->dst_height = dst_height;
+	ov1_channel->use_vpage = false;
+}
+
+static void aklcd_set_tvout_panel(enum ak_tvout_mode tvout_mode)
+{
+	//set output interface
+	lcd_set_reg(DISP_IF_TVOUT, AK98_LCD_CMD1, 6, 5);
+
+	switch(tvout_mode)
+	{
+    	case PAL:
+    	    //init the tvout registers in PAL mode.
+    		lcd_set_reg(89, TVOUT_PARA_CONFIG_REG6, 7, 0);		
+    		lcd_set_reg(625, TVOUT_PARA_CONFIG_REG3, 27, 18);
+    		lcd_set_reg(0x2A098ACB, TVOUT_CHROMA_FREQ_REG, 31, 0);	
+    		lcd_set_reg(138, TVOUT_PARA_CONFIG_REG1, 7, 0);//????	
+    		lcd_set_reg(1440, TVOUT_PARA_CONFIG_REG5, 10, 0);
+    		lcd_set_reg(24, TVOUT_PARA_CONFIG_REG5, 31, 24);
+    		lcd_set_reg(21, TVOUT_PARA_CONFIG_REG5, 23, 16); //????
+    		lcd_set_reg(282, TVOUT_PARA_CONFIG_REG2, 27, 18);
+    		lcd_set_reg(280, TVOUT_PARA_CONFIG_REG2, 17, 8);
+    		lcd_set_reg(44, TVOUT_PARA_CONFIG_REG2, 7, 0);
+    		lcd_set_reg(44, TVOUT_PARA_CONFIG_REG3, 7, 0);
+    		lcd_set_reg(137, TVOUT_PARA_CONFIG_REG4, 15, 8);
+    		lcd_set_reg(137, TVOUT_PARA_CONFIG_REG4, 7, 0);
+
+    		lcd_set_reg(0, TVOUT_CTRL_REG2, 8, 8); 
+    		break;
+
+    	case NTSC:
+    	default:
+    	    //restore tvout  registers with default values 
+    	    //when from PAL to NTSC
+            lcd_set_reg(0x21f07c1f, TVOUT_CHROMA_FREQ_REG, 31, 0);
+    	    lcd_set_reg(0x7e, TVOUT_PARA_CONFIG_REG1, 23, 16);
+    	    lcd_set_reg(0x4476, TVOUT_PARA_CONFIG_REG1, 14, 0);
+    	    lcd_set_reg(0x468f03b, TVOUT_PARA_CONFIG_REG2, 27, 0);   
+    	    lcd_set_reg(0x8372000, TVOUT_PARA_CONFIG_REG3, 27, 0);
+    	    lcd_set_reg(0x16008989, TVOUT_PARA_CONFIG_REG4, 28, 0);
+    	    lcd_set_reg(0x2016, TVOUT_PARA_CONFIG_REG5, 31, 16);
+    	    lcd_set_reg(0x5a0, TVOUT_PARA_CONFIG_REG5, 10, 0);
+    	    lcd_set_reg(0xc8a34802, TVOUT_PARA_CONFIG_REG6, 31, 0);
+
+    	    //Using the same interpolation scale mothed.
+    	    lcd_set_reg(1, TVOUT_CTRL_REG1, 28, 28);
+    	    //for NTSC mode, need to set soft_rst 
+    		lcd_set_reg(0, TVOUT_CTRL_REG2, 8, 8);  		
+    		break;
+	}
+}
+
+
+static unsigned long aklcd_get_irq_status(void)
+{
+	return lcd_get_reg(AK98_LCD_STATUS, 31, 0);
+}
+
+static void aklcd_set_rgb_irq(void)
+{
+	lcd_set_reg(1, AK98_LCD_INT_ENAB, 0, 0);
+}
+
+static void aklcd_set_alert_line(unsigned i)
+{
+#if 1
+	__raw_writel((1 << 11) | i, AK98_LCD_SOFT_CTRL);
+#else
+	lcd_set_reg(i, AK98_LCD_SOFT_CTRL, 10, 0);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 11, 11);
+#endif
+}
+
+/* enable alert irq or not */
+static void aklcd_enable_alert(bool enable)
+{
+	if (enable) {
+		/* read AK98_LCD_STATUS register to clean former alert_valid status bit,
+		   otherwise alert_valid interrupt will occur immediately */
+		aklcd_get_irq_status();
+		lcd_set_reg(1, AK98_LCD_INT_ENAB, 17, 17);
+	} else {
+		lcd_set_reg(0, AK98_LCD_INT_ENAB, 17, 17);
+	}
+}
+
+static void aklcd_set_screen(struct aklcd_screen *screen)
+{
+	/* set screen geometry */
+	lcd_set_reg(screen->width, AK98_DISP_SIZE, 21, 11);
+	lcd_set_reg(screen->height, AK98_DISP_SIZE, 10, 0);
+
+	/* set background color */
+	lcd_set_reg(screen->bg_color, AK98_BG_COLOR, 23, 0);
+
+	/* alert setting, for set_par (act as vsync) */
+	aklcd_set_alert_line(screen->height);
+}
+
+static void aklcd_set_rgb_channel(struct aklcd_rgb_channel *rgb_channel)
+{
+	/* source: */
+	lcd_set_reg(rgb_channel->format, AK98_LCD_CMD1, 14, 13);
+	lcd_set_reg(rgb_channel->data_addr, AK98_RGBIF_CTRL2, 28, 0);
+	if (rgb_channel->use_vpage) {
+		lcd_set_reg(1, AK98_RGBIF_CTRL2, 29, 29);
+		lcd_set_reg(rgb_channel->vpage_width, AK98_RGB_VPAGE_SIZE, 31, 16);
+		lcd_set_reg(rgb_channel->vpage_height, AK98_RGB_VPAGE_SIZE, 15, 0);
+		lcd_set_reg(rgb_channel->virt_left, AK98_RGB_VPAGE_OFFSET, 31, 16);
+		lcd_set_reg(rgb_channel->virt_top, AK98_RGB_VPAGE_OFFSET, 15, 0);
+	} else {
+		lcd_set_reg(0, AK98_RGBIF_CTRL2, 29, 29);
+	}
+
+	/* destination: (dst size is screen size, and already set in aklcd_set_screen() ) */
+	lcd_set_reg(rgb_channel->disp_left, AK98_RGB_OFFSET, 21, 11);
+	lcd_set_reg(rgb_channel->disp_top, AK98_RGB_OFFSET, 10, 0);
+	lcd_set_reg(rgb_channel->width,  AK98_RGB_SIZE, 21, 11);
+	lcd_set_reg(rgb_channel->height, AK98_RGB_SIZE, 10, 0);
+}
+
+static void aklcd_set_ov1_channel(struct aklcd_overlay_channel *ov1_channel)
+{
+	unsigned int scaler;
+
+	/* src: */
+	lcd_set_reg(ov1_channel->src_range, AK98_OV1_DISP_CONF, 27, 27);
+	lcd_set_reg(ov1_channel->y_addr, AK98_OV1_YADDR, 28, 0);
+	lcd_set_reg(ov1_channel->u_addr, AK98_OV1_UADDR, 28, 0);
+	lcd_set_reg(ov1_channel->v_addr, AK98_OV1_VADDR, 28, 0);
+	lcd_set_reg(ov1_channel->src_width, AK98_OV1_HORI_CONF, 10, 0);
+	lcd_set_reg(ov1_channel->src_height, AK98_OV1_VERT_CONF, 10, 0);
+
+	/* virtual page */
+	if (ov1_channel->use_vpage) {
+		lcd_set_reg(1, AK98_OV1_DISP_CONF, 24, 24);
+		lcd_set_reg(ov1_channel->vpage_width, AK98_OV1_VPAGE_SIZE, 31, 16);
+		lcd_set_reg(ov1_channel->vpage_height, AK98_OV1_VPAGE_SIZE, 15, 0);
+		lcd_set_reg(ov1_channel->virt_left, AK98_OV1_VPAGE_OFFSET, 31, 16);
+		lcd_set_reg(ov1_channel->virt_top, AK98_OV1_VPAGE_OFFSET, 15, 0);
+	} else {
+		lcd_set_reg(0, AK98_OV1_DISP_CONF, 24, 24);
+	}
+
+	/* dst: */
+	lcd_set_reg(ov1_channel->disp_left, AK98_OV1_DISP_CONF, 21, 11);
+	lcd_set_reg(ov1_channel->disp_top, AK98_OV1_DISP_CONF, 10, 0);
+	lcd_set_reg(ov1_channel->dst_width, AK98_OV1_HORI_CONF, 21, 11);
+	lcd_set_reg(ov1_channel->dst_height, AK98_OV1_VERT_CONF, 21, 11);
+	if (ov1_channel->dst_width != ov1_channel->src_width) {
+		lcd_set_reg(1, AK98_OV1_DISP_CONF, 23, 23);
+		scaler = AKLCD_HSCALER(ov1_channel->dst_width);
+		if (scaler == 0) scaler = 0xfff;
+		lcd_set_reg(scaler, AK98_OV1_SCALER, 11, 0);
+	} else {
+		lcd_set_reg(0, AK98_OV1_DISP_CONF, 23, 23);
+	}
+	if (ov1_channel->dst_height != ov1_channel->src_height) {
+		lcd_set_reg(1, AK98_OV1_DISP_CONF, 22, 22);
+		scaler = AKLCD_VSCALER(ov1_channel->dst_height);
+		if (scaler == 0) scaler = 0xfff;
+		lcd_set_reg(scaler, AK98_OV1_SCALER, 23, 12);
+		/* for reduce DMA translation */
+		if (ov1_channel->dst_height < ov1_channel->src_height) {
+			lcd_set_reg(1, AK98_OV1_DISP_CONF, 25, 25);
+		} else {
+			lcd_set_reg(0, AK98_OV1_DISP_CONF, 25, 25);
+		}
+	} else {
+		lcd_set_reg(0, AK98_OV1_DISP_CONF, 22, 22);
+	}
+}
+
+static void aklcd_set_ov2_channel(struct aklcd_overlay_channel *ov2_channel)
+{
+	unsigned int scaler;
+	unsigned int ov1_left, ov1_right, ov1_top, ov1_bottom;
+
+	/* src: */
+	lcd_set_reg(ov2_channel->y_addr, AK98_OV2_YADDR, 28, 0);
+	lcd_set_reg(ov2_channel->u_addr, AK98_OV2_UADDR, 28, 0);
+	lcd_set_reg(ov2_channel->v_addr, AK98_OV2_VADDR, 28, 0);
+	lcd_set_reg(ov2_channel->src_width, AK98_OV2_HORI_CONF, 10, 0);
+	lcd_set_reg(ov2_channel->src_height, AK98_OV2_VERT_CONF, 10, 0);
+
+	/* dst: */
+	lcd_set_reg(ov2_channel->disp_left, AK98_OV2_DISP_CONF, 21, 11);
+	lcd_set_reg(ov2_channel->disp_top, AK98_OV2_DISP_CONF, 10, 0);
+	lcd_set_reg(ov2_channel->dst_width, AK98_OV2_HORI_CONF, 21, 11);
+	lcd_set_reg(ov2_channel->dst_height, AK98_OV2_VERT_CONF, 21, 11);
+	if (ov2_channel->dst_width != ov2_channel->src_width) {
+		lcd_set_reg(1, AK98_OV2_DISP_CONF, 23, 23);
+		scaler = AKLCD_HSCALER(ov2_channel->dst_width);
+		if (scaler == 0) scaler = 0xfff;
+		lcd_set_reg(scaler, AK98_OV2_SCALER, 11, 0);
+	} else {
+		lcd_set_reg(0, AK98_OV2_DISP_CONF, 23, 23);
+	}
+	if (ov2_channel->dst_height != ov2_channel->src_height) {
+		lcd_set_reg(1, AK98_OV2_DISP_CONF, 22, 22);
+		scaler = AKLCD_VSCALER(ov2_channel->dst_height);
+		if (scaler == 0) scaler = 0xfff;
+		lcd_set_reg(scaler, AK98_OV2_SCALER, 23, 12);
+		/* for reduce DMA translation */
+		if (ov2_channel->dst_height < ov2_channel->src_height) {
+			lcd_set_reg(1, AK98_OV2_DISP_CONF, 25, 25);
+		} else {
+			lcd_set_reg(0, AK98_OV2_DISP_CONF, 25, 25);
+		}
+	} else {
+		lcd_set_reg(0, AK98_OV2_DISP_CONF, 22, 22);
+	}
+
+	/* 0: ov2 over ov1; 1: ov2 ex ov1; */
+	if (lcd_get_reg(AK98_LCD_CMD1, 2, 2)) {
+		ov1_left = lcd_get_reg(AK98_OV1_DISP_CONF, 21, 11);
+		ov1_top = lcd_get_reg(AK98_OV1_DISP_CONF, 10, 0);
+		ov1_right = ov1_left + lcd_get_reg(AK98_OV1_HORI_CONF, 21, 11);
+		ov1_bottom = ov1_top + lcd_get_reg(AK98_OV1_VERT_CONF, 21, 11);
+	} else {
+		ov1_left = ov1_top = ov1_right = ov1_bottom = 0;
+	}
+	if (ov2_channel->disp_left >= ov1_left && (ov2_channel->disp_left + ov2_channel->dst_width) <= ov1_right
+	    && ov2_channel->disp_top >= ov1_top && (ov2_channel->disp_top + ov2_channel->dst_height) <= ov1_bottom) {
+		lcd_set_reg(0, AK98_OV2_DISP_CONF, 24, 24);
+	} else if ((ov2_channel->disp_left + ov2_channel->dst_width) < ov1_left || ov2_channel->disp_left >= ov1_right
+		   || (ov2_channel->disp_top + ov2_channel->dst_height) < ov1_top || ov2_channel->disp_top >= ov1_bottom) {
+		lcd_set_reg(1, AK98_OV2_DISP_CONF, 24, 24);
+	} else {
+		return;
+	}
+
+	lcd_set_reg(ov2_channel->alpha, AK98_OV2_DISP_CONF, 29, 26);
+}
+
+static void aklcd_set_osd_channel(struct aklcd_osd_channel *osd_channel)
+{
+	/* src: */
+	lcd_set_reg(osd_channel->data_addr, AK98_OSD_ADDR, 28, 0);
+
+	/* Set color palette */
+	lcd_set_reg(osd_channel->palette[1], AK98_OSD_COLOR1, 31, 16);
+	lcd_set_reg(osd_channel->palette[2], AK98_OSD_COLOR1, 15, 0);
+	lcd_set_reg(osd_channel->palette[3], AK98_OSD_COLOR2, 31, 16);
+	lcd_set_reg(osd_channel->palette[4], AK98_OSD_COLOR2, 15, 0);
+	lcd_set_reg(osd_channel->palette[5], AK98_OSD_COLOR3, 31, 16);
+	lcd_set_reg(osd_channel->palette[6], AK98_OSD_COLOR3, 15, 0);
+	lcd_set_reg(osd_channel->palette[7], AK98_OSD_COLOR4, 31, 16);
+	lcd_set_reg(osd_channel->palette[8], AK98_OSD_COLOR4, 15, 0);
+	lcd_set_reg(osd_channel->palette[9], AK98_OSD_COLOR5, 31, 16);
+	lcd_set_reg(osd_channel->palette[10], AK98_OSD_COLOR5, 15, 0);
+	lcd_set_reg(osd_channel->palette[11], AK98_OSD_COLOR6, 31, 16);
+	lcd_set_reg(osd_channel->palette[12], AK98_OSD_COLOR6, 15, 0);
+	lcd_set_reg(osd_channel->palette[13], AK98_OSD_COLOR7, 31, 16);
+	lcd_set_reg(osd_channel->palette[14], AK98_OSD_COLOR7, 15, 0);
+	lcd_set_reg(osd_channel->palette[15], AK98_OSD_COLOR8, 15, 0);
+
+	/* dst: */
+	lcd_set_reg(osd_channel->disp_left, AK98_OSD_OFFSET, 21, 11);
+	lcd_set_reg(osd_channel->disp_top, AK98_OSD_OFFSET, 10, 0);
+	lcd_set_reg(osd_channel->width, AK98_OSD_SIZE_ALPHA, 10, 0);
+	lcd_set_reg(osd_channel->height, AK98_OSD_SIZE_ALPHA, 21, 11);
+
+	lcd_set_reg(osd_channel->alpha, AK98_OSD_SIZE_ALPHA, 25, 22);
+}
+
+static void aklcd_change_rgb_vpage_offset(unsigned xoffset, unsigned yoffset)
+{
+	lcd_set_reg(xoffset, AK98_RGB_VPAGE_OFFSET, 31, 16);
+	lcd_set_reg(yoffset, AK98_RGB_VPAGE_OFFSET, 15, 0);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_change_rgb_channel(struct aklcd_rgb_channel *rgb_channel)
+{
+	aklcd_set_rgb_channel(rgb_channel);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_change_ov1_channel(struct aklcd_overlay_channel *ov1_channel)
+{
+	aklcd_set_ov1_channel(ov1_channel);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_change_ov2_channel(struct aklcd_overlay_channel *ov2_channel)
+{
+	aklcd_set_ov2_channel(ov2_channel);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_change_osd_channel(struct aklcd_osd_channel *osd_channel)
+{
+	aklcd_set_osd_channel(osd_channel);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_open_rgb_channel(void)
+{
+	/* open rgb data channel */
+	lcd_set_reg(1, AK98_LCD_CMD1, 3, 3);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_open_ov1_channel(void)
+{
+	/* open yuv1 data channel */
+	lcd_set_reg(1, AK98_LCD_CMD1, 2, 2);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_open_ov2_channel(void)
+{
+	/* open yuv2 data channel */
+	lcd_set_reg(1, AK98_LCD_CMD1, 1, 1);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_open_osd_channel(void)
+{
+	/* open osd data channel */
+	lcd_set_reg(1, AK98_LCD_CMD1, 0, 0);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_close_rgb_channel(void)
+{
+	lcd_set_reg(0, AK98_LCD_CMD1, 3, 3);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_close_ov1_channel(void)
+{
+	lcd_set_reg(0, AK98_LCD_CMD1, 2, 2);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_close_ov2_channel(void)
+{
+	lcd_set_reg(0, AK98_LCD_CMD1, 1, 1);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static void aklcd_close_osd_channel(void)
+{
+	lcd_set_reg(0, AK98_LCD_CMD1, 0, 0);
+	lcd_set_reg(1, AK98_LCD_SOFT_CTRL, 12, 12);
+}
+
+static bool aklcd_get_rgb_enable(void)
+{
+	return (lcd_get_reg(AK98_LCD_CMD1, 3, 3) == 1);
+}
+
+static bool aklcd_get_ov1_enable(void)
+{
+	return (lcd_get_reg(AK98_LCD_CMD1, 2, 2) == 1);
+}
+
+static bool aklcd_get_ov2_enable(void)
+{
+	return (lcd_get_reg(AK98_LCD_CMD1, 1, 1) == 1);
+}
+
+static bool aklcd_get_osd_enable(void)
+{
+	return (lcd_get_reg(AK98_LCD_CMD1, 0, 0) == 1);
+}
+
+
+/********************
+ * irq handle
+ ********************/
+static inline void handle_alert_irq(struct akfb *akfb, struct device *dev)
+{
+	aklcd_enable_alert(false);
+
+	/* after read the final line to inner FIFO,
+	   LCD controller should use new parameter now */
+	if (test_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits))) {
+		complete(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+	}
+
+	if (test_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits))) {
+		/* update ov1ch information */
+		memcpy(&(akfb->ov1ch), &(akfb->ov1ch_new),sizeof(struct aklcd_overlay_channel));
+	}
+
+	if (test_bit(AKLCD_CHANNEL_OV2, &(akfb->par_change_bits))) {
+		memcpy(&(akfb->ov2ch), &(akfb->ov2ch_new),sizeof(struct aklcd_overlay_channel));
+	}
+
+	if (test_bit(AKLCD_CHANNEL_OSD, &(akfb->par_change_bits))) {
+		memcpy(&(akfb->osdch), &(akfb->osdch_new),sizeof(struct aklcd_osd_channel));
+	}
+}
+
+static irqreturn_t akfb_irq_handler(int irq, void *dev_id)
+{
+	struct akfb   *akfb = dev_id;
+	struct device *dev = &(akfb->pdev->dev);
+	u32 irq_status;
+
+	irq_status = aklcd_get_irq_status();
+
+	if (irq_status & 0x01) {
+		/* lcd controller error */
+		dev_err(dev, "LCD controller system error\n");
+		/* restart sync signal */
+		aklcd_stop_refresh(akfb->if_type, dev);
+		aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+		akfb->panel_refreshing = true;
+
+		return IRQ_HANDLED;
+	}
+
+	if (irq_status & (1<<17)) {
+		handle_alert_irq(akfb, dev);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/********************
+ * fb_ops
+ ********************/
+static const struct fb_bitfield rgb565_r = {.offset=11, .length=5, .msb_right=0};
+static const struct fb_bitfield rgb565_g = {.offset=5,  .length=6, .msb_right=0};
+static const struct fb_bitfield rgb565_b = {.offset=0,  .length=5, .msb_right=0};
+static const struct fb_bitfield bgr565_b = {.offset=11, .length=5, .msb_right=0};
+static const struct fb_bitfield bgr565_g = {.offset=5,  .length=6, .msb_right=0};
+static const struct fb_bitfield bgr565_r = {.offset=0,  .length=5, .msb_right=0};
+static const struct fb_bitfield rgb888_r = {.offset=16, .length=8, .msb_right=0};
+static const struct fb_bitfield rgb888_g = {.offset=8,  .length=8, .msb_right=0};
+static const struct fb_bitfield rgb888_b = {.offset=0,  .length=8, .msb_right=0};
+static const struct fb_bitfield bgr888_b = {.offset=16, .length=8, .msb_right=0};
+static const struct fb_bitfield bgr888_g = {.offset=8,  .length=8, .msb_right=0};
+static const struct fb_bitfield bgr888_r = {.offset=0,  .length=8, .msb_right=0};
+
+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
+{
+	unsigned int mask = (1 << bf->length) - 1;
+
+	return (val >> (16 - bf->length) & mask) << bf->offset;
+}
+
+static int akfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+			  unsigned blue, unsigned transp,
+			  struct fb_info *fb)
+{
+	/* anyka lcd controller only support true color */
+	if (regno >= 16)
+		return -EINVAL;
+
+	((u32*)(fb->pseudo_palette))[regno] = convert_bitfield(transp, &(fb->var.transp)) |
+		convert_bitfield(blue, &(fb->var.blue)) |
+		convert_bitfield(green, &(fb->var.green)) |
+		convert_bitfield(red, &(fb->var.red));
+
+	return 0;
+}
+
+static int __akfb_get_pixel_format(const struct fb_var_screeninfo *var)
+{
+	if (var->bits_per_pixel == 16) {
+		if (memcmp(&(var->red), &rgb565_r, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->green), &rgb565_g, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->blue), &rgb565_b, sizeof(struct fb_bitfield)) == 0)
+			return AKLCD_RGB565;
+
+		if (memcmp(&(var->red), &bgr565_r, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->green), &bgr565_g, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->blue), &bgr565_b, sizeof(struct fb_bitfield)) == 0)
+			return AKLCD_BGR565;
+	}
+
+	if (var->bits_per_pixel == 24) {
+		if (memcmp(&(var->red), &rgb888_r, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->green), &rgb888_g, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->blue), &rgb888_b, sizeof(struct fb_bitfield)) == 0)
+			return AKLCD_RGB888;
+
+		if (memcmp(&(var->red), &bgr888_r, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->green), &bgr888_g, sizeof(struct fb_bitfield)) == 0
+		    && memcmp(&(var->blue), &bgr888_b, sizeof(struct fb_bitfield)) == 0)
+			return AKLCD_BGR888;
+	}
+
+	return -EINVAL;
+}
+
+static int akfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
+{
+	struct akfb *akfb;
+	struct device *dev;
+
+	akfb = fb->par;
+	dev = &(akfb->pdev->dev);
+
+	if (var->xres_virtual < var->xres || var->yres_virtual < var->yres) {
+		return -EINVAL;
+	}
+
+	if (var->xoffset > (var->xres_virtual - var->xres)
+	    || var->yoffset > (var->yres_virtual - var->yres)) {
+		return -EINVAL;
+	}
+
+	if (var->xres > akfb->screen.width || var->yres > akfb->screen.height
+	    || var->xres_virtual > AKLCD_VPAGE_WIDTH_MAX || var->yres_virtual > AKLCD_VPAGE_HEIGHT_MAX) {
+		return -EINVAL;
+	}
+
+	if (__akfb_get_pixel_format(var) < 0) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int akfb_set_par(struct fb_info *fb)
+{
+	struct akfb                  *akfb;
+	struct aklcd_rgb_channel     new_rgbch;
+	struct aklcd_channel_meminfo new_rgbch_meminfo;
+	struct device                *dev;
+	int                          new_rgbch_bpp;
+
+	akfb = fb->par;
+	dev = &(akfb->pdev->dev);
+
+	mutex_lock_interruptible(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	init_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+
+	new_rgbch.format       = __akfb_get_pixel_format(&fb->var);
+	new_rgbch.use_vpage    = true; /* alway enable virtual page */
+	new_rgbch.vpage_width  = fb->var.xres_virtual;
+	new_rgbch.vpage_height = fb->var.yres_virtual;
+	new_rgbch.virt_left    = fb->var.xoffset;
+	new_rgbch.virt_top     = fb->var.yoffset;
+	new_rgbch.width        = fb->var.xres;
+	new_rgbch.height       = fb->var.yres;
+	new_rgbch.disp_left    = akfb->screen.width / 2 - new_rgbch.width / 2;
+	new_rgbch.disp_top     = akfb->screen.height / 2 - new_rgbch.height / 2;
+
+	if(new_rgbch.format == AKLCD_RGB565 || new_rgbch.format == AKLCD_BGR565)
+		new_rgbch_bpp   = 2;
+	else
+		new_rgbch_bpp   = 3;
+
+	if (new_rgbch.use_vpage)
+		new_rgbch_meminfo.size  = new_rgbch.vpage_width * new_rgbch.vpage_height * new_rgbch_bpp;
+	else
+		new_rgbch_meminfo.size  = new_rgbch.width * new_rgbch.height * new_rgbch_bpp;
+	dev_info(dev, "new fb memory size: %u\n", new_rgbch_meminfo.size);
+
+	if (new_rgbch_meminfo.size <= akfb->rgbch_meminfo.size
+	    && new_rgbch_meminfo.size > akfb->rgbch_meminfo.size/2) {
+		dev_info(dev, "reuse current fb memory\n");
+		new_rgbch_meminfo.paddr = akfb->rgbch_meminfo.paddr;
+		new_rgbch_meminfo.vaddr = akfb->rgbch_meminfo.vaddr;
+		new_rgbch_meminfo.size  = akfb->rgbch_meminfo.size;
+	} else {
+		new_rgbch_meminfo.vaddr =
+			dma_alloc_writecombine(dev, new_rgbch_meminfo.size,
+					       &new_rgbch_meminfo.paddr, GFP_KERNEL);
+		if (new_rgbch_meminfo.vaddr == NULL) {
+			dev_err(dev, "alloc fb memory error\n");
+			if (new_rgbch_meminfo.size <= akfb->rgbch_meminfo.size) {
+				dev_info(dev, "reuse current fb memory\n");
+				new_rgbch_meminfo.paddr = akfb->rgbch_meminfo.paddr;
+				new_rgbch_meminfo.vaddr = akfb->rgbch_meminfo.vaddr;
+				new_rgbch_meminfo.size  = akfb->rgbch_meminfo.size;
+			} else {
+				mutex_unlock(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+				return -ENOMEM;
+			}
+		}
+	}
+
+	new_rgbch.data_addr   = new_rgbch_meminfo.paddr;
+	dev_info(dev, "framebuffer address: 0x%08x\n", new_rgbch_meminfo.paddr);
+
+	aklcd_change_rgb_channel(&new_rgbch);
+
+	if (akfb->panel_refreshing) {
+		set_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits));
+
+		aklcd_enable_alert(true);
+
+		wait_for_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+	}
+
+	if (new_rgbch_meminfo.paddr != akfb->rgbch_meminfo.paddr) {
+		dma_free_writecombine(dev, akfb->rgbch_meminfo.size,
+				      akfb->rgbch_meminfo.vaddr, akfb->rgbch_meminfo.paddr);
+		memcpy(&(akfb->rgbch_meminfo), &new_rgbch_meminfo, sizeof(struct aklcd_channel_meminfo));
+	}
+	memcpy(&(akfb->rgbch), &new_rgbch, sizeof(struct aklcd_rgb_channel));
+
+	/* update fix info */
+	fb->fix.smem_start = new_rgbch_meminfo.paddr;
+	if (new_rgbch.use_vpage) {
+		fb->fix.line_length = new_rgbch.vpage_width * new_rgbch_bpp;
+		/* in reuse fb memory situation, new_rgbch_meminfo.size maybe not equal to 
+		   actual fb memory size, so we need to calculate it */
+		fb->fix.smem_len   = fb->fix.line_length * new_rgbch.vpage_height;
+	} else {
+		fb->fix.line_length = new_rgbch.width * new_rgbch_bpp;
+		fb->fix.smem_len   = fb->fix.line_length * new_rgbch.height;
+	}
+
+	fb->screen_base = new_rgbch_meminfo.vaddr;
+	fb->screen_size = fb->fix.smem_len;
+
+	mutex_unlock(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	return 0;
+}
+
+static int akfb_pan_display(struct fb_var_screeninfo *var,
+			    struct fb_info *fb)
+{
+	struct akfb                  *akfb;
+	struct device                *dev;
+
+	akfb = fb->par;
+	dev = &(akfb->pdev->dev);
+
+	if (var->xoffset == fb->var.xoffset && var->yoffset == fb->var.yoffset) {
+		dev_info(dev, "xoffset & yoffset not change\n");
+		return 0;
+	}
+
+	mutex_lock_interruptible(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	init_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+
+	aklcd_change_rgb_vpage_offset(var->xoffset, var->yoffset);
+
+	if (akfb->panel_refreshing) {
+		set_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits));
+
+		aklcd_enable_alert(true);
+
+		wait_for_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+	}
+
+	akfb->rgbch.virt_left = var->xoffset;
+	akfb->rgbch.virt_top = var->yoffset;
+
+	mutex_unlock(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	return 0;
+}
+
+static int akfb_blank(int blank, struct fb_info *fb)
+{
+	struct akfb    *akfb;
+	struct device  *dev;
+
+	akfb = fb->par;
+	dev = &(akfb->pdev->dev);
+
+	mutex_lock_interruptible(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	switch (blank) {
+	case FB_BLANK_POWERDOWN:
+	case FB_BLANK_HSYNC_SUSPEND:
+	case FB_BLANK_VSYNC_SUSPEND:
+	case FB_BLANK_NORMAL:
+		if (akfb->panel_refreshing == true) {
+			aklcd_stop_refresh(akfb->if_type, dev);
+			aklcd_set_power(false);
+			akfb->panel_refreshing = false;
+		}
+		break;
+	case FB_BLANK_UNBLANK:
+		if (akfb->panel_refreshing == false) {
+			aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+			aklcd_set_power(true);
+			akfb->panel_refreshing = true;
+		}
+		break;
+	}
+
+	mutex_unlock(&(akfb->aklcd_par_lock[AKLCD_CHANNEL_RGB]));
+
+	return 0;
+}
+
+static int akfb_ioctl(struct fb_info *fb, unsigned int cmd, unsigned long arg)
+{
+	struct akfb               *akfb;
+	struct device             *dev;
+	struct aklcd_overlay_info ovi;
+	struct aklcd_osd_info     osdi;
+	int                       ret;
+	enum ak_tvout_mode        tvout_mode = TVOUT_OFF;
+
+	akfb = fb->par;
+	dev = &(akfb->pdev->dev);
+	ret = 0;
+
+	switch(cmd) {
+	case FBIOGET_AKOVINFO:
+		if (copy_from_user(&ovi, (void __user *)arg, sizeof(struct aklcd_overlay_info)))
+			return -EFAULT;
+
+		switch(ovi.overlay_id) {
+		case 0:
+			ovi.enable = aklcd_get_ov1_enable();
+			if (ovi.enable) {
+				memcpy(&(ovi.overlay_setting), &(akfb->ov1ch),
+				       sizeof(struct aklcd_overlay_channel));
+			}
+			ret = copy_to_user((void __user *)arg, &ovi,
+					   sizeof(struct aklcd_overlay_info)) ? -EFAULT : 0;
+			break;
+		case 1:
+			ovi.enable = aklcd_get_ov2_enable();
+			if (ovi.enable) {
+				memcpy(&(ovi.overlay_setting), &(akfb->ov2ch),
+				       sizeof(struct aklcd_overlay_channel));
+			}
+			ret = copy_to_user((void __user *)arg, &ovi,
+					   sizeof(struct aklcd_overlay_info)) ? -EFAULT : 0;
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+
+	case FBIOPUT_AKOVINFO:
+		if (copy_from_user(&ovi, (void __user *)arg, sizeof(struct aklcd_overlay_info)))
+			return -EFAULT;
+
+		switch(ovi.overlay_id) {
+		case 0:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov1_enable() == true)
+					aklcd_close_ov1_channel();
+			} else {
+				if (aklcd_get_ov1_enable() == false) {
+					aklcd_set_ov1_channel(&(ovi.overlay_setting));
+					aklcd_open_ov1_channel();
+				} else {
+					aklcd_change_ov1_channel(&(ovi.overlay_setting));
+				}
+				memcpy(&(akfb->ov1ch_new), &(ovi.overlay_setting),
+				       sizeof(struct aklcd_overlay_channel));
+				set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+			}
+			break;
+		case 1:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov2_enable() == true)
+					aklcd_close_ov2_channel();
+			} else {
+				if (aklcd_get_ov2_enable() == false) {
+					aklcd_set_ov2_channel(&(ovi.overlay_setting));
+					aklcd_open_ov2_channel();
+				} else {
+					aklcd_change_ov2_channel(&(ovi.overlay_setting));
+				}
+				memcpy(&(akfb->ov2ch_new), &(ovi.overlay_setting),
+				       sizeof(struct aklcd_overlay_channel));
+
+				set_bit(AKLCD_CHANNEL_OV2, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+			}
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+
+	case FBIOGET_AKOSDINFO:
+		memset(&osdi, 0, sizeof(osdi)); /* avoid kernel data leak */
+		osdi.enable = aklcd_get_osd_enable();
+		if (osdi.enable) {
+			memcpy(&(osdi.osd_setting), &(akfb->osdch),
+			       sizeof(struct aklcd_osd_channel));
+		}
+
+		ret = copy_to_user((void __user *)arg, &osdi,
+				   sizeof(struct aklcd_osd_info)) ? -EFAULT : 0;
+		break;
+
+	case FBIOPUT_AKOSDINFO:
+		if (copy_from_user(&osdi, (void __user *)arg, sizeof(struct aklcd_osd_info)))
+			return -EFAULT;
+
+		if (osdi.enable == false) {
+			if (aklcd_get_osd_enable() == true)
+				aklcd_close_osd_channel();
+		} else {
+			if (aklcd_get_osd_enable() == false) {
+				aklcd_set_osd_channel(&(osdi.osd_setting));
+				aklcd_open_osd_channel();
+			} else {
+				aklcd_change_osd_channel(&(osdi.osd_setting));
+			}
+			memcpy(&(akfb->osdch_new), &(osdi.osd_setting),
+			       sizeof(struct aklcd_osd_channel));
+			set_bit(AKLCD_CHANNEL_OSD, &(akfb->par_change_bits));
+			aklcd_enable_alert(true);
+		}	
+		break;
+
+	case FBIOPUT_AKOVPOSI:
+		if (copy_from_user(&ovi, (void __user *)arg, sizeof(struct aklcd_overlay_info)))
+			return -EFAULT;
+
+		switch(ovi.overlay_id) {
+		case 0:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov1_enable() == true)
+					aklcd_close_ov1_channel();
+			} else {
+				if (akfb->tvout_mode == TVOUT_OFF) {
+					akfb->ov1ch_new.src_range = ovi.overlay_setting.src_range;
+					akfb->ov1ch_new.src_width = ovi.overlay_setting.src_width;
+					akfb->ov1ch_new.src_height = ovi.overlay_setting.src_height;
+					akfb->ov1ch_new.dst_width = ovi.overlay_setting.dst_width;
+					akfb->ov1ch_new.dst_height = ovi.overlay_setting.dst_height;
+					akfb->ov1ch_new.disp_left = ovi.overlay_setting.disp_left;
+					akfb->ov1ch_new.disp_top = ovi.overlay_setting.disp_top;
+					akfb->ov1ch_new.use_vpage = false;
+					set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+					aklcd_enable_alert(true);
+				} else {
+					akfb->ov1ch_saved.src_range = ovi.overlay_setting.src_range;
+					akfb->ov1ch_saved.src_width = ovi.overlay_setting.src_width;
+					akfb->ov1ch_saved.src_height = ovi.overlay_setting.src_height;
+					akfb->ov1ch_saved.dst_width = ovi.overlay_setting.dst_width;
+					akfb->ov1ch_saved.dst_height = ovi.overlay_setting.dst_height;
+					akfb->ov1ch_saved.disp_left = ovi.overlay_setting.disp_left;
+					akfb->ov1ch_saved.disp_top = ovi.overlay_setting.disp_top;
+					akfb->ov1ch_saved.use_vpage = false;
+
+					if (akfb->ov1ch_new.src_width != ovi.overlay_setting.src_width
+					    || akfb->ov1ch_new.src_height != ovi.overlay_setting.src_height) {
+
+                        akfb->ov1ch_new.src_range = ovi.overlay_setting.src_range;
+                        akfb->ov1ch_new.src_width = ovi.overlay_setting.src_width;
+                        akfb->ov1ch_new.src_height = ovi.overlay_setting.src_height;
+                        akfb->ov1ch_new.dst_width = ovi.overlay_setting.dst_width;
+                        akfb->ov1ch_new.dst_height = ovi.overlay_setting.dst_height;
+                        akfb->ov1ch_new.disp_left = ovi.overlay_setting.disp_left;
+                        akfb->ov1ch_new.disp_top = ovi.overlay_setting.disp_top;
+
+						aklcd_get_tvout_dst_params(&akfb->ov1ch_new,akfb->tvout_mode);
+						aklcd_set_ov1_channel(&akfb->ov1ch_new);					
+						set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+						aklcd_enable_alert(true);
+					}
+				}
+			}
+			break;
+		case 1:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov2_enable() == true)
+					aklcd_close_ov2_channel();
+			} else {
+				akfb->ov2ch_new.alpha = ovi.overlay_setting.alpha;
+				akfb->ov2ch_new.src_width = ovi.overlay_setting.src_width;
+				akfb->ov2ch_new.src_height = ovi.overlay_setting.src_height;
+				akfb->ov2ch_new.dst_width = ovi.overlay_setting.dst_width;
+				akfb->ov2ch_new.dst_height = ovi.overlay_setting.dst_height;
+				akfb->ov2ch_new.disp_left = ovi.overlay_setting.disp_left;
+				akfb->ov2ch_new.disp_top = ovi.overlay_setting.disp_top;
+				set_bit(AKLCD_CHANNEL_OV2, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+			}	
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+
+	case FBIOPUT_AKOVDATA:
+		if (copy_from_user(&ovi, (void __user *)arg, sizeof(struct aklcd_overlay_info)))
+			return -EFAULT;
+
+		switch(ovi.overlay_id) {
+		case 0:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov1_enable() == true)
+					aklcd_close_ov1_channel();
+			} else {
+				akfb->ov1ch_new.y_addr = ovi.overlay_setting.y_addr;
+				akfb->ov1ch_new.u_addr = ovi.overlay_setting.u_addr;
+				akfb->ov1ch_new.v_addr = ovi.overlay_setting.v_addr;
+				if (aklcd_get_ov1_enable() == false) {
+					aklcd_set_ov1_channel(&(akfb->ov1ch_new));
+					aklcd_open_ov1_channel();
+				} else {
+					aklcd_change_ov1_channel(&(akfb->ov1ch_new));
+				}
+				set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+			}	
+			break;
+		case 1:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov2_enable() == true)
+					aklcd_close_ov2_channel();
+			} else {
+				akfb->ov2ch_new.y_addr = ovi.overlay_setting.y_addr;
+				akfb->ov2ch_new.u_addr = ovi.overlay_setting.u_addr;
+				akfb->ov2ch_new.v_addr = ovi.overlay_setting.v_addr;
+
+				if (aklcd_get_ov2_enable() == false) {
+					aklcd_set_ov2_channel(&(akfb->ov2ch_new));
+					aklcd_open_ov2_channel();
+				} else {
+					aklcd_change_ov2_channel(&(akfb->ov2ch_new));
+				}
+		
+				set_bit(AKLCD_CHANNEL_OV2, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+			}	
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+
+	case FBIOPUT_AKOVSHOWING:
+		if (copy_from_user(&ovi, (void __user *)arg, sizeof(struct aklcd_overlay_info)))
+			return -EFAULT;
+
+		switch(ovi.overlay_id) {
+		case 0:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov1_enable() == true)
+					aklcd_close_ov1_channel();
+			} else {
+				if (aklcd_get_ov1_enable() == false) {
+					aklcd_set_ov1_channel(&(akfb->ov1ch));
+					aklcd_open_ov1_channel();
+				}
+			}
+			break;
+		case 1:
+			if (ovi.enable == false) {
+				if (aklcd_get_ov2_enable() == true)
+					aklcd_close_ov2_channel();
+			} else {
+				if (aklcd_get_ov2_enable() == false) {
+					aklcd_set_ov2_channel(&(akfb->ov2ch));
+					aklcd_open_ov2_channel();
+				}
+			}
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+		break;
+
+	case FBIOPUT_AKTVOUT:
+		if (copy_from_user(&tvout_mode, (void __user *)arg, sizeof(int)))
+			return -EFAULT;
+
+		printk("++FBIOPUT_AKTVOUT tvout_mode=%d,akfb->tvout_mode=%d\n",tvout_mode,akfb->tvout_mode);
+
+		switch (tvout_mode) {
+		case TVOUT_OFF:         //turn off tvout
+			if (akfb->tvout_mode == TVOUT_OFF)
+				break;
+
+			aklcd_stop_refresh(akfb->if_type, dev);
+			akfb->tvout_mode = TVOUT_OFF;
+			akfb->if_type = DISP_IF_RGB;
+
+            aklcd_close_osd_channel();
+            aklcd_close_ov1_channel();
+            aklcd_close_ov2_channel();
+            aklcd_close_rgb_channel();
+
+			/* set screen */
+			akfb->screen.width    = bsp_rgb_panel.thd;
+			akfb->screen.height   = bsp_rgb_panel.tvd;
+			akfb->screen.bg_color = AKRGB(0, 0, 0);
+			aklcd_set_screen(&akfb->screen);
+
+			aklcd_set_rgb_channel(&akfb->rgbch);
+			aklcd_open_rgb_channel();
+
+			//restore akfb->ov1ch_new
+			akfb->ov1ch_new.src_range  = akfb->ov1ch_saved.src_range;
+			akfb->ov1ch_new.src_width  = akfb->ov1ch_saved.src_width;
+			akfb->ov1ch_new.src_height = akfb->ov1ch_saved.src_height;
+			akfb->ov1ch_new.dst_width  = akfb->ov1ch_saved.dst_width;
+			akfb->ov1ch_new.dst_height = akfb->ov1ch_saved.dst_height;
+			akfb->ov1ch_new.disp_left  = akfb->ov1ch_saved.disp_left;
+			akfb->ov1ch_new.disp_top   = akfb->ov1ch_saved.disp_top;
+			akfb->ov1ch_new.use_vpage  = akfb->ov1ch_saved.use_vpage;
+			aklcd_set_ov1_channel(&akfb->ov1ch_new);
+			aklcd_open_ov1_channel();
+			set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+			aklcd_enable_alert(true);
+
+			aklcd_set_rgb_panel(akfb->rgb_panel, &(akfb->pdev->dev));
+			aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+			
+			akfb->panel_refreshing = true;
+            
+			break;
+
+        case PAL:
+		case NTSC:	//turn on tv out.
+			if(tvout_mode == akfb->tvout_mode)
+				break;
+
+			akfb->tvout_mode = tvout_mode;
+			akfb->if_type = DISP_IF_TVOUT;
+			akfb->panel_refreshing = false;
+
+			//tvout: stop refresh.
+			aklcd_stop_refresh(akfb->if_type, dev);
+
+            aklcd_close_osd_channel();
+            aklcd_close_ov1_channel();
+            aklcd_close_ov2_channel();
+            aklcd_close_rgb_channel();	  
+            
+			//tvout: change screen.
+			akfb->screen.width = (tvout_mode==PAL?TV_PAL_WIDTH:TV_NTSC_WIDTH);
+			akfb->screen.height = (tvout_mode==PAL?TV_PAL_HEIGHT:TV_NTSC_HEIGHT);
+			akfb->screen.bg_color = AKYUV(16,128,128);//black
+			aklcd_set_screen (&(akfb->screen));
+
+			//tvout: change overlay1
+			aklcd_get_tvout_dst_params(&akfb->ov1ch_new,akfb->tvout_mode);
+		    aklcd_set_ov1_channel(&akfb->ov1ch_new);
+		    aklcd_open_ov1_channel();
+			set_bit(AKLCD_CHANNEL_OV1, &(akfb->par_change_bits));
+			aklcd_enable_alert(true);
+
+            //tvout: set tvout interface.
+			aklcd_set_tvout_panel(akfb->tvout_mode);
+			aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+			break;
+
+		default:
+			ret = -EINVAL;
+			break;
+		} /* switch (tvout_mode) */
+		printk("--FBIOPUT_AKTVOUT\n");
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static struct fb_ops akfb_ops = {
+	.owner		= THIS_MODULE,
+	/* needed by fb_set_cmap() */
+	.fb_setcolreg	= akfb_setcolreg,
+	/* needed by FBIOPUT_VSCREENINFO */
+	.fb_check_var	= akfb_check_var,
+	.fb_set_par	= akfb_set_par,
+	.fb_pan_display	= akfb_pan_display,
+	/* need by FBIOBLANK */
+	.fb_blank	= akfb_blank,
+	/* needed by fbcon */
+	.fb_fillrect	= cfb_fillrect,
+	.fb_copyarea	= cfb_copyarea,
+	.fb_imageblit	= cfb_imageblit,
+	/* extended ioctl */
+	.fb_ioctl	= akfb_ioctl,
+};
+
+#define freq_to_akfb(_n) container_of(_n, struct akfb, freq_transition)
+
+#ifdef CONFIG_CPU_FREQ
+static void get_cpufreq_need_info(struct cpufreq_freqs *freqs,
+	int *prechange, int *postchange)
+{
+	int close_lcd_display = 0;
+	int open_lcd_display = 0;
+	
+	// new mode is low mode, else new mode is nomal mode
+	if (freqs->new_cpufreq.low_clock) {
+		if (!freqs->old_cpufreq.low_clock) {
+			close_lcd_display = 1;
+			open_lcd_display = 0;
+		}else {
+			close_lcd_display = 0;
+			open_lcd_display = 0;
+		}
+	} else if (!freqs->new_cpufreq.low_clock) {
+		if (!freqs->old_cpufreq.low_clock) {
+			if (freqs->old_cpufreq.pll_sel == freqs->new_cpufreq.pll_sel) {
+				if (freqs->old_cpufreq.asic_clk != freqs->new_cpufreq.asic_clk) {
+					close_lcd_display = 1;
+					open_lcd_display = 1;
+				} else {
+					close_lcd_display = 0;
+					open_lcd_display = 0;
+				}
+			} else {
+				close_lcd_display = 1;
+            	open_lcd_display = 1;
+			}
+		} else if (freqs->old_cpufreq.low_clock){
+			close_lcd_display = 0;
+			open_lcd_display = 1;
+		}
+	}
+
+	*prechange = close_lcd_display;
+	*postchange = open_lcd_display;
+}
+static int ak98fb_cpufreq_transition(struct notifier_block *nb,
+					unsigned long val, void *data)
+{
+	struct akfb *akfb = freq_to_akfb(nb);
+	struct cpufreq_freqs *freqs = data;	
+	struct device *dev = &(akfb->pdev->dev);
+	int lcd_close_display = 0;
+	int lcd_open_display = 0;
+
+	get_cpufreq_need_info(freqs, &lcd_close_display, &lcd_open_display);
+		
+	if (val == CPUFREQ_PRECHANGE)
+	{
+		if(lcd_close_display) {
+			struct fb_event event;
+			printk("AK98FB: CPUFREQ PRE-Change\n");
+			
+			acquire_console_sem();
+			event.info = akfb->fb;
+			fb_notifier_call_chain(FB_EVENT_PRE_CPUFREQ, &event);
+			
+			akfb->bOv1ChnlOpened = aklcd_get_ov1_enable();
+			akfb->bOv2ChnlOpened = aklcd_get_ov2_enable();
+			akfb->bOsdChnlOpened = aklcd_get_osd_enable();
+			
+			aklcd_close_rgb_channel();
+			aklcd_close_ov1_channel();
+			aklcd_close_ov2_channel();
+			aklcd_close_osd_channel();
+
+			if (akfb->panel_refreshing) {
+				init_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+				set_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+				wait_for_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+			}
+				
+			if (freqs->new_cpufreq.low_clock) {
+				akfb->panel_refreshing = false;
+			}
+			release_console_sem();
+		}
+	}
+	else if (val == CPUFREQ_POSTCHANGE)
+	{
+		if (lcd_open_display) {
+			struct fb_event event;
+			printk("AK98FB: CPUFREQ POST-Change\n");
+
+			acquire_console_sem();
+			event.info = akfb->fb;
+			fb_notifier_call_chain(FB_EVENT_POST_CPUFREQ, &event);
+
+			// from previous low mode to current's normal mode
+			if (freqs->old_cpufreq.low_clock) {
+				aklcd_enable();
+				aklcd_set_screen(&(akfb->screen));
+				aklcd_set_rgb_irq();
+				aklcd_set_rgb_panel(akfb->rgb_panel, dev);
+				aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+				aklcd_set_power(true);
+				akfb->panel_refreshing = true;
+			}
+			aklcd_set_rgb_channel(&(akfb->rgbch));
+			aklcd_open_rgb_channel();
+
+			if(akfb->bOv1ChnlOpened == true)
+			{
+				aklcd_set_ov1_channel(&(akfb->ov1ch));
+				aklcd_open_ov1_channel();
+			}
+			if(akfb->bOv2ChnlOpened == true)
+			{
+				aklcd_set_ov2_channel(&(akfb->ov2ch));
+				aklcd_open_ov2_channel();
+			}
+			if(akfb->bOsdChnlOpened == true)
+			{
+				aklcd_set_osd_channel(&(akfb->osdch));
+				aklcd_open_osd_channel();
+			}
+
+			if (akfb->panel_refreshing) {
+				init_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+				set_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits));
+				aklcd_enable_alert(true);
+				wait_for_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+			}
+
+			release_console_sem();
+		}
+	}
+	
+	return 0;
+
+}
+
+static inline int ak98fb_cpufreq_register(struct akfb *info)
+{
+	info->freq_transition.notifier_call = ak98fb_cpufreq_transition;
+
+	return cpufreq_register_notifier(&info->freq_transition,
+					 CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void ak98fb_cpufreq_deregister(struct akfb *info)
+{
+	cpufreq_unregister_notifier(&info->freq_transition,
+				    CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int ak98fb_cpufreq_register(struct akfb *info)
+{
+	return 0;
+}
+
+static inline void ak98fb_cpufreq_deregister(struct akfb *info)
+{
+}
+#endif
+
+
+/********************
+ * driver entry
+ ********************/
+extern const unsigned int ak_logo_width;
+extern const unsigned int ak_logo_height;
+extern const unsigned short ak_logo[]; /* rgb565 480x272 */
+
+static int __devinit ak98fb_probe(struct platform_device *pdev)
+{
+	struct akfb                  *akfb;
+	struct fb_info               *fb;
+	struct aklcd_rgb_panel       *rgb_panel;
+	struct aklcd_screen          *screen;
+	struct aklcd_rgb_channel     *rgbch;
+	struct aklcd_channel_meminfo *rgbch_meminfo;
+	struct aklcd_overlay_channel *ov1ch;
+	struct aklcd_channel_meminfo *ov1ch_meminfo;
+	struct aklcd_overlay_channel *ov2ch;
+	struct aklcd_channel_meminfo *ov2ch_meminfo;
+	struct aklcd_osd_channel     *osdch;
+	struct aklcd_channel_meminfo *osdch_meminfo;
+
+	unsigned int     width, height, rgbch_bpp;
+	struct device    *dev = &pdev->dev;
+	int              i, irq, ret;
+
+	fb = framebuffer_alloc(sizeof(struct akfb), dev);
+	if (fb == NULL) {
+		dev_err(dev, "alloc framebuffer error\n");
+		return -ENOMEM;
+	}
+
+	akfb = fb->par;
+	akfb->fb = fb;
+
+	platform_set_drvdata(pdev, akfb);
+	akfb->pdev = pdev;
+
+	for (i = 0; i < AKLCD_CHANNEL_MAX; i++) {
+		mutex_init(&(akfb->aklcd_par_lock[i]));
+		clear_bit(i, &(akfb->par_change_bits));
+	}
+
+	akfb->if_type   = DISP_IF_RGB;
+	akfb->rgb_panel = &bsp_rgb_panel;
+	rgb_panel       = akfb->rgb_panel;
+	screen          = &(akfb->screen);
+	rgbch           = &(akfb->rgbch);
+	ov1ch           = &(akfb->ov1ch);
+	ov2ch           = &(akfb->ov2ch);
+	osdch           = &(akfb->osdch);
+	rgbch_meminfo   = &(akfb->rgbch_meminfo);
+	ov1ch_meminfo   = &(akfb->ov1ch_meminfo);
+	ov2ch_meminfo   = &(akfb->ov2ch_meminfo);
+	osdch_meminfo   = &(akfb->osdch_meminfo);
+
+	aklcd_enable();
+
+	/* set screen */
+	screen->width    = rgb_panel->thd;
+	screen->height   = rgb_panel->tvd;
+	screen->bg_color = AKRGB(0, 0, 0);
+
+	aklcd_set_screen(screen);
+
+	/* open rgb channel */
+	rgbch->format       = AKLCD_RGB565;
+	rgbch->use_vpage    = true; /* alway enable virtual page */
+	rgbch->vpage_width  = screen->width;
+	rgbch->vpage_height = screen->height * 2;
+	rgbch->virt_left    = 0;
+	rgbch->virt_top     = 0;
+	rgbch->disp_left    = 0;
+	rgbch->disp_top     = 0;
+	rgbch->width        = screen->width;
+	rgbch->height       = screen->height;
+
+	if (rgbch->format == AKLCD_RGB565 || rgbch->format == AKLCD_BGR565)
+		rgbch_bpp   = 2;
+	else
+		rgbch_bpp   = 3;
+
+	if (rgbch->use_vpage) {
+		width = rgbch->vpage_width;
+		height = rgbch->vpage_height;
+	} else {
+		width = rgbch->width;
+		height = rgbch->height;
+	}
+
+	rgbch_meminfo->size = width * height * rgbch_bpp;
+	dev_info(dev, "alloc framebuffer %i bytes\n", rgbch_meminfo->size);
+
+	rgbch_meminfo->vaddr = dma_alloc_writecombine(dev, rgbch_meminfo->size, &rgbch_meminfo->paddr, GFP_KERNEL);
+	if (rgbch_meminfo->vaddr == NULL) {
+		dev_err(dev, "alloc fb memory error\n");
+		ret = -ENOMEM;
+		goto _probe_err1;
+	}
+	rgbch->data_addr   = rgbch_meminfo->paddr;
+	dev_info(dev, "framebuffer address: 0x%08x\n", rgbch_meminfo->paddr);
+
+	{
+		int l, left, top;
+		top = (screen->height - ak_logo_height)/2;
+		left = (screen->width - ak_logo_width)/2;
+		printk ("width =%i, height = %i, width =%i, height =%i, top=%i,left=%i\n",
+			screen->width, screen->height, ak_logo_width, ak_logo_height, top, left);
+		for (l = 0; l < ak_logo_height; l++)
+			memcpy (rgbch_meminfo->vaddr+rgbch_bpp*(screen->width*(top+l) + left),
+				(void *)ak_logo+rgbch_bpp*(ak_logo_width*l), ak_logo_width*rgbch_bpp);
+	}
+
+	aklcd_set_rgb_channel(rgbch);
+	aklcd_open_rgb_channel();
+
+	/* set default irq mask */
+	aklcd_set_rgb_irq();
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(dev, "no IRQ defined\n");
+		ret = -ENODEV;
+		goto _probe_err1;
+	}
+	ret = request_irq(irq, akfb_irq_handler, IRQF_DISABLED, "AK LCDC", akfb);
+	if (ret) {
+		dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
+		ret = -EBUSY;
+		goto _probe_err1;
+	}
+
+
+	/* framebuffer */
+	/* set fix info */
+	strncpy(fb->fix.id, "ak-lcd", sizeof(fb->fix.id));
+	fb->fix.type      = FB_TYPE_PACKED_PIXELS;
+	fb->fix.type_aux  = 0; /* ? */
+	fb->fix.visual    = FB_VISUAL_TRUECOLOR;
+	fb->fix.xpanstep  = 1;
+	fb->fix.ypanstep  = 1;
+	fb->fix.ywrapstep = 0;
+	fb->fix.accel     = FB_ACCEL_NONE;
+
+	fb->fix.smem_start = rgbch_meminfo->paddr;
+	fb->fix.smem_len   = rgbch_meminfo->size;
+	if (rgbch->use_vpage)
+		fb->fix.line_length = rgbch->vpage_width * rgbch_bpp;
+	else
+		fb->fix.line_length = rgbch->width * rgbch_bpp;
+	fb->fix.mmio_start = 0;
+	fb->fix.mmio_len   = 0;
+
+	/* set var info */
+	fb->var.xres         = rgbch->width;
+	fb->var.yres         = rgbch->height;
+	fb->var.xres_virtual = rgbch->vpage_width;
+	fb->var.yres_virtual = rgbch->vpage_height;
+	fb->var.xoffset      = 0;
+	fb->var.yoffset      = 0;
+	fb->var.grayscale    = 0;
+	memset(&(fb->var.transp), 0, sizeof(struct fb_bitfield));
+	switch (rgbch->format) {
+	case AKLCD_RGB565:
+		fb->var.bits_per_pixel = 16;
+		memcpy(&(fb->var.red), &rgb565_r, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.green), &rgb565_g, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.blue), &rgb565_b, sizeof(struct fb_bitfield));
+		break;
+	case AKLCD_BGR565:
+		fb->var.bits_per_pixel = 16;
+		memcpy(&(fb->var.red), &bgr565_r, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.green), &bgr565_g, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.blue), &bgr565_b, sizeof(struct fb_bitfield));
+		break;
+	case AKLCD_RGB888:
+		fb->var.bits_per_pixel = 24;
+		memcpy(&(fb->var.red), &rgb888_r, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.green), &rgb888_g, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.blue), &rgb888_b, sizeof(struct fb_bitfield));
+		break;
+	case AKLCD_BGR888:
+		fb->var.bits_per_pixel = 24;
+		memcpy(&(fb->var.red), &bgr888_r, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.green), &bgr888_g, sizeof(struct fb_bitfield));
+		memcpy(&(fb->var.blue), &bgr888_b, sizeof(struct fb_bitfield));
+		break;
+	}
+	fb->var.nonstd = 0;
+	fb->var.activate = FB_ACTIVATE_NOW;
+	fb->var.height = -1;
+	fb->var.width = -1;
+	fb->var.pixclock = rgb_panel->pclk_freq;
+	fb->var.left_margin = rgb_panel->thbp;
+	fb->var.right_margin = rgb_panel->thfp;
+	fb->var.upper_margin = rgb_panel->tvbp;
+	fb->var.lower_margin = rgb_panel->tvfp;
+	fb->var.hsync_len = rgb_panel->thpw;
+	fb->var.vsync_len = rgb_panel->tvpw;
+	fb->var.sync = 0;	/* ? */
+	fb->var.vmode = FB_VMODE_NONINTERLACED;
+	fb->var.rotate = 0;
+
+	fb->node = -1;
+	fb->fbops = &akfb_ops;
+	fb->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
+	fb->screen_base = rgbch_meminfo->vaddr;
+	fb->screen_size = rgbch_meminfo->size;
+
+	/* used by .fb_fillrect and .fb_imgblt */
+	fb->pseudo_palette = akfb->pseudo_palette;
+
+	/* needed by FBIOGETCMAP & FBIOPUTCMAP */
+	ret = fb_alloc_cmap(&fb->cmap, 256, 0);
+	if (ret < 0) {
+		dev_err(dev, "Failed to alloc cmap: %d\n", ret);
+		goto _probe_err2;
+	}
+
+	dev_info(dev, "register frame buffer device: %s\n", fb->fix.id);
+	ret = register_framebuffer(fb);
+	if (ret < 0) {
+		dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
+		goto _probe_err3;
+	}
+	dev_info(dev, "fb%d: %s frame buffer device\n", fb->node, fb->fix.id);
+
+	/* set display interface */
+	aklcd_set_rgb_panel(rgb_panel, dev);
+
+	aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+	aklcd_set_power(true);
+	akfb->panel_refreshing = true;
+	akfb->bOv1ChnlOpened = false;
+	akfb->bOv2ChnlOpened = false;
+	akfb->bOsdChnlOpened = false;
+	akfb->tvout_mode = TVOUT_OFF;
+
+	ret = ak98fb_cpufreq_register(akfb);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "Failed to register cpufreq\n");
+	}
+
+	return 0;
+
+_probe_err3:
+	if (fb->cmap.len)
+		fb_dealloc_cmap(&fb->cmap);
+
+_probe_err2:
+	free_irq(irq, akfb);
+
+_probe_err1:
+	aklcd_disable();
+
+	if (rgbch_meminfo->vaddr)
+		dma_free_writecombine(dev, rgbch_meminfo->size, rgbch_meminfo->vaddr, rgbch_meminfo->paddr);
+	if (ov1ch_meminfo->vaddr)
+		dma_free_writecombine(dev, ov1ch_meminfo->size, ov1ch_meminfo->vaddr, ov1ch_meminfo->paddr);
+	if (ov2ch_meminfo->vaddr)
+		dma_free_writecombine(dev, ov2ch_meminfo->size, ov2ch_meminfo->vaddr, ov2ch_meminfo->paddr);
+	if (osdch_meminfo->vaddr)
+		dma_free_writecombine(dev, osdch_meminfo->size, osdch_meminfo->vaddr, osdch_meminfo->paddr);
+
+	framebuffer_release(fb);
+
+	return ret;
+}
+
+static int __devexit ak98fb_remove(struct platform_device *pdev)
+{
+	struct akfb    *akfb;
+	struct fb_info *fb;
+	struct device  *dev = &pdev->dev;
+	struct aklcd_channel_meminfo *rgbch_meminfo;
+	struct aklcd_channel_meminfo *ov1ch_meminfo;
+	struct aklcd_channel_meminfo *ov2ch_meminfo;
+	struct aklcd_channel_meminfo *osdch_meminfo;
+	int    irq;
+
+	akfb = platform_get_drvdata(pdev);
+	fb = akfb->fb;
+
+	rgbch_meminfo = &(akfb->rgbch_meminfo);
+	ov1ch_meminfo = &(akfb->ov1ch_meminfo);
+	ov2ch_meminfo = &(akfb->ov2ch_meminfo);
+	osdch_meminfo = &(akfb->osdch_meminfo);
+
+	unregister_framebuffer(fb);
+	if (fb->cmap.len)
+		fb_dealloc_cmap(&fb->cmap);
+
+	ak98fb_cpufreq_deregister(akfb);
+
+	irq = platform_get_irq(pdev, 0);
+	free_irq(irq, akfb);
+
+	aklcd_set_power(false);
+	aklcd_disable();
+
+	if (rgbch_meminfo->vaddr)
+		dma_free_writecombine(dev, rgbch_meminfo->size, rgbch_meminfo->vaddr, rgbch_meminfo->paddr);
+	if (ov1ch_meminfo->vaddr)
+		dma_free_writecombine(dev, ov1ch_meminfo->size, ov1ch_meminfo->vaddr, ov1ch_meminfo->paddr);
+	if (ov2ch_meminfo->vaddr)
+		dma_free_writecombine(dev, ov2ch_meminfo->size, ov2ch_meminfo->vaddr, ov2ch_meminfo->paddr);
+	if (osdch_meminfo->vaddr)
+		dma_free_writecombine(dev, osdch_meminfo->size, osdch_meminfo->vaddr, osdch_meminfo->paddr);
+
+	framebuffer_release(fb);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int ak98fb_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+	struct akfb  *akfb = platform_get_drvdata(pdev);
+	struct device   *dev = &(akfb->pdev->dev);
+
+	if (current_mode_is_low_mode()) 
+		return 0;
+	
+	acquire_console_sem();
+	akfb->bOv1ChnlOpened = aklcd_get_ov1_enable();
+	akfb->bOv2ChnlOpened = aklcd_get_ov2_enable();
+	akfb->bOsdChnlOpened = aklcd_get_osd_enable();
+	aklcd_close_rgb_channel();
+	aklcd_close_ov1_channel();
+	aklcd_close_ov2_channel();
+	aklcd_close_osd_channel();
+	aklcd_stop_refresh(akfb->if_type, dev);
+	aklcd_disable();
+	aklcd_set_power(false);
+	akfb->panel_refreshing = false;
+	release_console_sem();
+	
+	return 0;
+}
+
+static int ak98fb_resume(struct platform_device *pdev)
+{
+	struct akfb   *akfb = platform_get_drvdata(pdev);	
+	struct device   *dev = &(akfb->pdev->dev);
+
+	if (current_mode_is_low_mode())
+		return 0;
+	
+	acquire_console_sem();
+	aklcd_enable();
+	aklcd_set_screen(&(akfb->screen));
+	aklcd_set_rgb_channel(&(akfb->rgbch));
+	aklcd_open_rgb_channel();
+	aklcd_set_rgb_irq();
+	aklcd_set_rgb_panel(akfb->rgb_panel, dev);
+	aklcd_start_refresh(akfb->if_type, akfb->rgb_panel->pclk_freq, dev);
+
+	aklcd_set_power(true);
+	akfb->panel_refreshing = true;
+
+	if(akfb->bOv1ChnlOpened == true)
+	{
+		aklcd_set_ov1_channel(&(akfb->ov1ch));
+		aklcd_open_ov1_channel();
+	}
+	if(akfb->bOv2ChnlOpened == true)
+	{
+		aklcd_set_ov2_channel(&(akfb->ov2ch));
+		aklcd_open_ov2_channel();
+	}
+	if(akfb->bOsdChnlOpened == true)
+	{
+		aklcd_set_osd_channel(&(akfb->osdch));
+		aklcd_open_osd_channel();
+	}
+
+	if (akfb->panel_refreshing) {
+		init_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+		set_bit(AKLCD_CHANNEL_RGB, &(akfb->par_change_bits));
+		aklcd_enable_alert(true);
+		wait_for_completion(&(akfb->aklcd_setpar_comp[AKLCD_CHANNEL_RGB]));
+	}
+	release_console_sem();
+	
+	return 0;
+}
+#else
+#define ak98fb_suspend	NULL
+#define ak98fb_resume	NULL
+#endif
+
+static struct platform_driver ak98fb_driver = {
+	.probe		= ak98fb_probe,
+	.remove 	= __devexit_p(ak98fb_remove),
+	.suspend	= ak98fb_suspend,
+	.resume		= ak98fb_resume,
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "ak98-lcd",
+	},
+};
+
+static int __init ak98fb_init(void)
+{
+	pr_debug("+%s\n", __func__);
+	return platform_driver_register(&ak98fb_driver);
+}
+
+static void __exit ak98fb_exit(void)
+{
+	pr_debug("+%s\n", __func__);
+	platform_driver_unregister(&ak98fb_driver);
+}
+
+module_init(ak98fb_init);
+module_exit(ak98fb_exit);
+
+MODULE_DESCRIPTION("loadable framebuffer driver for AK98");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/ak98fb.h b/drivers/video/ak98fb.h
new file mode 100755
index 00000000000..9b6799eea89
--- /dev/null
+++ b/drivers/video/ak98fb.h
@@ -0,0 +1,278 @@
+#ifndef __AK98FB_H__
+#define __AK98FB_H__
+
+#include <linux/fb.h>
+
+#include <asm/io.h>
+
+#include <mach/regs-lcd.h>
+
+/* each macro defined below can be used, I prefer the latter */
+#if 0
+
+#define clear_low_bits(val, len)        (((len)==sizeof(val)*8)?0:((val) >> (len) << (len)))
+#define mask(msb, lsb)                  clear_low_bits(~clear_low_bits(~0UL, (msb+1)), (lsb))
+
+#else
+
+#define clear_low_bits(val, len)        ((val) >> (len) << (len))
+#define clear_high_bits(val, len)       ((val) << (len) >> (len))
+#define mask(msb, lsb)                  clear_high_bits(clear_low_bits(~0UL, (lsb)), (sizeof(~0UL)*8 - 1 - (msb)))
+
+#endif
+
+#if 0
+
+#define lcd_set_reg(val, reg, msb, lsb) __raw_writel((__raw_readl(reg) & ~mask((msb), (lsb))) | (((val) & mask((msb)-(lsb), 0)) << (lsb)), \
+						     (reg))
+
+#else
+
+#define lcd_set_reg(val, reg, msb, lsb) __raw_writel((__raw_readl(reg) & ~mask((msb), (lsb))) | (((val) << (lsb)) & mask((msb), (lsb))), \
+						     (reg))
+
+#endif
+
+#define lcd_get_reg(reg, msb, lsb) ((__raw_readl(reg) & mask(msb, lsb)) >> lsb)
+
+/* tvout parameter */
+#define TV_XPAD 8
+#define TV_YPAD 4
+
+#define TV_NTSC_WIDTH 720
+#define TV_NTSC_HEIGHT 240
+#define TV_NTSC_DISP_WIDTH (TV_NTSC_WIDTH - TV_XPAD*2)
+#define TV_NTSC_DISP_HEIGHT (TV_NTSC_HEIGHT - TV_YPAD*2)
+#define TV_NTSC_DISP_LEFT  TV_XPAD
+#define TV_NTSC_DISP_TOP   TV_YPAD
+
+#define TV_PAL_WIDTH 720
+#define TV_PAL_HEIGHT 288
+#define TV_PAL_DISP_WIDTH (TV_PAL_WIDTH - TV_XPAD*2)
+#define TV_PAL_DISP_HEIGHT (TV_PAL_HEIGHT - TV_YPAD*2)
+#define TV_PAL_DISP_LEFT  TV_XPAD
+#define TV_PAL_DISP_TOP   TV_YPAD
+
+enum aklcd_if {
+	DISP_IF_MPU   = 0b01,
+	DISP_IF_RGB   = 0b10,
+	DISP_IF_TVOUT = 0b11
+};
+
+enum aklcd_panel_mode {
+	PANEL_INTERLEAVED = 0b0,
+	PANEL_PROGRESS    = 0b1
+};
+
+enum aklcd_data_width {
+	RGB8BITS  = 0b00,
+	RGB24BITS = 0b11
+};
+
+enum aklcd_data_seq {
+	SEQ_RGB = 0b0,
+	SEQ_BGR = 0b1
+};
+
+enum aklcd_tvunit {
+	TV_UNIT_TH   = 0b0,
+	TV_UNIT_PCLK = 0b1,
+};
+
+enum aklcd_signal_pol {
+	POL_NEGATIVE,
+	POL_POSITIVE
+};
+
+enum aklcd_cfmt {
+	AKLCD_RGB888 = 0b11,
+	AKLCD_BGR888 = 0b10,
+	AKLCD_RGB565 = 0b01,
+	AKLCD_BGR565 = 0b00
+};
+
+enum aklcd_yuv_range {
+	YUV_SHORT_RANGE = 0b0,
+	YUV_FULL_RANGE  = 0b1
+};
+
+enum aklcd_ov_alpha {
+	OV_TRANS_100 = 0x0,
+	OV_TRANS_87  = 0x1,
+	OV_TRANS_75  = 0x2,
+	OV_TRANS_62  = 0x3,
+	OV_TRANS_50  = 0x4,
+	OV_TRANS_37  = 0x5,
+	OV_TRANS_25  = 0x6,
+	OV_TRANS_12  = 0x7,
+	OV_TRANS_0   = 0xf
+};
+
+enum aklcd_osd_alpha {
+	OSD_TRANS_100 = 0x0,
+	OSD_TRANS_87  = 0x1,
+	OSD_TRANS_75  = 0x2,
+	OSD_TRANS_62  = 0x3,
+	OSD_TRANS_50  = 0x4,
+	OSD_TRANS_37  = 0x5,
+	OSD_TRANS_25  = 0x6,
+	OSD_TRANS_12  = 0x7,
+	OSD_TRANS_0   = 0x8
+};
+
+enum ak_tvout_mode{
+	TVOUT_OFF,
+	PAL,
+	NTSC
+};
+
+#define AKRGB(r, g, b) ((((r)&0xff) << 16) | (((g)&0xff) << 8)| ((b)&0xff))
+#define AKYUV(y, u, v) ((((y)&0xff) << 16) | (((u)&0xff) << 8)| ((v)&0xff))
+
+typedef int ak_color;
+
+#define AKLCD_HSCALER(w) (65536/((w)-1))
+#define AKLCD_VSCALER(h) (65536/(2*((h)-1)))
+
+struct aklcd_rgb_panel {
+	const char *name;
+
+	enum aklcd_panel_mode panel_mode;
+	enum aklcd_data_width data_width;
+	enum aklcd_data_seq   data_seq; /* valid when width is 8bits */
+
+	int thpw;
+	int thbp;
+	int thd;
+	int thfp;
+
+	int tvpw;
+	int tvbp;
+	int tvd;
+	int tvfp;
+	enum aklcd_tvunit tv_unit;
+
+	int pclk_freq;
+
+	enum aklcd_signal_pol pclk_pol;
+	enum aklcd_signal_pol hsync_pol;
+	enum aklcd_signal_pol vsync_pol;
+	enum aklcd_signal_pol vogate_pol;
+};
+
+struct aklcd_screen {
+	unsigned int width;
+	unsigned int height;
+	ak_color     bg_color;
+};
+
+struct aklcd_rgb_channel {
+	enum aklcd_cfmt format;
+	dma_addr_t      data_addr; /* physical address of RGB data */
+
+	bool            use_vpage;
+	unsigned int    vpage_width;
+	unsigned int    vpage_height;
+	unsigned int    virt_left;
+	unsigned int    virt_top;
+
+	unsigned int    disp_left;
+	unsigned int    disp_top;
+	unsigned int    width;
+	unsigned int    height;
+};
+
+struct aklcd_overlay_channel {
+	enum aklcd_yuv_range src_range; /* only apply to overlay1 */
+	dma_addr_t           y_addr;
+	dma_addr_t           u_addr;
+	dma_addr_t           v_addr;
+	unsigned int         src_width;
+	unsigned int         src_height;
+
+	bool                 use_vpage; /* only apply to overlay1 */
+	unsigned int         vpage_width;
+	unsigned int         vpage_height;
+	unsigned int         virt_left;
+	unsigned int         virt_top;
+
+	unsigned int         disp_left;
+	unsigned int         disp_top;
+	unsigned int         dst_width;
+	unsigned int         dst_height;
+
+	enum aklcd_ov_alpha  alpha; /* 0...7, 16, only apply to overlay2 */
+};
+
+typedef u16 aklcd_osd_color;	/* rgb565 */
+
+struct aklcd_osd_channel {
+	dma_addr_t           data_addr;
+
+	aklcd_osd_color      palette[16]; /* palette[0] is for transparency */
+
+	unsigned int         disp_left;
+	unsigned int         disp_top;
+	unsigned int         width;
+	unsigned int         height;
+
+	enum aklcd_osd_alpha alpha; /* 0...8 */
+};
+
+/* for framebuffer */
+enum {
+	AKLCD_CHANNEL_OSD,
+	AKLCD_CHANNEL_OV1,
+	AKLCD_CHANNEL_OV2,
+	AKLCD_CHANNEL_RGB,
+	AKLCD_CHANNEL_MAX
+};
+
+struct aklcd_channel_meminfo {
+	int        size;
+	dma_addr_t paddr;
+	void *     vaddr;
+};
+
+struct akfb {
+	struct platform_device       *pdev;
+	struct fb_info               *fb;
+
+	enum aklcd_if                if_type;
+	struct aklcd_rgb_panel       *rgb_panel;
+	enum ak_tvout_mode           tvout_mode;
+	struct aklcd_screen          screen;
+
+	struct aklcd_rgb_channel     rgbch;
+	struct aklcd_channel_meminfo rgbch_meminfo;
+
+	struct aklcd_overlay_channel ov1ch;  //params that hardware is working on
+	struct aklcd_overlay_channel ov1ch_new;  //params that passed down by ioctl
+	struct aklcd_overlay_channel ov1ch_saved; //params that passed down by ioctl when in tvout mode
+	struct aklcd_channel_meminfo ov1ch_meminfo;
+	bool   bOv1ChnlOpened;  //ov1 channel state when suspended
+
+	struct aklcd_overlay_channel ov2ch;  //params that hardware is working on
+	struct aklcd_overlay_channel ov2ch_new; //params that passed down by ioctl
+	struct aklcd_channel_meminfo ov2ch_meminfo;
+	bool   bOv2ChnlOpened;   //ov2 channel state when suspended
+
+	struct aklcd_osd_channel     osdch;  //params that hardware is working on
+	struct aklcd_osd_channel     osdch_new;  //params that passed down by ioctl
+	struct aklcd_channel_meminfo osdch_meminfo;
+	bool   bOsdChnlOpened;   //osd channel state when suspended
+
+	struct mutex                 aklcd_par_lock[AKLCD_CHANNEL_MAX];
+	unsigned long                par_change_bits;
+	struct completion            aklcd_setpar_comp[AKLCD_CHANNEL_MAX];
+
+	u32                          pseudo_palette[16];
+
+	bool                         panel_refreshing;
+
+#ifdef CONFIG_CPU_FREQ
+	struct notifier_block	freq_transition;
+#endif
+};
+
+#endif /* __AK98FB_H__ */
diff --git a/drivers/video/ak_logo.c b/drivers/video/ak_logo.c
new file mode 100644
index 00000000000..e6a37477157
--- /dev/null
+++ b/drivers/video/ak_logo.c
@@ -0,0 +1,4086 @@
+/* anyka logo, rgb565 480x272 */
+const unsigned int ak_logo_width = 480;
+const unsigned int ak_logo_height = 272;
+
+const unsigned short ak_logo[] = {
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
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+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
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+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
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+0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 
+};
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 09bfa9662e4..08c54a5dea8 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -148,6 +148,13 @@ config BACKLIGHT_GENERIC
 	  known as the Corgi backlight driver. If you have a Sharp Zaurus
 	  SL-C7xx, SL-Cxx00 or SL-6000x say y.
 
+config BACKLIGHT_AK98_PWM
+        tristate "AK98 PWM  Backlight Driver"
+	depends on BACKLIGHT_CLASS_DEVICE
+	default n
+	help
+	  Say y to enable the AK98 PWM backlight driver
+	  
 config BACKLIGHT_LOCOMO
 	tristate "Sharp LOCOMO LCD/Backlight Driver"
 	depends on BACKLIGHT_CLASS_DEVICE && SHARP_LOCOMO
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 9a405548874..6d66e9b3a95 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -28,4 +28,5 @@ obj-$(CONFIG_BACKLIGHT_SAHARA)	+= kb3886_bl.o
 obj-$(CONFIG_BACKLIGHT_WM831X)	+= wm831x_bl.o
 obj-$(CONFIG_BACKLIGHT_ADX)    += adx_bl.o
 obj-$(CONFIG_BACKLIGHT_ADP5520)	+= adp5520_bl.o
+obj-$(CONFIG_BACKLIGHT_AK98_PWM)	+= ak98pwm_bl.o
 
diff --git a/drivers/video/backlight/ak98pwm_bl.c b/drivers/video/backlight/ak98pwm_bl.c
new file mode 100644
index 00000000000..0431b49fcb3
--- /dev/null
+++ b/drivers/video/backlight/ak98pwm_bl.c
@@ -0,0 +1,193 @@
+

+/*

+ * linux/drivers/video/backlight/ak98pwm_bl.c

+ * 2011-4-13

+ * simple PWM based backlight control, board code has to setup

+ * 1) pin configuration so PWM waveforms can output

+ * 2) platform_data being correctly configured

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ */

+

+#include <linux/module.h>

+#include <linux/kernel.h>

+#include <linux/init.h>

+#include <linux/platform_device.h>

+#include <linux/fb.h>

+#include <linux/backlight.h>

+#include <linux/err.h>

+#include <linux/delay.h>

+

+#include <mach/pwm.h>

+

+

+//#define PWM_DEBUG

+

+#undef PDEBUG           /* undef it, just in case */

+#ifdef PWM_DEBUG

+# ifdef __KERNEL__

+/* This one if debugging is on, and kernel space */

+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)

+# else

+/* This one for user space */

+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)

+# endif

+#else

+# define PDEBUG(fmt, args...) /* not debugging: nothing */

+#endif

+

+

+

+static struct ak98_pwm *pwm_dev;

+

+static int pwm_backlight_update_status(struct backlight_device *bl)

+{	

+	int brightness = bl->props.brightness;

+	int max = bl->props.max_brightness;

+	unsigned short bt = brightness * pwm_dev->pwm_clk / max;

+

+	PDEBUG("Entering %s\n", __FUNCTION__);

+	PDEBUG("brightness: %d\n", brightness);

+	if (bl->props.power != FB_BLANK_UNBLANK)

+		brightness = 0;

+

+	if (bl->props.fb_blank != FB_BLANK_UNBLANK)

+		brightness = 0;

+

+	ak98_pwm_config(pwm_dev, bt ? bt:1, pwm_dev->pwm_clk - bt);

+	ak98_pwm_enable(pwm_dev);

+	

+	return 0;

+}

+

+static int pwm_backlight_get_brightness(struct backlight_device *bl)

+{

+	PDEBUG("Entering %s\n", __FUNCTION__);

+	return bl->props.brightness;

+}

+

+static struct backlight_ops pwm_backlight_ops = {

+	.update_status	= pwm_backlight_update_status,

+	.get_brightness	= pwm_backlight_get_brightness,

+};

+

+static int pwm_backlight_probe(struct platform_device *pdev)

+{

+	

+	struct ak98_platform_pwm_bl_data *data = pdev->dev.platform_data;

+	struct backlight_device *bl;

+	//struct pwm_bl_data *pb;

+	int ret;

+

+	pwm_dev = ak98_pwm_request(data->pwm_id);

+	if (pwm_dev == NULL)

+	{

+		dev_err(&pdev->dev, "failed to request pwm device\n");

+		return -EINVAL;

+	}

+		

+	if (!data) {

+		dev_err(&pdev->dev, "failed to find platform data\n");

+		return -EINVAL;

+	}

+

+	if (data->init) {

+		ret = data->init(pwm_dev);

+		if (ret < 0)

+			return ret;

+	}

+	

+	bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev,

+			NULL, &pwm_backlight_ops);

+	if (IS_ERR(bl)) {

+		dev_err(&pdev->dev, "failed to register backlight\n");

+		ret = PTR_ERR(bl);

+		goto err_bl;

+	}

+

+	bl->props.max_brightness = data->max_brightness;

+	bl->props.brightness = data->dft_brightness;

+	pwm_dev->pwm_clk = data->pwm_clk;

+	backlight_update_status(bl);

+	

+	platform_set_drvdata(pdev, bl);

+	return 0;

+

+err_bl:

+	if (data->exit)

+		data->exit(pwm_dev);

+	return ret;

+}

+

+static int pwm_backlight_remove(struct platform_device *pdev)

+{

+	struct ak98_platform_pwm_bl_data *data = pdev->dev.platform_data;

+	struct backlight_device *bl = platform_get_drvdata(pdev);

+

+	backlight_device_unregister(bl);

+	

+	if (data->exit)

+		data->exit(pwm_dev);

+	return 0;

+}

+

+#ifdef CONFIG_PM

+static int pwm_backlight_suspend(struct platform_device *pdev,

+				 pm_message_t state)

+{

+	//struct backlight_device *bl = platform_get_drvdata(pdev);

+	

+	ak98_pwm_config(pwm_dev, 0, 0);

+	ak98_pwm_disable(pwm_dev);

+	

+	return 0;

+}

+

+static int pwm_backlight_resume(struct platform_device *pdev)

+{

+	struct backlight_device *bl = platform_get_drvdata(pdev);

+

+	backlight_update_status(bl);

+	return 0;

+}

+#else

+#define pwm_backlight_suspend	NULL

+#define pwm_backlight_resume	NULL

+#endif

+

+static struct platform_driver ak98pwm_backlight_driver = {

+	.driver		= {

+		.name	= "ak98pwm-backlight",

+		.owner	= THIS_MODULE,

+	},

+	.probe		= pwm_backlight_probe,

+	.remove		= pwm_backlight_remove,

+	.suspend	= pwm_backlight_suspend,

+	.resume		= pwm_backlight_resume,

+};

+

+static int __init pwm_backlight_init(void)

+{

+	PDEBUG("AK98 PWM Backlight Driver!\n");

+	

+	return platform_driver_register(&ak98pwm_backlight_driver);

+}

+module_init(pwm_backlight_init);

+

+static void __exit pwm_backlight_exit(void)

+{

+	platform_driver_unregister(&ak98pwm_backlight_driver);

+}

+module_exit(pwm_backlight_exit);

+

+MODULE_DESCRIPTION("AK98 PWM based Backlight Driver");

+MODULE_LICENSE("GPL");

+MODULE_ALIAS("platform:ak98pwm-backlight");

+

+

+

+

+

+

diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c
index 6615ac7fa60..efc8f79c67d 100644
--- a/drivers/video/backlight/backlight.c
+++ b/drivers/video/backlight/backlight.c
@@ -13,6 +13,7 @@
 #include <linux/ctype.h>
 #include <linux/err.h>
 #include <linux/fb.h>
+#include <linux/anyka_cpufreq.h>
 
 #ifdef CONFIG_PMAC_BACKLIGHT
 #include <asm/backlight.h>
@@ -29,9 +30,11 @@ static int fb_notifier_callback(struct notifier_block *self,
 {
 	struct backlight_device *bd;
 	struct fb_event *evdata = data;
+	static int brightness = 0;
 
 	/* If we aren't interested in this event, skip it immediately ... */
-	if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
+	if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK
+		&& event != FB_EVENT_PRE_CPUFREQ && event != FB_EVENT_POST_CPUFREQ)
 		return 0;
 
 	bd = container_of(self, struct backlight_device, fb_notif);
@@ -39,12 +42,24 @@ static int fb_notifier_callback(struct notifier_block *self,
 	if (bd->ops)
 		if (!bd->ops->check_fb ||
 		    bd->ops->check_fb(evdata->info)) {
-			bd->props.fb_blank = *(int *)evdata->data;
-			if (bd->props.fb_blank == FB_BLANK_UNBLANK)
-				bd->props.state &= ~BL_CORE_FBBLANK;
-			else
-				bd->props.state |= BL_CORE_FBBLANK;
-			backlight_update_status(bd);
+		    if (event == FB_EVENT_PRE_CPUFREQ) {
+				brightness = bd->props.brightness;
+				bd->props.brightness = 0;
+				backlight_update_status(bd);
+		    } else if (event == FB_EVENT_POST_CPUFREQ) {
+				if (!previous_mode_is_low_mode()) {
+					bd->props.brightness = brightness;
+					brightness = 0;
+		    	}
+				backlight_update_status(bd);
+		    } else {
+				bd->props.fb_blank = *(int *)evdata->data;
+				if (bd->props.fb_blank == FB_BLANK_UNBLANK)
+					bd->props.state &= ~BL_CORE_FBBLANK;
+				else
+					bd->props.state |= BL_CORE_FBBLANK;
+				backlight_update_status(bd);
+		    }
 		}
 	mutex_unlock(&bd->ops_lock);
 	return 0;
diff --git a/drivers/video/console/bitblit.c b/drivers/video/console/bitblit.c
index 6b7c8fbc549..e50aaf279bf 100644
--- a/drivers/video/console/bitblit.c
+++ b/drivers/video/console/bitblit.c
@@ -382,8 +382,10 @@ static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode,
 	if (info->fbops->fb_cursor)
 		err = info->fbops->fb_cursor(info, &cursor);
 
+#if 0 /* !!! in anyka platform, in something situation cursor will display, this's a workaround */
 	if (err)
 		soft_cursor(info, &cursor);
+#endif
 
 	ops->cursor_reset = 0;
 }
diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c
index acc7e3b7fe1..db7b6198f15 100644
--- a/drivers/w1/w1.c
+++ b/drivers/w1/w1.c
@@ -517,10 +517,10 @@ static W1_MASTER_ATTR_RO(max_slave_count, S_IRUGO);
 static W1_MASTER_ATTR_RO(attempts, S_IRUGO);
 static W1_MASTER_ATTR_RO(timeout, S_IRUGO);
 static W1_MASTER_ATTR_RO(pointer, S_IRUGO);
-static W1_MASTER_ATTR_RW(search, S_IRUGO | S_IWUGO);
-static W1_MASTER_ATTR_RW(pullup, S_IRUGO | S_IWUGO);
-static W1_MASTER_ATTR_RW(add, S_IRUGO | S_IWUGO);
-static W1_MASTER_ATTR_RW(remove, S_IRUGO | S_IWUGO);
+static W1_MASTER_ATTR_RW(search, S_IRUGO | S_IWUSR | S_IWGRP);
+static W1_MASTER_ATTR_RW(pullup, S_IRUGO | S_IWUSR | S_IWGRP);
+static W1_MASTER_ATTR_RW(add, S_IRUGO | S_IWUSR | S_IWGRP);
+static W1_MASTER_ATTR_RW(remove, S_IRUGO | S_IWUSR | S_IWGRP);
 
 static struct attribute *w1_master_default_attrs[] = {
 	&w1_master_attribute_name.attr,
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 3711b888d48..a8fe67cd541 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -289,6 +289,12 @@ config ADX_WATCHDOG
 	  Say Y here if you want support for the watchdog timer on Avionic
 	  Design Xanthos boards.
 
+config AK98_WATCHDOG
+	tristate "ANYKA ak98 watchdog"
+	depends on ARCH_AK98
+	help
+	  Say Y here if you want support for the watchdog timer on ANYKA ak98 boards.
+	  
 # AVR32 Architecture
 
 config AT32AP700X_WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 699199b1baa..5ee208f0faa 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -46,6 +46,8 @@ obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
 obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o
 obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o
 obj-$(CONFIG_ADX_WATCHDOG) += adx_wdt.o
+obj-$(CONFIG_AK98_WATCHDOG) += ak98_wdt.o
+
 
 # AVR32 Architecture
 obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
diff --git a/drivers/watchdog/ak98_wdt.c b/drivers/watchdog/ak98_wdt.c
new file mode 100644
index 00000000000..f181f3ce977
--- /dev/null
+++ b/drivers/watchdog/ak98_wdt.c
@@ -0,0 +1,321 @@
+/*

+ * drivers/char/watchdog/ak98_wdt.c

+ *

+ * Watchdog driver for ANYKA ak98 processors

+ *

+ * Author: Wenyong Zhou

+ *

+ * Adapted from the IXP2000 watchdog driver by Lennert Buytenhek.

+ * The original version carries these notices:

+ *

+ * Author: Deepak Saxena <dsaxena@plexity.net>

+ *

+ * Copyright 2004 (c) MontaVista, Software, Inc.

+ * Based on sa1100 driver, Copyright (C) 2000 Oleg Drokin <green@crimea.edu>

+ *

+ * This file is licensed under  the terms of the GNU General Public

+ * License version 2. This program is licensed "as is" without any

+ * warranty of any kind, whether express or implied.

+ */

+

+#include <linux/module.h>

+#include <linux/moduleparam.h>

+#include <linux/types.h>

+#include <linux/kernel.h>

+#include <linux/fs.h>

+#include <linux/miscdevice.h>

+#include <linux/watchdog.h>

+#include <linux/init.h>

+#include <linux/bitops.h>

+#include <linux/uaccess.h>

+#include <mach/hardware.h>

+

+#include <mach/rtc.h>

+

+

+static int nowayout = WATCHDOG_NOWAYOUT;

+static unsigned int heartbeat = (0x1FFF - 1);	/* (secs) Default is 8091ms */

+static unsigned long wdt_status;

+static spinlock_t wdt_lock;

+

+#define	WDT_IN_USE		0

+#define	WDT_OK_TO_CLOSE		1

+

+//static unsigned long wdt_tick_rate;

+#undef REG32

+#define REG32(_reg_)  (*(volatile unsigned long *)(_reg_))

+

+#define SELECT_WTC 1

+#define SELECT_RTC 0

+

+//#define WDT_DEBUG

+

+#undef PDEBUG           /* undef it, just in case */

+#ifdef WDT_DEBUG

+# ifdef __KERNEL__

+/* This one if debugging is on, and kernel space */

+# define PDEBUG(fmt, args...) printk( KERN_INFO fmt,## args)

+# else

+/* This one for user space */

+# define PDEBUG(fmt, args...) fprintf(stderr, "%s %d: "fmt,__FILE__, __LINE__, ## args)

+# endif

+#else

+# define PDEBUG(fmt, args...) /* not debugging: nothing */

+#endif

+

+

+static int select_wdt(int which)

+{

+	unsigned long val;

+	int ret;

+

+	val = ak98_rtc_read(AK98_RTC_SETTING);

+	ret = val | (1 << 10);	

+	if (which == 0)

+		val &= ~(1 << 10);		

+	else

+		val |= (which << 10);

+	

+	

+	ak98_rtc_write(AK98_RTC_SETTING, val);

+	return ret;

+}

+static void wdt_enable(void)

+{

+	unsigned long val;

+	int pre;

+	PDEBUG("%s......\n", __FUNCTION__);

+	spin_lock(&wdt_lock);	

+	pre = select_wdt(SELECT_WTC);

+

+	//enable watchdog timer

+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);

+	val |= (1<<13);

+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);

+

+	//set timer

+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);

+	val &= (1<<13);

+	val |= (heartbeat & 0x1FFF);

+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);

+

+	//open watchdog and watchdog output

+	val = ak98_rtc_read(AK98_RTC_SETTING);

+	val |= ((1<<5) | (1<<2));

+	ak98_rtc_write(AK98_RTC_SETTING, val);	

+	select_wdt(pre);

+	spin_unlock(&wdt_lock);

+}

+

+static void wdt_disable(void)

+{

+	unsigned long val;

+	int pre;

+	

+	spin_lock(&wdt_lock);

+	pre = select_wdt(SELECT_WTC);

+	//clear watchdog timer

+	val = ak98_rtc_read(AK98_RTC_SETTING);

+	val |= (1<<6);

+	ak98_rtc_write(AK98_RTC_SETTING, val);

+

+	//disable watchdog timer

+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);

+	val &= ~(1<<13);

+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);

+

+	//close watchdog and watchdog output

+	val = ak98_rtc_read(AK98_RTC_SETTING);

+	val &= ~((1<<2) | (1<<5));

+	ak98_rtc_write(AK98_RTC_SETTING, val);

+	

+	select_wdt(pre);	

+	spin_unlock(&wdt_lock);

+}

+

+static void wdt_keepalive(void)

+{

+	unsigned long val;

+	int pre;

+	PDEBUG("%s......\n", __FUNCTION__);

+	spin_lock(&wdt_lock);

+

+	pre = select_wdt(SELECT_WTC);

+

+	//clear watchdog timer

+	val = ak98_rtc_read(AK98_RTC_SETTING);

+	val |= (1<<6);

+	ak98_rtc_write(AK98_RTC_SETTING, val);

+

+

+	val = ak98_rtc_read(AK98_WDT_RTC_TIMER_CONF);

+	val &= (1<<13);

+	val |= (heartbeat & 0x1FFF);

+	ak98_rtc_write(AK98_WDT_RTC_TIMER_CONF, val);

+

+	select_wdt(pre);

+	spin_unlock(&wdt_lock);

+}

+

+static int ak98_wdt_open(struct inode *inode, struct file *file)

+{

+	PDEBUG("%s......\n", __FUNCTION__);

+	if (test_and_set_bit(WDT_IN_USE, &wdt_status))

+		return -EBUSY;

+

+	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

+

+	wdt_enable();

+

+	return nonseekable_open(inode, file);

+}

+

+static ssize_t ak98_wdt_write(struct file *file, const char *data,

+						size_t len, loff_t *ppos)

+{

+	PDEBUG("wdt write: %s  %d\n", data, len);

+	if (len) {

+		if (!nowayout) {

+			size_t i;

+

+			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

+

+			for (i = 0; i != len; i++) {

+				char c;

+

+				if (get_user(c, data + i))

+					return -EFAULT;

+				if (c == 'V')

+					set_bit(WDT_OK_TO_CLOSE, &wdt_status);

+			}

+		}

+		wdt_keepalive();

+	}

+

+	return len;

+}

+

+

+static struct watchdog_info ident = {

+	.options	= WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |

+				WDIOF_KEEPALIVEPING,

+	.identity	= "ANYKA ak98 Watchdog",

+};

+

+static long ak98_wdt_ioctl(struct file *file, unsigned int cmd,

+							unsigned long arg)

+{

+	int ret = -ENOTTY;

+	int time;

+

+	switch (cmd) {

+	case WDIOC_GETSUPPORT:

+		ret = copy_to_user((struct watchdog_info *)arg, &ident,

+				   sizeof(ident)) ? -EFAULT : 0;

+		break;

+

+	case WDIOC_GETSTATUS:

+		ret = put_user(0, (int *)arg);

+		break;

+

+	case WDIOC_GETBOOTSTATUS:

+		ret = put_user(0, (int *)arg);

+		break;

+

+	case WDIOC_KEEPALIVE:

+		wdt_enable();

+		ret = 0;

+		break;

+

+	case WDIOC_SETTIMEOUT:

+		ret = get_user(time, (int *)arg);

+		if (ret)

+			break;

+

+		if (time <= 0 || time > 8) {

+			ret = -EINVAL;

+			break;

+		}

+		if (time == 8)

+			heartbeat = 0x1FFF - 1;

+		else

+			heartbeat = time * 1024;

+		wdt_keepalive();

+		/* Fall through */

+

+	case WDIOC_GETTIMEOUT:

+		ret = put_user(heartbeat/1024, (int *)arg);

+		break;

+	}

+

+	return ret;

+}

+

+static int ak98_wdt_release(struct inode *inode, struct file *file)

+{

+	PDEBUG("%s......\n", __FUNCTION__);

+

+	if (test_bit(WDT_OK_TO_CLOSE, &wdt_status))

+		wdt_disable();

+	else

+		printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - "

+					"timer will not stop\n");

+	clear_bit(WDT_IN_USE, &wdt_status);

+	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

+	

+	return 0;

+}

+

+

+static const struct file_operations ak98_wdt_fops = {

+	.owner		= THIS_MODULE,

+	.llseek		= no_llseek,

+	.write		= ak98_wdt_write,

+	.unlocked_ioctl	= ak98_wdt_ioctl,

+	.open		= ak98_wdt_open,

+	.release	= ak98_wdt_release,

+};

+

+static struct miscdevice ak98_wdt_miscdev = {

+	.minor		= WATCHDOG_MINOR,

+	.name		= "watchdog",

+	.fops		= &ak98_wdt_fops,

+};

+

+static int __init ak98_wdt_init(void)

+{		

+	spin_lock_init(&wdt_lock);

+	PDEBUG("%s......\n", __FUNCTION__);

+	wdt_status = 0;

+	

+	spin_lock(&wdt_lock);

+	ak98_rtc_power(RTC_ON);

+	spin_unlock(&wdt_lock);	

+	

+	return misc_register(&ak98_wdt_miscdev);

+}

+

+static void __exit ak98_wdt_exit(void)

+{

+	spin_lock(&wdt_lock);

+

+	ak98_rtc_power(RTC_OFF);

+	spin_unlock(&wdt_lock);	

+	misc_deregister(&ak98_wdt_miscdev);

+}

+

+module_init(ak98_wdt_init);

+module_exit(ak98_wdt_exit);

+

+

+MODULE_DESCRIPTION("ANYKA ak98 Watchdog");

+

+module_param(heartbeat, int, 0);

+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default 60s)");

+

+module_param(nowayout, int, 0);

+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");

+

+MODULE_LICENSE("GPL");

+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);

+

diff --git a/fs/Kconfig b/fs/Kconfig
index 64d44efad7a..55306d0214e 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -174,6 +174,10 @@ source "fs/hfsplus/Kconfig"
 source "fs/befs/Kconfig"
 source "fs/bfs/Kconfig"
 source "fs/efs/Kconfig"
+
+# Patched by YAFFS
+source "fs/yaffs2/Kconfig"
+
 source "fs/jffs2/Kconfig"
 # UBIFS File system configuration
 source "fs/ubifs/Kconfig"
diff --git a/fs/Makefile b/fs/Makefile
index af6d04700d9..b419c75e1d8 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -124,3 +124,6 @@ obj-$(CONFIG_OCFS2_FS)		+= ocfs2/
 obj-$(CONFIG_BTRFS_FS)		+= btrfs/
 obj-$(CONFIG_GFS2_FS)           += gfs2/
 obj-$(CONFIG_EXOFS_FS)          += exofs/
+
+# Patched by YAFFS
+obj-$(CONFIG_YAFFS_FS)		+= yaffs2/
diff --git a/fs/fat/dir.c b/fs/fat/dir.c
index 530b4ca0151..4ceff511041 100644
--- a/fs/fat/dir.c
+++ b/fs/fat/dir.c
@@ -758,6 +758,13 @@ static int fat_ioctl_readdir(struct inode *inode, struct file *filp,
 	return ret;
 }
 
+static int fat_ioctl_volume_id(struct inode *dir)
+{
+	struct super_block *sb = dir->i_sb;
+	struct msdos_sb_info *sbi = MSDOS_SB(sb);
+	return sbi->vol_id;
+}
+
 static int fat_dir_ioctl(struct inode *inode, struct file *filp,
 			 unsigned int cmd, unsigned long arg)
 {
@@ -773,6 +780,8 @@ static int fat_dir_ioctl(struct inode *inode, struct file *filp,
 		short_only = 0;
 		both = 1;
 		break;
+	case VFAT_IOCTL_GET_VOLUME_ID:
+		return fat_ioctl_volume_id(inode);
 	default:
 		return fat_generic_ioctl(inode, filp, cmd, arg);
 	}
diff --git a/fs/fat/fat.h b/fs/fat/fat.h
index 7db0979c6b7..4e25637d2b2 100644
--- a/fs/fat/fat.h
+++ b/fs/fat/fat.h
@@ -76,6 +76,7 @@ struct msdos_sb_info {
 	const void *dir_ops;		     /* Opaque; default directory operations */
 	int dir_per_block;	     /* dir entries per block */
 	int dir_per_block_bits;	     /* log2(dir_per_block) */
+	unsigned long vol_id;        /* volume ID */
 
 	int fatent_shift;
 	struct fatent_operations *fatent_ops;
diff --git a/fs/fat/inode.c b/fs/fat/inode.c
index 76b7961ab66..81261eb3215 100644
--- a/fs/fat/inode.c
+++ b/fs/fat/inode.c
@@ -1215,6 +1215,7 @@ int fat_fill_super(struct super_block *sb, void *data, int silent,
 	struct inode *root_inode = NULL, *fat_inode = NULL;
 	struct buffer_head *bh;
 	struct fat_boot_sector *b;
+	struct fat_boot_bsx *bsx;
 	struct msdos_sb_info *sbi;
 	u16 logical_sector_size;
 	u32 total_sectors, total_clusters, fat_clusters, rootdir_sectors;
@@ -1357,6 +1358,8 @@ int fat_fill_super(struct super_block *sb, void *data, int silent,
 			goto out_fail;
 		}
 
+		bsx = (struct fat_boot_bsx *)(bh->b_data + FAT32_BSX_OFFSET);
+
 		fsinfo = (struct fat_boot_fsinfo *)fsinfo_bh->b_data;
 		if (!IS_FSINFO(fsinfo)) {
 			printk(KERN_WARNING "FAT: Invalid FSINFO signature: "
@@ -1372,8 +1375,14 @@ int fat_fill_super(struct super_block *sb, void *data, int silent,
 		}
 
 		brelse(fsinfo_bh);
+	} else {
+		bsx = (struct fat_boot_bsx *)(bh->b_data + FAT16_BSX_OFFSET);
 	}
 
+	/* interpret volume ID as a little endian 32 bit integer */
+	sbi->vol_id = (((u32)bsx->vol_id[0]) | ((u32)bsx->vol_id[1] << 8) |
+		((u32)bsx->vol_id[2] << 16) | ((u32)bsx->vol_id[3] << 24));
+
 	sbi->dir_per_block = sb->s_blocksize / sizeof(struct msdos_dir_entry);
 	sbi->dir_per_block_bits = ffs(sbi->dir_per_block) - 1;
 
diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c
index 9d5360c4c2a..b1ff16fec7f 100644
--- a/fs/fs-writeback.c
+++ b/fs/fs-writeback.c
@@ -1071,7 +1071,7 @@ void __mark_inode_dirty(struct inode *inode, int flags)
 	if ((inode->i_state & flags) == flags)
 		return;
 
-	if (unlikely(block_dump))
+	if (unlikely(block_dump > 1))
 		block_dump___mark_inode_dirty(inode);
 
 	spin_lock(&inode_lock);
diff --git a/fs/partitions/check.c b/fs/partitions/check.c
index 7b685e10cba..5689a0a889a 100644
--- a/fs/partitions/check.c
+++ b/fs/partitions/check.c
@@ -327,10 +327,19 @@ static void part_release(struct device *dev)
 	kfree(p);
 }
 
+static int part_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+	struct hd_struct *part = dev_to_part(dev);
+
+	add_uevent_var(env, "PARTN=%u", part->partno);
+	return 0;
+}
+
 struct device_type part_type = {
 	.name		= "partition",
 	.groups		= part_attr_groups,
 	.release	= part_release,
+	.uevent		= part_uevent,
 };
 
 static void delete_partition_rcu_cb(struct rcu_head *head)
diff --git a/fs/proc/base.c b/fs/proc/base.c
index af643b5aefe..d7367affea2 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -128,6 +128,12 @@ struct pid_entry {
 		NULL, &proc_single_file_operations,	\
 		{ .proc_show = show } )
 
+/* ANDROID is for special files in /proc. */
+#define ANDROID(NAME, MODE, OTYPE)			\
+	NOD(NAME, (S_IFREG|(MODE)),			\
+		&proc_##OTYPE##_inode_operations,	\
+		&proc_##OTYPE##_operations, {})
+
 /*
  * Count the number of hardlinks for the pid_entry table, excluding the .
  * and .. links.
@@ -241,7 +247,8 @@ struct mm_struct *mm_for_maps(struct task_struct *task)
 
 	mm = get_task_mm(task);
 	if (mm && mm != current->mm &&
-			!ptrace_may_access(task, PTRACE_MODE_READ)) {
+			!ptrace_may_access(task, PTRACE_MODE_READ) &&
+			!capable(CAP_SYS_RESOURCE)) {
 		mmput(mm);
 		mm = NULL;
 	}
@@ -1061,6 +1068,33 @@ static ssize_t oom_adjust_write(struct file *file, const char __user *buf,
 	return count;
 }
 
+static int oom_adjust_permission(struct inode *inode, int mask)
+{
+	uid_t uid;
+	struct task_struct *p = get_proc_task(inode);
+	if(p) {
+		uid = task_uid(p);
+		put_task_struct(p);
+	}
+
+	/*
+	 * System Server (uid == 1000) is granted access to oom_adj of all 
+	 * android applications (uid > 10000) as and services (uid >= 1000)
+	 */
+	if (p && (current_fsuid() == 1000) && (uid >= 1000)) {
+		if (inode->i_mode >> 6 & mask) {
+			return 0;
+		}
+	}
+
+	/* Fall back to default. */
+	return generic_permission(inode, mask, NULL);
+}
+
+static const struct inode_operations proc_oom_adjust_inode_operations = {
+	.permission	= oom_adjust_permission,
+};
+
 static const struct file_operations proc_oom_adjust_operations = {
 	.read		= oom_adjust_read,
 	.write		= oom_adjust_write,
@@ -2548,7 +2582,7 @@ static const struct pid_entry tgid_base_stuff[] = {
 	REG("cgroup",  S_IRUGO, proc_cgroup_operations),
 #endif
 	INF("oom_score",  S_IRUGO, proc_oom_score),
-	REG("oom_adj",    S_IRUGO|S_IWUSR, proc_oom_adjust_operations),
+	ANDROID("oom_adj",S_IRUGO|S_IWUSR, oom_adjust),
 #ifdef CONFIG_AUDITSYSCALL
 	REG("loginuid",   S_IWUSR|S_IRUGO, proc_loginuid_operations),
 	REG("sessionid",  S_IRUGO, proc_sessionid_operations),
diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 2a1bef9203c..8e5fae2f7ae 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -404,6 +404,7 @@ static int show_smap(struct seq_file *m, void *v)
 
 	memset(&mss, 0, sizeof mss);
 	mss.vma = vma;
+	/* mmap_sem is held in m_start */
 	if (vma->vm_mm && !is_vm_hugetlb_page(vma))
 		walk_page_range(vma->vm_start, vma->vm_end, &smaps_walk);
 
@@ -550,7 +551,8 @@ const struct file_operations proc_clear_refs_operations = {
 };
 
 struct pagemapread {
-	u64 __user *out, *end;
+	int pos, len;
+	u64 *buffer;
 };
 
 #define PM_ENTRY_BYTES      sizeof(u64)
@@ -573,10 +575,8 @@ struct pagemapread {
 static int add_to_pagemap(unsigned long addr, u64 pfn,
 			  struct pagemapread *pm)
 {
-	if (put_user(pfn, pm->out))
-		return -EFAULT;
-	pm->out++;
-	if (pm->out >= pm->end)
+	pm->buffer[pm->pos++] = pfn;
+	if (pm->pos >= pm->len)
 		return PM_END_OF_BUFFER;
 	return 0;
 }
@@ -674,21 +674,20 @@ static int pagemap_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end,
  * determine which areas of memory are actually mapped and llseek to
  * skip over unmapped regions.
  */
+#define PAGEMAP_WALK_SIZE	(PMD_SIZE)
 static ssize_t pagemap_read(struct file *file, char __user *buf,
 			    size_t count, loff_t *ppos)
 {
 	struct task_struct *task = get_proc_task(file->f_path.dentry->d_inode);
-	struct page **pages, *page;
-	unsigned long uaddr, uend;
 	struct mm_struct *mm;
 	struct pagemapread pm;
-	int pagecount;
 	int ret = -ESRCH;
 	struct mm_walk pagemap_walk = {};
 	unsigned long src;
 	unsigned long svpfn;
 	unsigned long start_vaddr;
 	unsigned long end_vaddr;
+	int copied = 0;
 
 	if (!task)
 		goto out;
@@ -711,35 +710,12 @@ static ssize_t pagemap_read(struct file *file, char __user *buf,
 	if (!mm)
 		goto out_task;
 
-
-	uaddr = (unsigned long)buf & PAGE_MASK;
-	uend = (unsigned long)(buf + count);
-	pagecount = (PAGE_ALIGN(uend) - uaddr) / PAGE_SIZE;
-	ret = 0;
-	if (pagecount == 0)
-		goto out_mm;
-	pages = kcalloc(pagecount, sizeof(struct page *), GFP_KERNEL);
+	pm.len = PM_ENTRY_BYTES * (PAGEMAP_WALK_SIZE >> PAGE_SHIFT);
+	pm.buffer = kmalloc(pm.len, GFP_TEMPORARY);
 	ret = -ENOMEM;
-	if (!pages)
+	if (!pm.buffer)
 		goto out_mm;
 
-	down_read(&current->mm->mmap_sem);
-	ret = get_user_pages(current, current->mm, uaddr, pagecount,
-			     1, 0, pages, NULL);
-	up_read(&current->mm->mmap_sem);
-
-	if (ret < 0)
-		goto out_free;
-
-	if (ret != pagecount) {
-		pagecount = ret;
-		ret = -EFAULT;
-		goto out_pages;
-	}
-
-	pm.out = (u64 __user *)buf;
-	pm.end = (u64 __user *)(buf + count);
-
 	pagemap_walk.pmd_entry = pagemap_pte_range;
 	pagemap_walk.pte_hole = pagemap_pte_hole;
 	pagemap_walk.mm = mm;
@@ -760,23 +736,36 @@ static ssize_t pagemap_read(struct file *file, char __user *buf,
 	 * user buffer is tracked in "pm", and the walk
 	 * will stop when we hit the end of the buffer.
 	 */
-	ret = walk_page_range(start_vaddr, end_vaddr, &pagemap_walk);
-	if (ret == PM_END_OF_BUFFER)
-		ret = 0;
-	/* don't need mmap_sem for these, but this looks cleaner */
-	*ppos += (char __user *)pm.out - buf;
-	if (!ret)
-		ret = (char __user *)pm.out - buf;
-
-out_pages:
-	for (; pagecount; pagecount--) {
-		page = pages[pagecount-1];
-		if (!PageReserved(page))
-			SetPageDirty(page);
-		page_cache_release(page);
+	ret = 0;
+	while (count && (start_vaddr < end_vaddr)) {
+		int len;
+		unsigned long end;
+
+		pm.pos = 0;
+		end = start_vaddr + PAGEMAP_WALK_SIZE;
+		/* overflow ? */
+		if (end < start_vaddr || end > end_vaddr)
+			end = end_vaddr;
+		down_read(&mm->mmap_sem);
+		ret = walk_page_range(start_vaddr, end, &pagemap_walk);
+		up_read(&mm->mmap_sem);
+		start_vaddr = end;
+
+		len = min(count, PM_ENTRY_BYTES * pm.pos);
+		if (copy_to_user(buf, pm.buffer, len) < 0) {
+			ret = -EFAULT;
+			goto out_free;
+		}
+		copied += len;
+		buf += len;
+		count -= len;
 	}
+	*ppos += copied;
+	if (!ret || ret == PM_END_OF_BUFFER)
+		ret = copied;
+
 out_free:
-	kfree(pages);
+	kfree(pm.buffer);
 out_mm:
 	mmput(mm);
 out_task:
diff --git a/fs/yaffs2/Kconfig b/fs/yaffs2/Kconfig
new file mode 100644
index 00000000000..85844504057
--- /dev/null
+++ b/fs/yaffs2/Kconfig
@@ -0,0 +1,164 @@
+#
+# YAFFS file system configurations
+#
+
+config YAFFS_FS
+	tristate "YAFFS2 file system support"
+	default n
+	depends on MTD_BLOCK
+	select YAFFS_YAFFS1
+	select YAFFS_YAFFS2
+	help
+	  YAFFS2, or Yet Another Flash Filing System, is a filing system
+	  optimised for NAND Flash chips.
+
+	  To compile the YAFFS2 file system support as a module, choose M
+	  here: the module will be called yaffs2.
+
+	  If unsure, say N.
+
+	  Further information on YAFFS2 is available at
+	  <http://www.aleph1.co.uk/yaffs/>.
+
+config YAFFS_YAFFS1
+	bool "512 byte / page devices"
+	depends on YAFFS_FS
+	default y
+	help
+	  Enable YAFFS1 support -- yaffs for 512 byte / page devices
+
+	  Not needed for 2K-page devices.
+
+	  If unsure, say Y.
+
+config YAFFS_9BYTE_TAGS
+	bool "Use older-style on-NAND data format with pageStatus byte"
+	depends on YAFFS_YAFFS1
+	default n
+	help
+
+	  Older-style on-NAND data format has a "pageStatus" byte to record
+	  chunk/page state.  This byte is zero when the page is discarded.
+	  Choose this option if you have existing on-NAND data using this
+	  format that you need to continue to support.  New data written
+	  also uses the older-style format.  Note: Use of this option
+	  generally requires that MTD's oob layout be adjusted to use the
+	  older-style format.  See notes on tags formats and MTD versions
+	  in yaffs_mtdif1.c.
+
+	  If unsure, say N.
+
+config YAFFS_DOES_ECC
+	bool "Lets Yaffs do its own ECC"
+	depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS
+	default n
+	help
+	  This enables Yaffs to use its own ECC functions instead of using
+	  the ones from the generic MTD-NAND driver.
+
+	  If unsure, say N.
+
+config YAFFS_ECC_WRONG_ORDER
+	bool "Use the same ecc byte order as Steven Hill's nand_ecc.c"
+	depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS
+	default n
+	help
+	  This makes yaffs_ecc.c use the same ecc byte order as Steven
+	  Hill's nand_ecc.c. If not set, then you get the same ecc byte
+	  order as SmartMedia.
+
+	  If unsure, say N.
+
+config YAFFS_YAFFS2
+	bool "2048 byte (or larger) / page devices"
+	depends on YAFFS_FS
+	default y
+	help
+	  Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices
+
+	  If unsure, say Y.
+
+config YAFFS_AUTO_YAFFS2
+	bool "Autoselect yaffs2 format"
+	depends on YAFFS_YAFFS2
+	default y
+	help
+	  Without this, you need to explicitely use yaffs2 as the file
+	  system type. With this, you can say "yaffs" and yaffs or yaffs2
+	  will be used depending on the device page size (yaffs on
+	  512-byte page devices, yaffs2 on 2K page devices).
+
+	  If unsure, say Y.
+
+config YAFFS_DISABLE_LAZY_LOAD
+	bool "Disable lazy loading"
+	depends on YAFFS_YAFFS2
+	default n
+	help
+	  "Lazy loading" defers loading file details until they are
+	  required. This saves mount time, but makes the first look-up
+	  a bit longer.
+
+	  Lazy loading will only happen if enabled by this option being 'n'
+	  and if the appropriate tags are available, else yaffs2 will
+	  automatically fall back to immediate loading and do the right
+	  thing.
+
+	  Lazy laoding will be required by checkpointing.
+
+	  Setting this to 'y' will disable lazy loading.
+
+	  If unsure, say N.
+
+
+config YAFFS_DISABLE_WIDE_TNODES
+	bool "Turn off wide tnodes"
+	depends on YAFFS_FS
+	default n
+	help
+	  Wide tnodes are only used for NAND arrays >=32MB for 512-byte
+	  page devices and >=128MB for 2k page devices. They use slightly
+	  more RAM but are faster since they eliminate chunk group
+	  searching.
+
+	  Setting this to 'y' will force tnode width to 16 bits and save
+	  memory but make large arrays slower.
+
+	  If unsure, say N.
+
+config YAFFS_ALWAYS_CHECK_CHUNK_ERASED
+	bool "Force chunk erase check"
+	depends on YAFFS_FS
+	default n
+	help
+          Normally YAFFS only checks chunks before writing until an erased
+	  chunk is found. This helps to detect any partially written
+	  chunks that might have happened due to power loss.
+
+	  Enabling this forces on the test that chunks are erased in flash
+	  before writing to them. This takes more time but is potentially
+	  a bit more secure.
+
+	  Suggest setting Y during development and ironing out driver
+	  issues etc. Suggest setting to N if you want faster writing.
+
+	  If unsure, say Y.
+
+config YAFFS_SHORT_NAMES_IN_RAM
+	bool "Cache short names in RAM"
+	depends on YAFFS_FS
+	default y
+	help
+	  If this config is set, then short names are stored with the
+	  yaffs_Object.  This costs an extra 16 bytes of RAM per object,
+	  but makes look-ups faster.
+
+	  If unsure, say Y.
+
+config YAFFS_EMPTY_LOST_AND_FOUND
+	bool "Empty lost and found on mount"
+	depends on YAFFS_FS
+	default n
+	help
+	  If this is enabled then the contents of lost and found is
+	  automatically dumped at mount.
diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile
new file mode 100644
index 00000000000..382ee6142cf
--- /dev/null
+++ b/fs/yaffs2/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the linux YAFFS filesystem routines.
+#
+
+obj-$(CONFIG_YAFFS_FS) += yaffs.o
+
+yaffs-y := yaffs_ecc.o yaffs_fs.o yaffs_guts.o yaffs_checkptrw.o
+yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o yaffs_qsort.o
+yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o
+yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o
diff --git a/fs/yaffs2/devextras.h b/fs/yaffs2/devextras.h
new file mode 100644
index 00000000000..7df46dc2921
--- /dev/null
+++ b/fs/yaffs2/devextras.h
@@ -0,0 +1,196 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * This file is just holds extra declarations of macros that would normally
+ * be providesd in the Linux kernel. These macros have been written from
+ * scratch but are functionally equivalent to the Linux ones.
+ *
+ */
+
+#ifndef __EXTRAS_H__
+#define __EXTRAS_H__
+
+
+#if !(defined __KERNEL__)
+
+/* Definition of types */
+typedef unsigned char __u8;
+typedef unsigned short __u16;
+typedef unsigned __u32;
+
+#endif
+
+/*
+ * This is a simple doubly linked list implementation that matches the
+ * way the Linux kernel doubly linked list implementation works.
+ */
+
+struct ylist_head {
+	struct ylist_head *next; /* next in chain */
+	struct ylist_head *prev; /* previous in chain */
+};
+
+
+/* Initialise a static list */
+#define YLIST_HEAD(name) \
+struct ylist_head name = { &(name), &(name)}
+
+
+
+/* Initialise a list head to an empty list */
+#define YINIT_LIST_HEAD(p) \
+do { \
+	(p)->next = (p);\
+	(p)->prev = (p); \
+} while (0)
+
+
+/* Add an element to a list */
+static __inline__ void ylist_add(struct ylist_head *newEntry,
+				struct ylist_head *list)
+{
+	struct ylist_head *listNext = list->next;
+
+	list->next = newEntry;
+	newEntry->prev = list;
+	newEntry->next = listNext;
+	listNext->prev = newEntry;
+
+}
+
+static __inline__ void ylist_add_tail(struct ylist_head *newEntry,
+				 struct ylist_head *list)
+{
+	struct ylist_head *listPrev = list->prev;
+
+	list->prev = newEntry;
+	newEntry->next = list;
+	newEntry->prev = listPrev;
+	listPrev->next = newEntry;
+
+}
+
+
+/* Take an element out of its current list, with or without
+ * reinitialising the links.of the entry*/
+static __inline__ void ylist_del(struct ylist_head *entry)
+{
+	struct ylist_head *listNext = entry->next;
+	struct ylist_head *listPrev = entry->prev;
+
+	listNext->prev = listPrev;
+	listPrev->next = listNext;
+
+}
+
+static __inline__ void ylist_del_init(struct ylist_head *entry)
+{
+	ylist_del(entry);
+	entry->next = entry->prev = entry;
+}
+
+
+/* Test if the list is empty */
+static __inline__ int ylist_empty(struct ylist_head *entry)
+{
+	return (entry->next == entry);
+}
+
+
+/* ylist_entry takes a pointer to a list entry and offsets it to that
+ * we can find a pointer to the object it is embedded in.
+ */
+
+
+#define ylist_entry(entry, type, member) \
+	((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
+
+
+/* ylist_for_each and list_for_each_safe  iterate over lists.
+ * ylist_for_each_safe uses temporary storage to make the list delete safe
+ */
+
+#define ylist_for_each(itervar, list) \
+	for (itervar = (list)->next; itervar != (list); itervar = itervar->next)
+
+#define ylist_for_each_safe(itervar, saveVar, list) \
+	for (itervar = (list)->next, saveVar = (list)->next->next; \
+		itervar != (list); itervar = saveVar, saveVar = saveVar->next)
+
+
+#if !(defined __KERNEL__)
+
+
+#ifndef WIN32
+#include <sys/stat.h>
+#endif
+
+
+#ifdef CONFIG_YAFFS_PROVIDE_DEFS
+/* File types */
+
+
+#define DT_UNKNOWN	0
+#define DT_FIFO		1
+#define DT_CHR		2
+#define DT_DIR		4
+#define DT_BLK		6
+#define DT_REG		8
+#define DT_LNK		10
+#define DT_SOCK		12
+#define DT_WHT		14
+
+
+#ifndef WIN32
+#include <sys/stat.h>
+#endif
+
+/*
+ * Attribute flags.  These should be or-ed together to figure out what
+ * has been changed!
+ */
+#define ATTR_MODE	1
+#define ATTR_UID	2
+#define ATTR_GID	4
+#define ATTR_SIZE	8
+#define ATTR_ATIME	16
+#define ATTR_MTIME	32
+#define ATTR_CTIME	64
+
+struct iattr {
+	unsigned int ia_valid;
+	unsigned ia_mode;
+	unsigned ia_uid;
+	unsigned ia_gid;
+	unsigned ia_size;
+	unsigned ia_atime;
+	unsigned ia_mtime;
+	unsigned ia_ctime;
+	unsigned int ia_attr_flags;
+};
+
+#endif
+
+#else
+
+#include <linux/types.h>
+#include <linux/fs.h>
+#include <linux/stat.h>
+
+#endif
+
+
+#endif
diff --git a/fs/yaffs2/moduleconfig.h b/fs/yaffs2/moduleconfig.h
new file mode 100644
index 00000000000..a344baf372a
--- /dev/null
+++ b/fs/yaffs2/moduleconfig.h
@@ -0,0 +1,65 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Martin Fouts <Martin.Fouts@palmsource.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_CONFIG_H__
+#define __YAFFS_CONFIG_H__
+
+#ifdef YAFFS_OUT_OF_TREE
+
+/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */
+#define CONFIG_YAFFS_FS
+#define CONFIG_YAFFS_YAFFS1
+#define CONFIG_YAFFS_YAFFS2
+
+/* These options are independent of each other.  Select those that matter. */
+
+/* Default: Not selected */
+/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */
+/* #define CONFIG_YAFFS_DOES_ECC */
+
+/* Default: Not selected */
+/* Meaning: ECC byte order is 'wrong'.  Only meaningful if */
+/*          CONFIG_YAFFS_DOES_ECC is set */
+/* #define CONFIG_YAFFS_ECC_WRONG_ORDER */
+
+/* Default: Selected */
+/* Meaning: Disables testing whether chunks are erased before writing to them*/
+#define CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK
+
+/* Default: Selected */
+/* Meaning: Cache short names, taking more RAM, but faster look-ups */
+#define CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+
+/* Default: 10 */
+/* Meaning: set the count of blocks to reserve for checkpointing */
+#define CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS 10
+
+/*
+Older-style on-NAND data format has a "pageStatus" byte to record
+chunk/page state.  This byte is zeroed when the page is discarded.
+Choose this option if you have existing on-NAND data in this format
+that you need to continue to support.  New data written also uses the
+older-style format.
+Note: Use of this option generally requires that MTD's oob layout be
+adjusted to use the older-style format.  See notes on tags formats and
+MTD versions in yaffs_mtdif1.c.
+*/
+/* Default: Not selected */
+/* Meaning: Use older-style on-NAND data format with pageStatus byte */
+/* #define CONFIG_YAFFS_9BYTE_TAGS */
+
+#endif /* YAFFS_OUT_OF_TREE */
+
+#endif /* __YAFFS_CONFIG_H__ */
diff --git a/fs/yaffs2/yaffs_checkptrw.c b/fs/yaffs2/yaffs_checkptrw.c
new file mode 100644
index 00000000000..7b69a640f4b
--- /dev/null
+++ b/fs/yaffs2/yaffs_checkptrw.c
@@ -0,0 +1,402 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_checkptrw_c_version =
+	"$Id$";
+
+
+#include "yaffs_checkptrw.h"
+#include "yaffs_getblockinfo.h"
+
+static int yaffs_CheckpointSpaceOk(yaffs_Device *dev)
+{
+	int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
+
+	T(YAFFS_TRACE_CHECKPOINT,
+		(TSTR("checkpt blocks available = %d" TENDSTR),
+		blocksAvailable));
+
+	return (blocksAvailable <= 0) ? 0 : 1;
+}
+
+
+static int yaffs_CheckpointErase(yaffs_Device *dev)
+{
+	int i;
+
+	if (!dev->eraseBlockInNAND)
+		return 0;
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checking blocks %d to %d"TENDSTR),
+		dev->internalStartBlock, dev->internalEndBlock));
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+		if (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("erasing checkpt block %d"TENDSTR), i));
+
+			dev->nBlockErasures++;
+
+			if (dev->eraseBlockInNAND(dev, i - dev->blockOffset /* realign */)) {
+				bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
+				dev->nErasedBlocks++;
+				dev->nFreeChunks += dev->nChunksPerBlock;
+			} else {
+				dev->markNANDBlockBad(dev, i);
+				bi->blockState = YAFFS_BLOCK_STATE_DEAD;
+			}
+		}
+	}
+
+	dev->blocksInCheckpoint = 0;
+
+	return 1;
+}
+
+
+static void yaffs_CheckpointFindNextErasedBlock(yaffs_Device *dev)
+{
+	int  i;
+	int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
+	T(YAFFS_TRACE_CHECKPOINT,
+		(TSTR("allocating checkpt block: erased %d reserved %d avail %d next %d "TENDSTR),
+		dev->nErasedBlocks, dev->nReservedBlocks, blocksAvailable, dev->checkpointNextBlock));
+
+	if (dev->checkpointNextBlock >= 0 &&
+			dev->checkpointNextBlock <= dev->internalEndBlock &&
+			blocksAvailable > 0) {
+
+		for (i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++) {
+			yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+			if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
+				dev->checkpointNextBlock = i + 1;
+				dev->checkpointCurrentBlock = i;
+				T(YAFFS_TRACE_CHECKPOINT, (TSTR("allocating checkpt block %d"TENDSTR), i));
+				return;
+			}
+		}
+	}
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("out of checkpt blocks"TENDSTR)));
+
+	dev->checkpointNextBlock = -1;
+	dev->checkpointCurrentBlock = -1;
+}
+
+static void yaffs_CheckpointFindNextCheckpointBlock(yaffs_Device *dev)
+{
+	int  i;
+	yaffs_ExtendedTags tags;
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("find next checkpt block: start:  blocks %d next %d" TENDSTR),
+		dev->blocksInCheckpoint, dev->checkpointNextBlock));
+
+	if (dev->blocksInCheckpoint < dev->checkpointMaxBlocks)
+		for (i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++) {
+			int chunk = i * dev->nChunksPerBlock;
+			int realignedChunk = chunk - dev->chunkOffset;
+
+			dev->readChunkWithTagsFromNAND(dev, realignedChunk,
+					NULL, &tags);
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("find next checkpt block: search: block %d oid %d seq %d eccr %d" TENDSTR),
+				i, tags.objectId, tags.sequenceNumber, tags.eccResult));
+
+			if (tags.sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA) {
+				/* Right kind of block */
+				dev->checkpointNextBlock = tags.objectId;
+				dev->checkpointCurrentBlock = i;
+				dev->checkpointBlockList[dev->blocksInCheckpoint] = i;
+				dev->blocksInCheckpoint++;
+				T(YAFFS_TRACE_CHECKPOINT, (TSTR("found checkpt block %d"TENDSTR), i));
+				return;
+			}
+		}
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("found no more checkpt blocks"TENDSTR)));
+
+	dev->checkpointNextBlock = -1;
+	dev->checkpointCurrentBlock = -1;
+}
+
+
+int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting)
+{
+
+
+	dev->checkpointOpenForWrite = forWriting;
+
+	/* Got the functions we need? */
+	if (!dev->writeChunkWithTagsToNAND ||
+			!dev->readChunkWithTagsFromNAND ||
+			!dev->eraseBlockInNAND ||
+			!dev->markNANDBlockBad)
+		return 0;
+
+	if (forWriting && !yaffs_CheckpointSpaceOk(dev))
+		return 0;
+
+	if (!dev->checkpointBuffer)
+		dev->checkpointBuffer = YMALLOC_DMA(dev->totalBytesPerChunk);
+	if (!dev->checkpointBuffer)
+		return 0;
+
+
+	dev->checkpointPageSequence = 0;
+	dev->checkpointByteCount = 0;
+	dev->checkpointSum = 0;
+	dev->checkpointXor = 0;
+	dev->checkpointCurrentBlock = -1;
+	dev->checkpointCurrentChunk = -1;
+	dev->checkpointNextBlock = dev->internalStartBlock;
+
+	/* Erase all the blocks in the checkpoint area */
+	if (forWriting) {
+		memset(dev->checkpointBuffer, 0, dev->nDataBytesPerChunk);
+		dev->checkpointByteOffset = 0;
+		return yaffs_CheckpointErase(dev);
+	} else {
+		int i;
+		/* Set to a value that will kick off a read */
+		dev->checkpointByteOffset = dev->nDataBytesPerChunk;
+		/* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully)
+		 * going to be way more than we need */
+		dev->blocksInCheckpoint = 0;
+		dev->checkpointMaxBlocks = (dev->internalEndBlock - dev->internalStartBlock)/16 + 2;
+		dev->checkpointBlockList = YMALLOC(sizeof(int) * dev->checkpointMaxBlocks);
+		if(!dev->checkpointBlockList)
+			return 0;
+
+		for (i = 0; i < dev->checkpointMaxBlocks; i++)
+			dev->checkpointBlockList[i] = -1;
+	}
+
+	return 1;
+}
+
+int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum)
+{
+	__u32 compositeSum;
+	compositeSum =  (dev->checkpointSum << 8) | (dev->checkpointXor & 0xFF);
+	*sum = compositeSum;
+	return 1;
+}
+
+static int yaffs_CheckpointFlushBuffer(yaffs_Device *dev)
+{
+	int chunk;
+	int realignedChunk;
+
+	yaffs_ExtendedTags tags;
+
+	if (dev->checkpointCurrentBlock < 0) {
+		yaffs_CheckpointFindNextErasedBlock(dev);
+		dev->checkpointCurrentChunk = 0;
+	}
+
+	if (dev->checkpointCurrentBlock < 0)
+		return 0;
+
+	tags.chunkDeleted = 0;
+	tags.objectId = dev->checkpointNextBlock; /* Hint to next place to look */
+	tags.chunkId = dev->checkpointPageSequence + 1;
+	tags.sequenceNumber =  YAFFS_SEQUENCE_CHECKPOINT_DATA;
+	tags.byteCount = dev->nDataBytesPerChunk;
+	if (dev->checkpointCurrentChunk == 0) {
+		/* First chunk we write for the block? Set block state to
+		   checkpoint */
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, dev->checkpointCurrentBlock);
+		bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
+		dev->blocksInCheckpoint++;
+	}
+
+	chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock + dev->checkpointCurrentChunk;
+
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR),
+		chunk, dev->checkpointCurrentBlock, dev->checkpointCurrentChunk, tags.objectId, tags.chunkId));
+
+	realignedChunk = chunk - dev->chunkOffset;
+
+	dev->nPageWrites++;
+
+	dev->writeChunkWithTagsToNAND(dev, realignedChunk,
+			dev->checkpointBuffer, &tags);
+	dev->checkpointByteOffset = 0;
+	dev->checkpointPageSequence++;
+	dev->checkpointCurrentChunk++;
+	if (dev->checkpointCurrentChunk >= dev->nChunksPerBlock) {
+		dev->checkpointCurrentChunk = 0;
+		dev->checkpointCurrentBlock = -1;
+	}
+	memset(dev->checkpointBuffer, 0, dev->nDataBytesPerChunk);
+
+	return 1;
+}
+
+
+int yaffs_CheckpointWrite(yaffs_Device *dev, const void *data, int nBytes)
+{
+	int i = 0;
+	int ok = 1;
+
+
+	__u8 * dataBytes = (__u8 *)data;
+
+
+
+	if (!dev->checkpointBuffer)
+		return 0;
+
+	if (!dev->checkpointOpenForWrite)
+		return -1;
+
+	while (i < nBytes && ok) {
+		dev->checkpointBuffer[dev->checkpointByteOffset] = *dataBytes;
+		dev->checkpointSum += *dataBytes;
+		dev->checkpointXor ^= *dataBytes;
+
+		dev->checkpointByteOffset++;
+		i++;
+		dataBytes++;
+		dev->checkpointByteCount++;
+
+
+		if (dev->checkpointByteOffset < 0 ||
+		   dev->checkpointByteOffset >= dev->nDataBytesPerChunk)
+			ok = yaffs_CheckpointFlushBuffer(dev);
+	}
+
+	return i;
+}
+
+int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes)
+{
+	int i = 0;
+	int ok = 1;
+	yaffs_ExtendedTags tags;
+
+
+	int chunk;
+	int realignedChunk;
+
+	__u8 *dataBytes = (__u8 *)data;
+
+	if (!dev->checkpointBuffer)
+		return 0;
+
+	if (dev->checkpointOpenForWrite)
+		return -1;
+
+	while (i < nBytes && ok) {
+
+
+		if (dev->checkpointByteOffset < 0 ||
+			dev->checkpointByteOffset >= dev->nDataBytesPerChunk) {
+
+			if (dev->checkpointCurrentBlock < 0) {
+				yaffs_CheckpointFindNextCheckpointBlock(dev);
+				dev->checkpointCurrentChunk = 0;
+			}
+
+			if (dev->checkpointCurrentBlock < 0)
+				ok = 0;
+			else {
+				chunk = dev->checkpointCurrentBlock *
+					dev->nChunksPerBlock +
+					dev->checkpointCurrentChunk;
+
+				realignedChunk = chunk - dev->chunkOffset;
+				
+				dev->nPageReads++;
+
+				/* read in the next chunk */
+				/* printf("read checkpoint page %d\n",dev->checkpointPage); */
+				dev->readChunkWithTagsFromNAND(dev,
+						realignedChunk,
+						dev->checkpointBuffer,
+						&tags);
+
+				if (tags.chunkId != (dev->checkpointPageSequence + 1) ||
+					tags.eccResult > YAFFS_ECC_RESULT_FIXED ||
+					tags.sequenceNumber != YAFFS_SEQUENCE_CHECKPOINT_DATA)
+					ok = 0;
+
+				dev->checkpointByteOffset = 0;
+				dev->checkpointPageSequence++;
+				dev->checkpointCurrentChunk++;
+
+				if (dev->checkpointCurrentChunk >= dev->nChunksPerBlock)
+					dev->checkpointCurrentBlock = -1;
+			}
+		}
+
+		if (ok) {
+			*dataBytes = dev->checkpointBuffer[dev->checkpointByteOffset];
+			dev->checkpointSum += *dataBytes;
+			dev->checkpointXor ^= *dataBytes;
+			dev->checkpointByteOffset++;
+			i++;
+			dataBytes++;
+			dev->checkpointByteCount++;
+		}
+	}
+
+	return 	i;
+}
+
+int yaffs_CheckpointClose(yaffs_Device *dev)
+{
+
+	if (dev->checkpointOpenForWrite) {
+		if (dev->checkpointByteOffset != 0)
+			yaffs_CheckpointFlushBuffer(dev);
+	} else if(dev->checkpointBlockList){
+		int i;
+		for (i = 0; i < dev->blocksInCheckpoint && dev->checkpointBlockList[i] >= 0; i++) {
+			int blk = dev->checkpointBlockList[i];
+			yaffs_BlockInfo *bi = NULL;
+			if( dev->internalStartBlock <= blk && blk <= dev->internalEndBlock)
+				bi = yaffs_GetBlockInfo(dev, blk);
+			if (bi && bi->blockState == YAFFS_BLOCK_STATE_EMPTY)
+				bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
+			else {
+				/* Todo this looks odd... */
+			}
+		}
+		YFREE(dev->checkpointBlockList);
+		dev->checkpointBlockList = NULL;
+	}
+
+	dev->nFreeChunks -= dev->blocksInCheckpoint * dev->nChunksPerBlock;
+	dev->nErasedBlocks -= dev->blocksInCheckpoint;
+
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint byte count %d" TENDSTR),
+			dev->checkpointByteCount));
+
+	if (dev->checkpointBuffer) {
+		/* free the buffer */
+		YFREE(dev->checkpointBuffer);
+		dev->checkpointBuffer = NULL;
+		return 1;
+	} else
+		return 0;
+}
+
+int yaffs_CheckpointInvalidateStream(yaffs_Device *dev)
+{
+	/* Erase the checkpoint data */
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint invalidate of %d blocks"TENDSTR),
+		dev->blocksInCheckpoint));
+
+	return yaffs_CheckpointErase(dev);
+}
diff --git a/fs/yaffs2/yaffs_checkptrw.h b/fs/yaffs2/yaffs_checkptrw.h
new file mode 100644
index 00000000000..5d426ea8d77
--- /dev/null
+++ b/fs/yaffs2/yaffs_checkptrw.h
@@ -0,0 +1,35 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_CHECKPTRW_H__
+#define __YAFFS_CHECKPTRW_H__
+
+#include "yaffs_guts.h"
+
+int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting);
+
+int yaffs_CheckpointWrite(yaffs_Device *dev, const void *data, int nBytes);
+
+int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes);
+
+int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum);
+
+int yaffs_CheckpointClose(yaffs_Device *dev);
+
+int yaffs_CheckpointInvalidateStream(yaffs_Device *dev);
+
+
+#endif
+
diff --git a/fs/yaffs2/yaffs_ecc.c b/fs/yaffs2/yaffs_ecc.c
new file mode 100644
index 00000000000..4676346cef4
--- /dev/null
+++ b/fs/yaffs2/yaffs_ecc.c
@@ -0,0 +1,326 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This code implements the ECC algorithm used in SmartMedia.
+ *
+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
+ * The two unused bit are set to 1.
+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
+ * blocks are used on a 512-byte NAND page.
+ *
+ */
+
+/* Table generated by gen-ecc.c
+ * Using a table means we do not have to calculate p1..p4 and p1'..p4'
+ * for each byte of data. These are instead provided in a table in bits7..2.
+ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore
+ * this bytes influence on the line parity.
+ */
+
+const char *yaffs_ecc_c_version =
+	"$Id$";
+
+#include "yportenv.h"
+
+#include "yaffs_ecc.h"
+
+static const unsigned char column_parity_table[] = {
+	0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
+	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
+	0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
+	0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
+	0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
+	0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
+	0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
+	0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
+	0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
+	0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
+	0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
+	0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
+	0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
+	0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
+	0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
+	0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
+	0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0,
+	0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9,
+	0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55,
+	0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c,
+	0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59,
+	0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30,
+	0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc,
+	0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5,
+	0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65,
+	0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c,
+	0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0,
+	0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99,
+	0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc,
+	0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95,
+	0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
+	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
+};
+
+/* Count the bits in an unsigned char or a U32 */
+
+static int yaffs_CountBits(unsigned char x)
+{
+	int r = 0;
+	while (x) {
+		if (x & 1)
+			r++;
+		x >>= 1;
+	}
+	return r;
+}
+
+static int yaffs_CountBits32(unsigned x)
+{
+	int r = 0;
+	while (x) {
+		if (x & 1)
+			r++;
+		x >>= 1;
+	}
+	return r;
+}
+
+/* Calculate the ECC for a 256-byte block of data */
+void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
+{
+	unsigned int i;
+
+	unsigned char col_parity = 0;
+	unsigned char line_parity = 0;
+	unsigned char line_parity_prime = 0;
+	unsigned char t;
+	unsigned char b;
+
+	for (i = 0; i < 256; i++) {
+		b = column_parity_table[*data++];
+		col_parity ^= b;
+
+		if (b & 0x01) {		/* odd number of bits in the byte */
+			line_parity ^= i;
+			line_parity_prime ^= ~i;
+		}
+	}
+
+	ecc[2] = (~col_parity) | 0x03;
+
+	t = 0;
+	if (line_parity & 0x80)
+		t |= 0x80;
+	if (line_parity_prime & 0x80)
+		t |= 0x40;
+	if (line_parity & 0x40)
+		t |= 0x20;
+	if (line_parity_prime & 0x40)
+		t |= 0x10;
+	if (line_parity & 0x20)
+		t |= 0x08;
+	if (line_parity_prime & 0x20)
+		t |= 0x04;
+	if (line_parity & 0x10)
+		t |= 0x02;
+	if (line_parity_prime & 0x10)
+		t |= 0x01;
+	ecc[1] = ~t;
+
+	t = 0;
+	if (line_parity & 0x08)
+		t |= 0x80;
+	if (line_parity_prime & 0x08)
+		t |= 0x40;
+	if (line_parity & 0x04)
+		t |= 0x20;
+	if (line_parity_prime & 0x04)
+		t |= 0x10;
+	if (line_parity & 0x02)
+		t |= 0x08;
+	if (line_parity_prime & 0x02)
+		t |= 0x04;
+	if (line_parity & 0x01)
+		t |= 0x02;
+	if (line_parity_prime & 0x01)
+		t |= 0x01;
+	ecc[0] = ~t;
+
+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
+	/* Swap the bytes into the wrong order */
+	t = ecc[0];
+	ecc[0] = ecc[1];
+	ecc[1] = t;
+#endif
+}
+
+
+/* Correct the ECC on a 256 byte block of data */
+
+int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
+		     const unsigned char *test_ecc)
+{
+	unsigned char d0, d1, d2;	/* deltas */
+
+	d0 = read_ecc[0] ^ test_ecc[0];
+	d1 = read_ecc[1] ^ test_ecc[1];
+	d2 = read_ecc[2] ^ test_ecc[2];
+
+	if ((d0 | d1 | d2) == 0)
+		return 0; /* no error */
+
+	if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 &&
+	    ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 &&
+	    ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) {
+		/* Single bit (recoverable) error in data */
+
+		unsigned byte;
+		unsigned bit;
+
+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
+		/* swap the bytes to correct for the wrong order */
+		unsigned char t;
+
+		t = d0;
+		d0 = d1;
+		d1 = t;
+#endif
+
+		bit = byte = 0;
+
+		if (d1 & 0x80)
+			byte |= 0x80;
+		if (d1 & 0x20)
+			byte |= 0x40;
+		if (d1 & 0x08)
+			byte |= 0x20;
+		if (d1 & 0x02)
+			byte |= 0x10;
+		if (d0 & 0x80)
+			byte |= 0x08;
+		if (d0 & 0x20)
+			byte |= 0x04;
+		if (d0 & 0x08)
+			byte |= 0x02;
+		if (d0 & 0x02)
+			byte |= 0x01;
+
+		if (d2 & 0x80)
+			bit |= 0x04;
+		if (d2 & 0x20)
+			bit |= 0x02;
+		if (d2 & 0x08)
+			bit |= 0x01;
+
+		data[byte] ^= (1 << bit);
+
+		return 1; /* Corrected the error */
+	}
+
+	if ((yaffs_CountBits(d0) +
+	     yaffs_CountBits(d1) +
+	     yaffs_CountBits(d2)) ==  1) {
+		/* Reccoverable error in ecc */
+
+		read_ecc[0] = test_ecc[0];
+		read_ecc[1] = test_ecc[1];
+		read_ecc[2] = test_ecc[2];
+
+		return 1; /* Corrected the error */
+	}
+
+	/* Unrecoverable error */
+
+	return -1;
+
+}
+
+
+/*
+ * ECCxxxOther does ECC calcs on arbitrary n bytes of data
+ */
+void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
+				yaffs_ECCOther *eccOther)
+{
+	unsigned int i;
+
+	unsigned char col_parity = 0;
+	unsigned line_parity = 0;
+	unsigned line_parity_prime = 0;
+	unsigned char b;
+
+	for (i = 0; i < nBytes; i++) {
+		b = column_parity_table[*data++];
+		col_parity ^= b;
+
+		if (b & 0x01)	 {
+			/* odd number of bits in the byte */
+			line_parity ^= i;
+			line_parity_prime ^= ~i;
+		}
+
+	}
+
+	eccOther->colParity = (col_parity >> 2) & 0x3f;
+	eccOther->lineParity = line_parity;
+	eccOther->lineParityPrime = line_parity_prime;
+}
+
+int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *read_ecc,
+			const yaffs_ECCOther *test_ecc)
+{
+	unsigned char cDelta;	/* column parity delta */
+	unsigned lDelta;	/* line parity delta */
+	unsigned lDeltaPrime;	/* line parity delta */
+	unsigned bit;
+
+	cDelta = read_ecc->colParity ^ test_ecc->colParity;
+	lDelta = read_ecc->lineParity ^ test_ecc->lineParity;
+	lDeltaPrime = read_ecc->lineParityPrime ^ test_ecc->lineParityPrime;
+
+	if ((cDelta | lDelta | lDeltaPrime) == 0)
+		return 0; /* no error */
+
+	if (lDelta == ~lDeltaPrime &&
+	    (((cDelta ^ (cDelta >> 1)) & 0x15) == 0x15)) {
+		/* Single bit (recoverable) error in data */
+
+		bit = 0;
+
+		if (cDelta & 0x20)
+			bit |= 0x04;
+		if (cDelta & 0x08)
+			bit |= 0x02;
+		if (cDelta & 0x02)
+			bit |= 0x01;
+
+		if (lDelta >= nBytes)
+			return -1;
+
+		data[lDelta] ^= (1 << bit);
+
+		return 1; /* corrected */
+	}
+
+	if ((yaffs_CountBits32(lDelta) + yaffs_CountBits32(lDeltaPrime) +
+			yaffs_CountBits(cDelta)) == 1) {
+		/* Reccoverable error in ecc */
+
+		*read_ecc = *test_ecc;
+		return 1; /* corrected */
+	}
+
+	/* Unrecoverable error */
+
+	return -1;
+}
diff --git a/fs/yaffs2/yaffs_ecc.h b/fs/yaffs2/yaffs_ecc.h
new file mode 100644
index 00000000000..60765176e8d
--- /dev/null
+++ b/fs/yaffs2/yaffs_ecc.h
@@ -0,0 +1,44 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * This code implements the ECC algorithm used in SmartMedia.
+ *
+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
+ * The two unused bit are set to 1.
+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
+ * blocks are used on a 512-byte NAND page.
+ *
+ */
+
+#ifndef __YAFFS_ECC_H__
+#define __YAFFS_ECC_H__
+
+typedef struct {
+	unsigned char colParity;
+	unsigned lineParity;
+	unsigned lineParityPrime;
+} yaffs_ECCOther;
+
+void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc);
+int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
+		const unsigned char *test_ecc);
+
+void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *ecc);
+int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
+			yaffs_ECCOther *read_ecc,
+			const yaffs_ECCOther *test_ecc);
+#endif
diff --git a/fs/yaffs2/yaffs_fs.c b/fs/yaffs2/yaffs_fs.c
new file mode 100644
index 00000000000..4c155aef0a3
--- /dev/null
+++ b/fs/yaffs2/yaffs_fs.c
@@ -0,0 +1,2699 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2009 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ * Acknowledgements:
+ * Luc van OostenRyck for numerous patches.
+ * Nick Bane for numerous patches.
+ * Nick Bane for 2.5/2.6 integration.
+ * Andras Toth for mknod rdev issue.
+ * Michael Fischer for finding the problem with inode inconsistency.
+ * Some code bodily lifted from JFFS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ *
+ * This is the file system front-end to YAFFS that hooks it up to
+ * the VFS.
+ *
+ * Special notes:
+ * >> 2.4: sb->u.generic_sbp points to the yaffs_Device associated with
+ *         this superblock
+ * >> 2.6: sb->s_fs_info  points to the yaffs_Device associated with this
+ *         superblock
+ * >> inode->u.generic_ip points to the associated yaffs_Object.
+ */
+
+const char *yaffs_fs_c_version =
+    "$Id$";
+extern const char *yaffs_guts_c_version;
+
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+#include <linux/config.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/smp_lock.h>
+#include <linux/pagemap.h>
+#include <linux/mtd/mtd.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+
+#include "asm/div64.h"
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+#include <linux/statfs.h>	/* Added NCB 15-8-2003 */
+#include <linux/statfs.h>
+#define UnlockPage(p) unlock_page(p)
+#define Page_Uptodate(page)	test_bit(PG_uptodate, &(page)->flags)
+
+/* FIXME: use sb->s_id instead ? */
+#define yaffs_devname(sb, buf)	bdevname(sb->s_bdev, buf)
+
+#else
+
+#include <linux/locks.h>
+#define	BDEVNAME_SIZE		0
+#define	yaffs_devname(sb, buf)	kdevname(sb->s_dev)
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0))
+/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */
+#define __user
+#endif
+
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
+#define YPROC_ROOT  (&proc_root)
+#else
+#define YPROC_ROOT  NULL
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+#define WRITE_SIZE_STR "writesize"
+#define WRITE_SIZE(mtd) ((mtd)->writesize)
+#else
+#define WRITE_SIZE_STR "oobblock"
+#define WRITE_SIZE(mtd) ((mtd)->oobblock)
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27))
+#define YAFFS_USE_WRITE_BEGIN_END 1
+#else
+#define YAFFS_USE_WRITE_BEGIN_END 0
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28))
+static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size)
+{
+	uint64_t result = partition_size;
+	do_div(result, block_size);
+	return (uint32_t)result;
+}
+#else
+#define YCALCBLOCKS(s, b) ((s)/(b))
+#endif
+
+#include <linux/uaccess.h>
+
+#include "yportenv.h"
+#include "yaffs_guts.h"
+
+#include <linux/mtd/mtd.h>
+#include "yaffs_mtdif.h"
+#include "yaffs_mtdif1.h"
+#include "yaffs_mtdif2.h"
+
+unsigned int yaffs_traceMask = YAFFS_TRACE_BAD_BLOCKS;
+unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS;
+unsigned int yaffs_auto_checkpoint = 1;
+
+/* Module Parameters */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+module_param(yaffs_traceMask, uint, 0644);
+module_param(yaffs_wr_attempts, uint, 0644);
+module_param(yaffs_auto_checkpoint, uint, 0644);
+#else
+MODULE_PARM(yaffs_traceMask, "i");
+MODULE_PARM(yaffs_wr_attempts, "i");
+MODULE_PARM(yaffs_auto_checkpoint, "i");
+#endif
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25))
+/* use iget and read_inode */
+#define Y_IGET(sb, inum) iget((sb), (inum))
+static void yaffs_read_inode(struct inode *inode);
+
+#else
+/* Call local equivalent */
+#define YAFFS_USE_OWN_IGET
+#define Y_IGET(sb, inum) yaffs_iget((sb), (inum))
+
+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino);
+#endif
+
+/*#define T(x) printk x */
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+#define yaffs_InodeToObjectLV(iptr) ((iptr)->i_private)
+#else
+#define yaffs_InodeToObjectLV(iptr) ((iptr)->u.generic_ip)
+#endif
+
+#define yaffs_InodeToObject(iptr) ((yaffs_Object *)(yaffs_InodeToObjectLV(iptr)))
+#define yaffs_DentryToObject(dptr) yaffs_InodeToObject((dptr)->d_inode)
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+#define yaffs_SuperToDevice(sb)	((yaffs_Device *)sb->s_fs_info)
+#else
+#define yaffs_SuperToDevice(sb)	((yaffs_Device *)sb->u.generic_sbp)
+#endif
+
+
+#define update_dir_time(dir) do {\
+			(dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \
+		} while(0)
+		
+static void yaffs_put_super(struct super_block *sb);
+
+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
+				loff_t *pos);
+static ssize_t yaffs_hold_space(struct file *f);
+static void yaffs_release_space(struct file *f);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_file_flush(struct file *file, fl_owner_t id);
+#else
+static int yaffs_file_flush(struct file *file);
+#endif
+
+static int yaffs_sync_object(struct file *file, struct dentry *dentry,
+				int datasync);
+
+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
+			struct nameidata *n);
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
+					struct nameidata *n);
+#else
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode);
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry);
+#endif
+static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
+			struct dentry *dentry);
+static int yaffs_unlink(struct inode *dir, struct dentry *dentry);
+static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
+			const char *symname);
+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			dev_t dev);
+#else
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			int dev);
+#endif
+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
+			struct inode *new_dir, struct dentry *new_dentry);
+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_sync_fs(struct super_block *sb, int wait);
+static void yaffs_write_super(struct super_block *sb);
+#else
+static int yaffs_sync_fs(struct super_block *sb);
+static int yaffs_write_super(struct super_block *sb);
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf);
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf);
+#else
+static int yaffs_statfs(struct super_block *sb, struct statfs *buf);
+#endif
+
+#ifdef YAFFS_HAS_PUT_INODE
+static void yaffs_put_inode(struct inode *inode);
+#endif
+
+static void yaffs_delete_inode(struct inode *);
+static void yaffs_clear_inode(struct inode *);
+
+static int yaffs_readpage(struct file *file, struct page *page);
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_writepage(struct page *page, struct writeback_control *wbc);
+#else
+static int yaffs_writepage(struct page *page);
+#endif
+
+
+#if (YAFFS_USE_WRITE_BEGIN_END != 0)
+static int yaffs_write_begin(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned flags,
+				struct page **pagep, void **fsdata);
+static int yaffs_write_end(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned copied,
+				struct page *pg, void *fsdadata);
+#else
+static int yaffs_prepare_write(struct file *f, struct page *pg,
+				unsigned offset, unsigned to);
+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
+				unsigned to);
+
+#endif
+
+static int yaffs_readlink(struct dentry *dentry, char __user *buffer,
+				int buflen);
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
+#else
+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd);
+#endif
+
+static struct address_space_operations yaffs_file_address_operations = {
+	.readpage = yaffs_readpage,
+	.writepage = yaffs_writepage,
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+	.write_begin = yaffs_write_begin,
+	.write_end = yaffs_write_end,
+#else
+	.prepare_write = yaffs_prepare_write,
+	.commit_write = yaffs_commit_write,
+#endif
+};
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22))
+static const struct file_operations yaffs_file_operations = {
+	.read = do_sync_read,
+	.write = do_sync_write,
+	.aio_read = generic_file_aio_read,
+	.aio_write = generic_file_aio_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+	.splice_read = generic_file_splice_read,
+	.splice_write = generic_file_splice_write,
+	.llseek = generic_file_llseek,
+};
+
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
+
+static const struct file_operations yaffs_file_operations = {
+	.read = do_sync_read,
+	.write = do_sync_write,
+	.aio_read = generic_file_aio_read,
+	.aio_write = generic_file_aio_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+	.sendfile = generic_file_sendfile,
+};
+
+#else
+
+static const struct file_operations yaffs_file_operations = {
+	.read = generic_file_read,
+	.write = generic_file_write,
+	.mmap = generic_file_mmap,
+	.flush = yaffs_file_flush,
+	.fsync = yaffs_sync_object,
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	.sendfile = generic_file_sendfile,
+#endif
+};
+#endif
+
+static const struct inode_operations yaffs_file_inode_operations = {
+	.setattr = yaffs_setattr,
+};
+
+static const struct inode_operations yaffs_symlink_inode_operations = {
+	.readlink = yaffs_readlink,
+	.follow_link = yaffs_follow_link,
+	.setattr = yaffs_setattr,
+};
+
+static const struct inode_operations yaffs_dir_inode_operations = {
+	.create = yaffs_create,
+	.lookup = yaffs_lookup,
+	.link = yaffs_link,
+	.unlink = yaffs_unlink,
+	.symlink = yaffs_symlink,
+	.mkdir = yaffs_mkdir,
+	.rmdir = yaffs_unlink,
+	.mknod = yaffs_mknod,
+	.rename = yaffs_rename,
+	.setattr = yaffs_setattr,
+};
+
+static const struct file_operations yaffs_dir_operations = {
+	.read = generic_read_dir,
+	.readdir = yaffs_readdir,
+	.fsync = yaffs_sync_object,
+};
+
+static const struct super_operations yaffs_super_ops = {
+	.statfs = yaffs_statfs,
+
+#ifndef YAFFS_USE_OWN_IGET
+	.read_inode = yaffs_read_inode,
+#endif
+#ifdef YAFFS_HAS_PUT_INODE
+	.put_inode = yaffs_put_inode,
+#endif
+	.put_super = yaffs_put_super,
+	.delete_inode = yaffs_delete_inode,
+	.clear_inode = yaffs_clear_inode,
+	.sync_fs = yaffs_sync_fs,
+	.write_super = yaffs_write_super,
+};
+
+static void yaffs_GrossLock(yaffs_Device *dev)
+{
+	T(YAFFS_TRACE_OS, ("yaffs locking %p\n", current));
+	down(&dev->grossLock);
+	T(YAFFS_TRACE_OS, ("yaffs locked %p\n", current));
+}
+
+static void yaffs_GrossUnlock(yaffs_Device *dev)
+{
+	T(YAFFS_TRACE_OS, ("yaffs unlocking %p\n", current));
+	up(&dev->grossLock);
+}
+
+
+/*-----------------------------------------------------------------*/
+/* Directory search context allows us to unlock access to yaffs during
+ * filldir without causing problems with the directory being modified.
+ * This is similar to the tried and tested mechanism used in yaffs direct.
+ *
+ * A search context iterates along a doubly linked list of siblings in the
+ * directory. If the iterating object is deleted then this would corrupt
+ * the list iteration, likely causing a crash. The search context avoids
+ * this by using the removeObjectCallback to move the search context to the
+ * next object before the object is deleted.
+ *
+ * Many readdirs (and thus seach conexts) may be alive simulateously so
+ * each yaffs_Device has a list of these.
+ *
+ * A seach context lives for the duration of a readdir.
+ *
+ * All these functions must be called while yaffs is locked.
+ */
+
+struct yaffs_SearchContext {
+	yaffs_Device *dev;
+	yaffs_Object *dirObj;
+	yaffs_Object *nextReturn;
+	struct ylist_head others;
+};
+
+/*
+ * yaffs_NewSearch() creates a new search context, initialises it and
+ * adds it to the device's search context list.
+ *
+ * Called at start of readdir.
+ */
+static struct yaffs_SearchContext * yaffs_NewSearch(yaffs_Object *dir)
+{
+	yaffs_Device *dev = dir->myDev;
+	struct yaffs_SearchContext *sc = YMALLOC(sizeof(struct yaffs_SearchContext));
+	if(sc){
+		sc->dirObj = dir;
+		sc->dev = dev;
+		if( ylist_empty(&sc->dirObj->variant.directoryVariant.children))
+			sc->nextReturn = NULL;
+		else
+			sc->nextReturn = ylist_entry(
+                                dir->variant.directoryVariant.children.next,
+				yaffs_Object,siblings);
+		YINIT_LIST_HEAD(&sc->others);
+		ylist_add(&sc->others,&dev->searchContexts);
+	}
+	return sc;
+}
+
+/*
+ * yaffs_EndSearch() disposes of a search context and cleans up.
+ */
+static void yaffs_EndSearch(struct yaffs_SearchContext * sc)
+{
+	if(sc){
+		ylist_del(&sc->others);
+		YFREE(sc);
+	}
+}
+
+/*
+ * yaffs_SearchAdvance() moves a search context to the next object.
+ * Called when the search iterates or when an object removal causes
+ * the search context to be moved to the next object.
+ */
+static void yaffs_SearchAdvance(struct yaffs_SearchContext *sc)
+{
+        if(!sc)
+                return;
+
+        if( sc->nextReturn == NULL ||
+                ylist_empty(&sc->dirObj->variant.directoryVariant.children))
+                sc->nextReturn = NULL;
+        else {
+                struct ylist_head *next = sc->nextReturn->siblings.next;
+
+                if( next == &sc->dirObj->variant.directoryVariant.children)
+                        sc->nextReturn = NULL; /* end of list */
+                else
+                        sc->nextReturn = ylist_entry(next,yaffs_Object,siblings);
+        }
+}
+
+/*
+ * yaffs_RemoveObjectCallback() is called when an object is unlinked.
+ * We check open search contexts and advance any which are currently
+ * on the object being iterated.
+ */
+static void yaffs_RemoveObjectCallback(yaffs_Object *obj)
+{
+
+        struct ylist_head *i;
+        struct yaffs_SearchContext *sc;
+        struct ylist_head *search_contexts = &obj->myDev->searchContexts;
+
+
+        /* Iterate through the directory search contexts.
+         * If any are currently on the object being removed, then advance
+         * the search context to the next object to prevent a hanging pointer.
+         */
+         ylist_for_each(i, search_contexts) {
+                if (i) {
+                        sc = ylist_entry(i, struct yaffs_SearchContext,others);
+                        if(sc->nextReturn == obj)
+                                yaffs_SearchAdvance(sc);
+                }
+	}
+
+}
+
+
+/*-----------------------------------------------------------------*/
+
+static int yaffs_readlink(struct dentry *dentry, char __user *buffer,
+			int buflen)
+{
+	unsigned char *alias;
+	int ret;
+
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
+
+	yaffs_GrossUnlock(dev);
+
+	if (!alias)
+		return -ENOMEM;
+
+	ret = vfs_readlink(dentry, buffer, buflen, alias);
+	kfree(alias);
+	return ret;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
+#else
+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd)
+#endif
+{
+	unsigned char *alias;
+	int ret;
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry));
+
+	yaffs_GrossUnlock(dev);
+
+	if (!alias) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = vfs_follow_link(nd, alias);
+	kfree(alias);
+out:
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+	return ERR_PTR(ret);
+#else
+	return ret;
+#endif
+}
+
+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
+				yaffs_Object *obj);
+
+/*
+ * Lookup is used to find objects in the fs
+ */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry,
+				struct nameidata *n)
+#else
+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry)
+#endif
+{
+	yaffs_Object *obj;
+	struct inode *inode = NULL;	/* NCB 2.5/2.6 needs NULL here */
+
+	yaffs_Device *dev = yaffs_InodeToObject(dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_lookup for %d:%s\n",
+		yaffs_InodeToObject(dir)->objectId, dentry->d_name.name));
+
+	obj = yaffs_FindObjectByName(yaffs_InodeToObject(dir),
+					dentry->d_name.name);
+
+	obj = yaffs_GetEquivalentObject(obj);	/* in case it was a hardlink */
+
+	/* Can't hold gross lock when calling yaffs_get_inode() */
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_lookup found %d\n", obj->objectId));
+
+		inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
+
+		if (inode) {
+			T(YAFFS_TRACE_OS,
+				("yaffs_loookup dentry \n"));
+/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to
+ * d_add even if NULL inode */
+#if 0
+			/*dget(dentry); // try to solve directory bug */
+			d_add(dentry, inode);
+
+			/* return dentry; */
+			return NULL;
+#endif
+		}
+
+	} else {
+		T(YAFFS_TRACE_OS, ("yaffs_lookup not found\n"));
+
+	}
+
+/* added NCB for 2.5/6 compatability - forces add even if inode is
+ * NULL which creates dentry hash */
+	d_add(dentry, inode);
+
+	return NULL;
+}
+
+
+#ifdef YAFFS_HAS_PUT_INODE
+
+/* For now put inode is just for debugging
+ * Put inode is called when the inode **structure** is put.
+ */
+static void yaffs_put_inode(struct inode *inode)
+{
+	T(YAFFS_TRACE_OS,
+		("yaffs_put_inode: ino %d, count %d\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count)));
+
+}
+#endif
+
+/* clear is called to tell the fs to release any per-inode data it holds */
+static void yaffs_clear_inode(struct inode *inode)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	obj = yaffs_InodeToObject(inode);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_clear_inode: ino %d, count %d %s\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count),
+		obj ? "object exists" : "null object"));
+
+	if (obj) {
+		dev = obj->myDev;
+		yaffs_GrossLock(dev);
+
+		/* Clear the association between the inode and
+		 * the yaffs_Object.
+		 */
+		obj->myInode = NULL;
+		yaffs_InodeToObjectLV(inode) = NULL;
+
+		/* If the object freeing was deferred, then the real
+		 * free happens now.
+		 * This should fix the inode inconsistency problem.
+		 */
+
+		yaffs_HandleDeferedFree(obj);
+
+		yaffs_GrossUnlock(dev);
+	}
+
+}
+
+/* delete is called when the link count is zero and the inode
+ * is put (ie. nobody wants to know about it anymore, time to
+ * delete the file).
+ * NB Must call clear_inode()
+ */
+static void yaffs_delete_inode(struct inode *inode)
+{
+	yaffs_Object *obj = yaffs_InodeToObject(inode);
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_delete_inode: ino %d, count %d %s\n", (int)inode->i_ino,
+		atomic_read(&inode->i_count),
+		obj ? "object exists" : "null object"));
+
+	if (obj) {
+		dev = obj->myDev;
+		yaffs_GrossLock(dev);
+		yaffs_DeleteObject(obj);
+		yaffs_GrossUnlock(dev);
+	}
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13))
+	truncate_inode_pages(&inode->i_data, 0);
+#endif
+	clear_inode(inode);
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_file_flush(struct file *file, fl_owner_t id)
+#else
+static int yaffs_file_flush(struct file *file)
+#endif
+{
+	yaffs_Object *obj = yaffs_DentryToObject(file->f_dentry);
+
+	yaffs_Device *dev = obj->myDev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_file_flush object %d (%s)\n", obj->objectId,
+		obj->dirty ? "dirty" : "clean"));
+
+	yaffs_GrossLock(dev);
+
+	yaffs_FlushFile(obj, 1);
+
+	yaffs_GrossUnlock(dev);
+
+	return 0;
+}
+
+static int yaffs_readpage_nolock(struct file *f, struct page *pg)
+{
+	/* Lifted from jffs2 */
+
+	yaffs_Object *obj;
+	unsigned char *pg_buf;
+	int ret;
+
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS, ("yaffs_readpage at %08x, size %08x\n",
+			(unsigned)(pg->index << PAGE_CACHE_SHIFT),
+			(unsigned)PAGE_CACHE_SIZE));
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	BUG_ON(!PageLocked(pg));
+#else
+	if (!PageLocked(pg))
+		PAGE_BUG(pg);
+#endif
+
+	pg_buf = kmap(pg);
+	/* FIXME: Can kmap fail? */
+
+	yaffs_GrossLock(dev);
+
+	ret = yaffs_ReadDataFromFile(obj, pg_buf,
+				pg->index << PAGE_CACHE_SHIFT,
+				PAGE_CACHE_SIZE);
+
+	yaffs_GrossUnlock(dev);
+
+	if (ret >= 0)
+		ret = 0;
+
+	if (ret) {
+		ClearPageUptodate(pg);
+		SetPageError(pg);
+	} else {
+		SetPageUptodate(pg);
+		ClearPageError(pg);
+	}
+
+	flush_dcache_page(pg);
+	kunmap(pg);
+
+	T(YAFFS_TRACE_OS, ("yaffs_readpage done\n"));
+	return ret;
+}
+
+static int yaffs_readpage_unlock(struct file *f, struct page *pg)
+{
+	int ret = yaffs_readpage_nolock(f, pg);
+	UnlockPage(pg);
+	return ret;
+}
+
+static int yaffs_readpage(struct file *f, struct page *pg)
+{
+	return yaffs_readpage_unlock(f, pg);
+}
+
+/* writepage inspired by/stolen from smbfs */
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_writepage(struct page *page, struct writeback_control *wbc)
+#else
+static int yaffs_writepage(struct page *page)
+#endif
+{
+	struct address_space *mapping = page->mapping;
+	loff_t offset = (loff_t) page->index << PAGE_CACHE_SHIFT;
+	struct inode *inode;
+	unsigned long end_index;
+	char *buffer;
+	yaffs_Object *obj;
+	int nWritten = 0;
+	unsigned nBytes;
+
+	if (!mapping)
+		BUG();
+	inode = mapping->host;
+	if (!inode)
+		BUG();
+
+	if (offset > inode->i_size) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_writepage at %08x, inode size = %08x!!!\n",
+			(unsigned)(page->index << PAGE_CACHE_SHIFT),
+			(unsigned)inode->i_size));
+		T(YAFFS_TRACE_OS,
+			("                -> don't care!!\n"));
+		unlock_page(page);
+		return 0;
+	}
+
+	end_index = inode->i_size >> PAGE_CACHE_SHIFT;
+
+	/* easy case */
+	if (page->index < end_index)
+		nBytes = PAGE_CACHE_SIZE;
+	else
+		nBytes = inode->i_size & (PAGE_CACHE_SIZE - 1);
+
+	get_page(page);
+
+	buffer = kmap(page);
+
+	obj = yaffs_InodeToObject(inode);
+	yaffs_GrossLock(obj->myDev);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_writepage at %08x, size %08x\n",
+		(unsigned)(page->index << PAGE_CACHE_SHIFT), nBytes));
+	T(YAFFS_TRACE_OS,
+		("writepag0: obj = %05x, ino = %05x\n",
+		(int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
+
+	nWritten = yaffs_WriteDataToFile(obj, buffer,
+			page->index << PAGE_CACHE_SHIFT, nBytes, 0);
+
+	T(YAFFS_TRACE_OS,
+		("writepag1: obj = %05x, ino = %05x\n",
+		(int)obj->variant.fileVariant.fileSize, (int)inode->i_size));
+
+	yaffs_GrossUnlock(obj->myDev);
+
+	kunmap(page);
+	SetPageUptodate(page);
+	UnlockPage(page);
+	put_page(page);
+
+	return (nWritten == nBytes) ? 0 : -ENOSPC;
+}
+
+
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+static int yaffs_write_begin(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned flags,
+				struct page **pagep, void **fsdata)
+{
+	struct page *pg = NULL;
+	pgoff_t index = pos >> PAGE_CACHE_SHIFT;
+	uint32_t offset = pos & (PAGE_CACHE_SIZE - 1);
+	uint32_t to = offset + len;
+
+	int ret = 0;
+	int space_held = 0;
+
+	T(YAFFS_TRACE_OS, ("start yaffs_write_begin\n"));
+	/* Get a page */
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)
+	pg = grab_cache_page_write_begin(mapping, index, flags);
+#else
+	pg = __grab_cache_page(mapping, index);
+#endif
+
+	*pagep = pg;
+	if (!pg) {
+		ret =  -ENOMEM;
+		goto out;
+	}
+	/* Get fs space */
+	space_held = yaffs_hold_space(filp);
+
+	if (!space_held) {
+		ret = -ENOSPC;
+		goto out;
+	}
+
+	/* Update page if required */
+
+	if (!Page_Uptodate(pg) && (offset || to < PAGE_CACHE_SIZE))
+		ret = yaffs_readpage_nolock(filp, pg);
+
+	if (ret)
+		goto out;
+
+	/* Happy path return */
+	T(YAFFS_TRACE_OS, ("end yaffs_write_begin - ok\n"));
+
+	return 0;
+
+out:
+	T(YAFFS_TRACE_OS, ("end yaffs_write_begin fail returning %d\n", ret));
+	if (space_held)
+		yaffs_release_space(filp);
+	if (pg) {
+		unlock_page(pg);
+		page_cache_release(pg);
+	}
+	return ret;
+}
+
+#else
+
+static int yaffs_prepare_write(struct file *f, struct page *pg,
+				unsigned offset, unsigned to)
+{
+	T(YAFFS_TRACE_OS, ("yaffs_prepair_write\n"));
+
+	if (!Page_Uptodate(pg) && (offset || to < PAGE_CACHE_SIZE))
+		return yaffs_readpage_nolock(f, pg);
+	return 0;
+}
+#endif
+
+#if (YAFFS_USE_WRITE_BEGIN_END > 0)
+static int yaffs_write_end(struct file *filp, struct address_space *mapping,
+				loff_t pos, unsigned len, unsigned copied,
+				struct page *pg, void *fsdadata)
+{
+	int ret = 0;
+	void *addr, *kva;
+	uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1);
+
+	kva = kmap(pg);
+	addr = kva + offset_into_page;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_write_end addr %x pos %x nBytes %d\n",
+		(unsigned) addr,
+		(int)pos, copied));
+
+	ret = yaffs_file_write(filp, addr, copied, &pos);
+
+	if (ret != copied) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_write_end not same size ret %d  copied %d\n",
+			ret, copied));
+		SetPageError(pg);
+		ClearPageUptodate(pg);
+	} else {
+		SetPageUptodate(pg);
+	}
+
+	kunmap(pg);
+
+	yaffs_release_space(filp);
+	unlock_page(pg);
+	page_cache_release(pg);
+	return ret;
+}
+#else
+
+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset,
+				unsigned to)
+{
+	void *addr, *kva;
+
+	loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset;
+	int nBytes = to - offset;
+	int nWritten;
+
+	unsigned spos = pos;
+	unsigned saddr;
+
+	kva = kmap(pg);
+	addr = kva + offset;
+
+	saddr = (unsigned) addr;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_commit_write addr %x pos %x nBytes %d\n",
+		saddr, spos, nBytes));
+
+	nWritten = yaffs_file_write(f, addr, nBytes, &pos);
+
+	if (nWritten != nBytes) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_commit_write not same size nWritten %d  nBytes %d\n",
+			nWritten, nBytes));
+		SetPageError(pg);
+		ClearPageUptodate(pg);
+	} else {
+		SetPageUptodate(pg);
+	}
+
+	kunmap(pg);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_commit_write returning %d\n",
+		nWritten == nBytes ? 0 : nWritten));
+
+	return nWritten == nBytes ? 0 : nWritten;
+}
+#endif
+
+
+static void yaffs_FillInodeFromObject(struct inode *inode, yaffs_Object *obj)
+{
+	if (inode && obj) {
+
+
+		/* Check mode against the variant type and attempt to repair if broken. */
+		__u32 mode = obj->yst_mode;
+		switch (obj->variantType) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			if (!S_ISREG(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFREG;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			if (!S_ISLNK(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFLNK;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			if (!S_ISDIR(mode)) {
+				obj->yst_mode &= ~S_IFMT;
+				obj->yst_mode |= S_IFDIR;
+			}
+
+			break;
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+		default:
+			/* TODO? */
+			break;
+		}
+
+		inode->i_flags |= S_NOATIME;
+
+		inode->i_ino = obj->objectId;
+		inode->i_mode = obj->yst_mode;
+		inode->i_uid = obj->yst_uid;
+		inode->i_gid = obj->yst_gid;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+		inode->i_blksize = inode->i_sb->s_blocksize;
+#endif
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+
+		inode->i_rdev = old_decode_dev(obj->yst_rdev);
+		inode->i_atime.tv_sec = (time_t) (obj->yst_atime);
+		inode->i_atime.tv_nsec = 0;
+		inode->i_mtime.tv_sec = (time_t) obj->yst_mtime;
+		inode->i_mtime.tv_nsec = 0;
+		inode->i_ctime.tv_sec = (time_t) obj->yst_ctime;
+		inode->i_ctime.tv_nsec = 0;
+#else
+		inode->i_rdev = obj->yst_rdev;
+		inode->i_atime = obj->yst_atime;
+		inode->i_mtime = obj->yst_mtime;
+		inode->i_ctime = obj->yst_ctime;
+#endif
+		inode->i_size = yaffs_GetObjectFileLength(obj);
+		inode->i_blocks = (inode->i_size + 511) >> 9;
+
+		inode->i_nlink = yaffs_GetObjectLinkCount(obj);
+
+		T(YAFFS_TRACE_OS,
+			("yaffs_FillInode mode %x uid %d gid %d size %d count %d\n",
+			inode->i_mode, inode->i_uid, inode->i_gid,
+			(int)inode->i_size, atomic_read(&inode->i_count)));
+
+		switch (obj->yst_mode & S_IFMT) {
+		default:	/* fifo, device or socket */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+			init_special_inode(inode, obj->yst_mode,
+					old_decode_dev(obj->yst_rdev));
+#else
+			init_special_inode(inode, obj->yst_mode,
+					(dev_t) (obj->yst_rdev));
+#endif
+			break;
+		case S_IFREG:	/* file */
+			inode->i_op = &yaffs_file_inode_operations;
+			inode->i_fop = &yaffs_file_operations;
+			inode->i_mapping->a_ops =
+				&yaffs_file_address_operations;
+			break;
+		case S_IFDIR:	/* directory */
+			inode->i_op = &yaffs_dir_inode_operations;
+			inode->i_fop = &yaffs_dir_operations;
+			break;
+		case S_IFLNK:	/* symlink */
+			inode->i_op = &yaffs_symlink_inode_operations;
+			break;
+		}
+
+		yaffs_InodeToObjectLV(inode) = obj;
+
+		obj->myInode = inode;
+
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_FileInode invalid parameters\n"));
+	}
+
+}
+
+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev,
+				yaffs_Object *obj)
+{
+	struct inode *inode;
+
+	if (!sb) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_get_inode for NULL super_block!!\n"));
+		return NULL;
+
+	}
+
+	if (!obj) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_get_inode for NULL object!!\n"));
+		return NULL;
+
+	}
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_get_inode for object %d\n", obj->objectId));
+
+	inode = Y_IGET(sb, obj->objectId);
+	if (IS_ERR(inode))
+		return NULL;
+
+	/* NB Side effect: iget calls back to yaffs_read_inode(). */
+	/* iget also increments the inode's i_count */
+	/* NB You can't be holding grossLock or deadlock will happen! */
+
+	return inode;
+}
+
+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n,
+				loff_t *pos)
+{
+	yaffs_Object *obj;
+	int nWritten, ipos;
+	struct inode *inode;
+	yaffs_Device *dev;
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	inode = f->f_dentry->d_inode;
+
+	if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND)
+		ipos = inode->i_size;
+	else
+		ipos = *pos;
+
+	if (!obj)
+		T(YAFFS_TRACE_OS,
+			("yaffs_file_write: hey obj is null!\n"));
+	else
+		T(YAFFS_TRACE_OS,
+			("yaffs_file_write about to write writing %zu bytes"
+			"to object %d at %d\n",
+			n, obj->objectId, ipos));
+
+	nWritten = yaffs_WriteDataToFile(obj, buf, ipos, n, 0);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_file_write writing %zu bytes, %d written at %d\n",
+		n, nWritten, ipos));
+
+	if (nWritten > 0) {
+		ipos += nWritten;
+		*pos = ipos;
+		if (ipos > inode->i_size) {
+			inode->i_size = ipos;
+			inode->i_blocks = (ipos + 511) >> 9;
+
+			T(YAFFS_TRACE_OS,
+				("yaffs_file_write size updated to %d bytes, "
+				"%d blocks\n",
+				ipos, (int)(inode->i_blocks)));
+		}
+
+	}
+	yaffs_GrossUnlock(dev);
+	return (nWritten == 0) && (n > 0) ? -ENOSPC : nWritten;
+}
+
+/* Space holding and freeing is done to ensure we have space available for write_begin/end */
+/* For now we just assume few parallel writes and check against a small number. */
+/* Todo: need to do this with a counter to handle parallel reads better */
+
+static ssize_t yaffs_hold_space(struct file *f)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	int nFreeChunks;
+
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	nFreeChunks = yaffs_GetNumberOfFreeChunks(dev);
+
+	yaffs_GrossUnlock(dev);
+
+	return (nFreeChunks > 20) ? 1 : 0;
+}
+
+static void yaffs_release_space(struct file *f)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+
+	yaffs_GrossUnlock(dev);
+}
+
+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+        struct yaffs_SearchContext *sc;
+	struct inode *inode = f->f_dentry->d_inode;
+	unsigned long offset, curoffs;
+	yaffs_Object *l;
+        int retVal = 0;
+
+	char name[YAFFS_MAX_NAME_LENGTH + 1];
+
+	obj = yaffs_DentryToObject(f->f_dentry);
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	offset = f->f_pos;
+
+        sc = yaffs_NewSearch(obj);
+        if(!sc){
+                retVal = -ENOMEM;
+                goto unlock_out;
+        }
+
+	T(YAFFS_TRACE_OS, ("yaffs_readdir: starting at %d\n", (int)offset));
+
+	if (offset == 0) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_readdir: entry . ino %d \n",
+			(int)inode->i_ino));
+		yaffs_GrossUnlock(dev);
+		if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0)
+			goto out;
+		yaffs_GrossLock(dev);
+		offset++;
+		f->f_pos++;
+	}
+	if (offset == 1) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_readdir: entry .. ino %d \n",
+			(int)f->f_dentry->d_parent->d_inode->i_ino));
+		yaffs_GrossUnlock(dev);
+		if (filldir(dirent, "..", 2, offset,
+			f->f_dentry->d_parent->d_inode->i_ino, DT_DIR) < 0)
+			goto out;
+		yaffs_GrossLock(dev);
+		offset++;
+		f->f_pos++;
+	}
+
+	curoffs = 1;
+
+	/* If the directory has changed since the open or last call to
+	   readdir, rewind to after the 2 canned entries. */
+
+	if (f->f_version != inode->i_version) {
+		offset = 2;
+		f->f_pos = offset;
+		f->f_version = inode->i_version;
+	}
+
+	while(sc->nextReturn){
+		curoffs++;
+                l = sc->nextReturn;
+		if (curoffs >= offset) {
+                        int this_inode = yaffs_GetObjectInode(l);
+                        int this_type = yaffs_GetObjectType(l);
+
+			yaffs_GetObjectName(l, name,
+					    YAFFS_MAX_NAME_LENGTH + 1);
+			T(YAFFS_TRACE_OS,
+			  ("yaffs_readdir: %s inode %d\n", name,
+			   yaffs_GetObjectInode(l)));
+
+                        yaffs_GrossUnlock(dev);
+
+			if (filldir(dirent,
+					name,
+					strlen(name),
+					offset,
+					this_inode,
+					this_type) < 0)
+				goto out;
+
+                        yaffs_GrossLock(dev);
+
+			offset++;
+			f->f_pos++;
+		}
+                yaffs_SearchAdvance(sc);
+	}
+
+unlock_out:
+	yaffs_GrossUnlock(dev);
+out:
+        yaffs_EndSearch(sc);
+
+	return retVal;
+}
+
+/*
+ * File creation. Allocate an inode, and we're done..
+ */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
+#define YCRED(x) x
+#else
+#define YCRED(x) (x->cred)
+#endif
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			dev_t rdev)
+#else
+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode,
+			int rdev)
+#endif
+{
+	struct inode *inode;
+
+	yaffs_Object *obj = NULL;
+	yaffs_Device *dev;
+
+	yaffs_Object *parent = yaffs_InodeToObject(dir);
+
+	int error = -ENOSPC;
+	uid_t uid = YCRED(current)->fsuid;
+	gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid;
+
+	if ((dir->i_mode & S_ISGID) && S_ISDIR(mode))
+		mode |= S_ISGID;
+
+	if (parent) {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: parent object %d type %d\n",
+			parent->objectId, parent->variantType));
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: could not get parent object\n"));
+		return -EPERM;
+	}
+
+	T(YAFFS_TRACE_OS, ("yaffs_mknod: making oject for %s, "
+			"mode %x dev %x\n",
+			dentry->d_name.name, mode, rdev));
+
+	dev = parent->myDev;
+
+	yaffs_GrossLock(dev);
+
+	switch (mode & S_IFMT) {
+	default:
+		/* Special (socket, fifo, device...) */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making special\n"));
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+		obj = yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
+				gid, old_encode_dev(rdev));
+#else
+		obj = yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid,
+				gid, rdev);
+#endif
+		break;
+	case S_IFREG:		/* file          */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making file\n"));
+		obj = yaffs_MknodFile(parent, dentry->d_name.name, mode, uid,
+				gid);
+		break;
+	case S_IFDIR:		/* directory */
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod: making directory\n"));
+		obj = yaffs_MknodDirectory(parent, dentry->d_name.name, mode,
+					uid, gid);
+		break;
+	case S_IFLNK:		/* symlink */
+		T(YAFFS_TRACE_OS, ("yaffs_mknod: making symlink\n"));
+		obj = NULL;	/* Do we ever get here? */
+		break;
+	}
+
+	/* Can not call yaffs_get_inode() with gross lock held */
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj);
+		d_instantiate(dentry, inode);
+		update_dir_time(dir);
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod created object %d count = %d\n",
+			obj->objectId, atomic_read(&inode->i_count)));
+		error = 0;
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_mknod failed making object\n"));
+		error = -ENOMEM;
+	}
+
+	return error;
+}
+
+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode)
+{
+	int retVal;
+	T(YAFFS_TRACE_OS, ("yaffs_mkdir\n"));
+	retVal = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0);
+	return retVal;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode,
+			struct nameidata *n)
+#else
+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode)
+#endif
+{
+	T(YAFFS_TRACE_OS, ("yaffs_create\n"));
+	return yaffs_mknod(dir, dentry, mode | S_IFREG, 0);
+}
+
+static int yaffs_unlink(struct inode *dir, struct dentry *dentry)
+{
+	int retVal;
+
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_unlink %d:%s\n", (int)(dir->i_ino),
+		dentry->d_name.name));
+
+	dev = yaffs_InodeToObject(dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	retVal = yaffs_Unlink(yaffs_InodeToObject(dir), dentry->d_name.name);
+
+	if (retVal == YAFFS_OK) {
+		dentry->d_inode->i_nlink--;
+		dir->i_version++;
+		yaffs_GrossUnlock(dev);
+		mark_inode_dirty(dentry->d_inode);
+		update_dir_time(dir);
+		return 0;
+	}
+	yaffs_GrossUnlock(dev);
+	return -ENOTEMPTY;
+}
+
+/*
+ * Create a link...
+ */
+static int yaffs_link(struct dentry *old_dentry, struct inode *dir,
+			struct dentry *dentry)
+{
+	struct inode *inode = old_dentry->d_inode;
+	yaffs_Object *obj = NULL;
+	yaffs_Object *link = NULL;
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS, ("yaffs_link\n"));
+
+	obj = yaffs_InodeToObject(inode);
+	dev = obj->myDev;
+
+	yaffs_GrossLock(dev);
+
+	if (!S_ISDIR(inode->i_mode))		/* Don't link directories */
+		link = yaffs_Link(yaffs_InodeToObject(dir), dentry->d_name.name,
+			obj);
+
+	if (link) {
+		old_dentry->d_inode->i_nlink = yaffs_GetObjectLinkCount(obj);
+		d_instantiate(dentry, old_dentry->d_inode);
+		atomic_inc(&old_dentry->d_inode->i_count);
+		T(YAFFS_TRACE_OS,
+			("yaffs_link link count %d i_count %d\n",
+			old_dentry->d_inode->i_nlink,
+			atomic_read(&old_dentry->d_inode->i_count)));
+	}
+
+	yaffs_GrossUnlock(dev);
+
+	if (link){
+		update_dir_time(dir);
+		return 0;
+	}
+
+	return -EPERM;
+}
+
+static int yaffs_symlink(struct inode *dir, struct dentry *dentry,
+				const char *symname)
+{
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+	uid_t uid = YCRED(current)->fsuid;
+	gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid;
+
+	T(YAFFS_TRACE_OS, ("yaffs_symlink\n"));
+
+	dev = yaffs_InodeToObject(dir)->myDev;
+	yaffs_GrossLock(dev);
+	obj = yaffs_MknodSymLink(yaffs_InodeToObject(dir), dentry->d_name.name,
+				S_IFLNK | S_IRWXUGO, uid, gid, symname);
+	yaffs_GrossUnlock(dev);
+
+	if (obj) {
+		struct inode *inode;
+
+		inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj);
+		d_instantiate(dentry, inode);
+		update_dir_time(dir);
+		T(YAFFS_TRACE_OS, ("symlink created OK\n"));
+		return 0;
+	} else {
+		T(YAFFS_TRACE_OS, ("symlink not created\n"));
+	}
+
+	return -ENOMEM;
+}
+
+static int yaffs_sync_object(struct file *file, struct dentry *dentry,
+				int datasync)
+{
+
+	yaffs_Object *obj;
+	yaffs_Device *dev;
+
+	obj = yaffs_DentryToObject(dentry);
+
+	dev = obj->myDev;
+
+	T(YAFFS_TRACE_OS, ("yaffs_sync_object\n"));
+	yaffs_GrossLock(dev);
+	yaffs_FlushFile(obj, 1);
+	yaffs_GrossUnlock(dev);
+	return 0;
+}
+
+/*
+ * The VFS layer already does all the dentry stuff for rename.
+ *
+ * NB: POSIX says you can rename an object over an old object of the same name
+ */
+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry,
+			struct inode *new_dir, struct dentry *new_dentry)
+{
+	yaffs_Device *dev;
+	int retVal = YAFFS_FAIL;
+	yaffs_Object *target;
+
+	T(YAFFS_TRACE_OS, ("yaffs_rename\n"));
+	dev = yaffs_InodeToObject(old_dir)->myDev;
+
+	yaffs_GrossLock(dev);
+
+	/* Check if the target is an existing directory that is not empty. */
+	target = yaffs_FindObjectByName(yaffs_InodeToObject(new_dir),
+				new_dentry->d_name.name);
+
+
+
+	if (target && target->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+		!ylist_empty(&target->variant.directoryVariant.children)) {
+
+		T(YAFFS_TRACE_OS, ("target is non-empty dir\n"));
+
+		retVal = YAFFS_FAIL;
+	} else {
+		/* Now does unlinking internally using shadowing mechanism */
+		T(YAFFS_TRACE_OS, ("calling yaffs_RenameObject\n"));
+
+		retVal = yaffs_RenameObject(yaffs_InodeToObject(old_dir),
+				old_dentry->d_name.name,
+				yaffs_InodeToObject(new_dir),
+				new_dentry->d_name.name);
+	}
+	yaffs_GrossUnlock(dev);
+
+	if (retVal == YAFFS_OK) {
+		if (target) {
+			new_dentry->d_inode->i_nlink--;
+			mark_inode_dirty(new_dentry->d_inode);
+		}
+		
+		update_dir_time(old_dir);
+		if(old_dir != new_dir)
+			update_dir_time(new_dir);
+		return 0;
+	} else {
+		return -ENOTEMPTY;
+	}
+}
+
+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr)
+{
+	struct inode *inode = dentry->d_inode;
+	int error;
+	yaffs_Device *dev;
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_setattr of object %d\n",
+		yaffs_InodeToObject(inode)->objectId));
+
+	error = inode_change_ok(inode, attr);
+	if (error == 0) {
+		dev = yaffs_InodeToObject(inode)->myDev;
+		yaffs_GrossLock(dev);
+		if (yaffs_SetAttributes(yaffs_InodeToObject(inode), attr) ==
+				YAFFS_OK) {
+			error = 0;
+		} else {
+			error = -EPERM;
+		}
+		yaffs_GrossUnlock(dev);
+		if (!error)
+			error = inode_setattr(inode, attr);
+	}
+	return error;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf)
+{
+	yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev;
+	struct super_block *sb = dentry->d_sb;
+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+#else
+static int yaffs_statfs(struct super_block *sb, struct statfs *buf)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+#endif
+
+	T(YAFFS_TRACE_OS, ("yaffs_statfs\n"));
+
+	yaffs_GrossLock(dev);
+
+	buf->f_type = YAFFS_MAGIC;
+	buf->f_bsize = sb->s_blocksize;
+	buf->f_namelen = 255;
+
+	if (dev->nDataBytesPerChunk & (dev->nDataBytesPerChunk - 1)) {
+		/* Do this if chunk size is not a power of 2 */
+
+		uint64_t bytesInDev;
+		uint64_t bytesFree;
+
+		bytesInDev = ((uint64_t)((dev->endBlock - dev->startBlock + 1))) *
+			((uint64_t)(dev->nChunksPerBlock * dev->nDataBytesPerChunk));
+
+		do_div(bytesInDev, sb->s_blocksize); /* bytesInDev becomes the number of blocks */
+		buf->f_blocks = bytesInDev;
+
+		bytesFree  = ((uint64_t)(yaffs_GetNumberOfFreeChunks(dev))) *
+			((uint64_t)(dev->nDataBytesPerChunk));
+
+		do_div(bytesFree, sb->s_blocksize);
+
+		buf->f_bfree = bytesFree;
+
+	} else if (sb->s_blocksize > dev->nDataBytesPerChunk) {
+
+		buf->f_blocks =
+			(dev->endBlock - dev->startBlock + 1) *
+			dev->nChunksPerBlock /
+			(sb->s_blocksize / dev->nDataBytesPerChunk);
+		buf->f_bfree =
+			yaffs_GetNumberOfFreeChunks(dev) /
+			(sb->s_blocksize / dev->nDataBytesPerChunk);
+	} else {
+		buf->f_blocks =
+			(dev->endBlock - dev->startBlock + 1) *
+			dev->nChunksPerBlock *
+			(dev->nDataBytesPerChunk / sb->s_blocksize);
+
+		buf->f_bfree =
+			yaffs_GetNumberOfFreeChunks(dev) *
+			(dev->nDataBytesPerChunk / sb->s_blocksize);
+	}
+
+	buf->f_files = 0;
+	buf->f_ffree = 0;
+	buf->f_bavail = buf->f_bfree;
+
+	yaffs_GrossUnlock(dev);
+	return 0;
+}
+
+
+static int yaffs_do_sync_fs(struct super_block *sb)
+{
+
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+	T(YAFFS_TRACE_OS, ("yaffs_do_sync_fs\n"));
+
+	if (sb->s_dirt) {
+		yaffs_GrossLock(dev);
+
+		if (dev) {
+			yaffs_FlushEntireDeviceCache(dev);
+			yaffs_CheckpointSave(dev);
+		}
+
+		yaffs_GrossUnlock(dev);
+
+		sb->s_dirt = 0;
+	}
+	return 0;
+}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static void yaffs_write_super(struct super_block *sb)
+#else
+static int yaffs_write_super(struct super_block *sb)
+#endif
+{
+
+	T(YAFFS_TRACE_OS, ("yaffs_write_super\n"));
+	if (yaffs_auto_checkpoint >= 2)
+		yaffs_do_sync_fs(sb);
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
+	return 0;
+#endif
+}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_sync_fs(struct super_block *sb, int wait)
+#else
+static int yaffs_sync_fs(struct super_block *sb)
+#endif
+{
+	T(YAFFS_TRACE_OS, ("yaffs_sync_fs\n"));
+
+	if (yaffs_auto_checkpoint >= 1)
+		yaffs_do_sync_fs(sb);
+
+	return 0;
+}
+
+#ifdef YAFFS_USE_OWN_IGET
+
+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino)
+{
+	struct inode *inode;
+	yaffs_Object *obj;
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_iget for %lu\n", ino));
+
+	inode = iget_locked(sb, ino);
+	if (!inode)
+		return ERR_PTR(-ENOMEM);
+	if (!(inode->i_state & I_NEW))
+		return inode;
+
+	/* NB This is called as a side effect of other functions, but
+	 * we had to release the lock to prevent deadlocks, so
+	 * need to lock again.
+	 */
+
+	yaffs_GrossLock(dev);
+
+	obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
+
+	yaffs_FillInodeFromObject(inode, obj);
+
+	yaffs_GrossUnlock(dev);
+
+	unlock_new_inode(inode);
+	return inode;
+}
+
+#else
+
+static void yaffs_read_inode(struct inode *inode)
+{
+	/* NB This is called as a side effect of other functions, but
+	 * we had to release the lock to prevent deadlocks, so
+	 * need to lock again.
+	 */
+
+	yaffs_Object *obj;
+	yaffs_Device *dev = yaffs_SuperToDevice(inode->i_sb);
+
+	T(YAFFS_TRACE_OS,
+		("yaffs_read_inode for %d\n", (int)inode->i_ino));
+
+	yaffs_GrossLock(dev);
+
+	obj = yaffs_FindObjectByNumber(dev, inode->i_ino);
+
+	yaffs_FillInodeFromObject(inode, obj);
+
+	yaffs_GrossUnlock(dev);
+}
+
+#endif
+
+static YLIST_HEAD(yaffs_dev_list);
+
+#if 0 /* not used */
+static int yaffs_remount_fs(struct super_block *sb, int *flags, char *data)
+{
+	yaffs_Device    *dev = yaffs_SuperToDevice(sb);
+
+	if (*flags & MS_RDONLY) {
+		struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice;
+
+		T(YAFFS_TRACE_OS,
+			("yaffs_remount_fs: %s: RO\n", dev->name));
+
+		yaffs_GrossLock(dev);
+
+		yaffs_FlushEntireDeviceCache(dev);
+
+		yaffs_CheckpointSave(dev);
+
+		if (mtd->sync)
+			mtd->sync(mtd);
+
+		yaffs_GrossUnlock(dev);
+	} else {
+		T(YAFFS_TRACE_OS,
+			("yaffs_remount_fs: %s: RW\n", dev->name));
+	}
+
+	return 0;
+}
+#endif
+
+static void yaffs_put_super(struct super_block *sb)
+{
+	yaffs_Device *dev = yaffs_SuperToDevice(sb);
+
+	T(YAFFS_TRACE_OS, ("yaffs_put_super\n"));
+
+	yaffs_GrossLock(dev);
+
+	yaffs_FlushEntireDeviceCache(dev);
+
+	yaffs_CheckpointSave(dev);
+
+	if (dev->putSuperFunc)
+		dev->putSuperFunc(sb);
+
+	yaffs_Deinitialise(dev);
+
+	yaffs_GrossUnlock(dev);
+
+	/* we assume this is protected by lock_kernel() in mount/umount */
+	ylist_del(&dev->devList);
+
+	if (dev->spareBuffer) {
+		YFREE(dev->spareBuffer);
+		dev->spareBuffer = NULL;
+	}
+
+	kfree(dev);
+}
+
+
+static void yaffs_MTDPutSuper(struct super_block *sb)
+{
+	struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice;
+
+	if (mtd->sync)
+		mtd->sync(mtd);
+
+	put_mtd_device(mtd);
+}
+
+
+static void yaffs_MarkSuperBlockDirty(void *vsb)
+{
+	struct super_block *sb = (struct super_block *)vsb;
+
+	T(YAFFS_TRACE_OS, ("yaffs_MarkSuperBlockDirty() sb = %p\n", sb));
+	if (sb)
+		sb->s_dirt = 1;
+}
+
+typedef struct {
+	int inband_tags;
+	int skip_checkpoint_read;
+	int skip_checkpoint_write;
+	int no_cache;
+	int empty_lost_and_found_overridden;
+	int empty_lost_and_found;
+} yaffs_options;
+
+#define MAX_OPT_LEN 20
+static int yaffs_parse_options(yaffs_options *options, const char *options_str)
+{
+	char cur_opt[MAX_OPT_LEN + 1];
+	int p;
+	int error = 0;
+
+	/* Parse through the options which is a comma seperated list */
+
+	while (options_str && *options_str && !error) {
+		memset(cur_opt, 0, MAX_OPT_LEN + 1);
+		p = 0;
+
+		while (*options_str == ',')
+			options_str++;
+
+		while (*options_str && *options_str != ',') {
+			if (p < MAX_OPT_LEN) {
+				cur_opt[p] = *options_str;
+				p++;
+			}
+			options_str++;
+		}
+
+		if (!strcmp(cur_opt, "inband-tags"))
+			options->inband_tags = 1;
+		else if (!strcmp(cur_opt, "no-cache"))
+			options->no_cache = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint-read"))
+			options->skip_checkpoint_read = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint-write"))
+			options->skip_checkpoint_write = 1;
+		else if (!strcmp(cur_opt, "no-checkpoint")) {
+			options->skip_checkpoint_read = 1;
+			options->skip_checkpoint_write = 1;
+		} else if (!strcmp(cur_opt, "empty-lost-and-found-disable")) {
+			options->empty_lost_and_found = 0;
+			options->empty_lost_and_found_overridden = 1;
+		} else if (!strcmp(cur_opt, "empty-lost-and-found-enable")) {
+			options->empty_lost_and_found = 1;
+			options->empty_lost_and_found_overridden = 1;
+		} else {
+			printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n",
+					cur_opt);
+			error = 1;
+		}
+	}
+
+	return error;
+}
+
+static struct super_block *yaffs_internal_read_super(int yaffsVersion,
+						struct super_block *sb,
+						void *data, int silent)
+{
+	int nBlocks;
+	struct inode *inode = NULL;
+	struct dentry *root;
+	yaffs_Device *dev = 0;
+	char devname_buf[BDEVNAME_SIZE + 1];
+	struct mtd_info *mtd;
+	int err;
+	char *data_str = (char *)data;
+
+	yaffs_options options;
+
+	sb->s_magic = YAFFS_MAGIC;
+	sb->s_op = &yaffs_super_ops;
+	sb->s_flags |= MS_NOATIME;
+
+	if (!sb)
+		printk(KERN_INFO "yaffs: sb is NULL\n");
+	else if (!sb->s_dev)
+		printk(KERN_INFO "yaffs: sb->s_dev is NULL\n");
+	else if (!yaffs_devname(sb, devname_buf))
+		printk(KERN_INFO "yaffs: devname is NULL\n");
+	else
+		printk(KERN_INFO "yaffs: dev is %d name is \"%s\"\n",
+		       sb->s_dev,
+		       yaffs_devname(sb, devname_buf));
+
+	if (!data_str)
+		data_str = "";
+
+	printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str);
+
+	memset(&options, 0, sizeof(options));
+
+	if (yaffs_parse_options(&options, data_str)) {
+		/* Option parsing failed */
+		return NULL;
+	}
+
+
+	sb->s_blocksize = PAGE_CACHE_SIZE;
+	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: Using yaffs%d\n", yaffsVersion));
+	T(YAFFS_TRACE_OS,
+	  ("yaffs_read_super: block size %d\n", (int)(sb->s_blocksize)));
+
+#ifdef CONFIG_YAFFS_DISABLE_WRITE_VERIFY
+	T(YAFFS_TRACE_OS,
+	  ("yaffs: Write verification disabled. All guarantees "
+	   "null and void\n"));
+#endif
+
+	T(YAFFS_TRACE_ALWAYS, ("yaffs: Attempting MTD mount on %u.%u, "
+			       "\"%s\"\n",
+			       MAJOR(sb->s_dev), MINOR(sb->s_dev),
+			       yaffs_devname(sb, devname_buf)));
+
+	/* Check it's an mtd device..... */
+	if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR)
+		return NULL;	/* This isn't an mtd device */
+
+	/* Get the device */
+	mtd = get_mtd_device(NULL, MINOR(sb->s_dev));
+	if (!mtd) {
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs: MTD device #%u doesn't appear to exist\n",
+		   MINOR(sb->s_dev)));
+		return NULL;
+	}
+	/* Check it's NAND */
+	if (mtd->type != MTD_NANDFLASH) {
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs: MTD device is not NAND it's type %d\n", mtd->type));
+		return NULL;
+	}
+
+	T(YAFFS_TRACE_OS, (" erase %p\n", mtd->erase));
+	T(YAFFS_TRACE_OS, (" read %p\n", mtd->read));
+	T(YAFFS_TRACE_OS, (" write %p\n", mtd->write));
+	T(YAFFS_TRACE_OS, (" readoob %p\n", mtd->read_oob));
+	T(YAFFS_TRACE_OS, (" writeoob %p\n", mtd->write_oob));
+	T(YAFFS_TRACE_OS, (" block_isbad %p\n", mtd->block_isbad));
+	T(YAFFS_TRACE_OS, (" block_markbad %p\n", mtd->block_markbad));
+	T(YAFFS_TRACE_OS, (" %s %d\n", WRITE_SIZE_STR, WRITE_SIZE(mtd)));
+	T(YAFFS_TRACE_OS, (" oobsize %d\n", mtd->oobsize));
+	T(YAFFS_TRACE_OS, (" erasesize %d\n", mtd->erasesize));
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)
+	T(YAFFS_TRACE_OS, (" size %u\n", mtd->size));
+#else
+	T(YAFFS_TRACE_OS, (" size %lld\n", mtd->size));
+#endif
+
+
+#ifdef CONFIG_YAFFS_EMPTY_LOST_AND_FOUND
+	dev->emptyLostAndFound = 1;
+#endif
+	if(options.empty_lost_and_found_overridden)
+		dev->emptyLostAndFound = options.empty_lost_and_found;
+
+#ifdef CONFIG_YAFFS_AUTO_YAFFS2
+
+	if (yaffsVersion == 1 && WRITE_SIZE(mtd) >= 2048) {
+		T(YAFFS_TRACE_ALWAYS, ("yaffs: auto selecting yaffs2\n"));
+		yaffsVersion = 2;
+	}
+
+	/* Added NCB 26/5/2006 for completeness */
+	if (yaffsVersion == 2 && !options.inband_tags && WRITE_SIZE(mtd) == 512) {
+		T(YAFFS_TRACE_ALWAYS, ("yaffs: auto selecting yaffs1\n"));
+		yaffsVersion = 1;
+	}
+
+#endif
+
+	if (yaffsVersion == 2) {
+		/* Check for version 2 style functions */
+		if (!mtd->erase ||
+		    !mtd->block_isbad ||
+		    !mtd->block_markbad ||
+		    !mtd->read ||
+		    !mtd->write ||
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		    !mtd->read_oob || !mtd->write_oob) {
+#else
+		    !mtd->write_ecc ||
+		    !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
+#endif
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support required "
+			   "functions\n"));;
+			return NULL;
+		}
+
+		if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE ||
+		    mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) &&
+		    !options.inband_tags) {
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not have the "
+			   "right page sizes\n"));
+			return NULL;
+		}
+	} else {
+		/* Check for V1 style functions */
+		if (!mtd->erase ||
+		    !mtd->read ||
+		    !mtd->write ||
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		    !mtd->read_oob || !mtd->write_oob) {
+#else
+		    !mtd->write_ecc ||
+		    !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) {
+#endif
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support required "
+			   "functions\n"));;
+			return NULL;
+		}
+
+		if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK ||
+		    mtd->oobsize != YAFFS_BYTES_PER_SPARE) {
+			T(YAFFS_TRACE_ALWAYS,
+			  ("yaffs: MTD device does not support have the "
+			   "right page sizes\n"));
+			return NULL;
+		}
+	}
+
+	/* OK, so if we got here, we have an MTD that's NAND and looks
+	 * like it has the right capabilities
+	 * Set the yaffs_Device up for mtd
+	 */
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+	sb->s_fs_info = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL);
+#else
+	sb->u.generic_sbp = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL);
+#endif
+	if (!dev) {
+		/* Deep shit could not allocate device structure */
+		T(YAFFS_TRACE_ALWAYS,
+		  ("yaffs_read_super: Failed trying to allocate "
+		   "yaffs_Device. \n"));
+		return NULL;
+	}
+
+	memset(dev, 0, sizeof(yaffs_Device));
+	dev->genericDevice = mtd;
+	dev->name = mtd->name;
+
+	/* Set up the memory size parameters.... */
+
+	nBlocks = YCALCBLOCKS(mtd->size, (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK));
+
+	dev->startBlock = 0;
+	dev->endBlock = nBlocks - 1;
+	dev->nChunksPerBlock = YAFFS_CHUNKS_PER_BLOCK;
+	dev->totalBytesPerChunk = YAFFS_BYTES_PER_CHUNK;
+	dev->nReservedBlocks = 5;
+	dev->nShortOpCaches = (options.no_cache) ? 0 : 10;
+	dev->inbandTags = options.inband_tags;
+
+	/* ... and the functions. */
+	if (yaffsVersion == 2) {
+		dev->writeChunkWithTagsToNAND =
+		    nandmtd2_WriteChunkWithTagsToNAND;
+		dev->readChunkWithTagsFromNAND =
+		    nandmtd2_ReadChunkWithTagsFromNAND;
+		dev->markNANDBlockBad = nandmtd2_MarkNANDBlockBad;
+		dev->queryNANDBlock = nandmtd2_QueryNANDBlock;
+		dev->spareBuffer = YMALLOC(mtd->oobsize);
+		dev->isYaffs2 = 1;
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		dev->totalBytesPerChunk = mtd->writesize;
+		dev->nChunksPerBlock = mtd->erasesize / mtd->writesize;
+#else
+		dev->totalBytesPerChunk = mtd->oobblock;
+		dev->nChunksPerBlock = mtd->erasesize / mtd->oobblock;
+#endif
+		nBlocks = YCALCBLOCKS(mtd->size, mtd->erasesize);
+
+		dev->startBlock = 0;
+		dev->endBlock = nBlocks - 1;
+	} else {
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+		/* use the MTD interface in yaffs_mtdif1.c */
+		dev->writeChunkWithTagsToNAND =
+			nandmtd1_WriteChunkWithTagsToNAND;
+		dev->readChunkWithTagsFromNAND =
+			nandmtd1_ReadChunkWithTagsFromNAND;
+		dev->markNANDBlockBad = nandmtd1_MarkNANDBlockBad;
+		dev->queryNANDBlock = nandmtd1_QueryNANDBlock;
+#else
+		dev->writeChunkToNAND = nandmtd_WriteChunkToNAND;
+		dev->readChunkFromNAND = nandmtd_ReadChunkFromNAND;
+#endif
+		dev->isYaffs2 = 0;
+	}
+	/* ... and common functions */
+	dev->eraseBlockInNAND = nandmtd_EraseBlockInNAND;
+	dev->initialiseNAND = nandmtd_InitialiseNAND;
+
+	dev->putSuperFunc = yaffs_MTDPutSuper;
+
+	dev->superBlock = (void *)sb;
+	dev->markSuperBlockDirty = yaffs_MarkSuperBlockDirty;
+
+
+#ifndef CONFIG_YAFFS_DOES_ECC
+	dev->useNANDECC = 1;
+#endif
+
+#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES
+	dev->wideTnodesDisabled = 1;
+#endif
+
+	dev->skipCheckpointRead = options.skip_checkpoint_read;
+	dev->skipCheckpointWrite = options.skip_checkpoint_write;
+
+	/* we assume this is protected by lock_kernel() in mount/umount */
+	ylist_add_tail(&dev->devList, &yaffs_dev_list);
+
+        /* Directory search handling...*/
+        YINIT_LIST_HEAD(&dev->searchContexts);
+        dev->removeObjectCallback = yaffs_RemoveObjectCallback;
+
+	init_MUTEX(&dev->grossLock);
+
+	yaffs_GrossLock(dev);
+
+	err = yaffs_GutsInitialise(dev);
+
+	T(YAFFS_TRACE_OS,
+	  ("yaffs_read_super: guts initialised %s\n",
+	   (err == YAFFS_OK) ? "OK" : "FAILED"));
+
+	/* Release lock before yaffs_get_inode() */
+	yaffs_GrossUnlock(dev);
+
+	/* Create root inode */
+	if (err == YAFFS_OK)
+		inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0,
+					yaffs_Root(dev));
+
+	if (!inode)
+		return NULL;
+
+	inode->i_op = &yaffs_dir_inode_operations;
+	inode->i_fop = &yaffs_dir_operations;
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: got root inode\n"));
+
+	root = d_alloc_root(inode);
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: d_alloc_root done\n"));
+
+	if (!root) {
+		iput(inode);
+		return NULL;
+	}
+	sb->s_root = root;
+	sb->s_dirt = !dev->isCheckpointed;
+	T(YAFFS_TRACE_ALWAYS,
+	  ("yaffs_read_super: isCheckpointed %d\n", dev->isCheckpointed));
+
+	T(YAFFS_TRACE_OS, ("yaffs_read_super: done\n"));
+	return sb;
+}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data,
+					 int silent)
+{
+	return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs_read_super(struct file_system_type *fs,
+			    int flags, const char *dev_name,
+			    void *data, struct vfsmount *mnt)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs_internal_read_super_mtd, mnt);
+}
+#else
+static struct super_block *yaffs_read_super(struct file_system_type *fs,
+					    int flags, const char *dev_name,
+					    void *data)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs_internal_read_super_mtd);
+}
+#endif
+
+static struct file_system_type yaffs_fs_type = {
+	.owner = THIS_MODULE,
+	.name = "yaffs",
+	.get_sb = yaffs_read_super,
+	.kill_sb = kill_block_super,
+	.fs_flags = FS_REQUIRES_DEV,
+};
+#else
+static struct super_block *yaffs_read_super(struct super_block *sb, void *data,
+					    int silent)
+{
+	return yaffs_internal_read_super(1, sb, data, silent);
+}
+
+static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super,
+		      FS_REQUIRES_DEV);
+#endif
+
+
+#ifdef CONFIG_YAFFS_YAFFS2
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data,
+					  int silent)
+{
+	return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL;
+}
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+static int yaffs2_read_super(struct file_system_type *fs,
+			int flags, const char *dev_name, void *data,
+			struct vfsmount *mnt)
+{
+	return get_sb_bdev(fs, flags, dev_name, data,
+			yaffs2_internal_read_super_mtd, mnt);
+}
+#else
+static struct super_block *yaffs2_read_super(struct file_system_type *fs,
+					     int flags, const char *dev_name,
+					     void *data)
+{
+
+	return get_sb_bdev(fs, flags, dev_name, data,
+			   yaffs2_internal_read_super_mtd);
+}
+#endif
+
+static struct file_system_type yaffs2_fs_type = {
+	.owner = THIS_MODULE,
+	.name = "yaffs2",
+	.get_sb = yaffs2_read_super,
+	.kill_sb = kill_block_super,
+	.fs_flags = FS_REQUIRES_DEV,
+};
+#else
+static struct super_block *yaffs2_read_super(struct super_block *sb,
+					     void *data, int silent)
+{
+	return yaffs_internal_read_super(2, sb, data, silent);
+}
+
+static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super,
+		      FS_REQUIRES_DEV);
+#endif
+
+#endif				/* CONFIG_YAFFS_YAFFS2 */
+
+static struct proc_dir_entry *my_proc_entry;
+
+static char *yaffs_dump_dev(char *buf, yaffs_Device * dev)
+{
+	buf += sprintf(buf, "startBlock......... %d\n", dev->startBlock);
+	buf += sprintf(buf, "endBlock........... %d\n", dev->endBlock);
+	buf += sprintf(buf, "totalBytesPerChunk. %d\n", dev->totalBytesPerChunk);
+	buf += sprintf(buf, "nDataBytesPerChunk. %d\n", dev->nDataBytesPerChunk);
+	buf += sprintf(buf, "chunkGroupBits..... %d\n", dev->chunkGroupBits);
+	buf += sprintf(buf, "chunkGroupSize..... %d\n", dev->chunkGroupSize);
+	buf += sprintf(buf, "nErasedBlocks...... %d\n", dev->nErasedBlocks);
+	buf += sprintf(buf, "nReservedBlocks.... %d\n", dev->nReservedBlocks);
+	buf += sprintf(buf, "blocksInCheckpoint. %d\n", dev->blocksInCheckpoint);
+	buf += sprintf(buf, "nTnodesCreated..... %d\n", dev->nTnodesCreated);
+	buf += sprintf(buf, "nFreeTnodes........ %d\n", dev->nFreeTnodes);
+	buf += sprintf(buf, "nObjectsCreated.... %d\n", dev->nObjectsCreated);
+	buf += sprintf(buf, "nFreeObjects....... %d\n", dev->nFreeObjects);
+	buf += sprintf(buf, "nFreeChunks........ %d\n", dev->nFreeChunks);
+	buf += sprintf(buf, "nPageWrites........ %d\n", dev->nPageWrites);
+	buf += sprintf(buf, "nPageReads......... %d\n", dev->nPageReads);
+	buf += sprintf(buf, "nBlockErasures..... %d\n", dev->nBlockErasures);
+	buf += sprintf(buf, "nGCCopies.......... %d\n", dev->nGCCopies);
+	buf += sprintf(buf, "garbageCollections. %d\n", dev->garbageCollections);
+	buf += sprintf(buf, "passiveGCs......... %d\n",
+		    dev->passiveGarbageCollections);
+	buf += sprintf(buf, "nRetriedWrites..... %d\n", dev->nRetriedWrites);
+	buf += sprintf(buf, "nShortOpCaches..... %d\n", dev->nShortOpCaches);
+	buf += sprintf(buf, "nRetireBlocks...... %d\n", dev->nRetiredBlocks);
+	buf += sprintf(buf, "eccFixed........... %d\n", dev->eccFixed);
+	buf += sprintf(buf, "eccUnfixed......... %d\n", dev->eccUnfixed);
+	buf += sprintf(buf, "tagsEccFixed....... %d\n", dev->tagsEccFixed);
+	buf += sprintf(buf, "tagsEccUnfixed..... %d\n", dev->tagsEccUnfixed);
+	buf += sprintf(buf, "cacheHits.......... %d\n", dev->cacheHits);
+	buf += sprintf(buf, "nDeletedFiles...... %d\n", dev->nDeletedFiles);
+	buf += sprintf(buf, "nUnlinkedFiles..... %d\n", dev->nUnlinkedFiles);
+	buf +=
+	    sprintf(buf, "nBackgroudDeletions %d\n", dev->nBackgroundDeletions);
+	buf += sprintf(buf, "useNANDECC......... %d\n", dev->useNANDECC);
+	buf += sprintf(buf, "isYaffs2........... %d\n", dev->isYaffs2);
+	buf += sprintf(buf, "inbandTags......... %d\n", dev->inbandTags);
+
+	return buf;
+}
+
+static int yaffs_proc_read(char *page,
+			   char **start,
+			   off_t offset, int count, int *eof, void *data)
+{
+	struct ylist_head *item;
+	char *buf = page;
+	int step = offset;
+	int n = 0;
+
+	/* Get proc_file_read() to step 'offset' by one on each sucessive call.
+	 * We use 'offset' (*ppos) to indicate where we are in devList.
+	 * This also assumes the user has posted a read buffer large
+	 * enough to hold the complete output; but that's life in /proc.
+	 */
+
+	*(int *)start = 1;
+
+	/* Print header first */
+	if (step == 0) {
+		buf += sprintf(buf, "YAFFS built:" __DATE__ " " __TIME__
+			       "\n%s\n%s\n", yaffs_fs_c_version,
+			       yaffs_guts_c_version);
+	}
+
+	/* hold lock_kernel while traversing yaffs_dev_list */
+	lock_kernel();
+
+	/* Locate and print the Nth entry.  Order N-squared but N is small. */
+	ylist_for_each(item, &yaffs_dev_list) {
+		yaffs_Device *dev = ylist_entry(item, yaffs_Device, devList);
+		if (n < step) {
+			n++;
+			continue;
+		}
+		buf += sprintf(buf, "\nDevice %d \"%s\"\n", n, dev->name);
+		buf = yaffs_dump_dev(buf, dev);
+		break;
+	}
+	unlock_kernel();
+
+	return buf - page < count ? buf - page : count;
+}
+
+/**
+ * Set the verbosity of the warnings and error messages.
+ *
+ * Note that the names can only be a..z or _ with the current code.
+ */
+
+static struct {
+	char *mask_name;
+	unsigned mask_bitfield;
+} mask_flags[] = {
+	{"allocate", YAFFS_TRACE_ALLOCATE},
+	{"always", YAFFS_TRACE_ALWAYS},
+	{"bad_blocks", YAFFS_TRACE_BAD_BLOCKS},
+	{"buffers", YAFFS_TRACE_BUFFERS},
+	{"bug", YAFFS_TRACE_BUG},
+	{"checkpt", YAFFS_TRACE_CHECKPOINT},
+	{"deletion", YAFFS_TRACE_DELETION},
+	{"erase", YAFFS_TRACE_ERASE},
+	{"error", YAFFS_TRACE_ERROR},
+	{"gc_detail", YAFFS_TRACE_GC_DETAIL},
+	{"gc", YAFFS_TRACE_GC},
+	{"mtd", YAFFS_TRACE_MTD},
+	{"nandaccess", YAFFS_TRACE_NANDACCESS},
+	{"os", YAFFS_TRACE_OS},
+	{"scan_debug", YAFFS_TRACE_SCAN_DEBUG},
+	{"scan", YAFFS_TRACE_SCAN},
+	{"tracing", YAFFS_TRACE_TRACING},
+
+	{"verify", YAFFS_TRACE_VERIFY},
+	{"verify_nand", YAFFS_TRACE_VERIFY_NAND},
+	{"verify_full", YAFFS_TRACE_VERIFY_FULL},
+	{"verify_all", YAFFS_TRACE_VERIFY_ALL},
+
+	{"write", YAFFS_TRACE_WRITE},
+	{"all", 0xffffffff},
+	{"none", 0},
+	{NULL, 0},
+};
+
+#define MAX_MASK_NAME_LENGTH 40
+static int yaffs_proc_write(struct file *file, const char *buf,
+					 unsigned long count, void *data)
+{
+	unsigned rg = 0, mask_bitfield;
+	char *end;
+	char *mask_name;
+	const char *x;
+	char substring[MAX_MASK_NAME_LENGTH + 1];
+	int i;
+	int done = 0;
+	int add, len = 0;
+	int pos = 0;
+
+	rg = yaffs_traceMask;
+
+	while (!done && (pos < count)) {
+		done = 1;
+		while ((pos < count) && isspace(buf[pos]))
+			pos++;
+
+		switch (buf[pos]) {
+		case '+':
+		case '-':
+		case '=':
+			add = buf[pos];
+			pos++;
+			break;
+
+		default:
+			add = ' ';
+			break;
+		}
+		mask_name = NULL;
+
+		mask_bitfield = simple_strtoul(buf + pos, &end, 0);
+
+		if (end > buf + pos) {
+			mask_name = "numeral";
+			len = end - (buf + pos);
+			pos += len;
+			done = 0;
+		} else {
+			for (x = buf + pos, i = 0;
+			    (*x == '_' || (*x >= 'a' && *x <= 'z')) &&
+			    i < MAX_MASK_NAME_LENGTH; x++, i++, pos++)
+				substring[i] = *x;
+			substring[i] = '\0';
+
+			for (i = 0; mask_flags[i].mask_name != NULL; i++) {
+				if (strcmp(substring, mask_flags[i].mask_name) == 0) {
+					mask_name = mask_flags[i].mask_name;
+					mask_bitfield = mask_flags[i].mask_bitfield;
+					done = 0;
+					break;
+				}
+			}
+		}
+
+		if (mask_name != NULL) {
+			done = 0;
+			switch (add) {
+			case '-':
+				rg &= ~mask_bitfield;
+				break;
+			case '+':
+				rg |= mask_bitfield;
+				break;
+			case '=':
+				rg = mask_bitfield;
+				break;
+			default:
+				rg |= mask_bitfield;
+				break;
+			}
+		}
+	}
+
+	yaffs_traceMask = rg | YAFFS_TRACE_ALWAYS;
+
+	printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_traceMask);
+
+	if (rg & YAFFS_TRACE_ALWAYS) {
+		for (i = 0; mask_flags[i].mask_name != NULL; i++) {
+			char flag;
+			flag = ((rg & mask_flags[i].mask_bitfield) == mask_flags[i].mask_bitfield) ? '+' : '-';
+			printk(KERN_DEBUG "%c%s\n", flag, mask_flags[i].mask_name);
+		}
+	}
+
+	return count;
+}
+
+/* Stuff to handle installation of file systems */
+struct file_system_to_install {
+	struct file_system_type *fst;
+	int installed;
+};
+
+static struct file_system_to_install fs_to_install[] = {
+	{&yaffs_fs_type, 0},
+	{&yaffs2_fs_type, 0},
+	{NULL, 0}
+};
+
+static int __init init_yaffs_fs(void)
+{
+	int error = 0;
+	struct file_system_to_install *fsinst;
+
+	T(YAFFS_TRACE_ALWAYS,
+	  ("yaffs " __DATE__ " " __TIME__ " Installing. \n"));
+
+	/* Install the proc_fs entry */
+	my_proc_entry = create_proc_entry("yaffs",
+					       S_IRUGO | S_IFREG,
+					       YPROC_ROOT);
+
+	if (my_proc_entry) {
+		my_proc_entry->write_proc = yaffs_proc_write;
+		my_proc_entry->read_proc = yaffs_proc_read;
+		my_proc_entry->data = NULL;
+	} else
+		return -ENOMEM;
+
+	/* Now add the file system entries */
+
+	fsinst = fs_to_install;
+
+	while (fsinst->fst && !error) {
+		error = register_filesystem(fsinst->fst);
+		if (!error)
+			fsinst->installed = 1;
+		fsinst++;
+	}
+
+	/* Any errors? uninstall  */
+	if (error) {
+		fsinst = fs_to_install;
+
+		while (fsinst->fst) {
+			if (fsinst->installed) {
+				unregister_filesystem(fsinst->fst);
+				fsinst->installed = 0;
+			}
+			fsinst++;
+		}
+	}
+
+	return error;
+}
+
+static void __exit exit_yaffs_fs(void)
+{
+
+	struct file_system_to_install *fsinst;
+
+	T(YAFFS_TRACE_ALWAYS, ("yaffs " __DATE__ " " __TIME__
+			       " removing. \n"));
+
+	remove_proc_entry("yaffs", YPROC_ROOT);
+
+	fsinst = fs_to_install;
+
+	while (fsinst->fst) {
+		if (fsinst->installed) {
+			unregister_filesystem(fsinst->fst);
+			fsinst->installed = 0;
+		}
+		fsinst++;
+	}
+}
+
+module_init(init_yaffs_fs)
+module_exit(exit_yaffs_fs)
+
+MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system");
+MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2006");
+MODULE_LICENSE("GPL");
diff --git a/fs/yaffs2/yaffs_getblockinfo.h b/fs/yaffs2/yaffs_getblockinfo.h
new file mode 100644
index 00000000000..5b0a1ac24bf
--- /dev/null
+++ b/fs/yaffs2/yaffs_getblockinfo.h
@@ -0,0 +1,34 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_GETBLOCKINFO_H__
+#define __YAFFS_GETBLOCKINFO_H__
+
+#include "yaffs_guts.h"
+
+/* Function to manipulate block info */
+static Y_INLINE yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("**>> yaffs: getBlockInfo block %d is not valid" TENDSTR),
+		   blk));
+		YBUG();
+	}
+	return &dev->blockInfo[blk - dev->internalStartBlock];
+}
+
+#endif
diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
new file mode 100644
index 00000000000..f10e852b3ff
--- /dev/null
+++ b/fs/yaffs2/yaffs_guts.c
@@ -0,0 +1,7784 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_guts_c_version =
+    "$Id$";
+
+#include "yportenv.h"
+
+#include "yaffsinterface.h"
+#include "yaffs_guts.h"
+#include "yaffs_tagsvalidity.h"
+#include "yaffs_getblockinfo.h"
+
+#include "yaffs_tagscompat.h"
+#ifndef CONFIG_YAFFS_USE_OWN_SORT
+#include "yaffs_qsort.h"
+#endif
+#include "yaffs_nand.h"
+
+#include "yaffs_checkptrw.h"
+
+#include "yaffs_nand.h"
+#include "yaffs_packedtags2.h"
+
+
+#define YAFFS_PASSIVE_GC_CHUNKS 2
+
+#include "yaffs_ecc.h"
+
+
+/* Robustification (if it ever comes about...) */
+static void yaffs_RetireBlock(yaffs_Device *dev, int blockInNAND);
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND,
+		int erasedOk);
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags);
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				const yaffs_ExtendedTags *tags);
+
+/* Other local prototypes */
+static void yaffs_UpdateParent(yaffs_Object *obj);
+static int yaffs_UnlinkObject(yaffs_Object *obj);
+static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj);
+
+static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList);
+
+static int yaffs_WriteNewChunkWithTagsToNAND(yaffs_Device *dev,
+					const __u8 *buffer,
+					yaffs_ExtendedTags *tags,
+					int useReserve);
+static int yaffs_PutChunkIntoFile(yaffs_Object *in, int chunkInInode,
+				int chunkInNAND, int inScan);
+
+static yaffs_Object *yaffs_CreateNewObject(yaffs_Device *dev, int number,
+					yaffs_ObjectType type);
+static void yaffs_AddObjectToDirectory(yaffs_Object *directory,
+				yaffs_Object *obj);
+static int yaffs_UpdateObjectHeader(yaffs_Object *in, const YCHAR *name,
+				int force, int isShrink, int shadows);
+static void yaffs_RemoveObjectFromDirectory(yaffs_Object *obj);
+static int yaffs_CheckStructures(void);
+static int yaffs_DeleteWorker(yaffs_Object *in, yaffs_Tnode *tn, __u32 level,
+			int chunkOffset, int *limit);
+static int yaffs_DoGenericObjectDeletion(yaffs_Object *in);
+
+static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device *dev, int blockNo);
+
+
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND);
+
+static int yaffs_UnlinkWorker(yaffs_Object *obj);
+
+static int yaffs_TagsMatch(const yaffs_ExtendedTags *tags, int objectId,
+			int chunkInObject);
+
+static int yaffs_AllocateChunk(yaffs_Device *dev, int useReserve,
+				yaffs_BlockInfo **blockUsedPtr);
+
+static void yaffs_VerifyFreeChunks(yaffs_Device *dev);
+
+static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in);
+
+static void yaffs_VerifyDirectory(yaffs_Object *directory);
+#ifdef YAFFS_PARANOID
+static int yaffs_CheckFileSanity(yaffs_Object *in);
+#else
+#define yaffs_CheckFileSanity(in)
+#endif
+
+static void yaffs_InvalidateWholeChunkCache(yaffs_Object *in);
+static void yaffs_InvalidateChunkCache(yaffs_Object *object, int chunkId);
+
+static void yaffs_InvalidateCheckpoint(yaffs_Device *dev);
+
+static int yaffs_FindChunkInFile(yaffs_Object *in, int chunkInInode,
+				yaffs_ExtendedTags *tags);
+
+static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn,
+		unsigned pos);
+static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId);
+
+/* Function to calculate chunk and offset */
+
+static void yaffs_AddrToChunk(yaffs_Device *dev, loff_t addr, int *chunkOut,
+		__u32 *offsetOut)
+{
+	int chunk;
+	__u32 offset;
+
+	chunk  = (__u32)(addr >> dev->chunkShift);
+
+	if (dev->chunkDiv == 1) {
+		/* easy power of 2 case */
+		offset = (__u32)(addr & dev->chunkMask);
+	} else {
+		/* Non power-of-2 case */
+
+		loff_t chunkBase;
+
+		chunk /= dev->chunkDiv;
+
+		chunkBase = ((loff_t)chunk) * dev->nDataBytesPerChunk;
+		offset = (__u32)(addr - chunkBase);
+	}
+
+	*chunkOut = chunk;
+	*offsetOut = offset;
+}
+
+/* Function to return the number of shifts for a power of 2 greater than or
+ * equal to the given number
+ * Note we don't try to cater for all possible numbers and this does not have to
+ * be hellishly efficient.
+ */
+
+static __u32 ShiftsGE(__u32 x)
+{
+	int extraBits;
+	int nShifts;
+
+	nShifts = extraBits = 0;
+
+	while (x > 1) {
+		if (x & 1)
+			extraBits++;
+		x >>= 1;
+		nShifts++;
+	}
+
+	if (extraBits)
+		nShifts++;
+
+	return nShifts;
+}
+
+/* Function to return the number of shifts to get a 1 in bit 0
+ */
+
+static __u32 Shifts(__u32 x)
+{
+	int nShifts;
+
+	nShifts =  0;
+
+	if (!x)
+		return 0;
+
+	while (!(x&1)) {
+		x >>= 1;
+		nShifts++;
+	}
+
+	return nShifts;
+}
+
+
+
+/*
+ * Temporary buffer manipulations.
+ */
+
+static int yaffs_InitialiseTempBuffers(yaffs_Device *dev)
+{
+	int i;
+	__u8 *buf = (__u8 *)1;
+
+	memset(dev->tempBuffer, 0, sizeof(dev->tempBuffer));
+
+	for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) {
+		dev->tempBuffer[i].line = 0;	/* not in use */
+		dev->tempBuffer[i].buffer = buf =
+		    YMALLOC_DMA(dev->totalBytesPerChunk);
+	}
+
+	return buf ? YAFFS_OK : YAFFS_FAIL;
+}
+
+__u8 *yaffs_GetTempBuffer(yaffs_Device *dev, int lineNo)
+{
+	int i, j;
+
+	dev->tempInUse++;
+	if (dev->tempInUse > dev->maxTemp)
+		dev->maxTemp = dev->tempInUse;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].line == 0) {
+			dev->tempBuffer[i].line = lineNo;
+			if ((i + 1) > dev->maxTemp) {
+				dev->maxTemp = i + 1;
+				for (j = 0; j <= i; j++)
+					dev->tempBuffer[j].maxLine =
+					    dev->tempBuffer[j].line;
+			}
+
+			return dev->tempBuffer[i].buffer;
+		}
+	}
+
+	T(YAFFS_TRACE_BUFFERS,
+	  (TSTR("Out of temp buffers at line %d, other held by lines:"),
+	   lineNo));
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++)
+		T(YAFFS_TRACE_BUFFERS, (TSTR(" %d "), dev->tempBuffer[i].line));
+
+	T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR)));
+
+	/*
+	 * If we got here then we have to allocate an unmanaged one
+	 * This is not good.
+	 */
+
+	dev->unmanagedTempAllocations++;
+	return YMALLOC(dev->nDataBytesPerChunk);
+
+}
+
+void yaffs_ReleaseTempBuffer(yaffs_Device *dev, __u8 *buffer,
+				    int lineNo)
+{
+	int i;
+
+	dev->tempInUse--;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].buffer == buffer) {
+			dev->tempBuffer[i].line = 0;
+			return;
+		}
+	}
+
+	if (buffer) {
+		/* assume it is an unmanaged one. */
+		T(YAFFS_TRACE_BUFFERS,
+		  (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR),
+		   lineNo));
+		YFREE(buffer);
+		dev->unmanagedTempDeallocations++;
+	}
+
+}
+
+/*
+ * Determine if we have a managed buffer.
+ */
+int yaffs_IsManagedTempBuffer(yaffs_Device *dev, const __u8 *buffer)
+{
+	int i;
+
+	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
+		if (dev->tempBuffer[i].buffer == buffer)
+			return 1;
+	}
+
+	for (i = 0; i < dev->nShortOpCaches; i++) {
+		if (dev->srCache[i].data == buffer)
+			return 1;
+	}
+
+	if (buffer == dev->checkpointBuffer)
+		return 1;
+
+	T(YAFFS_TRACE_ALWAYS,
+		(TSTR("yaffs: unmaged buffer detected.\n" TENDSTR)));
+	return 0;
+}
+
+
+
+/*
+ * Chunk bitmap manipulations
+ */
+
+static Y_INLINE __u8 *yaffs_BlockBits(yaffs_Device *dev, int blk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR),
+			blk));
+		YBUG();
+	}
+	return dev->chunkBits +
+		(dev->chunkBitmapStride * (blk - dev->internalStartBlock));
+}
+
+static Y_INLINE void yaffs_VerifyChunkBitId(yaffs_Device *dev, int blk, int chunk)
+{
+	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock ||
+			chunk < 0 || chunk >= dev->nChunksPerBlock) {
+		T(YAFFS_TRACE_ERROR,
+		(TSTR("**>> yaffs: Chunk Id (%d:%d) invalid"TENDSTR),
+			blk, chunk));
+		YBUG();
+	}
+}
+
+static Y_INLINE void yaffs_ClearChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	memset(blkBits, 0, dev->chunkBitmapStride);
+}
+
+static Y_INLINE void yaffs_ClearChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	blkBits[chunk / 8] &= ~(1 << (chunk & 7));
+}
+
+static Y_INLINE void yaffs_SetChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	blkBits[chunk / 8] |= (1 << (chunk & 7));
+}
+
+static Y_INLINE int yaffs_CheckChunkBit(yaffs_Device *dev, int blk, int chunk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	yaffs_VerifyChunkBitId(dev, blk, chunk);
+
+	return (blkBits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0;
+}
+
+static Y_INLINE int yaffs_StillSomeChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	int i;
+	for (i = 0; i < dev->chunkBitmapStride; i++) {
+		if (*blkBits)
+			return 1;
+		blkBits++;
+	}
+	return 0;
+}
+
+static int yaffs_CountChunkBits(yaffs_Device *dev, int blk)
+{
+	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	int i;
+	int n = 0;
+	for (i = 0; i < dev->chunkBitmapStride; i++) {
+		__u8 x = *blkBits;
+		while (x) {
+			if (x & 1)
+				n++;
+			x >>= 1;
+		}
+
+		blkBits++;
+	}
+	return n;
+}
+
+/*
+ * Verification code
+ */
+
+static int yaffs_SkipVerification(yaffs_Device *dev)
+{
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_SkipFullVerification(yaffs_Device *dev)
+{
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_SkipNANDVerification(yaffs_Device *dev)
+{
+	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_NAND));
+}
+
+static const char *blockStateName[] = {
+"Unknown",
+"Needs scanning",
+"Scanning",
+"Empty",
+"Allocating",
+"Full",
+"Dirty",
+"Checkpoint",
+"Collecting",
+"Dead"
+};
+
+static void yaffs_VerifyBlock(yaffs_Device *dev, yaffs_BlockInfo *bi, int n)
+{
+	int actuallyUsed;
+	int inUse;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Report illegal runtime states */
+	if (bi->blockState >= YAFFS_NUMBER_OF_BLOCK_STATES)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has undefined state %d"TENDSTR), n, bi->blockState));
+
+	switch (bi->blockState) {
+	case YAFFS_BLOCK_STATE_UNKNOWN:
+	case YAFFS_BLOCK_STATE_SCANNING:
+	case YAFFS_BLOCK_STATE_NEEDS_SCANNING:
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has bad run-state %s"TENDSTR),
+		n, blockStateName[bi->blockState]));
+	}
+
+	/* Check pages in use and soft deletions are legal */
+
+	actuallyUsed = bi->pagesInUse - bi->softDeletions;
+
+	if (bi->pagesInUse < 0 || bi->pagesInUse > dev->nChunksPerBlock ||
+	   bi->softDeletions < 0 || bi->softDeletions > dev->nChunksPerBlock ||
+	   actuallyUsed < 0 || actuallyUsed > dev->nChunksPerBlock)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has illegal values pagesInUsed %d softDeletions %d"TENDSTR),
+		n, bi->pagesInUse, bi->softDeletions));
+
+
+	/* Check chunk bitmap legal */
+	inUse = yaffs_CountChunkBits(dev, n);
+	if (inUse != bi->pagesInUse)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has inconsistent values pagesInUse %d counted chunk bits %d"TENDSTR),
+			n, bi->pagesInUse, inUse));
+
+	/* Check that the sequence number is valid.
+	 * Ten million is legal, but is very unlikely
+	 */
+	if (dev->isYaffs2 &&
+	   (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || bi->blockState == YAFFS_BLOCK_STATE_FULL) &&
+	   (bi->sequenceNumber < YAFFS_LOWEST_SEQUENCE_NUMBER || bi->sequenceNumber > 10000000))
+		T(YAFFS_TRACE_VERIFY, (TSTR("Block %d has suspect sequence number of %d"TENDSTR),
+		n, bi->sequenceNumber));
+}
+
+static void yaffs_VerifyCollectedBlock(yaffs_Device *dev, yaffs_BlockInfo *bi,
+		int n)
+{
+	yaffs_VerifyBlock(dev, bi, n);
+
+	/* After collection the block should be in the erased state */
+	/* This will need to change if we do partial gc */
+
+	if (bi->blockState != YAFFS_BLOCK_STATE_COLLECTING &&
+			bi->blockState != YAFFS_BLOCK_STATE_EMPTY) {
+		T(YAFFS_TRACE_ERROR, (TSTR("Block %d is in state %d after gc, should be erased"TENDSTR),
+			n, bi->blockState));
+	}
+}
+
+static void yaffs_VerifyBlocks(yaffs_Device *dev)
+{
+	int i;
+	int nBlocksPerState[YAFFS_NUMBER_OF_BLOCK_STATES];
+	int nIllegalBlockStates = 0;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	memset(nBlocksPerState, 0, sizeof(nBlocksPerState));
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, i);
+		yaffs_VerifyBlock(dev, bi, i);
+
+		if (bi->blockState < YAFFS_NUMBER_OF_BLOCK_STATES)
+			nBlocksPerState[bi->blockState]++;
+		else
+			nIllegalBlockStates++;
+	}
+
+	T(YAFFS_TRACE_VERIFY, (TSTR(""TENDSTR)));
+	T(YAFFS_TRACE_VERIFY, (TSTR("Block summary"TENDSTR)));
+
+	T(YAFFS_TRACE_VERIFY, (TSTR("%d blocks have illegal states"TENDSTR), nIllegalBlockStates));
+	if (nBlocksPerState[YAFFS_BLOCK_STATE_ALLOCATING] > 1)
+		T(YAFFS_TRACE_VERIFY, (TSTR("Too many allocating blocks"TENDSTR)));
+
+	for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++)
+		T(YAFFS_TRACE_VERIFY,
+		  (TSTR("%s %d blocks"TENDSTR),
+		  blockStateName[i], nBlocksPerState[i]));
+
+	if (dev->blocksInCheckpoint != nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT])
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Checkpoint block count wrong dev %d count %d"TENDSTR),
+		 dev->blocksInCheckpoint, nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT]));
+
+	if (dev->nErasedBlocks != nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY])
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Erased block count wrong dev %d count %d"TENDSTR),
+		 dev->nErasedBlocks, nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY]));
+
+	if (nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING] > 1)
+		T(YAFFS_TRACE_VERIFY,
+		 (TSTR("Too many collecting blocks %d (max is 1)"TENDSTR),
+		 nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING]));
+
+	T(YAFFS_TRACE_VERIFY, (TSTR(""TENDSTR)));
+
+}
+
+/*
+ * Verify the object header. oh must be valid, but obj and tags may be NULL in which
+ * case those tests will not be performed.
+ */
+static void yaffs_VerifyObjectHeader(yaffs_Object *obj, yaffs_ObjectHeader *oh, yaffs_ExtendedTags *tags, int parentCheck)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	if (!(tags && obj && oh)) {
+		T(YAFFS_TRACE_VERIFY,
+				(TSTR("Verifying object header tags %x obj %x oh %x"TENDSTR),
+				(__u32)tags, (__u32)obj, (__u32)oh));
+		return;
+	}
+
+	if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN ||
+			oh->type > YAFFS_OBJECT_TYPE_MAX)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header type is illegal value 0x%x"TENDSTR),
+			tags->objectId, oh->type));
+
+	if (tags->objectId != obj->objectId)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch objectId %d"TENDSTR),
+			tags->objectId, obj->objectId));
+
+
+	/*
+	 * Check that the object's parent ids match if parentCheck requested.
+	 *
+	 * Tests do not apply to the root object.
+	 */
+
+	if (parentCheck && tags->objectId > 1 && !obj->parent)
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch parentId %d obj->parent is NULL"TENDSTR),
+			tags->objectId, oh->parentObjectId));
+
+	if (parentCheck && obj->parent &&
+			oh->parentObjectId != obj->parent->objectId &&
+			(oh->parentObjectId != YAFFS_OBJECTID_UNLINKED ||
+			obj->parent->objectId != YAFFS_OBJECTID_DELETED))
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header mismatch parentId %d parentObjectId %d"TENDSTR),
+			tags->objectId, oh->parentObjectId, obj->parent->objectId));
+
+	if (tags->objectId > 1 && oh->name[0] == 0) /* Null name */
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header name is NULL"TENDSTR),
+			obj->objectId));
+
+	if (tags->objectId > 1 && ((__u8)(oh->name[0])) == 0xff) /* Trashed name */
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d header name is 0xFF"TENDSTR),
+			obj->objectId));
+}
+
+
+
+static int yaffs_VerifyTnodeWorker(yaffs_Object *obj, yaffs_Tnode *tn,
+					__u32 level, int chunkOffset)
+{
+	int i;
+	yaffs_Device *dev = obj->myDev;
+	int ok = 1;
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) {
+				if (tn->internal[i]) {
+					ok = yaffs_VerifyTnodeWorker(obj,
+							tn->internal[i],
+							level - 1,
+							(chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
+				}
+			}
+		} else if (level == 0) {
+			yaffs_ExtendedTags tags;
+			__u32 objectId = obj->objectId;
+
+			chunkOffset <<=  YAFFS_TNODES_LEVEL0_BITS;
+
+			for (i = 0; i < YAFFS_NTNODES_LEVEL0; i++) {
+				__u32 theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+
+				if (theChunk > 0) {
+					/* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),tags.objectId,tags.chunkId,theChunk)); */
+					yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL, &tags);
+					if (tags.objectId != objectId || tags.chunkId != chunkOffset) {
+						T(~0, (TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
+							objectId, chunkOffset, theChunk,
+							tags.objectId, tags.chunkId));
+					}
+				}
+				chunkOffset++;
+			}
+		}
+	}
+
+	return ok;
+
+}
+
+
+static void yaffs_VerifyFile(yaffs_Object *obj)
+{
+	int requiredTallness;
+	int actualTallness;
+	__u32 lastChunk;
+	__u32 x;
+	__u32 i;
+	yaffs_Device *dev;
+	yaffs_ExtendedTags tags;
+	yaffs_Tnode *tn;
+	__u32 objectId;
+
+	if (!obj)
+		return;
+
+	if (yaffs_SkipVerification(obj->myDev))
+		return;
+
+	dev = obj->myDev;
+	objectId = obj->objectId;
+
+	/* Check file size is consistent with tnode depth */
+	lastChunk =  obj->variant.fileVariant.fileSize / dev->nDataBytesPerChunk + 1;
+	x = lastChunk >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (x > 0) {
+		x >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+	actualTallness = obj->variant.fileVariant.topLevel;
+
+	if (requiredTallness > actualTallness)
+		T(YAFFS_TRACE_VERIFY,
+		(TSTR("Obj %d had tnode tallness %d, needs to be %d"TENDSTR),
+		 obj->objectId, actualTallness, requiredTallness));
+
+
+	/* Check that the chunks in the tnode tree are all correct.
+	 * We do this by scanning through the tnode tree and
+	 * checking the tags for every chunk match.
+	 */
+
+	if (yaffs_SkipNANDVerification(dev))
+		return;
+
+	for (i = 1; i <= lastChunk; i++) {
+		tn = yaffs_FindLevel0Tnode(dev, &obj->variant.fileVariant, i);
+
+		if (tn) {
+			__u32 theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+			if (theChunk > 0) {
+				/* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),objectId,i,theChunk)); */
+				yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL, &tags);
+				if (tags.objectId != objectId || tags.chunkId != i) {
+					T(~0, (TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
+						objectId, i, theChunk,
+						tags.objectId, tags.chunkId));
+				}
+			}
+		}
+	}
+}
+
+
+static void yaffs_VerifyHardLink(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	/* Verify sane equivalent object */
+}
+
+static void yaffs_VerifySymlink(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+
+	/* Verify symlink string */
+}
+
+static void yaffs_VerifySpecial(yaffs_Object *obj)
+{
+	if (obj && yaffs_SkipVerification(obj->myDev))
+		return;
+}
+
+static void yaffs_VerifyObject(yaffs_Object *obj)
+{
+	yaffs_Device *dev;
+
+	__u32 chunkMin;
+	__u32 chunkMax;
+
+	__u32 chunkIdOk;
+	__u32 chunkInRange;
+	__u32 chunkShouldNotBeDeleted;
+	__u32 chunkValid;
+
+	if (!obj)
+		return;
+
+	if (obj->beingCreated)
+		return;
+
+	dev = obj->myDev;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Check sane object header chunk */
+
+	chunkMin = dev->internalStartBlock * dev->nChunksPerBlock;
+	chunkMax = (dev->internalEndBlock+1) * dev->nChunksPerBlock - 1;
+
+	chunkInRange = (((unsigned)(obj->hdrChunk)) >= chunkMin && ((unsigned)(obj->hdrChunk)) <= chunkMax);
+	chunkIdOk = chunkInRange || (obj->hdrChunk == 0);
+	chunkValid = chunkInRange &&
+			yaffs_CheckChunkBit(dev,
+					obj->hdrChunk / dev->nChunksPerBlock,
+					obj->hdrChunk % dev->nChunksPerBlock);
+	chunkShouldNotBeDeleted = chunkInRange && !chunkValid;
+
+	if (!obj->fake &&
+			(!chunkIdOk || chunkShouldNotBeDeleted)) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d has chunkId %d %s %s"TENDSTR),
+			obj->objectId, obj->hdrChunk,
+			chunkIdOk ? "" : ",out of range",
+			chunkShouldNotBeDeleted ? ",marked as deleted" : ""));
+	}
+
+	if (chunkValid && !yaffs_SkipNANDVerification(dev)) {
+		yaffs_ExtendedTags tags;
+		yaffs_ObjectHeader *oh;
+		__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+		oh = (yaffs_ObjectHeader *)buffer;
+
+		yaffs_ReadChunkWithTagsFromNAND(dev, obj->hdrChunk, buffer,
+				&tags);
+
+		yaffs_VerifyObjectHeader(obj, oh, &tags, 1);
+
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+	}
+
+	/* Verify it has a parent */
+	if (obj && !obj->fake &&
+			(!obj->parent || obj->parent->myDev != dev)) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d has parent pointer %p which does not look like an object"TENDSTR),
+			obj->objectId, obj->parent));
+	}
+
+	/* Verify parent is a directory */
+	if (obj->parent && obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Obj %d's parent is not a directory (type %d)"TENDSTR),
+			obj->objectId, obj->parent->variantType));
+	}
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		yaffs_VerifyFile(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		yaffs_VerifySymlink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		yaffs_VerifyDirectory(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		yaffs_VerifyHardLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		yaffs_VerifySpecial(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+	default:
+		T(YAFFS_TRACE_VERIFY,
+		(TSTR("Obj %d has illegaltype %d"TENDSTR),
+		obj->objectId, obj->variantType));
+		break;
+	}
+}
+
+static void yaffs_VerifyObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	int i;
+	struct ylist_head *lh;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	/* Iterate through the objects in each hash entry */
+
+	for (i = 0; i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each(lh, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				yaffs_VerifyObject(obj);
+			}
+		}
+	}
+}
+
+
+/*
+ *  Simple hash function. Needs to have a reasonable spread
+ */
+
+static Y_INLINE int yaffs_HashFunction(int n)
+{
+	n = abs(n);
+	return n % YAFFS_NOBJECT_BUCKETS;
+}
+
+/*
+ * Access functions to useful fake objects.
+ * Note that root might have a presence in NAND if permissions are set.
+ */
+
+yaffs_Object *yaffs_Root(yaffs_Device *dev)
+{
+	return dev->rootDir;
+}
+
+yaffs_Object *yaffs_LostNFound(yaffs_Device *dev)
+{
+	return dev->lostNFoundDir;
+}
+
+
+/*
+ *  Erased NAND checking functions
+ */
+
+int yaffs_CheckFF(__u8 *buffer, int nBytes)
+{
+	/* Horrible, slow implementation */
+	while (nBytes--) {
+		if (*buffer != 0xFF)
+			return 0;
+		buffer++;
+	}
+	return 1;
+}
+
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND)
+{
+	int retval = YAFFS_OK;
+	__u8 *data = yaffs_GetTempBuffer(dev, __LINE__);
+	yaffs_ExtendedTags tags;
+	int result;
+
+	result = yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
+
+	if (tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR)
+		retval = YAFFS_FAIL;
+
+	if (!yaffs_CheckFF(data, dev->nDataBytesPerChunk) || tags.chunkUsed) {
+		T(YAFFS_TRACE_NANDACCESS,
+		  (TSTR("Chunk %d not erased" TENDSTR), chunkInNAND));
+		retval = YAFFS_FAIL;
+	}
+
+	yaffs_ReleaseTempBuffer(dev, data, __LINE__);
+
+	return retval;
+
+}
+
+static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
+					const __u8 *data,
+					yaffs_ExtendedTags *tags,
+					int useReserve)
+{
+	int attempts = 0;
+	int writeOk = 0;
+	int chunk;
+
+	yaffs_InvalidateCheckpoint(dev);
+
+	do {
+		yaffs_BlockInfo *bi = 0;
+		int erasedOk = 0;
+
+		chunk = yaffs_AllocateChunk(dev, useReserve, &bi);
+		if (chunk < 0) {
+			/* no space */
+			break;
+		}
+
+		/* First check this chunk is erased, if it needs
+		 * checking.  The checking policy (unless forced
+		 * always on) is as follows:
+		 *
+		 * Check the first page we try to write in a block.
+		 * If the check passes then we don't need to check any
+		 * more.	If the check fails, we check again...
+		 * If the block has been erased, we don't need to check.
+		 *
+		 * However, if the block has been prioritised for gc,
+		 * then we think there might be something odd about
+		 * this block and stop using it.
+		 *
+		 * Rationale: We should only ever see chunks that have
+		 * not been erased if there was a partially written
+		 * chunk due to power loss.  This checking policy should
+		 * catch that case with very few checks and thus save a
+		 * lot of checks that are most likely not needed.
+		 */
+		if (bi->gcPrioritise) {
+			yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+			/* try another chunk */
+			continue;
+		}
+
+		/* let's give it a try */
+		attempts++;
+
+#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED
+		bi->skipErasedCheck = 0;
+#endif
+		if (!bi->skipErasedCheck) {
+			erasedOk = yaffs_CheckChunkErased(dev, chunk);
+			if (erasedOk != YAFFS_OK) {
+				T(YAFFS_TRACE_ERROR,
+				(TSTR("**>> yaffs chunk %d was not erased"
+				TENDSTR), chunk));
+
+				/* try another chunk */
+				continue;
+			}
+			bi->skipErasedCheck = 1;
+		}
+
+		writeOk = yaffs_WriteChunkWithTagsToNAND(dev, chunk,
+				data, tags);
+		if (writeOk != YAFFS_OK) {
+			yaffs_HandleWriteChunkError(dev, chunk, erasedOk);
+			/* try another chunk */
+			continue;
+		}
+
+		/* Copy the data into the robustification buffer */
+		yaffs_HandleWriteChunkOk(dev, chunk, data, tags);
+
+	} while (writeOk != YAFFS_OK &&
+		(yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts));
+
+	if (!writeOk)
+		chunk = -1;
+
+	if (attempts > 1) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("**>> yaffs write required %d attempts" TENDSTR),
+			attempts));
+
+		dev->nRetriedWrites += (attempts - 1);
+	}
+
+	return chunk;
+}
+
+/*
+ * Block retiring for handling a broken block.
+ */
+
+static void yaffs_RetireBlock(yaffs_Device *dev, int blockInNAND)
+{
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
+
+	yaffs_InvalidateCheckpoint(dev);
+
+	if (yaffs_MarkBlockBad(dev, blockInNAND) != YAFFS_OK) {
+		if (yaffs_EraseBlockInNAND(dev, blockInNAND) != YAFFS_OK) {
+			T(YAFFS_TRACE_ALWAYS, (TSTR(
+				"yaffs: Failed to mark bad and erase block %d"
+				TENDSTR), blockInNAND));
+		} else {
+			yaffs_ExtendedTags tags;
+			int chunkId = blockInNAND * dev->nChunksPerBlock;
+
+			__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+			memset(buffer, 0xff, dev->nDataBytesPerChunk);
+			yaffs_InitialiseTags(&tags);
+			tags.sequenceNumber = YAFFS_SEQUENCE_BAD_BLOCK;
+			if (dev->writeChunkWithTagsToNAND(dev, chunkId -
+				dev->chunkOffset, buffer, &tags) != YAFFS_OK)
+				T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Failed to "
+					TCONT("write bad block marker to block %d")
+					TENDSTR), blockInNAND));
+
+			yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+		}
+	}
+
+	bi->blockState = YAFFS_BLOCK_STATE_DEAD;
+	bi->gcPrioritise = 0;
+	bi->needsRetiring = 0;
+
+	dev->nRetiredBlocks++;
+}
+
+/*
+ * Functions for robustisizing TODO
+ *
+ */
+
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags)
+{
+}
+
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				const yaffs_ExtendedTags *tags)
+{
+}
+
+void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi)
+{
+	if (!bi->gcPrioritise) {
+		bi->gcPrioritise = 1;
+		dev->hasPendingPrioritisedGCs = 1;
+		bi->chunkErrorStrikes++;
+
+		if (bi->chunkErrorStrikes > 3) {
+			bi->needsRetiring = 1; /* Too many stikes, so retire this */
+			T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Block struck out" TENDSTR)));
+
+		}
+	}
+}
+
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND,
+		int erasedOk)
+{
+	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
+
+	yaffs_HandleChunkError(dev, bi);
+
+	if (erasedOk) {
+		/* Was an actual write failure, so mark the block for retirement  */
+		bi->needsRetiring = 1;
+		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		  (TSTR("**>> Block %d needs retiring" TENDSTR), blockInNAND));
+	}
+
+	/* Delete the chunk */
+	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+}
+
+
+/*---------------- Name handling functions ------------*/
+
+static __u16 yaffs_CalcNameSum(const YCHAR *name)
+{
+	__u16 sum = 0;
+	__u16 i = 1;
+
+	const YUCHAR *bname = (const YUCHAR *) name;
+	if (bname) {
+		while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH/2))) {
+
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+			sum += yaffs_toupper(*bname) * i;
+#else
+			sum += (*bname) * i;
+#endif
+			i++;
+			bname++;
+		}
+	}
+	return sum;
+}
+
+static void yaffs_SetObjectName(yaffs_Object *obj, const YCHAR *name)
+{
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	memset(obj->shortName, 0, sizeof(YCHAR) * (YAFFS_SHORT_NAME_LENGTH+1));
+	if (name && yaffs_strlen(name) <= YAFFS_SHORT_NAME_LENGTH)
+		yaffs_strcpy(obj->shortName, name);
+	else
+		obj->shortName[0] = _Y('\0');
+#endif
+	obj->sum = yaffs_CalcNameSum(name);
+}
+
+/*-------------------- TNODES -------------------
+
+ * List of spare tnodes
+ * The list is hooked together using the first pointer
+ * in the tnode.
+ */
+
+/* yaffs_CreateTnodes creates a bunch more tnodes and
+ * adds them to the tnode free list.
+ * Don't use this function directly
+ */
+
+static int yaffs_CreateTnodes(yaffs_Device *dev, int nTnodes)
+{
+	int i;
+	int tnodeSize;
+	yaffs_Tnode *newTnodes;
+	__u8 *mem;
+	yaffs_Tnode *curr;
+	yaffs_Tnode *next;
+	yaffs_TnodeList *tnl;
+
+	if (nTnodes < 1)
+		return YAFFS_OK;
+
+	/* Calculate the tnode size in bytes for variable width tnode support.
+	 * Must be a multiple of 32-bits  */
+	tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+	if (tnodeSize < sizeof(yaffs_Tnode))
+		tnodeSize = sizeof(yaffs_Tnode);
+
+	/* make these things */
+
+	newTnodes = YMALLOC(nTnodes * tnodeSize);
+	mem = (__u8 *)newTnodes;
+
+	if (!newTnodes) {
+		T(YAFFS_TRACE_ERROR,
+			(TSTR("yaffs: Could not allocate Tnodes" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Hook them into the free list */
+#if 0
+	for (i = 0; i < nTnodes - 1; i++) {
+		newTnodes[i].internal[0] = &newTnodes[i + 1];
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		newTnodes[i].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+	}
+
+	newTnodes[nTnodes - 1].internal[0] = dev->freeTnodes;
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+	newTnodes[nTnodes - 1].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+	dev->freeTnodes = newTnodes;
+#else
+	/* New hookup for wide tnodes */
+	for (i = 0; i < nTnodes - 1; i++) {
+		curr = (yaffs_Tnode *) &mem[i * tnodeSize];
+		next = (yaffs_Tnode *) &mem[(i+1) * tnodeSize];
+		curr->internal[0] = next;
+	}
+
+	curr = (yaffs_Tnode *) &mem[(nTnodes - 1) * tnodeSize];
+	curr->internal[0] = dev->freeTnodes;
+	dev->freeTnodes = (yaffs_Tnode *)mem;
+
+#endif
+
+
+	dev->nFreeTnodes += nTnodes;
+	dev->nTnodesCreated += nTnodes;
+
+	/* Now add this bunch of tnodes to a list for freeing up.
+	 * NB If we can't add this to the management list it isn't fatal
+	 * but it just means we can't free this bunch of tnodes later.
+	 */
+
+	tnl = YMALLOC(sizeof(yaffs_TnodeList));
+	if (!tnl) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("yaffs: Could not add tnodes to management list" TENDSTR)));
+		   return YAFFS_FAIL;
+	} else {
+		tnl->tnodes = newTnodes;
+		tnl->next = dev->allocatedTnodeList;
+		dev->allocatedTnodeList = tnl;
+	}
+
+	T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR)));
+
+	return YAFFS_OK;
+}
+
+/* GetTnode gets us a clean tnode. Tries to make allocate more if we run out */
+
+static yaffs_Tnode *yaffs_GetTnodeRaw(yaffs_Device *dev)
+{
+	yaffs_Tnode *tn = NULL;
+
+	/* If there are none left make more */
+	if (!dev->freeTnodes)
+		yaffs_CreateTnodes(dev, YAFFS_ALLOCATION_NTNODES);
+
+	if (dev->freeTnodes) {
+		tn = dev->freeTnodes;
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		if (tn->internal[YAFFS_NTNODES_INTERNAL] != (void *)1) {
+			/* Hoosterman, this thing looks like it isn't in the list */
+			T(YAFFS_TRACE_ALWAYS,
+			  (TSTR("yaffs: Tnode list bug 1" TENDSTR)));
+		}
+#endif
+		dev->freeTnodes = dev->freeTnodes->internal[0];
+		dev->nFreeTnodes--;
+	}
+
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+
+	return tn;
+}
+
+static yaffs_Tnode *yaffs_GetTnode(yaffs_Device *dev)
+{
+	yaffs_Tnode *tn = yaffs_GetTnodeRaw(dev);
+	int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+	if (tnodeSize < sizeof(yaffs_Tnode))
+		tnodeSize = sizeof(yaffs_Tnode);
+
+	if (tn)
+		memset(tn, 0, tnodeSize);
+
+	return tn;
+}
+
+/* FreeTnode frees up a tnode and puts it back on the free list */
+static void yaffs_FreeTnode(yaffs_Device *dev, yaffs_Tnode *tn)
+{
+	if (tn) {
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+		if (tn->internal[YAFFS_NTNODES_INTERNAL] != 0) {
+			/* Hoosterman, this thing looks like it is already in the list */
+			T(YAFFS_TRACE_ALWAYS,
+			  (TSTR("yaffs: Tnode list bug 2" TENDSTR)));
+		}
+		tn->internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
+#endif
+		tn->internal[0] = dev->freeTnodes;
+		dev->freeTnodes = tn;
+		dev->nFreeTnodes++;
+	}
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+}
+
+static void yaffs_DeinitialiseTnodes(yaffs_Device *dev)
+{
+	/* Free the list of allocated tnodes */
+	yaffs_TnodeList *tmp;
+
+	while (dev->allocatedTnodeList) {
+		tmp = dev->allocatedTnodeList->next;
+
+		YFREE(dev->allocatedTnodeList->tnodes);
+		YFREE(dev->allocatedTnodeList);
+		dev->allocatedTnodeList = tmp;
+
+	}
+
+	dev->freeTnodes = NULL;
+	dev->nFreeTnodes = 0;
+}
+
+static void yaffs_InitialiseTnodes(yaffs_Device *dev)
+{
+	dev->allocatedTnodeList = NULL;
+	dev->freeTnodes = NULL;
+	dev->nFreeTnodes = 0;
+	dev->nTnodesCreated = 0;
+}
+
+
+void yaffs_PutLevel0Tnode(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos,
+		unsigned val)
+{
+	__u32 *map = (__u32 *)tn;
+	__u32 bitInMap;
+	__u32 bitInWord;
+	__u32 wordInMap;
+	__u32 mask;
+
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
+	val >>= dev->chunkGroupBits;
+
+	bitInMap = pos * dev->tnodeWidth;
+	wordInMap = bitInMap / 32;
+	bitInWord = bitInMap & (32 - 1);
+
+	mask = dev->tnodeMask << bitInWord;
+
+	map[wordInMap] &= ~mask;
+	map[wordInMap] |= (mask & (val << bitInWord));
+
+	if (dev->tnodeWidth > (32 - bitInWord)) {
+		bitInWord = (32 - bitInWord);
+		wordInMap++;;
+		mask = dev->tnodeMask >> (/*dev->tnodeWidth -*/ bitInWord);
+		map[wordInMap] &= ~mask;
+		map[wordInMap] |= (mask & (val >> bitInWord));
+	}
+}
+
+static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn,
+		unsigned pos)
+{
+	__u32 *map = (__u32 *)tn;
+	__u32 bitInMap;
+	__u32 bitInWord;
+	__u32 wordInMap;
+	__u32 val;
+
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
+
+	bitInMap = pos * dev->tnodeWidth;
+	wordInMap = bitInMap / 32;
+	bitInWord = bitInMap & (32 - 1);
+
+	val = map[wordInMap] >> bitInWord;
+
+	if	(dev->tnodeWidth > (32 - bitInWord)) {
+		bitInWord = (32 - bitInWord);
+		wordInMap++;;
+		val |= (map[wordInMap] << bitInWord);
+	}
+
+	val &= dev->tnodeMask;
+	val <<= dev->chunkGroupBits;
+
+	return val;
+}
+
+/* ------------------- End of individual tnode manipulation -----------------*/
+
+/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------
+ * The look up tree is represented by the top tnode and the number of topLevel
+ * in the tree. 0 means only the level 0 tnode is in the tree.
+ */
+
+/* FindLevel0Tnode finds the level 0 tnode, if one exists. */
+static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId)
+{
+	yaffs_Tnode *tn = fStruct->top;
+	__u32 i;
+	int requiredTallness;
+	int level = fStruct->topLevel;
+
+	/* Check sane level and chunk Id */
+	if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL)
+		return NULL;
+
+	if (chunkId > YAFFS_MAX_CHUNK_ID)
+		return NULL;
+
+	/* First check we're tall enough (ie enough topLevel) */
+
+	i = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (i) {
+		i >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+	if (requiredTallness > fStruct->topLevel)
+		return NULL; /* Not tall enough, so we can't find it */
+
+	/* Traverse down to level 0 */
+	while (level > 0 && tn) {
+		tn = tn->internal[(chunkId >>
+			(YAFFS_TNODES_LEVEL0_BITS +
+				(level - 1) *
+				YAFFS_TNODES_INTERNAL_BITS)) &
+			YAFFS_TNODES_INTERNAL_MASK];
+		level--;
+	}
+
+	return tn;
+}
+
+/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree.
+ * This happens in two steps:
+ *  1. If the tree isn't tall enough, then make it taller.
+ *  2. Scan down the tree towards the level 0 tnode adding tnodes if required.
+ *
+ * Used when modifying the tree.
+ *
+ *  If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will
+ *  be plugged into the ttree.
+ */
+
+static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device *dev,
+					yaffs_FileStructure *fStruct,
+					__u32 chunkId,
+					yaffs_Tnode *passedTn)
+{
+	int requiredTallness;
+	int i;
+	int l;
+	yaffs_Tnode *tn;
+
+	__u32 x;
+
+
+	/* Check sane level and page Id */
+	if (fStruct->topLevel < 0 || fStruct->topLevel > YAFFS_TNODES_MAX_LEVEL)
+	{
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("yaffs_AddOrFindLevel0Tnode fail fStruct->topLevel%d"
+			TENDSTR), fStruct->topLevel));
+
+		return NULL;
+	}
+
+	if (chunkId > YAFFS_MAX_CHUNK_ID)
+	{
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("yaffs_AddOrFindLevel0Tnode fail chunkId%d"
+			TENDSTR), chunkId));
+
+		return NULL;
+	}
+
+	/* First check we're tall enough (ie enough topLevel) */
+
+	x = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
+	requiredTallness = 0;
+	while (x) {
+		x >>= YAFFS_TNODES_INTERNAL_BITS;
+		requiredTallness++;
+	}
+
+
+	if (requiredTallness > fStruct->topLevel) {
+		/* Not tall enough, gotta make the tree taller */
+		for (i = fStruct->topLevel; i < requiredTallness; i++) {
+
+			tn = yaffs_GetTnode(dev);
+
+			if (tn) {
+				tn->internal[0] = fStruct->top;
+				fStruct->top = tn;
+			} else {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR("yaffs: no more tnodes" TENDSTR)));
+			}
+		}
+
+		fStruct->topLevel = requiredTallness;
+	}
+
+	/* Traverse down to level 0, adding anything we need */
+
+	l = fStruct->topLevel;
+	tn = fStruct->top;
+
+	if (l > 0) {
+		while (l > 0 && tn) {
+			x = (chunkId >>
+			     (YAFFS_TNODES_LEVEL0_BITS +
+			      (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) &
+			    YAFFS_TNODES_INTERNAL_MASK;
+
+
+			if ((l > 1) && !tn->internal[x]) {
+				/* Add missing non-level-zero tnode */
+				tn->internal[x] = yaffs_GetTnode(dev);
+
+			} else if (l == 1) {
+				/* Looking from level 1 at level 0 */
+				if (passedTn) {
+					/* If we already have one, then release it.*/
+					if (tn->internal[x])
+						yaffs_FreeTnode(dev, tn->internal[x]);
+					tn->internal[x] = passedTn;
+
+				} else if (!tn->internal[x]) {
+					/* Don't have one, none passed in */
+					tn->internal[x] = yaffs_GetTnode(dev);
+				}
+			}
+
+			tn = tn->internal[x];
+			l--;
+		}
+	} else {
+		/* top is level 0 */
+		if (passedTn) {
+			memcpy(tn, passedTn, (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
+			yaffs_FreeTnode(dev, passedTn);
+		}
+	}
+
+	return tn;
+}
+
+static int yaffs_FindChunkInGroup(yaffs_Device *dev, int theChunk,
+				yaffs_ExtendedTags *tags, int objectId,
+				int chunkInInode)
+{
+	int j;
+
+	for (j = 0; theChunk && j < dev->chunkGroupSize; j++) {
+		if (yaffs_CheckChunkBit(dev, theChunk / dev->nChunksPerBlock,
+				theChunk % dev->nChunksPerBlock)) {
+			
+			if(dev->chunkGroupSize == 1)
+				return theChunk;
+			else {
+				yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL,
+								tags);
+				if (yaffs_TagsMatch(tags, objectId, chunkInInode)) {
+					/* found it; */
+					return theChunk;
+				}
+			}
+		}
+		theChunk++;
+	}
+	return -1;
+}
+
+
+/* DeleteWorker scans backwards through the tnode tree and deletes all the
+ * chunks and tnodes in the file
+ * Returns 1 if the tree was deleted.
+ * Returns 0 if it stopped early due to hitting the limit and the delete is incomplete.
+ */
+
+static int yaffs_DeleteWorker(yaffs_Object *in, yaffs_Tnode *tn, __u32 level,
+			      int chunkOffset, int *limit)
+{
+	int i;
+	int chunkInInode;
+	int theChunk;
+	yaffs_ExtendedTags tags;
+	int foundChunk;
+	yaffs_Device *dev = in->myDev;
+
+	int allDone = 1;
+
+	if (tn) {
+		if (level > 0) {
+			for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
+			     i--) {
+				if (tn->internal[i]) {
+					if (limit && (*limit) < 0) {
+						allDone = 0;
+					} else {
+						allDone =
+							yaffs_DeleteWorker(in,
+								tn->
+								internal
+								[i],
+								level -
+								1,
+								(chunkOffset
+									<<
+									YAFFS_TNODES_INTERNAL_BITS)
+								+ i,
+								limit);
+					}
+					if (allDone) {
+						yaffs_FreeTnode(dev,
+								tn->
+								internal[i]);
+						tn->internal[i] = NULL;
+					}
+				}
+			}
+			return (allDone) ? 1 : 0;
+		} else if (level == 0) {
+			int hitLimit = 0;
+
+			for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0 && !hitLimit;
+					i--) {
+				theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+				if (theChunk) {
+
+					chunkInInode = (chunkOffset <<
+						YAFFS_TNODES_LEVEL0_BITS) + i;
+
+					foundChunk =
+						yaffs_FindChunkInGroup(dev,
+								theChunk,
+								&tags,
+								in->objectId,
+								chunkInInode);
+
+					if (foundChunk > 0) {
+						yaffs_DeleteChunk(dev,
+								  foundChunk, 1,
+								  __LINE__);
+						in->nDataChunks--;
+						if (limit) {
+							*limit = *limit - 1;
+							if (*limit <= 0)
+								hitLimit = 1;
+						}
+
+					}
+
+					yaffs_PutLevel0Tnode(dev, tn, i, 0);
+				}
+
+			}
+			return (i < 0) ? 1 : 0;
+
+		}
+
+	}
+
+	return 1;
+
+}
+
+static void yaffs_SoftDeleteChunk(yaffs_Device *dev, int chunk)
+{
+	yaffs_BlockInfo *theBlock;
+
+	T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk));
+
+	theBlock = yaffs_GetBlockInfo(dev, chunk / dev->nChunksPerBlock);
+	if (theBlock) {
+		theBlock->softDeletions++;
+		dev->nFreeChunks++;
+	}
+}
+
+/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file.
+ * All soft deleting does is increment the block's softdelete count and pulls the chunk out
+ * of the tnode.
+ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted.
+ */
+
+static int yaffs_SoftDeleteWorker(yaffs_Object *in, yaffs_Tnode *tn,
+				  __u32 level, int chunkOffset)
+{
+	int i;
+	int theChunk;
+	int allDone = 1;
+	yaffs_Device *dev = in->myDev;
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
+			     i--) {
+				if (tn->internal[i]) {
+					allDone =
+					    yaffs_SoftDeleteWorker(in,
+								   tn->
+								   internal[i],
+								   level - 1,
+								   (chunkOffset
+								    <<
+								    YAFFS_TNODES_INTERNAL_BITS)
+								   + i);
+					if (allDone) {
+						yaffs_FreeTnode(dev,
+								tn->
+								internal[i]);
+						tn->internal[i] = NULL;
+					} else {
+						/* Hoosterman... how could this happen? */
+					}
+				}
+			}
+			return (allDone) ? 1 : 0;
+		} else if (level == 0) {
+
+			for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) {
+				theChunk = yaffs_GetChunkGroupBase(dev, tn, i);
+				if (theChunk) {
+					/* Note this does not find the real chunk, only the chunk group.
+					 * We make an assumption that a chunk group is not larger than
+					 * a block.
+					 */
+					yaffs_SoftDeleteChunk(dev, theChunk);
+					yaffs_PutLevel0Tnode(dev, tn, i, 0);
+				}
+
+			}
+			return 1;
+
+		}
+
+	}
+
+	return 1;
+
+}
+
+static void yaffs_SoftDeleteFile(yaffs_Object *obj)
+{
+	if (obj->deleted &&
+	    obj->variantType == YAFFS_OBJECT_TYPE_FILE && !obj->softDeleted) {
+		if (obj->nDataChunks <= 0) {
+			/* Empty file with no duplicate object headers, just delete it immediately */
+			yaffs_FreeTnode(obj->myDev,
+					obj->variant.fileVariant.top);
+			obj->variant.fileVariant.top = NULL;
+			T(YAFFS_TRACE_TRACING,
+			  (TSTR("yaffs: Deleting empty file %d" TENDSTR),
+			   obj->objectId));
+			yaffs_DoGenericObjectDeletion(obj);
+		} else {
+			yaffs_SoftDeleteWorker(obj,
+					       obj->variant.fileVariant.top,
+					       obj->variant.fileVariant.
+					       topLevel, 0);
+			obj->softDeleted = 1;
+		}
+	}
+}
+
+/* Pruning removes any part of the file structure tree that is beyond the
+ * bounds of the file (ie that does not point to chunks).
+ *
+ * A file should only get pruned when its size is reduced.
+ *
+ * Before pruning, the chunks must be pulled from the tree and the
+ * level 0 tnode entries must be zeroed out.
+ * Could also use this for file deletion, but that's probably better handled
+ * by a special case.
+ */
+
+static yaffs_Tnode *yaffs_PruneWorker(yaffs_Device *dev, yaffs_Tnode *tn,
+				__u32 level, int del0)
+{
+	int i;
+	int hasData;
+
+	if (tn) {
+		hasData = 0;
+
+		for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) {
+			if (tn->internal[i] && level > 0) {
+				tn->internal[i] =
+				    yaffs_PruneWorker(dev, tn->internal[i],
+						      level - 1,
+						      (i == 0) ? del0 : 1);
+			}
+
+			if (tn->internal[i])
+				hasData++;
+		}
+
+		if (hasData == 0 && del0) {
+			/* Free and return NULL */
+
+			yaffs_FreeTnode(dev, tn);
+			tn = NULL;
+		}
+
+	}
+
+	return tn;
+
+}
+
+static int yaffs_PruneFileStructure(yaffs_Device *dev,
+				yaffs_FileStructure *fStruct)
+{
+	int i;
+	int hasData;
+	int done = 0;
+	yaffs_Tnode *tn;
+
+	if (fStruct->topLevel > 0) {
+		fStruct->top =
+		    yaffs_PruneWorker(dev, fStruct->top, fStruct->topLevel, 0);
+
+		/* Now we have a tree with all the non-zero branches NULL but the height
+		 * is the same as it was.
+		 * Let's see if we can trim internal tnodes to shorten the tree.
+		 * We can do this if only the 0th element in the tnode is in use
+		 * (ie all the non-zero are NULL)
+		 */
+
+		while (fStruct->topLevel && !done) {
+			tn = fStruct->top;
+
+			hasData = 0;
+			for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) {
+				if (tn->internal[i])
+					hasData++;
+			}
+
+			if (!hasData) {
+				fStruct->top = tn->internal[0];
+				fStruct->topLevel--;
+				yaffs_FreeTnode(dev, tn);
+			} else {
+				done = 1;
+			}
+		}
+	}
+
+	return YAFFS_OK;
+}
+
+/*-------------------- End of File Structure functions.-------------------*/
+
+/* yaffs_CreateFreeObjects creates a bunch more objects and
+ * adds them to the object free list.
+ */
+static int yaffs_CreateFreeObjects(yaffs_Device *dev, int nObjects)
+{
+	int i;
+	yaffs_Object *newObjects;
+	yaffs_ObjectList *list;
+
+	if (nObjects < 1)
+		return YAFFS_OK;
+
+	/* make these things */
+	newObjects = YMALLOC(nObjects * sizeof(yaffs_Object));
+	list = YMALLOC(sizeof(yaffs_ObjectList));
+
+	if (!newObjects || !list) {
+		if (newObjects)
+			YFREE(newObjects);
+		if (list)
+			YFREE(list);
+		T(YAFFS_TRACE_ALLOCATE,
+		  (TSTR("yaffs: Could not allocate more objects" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Hook them into the free list */
+	for (i = 0; i < nObjects - 1; i++) {
+		newObjects[i].siblings.next =
+				(struct ylist_head *)(&newObjects[i + 1]);
+	}
+
+	newObjects[nObjects - 1].siblings.next = (void *)dev->freeObjects;
+	dev->freeObjects = newObjects;
+	dev->nFreeObjects += nObjects;
+	dev->nObjectsCreated += nObjects;
+
+	/* Now add this bunch of Objects to a list for freeing up. */
+
+	list->objects = newObjects;
+	list->next = dev->allocatedObjectList;
+	dev->allocatedObjectList = list;
+
+	return YAFFS_OK;
+}
+
+
+/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */
+static yaffs_Object *yaffs_AllocateEmptyObject(yaffs_Device *dev)
+{
+	yaffs_Object *tn = NULL;
+
+#ifdef VALGRIND_TEST
+	tn = YMALLOC(sizeof(yaffs_Object));
+#else
+	/* If there are none left make more */
+	if (!dev->freeObjects)
+		yaffs_CreateFreeObjects(dev, YAFFS_ALLOCATION_NOBJECTS);
+
+	if (dev->freeObjects) {
+		tn = dev->freeObjects;
+		dev->freeObjects =
+			(yaffs_Object *) (dev->freeObjects->siblings.next);
+		dev->nFreeObjects--;
+	}
+#endif
+	if (tn) {
+		/* Now sweeten it up... */
+
+		memset(tn, 0, sizeof(yaffs_Object));
+		tn->beingCreated = 1;
+
+		tn->myDev = dev;
+		tn->hdrChunk = 0;
+		tn->variantType = YAFFS_OBJECT_TYPE_UNKNOWN;
+		YINIT_LIST_HEAD(&(tn->hardLinks));
+		YINIT_LIST_HEAD(&(tn->hashLink));
+		YINIT_LIST_HEAD(&tn->siblings);
+
+
+		/* Now make the directory sane */
+		if (dev->rootDir) {
+			tn->parent = dev->rootDir;
+			ylist_add(&(tn->siblings), &dev->rootDir->variant.directoryVariant.children);
+		}
+
+		/* Add it to the lost and found directory.
+		 * NB Can't put root or lostNFound in lostNFound so
+		 * check if lostNFound exists first
+		 */
+		if (dev->lostNFoundDir)
+			yaffs_AddObjectToDirectory(dev->lostNFoundDir, tn);
+
+		tn->beingCreated = 0;
+	}
+
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+
+	return tn;
+}
+
+static yaffs_Object *yaffs_CreateFakeDirectory(yaffs_Device *dev, int number,
+					       __u32 mode)
+{
+
+	yaffs_Object *obj =
+	    yaffs_CreateNewObject(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY);
+	if (obj) {
+		obj->fake = 1;		/* it is fake so it might have no NAND presence... */
+		obj->renameAllowed = 0;	/* ... and we're not allowed to rename it... */
+		obj->unlinkAllowed = 0;	/* ... or unlink it */
+		obj->deleted = 0;
+		obj->unlinked = 0;
+		obj->yst_mode = mode;
+		obj->myDev = dev;
+		obj->hdrChunk = 0;	/* Not a valid chunk. */
+	}
+
+	return obj;
+
+}
+
+static void yaffs_UnhashObject(yaffs_Object *tn)
+{
+	int bucket;
+	yaffs_Device *dev = tn->myDev;
+
+	/* If it is still linked into the bucket list, free from the list */
+	if (!ylist_empty(&tn->hashLink)) {
+		ylist_del_init(&tn->hashLink);
+		bucket = yaffs_HashFunction(tn->objectId);
+		dev->objectBucket[bucket].count--;
+	}
+}
+
+/*  FreeObject frees up a Object and puts it back on the free list */
+static void yaffs_FreeObject(yaffs_Object *tn)
+{
+	yaffs_Device *dev = tn->myDev;
+
+#ifdef __KERNEL__
+	T(YAFFS_TRACE_OS, (TSTR("FreeObject %p inode %p"TENDSTR), tn, tn->myInode));
+#endif
+
+	if (tn->parent)
+		YBUG();
+	if (!ylist_empty(&tn->siblings))
+		YBUG();
+
+
+#ifdef __KERNEL__
+	if (tn->myInode) {
+		/* We're still hooked up to a cached inode.
+		 * Don't delete now, but mark for later deletion
+		 */
+		tn->deferedFree = 1;
+		return;
+	}
+#endif
+
+	yaffs_UnhashObject(tn);
+
+#ifdef VALGRIND_TEST
+	YFREE(tn);
+#else
+	/* Link into the free list. */
+	tn->siblings.next = (struct ylist_head *)(dev->freeObjects);
+	dev->freeObjects = tn;
+	dev->nFreeObjects++;
+#endif
+	dev->nCheckpointBlocksRequired = 0; /* force recalculation*/
+}
+
+#ifdef __KERNEL__
+
+void yaffs_HandleDeferedFree(yaffs_Object *obj)
+{
+	if (obj->deferedFree)
+		yaffs_FreeObject(obj);
+}
+
+#endif
+
+static void yaffs_DeinitialiseObjects(yaffs_Device *dev)
+{
+	/* Free the list of allocated Objects */
+
+	yaffs_ObjectList *tmp;
+
+	while (dev->allocatedObjectList) {
+		tmp = dev->allocatedObjectList->next;
+		YFREE(dev->allocatedObjectList->objects);
+		YFREE(dev->allocatedObjectList);
+
+		dev->allocatedObjectList = tmp;
+	}
+
+	dev->freeObjects = NULL;
+	dev->nFreeObjects = 0;
+}
+
+static void yaffs_InitialiseObjects(yaffs_Device *dev)
+{
+	int i;
+
+	dev->allocatedObjectList = NULL;
+	dev->freeObjects = NULL;
+	dev->nFreeObjects = 0;
+
+	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
+		YINIT_LIST_HEAD(&dev->objectBucket[i].list);
+		dev->objectBucket[i].count = 0;
+	}
+}
+
+static int yaffs_FindNiceObjectBucket(yaffs_Device *dev)
+{
+	static int x;
+	int i;
+	int l = 999;
+	int lowest = 999999;
+
+	/* First let's see if we can find one that's empty. */
+
+	for (i = 0; i < 10 && lowest > 0; i++) {
+		x++;
+		x %= YAFFS_NOBJECT_BUCKETS;
+		if (dev->objectBucket[x].count < lowest) {
+			lowest = dev->objectBucket[x].count;
+			l = x;
+		}
+
+	}
+
+	/* If we didn't find an empty list, then try
+	 * looking a bit further for a short one
+	 */
+
+	for (i = 0; i < 10 && lowest > 3; i++) {
+		x++;
+		x %= YAFFS_NOBJECT_BUCKETS;
+		if (dev->objectBucket[x].count < lowest) {
+			lowest = dev->objectBucket[x].count;
+			l = x;
+		}
+
+	}
+
+	return l;
+}
+
+static int yaffs_CreateNewObjectNumber(yaffs_Device *dev)
+{
+	int bucket = yaffs_FindNiceObjectBucket(dev);
+
+	/* Now find an object value that has not already been taken
+	 * by scanning the list.
+	 */
+
+	int found = 0;
+	struct ylist_head *i;
+
+	__u32 n = (__u32) bucket;
+
+	/* yaffs_CheckObjectHashSanity();  */
+
+	while (!found) {
+		found = 1;
+		n += YAFFS_NOBJECT_BUCKETS;
+		if (1 || dev->objectBucket[bucket].count > 0) {
+			ylist_for_each(i, &dev->objectBucket[bucket].list) {
+				/* If there is already one in the list */
+				if (i && ylist_entry(i, yaffs_Object,
+						hashLink)->objectId == n) {
+					found = 0;
+				}
+			}
+		}
+	}
+
+	return n;
+}
+
+static void yaffs_HashObject(yaffs_Object *in)
+{
+	int bucket = yaffs_HashFunction(in->objectId);
+	yaffs_Device *dev = in->myDev;
+
+	ylist_add(&in->hashLink, &dev->objectBucket[bucket].list);
+	dev->objectBucket[bucket].count++;
+}
+
+yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device *dev, __u32 number)
+{
+	int bucket = yaffs_HashFunction(number);
+	struct ylist_head *i;
+	yaffs_Object *in;
+
+	ylist_for_each(i, &dev->objectBucket[bucket].list) {
+		/* Look if it is in the list */
+		if (i) {
+			in = ylist_entry(i, yaffs_Object, hashLink);
+			if (in->objectId == number) {
+#ifdef __KERNEL__
+				/* Don't tell the VFS about this one if it is defered free */
+				if (in->deferedFree)
+					return NULL;
+#endif
+
+				return in;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+yaffs_Object *yaffs_CreateNewObject(yaffs_Device *dev, int number,
+				    yaffs_ObjectType type)
+{
+	yaffs_Object *theObject;
+	yaffs_Tnode *tn = NULL;
+
+	if (number < 0)
+		number = yaffs_CreateNewObjectNumber(dev);
+
+	theObject = yaffs_AllocateEmptyObject(dev);
+	if (!theObject)
+		return NULL;
+
+	if (type == YAFFS_OBJECT_TYPE_FILE) {
+		tn = yaffs_GetTnode(dev);
+		if (!tn) {
+			yaffs_FreeObject(theObject);
+			return NULL;
+		}
+	}
+
+	if (theObject) {
+		theObject->fake = 0;
+		theObject->renameAllowed = 1;
+		theObject->unlinkAllowed = 1;
+		theObject->objectId = number;
+		yaffs_HashObject(theObject);
+		theObject->variantType = type;
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_WinFileTimeNow(theObject->win_atime);
+		theObject->win_ctime[0] = theObject->win_mtime[0] =
+		    theObject->win_atime[0];
+		theObject->win_ctime[1] = theObject->win_mtime[1] =
+		    theObject->win_atime[1];
+
+#else
+
+		theObject->yst_atime = theObject->yst_mtime =
+		    theObject->yst_ctime = Y_CURRENT_TIME;
+#endif
+		switch (type) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			theObject->variant.fileVariant.fileSize = 0;
+			theObject->variant.fileVariant.scannedFileSize = 0;
+			theObject->variant.fileVariant.shrinkSize = 0xFFFFFFFF;	/* max __u32 */
+			theObject->variant.fileVariant.topLevel = 0;
+			theObject->variant.fileVariant.top = tn;
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			YINIT_LIST_HEAD(&theObject->variant.directoryVariant.
+					children);
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			/* No action required */
+			break;
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* todo this should not happen */
+			break;
+		}
+	}
+
+	return theObject;
+}
+
+static yaffs_Object *yaffs_FindOrCreateObjectByNumber(yaffs_Device *dev,
+						      int number,
+						      yaffs_ObjectType type)
+{
+	yaffs_Object *theObject = NULL;
+
+	if (number > 0)
+	{
+		theObject = yaffs_FindObjectByNumber(dev, number);
+		
+	}
+
+	if (!theObject)
+	{
+
+		theObject = yaffs_CreateNewObject(dev, number, type);
+	}
+
+	return theObject;
+
+}
+
+
+static YCHAR *yaffs_CloneString(const YCHAR *str)
+{
+	YCHAR *newStr = NULL;
+
+	if (str && *str) {
+		newStr = YMALLOC((yaffs_strlen(str) + 1) * sizeof(YCHAR));
+		if (newStr)
+			yaffs_strcpy(newStr, str);
+	}
+
+	return newStr;
+
+}
+
+/*
+ * Mknod (create) a new object.
+ * equivalentObject only has meaning for a hard link;
+ * aliasString only has meaning for a sumlink.
+ * rdev only has meaning for devices (a subset of special objects)
+ */
+
+static yaffs_Object *yaffs_MknodObject(yaffs_ObjectType type,
+				       yaffs_Object *parent,
+				       const YCHAR *name,
+				       __u32 mode,
+				       __u32 uid,
+				       __u32 gid,
+				       yaffs_Object *equivalentObject,
+				       const YCHAR *aliasString, __u32 rdev)
+{
+	yaffs_Object *in;
+	YCHAR *str = NULL;
+
+	yaffs_Device *dev = parent->myDev;
+
+	/* Check if the entry exists. If it does then fail the call since we don't want a dup.*/
+	if (yaffs_FindObjectByName(parent, name))
+		return NULL;
+
+	in = yaffs_CreateNewObject(dev, -1, type);
+
+	if (!in)
+		return YAFFS_FAIL;
+
+	if (type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		str = yaffs_CloneString(aliasString);
+		if (!str) {
+			yaffs_FreeObject(in);
+			return NULL;
+		}
+	}
+
+
+
+	if (in) {
+		in->hdrChunk = 0;
+		in->valid = 1;
+		in->variantType = type;
+
+		in->yst_mode = mode;
+
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_WinFileTimeNow(in->win_atime);
+		in->win_ctime[0] = in->win_mtime[0] = in->win_atime[0];
+		in->win_ctime[1] = in->win_mtime[1] = in->win_atime[1];
+
+#else
+		in->yst_atime = in->yst_mtime = in->yst_ctime = Y_CURRENT_TIME;
+
+		in->yst_rdev = rdev;
+		in->yst_uid = uid;
+		in->yst_gid = gid;
+#endif
+		in->nDataChunks = 0;
+
+		yaffs_SetObjectName(in, name);
+		in->dirty = 1;
+
+		yaffs_AddObjectToDirectory(parent, in);
+
+		in->myDev = parent->myDev;
+
+		switch (type) {
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			in->variant.symLinkVariant.alias = str;
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+			in->variant.hardLinkVariant.equivalentObject =
+				equivalentObject;
+			in->variant.hardLinkVariant.equivalentObjectId =
+				equivalentObject->objectId;
+			ylist_add(&in->hardLinks, &equivalentObject->hardLinks);
+			break;
+		case YAFFS_OBJECT_TYPE_FILE:
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* do nothing */
+			break;
+		}
+
+		if (yaffs_UpdateObjectHeader(in, name, 0, 0, 0) < 0) {
+			/* Could not create the object header, fail the creation */
+			yaffs_DeleteObject(in);
+			in = NULL;
+		}
+
+		yaffs_UpdateParent(parent);
+	}
+
+	return in;
+}
+
+yaffs_Object *yaffs_MknodFile(yaffs_Object *parent, const YCHAR *name,
+			__u32 mode, __u32 uid, __u32 gid)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_FILE, parent, name, mode,
+				uid, gid, NULL, NULL, 0);
+}
+
+yaffs_Object *yaffs_MknodDirectory(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name,
+				 mode, uid, gid, NULL, NULL, 0);
+}
+
+yaffs_Object *yaffs_MknodSpecial(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid, __u32 rdev)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode,
+				 uid, gid, NULL, NULL, rdev);
+}
+
+yaffs_Object *yaffs_MknodSymLink(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid,
+				const YCHAR *alias)
+{
+	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode,
+				uid, gid, NULL, alias, 0);
+}
+
+/* yaffs_Link returns the object id of the equivalent object.*/
+yaffs_Object *yaffs_Link(yaffs_Object *parent, const YCHAR *name,
+			yaffs_Object *equivalentObject)
+{
+	/* Get the real object in case we were fed a hard link as an equivalent object */
+	equivalentObject = yaffs_GetEquivalentObject(equivalentObject);
+
+	if (yaffs_MknodObject
+	    (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0,
+	     equivalentObject, NULL, 0)) {
+		return equivalentObject;
+	} else {
+		return NULL;
+	}
+
+}
+
+static int yaffs_ChangeObjectName(yaffs_Object *obj, yaffs_Object *newDir,
+				const YCHAR *newName, int force, int shadows)
+{
+	int unlinkOp;
+	int deleteOp;
+
+	yaffs_Object *existingTarget;
+
+	if (newDir == NULL)
+		newDir = obj->parent;	/* use the old directory */
+
+	if (newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_ChangeObjectName: newDir is not a directory"
+		    TENDSTR)));
+		YBUG();
+	}
+
+	/* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */
+	if (obj->myDev->isYaffs2)
+		unlinkOp = (newDir == obj->myDev->unlinkedDir);
+	else
+		unlinkOp = (newDir == obj->myDev->unlinkedDir
+			    && obj->variantType == YAFFS_OBJECT_TYPE_FILE);
+
+	deleteOp = (newDir == obj->myDev->deletedDir);
+
+	existingTarget = yaffs_FindObjectByName(newDir, newName);
+
+	/* If the object is a file going into the unlinked directory,
+	 *   then it is OK to just stuff it in since duplicate names are allowed.
+	 *   else only proceed if the new name does not exist and if we're putting
+	 *   it into a directory.
+	 */
+	if ((unlinkOp ||
+	     deleteOp ||
+	     force ||
+	     (shadows > 0) ||
+	     !existingTarget) &&
+	    newDir->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_SetObjectName(obj, newName);
+		obj->dirty = 1;
+
+		yaffs_AddObjectToDirectory(newDir, obj);
+
+		if (unlinkOp)
+			obj->unlinked = 1;
+
+		/* If it is a deletion then we mark it as a shrink for gc purposes. */
+		if (yaffs_UpdateObjectHeader(obj, newName, 0, deleteOp, shadows) >= 0)
+			return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+int yaffs_RenameObject(yaffs_Object *oldDir, const YCHAR *oldName,
+		yaffs_Object *newDir, const YCHAR *newName)
+{
+	yaffs_Object *obj = NULL;
+	yaffs_Object *existingTarget = NULL;
+	int force = 0;
+	int result;
+	yaffs_Device *dev;
+
+
+	if (!oldDir || oldDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+	if (!newDir || newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+
+	dev = oldDir->myDev;
+
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+	/* Special case for case insemsitive systems (eg. WinCE).
+	 * While look-up is case insensitive, the name isn't.
+	 * Therefore we might want to change x.txt to X.txt
+	*/
+	if (oldDir == newDir && yaffs_strcmp(oldName, newName) == 0)
+		force = 1;
+#endif
+
+	if(yaffs_strlen(newName) > YAFFS_MAX_NAME_LENGTH)
+		/* ENAMETOOLONG */
+		return YAFFS_FAIL;
+
+	obj = yaffs_FindObjectByName(oldDir, oldName);
+
+	if (obj && obj->renameAllowed) {
+
+		/* Now do the handling for an existing target, if there is one */
+
+		existingTarget = yaffs_FindObjectByName(newDir, newName);
+		if (existingTarget &&
+			existingTarget->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+			!ylist_empty(&existingTarget->variant.directoryVariant.children)) {
+			/* There is a target that is a non-empty directory, so we fail */
+			return YAFFS_FAIL;	/* EEXIST or ENOTEMPTY */
+		} else if (existingTarget && existingTarget != obj) {
+			/* Nuke the target first, using shadowing,
+			 * but only if it isn't the same object.
+			 *
+			 * Note we must disable gc otherwise it can mess up the shadowing.
+			 *
+			 */
+			dev->isDoingGC=1;
+			yaffs_ChangeObjectName(obj, newDir, newName, force,
+						existingTarget->objectId);
+			existingTarget->isShadowed = 1;
+			yaffs_UnlinkObject(existingTarget);
+			dev->isDoingGC=0;
+		}
+
+		result = yaffs_ChangeObjectName(obj, newDir, newName, 1, 0);
+
+		yaffs_UpdateParent(oldDir);
+		if(newDir != oldDir)
+			yaffs_UpdateParent(newDir);
+
+		return result;
+	}
+	return YAFFS_FAIL;
+}
+
+/*------------------------- Block Management and Page Allocation ----------------*/
+
+static int yaffs_InitialiseBlocks(yaffs_Device *dev)
+{
+	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
+
+	dev->blockInfo = NULL;
+	dev->chunkBits = NULL;
+
+	dev->allocationBlock = -1;	/* force it to get a new one */
+
+	/* If the first allocation strategy fails, thry the alternate one */
+	dev->blockInfo = YMALLOC(nBlocks * sizeof(yaffs_BlockInfo));
+	if (!dev->blockInfo) {
+		dev->blockInfo = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockInfo));
+		dev->blockInfoAlt = 1;
+	} else
+		dev->blockInfoAlt = 0;
+
+	if (dev->blockInfo) {
+		/* Set up dynamic blockinfo stuff. */
+		dev->chunkBitmapStride = (dev->nChunksPerBlock + 7) / 8; /* round up bytes */
+		dev->chunkBits = YMALLOC(dev->chunkBitmapStride * nBlocks);
+		if (!dev->chunkBits) {
+			dev->chunkBits = YMALLOC_ALT(dev->chunkBitmapStride * nBlocks);
+			dev->chunkBitsAlt = 1;
+		} else
+			dev->chunkBitsAlt = 0;
+	}
+
+	if (dev->blockInfo && dev->chunkBits) {
+		memset(dev->blockInfo, 0, nBlocks * sizeof(yaffs_BlockInfo));
+		memset(dev->chunkBits, 0, dev->chunkBitmapStride * nBlocks);
+		return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+static void yaffs_DeinitialiseBlocks(yaffs_Device *dev)
+{
+	if (dev->blockInfoAlt && dev->blockInfo)
+		YFREE_ALT(dev->blockInfo);
+	else if (dev->blockInfo)
+		YFREE(dev->blockInfo);
+
+	dev->blockInfoAlt = 0;
+
+	dev->blockInfo = NULL;
+
+	if (dev->chunkBitsAlt && dev->chunkBits)
+		YFREE_ALT(dev->chunkBits);
+	else if (dev->chunkBits)
+		YFREE(dev->chunkBits);
+	dev->chunkBitsAlt = 0;
+	dev->chunkBits = NULL;
+}
+
+static int yaffs_BlockNotDisqualifiedFromGC(yaffs_Device *dev,
+					yaffs_BlockInfo *bi)
+{
+	int i;
+	__u32 seq;
+	yaffs_BlockInfo *b;
+
+	if (!dev->isYaffs2)
+		return 1;	/* disqualification only applies to yaffs2. */
+
+	if (!bi->hasShrinkHeader)
+		return 1;	/* can gc */
+
+	/* Find the oldest dirty sequence number if we don't know it and save it
+	 * so we don't have to keep recomputing it.
+	 */
+	if (!dev->oldestDirtySequence) {
+		seq = dev->sequenceNumber;
+
+		for (i = dev->internalStartBlock; i <= dev->internalEndBlock;
+				i++) {
+			b = yaffs_GetBlockInfo(dev, i);
+			if (b->blockState == YAFFS_BLOCK_STATE_FULL &&
+			    (b->pagesInUse - b->softDeletions) <
+			    dev->nChunksPerBlock && b->sequenceNumber < seq) {
+				seq = b->sequenceNumber;
+			}
+		}
+		dev->oldestDirtySequence = seq;
+	}
+
+	/* Can't do gc of this block if there are any blocks older than this one that have
+	 * discarded pages.
+	 */
+	return (bi->sequenceNumber <= dev->oldestDirtySequence);
+}
+
+/* FindDiretiestBlock is used to select the dirtiest block (or close enough)
+ * for garbage collection.
+ */
+
+static int yaffs_FindBlockForGarbageCollection(yaffs_Device *dev,
+					int aggressive)
+{
+	int b = dev->currentDirtyChecker;
+
+	int i;
+	int iterations;
+	int dirtiest = -1;
+	int pagesInUse = 0;
+	int prioritised = 0;
+	yaffs_BlockInfo *bi;
+	int pendingPrioritisedExist = 0;
+
+	/* First let's see if we need to grab a prioritised block */
+	if (dev->hasPendingPrioritisedGCs) {
+		for (i = dev->internalStartBlock; i < dev->internalEndBlock && !prioritised; i++) {
+
+			bi = yaffs_GetBlockInfo(dev, i);
+			/* yaffs_VerifyBlock(dev,bi,i); */
+
+			if (bi->gcPrioritise) {
+				pendingPrioritisedExist = 1;
+				if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
+				   yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
+					pagesInUse = (bi->pagesInUse - bi->softDeletions);
+					dirtiest = i;
+					prioritised = 1;
+					aggressive = 1; /* Fool the non-aggressive skip logiv below */
+				}
+			}
+		}
+
+		if (!pendingPrioritisedExist) /* None found, so we can clear this */
+			dev->hasPendingPrioritisedGCs = 0;
+	}
+
+	/* If we're doing aggressive GC then we are happy to take a less-dirty block, and
+	 * search harder.
+	 * else (we're doing a leasurely gc), then we only bother to do this if the
+	 * block has only a few pages in use.
+	 */
+
+	dev->nonAggressiveSkip--;
+
+	if (!aggressive && (dev->nonAggressiveSkip > 0))
+		return -1;
+
+	if (!prioritised)
+		pagesInUse =
+			(aggressive) ? dev->nChunksPerBlock : YAFFS_PASSIVE_GC_CHUNKS + 1;
+
+	if (aggressive)
+		iterations =
+		    dev->internalEndBlock - dev->internalStartBlock + 1;
+	else {
+		iterations =
+		    dev->internalEndBlock - dev->internalStartBlock + 1;
+		iterations = iterations / 16;
+		if (iterations > 200)
+			iterations = 200;
+	}
+
+	for (i = 0; i <= iterations && pagesInUse > 0 && !prioritised; i++) {
+		b++;
+		if (b < dev->internalStartBlock || b > dev->internalEndBlock)
+			b = dev->internalStartBlock;
+
+		if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("**>> Block %d is not valid" TENDSTR), b));
+			YBUG();
+		}
+
+		bi = yaffs_GetBlockInfo(dev, b);
+
+		if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
+			(bi->pagesInUse - bi->softDeletions) < pagesInUse &&
+				yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
+			dirtiest = b;
+			pagesInUse = (bi->pagesInUse - bi->softDeletions);
+		}
+	}
+
+	dev->currentDirtyChecker = b;
+
+	if (dirtiest > 0) {
+		T(YAFFS_TRACE_GC,
+		  (TSTR("GC Selected block %d with %d free, prioritised:%d" TENDSTR), dirtiest,
+		   dev->nChunksPerBlock - pagesInUse, prioritised));
+	}
+
+	dev->oldestDirtySequence = 0;
+
+	if (dirtiest > 0)
+		dev->nonAggressiveSkip = 4;
+
+	return dirtiest;
+}
+
+static void yaffs_BlockBecameDirty(yaffs_Device *dev, int blockNo)
+{
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockNo);
+
+	int erasedOk = 0;
+
+	/* If the block is still healthy erase it and mark as clean.
+	 * If the block has had a data failure, then retire it.
+	 */
+
+	T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE,
+		(TSTR("yaffs_BlockBecameDirty block %d state %d %s"TENDSTR),
+		blockNo, bi->blockState, (bi->needsRetiring) ? "needs retiring" : ""));
+
+	bi->blockState = YAFFS_BLOCK_STATE_DIRTY;
+
+	if (!bi->needsRetiring) {
+		yaffs_InvalidateCheckpoint(dev);
+		erasedOk = yaffs_EraseBlockInNAND(dev, blockNo);
+		if (!erasedOk) {
+			dev->nErasureFailures++;
+			T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("**>> Erasure failed %d" TENDSTR), blockNo));
+		}
+	}
+
+	if (erasedOk &&
+	    ((yaffs_traceMask & YAFFS_TRACE_ERASE) || !yaffs_SkipVerification(dev))) {
+		int i;
+		for (i = 0; i < dev->nChunksPerBlock; i++) {
+			if (!yaffs_CheckChunkErased
+			    (dev, blockNo * dev->nChunksPerBlock + i)) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   (">>Block %d erasure supposedly OK, but chunk %d not erased"
+				    TENDSTR), blockNo, i));
+			}
+		}
+	}
+
+	if (erasedOk) {
+		/* Clean it up... */
+		bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
+		dev->nErasedBlocks++;
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+		bi->hasShrinkHeader = 0;
+		bi->skipErasedCheck = 1;  /* This is clean, so no need to check */
+		bi->gcPrioritise = 0;
+		yaffs_ClearChunkBits(dev, blockNo);
+
+		T(YAFFS_TRACE_ERASE,
+		  (TSTR("Erased block %d" TENDSTR), blockNo));
+	} else {
+		dev->nFreeChunks -= dev->nChunksPerBlock;	/* We lost a block of free space */
+
+		yaffs_RetireBlock(dev, blockNo);
+		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		  (TSTR("**>> Block %d retired" TENDSTR), blockNo));
+	}
+}
+
+static int yaffs_FindBlockForAllocation(yaffs_Device *dev)
+{
+	int i;
+
+	yaffs_BlockInfo *bi;
+
+	if (dev->nErasedBlocks < 1) {
+		/* Hoosterman we've got a problem.
+		 * Can't get space to gc
+		 */
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR("yaffs tragedy: no more erased blocks" TENDSTR)));
+
+		return -1;
+	}
+
+	/* Find an empty block. */
+
+	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
+		dev->allocationBlockFinder++;
+		if (dev->allocationBlockFinder < dev->internalStartBlock
+		    || dev->allocationBlockFinder > dev->internalEndBlock) {
+			dev->allocationBlockFinder = dev->internalStartBlock;
+		}
+
+		bi = yaffs_GetBlockInfo(dev, dev->allocationBlockFinder);
+
+		if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
+			bi->blockState = YAFFS_BLOCK_STATE_ALLOCATING;
+			dev->sequenceNumber++;
+			bi->sequenceNumber = dev->sequenceNumber;
+			dev->nErasedBlocks--;
+			T(YAFFS_TRACE_ALLOCATE,
+			  (TSTR("Allocated block %d, seq  %d, %d left" TENDSTR),
+			   dev->allocationBlockFinder, dev->sequenceNumber,
+			   dev->nErasedBlocks));
+			return dev->allocationBlockFinder;
+		}
+	}
+
+	T(YAFFS_TRACE_ALWAYS,
+	  (TSTR
+	   ("yaffs tragedy: no more erased blocks, but there should have been %d"
+	    TENDSTR), dev->nErasedBlocks));
+
+	return -1;
+}
+
+
+
+static int yaffs_CalcCheckpointBlocksRequired(yaffs_Device *dev)
+{
+	if (!dev->nCheckpointBlocksRequired &&
+	   dev->isYaffs2) {
+		/* Not a valid value so recalculate */
+		int nBytes = 0;
+		int nBlocks;
+		int devBlocks = (dev->endBlock - dev->startBlock + 1);
+		int tnodeSize;
+
+		tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+		if (tnodeSize < sizeof(yaffs_Tnode))
+			tnodeSize = sizeof(yaffs_Tnode);
+
+		nBytes += sizeof(yaffs_CheckpointValidity);
+		nBytes += sizeof(yaffs_CheckpointDevice);
+		nBytes += devBlocks * sizeof(yaffs_BlockInfo);
+		nBytes += devBlocks * dev->chunkBitmapStride;
+		nBytes += (sizeof(yaffs_CheckpointObject) + sizeof(__u32)) * (dev->nObjectsCreated - dev->nFreeObjects);
+		nBytes += (tnodeSize + sizeof(__u32)) * (dev->nTnodesCreated - dev->nFreeTnodes);
+		nBytes += sizeof(yaffs_CheckpointValidity);
+		nBytes += sizeof(__u32); /* checksum*/
+
+		/* Round up and add 2 blocks to allow for some bad blocks, so add 3 */
+
+		nBlocks = (nBytes/(dev->nDataBytesPerChunk * dev->nChunksPerBlock)) + 3;
+
+		dev->nCheckpointBlocksRequired = nBlocks;
+	}
+
+	return dev->nCheckpointBlocksRequired;
+}
+
+/*
+ * Check if there's space to allocate...
+ * Thinks.... do we need top make this ths same as yaffs_GetFreeChunks()?
+ */
+static int yaffs_CheckSpaceForAllocation(yaffs_Device *dev)
+{
+	int reservedChunks;
+	int reservedBlocks = dev->nReservedBlocks;
+	int checkpointBlocks;
+
+	if (dev->isYaffs2) {
+		checkpointBlocks =  yaffs_CalcCheckpointBlocksRequired(dev) -
+				    dev->blocksInCheckpoint;
+		if (checkpointBlocks < 0)
+			checkpointBlocks = 0;
+	} else {
+		checkpointBlocks = 0;
+	}
+
+	reservedChunks = ((reservedBlocks + checkpointBlocks) * dev->nChunksPerBlock);
+
+	return (dev->nFreeChunks > reservedChunks);
+}
+
+static int yaffs_AllocateChunk(yaffs_Device *dev, int useReserve,
+		yaffs_BlockInfo **blockUsedPtr)
+{
+	int retVal;
+	yaffs_BlockInfo *bi;
+
+	if (dev->allocationBlock < 0) {
+		/* Get next block to allocate off */
+		dev->allocationBlock = yaffs_FindBlockForAllocation(dev);
+		dev->allocationPage = 0;
+	}
+
+	if (!useReserve && !yaffs_CheckSpaceForAllocation(dev)) {
+		/* Not enough space to allocate unless we're allowed to use the reserve. */
+		return -1;
+	}
+
+	if (dev->nErasedBlocks < dev->nReservedBlocks
+			&& dev->allocationPage == 0) {
+		T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR)));
+	}
+
+	/* Next page please.... */
+	if (dev->allocationBlock >= 0) {
+		bi = yaffs_GetBlockInfo(dev, dev->allocationBlock);
+
+		retVal = (dev->allocationBlock * dev->nChunksPerBlock) +
+			dev->allocationPage;
+		bi->pagesInUse++;
+		yaffs_SetChunkBit(dev, dev->allocationBlock,
+				dev->allocationPage);
+
+		dev->allocationPage++;
+
+		dev->nFreeChunks--;
+
+		/* If the block is full set the state to full */
+		if (dev->allocationPage >= dev->nChunksPerBlock) {
+			bi->blockState = YAFFS_BLOCK_STATE_FULL;
+			dev->allocationBlock = -1;
+		}
+
+		if (blockUsedPtr)
+			*blockUsedPtr = bi;
+
+		return retVal;
+	}
+
+	T(YAFFS_TRACE_ERROR,
+			(TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR)));
+
+	return -1;
+}
+
+static int yaffs_GetErasedChunks(yaffs_Device *dev)
+{
+	int n;
+
+	n = dev->nErasedBlocks * dev->nChunksPerBlock;
+
+	if (dev->allocationBlock > 0)
+		n += (dev->nChunksPerBlock - dev->allocationPage);
+
+	return n;
+
+}
+
+static int yaffs_GarbageCollectBlock(yaffs_Device *dev, int block,
+		int wholeBlock)
+{
+	int oldChunk;
+	int newChunk;
+	int markNAND;
+	int retVal = YAFFS_OK;
+	int cleanups = 0;
+	int i;
+	int isCheckpointBlock;
+	int matchingChunk;
+	int maxCopies;
+
+	int chunksBefore = yaffs_GetErasedChunks(dev);
+	int chunksAfter;
+
+	yaffs_ExtendedTags tags;
+
+	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, block);
+
+	yaffs_Object *object;
+
+	isCheckpointBlock = (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT);
+
+
+	T(YAFFS_TRACE_TRACING,
+			(TSTR("Collecting block %d, in use %d, shrink %d, wholeBlock %d" TENDSTR),
+			 block,
+			 bi->pagesInUse,
+			 bi->hasShrinkHeader,
+			 wholeBlock));
+
+	/*yaffs_VerifyFreeChunks(dev); */
+
+	if(bi->blockState == YAFFS_BLOCK_STATE_FULL)
+		bi->blockState = YAFFS_BLOCK_STATE_COLLECTING;
+	
+	bi->hasShrinkHeader = 0;	/* clear the flag so that the block can erase */
+
+	/* Take off the number of soft deleted entries because
+	 * they're going to get really deleted during GC.
+	 */
+	if(dev->gcChunk == 0) /* first time through for this block */
+		dev->nFreeChunks -= bi->softDeletions;
+
+	dev->isDoingGC = 1;
+
+	if (isCheckpointBlock ||
+			!yaffs_StillSomeChunkBits(dev, block)) {
+		T(YAFFS_TRACE_TRACING,
+				(TSTR
+				 ("Collecting block %d that has no chunks in use" TENDSTR),
+				 block));
+		yaffs_BlockBecameDirty(dev, block);
+	} else {
+
+		__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+		yaffs_VerifyBlock(dev, bi, block);
+
+		maxCopies = (wholeBlock) ? dev->nChunksPerBlock : 10;
+		oldChunk = block * dev->nChunksPerBlock + dev->gcChunk;
+
+		for (/* init already done */;
+		     retVal == YAFFS_OK &&
+		     dev->gcChunk < dev->nChunksPerBlock &&
+		     (bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) &&
+		     maxCopies > 0;
+		     dev->gcChunk++, oldChunk++) {
+			if (yaffs_CheckChunkBit(dev, block, dev->gcChunk)) {
+
+				/* This page is in use and might need to be copied off */
+
+				maxCopies--;
+
+				markNAND = 1;
+
+				yaffs_InitialiseTags(&tags);
+
+				yaffs_ReadChunkWithTagsFromNAND(dev, oldChunk,
+								buffer, &tags);
+
+				object =
+				    yaffs_FindObjectByNumber(dev,
+							     tags.objectId);
+
+				T(YAFFS_TRACE_GC_DETAIL,
+				  (TSTR
+				   ("Collecting chunk in block %d, %d %d %d " TENDSTR),
+				   dev->gcChunk, tags.objectId, tags.chunkId,
+				   tags.byteCount));
+
+				if (object && !yaffs_SkipVerification(dev)) {
+					if (tags.chunkId == 0)
+						matchingChunk = object->hdrChunk;
+					else if (object->softDeleted)
+						matchingChunk = oldChunk; /* Defeat the test */
+					else
+						matchingChunk = yaffs_FindChunkInFile(object, tags.chunkId, NULL);
+
+					if (oldChunk != matchingChunk)
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR("gc: page in gc mismatch: %d %d %d %d"TENDSTR),
+						  oldChunk, matchingChunk, tags.objectId, tags.chunkId));
+
+				}
+
+				if (!object) {
+					T(YAFFS_TRACE_ERROR,
+					  (TSTR
+					   ("page %d in gc has no object: %d %d %d "
+					    TENDSTR), oldChunk,
+					    tags.objectId, tags.chunkId, tags.byteCount));
+				}
+
+				if (object &&
+				    object->deleted &&
+				    object->softDeleted &&
+				    tags.chunkId != 0) {
+					/* Data chunk in a soft deleted file, throw it away
+					 * It's a soft deleted data chunk,
+					 * No need to copy this, just forget about it and
+					 * fix up the object.
+					 */
+
+					object->nDataChunks--;
+
+					if (object->nDataChunks <= 0) {
+						/* remeber to clean up the object */
+						dev->gcCleanupList[cleanups] =
+						    tags.objectId;
+						cleanups++;
+					}
+					markNAND = 0;
+				} else if (0) {
+					/* Todo object && object->deleted && object->nDataChunks == 0 */
+					/* Deleted object header with no data chunks.
+					 * Can be discarded and the file deleted.
+					 */
+					object->hdrChunk = 0;
+					yaffs_FreeTnode(object->myDev,
+							object->variant.
+							fileVariant.top);
+					object->variant.fileVariant.top = NULL;
+					yaffs_DoGenericObjectDeletion(object);
+
+				} else if (object) {
+					/* It's either a data chunk in a live file or
+					 * an ObjectHeader, so we're interested in it.
+					 * NB Need to keep the ObjectHeaders of deleted files
+					 * until the whole file has been deleted off
+					 */
+					tags.serialNumber++;
+
+					dev->nGCCopies++;
+
+					if (tags.chunkId == 0) {
+						/* It is an object Id,
+						 * We need to nuke the shrinkheader flags first
+						 * Also need to clean up shadowing.
+						 * We no longer want the shrinkHeader flag since its work is done
+						 * and if it is left in place it will mess up scanning.
+						 */
+
+						yaffs_ObjectHeader *oh;
+						oh = (yaffs_ObjectHeader *)buffer;
+						oh->isShrink = 0;
+						tags.extraIsShrinkHeader = 0;
+						oh->shadowsObject = 0;
+						oh->inbandShadowsObject = 0;
+						tags.extraShadows = 0;
+
+						yaffs_VerifyObjectHeader(object, oh, &tags, 1);
+					}
+
+					newChunk =
+					    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &tags, 1);
+
+					if (newChunk < 0) {
+						retVal = YAFFS_FAIL;
+					} else {
+
+						/* Ok, now fix up the Tnodes etc. */
+
+						if (tags.chunkId == 0) {
+							/* It's a header */
+							object->hdrChunk =  newChunk;
+							object->serial =   tags.serialNumber;
+						} else {
+							/* It's a data chunk */
+							yaffs_PutChunkIntoFile
+							    (object,
+							     tags.chunkId,
+							     newChunk, 0);
+						}
+					}
+				}
+
+				if (retVal == YAFFS_OK)
+					yaffs_DeleteChunk(dev, oldChunk, markNAND, __LINE__);
+
+			}
+		}
+
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+
+
+		/* Do any required cleanups */
+		for (i = 0; i < cleanups; i++) {
+			/* Time to delete the file too */
+			object =
+			    yaffs_FindObjectByNumber(dev,
+						     dev->gcCleanupList[i]);
+			if (object) {
+				yaffs_FreeTnode(dev,
+						object->variant.fileVariant.
+						top);
+				object->variant.fileVariant.top = NULL;
+				T(YAFFS_TRACE_GC,
+				  (TSTR
+				   ("yaffs: About to finally delete object %d"
+				    TENDSTR), object->objectId));
+				yaffs_DoGenericObjectDeletion(object);
+				object->myDev->nDeletedFiles--;
+			}
+
+		}
+
+	}
+
+	yaffs_VerifyCollectedBlock(dev, bi, block);
+
+	chunksAfter = yaffs_GetErasedChunks(dev);
+	if (chunksBefore >= chunksAfter) {
+		T(YAFFS_TRACE_GC,
+		  (TSTR
+		   ("gc did not increase free chunks before %d after %d"
+		    TENDSTR), chunksBefore, chunksAfter));
+	}
+
+	/* If the gc completed then clear the current gcBlock so that we find another. */
+	if (bi->blockState != YAFFS_BLOCK_STATE_COLLECTING) {
+		dev->gcBlock = -1;
+		dev->gcChunk = 0;
+	}
+
+	dev->isDoingGC = 0;
+
+	return retVal;
+}
+
+/* New garbage collector
+ * If we're very low on erased blocks then we do aggressive garbage collection
+ * otherwise we do "leasurely" garbage collection.
+ * Aggressive gc looks further (whole array) and will accept less dirty blocks.
+ * Passive gc only inspects smaller areas and will only accept more dirty blocks.
+ *
+ * The idea is to help clear out space in a more spread-out manner.
+ * Dunno if it really does anything useful.
+ */
+static int yaffs_CheckGarbageCollection(yaffs_Device *dev)
+{
+	int block;
+	int aggressive;
+	int gcOk = YAFFS_OK;
+	int maxTries = 0;
+
+	int checkpointBlockAdjust;
+
+	if (dev->isDoingGC) {
+		/* Bail out so we don't get recursive gc */
+		return YAFFS_OK;
+	}
+
+	/* This loop should pass the first time.
+	 * We'll only see looping here if the erase of the collected block fails.
+	 */
+
+	do {
+		maxTries++;
+
+		checkpointBlockAdjust = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
+		if (checkpointBlockAdjust < 0)
+			checkpointBlockAdjust = 0;
+
+		if (dev->nErasedBlocks < (dev->nReservedBlocks + checkpointBlockAdjust + 2)) {
+			/* We need a block soon...*/
+			aggressive = 1;
+		} else {
+			/* We're in no hurry */
+			aggressive = 0;
+		}
+
+		if (dev->gcBlock <= 0) {
+			dev->gcBlock = yaffs_FindBlockForGarbageCollection(dev, aggressive);
+			dev->gcChunk = 0;
+		}
+
+		block = dev->gcBlock;
+
+		if (block > 0) {
+			dev->garbageCollections++;
+			if (!aggressive)
+				dev->passiveGarbageCollections++;
+
+			T(YAFFS_TRACE_GC,
+			  (TSTR
+			   ("yaffs: GC erasedBlocks %d aggressive %d" TENDSTR),
+			   dev->nErasedBlocks, aggressive));
+
+			gcOk = yaffs_GarbageCollectBlock(dev, block, aggressive);
+		}
+
+		if (dev->nErasedBlocks < (dev->nReservedBlocks) && block > 0) {
+			T(YAFFS_TRACE_GC,
+			  (TSTR
+			   ("yaffs: GC !!!no reclaim!!! erasedBlocks %d after try %d block %d"
+			    TENDSTR), dev->nErasedBlocks, maxTries, block));
+		}
+	} while ((dev->nErasedBlocks < dev->nReservedBlocks) &&
+		 (block > 0) &&
+		 (maxTries < 2));
+
+	return aggressive ? gcOk : YAFFS_OK;
+}
+
+/*-------------------------  TAGS --------------------------------*/
+
+static int yaffs_TagsMatch(const yaffs_ExtendedTags *tags, int objectId,
+			   int chunkInObject)
+{
+	return (tags->chunkId == chunkInObject &&
+		tags->objectId == objectId && !tags->chunkDeleted) ? 1 : 0;
+
+}
+
+
+/*-------------------- Data file manipulation -----------------*/
+
+static int yaffs_FindChunkInFile(yaffs_Object *in, int chunkInInode,
+				 yaffs_ExtendedTags *tags)
+{
+	/*Get the Tnode, then get the level 0 offset chunk offset */
+	yaffs_Tnode *tn;
+	int theChunk = -1;
+	yaffs_ExtendedTags localTags;
+	int retVal = -1;
+
+	yaffs_Device *dev = in->myDev;
+
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &localTags;
+	}
+
+	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
+
+	if (tn) {
+		theChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+		retVal =
+		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
+					   chunkInInode);
+	}
+	return retVal;
+}
+
+static int yaffs_FindAndDeleteChunkInFile(yaffs_Object *in, int chunkInInode,
+					  yaffs_ExtendedTags *tags)
+{
+	/* Get the Tnode, then get the level 0 offset chunk offset */
+	yaffs_Tnode *tn;
+	int theChunk = -1;
+	yaffs_ExtendedTags localTags;
+
+	yaffs_Device *dev = in->myDev;
+	int retVal = -1;
+
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &localTags;
+	}
+
+	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
+
+	if (tn) {
+
+		theChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+		retVal =
+		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
+					   chunkInInode);
+
+		/* Delete the entry in the filestructure (if found) */
+		if (retVal != -1)
+			yaffs_PutLevel0Tnode(dev, tn, chunkInInode, 0);
+	}
+
+	return retVal;
+}
+
+#ifdef YAFFS_PARANOID
+
+static int yaffs_CheckFileSanity(yaffs_Object *in)
+{
+	int chunk;
+	int nChunks;
+	int fSize;
+	int failed = 0;
+	int objId;
+	yaffs_Tnode *tn;
+	yaffs_Tags localTags;
+	yaffs_Tags *tags = &localTags;
+	int theChunk;
+	int chunkDeleted;
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+
+	objId = in->objectId;
+	fSize = in->variant.fileVariant.fileSize;
+	nChunks =
+	    (fSize + in->myDev->nDataBytesPerChunk - 1) / in->myDev->nDataBytesPerChunk;
+
+	for (chunk = 1; chunk <= nChunks; chunk++) {
+		tn = yaffs_FindLevel0Tnode(in->myDev, &in->variant.fileVariant,
+					   chunk);
+
+		if (tn) {
+
+			theChunk = yaffs_GetChunkGroupBase(dev, tn, chunk);
+
+			if (yaffs_CheckChunkBits
+			    (dev, theChunk / dev->nChunksPerBlock,
+			     theChunk % dev->nChunksPerBlock)) {
+
+				yaffs_ReadChunkTagsFromNAND(in->myDev, theChunk,
+							    tags,
+							    &chunkDeleted);
+				if (yaffs_TagsMatch
+				    (tags, in->objectId, chunk, chunkDeleted)) {
+					/* found it; */
+
+				}
+			} else {
+
+				failed = 1;
+			}
+
+		} else {
+			/* T(("No level 0 found for %d\n", chunk)); */
+		}
+	}
+
+	return failed ? YAFFS_FAIL : YAFFS_OK;
+}
+
+#endif
+
+static int yaffs_PutChunkIntoFile(yaffs_Object *in, int chunkInInode,
+				  int chunkInNAND, int inScan)
+{
+	/* NB inScan is zero unless scanning.
+	 * For forward scanning, inScan is > 0;
+	 * for backward scanning inScan is < 0
+	 */
+
+	yaffs_Tnode *tn;
+	yaffs_Device *dev = in->myDev;
+	int existingChunk;
+	yaffs_ExtendedTags existingTags;
+	yaffs_ExtendedTags newTags;
+	unsigned existingSerial, newSerial;
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
+		/* Just ignore an attempt at putting a chunk into a non-file during scanning
+		 * If it is not during Scanning then something went wrong!
+		 */
+		if (!inScan) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR
+			   ("yaffs tragedy:attempt to put data chunk into a non-file"
+			    TENDSTR)));
+			YBUG();
+		}
+
+		yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+		return YAFFS_OK;
+	}
+
+	tn = yaffs_AddOrFindLevel0Tnode(dev,
+					&in->variant.fileVariant,
+					chunkInInode,
+					NULL);
+	if (!tn)
+	{
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR
+		   ("yaffs_PutChunkIntoFile fail yaffs_AddOrFindLevel0Tnode fail"
+			TENDSTR)));
+
+		return YAFFS_FAIL;
+	}
+
+	existingChunk = yaffs_GetChunkGroupBase(dev, tn, chunkInInode);
+
+	if (inScan != 0) {
+		/* If we're scanning then we need to test for duplicates
+		 * NB This does not need to be efficient since it should only ever
+		 * happen when the power fails during a write, then only one
+		 * chunk should ever be affected.
+		 *
+		 * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO
+		 * Update: For backward scanning we don't need to re-read tags so this is quite cheap.
+		 */
+
+		if (existingChunk > 0) {
+			/* NB Right now existing chunk will not be real chunkId if the device >= 32MB
+			 *    thus we have to do a FindChunkInFile to get the real chunk id.
+			 *
+			 * We have a duplicate now we need to decide which one to use:
+			 *
+			 * Backwards scanning YAFFS2: The old one is what we use, dump the new one.
+			 * Forward scanning YAFFS2: The new one is what we use, dump the old one.
+			 * YAFFS1: Get both sets of tags and compare serial numbers.
+			 */
+
+			if (inScan > 0) {
+				/* Only do this for forward scanning */
+				yaffs_ReadChunkWithTagsFromNAND(dev,
+								chunkInNAND,
+								NULL, &newTags);
+
+				/* Do a proper find */
+				existingChunk =
+				    yaffs_FindChunkInFile(in, chunkInInode,
+							  &existingTags);
+			}
+
+			if (existingChunk <= 0) {
+				/*Hoosterman - how did this happen? */
+
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("yaffs tragedy: existing chunk < 0 in scan"
+				    TENDSTR)));
+
+			}
+
+			/* NB The deleted flags should be false, otherwise the chunks will
+			 * not be loaded during a scan
+			 */
+
+			if (inScan > 0) {
+				newSerial = newTags.serialNumber;
+				existingSerial = existingTags.serialNumber;
+			}
+
+			if ((inScan > 0) &&
+			    (in->myDev->isYaffs2 ||
+			     existingChunk <= 0 ||
+			     ((existingSerial + 1) & 3) == newSerial)) {
+				/* Forward scanning.
+				 * Use new
+				 * Delete the old one and drop through to update the tnode
+				 */
+				yaffs_DeleteChunk(dev, existingChunk, 1,
+						  __LINE__);
+			} else {
+				/* Backward scanning or we want to use the existing one
+				 * Use existing.
+				 * Delete the new one and return early so that the tnode isn't changed
+				 */
+				yaffs_DeleteChunk(dev, chunkInNAND, 1,
+						  __LINE__);
+				return YAFFS_OK;
+			}
+		}
+
+	}
+
+	if (existingChunk == 0)
+		in->nDataChunks++;
+
+	yaffs_PutLevel0Tnode(dev, tn, chunkInInode, chunkInNAND);
+
+	return YAFFS_OK;
+}
+
+static int yaffs_ReadChunkDataFromObject(yaffs_Object *in, int chunkInInode,
+					__u8 *buffer)
+{
+	int chunkInNAND = yaffs_FindChunkInFile(in, chunkInInode, NULL);
+
+	if (chunkInNAND >= 0)
+		return yaffs_ReadChunkWithTagsFromNAND(in->myDev, chunkInNAND,
+						buffer, NULL);
+	else {
+		T(YAFFS_TRACE_NANDACCESS,
+		  (TSTR("Chunk %d not found zero instead" TENDSTR),
+		   chunkInNAND));
+		/* get sane (zero) data if you read a hole */
+		memset(buffer, 0, in->myDev->nDataBytesPerChunk);
+		return 0;
+	}
+
+}
+
+void yaffs_DeleteChunk(yaffs_Device *dev, int chunkId, int markNAND, int lyn)
+{
+	int block;
+	int page;
+	yaffs_ExtendedTags tags;
+	yaffs_BlockInfo *bi;
+
+	if (chunkId <= 0)
+		return;
+
+	dev->nDeletions++;
+	block = chunkId / dev->nChunksPerBlock;
+	page = chunkId % dev->nChunksPerBlock;
+
+
+	if (!yaffs_CheckChunkBit(dev, block, page))
+		T(YAFFS_TRACE_VERIFY,
+			(TSTR("Deleting invalid chunk %d"TENDSTR),
+			 chunkId));
+
+	bi = yaffs_GetBlockInfo(dev, block);
+
+	T(YAFFS_TRACE_DELETION,
+	  (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunkId));
+
+	if (markNAND &&
+	    bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && !dev->isYaffs2) {
+
+		yaffs_InitialiseTags(&tags);
+
+		tags.chunkDeleted = 1;
+
+		yaffs_WriteChunkWithTagsToNAND(dev, chunkId, NULL, &tags);
+		yaffs_HandleUpdateChunk(dev, chunkId, &tags);
+	} else {
+		dev->nUnmarkedDeletions++;
+	}
+
+	/* Pull out of the management area.
+	 * If the whole block became dirty, this will kick off an erasure.
+	 */
+	if (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING ||
+	    bi->blockState == YAFFS_BLOCK_STATE_FULL ||
+	    bi->blockState == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+	    bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) {
+		dev->nFreeChunks++;
+
+		yaffs_ClearChunkBit(dev, block, page);
+
+		bi->pagesInUse--;
+
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState != YAFFS_BLOCK_STATE_ALLOCATING &&
+		    bi->blockState != YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			yaffs_BlockBecameDirty(dev, block);
+		}
+
+	}
+
+}
+
+static int yaffs_WriteChunkDataToObject(yaffs_Object *in, int chunkInInode,
+					const __u8 *buffer, int nBytes,
+					int useReserve)
+{
+	/* Find old chunk Need to do this to get serial number
+	 * Write new one and patch into tree.
+	 * Invalidate old tags.
+	 */
+
+	int prevChunkId;
+	yaffs_ExtendedTags prevTags;
+
+	int newChunkId;
+	yaffs_ExtendedTags newTags;
+
+	yaffs_Device *dev = in->myDev;
+
+	yaffs_CheckGarbageCollection(dev);
+
+	/* Get the previous chunk at this location in the file if it exists */
+	prevChunkId = yaffs_FindChunkInFile(in, chunkInInode, &prevTags);
+
+	/* Set up new tags */
+	yaffs_InitialiseTags(&newTags);
+
+	newTags.chunkId = chunkInInode;
+	newTags.objectId = in->objectId;
+	newTags.serialNumber =
+	    (prevChunkId > 0) ? prevTags.serialNumber + 1 : 1;
+	newTags.byteCount = nBytes;
+
+	if (nBytes < 1 || nBytes > dev->totalBytesPerChunk) {
+		T(YAFFS_TRACE_ERROR,
+		(TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), nBytes));
+		YBUG();
+	}
+
+	newChunkId =
+	    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
+					      useReserve);
+
+	if (newChunkId >= 0) {
+		yaffs_PutChunkIntoFile(in, chunkInInode, newChunkId, 0);
+
+		if (prevChunkId > 0)
+			yaffs_DeleteChunk(dev, prevChunkId, 1, __LINE__);
+
+		yaffs_CheckFileSanity(in);
+	}
+	return newChunkId;
+
+}
+
+/* UpdateObjectHeader updates the header on NAND for an object.
+ * If name is not NULL, then that new name is used.
+ */
+int yaffs_UpdateObjectHeader(yaffs_Object *in, const YCHAR *name, int force,
+			     int isShrink, int shadows)
+{
+
+	yaffs_BlockInfo *bi;
+
+	yaffs_Device *dev = in->myDev;
+
+	int prevChunkId;
+	int retVal = 0;
+	int result = 0;
+
+	int newChunkId;
+	yaffs_ExtendedTags newTags;
+	yaffs_ExtendedTags oldTags;
+
+	__u8 *buffer = NULL;
+	YCHAR oldName[YAFFS_MAX_NAME_LENGTH + 1];
+
+	yaffs_ObjectHeader *oh = NULL;
+
+	yaffs_strcpy(oldName, _Y("silly old name"));
+
+
+	if (!in->fake ||
+		in == dev->rootDir || /* The rootDir should also be saved */
+		force) {
+
+		yaffs_CheckGarbageCollection(dev);
+		yaffs_CheckObjectDetailsLoaded(in);
+
+		buffer = yaffs_GetTempBuffer(in->myDev, __LINE__);
+		oh = (yaffs_ObjectHeader *) buffer;
+
+		prevChunkId = in->hdrChunk;
+
+		if (prevChunkId > 0) {
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
+							buffer, &oldTags);
+
+			yaffs_VerifyObjectHeader(in, oh, &oldTags, 0);
+
+			memcpy(oldName, oh->name, sizeof(oh->name));
+		}
+
+		memset(buffer, 0xFF, dev->nDataBytesPerChunk);
+
+		oh->type = in->variantType;
+		oh->yst_mode = in->yst_mode;
+		oh->shadowsObject = oh->inbandShadowsObject = shadows;
+
+#ifdef CONFIG_YAFFS_WINCE
+		oh->win_atime[0] = in->win_atime[0];
+		oh->win_ctime[0] = in->win_ctime[0];
+		oh->win_mtime[0] = in->win_mtime[0];
+		oh->win_atime[1] = in->win_atime[1];
+		oh->win_ctime[1] = in->win_ctime[1];
+		oh->win_mtime[1] = in->win_mtime[1];
+#else
+		oh->yst_uid = in->yst_uid;
+		oh->yst_gid = in->yst_gid;
+		oh->yst_atime = in->yst_atime;
+		oh->yst_mtime = in->yst_mtime;
+		oh->yst_ctime = in->yst_ctime;
+		oh->yst_rdev = in->yst_rdev;
+#endif
+		if (in->parent)
+			oh->parentObjectId = in->parent->objectId;
+		else
+			oh->parentObjectId = 0;
+
+		if (name && *name) {
+			memset(oh->name, 0, sizeof(oh->name));
+			yaffs_strncpy(oh->name, name, YAFFS_MAX_NAME_LENGTH);
+		} else if (prevChunkId > 0)
+			memcpy(oh->name, oldName, sizeof(oh->name));
+		else
+			memset(oh->name, 0, sizeof(oh->name));
+
+		oh->isShrink = isShrink;
+
+		switch (in->variantType) {
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+			/* Should not happen */
+			break;
+		case YAFFS_OBJECT_TYPE_FILE:
+			oh->fileSize =
+			    (oh->parentObjectId == YAFFS_OBJECTID_DELETED
+			     || oh->parentObjectId ==
+			     YAFFS_OBJECTID_UNLINKED) ? 0 : in->variant.
+			    fileVariant.fileSize;
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+			oh->equivalentObjectId =
+			    in->variant.hardLinkVariant.equivalentObjectId;
+			break;
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			/* Do nothing */
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			/* Do nothing */
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			yaffs_strncpy(oh->alias,
+				      in->variant.symLinkVariant.alias,
+				      YAFFS_MAX_ALIAS_LENGTH);
+			oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0;
+			break;
+		}
+
+		/* Tags */
+		yaffs_InitialiseTags(&newTags);
+		in->serial++;
+		newTags.chunkId = 0;
+		newTags.objectId = in->objectId;
+		newTags.serialNumber = in->serial;
+
+		/* Add extra info for file header */
+
+		newTags.extraHeaderInfoAvailable = 1;
+		newTags.extraParentObjectId = oh->parentObjectId;
+		newTags.extraFileLength = oh->fileSize;
+		newTags.extraIsShrinkHeader = oh->isShrink;
+		newTags.extraEquivalentObjectId = oh->equivalentObjectId;
+		newTags.extraShadows = (oh->shadowsObject > 0) ? 1 : 0;
+		newTags.extraObjectType = in->variantType;
+
+		yaffs_VerifyObjectHeader(in, oh, &newTags, 1);
+
+		/* Create new chunk in NAND */
+		newChunkId =
+		    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
+						      (prevChunkId > 0) ? 1 : 0);
+
+		if (newChunkId >= 0) {
+
+			in->hdrChunk = newChunkId;
+
+			if (prevChunkId > 0) {
+				yaffs_DeleteChunk(dev, prevChunkId, 1,
+						  __LINE__);
+			}
+
+			if (!yaffs_ObjectHasCachedWriteData(in))
+				in->dirty = 0;
+
+			/* If this was a shrink, then mark the block that the chunk lives on */
+			if (isShrink) {
+				bi = yaffs_GetBlockInfo(in->myDev,
+					newChunkId / in->myDev->nChunksPerBlock);
+				bi->hasShrinkHeader = 1;
+			}
+
+		}
+
+		retVal = newChunkId;
+
+	}
+
+	if (buffer)
+		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+
+	return retVal;
+}
+
+/*------------------------ Short Operations Cache ----------------------------------------
+ *   In many situations where there is no high level buffering (eg WinCE) a lot of
+ *   reads might be short sequential reads, and a lot of writes may be short
+ *   sequential writes. eg. scanning/writing a jpeg file.
+ *   In these cases, a short read/write cache can provide a huge perfomance benefit
+ *   with dumb-as-a-rock code.
+ *   In Linux, the page cache provides read buffering aand the short op cache provides write
+ *   buffering.
+ *
+ *   There are a limited number (~10) of cache chunks per device so that we don't
+ *   need a very intelligent search.
+ */
+
+static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	int i;
+	yaffs_ChunkCache *cache;
+	int nCaches = obj->myDev->nShortOpCaches;
+
+	for (i = 0; i < nCaches; i++) {
+		cache = &dev->srCache[i];
+		if (cache->object == obj &&
+		    cache->dirty)
+			return 1;
+	}
+
+	return 0;
+}
+
+
+static void yaffs_FlushFilesChunkCache(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	int lowest = -99;	/* Stop compiler whining. */
+	int i;
+	yaffs_ChunkCache *cache;
+	int chunkWritten = 0;
+	int nCaches = obj->myDev->nShortOpCaches;
+
+	if (nCaches > 0) {
+		do {
+			cache = NULL;
+
+			/* Find the dirty cache for this object with the lowest chunk id. */
+			for (i = 0; i < nCaches; i++) {
+				if (dev->srCache[i].object == obj &&
+				    dev->srCache[i].dirty) {
+					if (!cache
+					    || dev->srCache[i].chunkId <
+					    lowest) {
+						cache = &dev->srCache[i];
+						lowest = cache->chunkId;
+					}
+				}
+			}
+
+			if (cache && !cache->locked) {
+				/* Write it out and free it up */
+
+				chunkWritten =
+				    yaffs_WriteChunkDataToObject(cache->object,
+								 cache->chunkId,
+								 cache->data,
+								 cache->nBytes,
+								 1);
+				cache->dirty = 0;
+				cache->object = NULL;
+			}
+
+		} while (cache && chunkWritten > 0);
+
+		if (cache) {
+			/* Hoosterman, disk full while writing cache out. */
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("yaffs tragedy: no space during cache write" TENDSTR)));
+
+		}
+	}
+
+}
+
+/*yaffs_FlushEntireDeviceCache(dev)
+ *
+ *
+ */
+
+void yaffs_FlushEntireDeviceCache(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	int nCaches = dev->nShortOpCaches;
+	int i;
+
+	/* Find a dirty object in the cache and flush it...
+	 * until there are no further dirty objects.
+	 */
+	do {
+		obj = NULL;
+		for (i = 0; i < nCaches && !obj; i++) {
+			if (dev->srCache[i].object &&
+			    dev->srCache[i].dirty)
+				obj = dev->srCache[i].object;
+
+		}
+		if (obj)
+			yaffs_FlushFilesChunkCache(obj);
+
+	} while (obj);
+
+}
+
+
+/* Grab us a cache chunk for use.
+ * First look for an empty one.
+ * Then look for the least recently used non-dirty one.
+ * Then look for the least recently used dirty one...., flush and look again.
+ */
+static yaffs_ChunkCache *yaffs_GrabChunkCacheWorker(yaffs_Device *dev)
+{
+	int i;
+
+	if (dev->nShortOpCaches > 0) {
+		for (i = 0; i < dev->nShortOpCaches; i++) {
+			if (!dev->srCache[i].object)
+				return &dev->srCache[i];
+		}
+	}
+
+	return NULL;
+}
+
+static yaffs_ChunkCache *yaffs_GrabChunkCache(yaffs_Device *dev)
+{
+	yaffs_ChunkCache *cache;
+	yaffs_Object *theObj;
+	int usage;
+	int i;
+	int pushout;
+
+	if (dev->nShortOpCaches > 0) {
+		/* Try find a non-dirty one... */
+
+		cache = yaffs_GrabChunkCacheWorker(dev);
+
+		if (!cache) {
+			/* They were all dirty, find the last recently used object and flush
+			 * its cache, then  find again.
+			 * NB what's here is not very accurate, we actually flush the object
+			 * the last recently used page.
+			 */
+
+			/* With locking we can't assume we can use entry zero */
+
+			theObj = NULL;
+			usage = -1;
+			cache = NULL;
+			pushout = -1;
+
+			for (i = 0; i < dev->nShortOpCaches; i++) {
+				if (dev->srCache[i].object &&
+				    !dev->srCache[i].locked &&
+				    (dev->srCache[i].lastUse < usage || !cache)) {
+					usage = dev->srCache[i].lastUse;
+					theObj = dev->srCache[i].object;
+					cache = &dev->srCache[i];
+					pushout = i;
+				}
+			}
+
+			if (!cache || cache->dirty) {
+				/* Flush and try again */
+				yaffs_FlushFilesChunkCache(theObj);
+				cache = yaffs_GrabChunkCacheWorker(dev);
+			}
+
+		}
+		return cache;
+	} else
+		return NULL;
+
+}
+
+/* Find a cached chunk */
+static yaffs_ChunkCache *yaffs_FindChunkCache(const yaffs_Object *obj,
+					      int chunkId)
+{
+	yaffs_Device *dev = obj->myDev;
+	int i;
+	if (dev->nShortOpCaches > 0) {
+		for (i = 0; i < dev->nShortOpCaches; i++) {
+			if (dev->srCache[i].object == obj &&
+			    dev->srCache[i].chunkId == chunkId) {
+				dev->cacheHits++;
+
+				return &dev->srCache[i];
+			}
+		}
+	}
+	return NULL;
+}
+
+/* Mark the chunk for the least recently used algorithym */
+static void yaffs_UseChunkCache(yaffs_Device *dev, yaffs_ChunkCache *cache,
+				int isAWrite)
+{
+
+	if (dev->nShortOpCaches > 0) {
+		if (dev->srLastUse < 0 || dev->srLastUse > 100000000) {
+			/* Reset the cache usages */
+			int i;
+			for (i = 1; i < dev->nShortOpCaches; i++)
+				dev->srCache[i].lastUse = 0;
+
+			dev->srLastUse = 0;
+		}
+
+		dev->srLastUse++;
+
+		cache->lastUse = dev->srLastUse;
+
+		if (isAWrite)
+			cache->dirty = 1;
+	}
+}
+
+/* Invalidate a single cache page.
+ * Do this when a whole page gets written,
+ * ie the short cache for this page is no longer valid.
+ */
+static void yaffs_InvalidateChunkCache(yaffs_Object *object, int chunkId)
+{
+	if (object->myDev->nShortOpCaches > 0) {
+		yaffs_ChunkCache *cache = yaffs_FindChunkCache(object, chunkId);
+
+		if (cache)
+			cache->object = NULL;
+	}
+}
+
+/* Invalidate all the cache pages associated with this object
+ * Do this whenever ther file is deleted or resized.
+ */
+static void yaffs_InvalidateWholeChunkCache(yaffs_Object *in)
+{
+	int i;
+	yaffs_Device *dev = in->myDev;
+
+	if (dev->nShortOpCaches > 0) {
+		/* Invalidate it. */
+		for (i = 0; i < dev->nShortOpCaches; i++) {
+			if (dev->srCache[i].object == in)
+				dev->srCache[i].object = NULL;
+		}
+	}
+}
+
+/*--------------------- Checkpointing --------------------*/
+
+
+static int yaffs_WriteCheckpointValidityMarker(yaffs_Device *dev, int head)
+{
+	yaffs_CheckpointValidity cp;
+
+	memset(&cp, 0, sizeof(cp));
+
+	cp.structType = sizeof(cp);
+	cp.magic = YAFFS_MAGIC;
+	cp.version = YAFFS_CHECKPOINT_VERSION;
+	cp.head = (head) ? 1 : 0;
+
+	return (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp)) ?
+		1 : 0;
+}
+
+static int yaffs_ReadCheckpointValidityMarker(yaffs_Device *dev, int head)
+{
+	yaffs_CheckpointValidity cp;
+	int ok;
+
+	ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	if (ok)
+		ok = (cp.structType == sizeof(cp)) &&
+		     (cp.magic == YAFFS_MAGIC) &&
+		     (cp.version == YAFFS_CHECKPOINT_VERSION) &&
+		     (cp.head == ((head) ? 1 : 0));
+	return ok ? 1 : 0;
+}
+
+static void yaffs_DeviceToCheckpointDevice(yaffs_CheckpointDevice *cp,
+					   yaffs_Device *dev)
+{
+	cp->nErasedBlocks = dev->nErasedBlocks;
+	cp->allocationBlock = dev->allocationBlock;
+	cp->allocationPage = dev->allocationPage;
+	cp->nFreeChunks = dev->nFreeChunks;
+
+	cp->nDeletedFiles = dev->nDeletedFiles;
+	cp->nUnlinkedFiles = dev->nUnlinkedFiles;
+	cp->nBackgroundDeletions = dev->nBackgroundDeletions;
+	cp->sequenceNumber = dev->sequenceNumber;
+	cp->oldestDirtySequence = dev->oldestDirtySequence;
+
+}
+
+static void yaffs_CheckpointDeviceToDevice(yaffs_Device *dev,
+					   yaffs_CheckpointDevice *cp)
+{
+	dev->nErasedBlocks = cp->nErasedBlocks;
+	dev->allocationBlock = cp->allocationBlock;
+	dev->allocationPage = cp->allocationPage;
+	dev->nFreeChunks = cp->nFreeChunks;
+
+	dev->nDeletedFiles = cp->nDeletedFiles;
+	dev->nUnlinkedFiles = cp->nUnlinkedFiles;
+	dev->nBackgroundDeletions = cp->nBackgroundDeletions;
+	dev->sequenceNumber = cp->sequenceNumber;
+	dev->oldestDirtySequence = cp->oldestDirtySequence;
+}
+
+
+static int yaffs_WriteCheckpointDevice(yaffs_Device *dev)
+{
+	yaffs_CheckpointDevice cp;
+	__u32 nBytes;
+	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+
+	int ok;
+
+	/* Write device runtime values*/
+	yaffs_DeviceToCheckpointDevice(&cp, dev);
+	cp.structType = sizeof(cp);
+
+	ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	/* Write block info */
+	if (ok) {
+		nBytes = nBlocks * sizeof(yaffs_BlockInfo);
+		ok = (yaffs_CheckpointWrite(dev, dev->blockInfo, nBytes) == nBytes);
+	}
+
+	/* Write chunk bits */
+	if (ok) {
+		nBytes = nBlocks * dev->chunkBitmapStride;
+		ok = (yaffs_CheckpointWrite(dev, dev->chunkBits, nBytes) == nBytes);
+	}
+	return	 ok ? 1 : 0;
+
+}
+
+static int yaffs_ReadCheckpointDevice(yaffs_Device *dev)
+{
+	yaffs_CheckpointDevice cp;
+	__u32 nBytes;
+	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+
+	int ok;
+
+	ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+	if (!ok)
+		return 0;
+
+	if (cp.structType != sizeof(cp))
+		return 0;
+
+
+	yaffs_CheckpointDeviceToDevice(dev, &cp);
+
+	nBytes = nBlocks * sizeof(yaffs_BlockInfo);
+
+	ok = (yaffs_CheckpointRead(dev, dev->blockInfo, nBytes) == nBytes);
+
+	if (!ok)
+		return 0;
+	nBytes = nBlocks * dev->chunkBitmapStride;
+
+	ok = (yaffs_CheckpointRead(dev, dev->chunkBits, nBytes) == nBytes);
+
+	return ok ? 1 : 0;
+}
+
+static void yaffs_ObjectToCheckpointObject(yaffs_CheckpointObject *cp,
+					   yaffs_Object *obj)
+{
+
+	cp->objectId = obj->objectId;
+	cp->parentId = (obj->parent) ? obj->parent->objectId : 0;
+	cp->hdrChunk = obj->hdrChunk;
+	cp->variantType = obj->variantType;
+	cp->deleted = obj->deleted;
+	cp->softDeleted = obj->softDeleted;
+	cp->unlinked = obj->unlinked;
+	cp->fake = obj->fake;
+	cp->renameAllowed = obj->renameAllowed;
+	cp->unlinkAllowed = obj->unlinkAllowed;
+	cp->serial = obj->serial;
+	cp->nDataChunks = obj->nDataChunks;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		cp->fileSizeOrEquivalentObjectId = obj->variant.fileVariant.fileSize;
+	else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
+		cp->fileSizeOrEquivalentObjectId = obj->variant.hardLinkVariant.equivalentObjectId;
+}
+
+static int yaffs_CheckpointObjectToObject(yaffs_Object *obj, yaffs_CheckpointObject *cp)
+{
+
+	yaffs_Object *parent;
+
+	if (obj->variantType != cp->variantType) {
+		T(YAFFS_TRACE_ERROR, (TSTR("Checkpoint read object %d type %d "
+			TCONT("chunk %d does not match existing object type %d")
+			TENDSTR), cp->objectId, cp->variantType, cp->hdrChunk,
+			obj->variantType));
+		return 0;
+	}
+
+	obj->objectId = cp->objectId;
+
+	if (cp->parentId)
+		parent = yaffs_FindOrCreateObjectByNumber(
+					obj->myDev,
+					cp->parentId,
+					YAFFS_OBJECT_TYPE_DIRECTORY);
+	else
+		parent = NULL;
+
+	if (parent) {
+		if (parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+			T(YAFFS_TRACE_ALWAYS, (TSTR("Checkpoint read object %d parent %d type %d"
+				TCONT(" chunk %d Parent type, %d, not directory")
+				TENDSTR),
+				cp->objectId, cp->parentId, cp->variantType,
+				cp->hdrChunk, parent->variantType));
+			return 0;
+		}
+		yaffs_AddObjectToDirectory(parent, obj);
+	}
+
+	obj->hdrChunk = cp->hdrChunk;
+	obj->variantType = cp->variantType;
+	obj->deleted = cp->deleted;
+	obj->softDeleted = cp->softDeleted;
+	obj->unlinked = cp->unlinked;
+	obj->fake = cp->fake;
+	obj->renameAllowed = cp->renameAllowed;
+	obj->unlinkAllowed = cp->unlinkAllowed;
+	obj->serial = cp->serial;
+	obj->nDataChunks = cp->nDataChunks;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		obj->variant.fileVariant.fileSize = cp->fileSizeOrEquivalentObjectId;
+	else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
+		obj->variant.hardLinkVariant.equivalentObjectId = cp->fileSizeOrEquivalentObjectId;
+
+	if (obj->hdrChunk > 0)
+		obj->lazyLoaded = 1;
+	return 1;
+}
+
+
+
+static int yaffs_CheckpointTnodeWorker(yaffs_Object *in, yaffs_Tnode *tn,
+					__u32 level, int chunkOffset)
+{
+	int i;
+	yaffs_Device *dev = in->myDev;
+	int ok = 1;
+	int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+	if (tnodeSize < sizeof(yaffs_Tnode))
+		tnodeSize = sizeof(yaffs_Tnode);
+
+
+	if (tn) {
+		if (level > 0) {
+
+			for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) {
+				if (tn->internal[i]) {
+					ok = yaffs_CheckpointTnodeWorker(in,
+							tn->internal[i],
+							level - 1,
+							(chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
+				}
+			}
+		} else if (level == 0) {
+			__u32 baseOffset = chunkOffset <<  YAFFS_TNODES_LEVEL0_BITS;
+			ok = (yaffs_CheckpointWrite(dev, &baseOffset, sizeof(baseOffset)) == sizeof(baseOffset));
+			if (ok)
+				ok = (yaffs_CheckpointWrite(dev, tn, tnodeSize) == tnodeSize);
+		}
+	}
+
+	return ok;
+
+}
+
+static int yaffs_WriteCheckpointTnodes(yaffs_Object *obj)
+{
+	__u32 endMarker = ~0;
+	int ok = 1;
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
+		ok = yaffs_CheckpointTnodeWorker(obj,
+					    obj->variant.fileVariant.top,
+					    obj->variant.fileVariant.topLevel,
+					    0);
+		if (ok)
+			ok = (yaffs_CheckpointWrite(obj->myDev, &endMarker, sizeof(endMarker)) ==
+				sizeof(endMarker));
+	}
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_ReadCheckpointTnodes(yaffs_Object *obj)
+{
+	__u32 baseChunk;
+	int ok = 1;
+	yaffs_Device *dev = obj->myDev;
+	yaffs_FileStructure *fileStructPtr = &obj->variant.fileVariant;
+	yaffs_Tnode *tn;
+	int nread = 0;
+	int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
+
+	if (tnodeSize < sizeof(yaffs_Tnode))
+		tnodeSize = sizeof(yaffs_Tnode);
+
+	ok = (yaffs_CheckpointRead(dev, &baseChunk, sizeof(baseChunk)) == sizeof(baseChunk));
+
+	while (ok && (~baseChunk)) {
+		nread++;
+		/* Read level 0 tnode */
+
+
+		tn = yaffs_GetTnodeRaw(dev);
+		if (tn)
+			ok = (yaffs_CheckpointRead(dev, tn, tnodeSize) == tnodeSize);
+		else
+			ok = 0;
+
+		if (tn && ok)
+			ok = yaffs_AddOrFindLevel0Tnode(dev,
+							fileStructPtr,
+							baseChunk,
+							tn) ? 1 : 0;
+
+		if (ok)
+			ok = (yaffs_CheckpointRead(dev, &baseChunk, sizeof(baseChunk)) == sizeof(baseChunk));
+
+	}
+
+	T(YAFFS_TRACE_CHECKPOINT, (
+		TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR),
+		nread, baseChunk, ok));
+
+	return ok ? 1 : 0;
+}
+
+
+static int yaffs_WriteCheckpointObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_CheckpointObject cp;
+	int i;
+	int ok = 1;
+	struct ylist_head *lh;
+
+
+	/* Iterate through the objects in each hash entry,
+	 * dumping them to the checkpointing stream.
+	 */
+
+	for (i = 0; ok &&  i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each(lh, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				if (!obj->deferedFree) {
+					yaffs_ObjectToCheckpointObject(&cp, obj);
+					cp.structType = sizeof(cp);
+
+					T(YAFFS_TRACE_CHECKPOINT, (
+						TSTR("Checkpoint write object %d parent %d type %d chunk %d obj addr %x" TENDSTR),
+						cp.objectId, cp.parentId, cp.variantType, cp.hdrChunk, (unsigned) obj));
+
+					ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+					if (ok && obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+						ok = yaffs_WriteCheckpointTnodes(obj);
+				}
+			}
+		}
+	}
+
+	/* Dump end of list */
+	memset(&cp, 0xFF, sizeof(yaffs_CheckpointObject));
+	cp.structType = sizeof(cp);
+
+	if (ok)
+		ok = (yaffs_CheckpointWrite(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_ReadCheckpointObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_CheckpointObject cp;
+	int ok = 1;
+	int done = 0;
+	yaffs_Object *hardList = NULL;
+
+	while (ok && !done) {
+		ok = (yaffs_CheckpointRead(dev, &cp, sizeof(cp)) == sizeof(cp));
+		if (cp.structType != sizeof(cp)) {
+			T(YAFFS_TRACE_CHECKPOINT, (TSTR("struct size %d instead of %d ok %d"TENDSTR),
+				cp.structType, sizeof(cp), ok));
+			ok = 0;
+		}
+
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("Checkpoint read object %d parent %d type %d chunk %d " TENDSTR),
+			cp.objectId, cp.parentId, cp.variantType, cp.hdrChunk));
+
+		if (ok && cp.objectId == ~0)
+			done = 1;
+		else if (ok) {
+			obj = yaffs_FindOrCreateObjectByNumber(dev, cp.objectId, cp.variantType);
+			if (obj) {
+				ok = yaffs_CheckpointObjectToObject(obj, &cp);
+				if (!ok)
+					break;
+				if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
+					ok = yaffs_ReadCheckpointTnodes(obj);
+				} else if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+					obj->hardLinks.next =
+						(struct ylist_head *) hardList;
+					hardList = obj;
+				}
+			} else
+				ok = 0;
+		}
+	}
+
+	if (ok)
+		yaffs_HardlinkFixup(dev, hardList);
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs_WriteCheckpointSum(yaffs_Device *dev)
+{
+	__u32 checkpointSum;
+	int ok;
+
+	yaffs_GetCheckpointSum(dev, &checkpointSum);
+
+	ok = (yaffs_CheckpointWrite(dev, &checkpointSum, sizeof(checkpointSum)) == sizeof(checkpointSum));
+
+	if (!ok)
+		return 0;
+
+	return 1;
+}
+
+static int yaffs_ReadCheckpointSum(yaffs_Device *dev)
+{
+	__u32 checkpointSum0;
+	__u32 checkpointSum1;
+	int ok;
+
+	yaffs_GetCheckpointSum(dev, &checkpointSum0);
+
+	ok = (yaffs_CheckpointRead(dev, &checkpointSum1, sizeof(checkpointSum1)) == sizeof(checkpointSum1));
+
+	if (!ok)
+		return 0;
+
+	if (checkpointSum0 != checkpointSum1)
+		return 0;
+
+	return 1;
+}
+
+
+static int yaffs_WriteCheckpointData(yaffs_Device *dev)
+{
+	int ok = 1;
+
+	if (dev->skipCheckpointWrite || !dev->isYaffs2) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("skipping checkpoint write" TENDSTR)));
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs_CheckpointOpen(dev, 1);
+
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint validity" TENDSTR)));
+		ok = yaffs_WriteCheckpointValidityMarker(dev, 1);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint device" TENDSTR)));
+		ok = yaffs_WriteCheckpointDevice(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint objects" TENDSTR)));
+		ok = yaffs_WriteCheckpointObjects(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("write checkpoint validity" TENDSTR)));
+		ok = yaffs_WriteCheckpointValidityMarker(dev, 0);
+	}
+
+	if (ok)
+		ok = yaffs_WriteCheckpointSum(dev);
+
+	if (!yaffs_CheckpointClose(dev))
+		ok = 0;
+
+	if (ok)
+		dev->isCheckpointed = 1;
+	else
+		dev->isCheckpointed = 0;
+
+	return dev->isCheckpointed;
+}
+
+static int yaffs_ReadCheckpointData(yaffs_Device *dev)
+{
+	int ok = 1;
+
+	if (dev->skipCheckpointRead || !dev->isYaffs2) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("skipping checkpoint read" TENDSTR)));
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs_CheckpointOpen(dev, 0); /* open for read */
+
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint validity" TENDSTR)));
+		ok = yaffs_ReadCheckpointValidityMarker(dev, 1);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint device" TENDSTR)));
+		ok = yaffs_ReadCheckpointDevice(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint objects" TENDSTR)));
+		ok = yaffs_ReadCheckpointObjects(dev);
+	}
+	if (ok) {
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint validity" TENDSTR)));
+		ok = yaffs_ReadCheckpointValidityMarker(dev, 0);
+	}
+
+	if (ok) {
+		ok = yaffs_ReadCheckpointSum(dev);
+		T(YAFFS_TRACE_CHECKPOINT, (TSTR("read checkpoint checksum %d" TENDSTR), ok));
+	}
+
+	if (!yaffs_CheckpointClose(dev))
+		ok = 0;
+
+	if (ok)
+		dev->isCheckpointed = 1;
+	else
+		dev->isCheckpointed = 0;
+
+	return ok ? 1 : 0;
+
+}
+
+static void yaffs_InvalidateCheckpoint(yaffs_Device *dev)
+{
+	if (dev->isCheckpointed ||
+			dev->blocksInCheckpoint > 0) {
+		dev->isCheckpointed = 0;
+		yaffs_CheckpointInvalidateStream(dev);
+		if (dev->superBlock && dev->markSuperBlockDirty)
+			dev->markSuperBlockDirty(dev->superBlock);
+	}
+}
+
+
+int yaffs_CheckpointSave(yaffs_Device *dev)
+{
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("save entry: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	yaffs_VerifyObjects(dev);
+	yaffs_VerifyBlocks(dev);
+	yaffs_VerifyFreeChunks(dev);
+
+	if (!dev->isCheckpointed) {
+		yaffs_InvalidateCheckpoint(dev);
+		yaffs_WriteCheckpointData(dev);
+	}
+
+	T(YAFFS_TRACE_ALWAYS, (TSTR("save exit: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	return dev->isCheckpointed;
+}
+
+int yaffs_CheckpointRestore(yaffs_Device *dev)
+{
+	int retval;
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("restore entry: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	retval = yaffs_ReadCheckpointData(dev);
+
+	if (dev->isCheckpointed) {
+		yaffs_VerifyObjects(dev);
+		yaffs_VerifyBlocks(dev);
+		yaffs_VerifyFreeChunks(dev);
+	}
+
+	T(YAFFS_TRACE_CHECKPOINT, (TSTR("restore exit: isCheckpointed %d"TENDSTR), dev->isCheckpointed));
+
+	return retval;
+}
+
+/*--------------------- File read/write ------------------------
+ * Read and write have very similar structures.
+ * In general the read/write has three parts to it
+ * An incomplete chunk to start with (if the read/write is not chunk-aligned)
+ * Some complete chunks
+ * An incomplete chunk to end off with
+ *
+ * Curve-balls: the first chunk might also be the last chunk.
+ */
+
+int yaffs_ReadDataFromFile(yaffs_Object *in, __u8 *buffer, loff_t offset,
+			int nBytes)
+{
+
+	int chunk;
+	__u32 start;
+	int nToCopy;
+	int n = nBytes;
+	int nDone = 0;
+	yaffs_ChunkCache *cache;
+
+	yaffs_Device *dev;
+
+	dev = in->myDev;
+
+	while (n > 0) {
+		/* chunk = offset / dev->nDataBytesPerChunk + 1; */
+		/* start = offset % dev->nDataBytesPerChunk; */
+		yaffs_AddrToChunk(dev, offset, &chunk, &start);
+		chunk++;
+
+		/* OK now check for the curveball where the start and end are in
+		 * the same chunk.
+		 */
+		if ((start + n) < dev->nDataBytesPerChunk)
+			nToCopy = n;
+		else
+			nToCopy = dev->nDataBytesPerChunk - start;
+
+		cache = yaffs_FindChunkCache(in, chunk);
+
+		/* If the chunk is already in the cache or it is less than a whole chunk
+		 * or we're using inband tags then use the cache (if there is caching)
+		 * else bypass the cache.
+		 */
+		if (cache || nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) {
+			if (dev->nShortOpCaches > 0) {
+
+				/* If we can't find the data in the cache, then load it up. */
+
+				if (!cache) {
+					cache = yaffs_GrabChunkCache(in->myDev);
+					cache->object = in;
+					cache->chunkId = chunk;
+					cache->dirty = 0;
+					cache->locked = 0;
+					yaffs_ReadChunkDataFromObject(in, chunk,
+								      cache->
+								      data);
+					cache->nBytes = 0;
+				}
+
+				yaffs_UseChunkCache(dev, cache, 0);
+
+				cache->locked = 1;
+
+
+				memcpy(buffer, &cache->data[start], nToCopy);
+
+				cache->locked = 0;
+			} else {
+				/* Read into the local buffer then copy..*/
+
+				__u8 *localBuffer =
+				    yaffs_GetTempBuffer(dev, __LINE__);
+				yaffs_ReadChunkDataFromObject(in, chunk,
+							      localBuffer);
+
+				memcpy(buffer, &localBuffer[start], nToCopy);
+
+
+				yaffs_ReleaseTempBuffer(dev, localBuffer,
+							__LINE__);
+			}
+
+		} else {
+
+			/* A full chunk. Read directly into the supplied buffer. */
+			yaffs_ReadChunkDataFromObject(in, chunk, buffer);
+
+		}
+
+		n -= nToCopy;
+		offset += nToCopy;
+		buffer += nToCopy;
+		nDone += nToCopy;
+
+	}
+
+	return nDone;
+}
+
+int yaffs_WriteDataToFile(yaffs_Object *in, const __u8 *buffer, loff_t offset,
+			int nBytes, int writeThrough)
+{
+
+	int chunk;
+	__u32 start;
+	int nToCopy;
+	int n = nBytes;
+	int nDone = 0;
+	int nToWriteBack;
+	int startOfWrite = offset;
+	int chunkWritten = 0;
+	__u32 nBytesRead;
+	__u32 chunkStart;
+
+	yaffs_Device *dev;
+
+	dev = in->myDev;
+
+	while (n > 0 && chunkWritten >= 0) {
+		/* chunk = offset / dev->nDataBytesPerChunk + 1; */
+		/* start = offset % dev->nDataBytesPerChunk; */
+		yaffs_AddrToChunk(dev, offset, &chunk, &start);
+
+		if (chunk * dev->nDataBytesPerChunk + start != offset ||
+				start >= dev->nDataBytesPerChunk) {
+			T(YAFFS_TRACE_ERROR, (
+			   TSTR("AddrToChunk of offset %d gives chunk %d start %d"
+			   TENDSTR),
+			   (int)offset, chunk, start));
+		}
+		chunk++;
+
+		/* OK now check for the curveball where the start and end are in
+		 * the same chunk.
+		 */
+
+		if ((start + n) < dev->nDataBytesPerChunk) {
+			nToCopy = n;
+
+			/* Now folks, to calculate how many bytes to write back....
+			 * If we're overwriting and not writing to then end of file then
+			 * we need to write back as much as was there before.
+			 */
+
+			chunkStart = ((chunk - 1) * dev->nDataBytesPerChunk);
+
+			if (chunkStart > in->variant.fileVariant.fileSize)
+				nBytesRead = 0; /* Past end of file */
+			else
+				nBytesRead = in->variant.fileVariant.fileSize - chunkStart;
+
+			if (nBytesRead > dev->nDataBytesPerChunk)
+				nBytesRead = dev->nDataBytesPerChunk;
+
+			nToWriteBack =
+			    (nBytesRead >
+			     (start + n)) ? nBytesRead : (start + n);
+
+			if (nToWriteBack < 0 || nToWriteBack > dev->nDataBytesPerChunk)
+				YBUG();
+
+		} else {
+			nToCopy = dev->nDataBytesPerChunk - start;
+			nToWriteBack = dev->nDataBytesPerChunk;
+		}
+
+		if (nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) {
+			/* An incomplete start or end chunk (or maybe both start and end chunk),
+			 * or we're using inband tags, so we want to use the cache buffers.
+			 */
+			if (dev->nShortOpCaches > 0) {
+				yaffs_ChunkCache *cache;
+				/* If we can't find the data in the cache, then load the cache */
+				cache = yaffs_FindChunkCache(in, chunk);
+
+				if (!cache
+				    && yaffs_CheckSpaceForAllocation(in->
+								     myDev)) {
+					cache = yaffs_GrabChunkCache(in->myDev);
+					cache->object = in;
+					cache->chunkId = chunk;
+					cache->dirty = 0;
+					cache->locked = 0;
+					yaffs_ReadChunkDataFromObject(in, chunk,
+								      cache->
+								      data);
+				} else if (cache &&
+					!cache->dirty &&
+					!yaffs_CheckSpaceForAllocation(in->myDev)) {
+					/* Drop the cache if it was a read cache item and
+					 * no space check has been made for it.
+					 */
+					 cache = NULL;
+				}
+
+				if (cache) {
+					yaffs_UseChunkCache(dev, cache, 1);
+					cache->locked = 1;
+
+
+					memcpy(&cache->data[start], buffer,
+					       nToCopy);
+
+
+					cache->locked = 0;
+					cache->nBytes = nToWriteBack;
+
+					if (writeThrough) {
+						chunkWritten =
+						    yaffs_WriteChunkDataToObject
+						    (cache->object,
+						     cache->chunkId,
+						     cache->data, cache->nBytes,
+						     1);
+						cache->dirty = 0;
+					}
+
+				} else {
+					chunkWritten = -1;	/* fail the write */
+				}
+			} else {
+				/* An incomplete start or end chunk (or maybe both start and end chunk)
+				 * Read into the local buffer then copy, then copy over and write back.
+				 */
+
+				__u8 *localBuffer =
+				    yaffs_GetTempBuffer(dev, __LINE__);
+
+				yaffs_ReadChunkDataFromObject(in, chunk,
+							      localBuffer);
+
+
+
+				memcpy(&localBuffer[start], buffer, nToCopy);
+
+				chunkWritten =
+				    yaffs_WriteChunkDataToObject(in, chunk,
+								 localBuffer,
+								 nToWriteBack,
+								 0);
+
+				yaffs_ReleaseTempBuffer(dev, localBuffer,
+							__LINE__);
+
+			}
+
+		} else {
+			/* A full chunk. Write directly from the supplied buffer. */
+
+
+
+			chunkWritten =
+			    yaffs_WriteChunkDataToObject(in, chunk, buffer,
+							 dev->nDataBytesPerChunk,
+							 0);
+
+			/* Since we've overwritten the cached data, we better invalidate it. */
+			yaffs_InvalidateChunkCache(in, chunk);
+		}
+
+		if (chunkWritten >= 0) {
+			n -= nToCopy;
+			offset += nToCopy;
+			buffer += nToCopy;
+			nDone += nToCopy;
+		}
+
+	}
+
+	/* Update file object */
+
+	if ((startOfWrite + nDone) > in->variant.fileVariant.fileSize)
+		in->variant.fileVariant.fileSize = (startOfWrite + nDone);
+
+	in->dirty = 1;
+
+	return nDone;
+}
+
+
+/* ---------------------- File resizing stuff ------------------ */
+
+static void yaffs_PruneResizedChunks(yaffs_Object *in, int newSize)
+{
+
+	yaffs_Device *dev = in->myDev;
+	int oldFileSize = in->variant.fileVariant.fileSize;
+
+	int lastDel = 1 + (oldFileSize - 1) / dev->nDataBytesPerChunk;
+
+	int startDel = 1 + (newSize + dev->nDataBytesPerChunk - 1) /
+	    dev->nDataBytesPerChunk;
+	int i;
+	int chunkId;
+
+	/* Delete backwards so that we don't end up with holes if
+	 * power is lost part-way through the operation.
+	 */
+	for (i = lastDel; i >= startDel; i--) {
+		/* NB this could be optimised somewhat,
+		 * eg. could retrieve the tags and write them without
+		 * using yaffs_DeleteChunk
+		 */
+
+		chunkId = yaffs_FindAndDeleteChunkInFile(in, i, NULL);
+		if (chunkId > 0) {
+			if (chunkId <
+			    (dev->internalStartBlock * dev->nChunksPerBlock)
+			    || chunkId >=
+			    ((dev->internalEndBlock +
+			      1) * dev->nChunksPerBlock)) {
+				T(YAFFS_TRACE_ALWAYS,
+				  (TSTR("Found daft chunkId %d for %d" TENDSTR),
+				   chunkId, i));
+			} else {
+				in->nDataChunks--;
+				yaffs_DeleteChunk(dev, chunkId, 1, __LINE__);
+			}
+		}
+	}
+
+}
+
+int yaffs_ResizeFile(yaffs_Object *in, loff_t newSize)
+{
+
+	int oldFileSize = in->variant.fileVariant.fileSize;
+	__u32 newSizeOfPartialChunk;
+	int newFullChunks;
+
+	yaffs_Device *dev = in->myDev;
+
+	yaffs_AddrToChunk(dev, newSize, &newFullChunks, &newSizeOfPartialChunk);
+
+	yaffs_FlushFilesChunkCache(in);
+	yaffs_InvalidateWholeChunkCache(in);
+
+	yaffs_CheckGarbageCollection(dev);
+
+	if (in->variantType != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+
+	if (newSize == oldFileSize)
+		return YAFFS_OK;
+
+	if (newSize < oldFileSize) {
+
+		yaffs_PruneResizedChunks(in, newSize);
+
+		if (newSizeOfPartialChunk != 0) {
+			int lastChunk = 1 + newFullChunks;
+
+			__u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
+
+			/* Got to read and rewrite the last chunk with its new size and zero pad */
+			yaffs_ReadChunkDataFromObject(in, lastChunk,
+						      localBuffer);
+
+			memset(localBuffer + newSizeOfPartialChunk, 0,
+			       dev->nDataBytesPerChunk - newSizeOfPartialChunk);
+
+			yaffs_WriteChunkDataToObject(in, lastChunk, localBuffer,
+						     newSizeOfPartialChunk, 1);
+
+			yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
+		}
+
+		in->variant.fileVariant.fileSize = newSize;
+
+		yaffs_PruneFileStructure(dev, &in->variant.fileVariant);
+	} else {
+		/* newsSize > oldFileSize */
+		in->variant.fileVariant.fileSize = newSize;
+	}
+
+
+	/* Write a new object header to reflect the resize.
+	 * show we've shrunk the file, if need be
+	 * Do this only if the file is not in the deleted directories
+	 * and is not shadowed.
+	 */
+	if (in->parent &&
+	    !in->isShadowed &&
+	    in->parent->objectId != YAFFS_OBJECTID_UNLINKED &&
+	    in->parent->objectId != YAFFS_OBJECTID_DELETED)
+		yaffs_UpdateObjectHeader(in, NULL, 0,
+					 (newSize < oldFileSize) ? 1 : 0, 0);
+
+	return YAFFS_OK;
+}
+
+loff_t yaffs_GetFileSize(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		return obj->variant.fileVariant.fileSize;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		return yaffs_strlen(obj->variant.symLinkVariant.alias);
+	default:
+		return 0;
+	}
+}
+
+
+
+int yaffs_FlushFile(yaffs_Object *in, int updateTime)
+{
+	int retVal;
+	if (in->dirty) {
+		yaffs_FlushFilesChunkCache(in);
+		if (updateTime) {
+#ifdef CONFIG_YAFFS_WINCE
+			yfsd_WinFileTimeNow(in->win_mtime);
+#else
+
+			in->yst_mtime = Y_CURRENT_TIME;
+
+#endif
+		}
+
+		retVal = (yaffs_UpdateObjectHeader(in, NULL, 0, 0, 0) >=
+			0) ? YAFFS_OK : YAFFS_FAIL;
+	} else {
+		retVal = YAFFS_OK;
+	}
+
+	return retVal;
+
+}
+
+static int yaffs_DoGenericObjectDeletion(yaffs_Object *in)
+{
+
+	/* First off, invalidate the file's data in the cache, without flushing. */
+	yaffs_InvalidateWholeChunkCache(in);
+
+	if (in->myDev->isYaffs2 && (in->parent != in->myDev->deletedDir)) {
+		/* Move to the unlinked directory so we have a record that it was deleted. */
+		yaffs_ChangeObjectName(in, in->myDev->deletedDir, _Y("deleted"), 0, 0);
+
+	}
+
+	yaffs_RemoveObjectFromDirectory(in);
+	yaffs_DeleteChunk(in->myDev, in->hdrChunk, 1, __LINE__);
+	in->hdrChunk = 0;
+
+	yaffs_FreeObject(in);
+	return YAFFS_OK;
+
+}
+
+/* yaffs_DeleteFile deletes the whole file data
+ * and the inode associated with the file.
+ * It does not delete the links associated with the file.
+ */
+static int yaffs_UnlinkFileIfNeeded(yaffs_Object *in)
+{
+
+	int retVal;
+	int immediateDeletion = 0;
+
+#ifdef __KERNEL__
+	if (!in->myInode)
+		immediateDeletion = 1;
+#else
+	if (in->inUse <= 0)
+		immediateDeletion = 1;
+#endif
+
+	if (immediateDeletion) {
+		retVal =
+		    yaffs_ChangeObjectName(in, in->myDev->deletedDir,
+					   _Y("deleted"), 0, 0);
+		T(YAFFS_TRACE_TRACING,
+		  (TSTR("yaffs: immediate deletion of file %d" TENDSTR),
+		   in->objectId));
+		in->deleted = 1;
+		in->myDev->nDeletedFiles++;
+		if (1 || in->myDev->isYaffs2)
+			yaffs_ResizeFile(in, 0);
+		yaffs_SoftDeleteFile(in);
+	} else {
+		retVal =
+		    yaffs_ChangeObjectName(in, in->myDev->unlinkedDir,
+					   _Y("unlinked"), 0, 0);
+	}
+
+
+	return retVal;
+}
+
+int yaffs_DeleteFile(yaffs_Object *in)
+{
+	int retVal = YAFFS_OK;
+	int deleted = in->deleted;
+
+	yaffs_ResizeFile(in, 0);
+
+	if (in->nDataChunks > 0) {
+		/* Use soft deletion if there is data in the file.
+		 * That won't be the case if it has been resized to zero.
+		 */
+		if (!in->unlinked)
+			retVal = yaffs_UnlinkFileIfNeeded(in);
+
+		if (retVal == YAFFS_OK && in->unlinked && !in->deleted) {
+			in->deleted = 1;
+			deleted = 1;
+			in->myDev->nDeletedFiles++;
+			yaffs_SoftDeleteFile(in);
+		}
+		return deleted ? YAFFS_OK : YAFFS_FAIL;
+	} else {
+		/* The file has no data chunks so we toss it immediately */
+		yaffs_FreeTnode(in->myDev, in->variant.fileVariant.top);
+		in->variant.fileVariant.top = NULL;
+		yaffs_DoGenericObjectDeletion(in);
+
+		return YAFFS_OK;
+	}
+}
+
+static int yaffs_IsNonEmptyDirectory(yaffs_Object *obj)
+{
+	return (obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) &&
+		!(ylist_empty(&obj->variant.directoryVariant.children));
+}
+
+static int yaffs_DeleteDirectory(yaffs_Object *obj)
+{
+	/* First check that the directory is empty. */
+	if (yaffs_IsNonEmptyDirectory(obj))
+		return YAFFS_FAIL;
+
+	return yaffs_DoGenericObjectDeletion(obj);
+}
+
+static int yaffs_DeleteSymLink(yaffs_Object *in)
+{
+	YFREE(in->variant.symLinkVariant.alias);
+
+	return yaffs_DoGenericObjectDeletion(in);
+}
+
+static int yaffs_DeleteHardLink(yaffs_Object *in)
+{
+	/* remove this hardlink from the list assocaited with the equivalent
+	 * object
+	 */
+	ylist_del_init(&in->hardLinks);
+	return yaffs_DoGenericObjectDeletion(in);
+}
+
+int yaffs_DeleteObject(yaffs_Object *obj)
+{
+int retVal = -1;
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		retVal = yaffs_DeleteFile(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		return yaffs_DeleteDirectory(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		retVal = yaffs_DeleteSymLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		retVal = yaffs_DeleteHardLink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		retVal = yaffs_DoGenericObjectDeletion(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		retVal = 0;
+		break;		/* should not happen. */
+	}
+
+	return retVal;
+}
+
+static int yaffs_UnlinkWorker(yaffs_Object *obj)
+{
+
+	int immediateDeletion = 0;
+
+#ifdef __KERNEL__
+	if (!obj->myInode)
+		immediateDeletion = 1;
+#else
+	if (obj->inUse <= 0)
+		immediateDeletion = 1;
+#endif
+
+	if(obj)
+		yaffs_UpdateParent(obj->parent);
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+		return yaffs_DeleteHardLink(obj);
+	} else if (!ylist_empty(&obj->hardLinks)) {
+		/* Curve ball: We're unlinking an object that has a hardlink.
+		 *
+		 * This problem arises because we are not strictly following
+		 * The Linux link/inode model.
+		 *
+		 * We can't really delete the object.
+		 * Instead, we do the following:
+		 * - Select a hardlink.
+		 * - Unhook it from the hard links
+		 * - Unhook it from its parent directory (so that the rename can work)
+		 * - Rename the object to the hardlink's name.
+		 * - Delete the hardlink
+		 */
+
+		yaffs_Object *hl;
+		int retVal;
+		YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
+
+		hl = ylist_entry(obj->hardLinks.next, yaffs_Object, hardLinks);
+
+		ylist_del_init(&hl->hardLinks);
+		ylist_del_init(&hl->siblings);
+
+		yaffs_GetObjectName(hl, name, YAFFS_MAX_NAME_LENGTH + 1);
+
+		retVal = yaffs_ChangeObjectName(obj, hl->parent, name, 0, 0);
+
+		if (retVal == YAFFS_OK)
+			retVal = yaffs_DoGenericObjectDeletion(hl);
+
+		return retVal;
+
+	} else if (immediateDeletion) {
+		switch (obj->variantType) {
+		case YAFFS_OBJECT_TYPE_FILE:
+			return yaffs_DeleteFile(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_DIRECTORY:
+			return yaffs_DeleteDirectory(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_SYMLINK:
+			return yaffs_DeleteSymLink(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_SPECIAL:
+			return yaffs_DoGenericObjectDeletion(obj);
+			break;
+		case YAFFS_OBJECT_TYPE_HARDLINK:
+		case YAFFS_OBJECT_TYPE_UNKNOWN:
+		default:
+			return YAFFS_FAIL;
+		}
+	} else if(yaffs_IsNonEmptyDirectory(obj))
+		return YAFFS_FAIL;
+	else
+		return yaffs_ChangeObjectName(obj, obj->myDev->unlinkedDir,
+					   _Y("unlinked"), 0, 0);
+}
+
+
+static int yaffs_UnlinkObject(yaffs_Object *obj)
+{
+
+	if (obj && obj->unlinkAllowed)
+		return yaffs_UnlinkWorker(obj);
+
+	return YAFFS_FAIL;
+
+}
+int yaffs_Unlink(yaffs_Object *dir, const YCHAR *name)
+{
+	yaffs_Object *obj;
+
+	obj = yaffs_FindObjectByName(dir, name);
+	return yaffs_UnlinkObject(obj);
+}
+
+/*----------------------- Initialisation Scanning ---------------------- */
+
+static void yaffs_HandleShadowedObject(yaffs_Device *dev, int objId,
+				int backwardScanning)
+{
+	yaffs_Object *obj;
+
+	if (!backwardScanning) {
+		/* Handle YAFFS1 forward scanning case
+		 * For YAFFS1 we always do the deletion
+		 */
+
+	} else {
+		/* Handle YAFFS2 case (backward scanning)
+		 * If the shadowed object exists then ignore.
+		 */
+		obj = yaffs_FindObjectByNumber(dev, objId);
+		if(obj)
+			return;
+	}
+
+	/* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc.
+	 * We put it in unlinked dir to be cleaned up after the scanning
+	 */
+	obj =
+	    yaffs_FindOrCreateObjectByNumber(dev, objId,
+					     YAFFS_OBJECT_TYPE_FILE);
+	if (!obj)
+		return;
+	obj->isShadowed = 1;
+	yaffs_AddObjectToDirectory(dev->unlinkedDir, obj);
+	obj->variant.fileVariant.shrinkSize = 0;
+	obj->valid = 1;		/* So that we don't read any other info for this file */
+
+}
+
+typedef struct {
+	int seq;
+	int block;
+} yaffs_BlockIndex;
+
+
+static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList)
+{
+	yaffs_Object *hl;
+	yaffs_Object *in;
+
+	while (hardList) {
+		hl = hardList;
+		hardList = (yaffs_Object *) (hardList->hardLinks.next);
+
+		in = yaffs_FindObjectByNumber(dev,
+					      hl->variant.hardLinkVariant.
+					      equivalentObjectId);
+
+		if (in) {
+			/* Add the hardlink pointers */
+			hl->variant.hardLinkVariant.equivalentObject = in;
+			ylist_add(&hl->hardLinks, &in->hardLinks);
+		} else {
+			/* Todo Need to report/handle this better.
+			 * Got a problem... hardlink to a non-existant object
+			 */
+			hl->variant.hardLinkVariant.equivalentObject = NULL;
+			YINIT_LIST_HEAD(&hl->hardLinks);
+
+		}
+	}
+}
+
+
+
+
+
+static int ybicmp(const void *a, const void *b)
+{
+	register int aseq = ((yaffs_BlockIndex *)a)->seq;
+	register int bseq = ((yaffs_BlockIndex *)b)->seq;
+	register int ablock = ((yaffs_BlockIndex *)a)->block;
+	register int bblock = ((yaffs_BlockIndex *)b)->block;
+	if (aseq == bseq)
+		return ablock - bblock;
+	else
+		return aseq - bseq;
+}
+
+
+struct yaffs_ShadowFixerStruct {
+	int objectId;
+	int shadowedId;
+	struct yaffs_ShadowFixerStruct *next;
+};
+
+
+static void yaffs_StripDeletedObjects(yaffs_Device *dev)
+{
+	/*
+	*  Sort out state of unlinked and deleted objects after scanning.
+	*/
+	struct ylist_head *i;
+	struct ylist_head *n;
+	yaffs_Object *l;
+
+	/* Soft delete all the unlinked files */
+	ylist_for_each_safe(i, n,
+		&dev->unlinkedDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			yaffs_DeleteObject(l);
+		}
+	}
+
+	ylist_for_each_safe(i, n,
+		&dev->deletedDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			yaffs_DeleteObject(l);
+		}
+	}
+
+}
+
+/*
+ * This code iterates through all the objects making sure that they are rooted.
+ * Any unrooted objects are re-rooted in lost+found.
+ * An object needs to be in one of:
+ * - Directly under deleted, unlinked
+ * - Directly or indirectly under root.
+ *
+ * Note:
+ *  This code assumes that we don't ever change the current relationships between
+ *  directories:
+ *   rootDir->parent == unlinkedDir->parent == deletedDir->parent == NULL
+ *   lostNfound->parent == rootDir
+ *
+ * This fixes the problem where directories might have inadvertently been deleted
+ * leaving the object "hanging" without being rooted in the directory tree.
+ */
+
+static int yaffs_HasNULLParent(yaffs_Device *dev, yaffs_Object *obj)
+{
+	return (obj == dev->deletedDir ||
+		obj == dev->unlinkedDir||
+		obj == dev->rootDir);
+}
+
+static void yaffs_FixHangingObjects(yaffs_Device *dev)
+{
+	yaffs_Object *obj;
+	yaffs_Object *parent;
+	int i;
+	struct ylist_head *lh;
+	struct ylist_head *n;
+	int depthLimit;
+	int hanging;
+
+
+	/* Iterate through the objects in each hash entry,
+	 * looking at each object.
+	 * Make sure it is rooted.
+	 */
+
+	for (i = 0; i <  YAFFS_NOBJECT_BUCKETS; i++) {
+		ylist_for_each_safe(lh, n, &dev->objectBucket[i].list) {
+			if (lh) {
+				obj = ylist_entry(lh, yaffs_Object, hashLink);
+				parent= obj->parent;
+
+				if(yaffs_HasNULLParent(dev,obj)){
+					/* These directories are not hanging */
+					hanging = 0;
+				}
+				else if(!parent || parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+					hanging = 1;
+				else if(yaffs_HasNULLParent(dev,parent))
+					hanging = 0;
+				else {
+					/*
+					 * Need to follow the parent chain to see if it is hanging.
+					 */
+					hanging = 0;
+					depthLimit=100;
+
+					while(parent != dev->rootDir &&
+						parent->parent &&
+						parent->parent->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
+						depthLimit > 0){
+						parent = parent->parent;
+						depthLimit--;
+					}
+					if(parent != dev->rootDir)
+						hanging = 1;
+				}
+				if(hanging){
+					T(YAFFS_TRACE_SCAN,
+					(TSTR("Hanging object %d moved to lost and found" TENDSTR),
+					obj->objectId));
+					yaffs_AddObjectToDirectory(dev->lostNFoundDir,obj);
+				}
+			}
+		}
+	}
+}
+
+
+/*
+ * Delete directory contents for cleaning up lost and found.
+ */
+static void yaffs_DeleteDirectoryContents(yaffs_Object *dir)
+{
+	yaffs_Object *obj;
+	struct ylist_head *lh;
+	struct ylist_head *n;
+
+	if(dir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
+		YBUG();
+
+	ylist_for_each_safe(lh, n, &dir->variant.directoryVariant.children) {
+		if (lh) {
+			obj = ylist_entry(lh, yaffs_Object, siblings);
+			if(obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
+				yaffs_DeleteDirectoryContents(obj);
+
+			T(YAFFS_TRACE_SCAN,
+				(TSTR("Deleting lost_found object %d" TENDSTR),
+				obj->objectId));
+
+			/* Need to use UnlinkObject since Delete would not handle
+			 * hardlinked objects correctly.
+			 */
+			yaffs_UnlinkObject(obj);
+		}
+	}
+
+}
+
+static void yaffs_EmptyLostAndFound(yaffs_Device *dev)
+{
+	yaffs_DeleteDirectoryContents(dev->lostNFoundDir);
+}
+
+static int yaffs_Scan(yaffs_Device *dev)
+{
+	yaffs_ExtendedTags tags;
+	int blk;
+	int blockIterator;
+	int startIterator;
+	int endIterator;
+	int result;
+
+	int chunk;
+	int c;
+	int deleted;
+	yaffs_BlockState state;
+	yaffs_Object *hardList = NULL;
+	yaffs_BlockInfo *bi;
+	__u32 sequenceNumber;
+	yaffs_ObjectHeader *oh;
+	yaffs_Object *in;
+	yaffs_Object *parent;
+
+	int alloc_failed = 0;
+
+	struct yaffs_ShadowFixerStruct *shadowFixerList = NULL;
+
+
+	__u8 *chunkData;
+
+
+
+	T(YAFFS_TRACE_SCAN,
+	  (TSTR("yaffs_Scan starts  intstartblk %d intendblk %d..." TENDSTR),
+	   dev->internalStartBlock, dev->internalEndBlock));
+
+	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	/* Scan all the blocks to determine their state */
+	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
+		bi = yaffs_GetBlockInfo(dev, blk);
+		yaffs_ClearChunkBits(dev, blk);
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+
+		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
+
+		bi->blockState = state;
+		bi->sequenceNumber = sequenceNumber;
+
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->blockState = state = YAFFS_BLOCK_STATE_DEAD;
+
+		T(YAFFS_TRACE_SCAN_DEBUG,
+		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
+		   state, sequenceNumber));
+
+		if (state == YAFFS_BLOCK_STATE_DEAD) {
+			T(YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("block %d is bad" TENDSTR), blk));
+		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
+			T(YAFFS_TRACE_SCAN_DEBUG,
+			  (TSTR("Block empty " TENDSTR)));
+			dev->nErasedBlocks++;
+			dev->nFreeChunks += dev->nChunksPerBlock;
+		}
+	}
+
+	startIterator = dev->internalStartBlock;
+	endIterator = dev->internalEndBlock;
+
+	/* For each block.... */
+	for (blockIterator = startIterator; !alloc_failed && blockIterator <= endIterator;
+	     blockIterator++) {
+
+		YYIELD();
+
+		YYIELD();
+
+		blk = blockIterator;
+
+		bi = yaffs_GetBlockInfo(dev, blk);
+		state = bi->blockState;
+
+		deleted = 0;
+
+		/* For each chunk in each block that needs scanning....*/
+		for (c = 0; !alloc_failed && c < dev->nChunksPerBlock &&
+		     state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) {
+			/* Read the tags and decide what to do */
+			chunk = blk * dev->nChunksPerBlock + c;
+
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+							&tags);
+
+			/* Let's have a good look at this chunk... */
+
+			if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED || tags.chunkDeleted) {
+				/* YAFFS1 only...
+				 * A deleted chunk
+				 */
+				deleted++;
+				dev->nFreeChunks++;
+				/*T((" %d %d deleted\n",blk,c)); */
+			} else if (!tags.chunkUsed) {
+				/* An unassigned chunk in the block
+				 * This means that either the block is empty or
+				 * this is the one being allocated from
+				 */
+
+				if (c == 0) {
+					/* We're looking at the first chunk in the block so the block is unused */
+					state = YAFFS_BLOCK_STATE_EMPTY;
+					dev->nErasedBlocks++;
+				} else {
+					/* this is the block being allocated from */
+					T(YAFFS_TRACE_SCAN,
+					  (TSTR
+					   (" Allocating from %d %d" TENDSTR),
+					   blk, c));
+					state = YAFFS_BLOCK_STATE_ALLOCATING;
+					dev->allocationBlock = blk;
+					dev->allocationPage = c;
+					dev->allocationBlockFinder = blk;
+					/* Set it to here to encourage the allocator to go forth from here. */
+
+				}
+
+				dev->nFreeChunks += (dev->nChunksPerBlock - c);
+			} else if (tags.chunkId > 0) {
+				/* chunkId > 0 so it is a data chunk... */
+				unsigned int endpos;
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      YAFFS_OBJECT_TYPE_FILE);
+				/* PutChunkIntoFile checks for a clash (two data chunks with
+				 * the same chunkId).
+				 */
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in) {
+					if (!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk, 1))
+						alloc_failed = 1;
+				}
+
+				endpos =
+				    (tags.chunkId - 1) * dev->nDataBytesPerChunk +
+				    tags.byteCount;
+				if (in &&
+				    in->variantType == YAFFS_OBJECT_TYPE_FILE
+				    && in->variant.fileVariant.scannedFileSize <
+				    endpos) {
+					in->variant.fileVariant.
+					    scannedFileSize = endpos;
+					if (!dev->useHeaderFileSize) {
+						in->variant.fileVariant.
+						    fileSize =
+						    in->variant.fileVariant.
+						    scannedFileSize;
+					}
+
+				}
+				/* T((" %d %d data %d %d\n",blk,c,tags.objectId,tags.chunkId));   */
+			} else {
+				/* chunkId == 0, so it is an ObjectHeader.
+				 * Thus, we read in the object header and make the object
+				 */
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
+								chunkData,
+								NULL);
+
+				oh = (yaffs_ObjectHeader *) chunkData;
+
+				in = yaffs_FindObjectByNumber(dev,
+							      tags.objectId);
+				if (in && in->variantType != oh->type) {
+					/* This should not happen, but somehow
+					 * Wev'e ended up with an objectId that has been reused but not yet
+					 * deleted, and worse still it has changed type. Delete the old object.
+					 */
+
+					yaffs_DeleteObject(in);
+
+					in = 0;
+				}
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      oh->type);
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in && oh->shadowsObject > 0) {
+
+					struct yaffs_ShadowFixerStruct *fixer;
+					fixer = YMALLOC(sizeof(struct yaffs_ShadowFixerStruct));
+					if (fixer) {
+						fixer->next = shadowFixerList;
+						shadowFixerList = fixer;
+						fixer->objectId = tags.objectId;
+						fixer->shadowedId = oh->shadowsObject;
+					}
+
+				}
+
+				if (in && in->valid) {
+					/* We have already filled this one. We have a duplicate and need to resolve it. */
+
+					unsigned existingSerial = in->serial;
+					unsigned newSerial = tags.serialNumber;
+
+					if (((existingSerial + 1) & 3) == newSerial) {
+						/* Use new one - destroy the exisiting one */
+						yaffs_DeleteChunk(dev,
+								  in->hdrChunk,
+								  1, __LINE__);
+						in->valid = 0;
+					} else {
+						/* Use existing - destroy this one. */
+						yaffs_DeleteChunk(dev, chunk, 1,
+								  __LINE__);
+					}
+				}
+
+				if (in && !in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) {
+					/* We only load some info, don't fiddle with directory structure */
+					in->valid = 1;
+					in->variantType = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+					in->win_atime[0] = oh->win_atime[0];
+					in->win_ctime[0] = oh->win_ctime[0];
+					in->win_mtime[0] = oh->win_mtime[0];
+					in->win_atime[1] = oh->win_atime[1];
+					in->win_ctime[1] = oh->win_ctime[1];
+					in->win_mtime[1] = oh->win_mtime[1];
+#else
+					in->yst_uid = oh->yst_uid;
+					in->yst_gid = oh->yst_gid;
+					in->yst_atime = oh->yst_atime;
+					in->yst_mtime = oh->yst_mtime;
+					in->yst_ctime = oh->yst_ctime;
+					in->yst_rdev = oh->yst_rdev;
+#endif
+					in->hdrChunk = chunk;
+					in->serial = tags.serialNumber;
+
+				} else if (in && !in->valid) {
+					/* we need to load this info */
+
+					in->valid = 1;
+					in->variantType = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+					in->win_atime[0] = oh->win_atime[0];
+					in->win_ctime[0] = oh->win_ctime[0];
+					in->win_mtime[0] = oh->win_mtime[0];
+					in->win_atime[1] = oh->win_atime[1];
+					in->win_ctime[1] = oh->win_ctime[1];
+					in->win_mtime[1] = oh->win_mtime[1];
+#else
+					in->yst_uid = oh->yst_uid;
+					in->yst_gid = oh->yst_gid;
+					in->yst_atime = oh->yst_atime;
+					in->yst_mtime = oh->yst_mtime;
+					in->yst_ctime = oh->yst_ctime;
+					in->yst_rdev = oh->yst_rdev;
+#endif
+					in->hdrChunk = chunk;
+					in->serial = tags.serialNumber;
+
+					yaffs_SetObjectName(in, oh->name);
+					in->dirty = 0;
+
+					/* directory stuff...
+					 * hook up to parent
+					 */
+
+					parent =
+					    yaffs_FindOrCreateObjectByNumber
+					    (dev, oh->parentObjectId,
+					     YAFFS_OBJECT_TYPE_DIRECTORY);
+					if (!parent)
+						alloc_failed = 1;
+					if (parent && parent->variantType ==
+					    YAFFS_OBJECT_TYPE_UNKNOWN) {
+						/* Set up as a directory */
+						parent->variantType =
+							YAFFS_OBJECT_TYPE_DIRECTORY;
+						YINIT_LIST_HEAD(&parent->variant.
+								directoryVariant.
+								children);
+					} else if (!parent || parent->variantType !=
+						   YAFFS_OBJECT_TYPE_DIRECTORY) {
+						/* Hoosterman, another problem....
+						 * We're trying to use a non-directory as a directory
+						 */
+
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR
+						   ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+						    TENDSTR)));
+						parent = dev->lostNFoundDir;
+					}
+
+					yaffs_AddObjectToDirectory(parent, in);
+
+					if (0 && (parent == dev->deletedDir ||
+						  parent == dev->unlinkedDir)) {
+						in->deleted = 1;	/* If it is unlinked at start up then it wants deleting */
+						dev->nDeletedFiles++;
+					}
+					/* Note re hardlinks.
+					 * Since we might scan a hardlink before its equivalent object is scanned
+					 * we put them all in a list.
+					 * After scanning is complete, we should have all the objects, so we run through this
+					 * list and fix up all the chains.
+					 */
+
+					switch (in->variantType) {
+					case YAFFS_OBJECT_TYPE_UNKNOWN:
+						/* Todo got a problem */
+						break;
+					case YAFFS_OBJECT_TYPE_FILE:
+						if (dev->useHeaderFileSize)
+
+							in->variant.fileVariant.
+							    fileSize =
+							    oh->fileSize;
+
+						break;
+					case YAFFS_OBJECT_TYPE_HARDLINK:
+						in->variant.hardLinkVariant.
+							equivalentObjectId =
+							oh->equivalentObjectId;
+						in->hardLinks.next =
+							(struct ylist_head *)
+							hardList;
+						hardList = in;
+						break;
+					case YAFFS_OBJECT_TYPE_DIRECTORY:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SPECIAL:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SYMLINK:
+						in->variant.symLinkVariant.alias =
+						    yaffs_CloneString(oh->alias);
+						if (!in->variant.symLinkVariant.alias)
+							alloc_failed = 1;
+						break;
+					}
+
+/*
+					if (parent == dev->deletedDir) {
+						yaffs_DestroyObject(in);
+						bi->hasShrinkHeader = 1;
+					}
+*/
+				}
+			}
+		}
+
+		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			/* If we got this far while scanning, then the block is fully allocated.*/
+			state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+		bi->blockState = state;
+
+		/* Now let's see if it was dirty */
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
+			yaffs_BlockBecameDirty(dev, blk);
+		}
+
+	}
+
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We should now have scanned all the objects, now it's time to add these
+	 * hardlinks.
+	 */
+
+	yaffs_HardlinkFixup(dev, hardList);
+
+	/* Fix up any shadowed objects */
+	{
+		struct yaffs_ShadowFixerStruct *fixer;
+		yaffs_Object *obj;
+
+		while (shadowFixerList) {
+			fixer = shadowFixerList;
+			shadowFixerList = fixer->next;
+			/* Complete the rename transaction by deleting the shadowed object
+			 * then setting the object header to unshadowed.
+			 */
+			obj = yaffs_FindObjectByNumber(dev, fixer->shadowedId);
+			if (obj)
+				yaffs_DeleteObject(obj);
+
+			obj = yaffs_FindObjectByNumber(dev, fixer->objectId);
+
+			if (obj)
+				yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
+
+			YFREE(fixer);
+		}
+	}
+
+	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+
+	if (alloc_failed)
+		return YAFFS_FAIL;
+
+	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_Scan ends" TENDSTR)));
+
+
+	return YAFFS_OK;
+}
+
+static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in)
+{
+	__u8 *chunkData;
+	yaffs_ObjectHeader *oh;
+	yaffs_Device *dev;
+	yaffs_ExtendedTags tags;
+	int result;
+	int alloc_failed = 0;
+
+	if (!in)
+		return;
+
+	dev = in->myDev;
+
+#if 0
+	T(YAFFS_TRACE_SCAN, (TSTR("details for object %d %s loaded" TENDSTR),
+		in->objectId,
+		in->lazyLoaded ? "not yet" : "already"));
+#endif
+
+	if (in->lazyLoaded && in->hdrChunk > 0) {
+		in->lazyLoaded = 0;
+		chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+		result = yaffs_ReadChunkWithTagsFromNAND(dev, in->hdrChunk, chunkData, &tags);
+		oh = (yaffs_ObjectHeader *) chunkData;
+
+		in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+		in->win_atime[0] = oh->win_atime[0];
+		in->win_ctime[0] = oh->win_ctime[0];
+		in->win_mtime[0] = oh->win_mtime[0];
+		in->win_atime[1] = oh->win_atime[1];
+		in->win_ctime[1] = oh->win_ctime[1];
+		in->win_mtime[1] = oh->win_mtime[1];
+#else
+		in->yst_uid = oh->yst_uid;
+		in->yst_gid = oh->yst_gid;
+		in->yst_atime = oh->yst_atime;
+		in->yst_mtime = oh->yst_mtime;
+		in->yst_ctime = oh->yst_ctime;
+		in->yst_rdev = oh->yst_rdev;
+
+#endif
+		yaffs_SetObjectName(in, oh->name);
+
+		if (in->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
+			in->variant.symLinkVariant.alias =
+						    yaffs_CloneString(oh->alias);
+			if (!in->variant.symLinkVariant.alias)
+				alloc_failed = 1; /* Not returned to caller */
+		}
+
+		yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+	}
+}
+
+static int yaffs_ScanBackwards(yaffs_Device *dev)
+{
+	yaffs_ExtendedTags tags;
+	int blk;
+	int blockIterator;
+	int startIterator;
+	int endIterator;
+	int nBlocksToScan = 0;
+
+	int chunk;
+	int result;
+	int c;
+	int deleted;
+	yaffs_BlockState state;
+	yaffs_Object *hardList = NULL;
+	yaffs_BlockInfo *bi;
+	__u32 sequenceNumber;
+	yaffs_ObjectHeader *oh;
+	yaffs_Object *in;
+	yaffs_Object *parent;
+	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
+	int itsUnlinked;
+	__u8 *chunkData;
+
+	int fileSize;
+	int isShrink;
+	int foundChunksInBlock;
+	int equivalentObjectId;
+	int alloc_failed = 0;
+
+
+	yaffs_BlockIndex *blockIndex = NULL;
+	int altBlockIndex = 0;
+
+	if (!dev->isYaffs2) {
+		T(YAFFS_TRACE_SCAN,
+		  (TSTR("yaffs_ScanBackwards is only for YAFFS2!" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	T(YAFFS_TRACE_SCAN,
+	  (TSTR
+	   ("yaffs_ScanBackwards starts  intstartblk %d intendblk %d..."
+	    TENDSTR), dev->internalStartBlock, dev->internalEndBlock));
+
+
+	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex));
+
+	if (!blockIndex) {
+		blockIndex = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockIndex));
+		altBlockIndex = 1;
+	}
+
+	if (!blockIndex) {
+		T(YAFFS_TRACE_SCAN,
+		  (TSTR("yaffs_Scan() could not allocate block index!" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	dev->blocksInCheckpoint = 0;
+
+	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
+
+	/* Scan all the blocks to determine their state */
+	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
+		bi = yaffs_GetBlockInfo(dev, blk);
+		yaffs_ClearChunkBits(dev, blk);
+		bi->pagesInUse = 0;
+		bi->softDeletions = 0;
+
+		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
+
+		bi->blockState = state;
+		bi->sequenceNumber = sequenceNumber;
+
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA)
+			bi->blockState = state = YAFFS_BLOCK_STATE_CHECKPOINT;
+		if (bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->blockState = state = YAFFS_BLOCK_STATE_DEAD;
+
+		T(YAFFS_TRACE_SCAN_DEBUG,
+		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
+		   state, sequenceNumber));
+
+
+		if (state == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			dev->blocksInCheckpoint++;
+
+		} else if (state == YAFFS_BLOCK_STATE_DEAD) {
+			T(YAFFS_TRACE_BAD_BLOCKS,
+			  (TSTR("block %d is bad" TENDSTR), blk));
+		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
+			T(YAFFS_TRACE_SCAN_DEBUG,
+			  (TSTR("Block empty " TENDSTR)));
+			dev->nErasedBlocks++;
+			dev->nFreeChunks += dev->nChunksPerBlock;
+		} else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+
+			/* Determine the highest sequence number */
+			if (sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
+			    sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
+
+				blockIndex[nBlocksToScan].seq = sequenceNumber;
+				blockIndex[nBlocksToScan].block = blk;
+
+				nBlocksToScan++;
+
+				if (sequenceNumber >= dev->sequenceNumber)
+					dev->sequenceNumber = sequenceNumber;
+			} else {
+				/* TODO: Nasty sequence number! */
+				T(YAFFS_TRACE_SCAN,
+				  (TSTR
+				   ("Block scanning block %d has bad sequence number %d"
+				    TENDSTR), blk, sequenceNumber));
+
+			}
+		}
+	}
+
+	T(YAFFS_TRACE_SCAN,
+	(TSTR("%d blocks to be sorted..." TENDSTR), nBlocksToScan));
+
+
+
+	YYIELD();
+
+	/* Sort the blocks */
+#ifndef CONFIG_YAFFS_USE_OWN_SORT
+	{
+		/* Use qsort now. */
+		yaffs_qsort(blockIndex, nBlocksToScan, sizeof(yaffs_BlockIndex), ybicmp);
+	}
+#else
+	{
+		/* Dungy old bubble sort... */
+
+		yaffs_BlockIndex temp;
+		int i;
+		int j;
+
+		for (i = 0; i < nBlocksToScan; i++)
+			for (j = i + 1; j < nBlocksToScan; j++)
+				if (blockIndex[i].seq > blockIndex[j].seq) {
+					temp = blockIndex[j];
+					blockIndex[j] = blockIndex[i];
+					blockIndex[i] = temp;
+				}
+	}
+#endif
+
+	YYIELD();
+
+	T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR)));
+
+	/* Now scan the blocks looking at the data. */
+	startIterator = 0;
+	endIterator = nBlocksToScan - 1;
+	T(YAFFS_TRACE_SCAN_DEBUG,
+	  (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan));
+
+	/* For each block.... backwards */
+	for (blockIterator = endIterator; !alloc_failed && blockIterator >= startIterator;
+			blockIterator--) {
+		/* Cooperative multitasking! This loop can run for so
+		   long that watchdog timers expire. */
+		YYIELD();
+
+		/* get the block to scan in the correct order */
+		blk = blockIndex[blockIterator].block;
+
+		bi = yaffs_GetBlockInfo(dev, blk);
+
+
+		state = bi->blockState;
+
+		deleted = 0;
+
+		/* For each chunk in each block that needs scanning.... */
+		foundChunksInBlock = 0;
+		for (c = dev->nChunksPerBlock - 1;
+		     !alloc_failed && c >= 0 &&
+		     (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+		      state == YAFFS_BLOCK_STATE_ALLOCATING); c--) {
+			/* Scan backwards...
+			 * Read the tags and decide what to do
+			 */
+
+			chunk = blk * dev->nChunksPerBlock + c;
+
+			result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
+							&tags);
+
+			/* Let's have a good look at this chunk... */
+
+			if (!tags.chunkUsed) {
+				/* An unassigned chunk in the block.
+				 * If there are used chunks after this one, then
+				 * it is a chunk that was skipped due to failing the erased
+				 * check. Just skip it so that it can be deleted.
+				 * But, more typically, We get here when this is an unallocated
+				 * chunk and his means that either the block is empty or
+				 * this is the one being allocated from
+				 */
+
+				if (foundChunksInBlock) {
+					/* This is a chunk that was skipped due to failing the erased check */
+				} else if (c == 0) {
+					/* We're looking at the first chunk in the block so the block is unused */
+					state = YAFFS_BLOCK_STATE_EMPTY;
+					dev->nErasedBlocks++;
+				} else {
+					if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
+					    state == YAFFS_BLOCK_STATE_ALLOCATING) {
+						if (dev->sequenceNumber == bi->sequenceNumber) {
+							/* this is the block being allocated from */
+
+							T(YAFFS_TRACE_SCAN,
+							  (TSTR
+							   (" Allocating from %d %d"
+							    TENDSTR), blk, c));
+
+							state = YAFFS_BLOCK_STATE_ALLOCATING;
+							dev->allocationBlock = blk;
+							dev->allocationPage = c;
+							dev->allocationBlockFinder = blk;
+						} else {
+							/* This is a partially written block that is not
+							 * the current allocation block. This block must have
+							 * had a write failure, so set up for retirement.
+							 */
+
+							 /* bi->needsRetiring = 1; ??? TODO */
+							 bi->gcPrioritise = 1;
+
+							 T(YAFFS_TRACE_ALWAYS,
+							 (TSTR("Partially written block %d detected" TENDSTR),
+							 blk));
+						}
+					}
+				}
+
+				dev->nFreeChunks++;
+
+			} else if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED) {
+				T(YAFFS_TRACE_SCAN,
+				  (TSTR(" Unfixed ECC in chunk(%d:%d), chunk ignored"TENDSTR),
+				  blk, c));
+
+				  dev->nFreeChunks++;
+
+			} else if (tags.chunkId > 0) {
+				/* chunkId > 0 so it is a data chunk... */
+				unsigned int endpos;
+				__u32 chunkBase =
+				    (tags.chunkId - 1) * dev->nDataBytesPerChunk;
+
+				foundChunksInBlock = 1;
+
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				in = yaffs_FindOrCreateObjectByNumber(dev,
+								      tags.
+								      objectId,
+								      YAFFS_OBJECT_TYPE_FILE);
+				if (!in) {
+					/* Out of memory */
+					alloc_failed = 1;
+					T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed !yaffs_FindOrCreateObjectByNumber3" TENDSTR)));
+				}
+
+				if (in &&
+				    in->variantType == YAFFS_OBJECT_TYPE_FILE
+				    && chunkBase <
+				    in->variant.fileVariant.shrinkSize) {
+					/* This has not been invalidated by a resize */
+					if (!yaffs_PutChunkIntoFile(in, tags.chunkId,
+							       chunk, -1)) {
+						alloc_failed = 1;
+						T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed !yaffs_PutChunkIntoFile" TENDSTR)));
+					}
+
+					/* File size is calculated by looking at the data chunks if we have not
+					 * seen an object header yet. Stop this practice once we find an object header.
+					 */
+					endpos =
+					    (tags.chunkId -
+					     1) * dev->nDataBytesPerChunk +
+					    tags.byteCount;
+
+					if (!in->valid &&	/* have not got an object header yet */
+					    in->variant.fileVariant.
+					    scannedFileSize < endpos) {
+						in->variant.fileVariant.
+						    scannedFileSize = endpos;
+						in->variant.fileVariant.
+						    fileSize =
+						    in->variant.fileVariant.
+						    scannedFileSize;
+					}
+
+				} else if (in) {
+					/* This chunk has been invalidated by a resize, so delete */
+					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+
+				}
+			} else {
+				/* chunkId == 0, so it is an ObjectHeader.
+				 * Thus, we read in the object header and make the object
+				 */
+				foundChunksInBlock = 1;
+
+				yaffs_SetChunkBit(dev, blk, c);
+				bi->pagesInUse++;
+
+				oh = NULL;
+				in = NULL;
+
+				if (tags.extraHeaderInfoAvailable) {
+					in = yaffs_FindOrCreateObjectByNumber
+					    (dev, tags.objectId,
+					     tags.extraObjectType);
+					if (!in)
+					{
+						alloc_failed = 1;
+						T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed yaffs_FindOrCreateObjectByNumber2(dev, tags.objectId, oh->type);" TENDSTR)));
+					}
+				}
+
+				if (!in ||
+#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD
+				    !in->valid ||
+#endif
+				    tags.extraShadows ||
+				    (!in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND))) {
+
+					/* If we don't have  valid info then we need to read the chunk
+					 * TODO In future we can probably defer reading the chunk and
+					 * living with invalid data until needed.
+					 */
+
+					result = yaffs_ReadChunkWithTagsFromNAND(dev,
+									chunk,
+									chunkData,
+									NULL);
+
+					oh = (yaffs_ObjectHeader *) chunkData;
+
+					if (dev->inbandTags) {
+						/* Fix up the header if they got corrupted by inband tags */
+						oh->shadowsObject = oh->inbandShadowsObject;
+						oh->isShrink = oh->inbandIsShrink;
+					}
+
+					if (!in) {
+						in = yaffs_FindOrCreateObjectByNumber(dev, tags.objectId, oh->type);
+						if (!in)
+							{
+								alloc_failed = 1;
+								T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed yaffs_FindOrCreateObjectByNumber1(dev, tags.objectId, oh->type);" TENDSTR)));
+
+							}
+					}
+
+				}
+
+				if (!in) {
+					/* TODO Hoosterman we have a problem! */
+					T(YAFFS_TRACE_ERROR,
+					  (TSTR
+					   ("yaffs tragedy: Could not make object for object  %d at chunk %d during scan"
+					    TENDSTR), tags.objectId, chunk));
+					continue;
+				}
+
+				if (in->valid) {
+					/* We have already filled this one.
+					 * We have a duplicate that will be discarded, but
+					 * we first have to suck out resize info if it is a file.
+					 */
+
+					if ((in->variantType == YAFFS_OBJECT_TYPE_FILE) &&
+					     ((oh &&
+					       oh->type == YAFFS_OBJECT_TYPE_FILE) ||
+					      (tags.extraHeaderInfoAvailable  &&
+					       tags.extraObjectType == YAFFS_OBJECT_TYPE_FILE))) {
+						__u32 thisSize =
+						    (oh) ? oh->fileSize : tags.
+						    extraFileLength;
+						__u32 parentObjectId =
+						    (oh) ? oh->
+						    parentObjectId : tags.
+						    extraParentObjectId;
+
+
+						isShrink =
+						    (oh) ? oh->isShrink : tags.
+						    extraIsShrinkHeader;
+
+						/* If it is deleted (unlinked at start also means deleted)
+						 * we treat the file size as being zeroed at this point.
+						 */
+						if (parentObjectId ==
+						    YAFFS_OBJECTID_DELETED
+						    || parentObjectId ==
+						    YAFFS_OBJECTID_UNLINKED) {
+							thisSize = 0;
+							isShrink = 1;
+						}
+
+						if (isShrink &&
+						    in->variant.fileVariant.
+						    shrinkSize > thisSize) {
+							in->variant.fileVariant.
+							    shrinkSize =
+							    thisSize;
+						}
+
+						if (isShrink)
+							bi->hasShrinkHeader = 1;
+
+					}
+					/* Use existing - destroy this one. */
+					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+
+				}
+
+				if (!in->valid && in->variantType !=
+				    (oh ? oh->type : tags.extraObjectType))
+					T(YAFFS_TRACE_ERROR, (
+						TSTR("yaffs tragedy: Bad object type, "
+					    TCONT("%d != %d, for object %d at chunk ")
+					    TCONT("%d during scan")
+						TENDSTR), oh ?
+					    oh->type : tags.extraObjectType,
+					    in->variantType, tags.objectId,
+					    chunk));
+
+				if (!in->valid &&
+				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
+				     tags.objectId ==
+				     YAFFS_OBJECTID_LOSTNFOUND)) {
+					/* We only load some info, don't fiddle with directory structure */
+					in->valid = 1;
+
+					if (oh) {
+						in->variantType = oh->type;
+
+						in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+						in->win_atime[0] = oh->win_atime[0];
+						in->win_ctime[0] = oh->win_ctime[0];
+						in->win_mtime[0] = oh->win_mtime[0];
+						in->win_atime[1] = oh->win_atime[1];
+						in->win_ctime[1] = oh->win_ctime[1];
+						in->win_mtime[1] = oh->win_mtime[1];
+#else
+						in->yst_uid = oh->yst_uid;
+						in->yst_gid = oh->yst_gid;
+						in->yst_atime = oh->yst_atime;
+						in->yst_mtime = oh->yst_mtime;
+						in->yst_ctime = oh->yst_ctime;
+						in->yst_rdev = oh->yst_rdev;
+
+#endif
+					} else {
+						in->variantType = tags.extraObjectType;
+						in->lazyLoaded = 1;
+					}
+
+					in->hdrChunk = chunk;
+
+				} else if (!in->valid) {
+					/* we need to load this info */
+
+					in->valid = 1;
+					in->hdrChunk = chunk;
+
+					if (oh) {
+						in->variantType = oh->type;
+
+						in->yst_mode = oh->yst_mode;
+#ifdef CONFIG_YAFFS_WINCE
+						in->win_atime[0] = oh->win_atime[0];
+						in->win_ctime[0] = oh->win_ctime[0];
+						in->win_mtime[0] = oh->win_mtime[0];
+						in->win_atime[1] = oh->win_atime[1];
+						in->win_ctime[1] = oh->win_ctime[1];
+						in->win_mtime[1] = oh->win_mtime[1];
+#else
+						in->yst_uid = oh->yst_uid;
+						in->yst_gid = oh->yst_gid;
+						in->yst_atime = oh->yst_atime;
+						in->yst_mtime = oh->yst_mtime;
+						in->yst_ctime = oh->yst_ctime;
+						in->yst_rdev = oh->yst_rdev;
+#endif
+
+						if (oh->shadowsObject > 0)
+							yaffs_HandleShadowedObject(dev,
+									   oh->
+									   shadowsObject,
+									   1);
+
+
+						yaffs_SetObjectName(in, oh->name);
+						parent =
+						    yaffs_FindOrCreateObjectByNumber
+							(dev, oh->parentObjectId,
+							 YAFFS_OBJECT_TYPE_DIRECTORY);
+
+						 fileSize = oh->fileSize;
+						 isShrink = oh->isShrink;
+						 equivalentObjectId = oh->equivalentObjectId;
+
+					} else {
+						in->variantType = tags.extraObjectType;
+						parent =
+						    yaffs_FindOrCreateObjectByNumber
+							(dev, tags.extraParentObjectId,
+							 YAFFS_OBJECT_TYPE_DIRECTORY);
+						 fileSize = tags.extraFileLength;
+						 isShrink = tags.extraIsShrinkHeader;
+						 equivalentObjectId = tags.extraEquivalentObjectId;
+						in->lazyLoaded = 1;
+
+					}
+					in->dirty = 0;
+
+					if (!parent)
+						{
+							T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed !parent" TENDSTR)));
+							alloc_failed = 1;
+						}
+
+					/* directory stuff...
+					 * hook up to parent
+					 */
+
+					if (parent && parent->variantType ==
+					    YAFFS_OBJECT_TYPE_UNKNOWN) {
+						/* Set up as a directory */
+						parent->variantType =
+							YAFFS_OBJECT_TYPE_DIRECTORY;
+						YINIT_LIST_HEAD(&parent->variant.
+							directoryVariant.
+							children);
+					} else if (!parent || parent->variantType !=
+						   YAFFS_OBJECT_TYPE_DIRECTORY) {
+						/* Hoosterman, another problem....
+						 * We're trying to use a non-directory as a directory
+						 */
+
+						T(YAFFS_TRACE_ERROR,
+						  (TSTR
+						   ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+						    TENDSTR)));
+						parent = dev->lostNFoundDir;
+					}
+
+					yaffs_AddObjectToDirectory(parent, in);
+
+					itsUnlinked = (parent == dev->deletedDir) ||
+						      (parent == dev->unlinkedDir);
+
+					if (isShrink) {
+						/* Mark the block as having a shrinkHeader */
+						bi->hasShrinkHeader = 1;
+					}
+
+					/* Note re hardlinks.
+					 * Since we might scan a hardlink before its equivalent object is scanned
+					 * we put them all in a list.
+					 * After scanning is complete, we should have all the objects, so we run
+					 * through this list and fix up all the chains.
+					 */
+
+					switch (in->variantType) {
+					case YAFFS_OBJECT_TYPE_UNKNOWN:
+						/* Todo got a problem */
+						break;
+					case YAFFS_OBJECT_TYPE_FILE:
+
+						if (in->variant.fileVariant.
+						    scannedFileSize < fileSize) {
+							/* This covers the case where the file size is greater
+							 * than where the data is
+							 * This will happen if the file is resized to be larger
+							 * than its current data extents.
+							 */
+							in->variant.fileVariant.fileSize = fileSize;
+							in->variant.fileVariant.scannedFileSize =
+							    in->variant.fileVariant.fileSize;
+						}
+
+						if (isShrink &&
+						    in->variant.fileVariant.shrinkSize > fileSize) {
+							in->variant.fileVariant.shrinkSize = fileSize;
+						}
+
+						break;
+					case YAFFS_OBJECT_TYPE_HARDLINK:
+						if (!itsUnlinked) {
+							in->variant.hardLinkVariant.equivalentObjectId =
+								equivalentObjectId;
+							in->hardLinks.next =
+								(struct ylist_head *) hardList;
+							hardList = in;
+						}
+						break;
+					case YAFFS_OBJECT_TYPE_DIRECTORY:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SPECIAL:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SYMLINK:
+						if (oh) {
+							in->variant.symLinkVariant.alias =
+								yaffs_CloneString(oh->alias);
+							if (!in->variant.symLinkVariant.alias)
+							{
+								T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed !in->variant.symLinkVariant.alias" TENDSTR)));
+								alloc_failed = 1;
+							}
+						}
+						break;
+					}
+
+				}
+
+			}
+
+		} /* End of scanning for each chunk */
+
+		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
+			/* If we got this far while scanning, then the block is fully allocated. */
+			state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+		bi->blockState = state;
+
+		/* Now let's see if it was dirty */
+		if (bi->pagesInUse == 0 &&
+		    !bi->hasShrinkHeader &&
+		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
+			yaffs_BlockBecameDirty(dev, blk);
+		}
+
+	}
+
+	if (altBlockIndex)
+		YFREE_ALT(blockIndex);
+	else
+		YFREE(blockIndex);
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We should now have scanned all the objects, now it's time to add these
+	 * hardlinks.
+	 */
+	yaffs_HardlinkFixup(dev, hardList);
+
+
+	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
+
+	if (alloc_failed)
+	{
+		T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards alloc_failed%d" TENDSTR), alloc_failed));
+		return YAFFS_FAIL;
+	}
+
+	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards ends" TENDSTR)));
+
+	return YAFFS_OK;
+}
+
+/*------------------------------  Directory Functions ----------------------------- */
+
+static void yaffs_VerifyObjectInDirectory(yaffs_Object *obj)
+{
+	struct ylist_head *lh;
+	yaffs_Object *listObj;
+
+	int count = 0;
+
+	if (!obj) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR)));
+		YBUG();
+		return;
+	}
+
+	if (yaffs_SkipVerification(obj->myDev))
+		return;
+
+	if (!obj->parent) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Object does not have parent" TENDSTR)));
+		YBUG();
+		return;
+	}
+
+	if (obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Parent is not directory" TENDSTR)));
+		YBUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	ylist_for_each(lh, &obj->parent->variant.directoryVariant.children) {
+		if (lh) {
+			listObj = ylist_entry(lh, yaffs_Object, siblings);
+			yaffs_VerifyObject(listObj);
+			if (obj == listObj)
+				count++;
+		}
+	 }
+
+	if (count != 1) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory %d times" TENDSTR), count));
+		YBUG();
+	}
+}
+
+static void yaffs_VerifyDirectory(yaffs_Object *directory)
+{
+	struct ylist_head *lh;
+	yaffs_Object *listObj;
+
+	if (!directory) {
+		YBUG();
+		return;
+	}
+
+	if (yaffs_SkipFullVerification(directory->myDev))
+		return;
+
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("Directory has wrong type: %d" TENDSTR), directory->variantType));
+		YBUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	ylist_for_each(lh, &directory->variant.directoryVariant.children) {
+		if (lh) {
+			listObj = ylist_entry(lh, yaffs_Object, siblings);
+			if (listObj->parent != directory) {
+				T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory list has wrong parent %p" TENDSTR), listObj->parent));
+				YBUG();
+			}
+			yaffs_VerifyObjectInDirectory(listObj);
+		}
+	}
+}
+
+/*
+ *yaffs_UpdateParent() handles fixing a directories mtime and ctime when a new
+ * link (ie. name) is created or deleted in the directory.
+ *
+ * ie.
+ *   create dir/a : update dir's mtime/ctime
+ *   rm dir/a:   update dir's mtime/ctime
+ *   modify dir/a: don't update dir's mtimme/ctime
+ */
+ 
+static void yaffs_UpdateParent(yaffs_Object *obj)
+{
+	if(!obj)
+		return;
+
+	obj->dirty = 1;
+	obj->yst_mtime = obj->yst_ctime = Y_CURRENT_TIME;
+
+	yaffs_UpdateObjectHeader(obj,NULL,0,0,0);
+}
+
+static void yaffs_RemoveObjectFromDirectory(yaffs_Object *obj)
+{
+	yaffs_Device *dev = obj->myDev;
+	yaffs_Object *parent;
+
+	yaffs_VerifyObjectInDirectory(obj);
+	parent = obj->parent;
+
+	yaffs_VerifyDirectory(parent);
+
+	if (dev && dev->removeObjectCallback)
+		dev->removeObjectCallback(obj);
+
+
+	ylist_del_init(&obj->siblings);
+	obj->parent = NULL;
+	
+	yaffs_VerifyDirectory(parent);
+}
+
+static void yaffs_AddObjectToDirectory(yaffs_Object *directory,
+					yaffs_Object *obj)
+{
+	if (!directory) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: Trying to add an object to a null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return;
+	}
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: Trying to add an object to a non-directory"
+		    TENDSTR)));
+		YBUG();
+	}
+
+	if (obj->siblings.prev == NULL) {
+		/* Not initialised */
+		YBUG();
+	}
+
+
+	yaffs_VerifyDirectory(directory);
+
+	yaffs_RemoveObjectFromDirectory(obj);
+
+
+	/* Now add it */
+	ylist_add(&obj->siblings, &directory->variant.directoryVariant.children);
+	obj->parent = directory;
+
+	if (directory == obj->myDev->unlinkedDir
+			|| directory == obj->myDev->deletedDir) {
+		obj->unlinked = 1;
+		obj->myDev->nUnlinkedFiles++;
+		obj->renameAllowed = 0;
+	}
+
+	yaffs_VerifyDirectory(directory);
+	yaffs_VerifyObjectInDirectory(obj);
+}
+
+yaffs_Object *yaffs_FindObjectByName(yaffs_Object *directory,
+				     const YCHAR *name)
+{
+	int sum;
+
+	struct ylist_head *i;
+	YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1];
+
+	yaffs_Object *l;
+
+	if (!name)
+		return NULL;
+
+	if (!directory) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return NULL;
+	}
+	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
+		YBUG();
+	}
+
+	sum = yaffs_CalcNameSum(name);
+
+	ylist_for_each(i, &directory->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+
+			if (l->parent != directory)
+				YBUG();
+
+			yaffs_CheckObjectDetailsLoaded(l);
+
+			/* Special case for lost-n-found */
+			if (l->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
+				if (yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME) == 0)
+					return l;
+			} else if (yaffs_SumCompare(l->sum, sum) || l->hdrChunk <= 0) {
+				/* LostnFound chunk called Objxxx
+				 * Do a real check
+				 */
+				yaffs_GetObjectName(l, buffer,
+						    YAFFS_MAX_NAME_LENGTH + 1);
+				if (yaffs_strncmp(name, buffer, YAFFS_MAX_NAME_LENGTH) == 0)
+					return l;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+
+#if 0
+int yaffs_ApplyToDirectoryChildren(yaffs_Object *theDir,
+					int (*fn) (yaffs_Object *))
+{
+	struct ylist_head *i;
+	yaffs_Object *l;
+
+	if (!theDir) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
+		    TENDSTR)));
+		YBUG();
+		return YAFFS_FAIL;
+	}
+	if (theDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
+		YBUG();
+		return YAFFS_FAIL;
+	}
+
+	ylist_for_each(i, &theDir->variant.directoryVariant.children) {
+		if (i) {
+			l = ylist_entry(i, yaffs_Object, siblings);
+			if (l && !fn(l))
+				return YAFFS_FAIL;
+		}
+	}
+
+	return YAFFS_OK;
+
+}
+#endif
+
+/* GetEquivalentObject dereferences any hard links to get to the
+ * actual object.
+ */
+
+yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object *obj)
+{
+	if (obj && obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
+		/* We want the object id of the equivalent object, not this one */
+		obj = obj->variant.hardLinkVariant.equivalentObject;
+		yaffs_CheckObjectDetailsLoaded(obj);
+	}
+	return obj;
+}
+
+int yaffs_GetObjectName(yaffs_Object *obj, YCHAR *name, int buffSize)
+{
+	memset(name, 0, buffSize * sizeof(YCHAR));
+
+	yaffs_CheckObjectDetailsLoaded(obj);
+
+	if (obj->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
+		yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffSize - 1);
+	} else if (obj->hdrChunk <= 0) {
+		YCHAR locName[20];
+		YCHAR numString[20];
+		YCHAR *x = &numString[19];
+		unsigned v = obj->objectId;
+		numString[19] = 0;
+		while (v > 0) {
+			x--;
+			*x = '0' + (v % 10);
+			v /= 10;
+		}
+		/* make up a name */
+		yaffs_strcpy(locName, YAFFS_LOSTNFOUND_PREFIX);
+		yaffs_strcat(locName, x);
+		yaffs_strncpy(name, locName, buffSize - 1);
+
+	}
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	else if (obj->shortName[0])
+		yaffs_strcpy(name, obj->shortName);
+#endif
+	else {
+		int result;
+		__u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__);
+
+		yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer;
+
+		memset(buffer, 0, obj->myDev->nDataBytesPerChunk);
+
+		if (obj->hdrChunk > 0) {
+			result = yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
+							obj->hdrChunk, buffer,
+							NULL);
+		}
+		yaffs_strncpy(name, oh->name, buffSize - 1);
+
+		yaffs_ReleaseTempBuffer(obj->myDev, buffer, __LINE__);
+	}
+
+	return yaffs_strlen(name);
+}
+
+int yaffs_GetObjectFileLength(yaffs_Object *obj)
+{
+	/* Dereference any hard linking */
+	obj = yaffs_GetEquivalentObject(obj);
+
+	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE)
+		return obj->variant.fileVariant.fileSize;
+	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
+		return yaffs_strlen(obj->variant.symLinkVariant.alias);
+	else {
+		/* Only a directory should drop through to here */
+		return obj->myDev->nDataBytesPerChunk;
+	}
+}
+
+int yaffs_GetObjectLinkCount(yaffs_Object *obj)
+{
+	int count = 0;
+	struct ylist_head *i;
+
+	if (!obj->unlinked)
+		count++;		/* the object itself */
+
+	ylist_for_each(i, &obj->hardLinks)
+		count++;		/* add the hard links; */
+
+	return count;
+}
+
+int yaffs_GetObjectInode(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+
+	return obj->objectId;
+}
+
+unsigned yaffs_GetObjectType(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+
+	switch (obj->variantType) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		return DT_REG;
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		return DT_DIR;
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		return DT_LNK;
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		return DT_REG;
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		if (S_ISFIFO(obj->yst_mode))
+			return DT_FIFO;
+		if (S_ISCHR(obj->yst_mode))
+			return DT_CHR;
+		if (S_ISBLK(obj->yst_mode))
+			return DT_BLK;
+		if (S_ISSOCK(obj->yst_mode))
+			return DT_SOCK;
+	default:
+		return DT_REG;
+		break;
+	}
+}
+
+YCHAR *yaffs_GetSymlinkAlias(yaffs_Object *obj)
+{
+	obj = yaffs_GetEquivalentObject(obj);
+	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
+		return yaffs_CloneString(obj->variant.symLinkVariant.alias);
+	else
+		return yaffs_CloneString(_Y(""));
+}
+
+#ifndef CONFIG_YAFFS_WINCE
+
+int yaffs_SetAttributes(yaffs_Object *obj, struct iattr *attr)
+{
+	unsigned int valid = attr->ia_valid;
+
+	if (valid & ATTR_MODE)
+		obj->yst_mode = attr->ia_mode;
+	if (valid & ATTR_UID)
+		obj->yst_uid = attr->ia_uid;
+	if (valid & ATTR_GID)
+		obj->yst_gid = attr->ia_gid;
+
+	if (valid & ATTR_ATIME)
+		obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime);
+	if (valid & ATTR_CTIME)
+		obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime);
+	if (valid & ATTR_MTIME)
+		obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime);
+
+	if (valid & ATTR_SIZE)
+		yaffs_ResizeFile(obj, attr->ia_size);
+
+	yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
+
+	return YAFFS_OK;
+
+}
+int yaffs_GetAttributes(yaffs_Object *obj, struct iattr *attr)
+{
+	unsigned int valid = 0;
+
+	attr->ia_mode = obj->yst_mode;
+	valid |= ATTR_MODE;
+	attr->ia_uid = obj->yst_uid;
+	valid |= ATTR_UID;
+	attr->ia_gid = obj->yst_gid;
+	valid |= ATTR_GID;
+
+	Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime;
+	valid |= ATTR_ATIME;
+	Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime;
+	valid |= ATTR_CTIME;
+	Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime;
+	valid |= ATTR_MTIME;
+
+	attr->ia_size = yaffs_GetFileSize(obj);
+	valid |= ATTR_SIZE;
+
+	attr->ia_valid = valid;
+
+	return YAFFS_OK;
+}
+
+#endif
+
+#if 0
+int yaffs_DumpObject(yaffs_Object *obj)
+{
+	YCHAR name[257];
+
+	yaffs_GetObjectName(obj, name, YAFFS_MAX_NAME_LENGTH + 1);
+
+	T(YAFFS_TRACE_ALWAYS,
+	  (TSTR
+	   ("Object %d, inode %d \"%s\"\n dirty %d valid %d serial %d sum %d"
+	    " chunk %d type %d size %d\n"
+	    TENDSTR), obj->objectId, yaffs_GetObjectInode(obj), name,
+	   obj->dirty, obj->valid, obj->serial, obj->sum, obj->hdrChunk,
+	   yaffs_GetObjectType(obj), yaffs_GetObjectFileLength(obj)));
+
+	return YAFFS_OK;
+}
+#endif
+
+/*---------------------------- Initialisation code -------------------------------------- */
+
+static int yaffs_CheckDevFunctions(const yaffs_Device *dev)
+{
+
+	/* Common functions, gotta have */
+	if (!dev->eraseBlockInNAND || !dev->initialiseNAND)
+		return 0;
+
+#ifdef CONFIG_YAFFS_YAFFS2
+
+	/* Can use the "with tags" style interface for yaffs1 or yaffs2 */
+	if (dev->writeChunkWithTagsToNAND &&
+	    dev->readChunkWithTagsFromNAND &&
+	    !dev->writeChunkToNAND &&
+	    !dev->readChunkFromNAND &&
+	    dev->markNANDBlockBad && dev->queryNANDBlock)
+		return 1;
+#endif
+
+	/* Can use the "spare" style interface for yaffs1 */
+	if (!dev->isYaffs2 &&
+	    !dev->writeChunkWithTagsToNAND &&
+	    !dev->readChunkWithTagsFromNAND &&
+	    dev->writeChunkToNAND &&
+	    dev->readChunkFromNAND &&
+	    !dev->markNANDBlockBad && !dev->queryNANDBlock)
+		return 1;
+
+	return 0;		/* bad */
+}
+
+
+static int yaffs_CreateInitialDirectories(yaffs_Device *dev)
+{
+	/* Initialise the unlinked, deleted, root and lost and found directories */
+
+	dev->lostNFoundDir = dev->rootDir =  NULL;
+	dev->unlinkedDir = dev->deletedDir = NULL;
+
+	dev->unlinkedDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR);
+
+	dev->deletedDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_DELETED, S_IFDIR);
+
+	dev->rootDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_ROOT,
+				      YAFFS_ROOT_MODE | S_IFDIR);
+	dev->lostNFoundDir =
+	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_LOSTNFOUND,
+				      YAFFS_LOSTNFOUND_MODE | S_IFDIR);
+
+	if (dev->lostNFoundDir && dev->rootDir && dev->unlinkedDir && dev->deletedDir) {
+		yaffs_AddObjectToDirectory(dev->rootDir, dev->lostNFoundDir);
+		return YAFFS_OK;
+	}
+
+	return YAFFS_FAIL;
+}
+
+int yaffs_GutsInitialise(yaffs_Device *dev)
+{
+	int init_failed = 0;
+	unsigned x;
+	int bits;
+
+	T(YAFFS_TRACE_TRACING, (TSTR("yaffs: yaffs_GutsInitialise()" TENDSTR)));
+
+	/* Check stuff that must be set */
+
+	if (!dev) {
+		T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	dev->internalStartBlock = dev->startBlock;
+	dev->internalEndBlock = dev->endBlock;
+	dev->blockOffset = 0;
+	dev->chunkOffset = 0;
+	dev->nFreeChunks = 0;
+
+	dev->gcBlock = -1;
+
+	if (dev->startBlock == 0) {
+		dev->internalStartBlock = dev->startBlock + 1;
+		dev->internalEndBlock = dev->endBlock + 1;
+		dev->blockOffset = 1;
+		dev->chunkOffset = dev->nChunksPerBlock;
+	}
+
+	/* Check geometry parameters. */
+
+	if ((!dev->inbandTags && dev->isYaffs2 && dev->totalBytesPerChunk < 1024) ||
+	    (!dev->isYaffs2 && dev->totalBytesPerChunk < 512) ||
+	    (dev->inbandTags && !dev->isYaffs2) ||
+	     dev->nChunksPerBlock < 2 ||
+	     dev->nReservedBlocks < 2 ||
+	     dev->internalStartBlock <= 0 ||
+	     dev->internalEndBlock <= 0 ||
+	     dev->internalEndBlock <= (dev->internalStartBlock + dev->nReservedBlocks + 2)) {	/* otherwise it is too small */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inbandTags %d "
+		    TENDSTR), dev->totalBytesPerChunk, dev->isYaffs2 ? "2" : "", dev->inbandTags));
+		return YAFFS_FAIL;
+	}
+
+	if (yaffs_InitialiseNAND(dev) != YAFFS_OK) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: InitialiseNAND failed" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Sort out space for inband tags, if required */
+	if (dev->inbandTags)
+		dev->nDataBytesPerChunk = dev->totalBytesPerChunk - sizeof(yaffs_PackedTags2TagsPart);
+	else
+		dev->nDataBytesPerChunk = dev->totalBytesPerChunk;
+
+	/* Got the right mix of functions? */
+	if (!yaffs_CheckDevFunctions(dev)) {
+		/* Function missing */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR
+		   ("yaffs: device function(s) missing or wrong\n" TENDSTR)));
+
+		return YAFFS_FAIL;
+	}
+
+	/* This is really a compilation check. */
+	if (!yaffs_CheckStructures()) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs_CheckStructures failed\n" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	if (dev->isMounted) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: device already mounted\n" TENDSTR)));
+		return YAFFS_FAIL;
+	}
+
+	/* Finished with most checks. One or two more checks happen later on too. */
+
+	dev->isMounted = 1;
+
+	/* OK now calculate a few things for the device */
+
+	/*
+	 *  Calculate all the chunk size manipulation numbers:
+	 */
+	x = dev->nDataBytesPerChunk;
+	/* We always use dev->chunkShift and dev->chunkDiv */
+	dev->chunkShift = Shifts(x);
+	x >>= dev->chunkShift;
+	dev->chunkDiv = x;
+	/* We only use chunk mask if chunkDiv is 1 */
+	dev->chunkMask = (1<<dev->chunkShift) - 1;
+
+	/*
+	 * Calculate chunkGroupBits.
+	 * We need to find the next power of 2 > than internalEndBlock
+	 */
+
+	x = dev->nChunksPerBlock * (dev->internalEndBlock + 1);
+
+	bits = ShiftsGE(x);
+
+	/* Set up tnode width if wide tnodes are enabled. */
+	if (!dev->wideTnodesDisabled) {
+		/* bits must be even so that we end up with 32-bit words */
+		if (bits & 1)
+			bits++;
+		if (bits < 16)
+			dev->tnodeWidth = 16;
+		else
+			dev->tnodeWidth = bits;
+	} else
+		dev->tnodeWidth = 16;
+
+	dev->tnodeMask = (1<<dev->tnodeWidth)-1;
+
+	/* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled),
+	 * so if the bitwidth of the
+	 * chunk range we're using is greater than 16 we need
+	 * to figure out chunk shift and chunkGroupSize
+	 */
+
+	if (bits <= dev->tnodeWidth)
+		dev->chunkGroupBits = 0;
+	else
+		dev->chunkGroupBits = bits - dev->tnodeWidth;
+
+
+	dev->chunkGroupSize = 1 << dev->chunkGroupBits;
+
+	if (dev->nChunksPerBlock < dev->chunkGroupSize) {
+		/* We have a problem because the soft delete won't work if
+		 * the chunk group size > chunks per block.
+		 * This can be remedied by using larger "virtual blocks".
+		 */
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("yaffs: chunk group too large\n" TENDSTR)));
+
+		return YAFFS_FAIL;
+	}
+
+	/* OK, we've finished verifying the device, lets continue with initialisation */
+
+	/* More device initialisation */
+	dev->garbageCollections = 0;
+	dev->passiveGarbageCollections = 0;
+	dev->currentDirtyChecker = 0;
+	dev->bufferedBlock = -1;
+	dev->doingBufferedBlockRewrite = 0;
+	dev->nDeletedFiles = 0;
+	dev->nBackgroundDeletions = 0;
+	dev->nUnlinkedFiles = 0;
+	dev->eccFixed = 0;
+	dev->eccUnfixed = 0;
+	dev->tagsEccFixed = 0;
+	dev->tagsEccUnfixed = 0;
+	dev->nErasureFailures = 0;
+	dev->nErasedBlocks = 0;
+	dev->isDoingGC = 0;
+	dev->hasPendingPrioritisedGCs = 1; /* Assume the worst for now, will get fixed on first GC */
+
+	/* Initialise temporary buffers and caches. */
+	if (!yaffs_InitialiseTempBuffers(dev))
+		init_failed = 1;
+
+	dev->srCache = NULL;
+	dev->gcCleanupList = NULL;
+
+
+	if (!init_failed &&
+	    dev->nShortOpCaches > 0) {
+		int i;
+		void *buf;
+		int srCacheBytes = dev->nShortOpCaches * sizeof(yaffs_ChunkCache);
+
+		if (dev->nShortOpCaches > YAFFS_MAX_SHORT_OP_CACHES)
+			dev->nShortOpCaches = YAFFS_MAX_SHORT_OP_CACHES;
+
+		dev->srCache =  YMALLOC(srCacheBytes);
+
+		buf = (__u8 *) dev->srCache;
+
+		if (dev->srCache)
+			memset(dev->srCache, 0, srCacheBytes);
+
+		for (i = 0; i < dev->nShortOpCaches && buf; i++) {
+			dev->srCache[i].object = NULL;
+			dev->srCache[i].lastUse = 0;
+			dev->srCache[i].dirty = 0;
+			dev->srCache[i].data = buf = YMALLOC_DMA(dev->totalBytesPerChunk);
+		}
+		if (!buf)
+			init_failed = 1;
+
+		dev->srLastUse = 0;
+	}
+
+	dev->cacheHits = 0;
+
+	if (!init_failed) {
+		dev->gcCleanupList = YMALLOC(dev->nChunksPerBlock * sizeof(__u32));
+		if (!dev->gcCleanupList)
+			init_failed = 1;
+	}
+
+	if (dev->isYaffs2)
+		dev->useHeaderFileSize = 1;
+
+	if (!init_failed && !yaffs_InitialiseBlocks(dev))
+		init_failed = 1;
+
+	yaffs_InitialiseTnodes(dev);
+	yaffs_InitialiseObjects(dev);
+
+	if (!init_failed && !yaffs_CreateInitialDirectories(dev))
+		init_failed = 1;
+
+
+	if (!init_failed) {
+		/* Now scan the flash. */
+		if (dev->isYaffs2) {
+			if (yaffs_CheckpointRestore(dev)) {
+				yaffs_CheckObjectDetailsLoaded(dev->rootDir);
+				T(YAFFS_TRACE_ALWAYS,
+				  (TSTR("yaffs: restored from checkpoint" TENDSTR)));
+			} else {
+
+				/* Clean up the mess caused by an aborted checkpoint load
+				 * and scan backwards.
+				 */
+				yaffs_DeinitialiseBlocks(dev);
+				yaffs_DeinitialiseTnodes(dev);
+				yaffs_DeinitialiseObjects(dev);
+
+
+				dev->nErasedBlocks = 0;
+				dev->nFreeChunks = 0;
+				dev->allocationBlock = -1;
+				dev->allocationPage = -1;
+				dev->nDeletedFiles = 0;
+				dev->nUnlinkedFiles = 0;
+				dev->nBackgroundDeletions = 0;
+				dev->oldestDirtySequence = 0;
+
+				if (!init_failed && !yaffs_InitialiseBlocks(dev))
+					init_failed = 1;
+
+				yaffs_InitialiseTnodes(dev);
+				yaffs_InitialiseObjects(dev);
+
+				if (!init_failed && !yaffs_CreateInitialDirectories(dev))
+					init_failed = 1;
+
+				if (!init_failed && !yaffs_ScanBackwards(dev))
+					init_failed = 1;
+			}
+		} else if (!yaffs_Scan(dev))
+				init_failed = 1;
+
+		yaffs_StripDeletedObjects(dev);
+		yaffs_FixHangingObjects(dev);
+		if(dev->emptyLostAndFound)
+			yaffs_EmptyLostAndFound(dev);
+	}
+
+	if (init_failed) {
+		/* Clean up the mess */
+		T(YAFFS_TRACE_TRACING,
+		  (TSTR("yaffs: yaffs_GutsInitialise() aborted.\n" TENDSTR)));
+
+		yaffs_Deinitialise(dev);
+		return YAFFS_FAIL;
+	}
+
+	/* Zero out stats */
+	dev->nPageReads = 0;
+	dev->nPageWrites = 0;
+	dev->nBlockErasures = 0;
+	dev->nGCCopies = 0;
+	dev->nRetriedWrites = 0;
+
+	dev->nRetiredBlocks = 0;
+
+	yaffs_VerifyFreeChunks(dev);
+	yaffs_VerifyBlocks(dev);
+
+	/* Clean up any aborted checkpoint data */
+	if (!dev->isCheckpointed && dev->blocksInCheckpoint > 0)
+		yaffs_InvalidateCheckpoint(dev);
+
+	T(YAFFS_TRACE_TRACING,
+	  (TSTR("yaffs: yaffs_GutsInitialise() done.\n" TENDSTR)));
+	return YAFFS_OK;
+
+}
+
+void yaffs_Deinitialise(yaffs_Device *dev)
+{
+	if (dev->isMounted) {
+		int i;
+
+		yaffs_DeinitialiseBlocks(dev);
+		yaffs_DeinitialiseTnodes(dev);
+		yaffs_DeinitialiseObjects(dev);
+		if (dev->nShortOpCaches > 0 &&
+		    dev->srCache) {
+
+			for (i = 0; i < dev->nShortOpCaches; i++) {
+				if (dev->srCache[i].data)
+					YFREE(dev->srCache[i].data);
+				dev->srCache[i].data = NULL;
+			}
+
+			YFREE(dev->srCache);
+			dev->srCache = NULL;
+		}
+
+		YFREE(dev->gcCleanupList);
+
+		for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++)
+			YFREE(dev->tempBuffer[i].buffer);
+
+		dev->isMounted = 0;
+
+		if (dev->deinitialiseNAND)
+			dev->deinitialiseNAND(dev);
+	}
+}
+
+static int yaffs_CountFreeChunks(yaffs_Device *dev)
+{
+	int nFree;
+	int b;
+
+	yaffs_BlockInfo *blk;
+
+	for (nFree = 0, b = dev->internalStartBlock; b <= dev->internalEndBlock;
+			b++) {
+		blk = yaffs_GetBlockInfo(dev, b);
+
+		switch (blk->blockState) {
+		case YAFFS_BLOCK_STATE_EMPTY:
+		case YAFFS_BLOCK_STATE_ALLOCATING:
+		case YAFFS_BLOCK_STATE_COLLECTING:
+		case YAFFS_BLOCK_STATE_FULL:
+			nFree +=
+			    (dev->nChunksPerBlock - blk->pagesInUse +
+			     blk->softDeletions);
+			break;
+		default:
+			break;
+		}
+	}
+
+	return nFree;
+}
+
+int yaffs_GetNumberOfFreeChunks(yaffs_Device *dev)
+{
+	/* This is what we report to the outside world */
+
+	int nFree;
+	int nDirtyCacheChunks;
+	int blocksForCheckpoint;
+	int i;
+
+#if 1
+	nFree = dev->nFreeChunks;
+#else
+	nFree = yaffs_CountFreeChunks(dev);
+#endif
+
+	nFree += dev->nDeletedFiles;
+
+	/* Now count the number of dirty chunks in the cache and subtract those */
+
+	for (nDirtyCacheChunks = 0, i = 0; i < dev->nShortOpCaches; i++) {
+		if (dev->srCache[i].dirty)
+			nDirtyCacheChunks++;
+	}
+
+	nFree -= nDirtyCacheChunks;
+
+	nFree -= ((dev->nReservedBlocks + 1) * dev->nChunksPerBlock);
+
+	/* Now we figure out how much to reserve for the checkpoint and report that... */
+	blocksForCheckpoint = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint;
+	if (blocksForCheckpoint < 0)
+		blocksForCheckpoint = 0;
+
+	nFree -= (blocksForCheckpoint * dev->nChunksPerBlock);
+
+	if (nFree < 0)
+		nFree = 0;
+
+	return nFree;
+
+}
+
+static int yaffs_freeVerificationFailures;
+
+static void yaffs_VerifyFreeChunks(yaffs_Device *dev)
+{
+	int counted;
+	int difference;
+
+	if (yaffs_SkipVerification(dev))
+		return;
+
+	counted = yaffs_CountFreeChunks(dev);
+
+	difference = dev->nFreeChunks - counted;
+
+	if (difference) {
+		T(YAFFS_TRACE_ALWAYS,
+		  (TSTR("Freechunks verification failure %d %d %d" TENDSTR),
+		   dev->nFreeChunks, counted, difference));
+		yaffs_freeVerificationFailures++;
+	}
+}
+
+/*---------------------------------------- YAFFS test code ----------------------*/
+
+#define yaffs_CheckStruct(structure, syze, name) \
+	do { \
+		if (sizeof(structure) != syze) { \
+			T(YAFFS_TRACE_ALWAYS, (TSTR("%s should be %d but is %d\n" TENDSTR),\
+				name, syze, sizeof(structure))); \
+			return YAFFS_FAIL; \
+		} \
+	} while (0)
+
+static int yaffs_CheckStructures(void)
+{
+/*      yaffs_CheckStruct(yaffs_Tags,8,"yaffs_Tags"); */
+/*      yaffs_CheckStruct(yaffs_TagsUnion,8,"yaffs_TagsUnion"); */
+/*      yaffs_CheckStruct(yaffs_Spare,16,"yaffs_Spare"); */
+#ifndef CONFIG_YAFFS_TNODE_LIST_DEBUG
+	yaffs_CheckStruct(yaffs_Tnode, 2 * YAFFS_NTNODES_LEVEL0, "yaffs_Tnode");
+#endif
+#ifndef CONFIG_YAFFS_WINCE
+	yaffs_CheckStruct(yaffs_ObjectHeader, 512, "yaffs_ObjectHeader");
+#endif
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffs_guts.h b/fs/yaffs2/yaffs_guts.h
new file mode 100644
index 00000000000..1305909ecc0
--- /dev/null
+++ b/fs/yaffs2/yaffs_guts.h
@@ -0,0 +1,912 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_GUTS_H__
+#define __YAFFS_GUTS_H__
+
+#include "devextras.h"
+#include "yportenv.h"
+
+#define YAFFS_OK	1
+#define YAFFS_FAIL  0
+
+/* Give us a  Y=0x59,
+ * Give us an A=0x41,
+ * Give us an FF=0xFF
+ * Give us an S=0x53
+ * And what have we got...
+ */
+#define YAFFS_MAGIC			0x5941FF53
+
+#define YAFFS_NTNODES_LEVEL0	  	16
+#define YAFFS_TNODES_LEVEL0_BITS	4
+#define YAFFS_TNODES_LEVEL0_MASK	0xf
+
+#define YAFFS_NTNODES_INTERNAL 		(YAFFS_NTNODES_LEVEL0 / 2)
+#define YAFFS_TNODES_INTERNAL_BITS 	(YAFFS_TNODES_LEVEL0_BITS - 1)
+#define YAFFS_TNODES_INTERNAL_MASK	0x7
+#define YAFFS_TNODES_MAX_LEVEL		6
+
+#ifndef CONFIG_YAFFS_NO_YAFFS1
+#define YAFFS_BYTES_PER_SPARE		16
+#define YAFFS_BYTES_PER_CHUNK		512
+#define YAFFS_CHUNK_SIZE_SHIFT		9
+#define YAFFS_CHUNKS_PER_BLOCK		32
+#define YAFFS_BYTES_PER_BLOCK		(YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK)
+#endif
+
+#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 	1024
+#define YAFFS_MIN_YAFFS2_SPARE_SIZE	32
+
+#define YAFFS_MAX_CHUNK_ID		0x000FFFFF
+
+#define YAFFS_UNUSED_OBJECT_ID		0x0003FFFF
+
+#define YAFFS_ALLOCATION_NOBJECTS	100
+#define YAFFS_ALLOCATION_NTNODES	100
+#define YAFFS_ALLOCATION_NLINKS		100
+
+#define YAFFS_NOBJECT_BUCKETS		256
+
+
+#define YAFFS_OBJECT_SPACE		0x40000
+
+#define YAFFS_CHECKPOINT_VERSION 	3
+
+#ifdef CONFIG_YAFFS_UNICODE
+#define YAFFS_MAX_NAME_LENGTH		127
+#define YAFFS_MAX_ALIAS_LENGTH		79
+#else
+#define YAFFS_MAX_NAME_LENGTH		255
+#define YAFFS_MAX_ALIAS_LENGTH		159
+#endif
+
+#define YAFFS_SHORT_NAME_LENGTH		15
+
+/* Some special object ids for pseudo objects */
+#define YAFFS_OBJECTID_ROOT		1
+#define YAFFS_OBJECTID_LOSTNFOUND	2
+#define YAFFS_OBJECTID_UNLINKED		3
+#define YAFFS_OBJECTID_DELETED		4
+
+/* Sseudo object ids for checkpointing */
+#define YAFFS_OBJECTID_SB_HEADER	0x10
+#define YAFFS_OBJECTID_CHECKPOINT_DATA	0x20
+#define YAFFS_SEQUENCE_CHECKPOINT_DATA  0x21
+
+/* */
+
+#define YAFFS_MAX_SHORT_OP_CACHES	20
+
+#define YAFFS_N_TEMP_BUFFERS		6
+
+/* We limit the number attempts at sucessfully saving a chunk of data.
+ * Small-page devices have 32 pages per block; large-page devices have 64.
+ * Default to something in the order of 5 to 10 blocks worth of chunks.
+ */
+#define YAFFS_WR_ATTEMPTS		(5*64)
+
+/* Sequence numbers are used in YAFFS2 to determine block allocation order.
+ * The range is limited slightly to help distinguish bad numbers from good.
+ * This also allows us to perhaps in the future use special numbers for
+ * special purposes.
+ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years,
+ * and is a larger number than the lifetime of a 2GB device.
+ */
+#define YAFFS_LOWEST_SEQUENCE_NUMBER	0x00001000
+#define YAFFS_HIGHEST_SEQUENCE_NUMBER	0xEFFFFF00
+
+/* Special sequence number for bad block that failed to be marked bad */
+#define YAFFS_SEQUENCE_BAD_BLOCK	0xFFFF0000
+
+/* ChunkCache is used for short read/write operations.*/
+typedef struct {
+	struct yaffs_ObjectStruct *object;
+	int chunkId;
+	int lastUse;
+	int dirty;
+	int nBytes;		/* Only valid if the cache is dirty */
+	int locked;		/* Can't push out or flush while locked. */
+#ifdef CONFIG_YAFFS_YAFFS2
+	__u8 *data;
+#else
+	__u8 data[YAFFS_BYTES_PER_CHUNK];
+#endif
+} yaffs_ChunkCache;
+
+
+
+/* Tags structures in RAM
+ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise
+ * the structure size will get blown out.
+ */
+
+#ifndef CONFIG_YAFFS_NO_YAFFS1
+typedef struct {
+	unsigned chunkId:20;
+	unsigned serialNumber:2;
+	unsigned byteCountLSB:10;
+	unsigned objectId:18;
+	unsigned ecc:12;
+	unsigned byteCountMSB:2;
+} yaffs_Tags;
+
+typedef union {
+	yaffs_Tags asTags;
+	__u8 asBytes[8];
+} yaffs_TagsUnion;
+
+#endif
+
+/* Stuff used for extended tags in YAFFS2 */
+
+typedef enum {
+	YAFFS_ECC_RESULT_UNKNOWN,
+	YAFFS_ECC_RESULT_NO_ERROR,
+	YAFFS_ECC_RESULT_FIXED,
+	YAFFS_ECC_RESULT_UNFIXED
+} yaffs_ECCResult;
+
+typedef enum {
+	YAFFS_OBJECT_TYPE_UNKNOWN,
+	YAFFS_OBJECT_TYPE_FILE,
+	YAFFS_OBJECT_TYPE_SYMLINK,
+	YAFFS_OBJECT_TYPE_DIRECTORY,
+	YAFFS_OBJECT_TYPE_HARDLINK,
+	YAFFS_OBJECT_TYPE_SPECIAL
+} yaffs_ObjectType;
+
+#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL
+
+typedef struct {
+
+	unsigned validMarker0;
+	unsigned chunkUsed;	/*  Status of the chunk: used or unused */
+	unsigned objectId;	/* If 0 then this is not part of an object (unused) */
+	unsigned chunkId;	/* If 0 then this is a header, else a data chunk */
+	unsigned byteCount;	/* Only valid for data chunks */
+
+	/* The following stuff only has meaning when we read */
+	yaffs_ECCResult eccResult;
+	unsigned blockBad;
+
+	/* YAFFS 1 stuff */
+	unsigned chunkDeleted;	/* The chunk is marked deleted */
+	unsigned serialNumber;	/* Yaffs1 2-bit serial number */
+
+	/* YAFFS2 stuff */
+	unsigned sequenceNumber;	/* The sequence number of this block */
+
+	/* Extra info if this is an object header (YAFFS2 only) */
+
+	unsigned extraHeaderInfoAvailable;	/* There is extra info available if this is not zero */
+	unsigned extraParentObjectId;	/* The parent object */
+	unsigned extraIsShrinkHeader;	/* Is it a shrink header? */
+	unsigned extraShadows;		/* Does this shadow another object? */
+
+	yaffs_ObjectType extraObjectType;	/* What object type? */
+
+	unsigned extraFileLength;		/* Length if it is a file */
+	unsigned extraEquivalentObjectId;	/* Equivalent object Id if it is a hard link */
+
+	unsigned validMarker1;
+
+} yaffs_ExtendedTags;
+
+/* Spare structure for YAFFS1 */
+typedef struct {
+	__u8 tagByte0;
+	__u8 tagByte1;
+	__u8 tagByte2;
+	__u8 tagByte3;
+	__u8 pageStatus;	/* set to 0 to delete the chunk */
+	__u8 blockStatus;
+	__u8 tagByte4;
+	__u8 tagByte5;
+	__u8 ecc1[3];
+	__u8 tagByte6;
+	__u8 tagByte7;
+	__u8 ecc2[3];
+} yaffs_Spare;
+
+/*Special structure for passing through to mtd */
+struct yaffs_NANDSpare {
+	yaffs_Spare spare;
+	int eccres1;
+	int eccres2;
+};
+
+/* Block data in RAM */
+
+typedef enum {
+	YAFFS_BLOCK_STATE_UNKNOWN = 0,
+
+	YAFFS_BLOCK_STATE_SCANNING,
+	YAFFS_BLOCK_STATE_NEEDS_SCANNING,
+	/* The block might have something on it (ie it is allocating or full, perhaps empty)
+	 * but it needs to be scanned to determine its true state.
+	 * This state is only valid during yaffs_Scan.
+	 * NB We tolerate empty because the pre-scanner might be incapable of deciding
+	 * However, if this state is returned on a YAFFS2 device, then we expect a sequence number
+	 */
+
+	YAFFS_BLOCK_STATE_EMPTY,
+	/* This block is empty */
+
+	YAFFS_BLOCK_STATE_ALLOCATING,
+	/* This block is partially allocated.
+	 * At least one page holds valid data.
+	 * This is the one currently being used for page
+	 * allocation. Should never be more than one of these
+	 */
+
+	YAFFS_BLOCK_STATE_FULL,
+	/* All the pages in this block have been allocated.
+	 */
+
+	YAFFS_BLOCK_STATE_DIRTY,
+	/* All pages have been allocated and deleted.
+	 * Erase me, reuse me.
+	 */
+
+	YAFFS_BLOCK_STATE_CHECKPOINT,
+	/* This block is assigned to holding checkpoint data.
+	 */
+
+	YAFFS_BLOCK_STATE_COLLECTING,
+	/* This block is being garbage collected */
+
+	YAFFS_BLOCK_STATE_DEAD
+	/* This block has failed and is not in use */
+} yaffs_BlockState;
+
+#define	YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1)
+
+
+typedef struct {
+
+	int softDeletions:10;	/* number of soft deleted pages */
+	int pagesInUse:10;	/* number of pages in use */
+	unsigned blockState:4;	/* One of the above block states. NB use unsigned because enum is sometimes an int */
+	__u32 needsRetiring:1;	/* Data has failed on this block, need to get valid data off */
+				/* and retire the block. */
+	__u32 skipErasedCheck:1; /* If this is set we can skip the erased check on this block */
+	__u32 gcPrioritise:1; 	/* An ECC check or blank check has failed on this block.
+				   It should be prioritised for GC */
+	__u32 chunkErrorStrikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */
+
+#ifdef CONFIG_YAFFS_YAFFS2
+	__u32 hasShrinkHeader:1; /* This block has at least one shrink object header */
+	__u32 sequenceNumber;	 /* block sequence number for yaffs2 */
+#endif
+
+} yaffs_BlockInfo;
+
+/* -------------------------- Object structure -------------------------------*/
+/* This is the object structure as stored on NAND */
+
+typedef struct {
+	yaffs_ObjectType type;
+
+	/* Apply to everything  */
+	int parentObjectId;
+	__u16 sum__NoLongerUsed;        /* checksum of name. No longer used */
+	YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
+
+	/* The following apply to directories, files, symlinks - not hard links */
+	__u32 yst_mode;         /* protection */
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 notForWinCE[5];
+#else
+	__u32 yst_uid;
+	__u32 yst_gid;
+	__u32 yst_atime;
+	__u32 yst_mtime;
+	__u32 yst_ctime;
+#endif
+
+	/* File size  applies to files only */
+	int fileSize;
+
+	/* Equivalent object id applies to hard links only. */
+	int equivalentObjectId;
+
+	/* Alias is for symlinks only. */
+	YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1];
+
+	__u32 yst_rdev;		/* device stuff for block and char devices (major/min) */
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 win_ctime[2];
+	__u32 win_atime[2];
+	__u32 win_mtime[2];
+#else
+	__u32 roomToGrow[6];
+
+#endif
+	__u32 inbandShadowsObject;
+	__u32 inbandIsShrink;
+
+	__u32 reservedSpace[2];
+	int shadowsObject;	/* This object header shadows the specified object if > 0 */
+
+	/* isShrink applies to object headers written when we shrink the file (ie resize) */
+	__u32 isShrink;
+
+} yaffs_ObjectHeader;
+
+/*--------------------------- Tnode -------------------------- */
+
+union yaffs_Tnode_union {
+#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
+	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL + 1];
+#else
+	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL];
+#endif
+/*	__u16 level0[YAFFS_NTNODES_LEVEL0]; */
+
+};
+
+typedef union yaffs_Tnode_union yaffs_Tnode;
+
+struct yaffs_TnodeList_struct {
+	struct yaffs_TnodeList_struct *next;
+	yaffs_Tnode *tnodes;
+};
+
+typedef struct yaffs_TnodeList_struct yaffs_TnodeList;
+
+/*------------------------  Object -----------------------------*/
+/* An object can be one of:
+ * - a directory (no data, has children links
+ * - a regular file (data.... not prunes :->).
+ * - a symlink [symbolic link] (the alias).
+ * - a hard link
+ */
+
+typedef struct {
+	__u32 fileSize;
+	__u32 scannedFileSize;
+	__u32 shrinkSize;
+	int topLevel;
+	yaffs_Tnode *top;
+} yaffs_FileStructure;
+
+typedef struct {
+	struct ylist_head children;     /* list of child links */
+} yaffs_DirectoryStructure;
+
+typedef struct {
+	YCHAR *alias;
+} yaffs_SymLinkStructure;
+
+typedef struct {
+	struct yaffs_ObjectStruct *equivalentObject;
+	__u32 equivalentObjectId;
+} yaffs_HardLinkStructure;
+
+typedef union {
+	yaffs_FileStructure fileVariant;
+	yaffs_DirectoryStructure directoryVariant;
+	yaffs_SymLinkStructure symLinkVariant;
+	yaffs_HardLinkStructure hardLinkVariant;
+} yaffs_ObjectVariant;
+
+struct yaffs_ObjectStruct {
+	__u8 deleted:1;		/* This should only apply to unlinked files. */
+	__u8 softDeleted:1;	/* it has also been soft deleted */
+	__u8 unlinked:1;	/* An unlinked file. The file should be in the unlinked directory.*/
+	__u8 fake:1;		/* A fake object has no presence on NAND. */
+	__u8 renameAllowed:1;	/* Some objects are not allowed to be renamed. */
+	__u8 unlinkAllowed:1;
+	__u8 dirty:1;		/* the object needs to be written to flash */
+	__u8 valid:1;		/* When the file system is being loaded up, this
+				 * object might be created before the data
+				 * is available (ie. file data records appear before the header).
+				 */
+	__u8 lazyLoaded:1;	/* This object has been lazy loaded and is missing some detail */
+
+	__u8 deferedFree:1;	/* For Linux kernel. Object is removed from NAND, but is
+				 * still in the inode cache. Free of object is defered.
+				 * until the inode is released.
+				 */
+	__u8 beingCreated:1;	/* This object is still being created so skip some checks. */
+	__u8 isShadowed:1;      /* This object is shadowed on the way to being renamed. */
+
+	__u8 serial;		/* serial number of chunk in NAND. Cached here */
+	__u16 sum;		/* sum of the name to speed searching */
+
+	struct yaffs_DeviceStruct *myDev;       /* The device I'm on */
+
+	struct ylist_head hashLink;     /* list of objects in this hash bucket */
+
+	struct ylist_head hardLinks;    /* all the equivalent hard linked objects */
+
+	/* directory structure stuff */
+	/* also used for linking up the free list */
+	struct yaffs_ObjectStruct *parent;
+	struct ylist_head siblings;
+
+	/* Where's my object header in NAND? */
+	int hdrChunk;
+
+	int nDataChunks;	/* Number of data chunks attached to the file. */
+
+	__u32 objectId;		/* the object id value */
+
+	__u32 yst_mode;
+
+#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
+	YCHAR shortName[YAFFS_SHORT_NAME_LENGTH + 1];
+#endif
+
+#ifndef __KERNEL__
+	__u32 inUse;
+#endif
+
+#ifdef CONFIG_YAFFS_WINCE
+	__u32 win_ctime[2];
+	__u32 win_mtime[2];
+	__u32 win_atime[2];
+#else
+	__u32 yst_uid;
+	__u32 yst_gid;
+	__u32 yst_atime;
+	__u32 yst_mtime;
+	__u32 yst_ctime;
+#endif
+
+	__u32 yst_rdev;
+
+#ifdef __KERNEL__
+	struct inode *myInode;
+
+#endif
+
+	yaffs_ObjectType variantType;
+
+	yaffs_ObjectVariant variant;
+
+};
+
+typedef struct yaffs_ObjectStruct yaffs_Object;
+
+struct yaffs_ObjectList_struct {
+	yaffs_Object *objects;
+	struct yaffs_ObjectList_struct *next;
+};
+
+typedef struct yaffs_ObjectList_struct yaffs_ObjectList;
+
+typedef struct {
+	struct ylist_head list;
+	int count;
+} yaffs_ObjectBucket;
+
+
+/* yaffs_CheckpointObject holds the definition of an object as dumped
+ * by checkpointing.
+ */
+
+typedef struct {
+	int structType;
+	__u32 objectId;
+	__u32 parentId;
+	int hdrChunk;
+	yaffs_ObjectType variantType:3;
+	__u8 deleted:1;
+	__u8 softDeleted:1;
+	__u8 unlinked:1;
+	__u8 fake:1;
+	__u8 renameAllowed:1;
+	__u8 unlinkAllowed:1;
+	__u8 serial;
+
+	int nDataChunks;
+	__u32 fileSizeOrEquivalentObjectId;
+} yaffs_CheckpointObject;
+
+/*--------------------- Temporary buffers ----------------
+ *
+ * These are chunk-sized working buffers. Each device has a few
+ */
+
+typedef struct {
+	__u8 *buffer;
+	int line;	/* track from whence this buffer was allocated */
+	int maxLine;
+} yaffs_TempBuffer;
+
+/*----------------- Device ---------------------------------*/
+
+struct yaffs_DeviceStruct {
+	struct ylist_head devList;
+	const char *name;
+
+	/* Entry parameters set up way early. Yaffs sets up the rest.*/
+	int nDataBytesPerChunk;	/* Should be a power of 2 >= 512 */
+	int nChunksPerBlock;	/* does not need to be a power of 2 */
+	int spareBytesPerChunk;	/* spare area size */
+	int startBlock;		/* Start block we're allowed to use */
+	int endBlock;		/* End block we're allowed to use */
+	int nReservedBlocks;	/* We want this tuneable so that we can reduce */
+				/* reserved blocks on NOR and RAM. */
+
+
+	/* Stuff used by the shared space checkpointing mechanism */
+	/* If this value is zero, then this mechanism is disabled */
+
+/*	int nCheckpointReservedBlocks; */ /* Blocks to reserve for checkpoint data */
+
+
+	int nShortOpCaches;	/* If <= 0, then short op caching is disabled, else
+				 * the number of short op caches (don't use too many)
+				 */
+
+	int useHeaderFileSize;	/* Flag to determine if we should use file sizes from the header */
+
+	int emptyLostAndFound;  /* Flasg to determine if lst+found should be emptied on init */
+
+	int useNANDECC;		/* Flag to decide whether or not to use NANDECC */
+
+	void *genericDevice;	/* Pointer to device context
+				 * On an mtd this holds the mtd pointer.
+				 */
+	void *superBlock;
+
+	/* NAND access functions (Must be set before calling YAFFS)*/
+
+	int (*writeChunkToNAND) (struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, const __u8 *data,
+					const yaffs_Spare *spare);
+	int (*readChunkFromNAND) (struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, __u8 *data,
+					yaffs_Spare *spare);
+	int (*eraseBlockInNAND) (struct yaffs_DeviceStruct *dev,
+					int blockInNAND);
+	int (*initialiseNAND) (struct yaffs_DeviceStruct *dev);
+	int (*deinitialiseNAND) (struct yaffs_DeviceStruct *dev);
+
+#ifdef CONFIG_YAFFS_YAFFS2
+	int (*writeChunkWithTagsToNAND) (struct yaffs_DeviceStruct *dev,
+					 int chunkInNAND, const __u8 *data,
+					 const yaffs_ExtendedTags *tags);
+	int (*readChunkWithTagsFromNAND) (struct yaffs_DeviceStruct *dev,
+					  int chunkInNAND, __u8 *data,
+					  yaffs_ExtendedTags *tags);
+	int (*markNANDBlockBad) (struct yaffs_DeviceStruct *dev, int blockNo);
+	int (*queryNANDBlock) (struct yaffs_DeviceStruct *dev, int blockNo,
+			       yaffs_BlockState *state, __u32 *sequenceNumber);
+#endif
+
+	int isYaffs2;
+
+	/* The removeObjectCallback function must be supplied by OS flavours that
+	 * need it.
+         * yaffs direct uses it to implement the faster readdir.
+         * Linux uses it to protect the directory during unlocking.
+	 */
+	void (*removeObjectCallback)(struct yaffs_ObjectStruct *obj);
+
+	/* Callback to mark the superblock dirsty */
+	void (*markSuperBlockDirty)(void *superblock);
+
+	int wideTnodesDisabled; /* Set to disable wide tnodes */
+
+	YCHAR *pathDividers;	/* String of legal path dividers */
+
+
+	/* End of stuff that must be set before initialisation. */
+
+	/* Checkpoint control. Can be set before or after initialisation */
+	__u8 skipCheckpointRead;
+	__u8 skipCheckpointWrite;
+
+	/* Runtime parameters. Set up by YAFFS. */
+
+	__u16 chunkGroupBits;	/* 0 for devices <= 32MB. else log2(nchunks) - 16 */
+	__u16 chunkGroupSize;	/* == 2^^chunkGroupBits */
+
+	/* Stuff to support wide tnodes */
+	__u32 tnodeWidth;
+	__u32 tnodeMask;
+
+	/* Stuff for figuring out file offset to chunk conversions */
+	__u32 chunkShift; /* Shift value */
+	__u32 chunkDiv;   /* Divisor after shifting: 1 for power-of-2 sizes */
+	__u32 chunkMask;  /* Mask to use for power-of-2 case */
+
+	/* Stuff to handle inband tags */
+	int inbandTags;
+	__u32 totalBytesPerChunk;
+
+#ifdef __KERNEL__
+
+	struct semaphore sem;	/* Semaphore for waiting on erasure.*/
+	struct semaphore grossLock;	/* Gross locking semaphore */
+	struct rw_semaphore dirLock; /* Lock the directory structure */
+	__u8 *spareBuffer;	/* For mtdif2 use. Don't know the size of the buffer
+				 * at compile time so we have to allocate it.
+
+				 */
+	void (*putSuperFunc) (struct super_block *sb);
+        struct ylist_head searchContexts;
+
+#endif
+
+	int isMounted;
+
+	int isCheckpointed;
+
+
+	/* Stuff to support block offsetting to support start block zero */
+	int internalStartBlock;
+	int internalEndBlock;
+	int blockOffset;
+	int chunkOffset;
+
+
+	/* Runtime checkpointing stuff */
+	int checkpointPageSequence;   /* running sequence number of checkpoint pages */
+	int checkpointByteCount;
+	int checkpointByteOffset;
+	__u8 *checkpointBuffer;
+	int checkpointOpenForWrite;
+	int blocksInCheckpoint;
+	int checkpointCurrentChunk;
+	int checkpointCurrentBlock;
+	int checkpointNextBlock;
+	int *checkpointBlockList;
+	int checkpointMaxBlocks;
+	__u32 checkpointSum;
+	__u32 checkpointXor;
+
+	int nCheckpointBlocksRequired; /* Number of blocks needed to store current checkpoint set */
+
+	/* Block Info */
+	yaffs_BlockInfo *blockInfo;
+	__u8 *chunkBits;	/* bitmap of chunks in use */
+	unsigned blockInfoAlt:1;	/* was allocated using alternative strategy */
+	unsigned chunkBitsAlt:1;	/* was allocated using alternative strategy */
+	int chunkBitmapStride;	/* Number of bytes of chunkBits per block.
+				 * Must be consistent with nChunksPerBlock.
+				 */
+
+	int nErasedBlocks;
+	int allocationBlock;	/* Current block being allocated off */
+	__u32 allocationPage;
+	int allocationBlockFinder;	/* Used to search for next allocation block */
+
+	/* Runtime state */
+	int nTnodesCreated;
+	yaffs_Tnode *freeTnodes;
+	int nFreeTnodes;
+	yaffs_TnodeList *allocatedTnodeList;
+
+	int isDoingGC;
+	int gcBlock;
+	int gcChunk;
+
+	int nObjectsCreated;
+	yaffs_Object *freeObjects;
+	int nFreeObjects;
+
+	int nHardLinks;
+
+	yaffs_ObjectList *allocatedObjectList;
+
+	yaffs_ObjectBucket objectBucket[YAFFS_NOBJECT_BUCKETS];
+
+	int nFreeChunks;
+
+	int currentDirtyChecker;	/* Used to find current dirtiest block */
+
+	__u32 *gcCleanupList;	/* objects to delete at the end of a GC. */
+	int nonAggressiveSkip;	/* GC state/mode */
+
+	/* Statistcs */
+	int nPageWrites;
+	int nPageReads;
+	int nBlockErasures;
+	int nErasureFailures;
+	int nGCCopies;
+	int garbageCollections;
+	int passiveGarbageCollections;
+	int nRetriedWrites;
+	int nRetiredBlocks;
+	int eccFixed;
+	int eccUnfixed;
+	int tagsEccFixed;
+	int tagsEccUnfixed;
+	int nDeletions;
+	int nUnmarkedDeletions;
+
+	int hasPendingPrioritisedGCs; /* We think this device might have pending prioritised gcs */
+
+	/* Special directories */
+	yaffs_Object *rootDir;
+	yaffs_Object *lostNFoundDir;
+
+	/* Buffer areas for storing data to recover from write failures TODO
+	 *      __u8            bufferedData[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK];
+	 *      yaffs_Spare bufferedSpare[YAFFS_CHUNKS_PER_BLOCK];
+	 */
+
+	int bufferedBlock;	/* Which block is buffered here? */
+	int doingBufferedBlockRewrite;
+
+	yaffs_ChunkCache *srCache;
+	int srLastUse;
+
+	int cacheHits;
+
+	/* Stuff for background deletion and unlinked files.*/
+	yaffs_Object *unlinkedDir;	/* Directory where unlinked and deleted files live. */
+	yaffs_Object *deletedDir;	/* Directory where deleted objects are sent to disappear. */
+	yaffs_Object *unlinkedDeletion;	/* Current file being background deleted.*/
+	int nDeletedFiles;		/* Count of files awaiting deletion;*/
+	int nUnlinkedFiles;		/* Count of unlinked files. */
+	int nBackgroundDeletions;	/* Count of background deletions. */
+
+
+	/* Temporary buffer management */
+	yaffs_TempBuffer tempBuffer[YAFFS_N_TEMP_BUFFERS];
+	int maxTemp;
+	int tempInUse;
+	int unmanagedTempAllocations;
+	int unmanagedTempDeallocations;
+
+	/* yaffs2 runtime stuff */
+	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
+	unsigned oldestDirtySequence;
+
+};
+
+typedef struct yaffs_DeviceStruct yaffs_Device;
+
+/* The static layout of block usage etc is stored in the super block header */
+typedef struct {
+	int StructType;
+	int version;
+	int checkpointStartBlock;
+	int checkpointEndBlock;
+	int startBlock;
+	int endBlock;
+	int rfu[100];
+} yaffs_SuperBlockHeader;
+
+/* The CheckpointDevice structure holds the device information that changes at runtime and
+ * must be preserved over unmount/mount cycles.
+ */
+typedef struct {
+	int structType;
+	int nErasedBlocks;
+	int allocationBlock;	/* Current block being allocated off */
+	__u32 allocationPage;
+	int nFreeChunks;
+
+	int nDeletedFiles;		/* Count of files awaiting deletion;*/
+	int nUnlinkedFiles;		/* Count of unlinked files. */
+	int nBackgroundDeletions;	/* Count of background deletions. */
+
+	/* yaffs2 runtime stuff */
+	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
+	unsigned oldestDirtySequence;
+
+} yaffs_CheckpointDevice;
+
+
+typedef struct {
+	int structType;
+	__u32 magic;
+	__u32 version;
+	__u32 head;
+} yaffs_CheckpointValidity;
+
+
+/*----------------------- YAFFS Functions -----------------------*/
+
+int yaffs_GutsInitialise(yaffs_Device *dev);
+void yaffs_Deinitialise(yaffs_Device *dev);
+
+int yaffs_GetNumberOfFreeChunks(yaffs_Device *dev);
+
+int yaffs_RenameObject(yaffs_Object *oldDir, const YCHAR *oldName,
+		       yaffs_Object *newDir, const YCHAR *newName);
+
+int yaffs_Unlink(yaffs_Object *dir, const YCHAR *name);
+int yaffs_DeleteObject(yaffs_Object *obj);
+
+int yaffs_GetObjectName(yaffs_Object *obj, YCHAR *name, int buffSize);
+int yaffs_GetObjectFileLength(yaffs_Object *obj);
+int yaffs_GetObjectInode(yaffs_Object *obj);
+unsigned yaffs_GetObjectType(yaffs_Object *obj);
+int yaffs_GetObjectLinkCount(yaffs_Object *obj);
+
+int yaffs_SetAttributes(yaffs_Object *obj, struct iattr *attr);
+int yaffs_GetAttributes(yaffs_Object *obj, struct iattr *attr);
+
+/* File operations */
+int yaffs_ReadDataFromFile(yaffs_Object *obj, __u8 *buffer, loff_t offset,
+				int nBytes);
+int yaffs_WriteDataToFile(yaffs_Object *obj, const __u8 *buffer, loff_t offset,
+				int nBytes, int writeThrough);
+int yaffs_ResizeFile(yaffs_Object *obj, loff_t newSize);
+
+yaffs_Object *yaffs_MknodFile(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid);
+int yaffs_FlushFile(yaffs_Object *obj, int updateTime);
+
+/* Flushing and checkpointing */
+void yaffs_FlushEntireDeviceCache(yaffs_Device *dev);
+
+int yaffs_CheckpointSave(yaffs_Device *dev);
+int yaffs_CheckpointRestore(yaffs_Device *dev);
+
+/* Directory operations */
+yaffs_Object *yaffs_MknodDirectory(yaffs_Object *parent, const YCHAR *name,
+				__u32 mode, __u32 uid, __u32 gid);
+yaffs_Object *yaffs_FindObjectByName(yaffs_Object *theDir, const YCHAR *name);
+int yaffs_ApplyToDirectoryChildren(yaffs_Object *theDir,
+				   int (*fn) (yaffs_Object *));
+
+yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device *dev, __u32 number);
+
+/* Link operations */
+yaffs_Object *yaffs_Link(yaffs_Object *parent, const YCHAR *name,
+			 yaffs_Object *equivalentObject);
+
+yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object *obj);
+
+/* Symlink operations */
+yaffs_Object *yaffs_MknodSymLink(yaffs_Object *parent, const YCHAR *name,
+				 __u32 mode, __u32 uid, __u32 gid,
+				 const YCHAR *alias);
+YCHAR *yaffs_GetSymlinkAlias(yaffs_Object *obj);
+
+/* Special inodes (fifos, sockets and devices) */
+yaffs_Object *yaffs_MknodSpecial(yaffs_Object *parent, const YCHAR *name,
+				 __u32 mode, __u32 uid, __u32 gid, __u32 rdev);
+
+/* Special directories */
+yaffs_Object *yaffs_Root(yaffs_Device *dev);
+yaffs_Object *yaffs_LostNFound(yaffs_Device *dev);
+
+#ifdef CONFIG_YAFFS_WINCE
+/* CONFIG_YAFFS_WINCE special stuff */
+void yfsd_WinFileTimeNow(__u32 target[2]);
+#endif
+
+#ifdef __KERNEL__
+
+void yaffs_HandleDeferedFree(yaffs_Object *obj);
+#endif
+
+/* Debug dump  */
+int yaffs_DumpObject(yaffs_Object *obj);
+
+void yaffs_GutsTest(yaffs_Device *dev);
+
+/* A few useful functions */
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags);
+void yaffs_DeleteChunk(yaffs_Device *dev, int chunkId, int markNAND, int lyn);
+int yaffs_CheckFF(__u8 *buffer, int nBytes);
+void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi);
+
+__u8 *yaffs_GetTempBuffer(yaffs_Device *dev, int lineNo);
+void yaffs_ReleaseTempBuffer(yaffs_Device *dev, __u8 *buffer, int lineNo);
+
+#endif
diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
new file mode 100644
index 00000000000..72f64203f31
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif.c
@@ -0,0 +1,241 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_mtdif_c_version =
+	"$Id$";
+
+#include "yportenv.h"
+
+
+#include "yaffs_mtdif.h"
+
+#include "linux/mtd/mtd.h"
+#include "linux/types.h"
+#include "linux/time.h"
+#include "linux/mtd/nand.h"
+
+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 18))
+static struct nand_oobinfo yaffs_oobinfo = {
+	.useecc = 1,
+	.eccbytes = 6,
+	.eccpos = {8, 9, 10, 13, 14, 15}
+};
+
+static struct nand_oobinfo yaffs_noeccinfo = {
+	.useecc = 0,
+};
+#endif
+
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+static inline void translate_spare2oob(const yaffs_Spare *spare, __u8 *oob)
+{
+	oob[0] = spare->tagByte0;
+	oob[1] = spare->tagByte1;
+	oob[2] = spare->tagByte2;
+	oob[3] = spare->tagByte3;
+	oob[4] = spare->tagByte4;
+	oob[5] = spare->tagByte5 & 0x3f;
+	oob[5] |= spare->blockStatus == 'Y' ? 0 : 0x80;
+	oob[5] |= spare->pageStatus == 0 ? 0 : 0x40;
+	oob[6] = spare->tagByte6;
+	oob[7] = spare->tagByte7;
+}
+
+static inline void translate_oob2spare(yaffs_Spare *spare, __u8 *oob)
+{
+	struct yaffs_NANDSpare *nspare = (struct yaffs_NANDSpare *)spare;
+	spare->tagByte0 = oob[0];
+	spare->tagByte1 = oob[1];
+	spare->tagByte2 = oob[2];
+	spare->tagByte3 = oob[3];
+	spare->tagByte4 = oob[4];
+	spare->tagByte5 = oob[5] == 0xff ? 0xff : oob[5] & 0x3f;
+	spare->blockStatus = oob[5] & 0x80 ? 0xff : 'Y';
+	spare->pageStatus = oob[5] & 0x40 ? 0xff : 0;
+	spare->ecc1[0] = spare->ecc1[1] = spare->ecc1[2] = 0xff;
+	spare->tagByte6 = oob[6];
+	spare->tagByte7 = oob[7];
+	spare->ecc2[0] = spare->ecc2[1] = spare->ecc2[2] = 0xff;
+
+	nspare->eccres1 = nspare->eccres2 = 0; /* FIXME */
+}
+#endif
+
+int nandmtd_WriteChunkToNAND(yaffs_Device *dev, int chunkInNAND,
+			     const __u8 *data, const yaffs_Spare *spare)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#endif
+	size_t dummy;
+	int retval = 0;
+
+	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	__u8 spareAsBytes[8]; /* OOB */
+
+	if (data && !spare)
+		retval = mtd->write(mtd, addr, dev->nDataBytesPerChunk,
+				&dummy, data);
+	else if (spare) {
+		if (dev->useNANDECC) {
+			translate_spare2oob(spare, spareAsBytes);
+			ops.mode = MTD_OOB_AUTO;
+			ops.ooblen = 8; /* temp hack */
+		} else {
+			ops.mode = MTD_OOB_RAW;
+			ops.ooblen = YAFFS_BYTES_PER_SPARE;
+		}
+		ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
+		ops.datbuf = (u8 *)data;
+		ops.ooboffs = 0;
+		ops.oobbuf = spareAsBytes;
+		retval = mtd->write_oob(mtd, addr, &ops);
+	}
+#else
+	__u8 *spareAsBytes = (__u8 *) spare;
+
+	if (data && spare) {
+		if (dev->useNANDECC)
+			retval =
+			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					   &dummy, data, spareAsBytes,
+					   &yaffs_oobinfo);
+		else
+			retval =
+			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					   &dummy, data, spareAsBytes,
+					   &yaffs_noeccinfo);
+	} else {
+		if (data)
+			retval =
+			    mtd->write(mtd, addr, dev->nDataBytesPerChunk, &dummy,
+				       data);
+		if (spare)
+			retval =
+			    mtd->write_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
+					   &dummy, spareAsBytes);
+	}
+#endif
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd_ReadChunkFromNAND(yaffs_Device *dev, int chunkInNAND, __u8 *data,
+			      yaffs_Spare *spare)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#endif
+	size_t dummy;
+	int retval = 0;
+
+	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	__u8 spareAsBytes[8]; /* OOB */
+
+	if (data && !spare)
+		retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk,
+				&dummy, data);
+	else if (spare) {
+		if (dev->useNANDECC) {
+			ops.mode = MTD_OOB_AUTO;
+			ops.ooblen = 8; /* temp hack */
+		} else {
+			ops.mode = MTD_OOB_RAW;
+			ops.ooblen = YAFFS_BYTES_PER_SPARE;
+		}
+		ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
+		ops.datbuf = data;
+		ops.ooboffs = 0;
+		ops.oobbuf = spareAsBytes;
+		retval = mtd->read_oob(mtd, addr, &ops);
+		if (dev->useNANDECC)
+			translate_oob2spare(spare, spareAsBytes);
+	}
+#else
+	__u8 *spareAsBytes = (__u8 *) spare;
+
+	if (data && spare) {
+		if (dev->useNANDECC) {
+			/* Careful, this call adds 2 ints */
+			/* to the end of the spare data.  Calling function */
+			/* should allocate enough memory for spare, */
+			/* i.e. [YAFFS_BYTES_PER_SPARE+2*sizeof(int)]. */
+			retval =
+			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					  &dummy, data, spareAsBytes,
+					  &yaffs_oobinfo);
+		} else {
+			retval =
+			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					  &dummy, data, spareAsBytes,
+					  &yaffs_noeccinfo);
+		}
+	} else {
+		if (data)
+			retval =
+			    mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
+				      data);
+		if (spare)
+			retval =
+			    mtd->read_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
+					  &dummy, spareAsBytes);
+	}
+#endif
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd_EraseBlockInNAND(yaffs_Device *dev, int blockNumber)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	__u32 addr =
+	    ((loff_t) blockNumber) * dev->nDataBytesPerChunk
+		* dev->nChunksPerBlock;
+	struct erase_info ei;
+	int retval = 0;
+
+	ei.mtd = mtd;
+	ei.addr = addr;
+	ei.len = dev->nDataBytesPerChunk * dev->nChunksPerBlock;
+	ei.time = 1000;
+	ei.retries = 2;
+	ei.callback = NULL;
+	ei.priv = (u_long) dev;
+
+	/* Todo finish off the ei if required */
+
+	sema_init(&dev->sem, 0);
+
+	retval = mtd->erase(mtd, &ei);
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd_InitialiseNAND(yaffs_Device *dev)
+{
+	return YAFFS_OK;
+}
+
diff --git a/fs/yaffs2/yaffs_mtdif.h b/fs/yaffs2/yaffs_mtdif.h
new file mode 100644
index 00000000000..e72cfcddfe9
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif.h
@@ -0,0 +1,32 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF_H__
+#define __YAFFS_MTDIF_H__
+
+#include "yaffs_guts.h"
+
+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 18))
+extern struct nand_oobinfo yaffs_oobinfo;
+extern struct nand_oobinfo yaffs_noeccinfo;
+#endif
+
+int nandmtd_WriteChunkToNAND(yaffs_Device *dev, int chunkInNAND,
+			const __u8 *data, const yaffs_Spare *spare);
+int nandmtd_ReadChunkFromNAND(yaffs_Device *dev, int chunkInNAND, __u8 *data,
+			yaffs_Spare *spare);
+int nandmtd_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
+int nandmtd_InitialiseNAND(yaffs_Device *dev);
+#endif
diff --git a/fs/yaffs2/yaffs_mtdif1.c b/fs/yaffs2/yaffs_mtdif1.c
new file mode 100644
index 00000000000..bcac47025ec
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif1.c
@@ -0,0 +1,361 @@
+/*
+ * YAFFS: Yet another FFS. A NAND-flash specific file system.
+ * yaffs_mtdif1.c  NAND mtd interface functions for small-page NAND.
+ *
+ * Copyright (C) 2002 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This module provides the interface between yaffs_nand.c and the
+ * MTD API.  This version is used when the MTD interface supports the
+ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17,
+ * and we have small-page NAND device.
+ *
+ * These functions are invoked via function pointers in yaffs_nand.c.
+ * This replaces functionality provided by functions in yaffs_mtdif.c
+ * and the yaffs_TagsCompatability functions in yaffs_tagscompat.c that are
+ * called in yaffs_mtdif.c when the function pointers are NULL.
+ * We assume the MTD layer is performing ECC (useNANDECC is true).
+ */
+
+#include "yportenv.h"
+#include "yaffs_guts.h"
+#include "yaffs_packedtags1.h"
+#include "yaffs_tagscompat.h"	/* for yaffs_CalcTagsECC */
+
+#include "linux/kernel.h"
+#include "linux/version.h"
+#include "linux/types.h"
+#include "linux/mtd/mtd.h"
+
+/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+
+const char *yaffs_mtdif1_c_version = "$Id$";
+
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+# define YTAG1_SIZE 8
+#else
+# define YTAG1_SIZE 9
+#endif
+
+#if 0
+/* Use the following nand_ecclayout with MTD when using
+ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout.
+ * If you have existing Yaffs images and the byte order differs from this,
+ * adjust 'oobfree' to match your existing Yaffs data.
+ *
+ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the
+ * pageStatus byte (at NAND spare offset 4) scattered/gathered from/to
+ * the 9th byte.
+ *
+ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5
+ * We have/need PackedTags1 plus pageStatus: T0,T1,T2,T3,T4,T5,T6,T7,P
+ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the pageStatus
+ * byte and B is the small-page bad-block indicator byte.
+ */
+static struct nand_ecclayout nand_oob_16 = {
+	.eccbytes = 6,
+	.eccpos = { 8, 9, 10, 13, 14, 15 },
+	.oobavail = 9,
+	.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+#endif
+
+/* Write a chunk (page) of data to NAND.
+ *
+ * Caller always provides ExtendedTags data which are converted to a more
+ * compact (packed) form for storage in NAND.  A mini-ECC runs over the
+ * contents of the tags meta-data; used to valid the tags when read.
+ *
+ *  - Pack ExtendedTags to PackedTags1 form
+ *  - Compute mini-ECC for PackedTags1
+ *  - Write data and packed tags to NAND.
+ *
+ * Note: Due to the use of the PackedTags1 meta-data which does not include
+ * a full sequence number (as found in the larger PackedTags2 form) it is
+ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as
+ * discarded and dirty.  This is not ideal: newer NAND parts are supposed
+ * to be written just once.  When Yaffs performs this operation, this
+ * function is called with a NULL data pointer -- calling MTD write_oob
+ * without data is valid usage (2.6.17).
+ *
+ * Any underlying MTD error results in YAFFS_FAIL.
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+	int chunkInNAND, const __u8 *data, const yaffs_ExtendedTags *etags)
+{
+	struct mtd_info *mtd = dev->genericDevice;
+	int chunkBytes = dev->nDataBytesPerChunk;
+	loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
+	struct mtd_oob_ops ops;
+	yaffs_PackedTags1 pt1;
+	int retval;
+
+	/* we assume that PackedTags1 and yaffs_Tags are compatible */
+	compile_time_assertion(sizeof(yaffs_PackedTags1) == 12);
+	compile_time_assertion(sizeof(yaffs_Tags) == 8);
+
+	yaffs_PackTags1(&pt1, etags);
+	yaffs_CalcTagsECC((yaffs_Tags *)&pt1);
+
+	/* When deleting a chunk, the upper layer provides only skeletal
+	 * etags, one with chunkDeleted set.  However, we need to update the
+	 * tags, not erase them completely.  So we use the NAND write property
+	 * that only zeroed-bits stick and set tag bytes to all-ones and
+	 * zero just the (not) deleted bit.
+	 */
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+	if (etags->chunkDeleted) {
+		memset(&pt1, 0xff, 8);
+		/* clear delete status bit to indicate deleted */
+		pt1.deleted = 0;
+	}
+#else
+	((__u8 *)&pt1)[8] = 0xff;
+	if (etags->chunkDeleted) {
+		memset(&pt1, 0xff, 8);
+		/* zero pageStatus byte to indicate deleted */
+		((__u8 *)&pt1)[8] = 0;
+	}
+#endif
+
+	memset(&ops, 0, sizeof(ops));
+	ops.mode = MTD_OOB_AUTO;
+	ops.len = (data) ? chunkBytes : 0;
+	ops.ooblen = YTAG1_SIZE;
+	ops.datbuf = (__u8 *)data;
+	ops.oobbuf = (__u8 *)&pt1;
+
+	retval = mtd->write_oob(mtd, addr, &ops);
+	if (retval) {
+		yaffs_trace(YAFFS_TRACE_MTD,
+			"write_oob failed, chunk %d, mtd error %d\n",
+			chunkInNAND, retval);
+	}
+	return retval ? YAFFS_FAIL : YAFFS_OK;
+}
+
+/* Return with empty ExtendedTags but add eccResult.
+ */
+static int rettags(yaffs_ExtendedTags *etags, int eccResult, int retval)
+{
+	if (etags) {
+		memset(etags, 0, sizeof(*etags));
+		etags->eccResult = eccResult;
+	}
+	return retval;
+}
+
+/* Read a chunk (page) from NAND.
+ *
+ * Caller expects ExtendedTags data to be usable even on error; that is,
+ * all members except eccResult and blockBad are zeroed.
+ *
+ *  - Check ECC results for data (if applicable)
+ *  - Check for blank/erased block (return empty ExtendedTags if blank)
+ *  - Check the PackedTags1 mini-ECC (correct if necessary/possible)
+ *  - Convert PackedTags1 to ExtendedTags
+ *  - Update eccResult and blockBad members to refect state.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev,
+	int chunkInNAND, __u8 *data, yaffs_ExtendedTags *etags)
+{
+	struct mtd_info *mtd = dev->genericDevice;
+	int chunkBytes = dev->nDataBytesPerChunk;
+	loff_t addr = ((loff_t)chunkInNAND) * chunkBytes;
+	int eccres = YAFFS_ECC_RESULT_NO_ERROR;
+	struct mtd_oob_ops ops;
+	yaffs_PackedTags1 pt1;
+	int retval;
+	int deleted;
+
+	memset(&ops, 0, sizeof(ops));
+	ops.mode = MTD_OOB_AUTO;
+	ops.len = (data) ? chunkBytes : 0;
+	ops.ooblen = YTAG1_SIZE;
+	ops.datbuf = data;
+	ops.oobbuf = (__u8 *)&pt1;
+
+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20))
+	/* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug;
+	 * help it out with ops.len = ops.ooblen when ops.datbuf == NULL.
+	 */
+	ops.len = (ops.datbuf) ? ops.len : ops.ooblen;
+#endif
+	/* Read page and oob using MTD.
+	 * Check status and determine ECC result.
+	 */
+	retval = mtd->read_oob(mtd, addr, &ops);
+	if (retval) {
+		yaffs_trace(YAFFS_TRACE_MTD,
+			"read_oob failed, chunk %d, mtd error %d\n",
+			chunkInNAND, retval);
+	}
+
+	switch (retval) {
+	case 0:
+		/* no error */
+		break;
+
+	case -EUCLEAN:
+		/* MTD's ECC fixed the data */
+		eccres = YAFFS_ECC_RESULT_FIXED;
+		dev->eccFixed++;
+		break;
+
+	case -EBADMSG:
+		/* MTD's ECC could not fix the data */
+		dev->eccUnfixed++;
+		/* fall into... */
+	default:
+		rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0);
+		etags->blockBad = (mtd->block_isbad)(mtd, addr);
+		return YAFFS_FAIL;
+	}
+
+	/* Check for a blank/erased chunk.
+	 */
+	if (yaffs_CheckFF((__u8 *)&pt1, 8)) {
+		/* when blank, upper layers want eccResult to be <= NO_ERROR */
+		return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK);
+	}
+
+#ifndef CONFIG_YAFFS_9BYTE_TAGS
+	/* Read deleted status (bit) then return it to it's non-deleted
+	 * state before performing tags mini-ECC check. pt1.deleted is
+	 * inverted.
+	 */
+	deleted = !pt1.deleted;
+	pt1.deleted = 1;
+#else
+	deleted = (yaffs_CountBits(((__u8 *)&pt1)[8]) < 7);
+#endif
+
+	/* Check the packed tags mini-ECC and correct if necessary/possible.
+	 */
+	retval = yaffs_CheckECCOnTags((yaffs_Tags *)&pt1);
+	switch (retval) {
+	case 0:
+		/* no tags error, use MTD result */
+		break;
+	case 1:
+		/* recovered tags-ECC error */
+		dev->tagsEccFixed++;
+		if (eccres == YAFFS_ECC_RESULT_NO_ERROR)
+			eccres = YAFFS_ECC_RESULT_FIXED;
+		break;
+	default:
+		/* unrecovered tags-ECC error */
+		dev->tagsEccUnfixed++;
+		return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL);
+	}
+
+	/* Unpack the tags to extended form and set ECC result.
+	 * [set shouldBeFF just to keep yaffs_UnpackTags1 happy]
+	 */
+	pt1.shouldBeFF = 0xFFFFFFFF;
+	yaffs_UnpackTags1(etags, &pt1);
+	etags->eccResult = eccres;
+
+	/* Set deleted state */
+	etags->chunkDeleted = deleted;
+	return YAFFS_OK;
+}
+
+/* Mark a block bad.
+ *
+ * This is a persistant state.
+ * Use of this function should be rare.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
+{
+	struct mtd_info *mtd = dev->genericDevice;
+	int blocksize = dev->nChunksPerBlock * dev->nDataBytesPerChunk;
+	int retval;
+
+	yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad\n", blockNo);
+
+	retval = mtd->block_markbad(mtd, (loff_t)blocksize * blockNo);
+	return (retval) ? YAFFS_FAIL : YAFFS_OK;
+}
+
+/* Check any MTD prerequists.
+ *
+ * Returns YAFFS_OK or YAFFS_FAIL.
+ */
+static int nandmtd1_TestPrerequists(struct mtd_info *mtd)
+{
+	/* 2.6.18 has mtd->ecclayout->oobavail */
+	/* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */
+	int oobavail = mtd->ecclayout->oobavail;
+
+	if (oobavail < YTAG1_SIZE) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"mtd device has only %d bytes for tags, need %d\n",
+			oobavail, YTAG1_SIZE);
+		return YAFFS_FAIL;
+	}
+	return YAFFS_OK;
+}
+
+/* Query for the current state of a specific block.
+ *
+ * Examine the tags of the first chunk of the block and return the state:
+ *  - YAFFS_BLOCK_STATE_DEAD, the block is marked bad
+ *  - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use
+ *  - YAFFS_BLOCK_STATE_EMPTY, the block is clean
+ *
+ * Always returns YAFFS_OK.
+ */
+int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+	yaffs_BlockState *pState, __u32 *pSequenceNumber)
+{
+	struct mtd_info *mtd = dev->genericDevice;
+	int chunkNo = blockNo * dev->nChunksPerBlock;
+	loff_t addr = (loff_t)chunkNo * dev->nDataBytesPerChunk;
+	yaffs_ExtendedTags etags;
+	int state = YAFFS_BLOCK_STATE_DEAD;
+	int seqnum = 0;
+	int retval;
+
+	/* We don't yet have a good place to test for MTD config prerequists.
+	 * Do it here as we are called during the initial scan.
+	 */
+	if (nandmtd1_TestPrerequists(mtd) != YAFFS_OK)
+		return YAFFS_FAIL;
+
+	retval = nandmtd1_ReadChunkWithTagsFromNAND(dev, chunkNo, NULL, &etags);
+	etags.blockBad = (mtd->block_isbad)(mtd, addr);
+	if (etags.blockBad) {
+		yaffs_trace(YAFFS_TRACE_BAD_BLOCKS,
+			"block %d is marked bad\n", blockNo);
+		state = YAFFS_BLOCK_STATE_DEAD;
+	} else if (etags.eccResult != YAFFS_ECC_RESULT_NO_ERROR) {
+		/* bad tags, need to look more closely */
+		state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+	} else if (etags.chunkUsed) {
+		state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		seqnum = etags.sequenceNumber;
+	} else {
+		state = YAFFS_BLOCK_STATE_EMPTY;
+	}
+
+	*pState = state;
+	*pSequenceNumber = seqnum;
+
+	/* query always succeeds */
+	return YAFFS_OK;
+}
+
+#endif /*MTD_VERSION*/
diff --git a/fs/yaffs2/yaffs_mtdif1.h b/fs/yaffs2/yaffs_mtdif1.h
new file mode 100644
index 00000000000..240202cdf7f
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif1.h
@@ -0,0 +1,28 @@
+/*
+ * YAFFS: Yet another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF1_H__
+#define __YAFFS_MTDIF1_H__
+
+int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+	const __u8 *data, const yaffs_ExtendedTags *tags);
+
+int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+	__u8 *data, yaffs_ExtendedTags *tags);
+
+int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+
+int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+	yaffs_BlockState *state, __u32 *sequenceNumber);
+
+#endif
diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
new file mode 100644
index 00000000000..282a093d854
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif2.c
@@ -0,0 +1,251 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* mtd interface for YAFFS2 */
+
+const char *yaffs_mtdif2_c_version =
+	"$Id$";
+
+#include "yportenv.h"
+
+
+#include "yaffs_mtdif2.h"
+
+#include "linux/mtd/mtd.h"
+#include "linux/types.h"
+#include "linux/time.h"
+
+#include "yaffs_packedtags2.h"
+
+/* NB For use with inband tags....
+ * We assume that the data buffer is of size totalBytersPerChunk so that we can also
+ * use it to load the tags.
+ */
+int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+				      const __u8 *data,
+				      const yaffs_ExtendedTags *tags)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#else
+	size_t dummy;
+#endif
+	int retval = 0;
+
+	loff_t addr;
+
+	yaffs_PackedTags2 pt;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p"
+	    TENDSTR), chunkInNAND, data, tags));
+
+	addr  = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk;
+
+	/* For yaffs2 writing there must be both data and tags.
+	 * If we're using inband tags, then the tags are stuffed into
+	 * the end of the data buffer.
+	 */
+	if (!data || !tags)
+		BUG();
+	else if (dev->inbandTags) {
+		yaffs_PackedTags2TagsPart *pt2tp;
+		pt2tp = (yaffs_PackedTags2TagsPart *)(data + dev->nDataBytesPerChunk);
+		yaffs_PackTags2TagsPart(pt2tp, tags);
+	} else
+		yaffs_PackTags2(&pt, tags);
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+	ops.mode = MTD_OOB_AUTO;
+	ops.ooblen = (dev->inbandTags) ? 0 : sizeof(pt);
+	ops.len = dev->totalBytesPerChunk;
+	ops.ooboffs = 0;
+	ops.datbuf = (__u8 *)data;
+	ops.oobbuf = (dev->inbandTags) ? NULL : (void *)&pt;
+	retval = mtd->write_oob(mtd, addr, &ops);
+
+#else
+	if (!dev->inbandTags) {
+		retval =
+		    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
+				   &dummy, data, (__u8 *) &pt, NULL);
+	} else {
+		retval =
+		    mtd->write(mtd, addr, dev->totalBytesPerChunk, &dummy,
+			       data);
+	}
+#endif
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+				       __u8 *data, yaffs_ExtendedTags *tags)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17))
+	struct mtd_oob_ops ops;
+#endif
+	size_t dummy;
+	int retval = 0;
+	int localData = 0;
+
+	loff_t addr = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk;
+
+	yaffs_PackedTags2 pt;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p"
+	    TENDSTR), chunkInNAND, data, tags));
+
+	if (dev->inbandTags) {
+
+		if (!data) {
+			localData = 1;
+			data = yaffs_GetTempBuffer(dev, __LINE__);
+		}
+
+
+	}
+
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17))
+	if (dev->inbandTags || (data && !tags))
+		retval = mtd->read(mtd, addr, dev->totalBytesPerChunk,
+				&dummy, data);
+	else if (tags) {
+		ops.mode = MTD_OOB_AUTO;
+		ops.ooblen = sizeof(pt);
+		ops.len = data ? dev->nDataBytesPerChunk : sizeof(pt);
+		ops.ooboffs = 0;
+		ops.datbuf = data;
+		ops.oobbuf = dev->spareBuffer;
+		retval = mtd->read_oob(mtd, addr, &ops);
+	}
+#else
+	if (!dev->inbandTags && data && tags) {
+
+		retval = mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
+					  &dummy, data, dev->spareBuffer,
+					  NULL);
+	} else {
+		if (data)
+			retval =
+			    mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
+				      data);
+		if (!dev->inbandTags && tags)
+			retval =
+			    mtd->read_oob(mtd, addr, mtd->oobsize, &dummy,
+					  dev->spareBuffer);
+	}
+#endif
+
+
+	if (dev->inbandTags) {
+		if (tags) {
+			yaffs_PackedTags2TagsPart *pt2tp;
+			pt2tp = (yaffs_PackedTags2TagsPart *)&data[dev->nDataBytesPerChunk];
+			yaffs_UnpackTags2TagsPart(tags, pt2tp);
+		}
+	} else {
+		if (tags) {
+			memcpy(&pt, dev->spareBuffer, sizeof(pt));
+			yaffs_UnpackTags2(tags, &pt);
+		}
+	}
+
+	if (localData)
+		yaffs_ReleaseTempBuffer(dev, data, __LINE__);
+
+	if (tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR) {
+		tags->eccResult = YAFFS_ECC_RESULT_UNFIXED;
+		dev->eccUnfixed++;
+	}
+	if (tags && retval == -EUCLEAN && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR) {
+		tags->eccResult = YAFFS_ECC_RESULT_FIXED;
+		dev->eccFixed++;
+	}
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
+int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	int retval;
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("nandmtd2_MarkNANDBlockBad %d" TENDSTR), blockNo));
+
+	retval =
+	    mtd->block_markbad(mtd,
+			       blockNo * dev->nChunksPerBlock *
+			       dev->totalBytesPerChunk);
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+
+}
+
+int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			    yaffs_BlockState *state, __u32 *sequenceNumber)
+{
+	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	int retval;
+
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("nandmtd2_QueryNANDBlock %d" TENDSTR), blockNo));
+	retval =
+	    mtd->block_isbad(mtd,
+			     blockNo * dev->nChunksPerBlock *
+			     dev->totalBytesPerChunk);
+
+	if (retval) {
+		T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR)));
+
+		*state = YAFFS_BLOCK_STATE_DEAD;
+		*sequenceNumber = 0;
+	} else {
+		yaffs_ExtendedTags t;
+		nandmtd2_ReadChunkWithTagsFromNAND(dev,
+						   blockNo *
+						   dev->nChunksPerBlock, NULL,
+						   &t);
+
+		if (t.chunkUsed) {
+			*sequenceNumber = t.sequenceNumber;
+			*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		} else {
+			*sequenceNumber = 0;
+			*state = YAFFS_BLOCK_STATE_EMPTY;
+		}
+	}
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("block is bad seq %d state %d" TENDSTR), *sequenceNumber,
+	   *state));
+
+	if (retval == 0)
+		return YAFFS_OK;
+	else
+		return YAFFS_FAIL;
+}
+
diff --git a/fs/yaffs2/yaffs_mtdif2.h b/fs/yaffs2/yaffs_mtdif2.h
new file mode 100644
index 00000000000..b5ff07881ff
--- /dev/null
+++ b/fs/yaffs2/yaffs_mtdif2.h
@@ -0,0 +1,29 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_MTDIF2_H__
+#define __YAFFS_MTDIF2_H__
+
+#include "yaffs_guts.h"
+int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device *dev, int chunkInNAND,
+				const __u8 *data,
+				const yaffs_ExtendedTags *tags);
+int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+				__u8 *data, yaffs_ExtendedTags *tags);
+int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			yaffs_BlockState *state, __u32 *sequenceNumber);
+
+#endif
diff --git a/fs/yaffs2/yaffs_nand.c b/fs/yaffs2/yaffs_nand.c
new file mode 100644
index 00000000000..f6ba4c794ac
--- /dev/null
+++ b/fs/yaffs2/yaffs_nand.c
@@ -0,0 +1,140 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+const char *yaffs_nand_c_version =
+	"$Id$";
+
+#include "yaffs_nand.h"
+#include "yaffs_tagscompat.h"
+#include "yaffs_tagsvalidity.h"
+
+#include "yaffs_getblockinfo.h"
+
+int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+					   __u8 *buffer,
+					   yaffs_ExtendedTags *tags)
+{
+	int result;
+	yaffs_ExtendedTags localTags;
+
+	int realignedChunkInNAND = chunkInNAND - dev->chunkOffset;
+
+	dev->nPageReads++;
+
+	/* If there are no tags provided, use local tags to get prioritised gc working */
+	if (!tags)
+		tags = &localTags;
+
+	if (dev->readChunkWithTagsFromNAND)
+		result = dev->readChunkWithTagsFromNAND(dev, realignedChunkInNAND, buffer,
+						      tags);
+	else
+		result = yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(dev,
+									realignedChunkInNAND,
+									buffer,
+									tags);
+	if (tags &&
+	   tags->eccResult > YAFFS_ECC_RESULT_NO_ERROR) {
+
+		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, chunkInNAND/dev->nChunksPerBlock);
+		yaffs_HandleChunkError(dev, bi);
+	}
+
+	return result;
+}
+
+int yaffs_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+						   int chunkInNAND,
+						   const __u8 *buffer,
+						   yaffs_ExtendedTags *tags)
+{
+
+	dev->nPageWrites++;
+
+	chunkInNAND -= dev->chunkOffset;
+
+
+	if (tags) {
+		tags->sequenceNumber = dev->sequenceNumber;
+		tags->chunkUsed = 1;
+		if (!yaffs_ValidateTags(tags)) {
+			T(YAFFS_TRACE_ERROR,
+			  (TSTR("Writing uninitialised tags" TENDSTR)));
+			YBUG();
+		}
+		T(YAFFS_TRACE_WRITE,
+		  (TSTR("Writing chunk %d tags %d %d" TENDSTR), chunkInNAND,
+		   tags->objectId, tags->chunkId));
+	} else {
+		T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR)));
+		YBUG();
+	}
+
+	if (dev->writeChunkWithTagsToNAND)
+		return dev->writeChunkWithTagsToNAND(dev, chunkInNAND, buffer,
+						     tags);
+	else
+		return yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(dev,
+								       chunkInNAND,
+								       buffer,
+								       tags);
+}
+
+int yaffs_MarkBlockBad(yaffs_Device *dev, int blockNo)
+{
+	blockNo -= dev->blockOffset;
+
+
+	if (dev->markNANDBlockBad)
+		return dev->markNANDBlockBad(dev, blockNo);
+	else
+		return yaffs_TagsCompatabilityMarkNANDBlockBad(dev, blockNo);
+}
+
+int yaffs_QueryInitialBlockState(yaffs_Device *dev,
+						 int blockNo,
+						 yaffs_BlockState *state,
+						 __u32 *sequenceNumber)
+{
+	blockNo -= dev->blockOffset;
+
+	if (dev->queryNANDBlock)
+		return dev->queryNANDBlock(dev, blockNo, state, sequenceNumber);
+	else
+		return yaffs_TagsCompatabilityQueryNANDBlock(dev, blockNo,
+							     state,
+							     sequenceNumber);
+}
+
+
+int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				  int blockInNAND)
+{
+	int result;
+
+	blockInNAND -= dev->blockOffset;
+
+	dev->nBlockErasures++;
+
+	result = dev->eraseBlockInNAND(dev, blockInNAND);
+
+	return result;
+}
+
+int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev)
+{
+	return dev->initialiseNAND(dev);
+}
+
+
+
diff --git a/fs/yaffs2/yaffs_nand.h b/fs/yaffs2/yaffs_nand.h
new file mode 100644
index 00000000000..e013cdc2f54
--- /dev/null
+++ b/fs/yaffs2/yaffs_nand.h
@@ -0,0 +1,44 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_NAND_H__
+#define __YAFFS_NAND_H__
+#include "yaffs_guts.h"
+
+
+
+int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device *dev, int chunkInNAND,
+					__u8 *buffer,
+					yaffs_ExtendedTags *tags);
+
+int yaffs_WriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *buffer,
+						yaffs_ExtendedTags *tags);
+
+int yaffs_MarkBlockBad(yaffs_Device *dev, int blockNo);
+
+int yaffs_QueryInitialBlockState(yaffs_Device *dev,
+						int blockNo,
+						yaffs_BlockState *state,
+						unsigned *sequenceNumber);
+
+int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				  int blockInNAND);
+
+int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+
+#endif
+
diff --git a/fs/yaffs2/yaffs_nandemul2k.h b/fs/yaffs2/yaffs_nandemul2k.h
new file mode 100644
index 00000000000..41bc2b5f8b4
--- /dev/null
+++ b/fs/yaffs2/yaffs_nandemul2k.h
@@ -0,0 +1,39 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* Interface to emulated NAND functions (2k page size) */
+
+#ifndef __YAFFS_NANDEMUL2K_H__
+#define __YAFFS_NANDEMUL2K_H__
+
+#include "yaffs_guts.h"
+
+int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
+					int chunkInNAND, const __u8 *data,
+					const yaffs_ExtendedTags *tags);
+int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_DeviceStruct *dev,
+					 int chunkInNAND, __u8 *data,
+					 yaffs_ExtendedTags *tags);
+int nandemul2k_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
+int nandemul2k_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
+			      yaffs_BlockState *state, __u32 *sequenceNumber);
+int nandemul2k_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
+				int blockInNAND);
+int nandemul2k_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+int nandemul2k_GetBytesPerChunk(void);
+int nandemul2k_GetChunksPerBlock(void);
+int nandemul2k_GetNumberOfBlocks(void);
+
+#endif
diff --git a/fs/yaffs2/yaffs_packedtags1.c b/fs/yaffs2/yaffs_packedtags1.c
new file mode 100644
index 00000000000..3e67e691666
--- /dev/null
+++ b/fs/yaffs2/yaffs_packedtags1.c
@@ -0,0 +1,50 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_packedtags1.h"
+#include "yportenv.h"
+
+void yaffs_PackTags1(yaffs_PackedTags1 *pt, const yaffs_ExtendedTags *t)
+{
+	pt->chunkId = t->chunkId;
+	pt->serialNumber = t->serialNumber;
+	pt->byteCount = t->byteCount;
+	pt->objectId = t->objectId;
+	pt->ecc = 0;
+	pt->deleted = (t->chunkDeleted) ? 0 : 1;
+	pt->unusedStuff = 0;
+	pt->shouldBeFF = 0xFFFFFFFF;
+
+}
+
+void yaffs_UnpackTags1(yaffs_ExtendedTags *t, const yaffs_PackedTags1 *pt)
+{
+	static const __u8 allFF[] =
+	    { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff };
+
+	if (memcmp(allFF, pt, sizeof(yaffs_PackedTags1))) {
+		t->blockBad = 0;
+		if (pt->shouldBeFF != 0xFFFFFFFF)
+			t->blockBad = 1;
+		t->chunkUsed = 1;
+		t->objectId = pt->objectId;
+		t->chunkId = pt->chunkId;
+		t->byteCount = pt->byteCount;
+		t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+		t->chunkDeleted = (pt->deleted) ? 0 : 1;
+		t->serialNumber = pt->serialNumber;
+	} else {
+		memset(t, 0, sizeof(yaffs_ExtendedTags));
+	}
+}
diff --git a/fs/yaffs2/yaffs_packedtags1.h b/fs/yaffs2/yaffs_packedtags1.h
new file mode 100644
index 00000000000..f8c0471d4a4
--- /dev/null
+++ b/fs/yaffs2/yaffs_packedtags1.h
@@ -0,0 +1,37 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */
+
+#ifndef __YAFFS_PACKEDTAGS1_H__
+#define __YAFFS_PACKEDTAGS1_H__
+
+#include "yaffs_guts.h"
+
+typedef struct {
+	unsigned chunkId:20;
+	unsigned serialNumber:2;
+	unsigned byteCount:10;
+	unsigned objectId:18;
+	unsigned ecc:12;
+	unsigned deleted:1;
+	unsigned unusedStuff:1;
+	unsigned shouldBeFF;
+
+} yaffs_PackedTags1;
+
+void yaffs_PackTags1(yaffs_PackedTags1 *pt, const yaffs_ExtendedTags *t);
+void yaffs_UnpackTags1(yaffs_ExtendedTags *t, const yaffs_PackedTags1 *pt);
+#endif
diff --git a/fs/yaffs2/yaffs_packedtags2.c b/fs/yaffs2/yaffs_packedtags2.c
new file mode 100644
index 00000000000..62efec02d19
--- /dev/null
+++ b/fs/yaffs2/yaffs_packedtags2.c
@@ -0,0 +1,209 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_packedtags2.h"
+#include "yportenv.h"
+#include "yaffs_tagsvalidity.h"
+
+/* This code packs a set of extended tags into a binary structure for
+ * NAND storage
+ */
+
+/* Some of the information is "extra" struff which can be packed in to
+ * speed scanning
+ * This is defined by having the EXTRA_HEADER_INFO_FLAG set.
+ */
+
+/* Extra flags applied to chunkId */
+
+#define EXTRA_HEADER_INFO_FLAG	0x80000000
+#define EXTRA_SHRINK_FLAG	0x40000000
+#define EXTRA_SHADOWS_FLAG	0x20000000
+#define EXTRA_SPARE_FLAGS	0x10000000
+
+#define ALL_EXTRA_FLAGS		0xF0000000
+
+/* Also, the top 4 bits of the object Id are set to the object type. */
+#define EXTRA_OBJECT_TYPE_SHIFT (28)
+#define EXTRA_OBJECT_TYPE_MASK  ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT)
+
+#ifndef CONFIG_YAFFS_DOES_ECC
+#define YAFFS_IGNORE_TAGS_ECC 1
+#endif
+
+static void yaffs_DumpPackedTags2TagsPart(const yaffs_PackedTags2TagsPart *ptt)
+{
+	T(YAFFS_TRACE_MTD,
+	  (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR),
+	   ptt->objectId, ptt->chunkId, ptt->byteCount,
+	   ptt->sequenceNumber));
+}
+static void yaffs_DumpPackedTags2(const yaffs_PackedTags2 *pt)
+{
+	yaffs_DumpPackedTags2TagsPart(&pt->t);
+}
+
+static void yaffs_DumpTags2(const yaffs_ExtendedTags *t)
+{
+	T(YAFFS_TRACE_MTD,
+	  (TSTR
+	   ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d"
+	    TENDSTR), t->eccResult, t->blockBad, t->chunkUsed, t->objectId,
+	   t->chunkId, t->byteCount, t->chunkDeleted, t->serialNumber,
+	   t->sequenceNumber));
+
+}
+
+void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart *ptt,
+		const yaffs_ExtendedTags *t)
+{
+	ptt->chunkId = t->chunkId;
+	ptt->sequenceNumber = t->sequenceNumber;
+	ptt->byteCount = t->byteCount;
+	ptt->objectId = t->objectId;
+
+	if (t->chunkId == 0 && t->extraHeaderInfoAvailable) {
+		/* Store the extra header info instead */
+		/* We save the parent object in the chunkId */
+		ptt->chunkId = EXTRA_HEADER_INFO_FLAG
+			| t->extraParentObjectId;
+		if (t->extraIsShrinkHeader)
+			ptt->chunkId |= EXTRA_SHRINK_FLAG;
+		if (t->extraShadows)
+			ptt->chunkId |= EXTRA_SHADOWS_FLAG;
+
+		ptt->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
+		ptt->objectId |=
+		    (t->extraObjectType << EXTRA_OBJECT_TYPE_SHIFT);
+
+		if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK)
+			ptt->byteCount = t->extraEquivalentObjectId;
+		else if (t->extraObjectType == YAFFS_OBJECT_TYPE_FILE)
+			ptt->byteCount = t->extraFileLength;
+		else
+			ptt->byteCount = 0;
+	}
+
+	yaffs_DumpPackedTags2TagsPart(ptt);
+	yaffs_DumpTags2(t);
+}
+
+
+void yaffs_PackTags2(yaffs_PackedTags2 *pt, const yaffs_ExtendedTags *t)
+{
+	yaffs_PackTags2TagsPart(&pt->t, t);
+
+#ifndef YAFFS_IGNORE_TAGS_ECC
+	{
+		yaffs_ECCCalculateOther((unsigned char *)&pt->t,
+					sizeof(yaffs_PackedTags2TagsPart),
+					&pt->ecc);
+	}
+#endif
+}
+
+
+void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags *t,
+		yaffs_PackedTags2TagsPart *ptt)
+{
+
+	memset(t, 0, sizeof(yaffs_ExtendedTags));
+
+	yaffs_InitialiseTags(t);
+
+	if (ptt->sequenceNumber != 0xFFFFFFFF) {
+		t->blockBad = 0;
+		t->chunkUsed = 1;
+		t->objectId = ptt->objectId;
+		t->chunkId = ptt->chunkId;
+		t->byteCount = ptt->byteCount;
+		t->chunkDeleted = 0;
+		t->serialNumber = 0;
+		t->sequenceNumber = ptt->sequenceNumber;
+
+		/* Do extra header info stuff */
+
+		if (ptt->chunkId & EXTRA_HEADER_INFO_FLAG) {
+			t->chunkId = 0;
+			t->byteCount = 0;
+
+			t->extraHeaderInfoAvailable = 1;
+			t->extraParentObjectId =
+			    ptt->chunkId & (~(ALL_EXTRA_FLAGS));
+			t->extraIsShrinkHeader =
+			    (ptt->chunkId & EXTRA_SHRINK_FLAG) ? 1 : 0;
+			t->extraShadows =
+			    (ptt->chunkId & EXTRA_SHADOWS_FLAG) ? 1 : 0;
+			t->extraObjectType =
+			    ptt->objectId >> EXTRA_OBJECT_TYPE_SHIFT;
+			t->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
+
+			if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK)
+				t->extraEquivalentObjectId = ptt->byteCount;
+			else
+				t->extraFileLength = ptt->byteCount;
+		}
+	}
+
+	yaffs_DumpPackedTags2TagsPart(ptt);
+	yaffs_DumpTags2(t);
+
+}
+
+
+void yaffs_UnpackTags2(yaffs_ExtendedTags *t, yaffs_PackedTags2 *pt)
+{
+
+	yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+
+	if (pt->t.sequenceNumber != 0xFFFFFFFF) {
+		/* Page is in use */
+#ifndef YAFFS_IGNORE_TAGS_ECC
+		{
+			yaffs_ECCOther ecc;
+			int result;
+			yaffs_ECCCalculateOther((unsigned char *)&pt->t,
+						sizeof
+						(yaffs_PackedTags2TagsPart),
+						&ecc);
+			result =
+			    yaffs_ECCCorrectOther((unsigned char *)&pt->t,
+						  sizeof
+						  (yaffs_PackedTags2TagsPart),
+						  &pt->ecc, &ecc);
+			switch (result) {
+			case 0:
+				eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+				break;
+			case 1:
+				eccResult = YAFFS_ECC_RESULT_FIXED;
+				break;
+			case -1:
+				eccResult = YAFFS_ECC_RESULT_UNFIXED;
+				break;
+			default:
+				eccResult = YAFFS_ECC_RESULT_UNKNOWN;
+			}
+		}
+#endif
+	}
+
+	yaffs_UnpackTags2TagsPart(t, &pt->t);
+
+	t->eccResult = eccResult;
+
+	yaffs_DumpPackedTags2(pt);
+	yaffs_DumpTags2(t);
+
+}
+
diff --git a/fs/yaffs2/yaffs_packedtags2.h b/fs/yaffs2/yaffs_packedtags2.h
new file mode 100644
index 00000000000..ec30f843bcb
--- /dev/null
+++ b/fs/yaffs2/yaffs_packedtags2.h
@@ -0,0 +1,43 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/* This is used to pack YAFFS2 tags, not YAFFS1tags. */
+
+#ifndef __YAFFS_PACKEDTAGS2_H__
+#define __YAFFS_PACKEDTAGS2_H__
+
+#include "yaffs_guts.h"
+#include "yaffs_ecc.h"
+
+typedef struct {
+	unsigned sequenceNumber;
+	unsigned objectId;
+	unsigned chunkId;
+	unsigned byteCount;
+} yaffs_PackedTags2TagsPart;
+
+typedef struct {
+	yaffs_PackedTags2TagsPart t;
+	yaffs_ECCOther ecc;
+} yaffs_PackedTags2;
+
+/* Full packed tags with ECC, used for oob tags */
+void yaffs_PackTags2(yaffs_PackedTags2 *pt, const yaffs_ExtendedTags *t);
+void yaffs_UnpackTags2(yaffs_ExtendedTags *t, yaffs_PackedTags2 *pt);
+
+/* Only the tags part (no ECC for use with inband tags */
+void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart *pt, const yaffs_ExtendedTags *t);
+void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags *t, yaffs_PackedTags2TagsPart *pt);
+#endif
diff --git a/fs/yaffs2/yaffs_qsort.c b/fs/yaffs2/yaffs_qsort.c
new file mode 100644
index 00000000000..187519fbdb5
--- /dev/null
+++ b/fs/yaffs2/yaffs_qsort.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "yportenv.h"
+/* #include <linux/string.h> */
+
+/*
+ * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".
+ */
+#define swapcode(TYPE, parmi, parmj, n) do { 		\
+	long i = (n) / sizeof (TYPE); 			\
+	register TYPE *pi = (TYPE *) (parmi); 		\
+	register TYPE *pj = (TYPE *) (parmj); 		\
+	do { 						\
+		register TYPE	t = *pi;		\
+		*pi++ = *pj;				\
+		*pj++ = t;				\
+	} while (--i > 0);				\
+} while (0)
+
+#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \
+	es % sizeof(long) ? 2 : es == sizeof(long) ? 0 : 1;
+
+static __inline void
+swapfunc(char *a, char *b, int n, int swaptype)
+{
+	if (swaptype <= 1)
+		swapcode(long, a, b, n);
+	else
+		swapcode(char, a, b, n);
+}
+
+#define yswap(a, b) do {					\
+	if (swaptype == 0) {				\
+		long t = *(long *)(a);			\
+		*(long *)(a) = *(long *)(b);		\
+		*(long *)(b) = t;			\
+	} else						\
+		swapfunc(a, b, es, swaptype);		\
+} while (0)
+
+#define vecswap(a, b, n) 	if ((n) > 0) swapfunc(a, b, n, swaptype)
+
+static __inline char *
+med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *))
+{
+	return cmp(a, b) < 0 ?
+		(cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a))
+		: (cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c));
+}
+
+#ifndef min
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+void
+yaffs_qsort(void *aa, size_t n, size_t es,
+	int (*cmp)(const void *, const void *))
+{
+	char *pa, *pb, *pc, *pd, *pl, *pm, *pn;
+	int d, r, swaptype, swap_cnt;
+	register char *a = aa;
+
+loop:	SWAPINIT(a, es);
+	swap_cnt = 0;
+	if (n < 7) {
+		for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es)
+			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
+			     pl -= es)
+				yswap(pl, pl - es);
+		return;
+	}
+	pm = (char *)a + (n / 2) * es;
+	if (n > 7) {
+		pl = (char *)a;
+		pn = (char *)a + (n - 1) * es;
+		if (n > 40) {
+			d = (n / 8) * es;
+			pl = med3(pl, pl + d, pl + 2 * d, cmp);
+			pm = med3(pm - d, pm, pm + d, cmp);
+			pn = med3(pn - 2 * d, pn - d, pn, cmp);
+		}
+		pm = med3(pl, pm, pn, cmp);
+	}
+	yswap(a, pm);
+	pa = pb = (char *)a + es;
+
+	pc = pd = (char *)a + (n - 1) * es;
+	for (;;) {
+		while (pb <= pc && (r = cmp(pb, a)) <= 0) {
+			if (r == 0) {
+				swap_cnt = 1;
+				yswap(pa, pb);
+				pa += es;
+			}
+			pb += es;
+		}
+		while (pb <= pc && (r = cmp(pc, a)) >= 0) {
+			if (r == 0) {
+				swap_cnt = 1;
+				yswap(pc, pd);
+				pd -= es;
+			}
+			pc -= es;
+		}
+		if (pb > pc)
+			break;
+		yswap(pb, pc);
+		swap_cnt = 1;
+		pb += es;
+		pc -= es;
+	}
+	if (swap_cnt == 0) {  /* Switch to insertion sort */
+		for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es)
+			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
+			     pl -= es)
+				yswap(pl, pl - es);
+		return;
+	}
+
+	pn = (char *)a + n * es;
+	r = min(pa - (char *)a, pb - pa);
+	vecswap(a, pb - r, r);
+	r = min((long)(pd - pc), (long)(pn - pd - es));
+	vecswap(pb, pn - r, r);
+	r = pb - pa;
+	if (r > es)
+		yaffs_qsort(a, r / es, es, cmp);
+	r = pd - pc;
+	if (r > es) {
+		/* Iterate rather than recurse to save stack space */
+		a = pn - r;
+		n = r / es;
+		goto loop;
+	}
+/*		yaffs_qsort(pn - r, r / es, es, cmp);*/
+}
diff --git a/fs/yaffs2/yaffs_qsort.h b/fs/yaffs2/yaffs_qsort.h
new file mode 100644
index 00000000000..941c7a87ca0
--- /dev/null
+++ b/fs/yaffs2/yaffs_qsort.h
@@ -0,0 +1,23 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YAFFS_QSORT_H__
+#define __YAFFS_QSORT_H__
+
+extern void yaffs_qsort(void *const base, size_t total_elems, size_t size,
+			int (*cmp)(const void *, const void *));
+
+#endif
diff --git a/fs/yaffs2/yaffs_tagscompat.c b/fs/yaffs2/yaffs_tagscompat.c
new file mode 100644
index 00000000000..e3173cc2e23
--- /dev/null
+++ b/fs/yaffs2/yaffs_tagscompat.c
@@ -0,0 +1,538 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_guts.h"
+#include "yaffs_tagscompat.h"
+#include "yaffs_ecc.h"
+#include "yaffs_getblockinfo.h"
+
+static void yaffs_HandleReadDataError(yaffs_Device *dev, int chunkInNAND);
+#ifdef NOTYET
+static void yaffs_CheckWrittenBlock(yaffs_Device *dev, int chunkInNAND);
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				     const __u8 *data,
+				     const yaffs_Spare *spare);
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				    const yaffs_Spare *spare);
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND);
+#endif
+
+static const char yaffs_countBitsTable[256] = {
+	0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+	4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8
+};
+
+int yaffs_CountBits(__u8 x)
+{
+	int retVal;
+	retVal = yaffs_countBitsTable[x];
+	return retVal;
+}
+
+/********** Tags ECC calculations  *********/
+
+void yaffs_CalcECC(const __u8 *data, yaffs_Spare *spare)
+{
+	yaffs_ECCCalculate(data, spare->ecc1);
+	yaffs_ECCCalculate(&data[256], spare->ecc2);
+}
+
+void yaffs_CalcTagsECC(yaffs_Tags *tags)
+{
+	/* Calculate an ecc */
+
+	unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+	unsigned i, j;
+	unsigned ecc = 0;
+	unsigned bit = 0;
+
+	tags->ecc = 0;
+
+	for (i = 0; i < 8; i++) {
+		for (j = 1; j & 0xff; j <<= 1) {
+			bit++;
+			if (b[i] & j)
+				ecc ^= bit;
+		}
+	}
+
+	tags->ecc = ecc;
+
+}
+
+int yaffs_CheckECCOnTags(yaffs_Tags *tags)
+{
+	unsigned ecc = tags->ecc;
+
+	yaffs_CalcTagsECC(tags);
+
+	ecc ^= tags->ecc;
+
+	if (ecc && ecc <= 64) {
+		/* TODO: Handle the failure better. Retire? */
+		unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+
+		ecc--;
+
+		b[ecc / 8] ^= (1 << (ecc & 7));
+
+		/* Now recvalc the ecc */
+		yaffs_CalcTagsECC(tags);
+
+		return 1;	/* recovered error */
+	} else if (ecc) {
+		/* Wierd ecc failure value */
+		/* TODO Need to do somethiong here */
+		return -1;	/* unrecovered error */
+	}
+
+	return 0;
+}
+
+/********** Tags **********/
+
+static void yaffs_LoadTagsIntoSpare(yaffs_Spare *sparePtr,
+				yaffs_Tags *tagsPtr)
+{
+	yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
+
+	yaffs_CalcTagsECC(tagsPtr);
+
+	sparePtr->tagByte0 = tu->asBytes[0];
+	sparePtr->tagByte1 = tu->asBytes[1];
+	sparePtr->tagByte2 = tu->asBytes[2];
+	sparePtr->tagByte3 = tu->asBytes[3];
+	sparePtr->tagByte4 = tu->asBytes[4];
+	sparePtr->tagByte5 = tu->asBytes[5];
+	sparePtr->tagByte6 = tu->asBytes[6];
+	sparePtr->tagByte7 = tu->asBytes[7];
+}
+
+static void yaffs_GetTagsFromSpare(yaffs_Device *dev, yaffs_Spare *sparePtr,
+				yaffs_Tags *tagsPtr)
+{
+	yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
+	int result;
+
+	tu->asBytes[0] = sparePtr->tagByte0;
+	tu->asBytes[1] = sparePtr->tagByte1;
+	tu->asBytes[2] = sparePtr->tagByte2;
+	tu->asBytes[3] = sparePtr->tagByte3;
+	tu->asBytes[4] = sparePtr->tagByte4;
+	tu->asBytes[5] = sparePtr->tagByte5;
+	tu->asBytes[6] = sparePtr->tagByte6;
+	tu->asBytes[7] = sparePtr->tagByte7;
+
+	result = yaffs_CheckECCOnTags(tagsPtr);
+	if (result > 0)
+		dev->tagsEccFixed++;
+	else if (result < 0)
+		dev->tagsEccUnfixed++;
+}
+
+static void yaffs_SpareInitialise(yaffs_Spare *spare)
+{
+	memset(spare, 0xFF, sizeof(yaffs_Spare));
+}
+
+static int yaffs_WriteChunkToNAND(struct yaffs_DeviceStruct *dev,
+				int chunkInNAND, const __u8 *data,
+				yaffs_Spare *spare)
+{
+	if (chunkInNAND < dev->startBlock * dev->nChunksPerBlock) {
+		T(YAFFS_TRACE_ERROR,
+		  (TSTR("**>> yaffs chunk %d is not valid" TENDSTR),
+		   chunkInNAND));
+		return YAFFS_FAIL;
+	}
+
+	return dev->writeChunkToNAND(dev, chunkInNAND, data, spare);
+}
+
+static int yaffs_ReadChunkFromNAND(struct yaffs_DeviceStruct *dev,
+				   int chunkInNAND,
+				   __u8 *data,
+				   yaffs_Spare *spare,
+				   yaffs_ECCResult *eccResult,
+				   int doErrorCorrection)
+{
+	int retVal;
+	yaffs_Spare localSpare;
+
+	if (!spare && data) {
+		/* If we don't have a real spare, then we use a local one. */
+		/* Need this for the calculation of the ecc */
+		spare = &localSpare;
+	}
+
+	if (!dev->useNANDECC) {
+		retVal = dev->readChunkFromNAND(dev, chunkInNAND, data, spare);
+		if (data && doErrorCorrection) {
+			/* Do ECC correction */
+			/* Todo handle any errors */
+			int eccResult1, eccResult2;
+			__u8 calcEcc[3];
+
+			yaffs_ECCCalculate(data, calcEcc);
+			eccResult1 =
+			    yaffs_ECCCorrect(data, spare->ecc1, calcEcc);
+			yaffs_ECCCalculate(&data[256], calcEcc);
+			eccResult2 =
+			    yaffs_ECCCorrect(&data[256], spare->ecc2, calcEcc);
+
+			if (eccResult1 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error fix performed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+				dev->eccFixed++;
+			} else if (eccResult1 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error unfixed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+				dev->eccUnfixed++;
+			}
+
+			if (eccResult2 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error fix performed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+				dev->eccFixed++;
+			} else if (eccResult2 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>yaffs ecc error unfixed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+				dev->eccUnfixed++;
+			}
+
+			if (eccResult1 || eccResult2) {
+				/* We had a data problem on this page */
+				yaffs_HandleReadDataError(dev, chunkInNAND);
+			}
+
+			if (eccResult1 < 0 || eccResult2 < 0)
+				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
+			else if (eccResult1 > 0 || eccResult2 > 0)
+				*eccResult = YAFFS_ECC_RESULT_FIXED;
+			else
+				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+		}
+	} else {
+		/* Must allocate enough memory for spare+2*sizeof(int) */
+		/* for ecc results from device. */
+		struct yaffs_NANDSpare nspare;
+
+		memset(&nspare, 0, sizeof(nspare));
+
+		retVal = dev->readChunkFromNAND(dev, chunkInNAND, data,
+					(yaffs_Spare *) &nspare);
+		memcpy(spare, &nspare, sizeof(yaffs_Spare));
+		if (data && doErrorCorrection) {
+			if (nspare.eccres1 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error fix performed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+			} else if (nspare.eccres1 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error unfixed on chunk %d:0"
+				    TENDSTR), chunkInNAND));
+			}
+
+			if (nspare.eccres2 > 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error fix performed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+			} else if (nspare.eccres2 < 0) {
+				T(YAFFS_TRACE_ERROR,
+				  (TSTR
+				   ("**>>mtd ecc error unfixed on chunk %d:1"
+				    TENDSTR), chunkInNAND));
+			}
+
+			if (nspare.eccres1 || nspare.eccres2) {
+				/* We had a data problem on this page */
+				yaffs_HandleReadDataError(dev, chunkInNAND);
+			}
+
+			if (nspare.eccres1 < 0 || nspare.eccres2 < 0)
+				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
+			else if (nspare.eccres1 > 0 || nspare.eccres2 > 0)
+				*eccResult = YAFFS_ECC_RESULT_FIXED;
+			else
+				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+
+		}
+	}
+	return retVal;
+}
+
+#ifdef NOTYET
+static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
+				  int chunkInNAND)
+{
+	static int init;
+	static __u8 cmpbuf[YAFFS_BYTES_PER_CHUNK];
+	static __u8 data[YAFFS_BYTES_PER_CHUNK];
+	/* Might as well always allocate the larger size for */
+	/* dev->useNANDECC == true; */
+	static __u8 spare[sizeof(struct yaffs_NANDSpare)];
+
+	dev->readChunkFromNAND(dev, chunkInNAND, data, (yaffs_Spare *) spare);
+
+	if (!init) {
+		memset(cmpbuf, 0xff, YAFFS_BYTES_PER_CHUNK);
+		init = 1;
+	}
+
+	if (memcmp(cmpbuf, data, YAFFS_BYTES_PER_CHUNK))
+		return YAFFS_FAIL;
+	if (memcmp(cmpbuf, spare, 16))
+		return YAFFS_FAIL;
+
+	return YAFFS_OK;
+
+}
+#endif
+
+/*
+ * Functions for robustisizing
+ */
+
+static void yaffs_HandleReadDataError(yaffs_Device *dev, int chunkInNAND)
+{
+	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
+
+	/* Mark the block for retirement */
+	yaffs_GetBlockInfo(dev, blockInNAND + dev->blockOffset)->needsRetiring = 1;
+	T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+	  (TSTR("**>>Block %d marked for retirement" TENDSTR), blockInNAND));
+
+	/* TODO:
+	 * Just do a garbage collection on the affected block
+	 * then retire the block
+	 * NB recursion
+	 */
+}
+
+#ifdef NOTYET
+static void yaffs_CheckWrittenBlock(yaffs_Device *dev, int chunkInNAND)
+{
+}
+
+static void yaffs_HandleWriteChunkOk(yaffs_Device *dev, int chunkInNAND,
+				     const __u8 *data,
+				     const yaffs_Spare *spare)
+{
+}
+
+static void yaffs_HandleUpdateChunk(yaffs_Device *dev, int chunkInNAND,
+				    const yaffs_Spare *spare)
+{
+}
+
+static void yaffs_HandleWriteChunkError(yaffs_Device *dev, int chunkInNAND)
+{
+	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
+
+	/* Mark the block for retirement */
+	yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1;
+	/* Delete the chunk */
+	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+}
+
+static int yaffs_VerifyCompare(const __u8 *d0, const __u8 *d1,
+			       const yaffs_Spare *s0, const yaffs_Spare *s1)
+{
+
+	if (memcmp(d0, d1, YAFFS_BYTES_PER_CHUNK) != 0 ||
+	    s0->tagByte0 != s1->tagByte0 ||
+	    s0->tagByte1 != s1->tagByte1 ||
+	    s0->tagByte2 != s1->tagByte2 ||
+	    s0->tagByte3 != s1->tagByte3 ||
+	    s0->tagByte4 != s1->tagByte4 ||
+	    s0->tagByte5 != s1->tagByte5 ||
+	    s0->tagByte6 != s1->tagByte6 ||
+	    s0->tagByte7 != s1->tagByte7 ||
+	    s0->ecc1[0] != s1->ecc1[0] ||
+	    s0->ecc1[1] != s1->ecc1[1] ||
+	    s0->ecc1[2] != s1->ecc1[2] ||
+	    s0->ecc2[0] != s1->ecc2[0] ||
+	    s0->ecc2[1] != s1->ecc2[1] || s0->ecc2[2] != s1->ecc2[2]) {
+		return 0;
+	}
+
+	return 1;
+}
+#endif				/* NOTYET */
+
+int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *data,
+						const yaffs_ExtendedTags *eTags)
+{
+	yaffs_Spare spare;
+	yaffs_Tags tags;
+
+	yaffs_SpareInitialise(&spare);
+
+	if (eTags->chunkDeleted)
+		spare.pageStatus = 0;
+	else {
+		tags.objectId = eTags->objectId;
+		tags.chunkId = eTags->chunkId;
+
+		tags.byteCountLSB = eTags->byteCount & 0x3ff;
+
+		if (dev->nDataBytesPerChunk >= 1024)
+			tags.byteCountMSB = (eTags->byteCount >> 10) & 3;
+		else
+			tags.byteCountMSB = 3;
+
+
+		tags.serialNumber = eTags->serialNumber;
+
+		if (!dev->useNANDECC && data)
+			yaffs_CalcECC(data, &spare);
+
+		yaffs_LoadTagsIntoSpare(&spare, &tags);
+
+	}
+
+	return yaffs_WriteChunkToNAND(dev, chunkInNAND, data, &spare);
+}
+
+int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device *dev,
+						     int chunkInNAND,
+						     __u8 *data,
+						     yaffs_ExtendedTags *eTags)
+{
+
+	yaffs_Spare spare;
+	yaffs_Tags tags;
+	yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_UNKNOWN;
+
+	static yaffs_Spare spareFF;
+	static int init;
+
+	if (!init) {
+		memset(&spareFF, 0xFF, sizeof(spareFF));
+		init = 1;
+	}
+
+	if (yaffs_ReadChunkFromNAND
+	    (dev, chunkInNAND, data, &spare, &eccResult, 1)) {
+		/* eTags may be NULL */
+		if (eTags) {
+
+			int deleted =
+			    (yaffs_CountBits(spare.pageStatus) < 7) ? 1 : 0;
+
+			eTags->chunkDeleted = deleted;
+			eTags->eccResult = eccResult;
+			eTags->blockBad = 0;	/* We're reading it */
+			/* therefore it is not a bad block */
+			eTags->chunkUsed =
+			    (memcmp(&spareFF, &spare, sizeof(spareFF)) !=
+			     0) ? 1 : 0;
+
+			if (eTags->chunkUsed) {
+				yaffs_GetTagsFromSpare(dev, &spare, &tags);
+
+				eTags->objectId = tags.objectId;
+				eTags->chunkId = tags.chunkId;
+				eTags->byteCount = tags.byteCountLSB;
+
+				if (dev->nDataBytesPerChunk >= 1024)
+					eTags->byteCount |= (((unsigned) tags.byteCountMSB) << 10);
+
+				eTags->serialNumber = tags.serialNumber;
+			}
+		}
+
+		return YAFFS_OK;
+	} else {
+		return YAFFS_FAIL;
+	}
+}
+
+int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
+					    int blockInNAND)
+{
+
+	yaffs_Spare spare;
+
+	memset(&spare, 0xff, sizeof(yaffs_Spare));
+
+	spare.blockStatus = 'Y';
+
+	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock, NULL,
+			       &spare);
+	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock + 1,
+			       NULL, &spare);
+
+	return YAFFS_OK;
+
+}
+
+int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
+					  int blockNo,
+					  yaffs_BlockState *state,
+					  __u32 *sequenceNumber)
+{
+
+	yaffs_Spare spare0, spare1;
+	static yaffs_Spare spareFF;
+	static int init;
+	yaffs_ECCResult dummy;
+
+	if (!init) {
+		memset(&spareFF, 0xFF, sizeof(spareFF));
+		init = 1;
+	}
+
+	*sequenceNumber = 0;
+
+	yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock, NULL,
+				&spare0, &dummy, 1);
+	yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock + 1, NULL,
+				&spare1, &dummy, 1);
+
+	if (yaffs_CountBits(spare0.blockStatus & spare1.blockStatus) < 7)
+		*state = YAFFS_BLOCK_STATE_DEAD;
+	else if (memcmp(&spareFF, &spare0, sizeof(spareFF)) == 0)
+		*state = YAFFS_BLOCK_STATE_EMPTY;
+	else
+		*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffs_tagscompat.h b/fs/yaffs2/yaffs_tagscompat.h
new file mode 100644
index 00000000000..6f95119e0aa
--- /dev/null
+++ b/fs/yaffs2/yaffs_tagscompat.h
@@ -0,0 +1,39 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_TAGSCOMPAT_H__
+#define __YAFFS_TAGSCOMPAT_H__
+
+#include "yaffs_guts.h"
+int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						const __u8 *data,
+						const yaffs_ExtendedTags *tags);
+int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device *dev,
+						int chunkInNAND,
+						__u8 *data,
+						yaffs_ExtendedTags *tags);
+int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
+					    int blockNo);
+int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
+					  int blockNo,
+					  yaffs_BlockState *state,
+					  __u32 *sequenceNumber);
+
+void yaffs_CalcTagsECC(yaffs_Tags *tags);
+int yaffs_CheckECCOnTags(yaffs_Tags *tags);
+int yaffs_CountBits(__u8 byte);
+
+#endif
diff --git a/fs/yaffs2/yaffs_tagsvalidity.c b/fs/yaffs2/yaffs_tagsvalidity.c
new file mode 100644
index 00000000000..5233bcba8b3
--- /dev/null
+++ b/fs/yaffs2/yaffs_tagsvalidity.c
@@ -0,0 +1,28 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_tagsvalidity.h"
+
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags)
+{
+	memset(tags, 0, sizeof(yaffs_ExtendedTags));
+	tags->validMarker0 = 0xAAAAAAAA;
+	tags->validMarker1 = 0x55555555;
+}
+
+int yaffs_ValidateTags(yaffs_ExtendedTags *tags)
+{
+	return (tags->validMarker0 == 0xAAAAAAAA &&
+		tags->validMarker1 == 0x55555555);
+
+}
diff --git a/fs/yaffs2/yaffs_tagsvalidity.h b/fs/yaffs2/yaffs_tagsvalidity.h
new file mode 100644
index 00000000000..cb11884b2d1
--- /dev/null
+++ b/fs/yaffs2/yaffs_tagsvalidity.h
@@ -0,0 +1,24 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YAFFS_TAGS_VALIDITY_H__
+#define __YAFFS_TAGS_VALIDITY_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_InitialiseTags(yaffs_ExtendedTags *tags);
+int yaffs_ValidateTags(yaffs_ExtendedTags *tags);
+#endif
diff --git a/fs/yaffs2/yaffsinterface.h b/fs/yaffs2/yaffsinterface.h
new file mode 100644
index 00000000000..810837a32d9
--- /dev/null
+++ b/fs/yaffs2/yaffsinterface.h
@@ -0,0 +1,21 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFSINTERFACE_H__
+#define __YAFFSINTERFACE_H__
+
+int yaffs_Initialise(unsigned nBlocks);
+
+#endif
diff --git a/fs/yaffs2/yportenv.h b/fs/yaffs2/yportenv.h
new file mode 100644
index 00000000000..28e205bbd8c
--- /dev/null
+++ b/fs/yaffs2/yportenv.h
@@ -0,0 +1,203 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YPORTENV_H__
+#define __YPORTENV_H__
+
+/*
+ * Define the MTD version in terms of Linux Kernel versions
+ * This allows yaffs to be used independantly of the kernel
+ * as well as with it.
+ */
+
+#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
+
+#if defined CONFIG_YAFFS_WINCE
+
+#include "ywinceenv.h"
+
+#elif defined __KERNEL__
+
+#include "moduleconfig.h"
+
+/* Linux kernel */
+
+#include <linux/version.h>
+#define MTD_VERSION_CODE LINUX_VERSION_CODE
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
+#include <linux/config.h>
+#endif
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#define YCHAR char
+#define YUCHAR unsigned char
+#define _Y(x)     x
+#define yaffs_strcat(a, b)     strcat(a, b)
+#define yaffs_strcpy(a, b)     strcpy(a, b)
+#define yaffs_strncpy(a, b, c) strncpy(a, b, c)
+#define yaffs_strncmp(a, b, c) strncmp(a, b, c)
+#define yaffs_strlen(s)	       strlen(s)
+#define yaffs_sprintf	       sprintf
+#define yaffs_toupper(a)       toupper(a)
+
+#define Y_INLINE inline
+
+#define YAFFS_LOSTNFOUND_NAME		"lost+found"
+#define YAFFS_LOSTNFOUND_PREFIX		"obj"
+
+/* #define YPRINTF(x) printk x */
+#define YMALLOC(x) kmalloc(x, GFP_NOFS)
+#define YFREE(x)   kfree(x)
+#define YMALLOC_ALT(x) vmalloc(x)
+#define YFREE_ALT(x)   vfree(x)
+#define YMALLOC_DMA(x) YMALLOC(x)
+
+/* KR - added for use in scan so processes aren't blocked indefinitely. */
+#define YYIELD() schedule()
+
+#define YAFFS_ROOT_MODE			0666
+#define YAFFS_LOSTNFOUND_MODE		0666
+
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0))
+#define Y_CURRENT_TIME CURRENT_TIME.tv_sec
+#define Y_TIME_CONVERT(x) (x).tv_sec
+#else
+#define Y_CURRENT_TIME CURRENT_TIME
+#define Y_TIME_CONVERT(x) (x)
+#endif
+
+#define yaffs_SumCompare(x, y) ((x) == (y))
+#define yaffs_strcmp(a, b) strcmp(a, b)
+
+#define TENDSTR "\n"
+#define TSTR(x) KERN_WARNING x
+#define TCONT(x) x
+#define TOUT(p) printk p
+
+#define yaffs_trace(mask, fmt, args...) \
+	do { if ((mask) & (yaffs_traceMask|YAFFS_TRACE_ERROR)) \
+		printk(KERN_WARNING "yaffs: " fmt, ## args); \
+	} while (0)
+
+#define compile_time_assertion(assertion) \
+	({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; })
+
+#elif defined CONFIG_YAFFS_DIRECT
+
+#define MTD_VERSION_CODE MTD_VERSION(2, 6, 22)
+
+/* Direct interface */
+#include "ydirectenv.h"
+
+#elif defined CONFIG_YAFFS_UTIL
+
+/* Stuff for YAFFS utilities */
+
+#include "stdlib.h"
+#include "stdio.h"
+#include "string.h"
+
+#include "devextras.h"
+
+#define YMALLOC(x) malloc(x)
+#define YFREE(x)   free(x)
+#define YMALLOC_ALT(x) malloc(x)
+#define YFREE_ALT(x) free(x)
+
+#define YCHAR char
+#define YUCHAR unsigned char
+#define _Y(x)     x
+#define yaffs_strcat(a, b)     strcat(a, b)
+#define yaffs_strcpy(a, b)     strcpy(a, b)
+#define yaffs_strncpy(a, b, c) strncpy(a, b, c)
+#define yaffs_strlen(s)	       strlen(s)
+#define yaffs_sprintf	       sprintf
+#define yaffs_toupper(a)       toupper(a)
+
+#define Y_INLINE inline
+
+/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */
+/* #define YALERT(s) YINFO(s) */
+
+#define TENDSTR "\n"
+#define TSTR(x) x
+#define TOUT(p) printf p
+
+#define YAFFS_LOSTNFOUND_NAME		"lost+found"
+#define YAFFS_LOSTNFOUND_PREFIX		"obj"
+/* #define YPRINTF(x) printf x */
+
+#define YAFFS_ROOT_MODE				0666
+#define YAFFS_LOSTNFOUND_MODE		0666
+
+#define yaffs_SumCompare(x, y) ((x) == (y))
+#define yaffs_strcmp(a, b) strcmp(a, b)
+
+#else
+/* Should have specified a configuration type */
+#error Unknown configuration
+
+#endif
+
+/* see yaffs_fs.c */
+extern unsigned int yaffs_traceMask;
+extern unsigned int yaffs_wr_attempts;
+
+/*
+ * Tracing flags.
+ * The flags masked in YAFFS_TRACE_ALWAYS are always traced.
+ */
+
+#define YAFFS_TRACE_OS			0x00000002
+#define YAFFS_TRACE_ALLOCATE		0x00000004
+#define YAFFS_TRACE_SCAN		0x00000008
+#define YAFFS_TRACE_BAD_BLOCKS		0x00000010
+#define YAFFS_TRACE_ERASE		0x00000020
+#define YAFFS_TRACE_GC			0x00000040
+#define YAFFS_TRACE_WRITE		0x00000080
+#define YAFFS_TRACE_TRACING		0x00000100
+#define YAFFS_TRACE_DELETION		0x00000200
+#define YAFFS_TRACE_BUFFERS		0x00000400
+#define YAFFS_TRACE_NANDACCESS		0x00000800
+#define YAFFS_TRACE_GC_DETAIL		0x00001000
+#define YAFFS_TRACE_SCAN_DEBUG		0x00002000
+#define YAFFS_TRACE_MTD			0x00004000
+#define YAFFS_TRACE_CHECKPOINT		0x00008000
+
+#define YAFFS_TRACE_VERIFY		0x00010000
+#define YAFFS_TRACE_VERIFY_NAND		0x00020000
+#define YAFFS_TRACE_VERIFY_FULL		0x00040000
+#define YAFFS_TRACE_VERIFY_ALL		0x000F0000
+
+
+#define YAFFS_TRACE_ERROR		0x40000000
+#define YAFFS_TRACE_BUG			0x80000000
+#define YAFFS_TRACE_ALWAYS		0xF0000000
+
+
+#define T(mask, p) do { if ((mask) & (yaffs_traceMask | YAFFS_TRACE_ALWAYS)) TOUT(p); } while (0)
+
+#ifndef YBUG
+#define YBUG() do {T(YAFFS_TRACE_BUG, (TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR), __LINE__)); } while (0)
+#endif
+
+#endif
diff --git a/include/Kbuild b/include/Kbuild
index 8d226bfa269..f615202ef64 100644
--- a/include/Kbuild
+++ b/include/Kbuild
@@ -10,3 +10,4 @@ header-y += video/
 header-y += drm/
 header-y += xen/
 header-y += scsi/
+header-y += mach-anyka/
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index b6e818f4b24..732044ceab1 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -754,3 +754,14 @@
 	BSS(bss_align)							\
 	. = ALIGN(stop_align);						\
 	VMLINUX_SYMBOL(__bss_stop) = .;
+
+#define L2MEM(x)	\
+	_start_##x = .;	\
+	.l2mem_##x 0x48000000 : AT(_start_##x) {	\
+	__l2mem_start_##x = .;\
+	*(.l2mem_##x)	\
+	__l2mem_end_##x = .;\
+	}	\
+	. = _start_##x + __l2mem_end_##x - __l2mem_start_##x;\
+	_end_##x = .;	
+
diff --git a/include/linux/ak98_freq_policy.h b/include/linux/ak98_freq_policy.h
new file mode 100755
index 00000000000..3525cfd221c
--- /dev/null
+++ b/include/linux/ak98_freq_policy.h
@@ -0,0 +1,68 @@
+#ifndef _AK98_FREQ_POLICY_H_
+#define _AK98_FREQ_POLICY_H_
+
+#define MAX_NAME_LEN	100
+
+#define FREQ_IOC_MAGIC 'f'
+
+#define REQUEST_MODE			_IOW(FREQ_IOC_MAGIC, 32, __u8)
+#define RELEASE_MODE			_IOW(FREQ_IOC_MAGIC, 33, __u8)
+
+#ifdef __KERNEL__
+
+#include <linux/anyka_cpufreq.h>
+
+/* micros definitions  */
+#define HIGHEST_MODE 	FREQ_MODE_MAX
+#define LOWEST_MODE		FREQ_MODE_MIN
+
+#define HIGH_IX (HIGHEST_MODE>LOWEST_MODE ? HIGHEST_MODE : LOWEST_MODE)
+#define LOW_IX  (HIGHEST_MODE<LOWEST_MODE ? HIGHEST_MODE : LOWEST_MODE)
+
+#define NUM_OF_MODE  	(LOWEST_MODE-HIGHEST_MODE>0 ? (LOWEST_MODE-HIGHEST_MODE+1):(HIGHEST_MODE-LOWEST_MODE+1))
+
+#define DEFAULT_MODE 		LOWEST_MODE
+#define NORMAL_DELTA_MIN 	NORMAL_MODE_CLOCK_3
+#define BK_MUSIC_MODE  		NORMAL_MODE_CLOCK_5
+#define RELEASE_DELAY 		5000  /* unit: microsecond  */
+#define REQUEST_DELAY		2000 
+#define PLL_CHANGE_DELAY    2000
+
+typedef T_OPERATION_MODE T_MODE_TYPE;
+/**************************************************************/
+
+struct t_app_to_mode {
+	char appName[MAX_NAME_LEN];	
+	T_OPERATION_MODE mode;
+};
+
+struct mode_table_node {
+	char modeName[MAX_NAME_LEN];
+	T_OPERATION_MODE mode;
+};
+
+struct rqst_info
+{
+	char appName[MAX_NAME_LEN];
+	pid_t pid;
+	int tag;
+};
+
+struct rqst_node {
+	struct rqst_info app_info;
+	struct list_head list;
+};
+
+
+/*
+	request the system to hold the mode until the ak98_release_hold_mode is called
+*/
+typedef void (*AK98_RQSTMODE_CALLBACK)(void *data);
+int ak98_request_hold_mode(T_MODE_TYPE mode, AK98_RQSTMODE_CALLBACK fn, 
+	void *data);
+int ak98_release_hold_mode(T_MODE_TYPE mode);
+
+
+#endif
+
+#endif
diff --git a/include/linux/akfb.h b/include/linux/akfb.h
new file mode 100755
index 00000000000..262b6683e22
--- /dev/null
+++ b/include/linux/akfb.h
@@ -0,0 +1,111 @@
+#ifndef __LINUX_AKFB_H__
+#define __LINUX_AKFB_H__
+
+#ifndef __KERNEL__
+#include <linux/ioctl.h>
+typedef unsigned long dma_addr_t;
+typedef unsigned char bool;
+#define true  1
+#define false 0
+
+enum aklcd_yuv_range {
+	YUV_SHORT_RANGE = 0b0,
+	YUV_FULL_RANGE  = 0b1
+};
+
+enum aklcd_ov_alpha {
+	OV_TRANS_100 = 0x0,
+	OV_TRANS_87  = 0x1,
+	OV_TRANS_75  = 0x2,
+	OV_TRANS_62  = 0x3,
+	OV_TRANS_50  = 0x4,
+	OV_TRANS_37  = 0x5,
+	OV_TRANS_25  = 0x6,
+	OV_TRANS_12  = 0x7,
+	OV_TRANS_0   = 0xf
+};
+
+enum aklcd_osd_alpha {
+	OSD_TRANS_100 = 0x0,
+	OSD_TRANS_87  = 0x1,
+	OSD_TRANS_75  = 0x2,
+	OSD_TRANS_62  = 0x3,
+	OSD_TRANS_50  = 0x4,
+	OSD_TRANS_37  = 0x5,
+	OSD_TRANS_25  = 0x6,
+	OSD_TRANS_12  = 0x7,
+	OSD_TRANS_0   = 0x8
+};
+
+enum ak_tvout_mode{
+    TVOUT_OFF,
+    PAL,
+    NTSC
+};
+
+struct aklcd_overlay_channel {
+	enum aklcd_yuv_range src_range; /* only apply to overlay1 */
+	dma_addr_t           y_addr;
+	dma_addr_t           u_addr;
+	dma_addr_t           v_addr;
+	unsigned int         src_width;
+	unsigned int         src_height;
+
+	bool                 use_vpage;	  /* only apply to overlay1 */
+	unsigned int         vpage_width; /* width of ov1 rectangle */
+	unsigned int         vpage_height; /* height of ov1 rectangle */
+	unsigned int         virt_left;	/* src rect's left on ov1 */
+	unsigned int         virt_top; /* src rect's top on ov1 */
+
+	unsigned int         disp_left;
+	unsigned int         disp_top;
+	unsigned int         dst_width;
+	unsigned int         dst_height;
+
+	enum aklcd_ov_alpha  alpha; /* 0...7, 16, only apply to overlay2 */
+};
+
+typedef unsigned short int aklcd_osd_color;	/* rgb565 */
+
+struct aklcd_osd_channel {
+	dma_addr_t           data_addr;
+
+	aklcd_osd_color      palette[16]; /* palette[0] is for transparency */
+
+	unsigned int         disp_left;
+	unsigned int         disp_top;
+	unsigned int         width;
+	unsigned int         height;
+
+	enum aklcd_osd_alpha alpha; /* 0...8 */
+};
+#endif
+
+struct aklcd_overlay_info {
+	unsigned int         overlay_id; /* 0 for overlay1, 1 for overlay2 */
+	bool                 enable;
+	struct aklcd_overlay_channel overlay_setting;
+};
+
+struct aklcd_osd_info {
+	bool                 enable;
+	struct aklcd_osd_channel osd_setting;
+};
+
+#define FBIOPUT_AKOVINFO          _IOW('F', 0x80, struct aklcd_overlay_info)
+#define FBIOGET_AKOVINFO          _IOWR('F', 0x81, struct aklcd_overlay_info)
+#define FBIOPUT_AKOSDINFO         _IOW('F', 0x82, struct aklcd_osd_info)
+#define FBIOGET_AKOSDINFO         _IOR('F', 0x83, struct aklcd_osd_info)
+/* for android overlay hal control interface. enable is valid,
+   every member in aklcd_overlay_channel except [yuv]_addr and vpage is valid */
+#define FBIOPUT_AKOVPOSI          _IOW('F', 0x84, struct aklcd_overlay_info)
+/* for android overlay hal data interface. enable is valid,
+   [yuv]_addr in aklcd_overlay_channel is valid */
+#define FBIOPUT_AKOVDATA          _IOW('F', 0x85, struct aklcd_overlay_info)
+/* for anyka's android overlay hal extension.
+   enable == 0 means hide overlay, enable == 1 means show overlay again */
+#define FBIOPUT_AKOVSHOWING       _IOW('F', 0x86, struct aklcd_overlay_info)
+
+#define FBIOPUT_AKTVOUT       _IOW('F', 0x87, enum ak_tvout_mode)
+
+#endif
diff --git a/include/linux/akuio_driver.h b/include/linux/akuio_driver.h
new file mode 100644
index 00000000000..8f0d1f8b5d9
--- /dev/null
+++ b/include/linux/akuio_driver.h
@@ -0,0 +1,17 @@
+#ifndef _AKUIO_DRIVER_H
+#define _AKUIO_DRIVER_H
+
+struct akuio_sysreg_write_t
+{
+	unsigned int paddr;
+	unsigned int val;
+	unsigned int mask;
+};
+
+/* write system register */
+#define AKUIO_SYSREG_WRITE       _IOW('U', 100, struct akuio_sysreg_write_t)
+
+/* wait for a interrupt occur */
+#define AKUIO_WAIT_IRQ           _IOR('U', 101, int)
+
+#endif
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index 6b4241748dd..2e4f1cf64f5 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -5,6 +5,15 @@
 #define AMBA_MMCI_H
 
 #include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio_func.h>
+
+struct embedded_sdio_data {
+        struct sdio_cis cis;
+        struct sdio_cccr cccr;
+        struct sdio_embedded_func *funcs;
+        int num_funcs;
+};
 
 struct mmci_platform_data {
 	unsigned int ocr_mask;			/* available voltages */
@@ -13,6 +22,9 @@ struct mmci_platform_data {
 	int	gpio_wp;
 	int	gpio_cd;
 	unsigned long capabilities;
+	unsigned int status_irq;
+	struct embedded_sdio_data *embedded_sdio;
+	int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
 };
 
 #endif
diff --git a/include/linux/android_aid.h b/include/linux/android_aid.h
new file mode 100644
index 00000000000..7f16a14c0fe
--- /dev/null
+++ b/include/linux/android_aid.h
@@ -0,0 +1,26 @@
+/* include/linux/android_aid.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ANDROID_AID_H
+#define _LINUX_ANDROID_AID_H
+
+/* AIDs that the kernel treats differently */
+#define AID_NET_BT_ADMIN 3001
+#define AID_NET_BT       3002
+#define AID_INET         3003
+#define AID_NET_RAW      3004
+#define AID_NET_ADMIN    3005
+
+#endif
diff --git a/include/linux/android_alarm.h b/include/linux/android_alarm.h
new file mode 100644
index 00000000000..f8f14e793db
--- /dev/null
+++ b/include/linux/android_alarm.h
@@ -0,0 +1,106 @@
+/* include/linux/android_alarm.h
+ *
+ * Copyright (C) 2006-2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ANDROID_ALARM_H
+#define _LINUX_ANDROID_ALARM_H
+
+#include <linux/ioctl.h>
+#include <linux/time.h>
+
+enum android_alarm_type {
+	/* return code bit numbers or set alarm arg */
+	ANDROID_ALARM_RTC_WAKEUP,
+	ANDROID_ALARM_RTC,
+	ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
+	ANDROID_ALARM_ELAPSED_REALTIME,
+	ANDROID_ALARM_SYSTEMTIME,
+
+	ANDROID_ALARM_TYPE_COUNT,
+
+	/* return code bit numbers */
+	/* ANDROID_ALARM_TIME_CHANGE = 16 */
+};
+
+#ifdef __KERNEL__
+
+#include <linux/ktime.h>
+#include <linux/rbtree.h>
+
+/*
+ * The alarm interface is similar to the hrtimer interface but adds support
+ * for wakeup from suspend. It also adds an elapsed realtime clock that can
+ * be used for periodic timers that need to keep runing while the system is
+ * suspended and not be disrupted when the wall time is set.
+ */
+
+/**
+ * struct alarm - the basic alarm structure
+ * @node:	red black tree node for time ordered insertion
+ * @type:	alarm type. rtc/elapsed-realtime/systemtime, wakeup/non-wakeup.
+ * @softexpires: the absolute earliest expiry time of the alarm.
+ * @expires:	the absolute expiry time.
+ * @function:	alarm expiry callback function
+ *
+ * The alarm structure must be initialized by alarm_init()
+ *
+ */
+
+struct alarm {
+	struct rb_node 		node;
+	enum android_alarm_type type;
+	ktime_t			softexpires;
+	ktime_t			expires;
+	void			(*function)(struct alarm *);
+};
+
+void alarm_init(struct alarm *alarm,
+	enum android_alarm_type type, void (*function)(struct alarm *));
+void alarm_start_range(struct alarm *alarm, ktime_t start, ktime_t end);
+int alarm_try_to_cancel(struct alarm *alarm);
+int alarm_cancel(struct alarm *alarm);
+ktime_t alarm_get_elapsed_realtime(void);
+
+/* set rtc while preserving elapsed realtime */
+int alarm_set_rtc(const struct timespec ts);
+
+#endif
+
+enum android_alarm_return_flags {
+	ANDROID_ALARM_RTC_WAKEUP_MASK = 1U << ANDROID_ALARM_RTC_WAKEUP,
+	ANDROID_ALARM_RTC_MASK = 1U << ANDROID_ALARM_RTC,
+	ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK =
+				1U << ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
+	ANDROID_ALARM_ELAPSED_REALTIME_MASK =
+				1U << ANDROID_ALARM_ELAPSED_REALTIME,
+	ANDROID_ALARM_SYSTEMTIME_MASK = 1U << ANDROID_ALARM_SYSTEMTIME,
+	ANDROID_ALARM_TIME_CHANGE_MASK = 1U << 16
+};
+
+/* Disable alarm */
+#define ANDROID_ALARM_CLEAR(type)           _IO('a', 0 | ((type) << 4))
+
+/* Ack last alarm and wait for next */
+#define ANDROID_ALARM_WAIT                  _IO('a', 1)
+
+#define ALARM_IOW(c, type, size)            _IOW('a', (c) | ((type) << 4), size)
+/* Set alarm */
+#define ANDROID_ALARM_SET(type)             ALARM_IOW(2, type, struct timespec)
+#define ANDROID_ALARM_SET_AND_WAIT(type)    ALARM_IOW(3, type, struct timespec)
+#define ANDROID_ALARM_GET_TIME(type)        ALARM_IOW(4, type, struct timespec)
+#define ANDROID_ALARM_SET_RTC               _IOW('a', 5, struct timespec)
+#define ANDROID_ALARM_BASE_CMD(cmd)         (cmd & ~(_IOC(0, 0, 0xf0, 0)))
+#define ANDROID_ALARM_IOCTL_TO_TYPE(cmd)    (_IOC_NR(cmd) >> 4)
+
+#endif
diff --git a/include/linux/android_pmem.h b/include/linux/android_pmem.h
new file mode 100644
index 00000000000..f633621f5be
--- /dev/null
+++ b/include/linux/android_pmem.h
@@ -0,0 +1,93 @@
+/* include/linux/android_pmem.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _ANDROID_PMEM_H_
+#define _ANDROID_PMEM_H_
+
+#define PMEM_IOCTL_MAGIC 'p'
+#define PMEM_GET_PHYS		_IOW(PMEM_IOCTL_MAGIC, 1, unsigned int)
+#define PMEM_MAP		_IOW(PMEM_IOCTL_MAGIC, 2, unsigned int)
+#define PMEM_GET_SIZE		_IOW(PMEM_IOCTL_MAGIC, 3, unsigned int)
+#define PMEM_UNMAP		_IOW(PMEM_IOCTL_MAGIC, 4, unsigned int)
+/* This ioctl will allocate pmem space, backing the file, it will fail
+ * if the file already has an allocation, pass it the len as the argument
+ * to the ioctl */
+#define PMEM_ALLOCATE		_IOW(PMEM_IOCTL_MAGIC, 5, unsigned int)
+/* This will connect a one pmem file to another, pass the file that is already
+ * backed in memory as the argument to the ioctl
+ */
+#define PMEM_CONNECT		_IOW(PMEM_IOCTL_MAGIC, 6, unsigned int)
+/* Returns the total size of the pmem region it is sent to as a pmem_region
+ * struct (with offset set to 0). 
+ */
+#define PMEM_GET_TOTAL_SIZE	_IOW(PMEM_IOCTL_MAGIC, 7, unsigned int)
+#define PMEM_CACHE_FLUSH	_IOW(PMEM_IOCTL_MAGIC, 8, unsigned int)
+
+struct android_pmem_platform_data
+{
+	const char* name;
+	/* starting physical address of memory region */
+	unsigned long start;
+	/* size of memory region */
+	unsigned long size;
+	/* set to indicate the region should not be managed with an allocator */
+	unsigned no_allocator;
+	/* set to indicate maps of this region should be cached, if a mix of
+	 * cached and uncached is desired, set this and open the device with
+	 * O_SYNC to get an uncached region */
+	unsigned cached;
+	/* The MSM7k has bits to enable a write buffer in the bus controller*/
+	unsigned buffered;
+};
+
+struct pmem_region {
+	unsigned long offset;
+	unsigned long len;
+};
+
+#ifdef CONFIG_ANDROID_PMEM
+int is_pmem_file(struct file *file);
+int get_pmem_file(int fd, unsigned long *start, unsigned long *vstart,
+		  unsigned long *end, struct file **filp);
+int get_pmem_user_addr(struct file *file, unsigned long *start,
+		       unsigned long *end);
+void put_pmem_file(struct file* file);
+void flush_pmem_file(struct file *file, unsigned long start, unsigned long len);
+int pmem_setup(struct android_pmem_platform_data *pdata,
+	       long (*ioctl)(struct file *, unsigned int, unsigned long),
+	       int (*release)(struct inode *, struct file *));
+int pmem_remap(struct pmem_region *region, struct file *file,
+	       unsigned operation);
+
+#else
+static inline int is_pmem_file(struct file *file) { return 0; }
+static inline int get_pmem_file(int fd, unsigned long *start,
+				unsigned long *vstart, unsigned long *end,
+				struct file **filp) { return -ENOSYS; }
+static inline int get_pmem_user_addr(struct file *file, unsigned long *start,
+				     unsigned long *end) { return -ENOSYS; }
+static inline void put_pmem_file(struct file* file) { return; }
+static inline void flush_pmem_file(struct file *file, unsigned long start,
+				   unsigned long len) { return; }
+static inline int pmem_setup(struct android_pmem_platform_data *pdata,
+	      long (*ioctl)(struct file *, unsigned int, unsigned long),
+	      int (*release)(struct inode *, struct file *)) { return -ENOSYS; }
+
+static inline int pmem_remap(struct pmem_region *region, struct file *file,
+			     unsigned operation) { return -ENOSYS; }
+#endif
+
+#endif //_ANDROID_PPP_H_
+
diff --git a/include/linux/anyka_cpufreq.h b/include/linux/anyka_cpufreq.h
new file mode 100755
index 00000000000..35dda7bf2e3
--- /dev/null
+++ b/include/linux/anyka_cpufreq.h
@@ -0,0 +1,62 @@
+#ifndef __ANYKA_CPUFREQ_H
+#define __ANYKA_CPUFREQ_H
+
+typedef enum OPERATION_MODE {	
+	FREQ_MODE_MIN = 0,
+	LOW_MODE_CLOCK_MIN = 0,
+	LOW_MODE_CLOCK_0 = LOW_MODE_CLOCK_MIN,
+	LOW_MODE_CLOCK_1,
+	LOW_MODE_CLOCK_2,
+	LOW_MODE_CLOCK_3,
+	LOW_MODE_CLOCK_4,
+	LOW_MODE_CLOCK_5,
+	LOW_MODE_CLOCK_6,
+	LOW_MODE_CLOCK_7,
+	LOW_MODE_CLOCK_MAX = LOW_MODE_CLOCK_7,
+
+	NORMAL_MODE_CLOCK_MIN,
+	NORMAL_MODE_CLOCK_0 = NORMAL_MODE_CLOCK_MIN,
+	NORMAL_MODE_CLOCK_1,
+	NORMAL_MODE_CLOCK_2,
+	NORMAL_MODE_CLOCK_3,
+	NORMAL_MODE_CLOCK_4,
+	NORMAL_MODE_CLOCK_5,
+	NORMAL_MODE_CLOCK_6,
+	NORMAL_MODE_CLOCK_7,
+	NORMAL_MODE_CLOCK_MAX = NORMAL_MODE_CLOCK_7,
+
+	VIDEO_MODE_CLOCK_MIN,
+	VIDEO_MODE_CLOCK_0 = VIDEO_MODE_CLOCK_MIN,
+	VIDEO_MODE_CLOCK_1,
+	VIDEO_MODE_CLOCK_2,
+	VIDEO_MODE_CLOCK_3,
+	VIDEO_MODE_CLOCK_4,
+	VIDEO_MODE_CLOCK_5,
+	VIDEO_MODE_CLOCK_6,
+	VIDEO_MODE_CLOCK_7,
+	VIDEO_MODE_CLOCK_MAX = VIDEO_MODE_CLOCK_7,
+	FREQ_MODE_MAX = VIDEO_MODE_CLOCK_MAX,
+}T_OPERATION_MODE; 
+
+struct cpufreq_mode_clkkdiv {
+    T_OPERATION_MODE mode_name;
+    unsigned int pll_sel;
+    unsigned int clk168_div;
+	unsigned int cpu_div;
+	unsigned int mem_div;
+	unsigned int asic_div;
+	unsigned int low_clock;
+	unsigned int is_3x;
+};
+
+T_OPERATION_MODE get_current_mode(void);
+int request_cpufreq_enter(T_OPERATION_MODE mode);
+unsigned int get_pll_sel(T_OPERATION_MODE state);
+int is_low_clock_mode(void);
+int previous_mode_is_low_mode(void);
+int current_mode_is_low_mode(void);
+
+
+
+#endif /*  __ANYKA_CPUFREQ_H */
+
diff --git a/include/linux/ashmem.h b/include/linux/ashmem.h
new file mode 100644
index 00000000000..1976b10ef93
--- /dev/null
+++ b/include/linux/ashmem.h
@@ -0,0 +1,48 @@
+/*
+ * include/linux/ashmem.h
+ *
+ * Copyright 2008 Google Inc.
+ * Author: Robert Love
+ *
+ * This file is dual licensed.  It may be redistributed and/or modified
+ * under the terms of the Apache 2.0 License OR version 2 of the GNU
+ * General Public License.
+ */
+
+#ifndef _LINUX_ASHMEM_H
+#define _LINUX_ASHMEM_H
+
+#include <linux/limits.h>
+#include <linux/ioctl.h>
+
+#define ASHMEM_NAME_LEN		256
+
+#define ASHMEM_NAME_DEF		"dev/ashmem"
+
+/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */
+#define ASHMEM_NOT_PURGED	0
+#define ASHMEM_WAS_PURGED	1
+
+/* Return values from ASHMEM_GET_PIN_STATUS: Is the mapping pinned? */
+#define ASHMEM_IS_UNPINNED	0
+#define ASHMEM_IS_PINNED	1
+
+struct ashmem_pin {
+	__u32 offset;	/* offset into region, in bytes, page-aligned */
+	__u32 len;	/* length forward from offset, in bytes, page-aligned */
+};
+
+#define __ASHMEMIOC		0x77
+
+#define ASHMEM_SET_NAME		_IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN])
+#define ASHMEM_GET_NAME		_IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN])
+#define ASHMEM_SET_SIZE		_IOW(__ASHMEMIOC, 3, size_t)
+#define ASHMEM_GET_SIZE		_IO(__ASHMEMIOC, 4)
+#define ASHMEM_SET_PROT_MASK	_IOW(__ASHMEMIOC, 5, unsigned long)
+#define ASHMEM_GET_PROT_MASK	_IO(__ASHMEMIOC, 6)
+#define ASHMEM_PIN		_IOW(__ASHMEMIOC, 7, struct ashmem_pin)
+#define ASHMEM_UNPIN		_IOW(__ASHMEMIOC, 8, struct ashmem_pin)
+#define ASHMEM_GET_PIN_STATUS	_IO(__ASHMEMIOC, 9)
+#define ASHMEM_PURGE_ALL_CACHES	_IO(__ASHMEMIOC, 10)
+
+#endif	/* _LINUX_ASHMEM_H */
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 79a2340d83c..6a9739019ab 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -123,11 +123,25 @@ struct cpufreq_policy {
 #define CPUFREQ_RESUMECHANGE	(8)
 #define CPUFREQ_SUSPENDCHANGE	(9)
 
+#ifdef CONFIG_CPU_FREQ
+struct cpufreq_operation {
+	unsigned int cpu_clk;
+	unsigned int mem_clk;
+	unsigned int asic_clk;
+	unsigned int pll_sel;
+	unsigned int low_clock;
+};
+#endif
+
 struct cpufreq_freqs {
 	unsigned int cpu;	/* cpu nr */
 	unsigned int old;
 	unsigned int new;
 	u8 flags;		/* flags of cpufreq_driver, see below. */
+#ifdef CONFIG_CPU_FREQ
+	struct cpufreq_operation new_cpufreq;
+	struct cpufreq_operation old_cpufreq;
+#endif
 };
 
 
diff --git a/include/linux/earlysuspend.h b/include/linux/earlysuspend.h
new file mode 100755
index 00000000000..8343b817af3
--- /dev/null
+++ b/include/linux/earlysuspend.h
@@ -0,0 +1,56 @@
+/* include/linux/earlysuspend.h
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_EARLYSUSPEND_H
+#define _LINUX_EARLYSUSPEND_H
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/list.h>
+#endif
+
+/* The early_suspend structure defines suspend and resume hooks to be called
+ * when the user visible sleep state of the system changes, and a level to
+ * control the order. They can be used to turn off the screen and input
+ * devices that are not used for wakeup.
+ * Suspend handlers are called in low to high level order, resume handlers are
+ * called in the opposite order. If, when calling register_early_suspend,
+ * the suspend handlers have already been called without a matching call to the
+ * resume handlers, the suspend handler will be called directly from
+ * register_early_suspend. This direct call can violate the normal level order.
+ */
+enum {
+	EARLY_SUSPEND_LEVEL_BLANK_SCREEN = 50,
+	EARLY_SUSPEND_LEVEL_STOP_DRAWING = 100,
+	EARLY_SUSPEND_LEVEL_DISABLE_FB = 150,
+};
+struct early_suspend {
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct list_head link;
+	int level;
+	void (*suspend)(struct early_suspend *h);
+	void (*resume)(struct early_suspend *h);
+#endif
+};
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void register_early_suspend(struct early_suspend *handler);
+void unregister_early_suspend(struct early_suspend *handler);
+#else
+#define register_early_suspend(handler) do { } while (0)
+#define unregister_early_suspend(handler) do { } while (0)
+#endif
+
+#endif
+
diff --git a/include/linux/fb.h b/include/linux/fb.h
index de9c722e7b9..64d7b8ee353 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -544,6 +544,13 @@ struct fb_cursor_user {
 /*      Unbind from the console if possible */
 #define FB_EVENT_FB_UNBIND              0x0E
 
+/*
+ * Framebuffer events which support cpu frequency changing
+ */
+#define FB_EVENT_PRE_CPUFREQ			0x0F
+#define FB_EVENT_POST_CPUFREQ			0x10
+
+
 struct fb_event {
 	struct fb_info *info;
 	void *data;
diff --git a/include/linux/freezer.h b/include/linux/freezer.h
index 5a361f85cfe..f0a5cab1693 100644
--- a/include/linux/freezer.h
+++ b/include/linux/freezer.h
@@ -49,6 +49,7 @@ extern int thaw_process(struct task_struct *p);
 
 extern void refrigerator(void);
 extern int freeze_processes(void);
+extern int cpufreq_freeze_processes(void);
 extern void thaw_processes(void);
 
 static inline int try_to_freeze(void)
@@ -169,6 +170,7 @@ static inline int thaw_process(struct task_struct *p) { return 1; }
 
 static inline void refrigerator(void) {}
 static inline int freeze_processes(void) { BUG(); return 0; }
+static inline int cpufreq_freeze_processes(void) { BUG(); return 0; }
 static inline void thaw_processes(void) {}
 
 static inline int try_to_freeze(void) { return 0; }
diff --git a/include/linux/gpio_event.h b/include/linux/gpio_event.h
new file mode 100644
index 00000000000..360b4ddb46a
--- /dev/null
+++ b/include/linux/gpio_event.h
@@ -0,0 +1,169 @@
+/* include/linux/gpio_event.h
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_GPIO_EVENT_H
+#define _LINUX_GPIO_EVENT_H
+
+#include <linux/input.h>
+
+struct gpio_event_input_devs {
+	int count;
+	struct input_dev *dev[];
+};
+enum {
+	GPIO_EVENT_FUNC_UNINIT  = 0x0,
+	GPIO_EVENT_FUNC_INIT    = 0x1,
+	GPIO_EVENT_FUNC_SUSPEND = 0x2,
+	GPIO_EVENT_FUNC_RESUME  = 0x3,
+};
+struct gpio_event_info {
+	int (*func)(struct gpio_event_input_devs *input_devs,
+		    struct gpio_event_info *info,
+		    void **data, int func);
+	int (*event)(struct gpio_event_input_devs *input_devs,
+		     struct gpio_event_info *info,
+		     void **data, unsigned int dev, unsigned int type,
+		     unsigned int code, int value); /* out events */
+	bool no_suspend;
+};
+
+struct gpio_event_platform_data {
+	const char *name;
+	struct gpio_event_info **info;
+	size_t info_count;
+	int (*power)(const struct gpio_event_platform_data *pdata, bool on);
+	const char *names[]; /* If name is NULL, names contain a NULL */
+			     /* terminated list of input devices to create */
+};
+
+#define GPIO_EVENT_DEV_NAME "gpio-event"
+
+/* Key matrix */
+
+enum gpio_event_matrix_flags {
+	/* unset: drive active output low, set: drive active output high */
+	GPIOKPF_ACTIVE_HIGH              = 1U << 0,
+	GPIOKPF_DEBOUNCE                 = 1U << 1,
+	GPIOKPF_REMOVE_SOME_PHANTOM_KEYS = 1U << 2,
+	GPIOKPF_REMOVE_PHANTOM_KEYS      = GPIOKPF_REMOVE_SOME_PHANTOM_KEYS |
+					   GPIOKPF_DEBOUNCE,
+	GPIOKPF_DRIVE_INACTIVE           = 1U << 3,
+	GPIOKPF_LEVEL_TRIGGERED_IRQ      = 1U << 4,
+	GPIOKPF_PRINT_UNMAPPED_KEYS      = 1U << 16,
+	GPIOKPF_PRINT_MAPPED_KEYS        = 1U << 17,
+	GPIOKPF_PRINT_PHANTOM_KEYS       = 1U << 18,
+};
+
+#define MATRIX_CODE_BITS (10)
+#define MATRIX_KEY_MASK ((1U << MATRIX_CODE_BITS) - 1)
+#define MATRIX_KEY(dev, code) \
+	(((dev) << MATRIX_CODE_BITS) | (code & MATRIX_KEY_MASK))
+
+extern int gpio_event_matrix_func(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data, int func);
+struct gpio_event_matrix_info {
+	/* initialize to gpio_event_matrix_func */
+	struct gpio_event_info info;
+	/* size must be ninputs * noutputs */
+	const unsigned short *keymap;
+	unsigned int *input_gpios;
+	unsigned int *output_gpios;
+	unsigned int ninputs;
+	unsigned int noutputs;
+	/* time to wait before reading inputs after driving each output */
+	ktime_t settle_time;
+	/* time to wait before scanning the keypad a second time */
+	ktime_t debounce_delay;
+	ktime_t poll_time;
+	unsigned flags;
+};
+
+/* Directly connected inputs and outputs */
+
+enum gpio_event_direct_flags {
+	GPIOEDF_ACTIVE_HIGH         = 1U << 0,
+/*	GPIOEDF_USE_DOWN_IRQ        = 1U << 1, */
+/*	GPIOEDF_USE_IRQ             = (1U << 2) | GPIOIDF_USE_DOWN_IRQ, */
+	GPIOEDF_PRINT_KEYS          = 1U << 8,
+	GPIOEDF_PRINT_KEY_DEBOUNCE  = 1U << 9,
+};
+
+struct gpio_event_direct_entry {
+	uint32_t gpio:16;
+	uint32_t code:10;
+	uint32_t dev:6;
+};
+
+/* inputs */
+extern int gpio_event_input_func(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data, int func);
+struct gpio_event_input_info {
+	/* initialize to gpio_event_input_func */
+	struct gpio_event_info info;
+	ktime_t debounce_time;
+	ktime_t poll_time;
+	uint16_t flags;
+	uint16_t type;
+	const struct gpio_event_direct_entry *keymap;
+	size_t keymap_size;
+};
+
+/* outputs */
+extern int gpio_event_output_func(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data, int func);
+extern int gpio_event_output_event(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data,
+			unsigned int dev, unsigned int type,
+			unsigned int code, int value);
+struct gpio_event_output_info {
+	/* initialize to gpio_event_output_func and gpio_event_output_event */
+	struct gpio_event_info info;
+	uint16_t flags;
+	uint16_t type;
+	const struct gpio_event_direct_entry *keymap;
+	size_t keymap_size;
+};
+
+
+/* axes */
+
+enum gpio_event_axis_flags {
+	GPIOEAF_PRINT_UNKNOWN_DIRECTION  = 1U << 16,
+	GPIOEAF_PRINT_RAW                = 1U << 17,
+	GPIOEAF_PRINT_EVENT              = 1U << 18,
+};
+
+extern int gpio_event_axis_func(struct gpio_event_input_devs *input_devs,
+			struct gpio_event_info *info, void **data, int func);
+struct gpio_event_axis_info {
+	/* initialize to gpio_event_axis_func */
+	struct gpio_event_info info;
+	uint8_t  count; /* number of gpios for this axis */
+	uint8_t  dev; /* device index when using multiple input devices */
+	uint8_t  type; /* EV_REL or EV_ABS */
+	uint16_t code;
+	uint16_t decoded_size;
+	uint16_t (*map)(struct gpio_event_axis_info *info, uint16_t in);
+	uint32_t *gpio;
+	uint32_t flags;
+};
+#define gpio_axis_2bit_gray_map gpio_axis_4bit_gray_map
+#define gpio_axis_3bit_gray_map gpio_axis_4bit_gray_map
+uint16_t gpio_axis_4bit_gray_map(
+			struct gpio_event_axis_info *info, uint16_t in);
+uint16_t gpio_axis_5bit_singletrack_map(
+			struct gpio_event_axis_info *info, uint16_t in);
+
+#endif
diff --git a/include/linux/i2c/aw9523.h b/include/linux/i2c/aw9523.h
new file mode 100755
index 00000000000..33c1f59071a
--- /dev/null
+++ b/include/linux/i2c/aw9523.h
@@ -0,0 +1,117 @@
+#ifndef __AW9523_H_
+#define __AW9523_H_
+
+#include <mach/gpio.h>
+#include <linux/mutex.h>
+#include <linux/i2c.h>
+
+
+/*
+ * AW9523 registers
+ */
+#define AW9523_REG_INPUT_PORT0	0x00
+#define AW9523_REG_INPUT_PORT1	0x01
+#define AW9523_REG_OUTPUT_PORT0	0x02
+#define AW9523_REG_OUTPUT_PORT1	0x03
+#define AW9523_REG_CFG_PORT0	0x04
+#define AW9523_REG_CFG_PORT1	0x05
+#define AW9523_REG_INTN_PORT0	0x06
+#define AW9523_REG_INTN_PORT1	0x07
+#define AW9523_REG_GPOMD		0x11
+#define AW9523_REG_RESET		0x7F
+
+/*
+ * operation flags
+ */
+/*  mode */
+#define AW9523_MOD_OPENDRAIN	0
+#define AW9523_MOD_PUSHPULL	1
+
+
+
+/*
+* pin definitions 
+*/
+enum {
+	PMIN=0,
+	P00 = PMIN,
+	P01,P02,P03,P04,P05,P06,P07,
+	P10,P11,P12,P13,P14,P15,P16,P17,
+	PMAX = P17,
+};
+
+
+/* platform data for the AW9523 16-bit I/O expander driver */
+
+struct aw9523_platform_data {
+	/* number of the first GPIO */
+	unsigned	gpio_base;
+	unsigned	irq_base;
+
+	unsigned int parent_irq;
+	struct gpio_info *gpios;
+	int npins;
+
+	uint8_t		p0xmod;
+	/* initial polarity inversion setting */
+	uint16_t	invert;
+
+	void		*context;	/* param to setup/teardown */
+
+	int		(*setup)(struct i2c_client *client,
+				unsigned gpio, unsigned ngpio,
+				void *context);
+	int		(*teardown)(struct i2c_client *client,
+				unsigned gpio, unsigned ngpio,
+				void *context);
+	char		**names;
+};
+
+struct aw9523_chip {
+	uint8_t reg_output0;	/* AW9523 Port 0 output value */
+	uint8_t reg_output1;	/* AW9523 Port 1 output value */
+	uint8_t reg_direction0;	/* AW9523 Port 0 direction: */
+	uint8_t reg_direction1;	/* AW9523 Port 1 direction: */
+	uint8_t reg_setmod;		/* AW9523 Port 0 mode: */
+	uint8_t reg_int0;
+	uint8_t reg_int1;
+	uint8_t reg_input0;
+	uint8_t reg_input1;
+	
+	struct i2c_client *client;
+
+	uint8_t irq_mask0;
+	uint8_t irq_mask1;
+
+	struct mutex aw9523_lock;
+	struct aw9523_platform_data *pdata;
+	
+};
+
+
+int aw9523_gpio_to_irq(unsigned int pino);
+int aw9523_irq_to_gpio(unsigned int irq);
+
+/*function: set gpio direction 
+ * param pinno: pin number
+ * param direction:
+ *	1: input mode,  0: output mode
+ */
+int aw9523_gpio_dircfg(unsigned int pino, unsigned int direction);
+
+int aw9523_gpio_intcfg(unsigned int pino, unsigned int enable);
+
+/* function: get pin state
+ * param pino: pin number
+ */
+int aw9523_gpio_getpin(unsigned int pino);
+
+/* function : setup output value
+ * param pino: pin number
+ * param level: 
+ *	1: output high level, 0: ouput low level
+ */
+int aw9523_gpio_setpin(unsigned int pino, unsigned int level);
+
+#endif  /* __AW9523_H */
+
diff --git a/include/linux/i2c/cp2007.h b/include/linux/i2c/cp2007.h
new file mode 100755
index 00000000000..9b200d0d095
--- /dev/null
+++ b/include/linux/i2c/cp2007.h
@@ -0,0 +1,32 @@
+#ifndef __LINUX_I2C_CP2007_H
+#define __LINUX_I2C_CP2007_H
+
+#include <linux/swab.h>
+
+enum {
+	ORIGIN_TOPLEFT = 1,
+	ORIGIN_BOTTOMLEFT,
+	ORIGIN_TOPRIGHT,
+	ORIGIN_BOTTOMRIGHT,
+};
+
+struct cp2007_intpin_info {
+	unsigned int pin;
+	char pulldown;  //pulldown function flag
+	char pullup;    //pullup function flag
+	char dir;       //direction  input/output
+	char int_pol;   //interrupt polarity
+};
+
+struct cp2007_ts_platform_data {
+	u16	x_plate_ohms;
+	char origin_pos;
+	struct cp2007_intpin_info intpin_info;
+	int	(*is_pen_down)(unsigned int pin);
+	void (*clear_penirq)(void);		/* If needed, clear 2nd level interrupt source */
+	void (*init_ts_hw)(const struct cp2007_intpin_info *intpin_info);
+	void (*exit_ts_hw)(void);
+};
+
+
+#endif /* __LINUX_I2C_CP2007_H */
diff --git a/include/linux/if_pppolac.h b/include/linux/if_pppolac.h
new file mode 100644
index 00000000000..8d827ea6642
--- /dev/null
+++ b/include/linux/if_pppolac.h
@@ -0,0 +1,35 @@
+/* include/linux/if_pppolac.h
+ *
+ * Header for PPP on L2TP Access Concentrator / PPPoLAC Socket (RFC 2661)
+ *
+ * Copyright (C) 2009 Google, Inc.
+ * Author: Chia-chi Yeh <chiachi@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_IF_PPPOLAC_H
+#define __LINUX_IF_PPPOLAC_H
+
+#include <linux/socket.h>
+#include <linux/types.h>
+
+#define PX_PROTO_OLAC	2
+
+struct sockaddr_pppolac {
+	sa_family_t	sa_family;	/* AF_PPPOX */
+	unsigned int	sa_protocol;	/* PX_PROTO_OLAC */
+	int		udp_socket;
+	struct __attribute__((packed)) {
+		__u16	tunnel, session;
+	} local, remote;
+} __attribute__((packed));
+
+#endif /* __LINUX_IF_PPPOLAC_H */
diff --git a/include/linux/if_pppopns.h b/include/linux/if_pppopns.h
new file mode 100644
index 00000000000..305d4c40459
--- /dev/null
+++ b/include/linux/if_pppopns.h
@@ -0,0 +1,34 @@
+/* include/linux/if_pppopns.h
+ *
+ * Header for PPP on PPTP Network Server / PPPoPNS Socket (RFC 2637)
+ *
+ * Copyright (C) 2009 Google, Inc.
+ * Author: Chia-chi Yeh <chiachi@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_IF_PPPOPNS_H
+#define __LINUX_IF_PPPOPNS_H
+
+#include <linux/socket.h>
+#include <linux/types.h>
+
+#define PX_PROTO_OPNS	3
+
+struct sockaddr_pppopns {
+	sa_family_t	sa_family;	/* AF_PPPOX */
+	unsigned int	sa_protocol;	/* PX_PROTO_OPNS */
+	int		tcp_socket;
+	__u16		local;
+	__u16		remote;
+} __attribute__((packed));
+
+#endif /* __LINUX_IF_PPPOPNS_H */
diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h
index 90b5fae5d71..9f581dab63b 100644
--- a/include/linux/if_pppox.h
+++ b/include/linux/if_pppox.h
@@ -27,6 +27,8 @@
 #include <linux/ppp_channel.h>
 #endif /* __KERNEL__ */
 #include <linux/if_pppol2tp.h>
+#include <linux/if_pppolac.h>
+#include <linux/if_pppopns.h>
 
 /* For user-space programs to pick up these definitions
  * which they wouldn't get otherwise without defining __KERNEL__
@@ -51,7 +53,9 @@ struct pppoe_addr{
  */ 
 #define PX_PROTO_OE    0 /* Currently just PPPoE */
 #define PX_PROTO_OL2TP 1 /* Now L2TP also */
-#define PX_MAX_PROTO   2
+#define PX_PROTO_OLAC  2
+#define PX_PROTO_OPNS  3
+#define PX_MAX_PROTO   4
 
 struct sockaddr_pppox { 
        sa_family_t     sa_family;            /* address family, AF_PPPOX */ 
@@ -141,6 +145,22 @@ struct pppoe_opt {
 					     relayed to (PPPoE relaying) */
 };
 
+struct pppolac_opt {
+	__u32	local;
+	__u32	remote;
+	__u16	sequence;
+	__u8	sequencing;
+	int	(*backlog_rcv)(struct sock *sk_udp, struct sk_buff *skb);
+};
+
+struct pppopns_opt {
+	__u16	local;
+	__u16	remote;
+	__u32	sequence;
+	void	(*data_ready)(struct sock *sk_raw, int length);
+	int	(*backlog_rcv)(struct sock *sk_raw, struct sk_buff *skb);
+};
+
 #include <net/sock.h>
 
 struct pppox_sock {
@@ -150,6 +170,8 @@ struct pppox_sock {
 	struct pppox_sock	*next;	  /* for hash table */
 	union {
 		struct pppoe_opt pppoe;
+		struct pppolac_opt lac;
+		struct pppopns_opt pns;
 	} proto;
 	__be16			num;
 };
diff --git a/include/linux/input/ak98matrix_keypad.h b/include/linux/input/ak98matrix_keypad.h
new file mode 100755
index 00000000000..ffb65821b69
--- /dev/null
+++ b/include/linux/input/ak98matrix_keypad.h
@@ -0,0 +1,105 @@
+#ifndef _MATRIX_KEYPAD_H
+#define _MATRIX_KEYPAD_H
+
+#include <linux/types.h>
+#include <linux/input.h>
+#include <mach/gpio.h>
+
+#define MATRIX_MAX_ROWS		16
+#define MATRIX_MAX_COLS		16
+
+#define KEY(row, col, val)	((((row) & (MATRIX_MAX_ROWS - 1)) << 24) |\
+				 (((col) & (MATRIX_MAX_COLS - 1)) << 16) |\
+				 (val & 0xffff))
+
+#define KEY_ROW(k)		(((k) >> 24) & 0xff)
+#define KEY_COL(k)		(((k) >> 16) & 0xff)
+#define KEY_VAL(k)		((k) & 0xffff)
+
+#define MATRIX_SCAN_CODE(row, col, row_shift)	(((row) << (row_shift)) + (col))
+
+/**
+ * struct matrix_keymap_data - keymap for matrix keyboards
+ * @keymap: pointer to array of uint32 values encoded with KEY() macro
+ *	representing keymap
+ * @keymap_size: number of entries (initialized) in this keymap
+ *
+ * This structure is supposed to be used by platform code to supply
+ * keymaps to drivers that implement matrix-like keypads/keyboards.
+ */
+struct matrix_keymap_data {
+	const uint32_t *keymap;
+	unsigned int	keymap_size;
+};
+
+/**
+ * struct matrix_keypad_platform_data - platform-dependent keypad data
+ * @keymap_data: pointer to &matrix_keymap_data
+ * @row_gpios: pointer to array of gpio numbers representing rows
+ * @col_gpios: pointer to array of gpio numbers reporesenting colums
+ * @num_row_gpios: actual number of row gpios used by device
+ * @num_col_gpios: actual number of col gpios used by device
+ * @col_scan_delay_us: delay, measured in microseconds, that is
+ *	needed before we can keypad after activating column gpio
+ * @debounce_ms: debounce interval in milliseconds
+ *
+ * This structure represents platform-specific data that use used by
+ * matrix_keypad driver to perform proper initialization.
+ */
+struct matrix_keypad_platform_data {
+	const struct matrix_keymap_data *keymap_data;
+
+	const unsigned int *row_gpios;
+	const unsigned int *col_gpios;
+	
+	unsigned int	num_row_gpios;
+	unsigned int	num_col_gpios;
+
+	unsigned int	col_scan_delay_us;
+
+	/* key debounce interval in milli-second */
+	unsigned int	debounce_ms;
+
+	bool		active_low;
+	bool		wakeup;
+
+	/* add for ak98 */
+	struct gpio_info row_gpios_cfginfo;
+	struct gpio_info col_gpios_cfginfo;
+	/* true: one column selecting line is grounded */
+	bool		grounding;
+};
+
+/**
+ * matrix_keypad_build_keymap - convert platform keymap into matrix keymap
+ * @keymap_data: keymap supplied by the platform code
+ * @row_shift: number of bits to shift row value by to advance to the next
+ * line in the keymap
+ * @keymap: expanded version of keymap that is suitable for use by
+ * matrix keyboad driver
+ * @keybit: pointer to bitmap of keys supported by input device
+ *
+ * This function converts platform keymap (encoded with KEY() macro) into
+ * an array of keycodes that is suitable for using in a standard matrix
+ * keyboard driver that uses row and col as indices.
+ */
+static inline void
+matrix_keypad_build_keymap(const struct matrix_keymap_data *keymap_data,
+			   unsigned int row_shift,
+			   unsigned short *keymap, unsigned long *keybit)
+{
+	int i;
+
+	for (i = 0; i < keymap_data->keymap_size; i++) {
+		unsigned int key = keymap_data->keymap[i];
+		unsigned int row = KEY_ROW(key);
+		unsigned int col = KEY_COL(key);
+		unsigned short code = KEY_VAL(key);
+
+		keymap[MATRIX_SCAN_CODE(row, col, row_shift)] = code;
+		__set_bit(code, keybit);
+	}
+	__clear_bit(KEY_RESERVED, keybit);
+}
+
+#endif /* _MATRIX_KEYPAD_H */
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index 7ca72b74eec..76a0ac26f0c 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -18,6 +18,7 @@
 #include <asm/atomic.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
+#include <mach/irqs.h>
 
 /*
  * These correspond to the IORESOURCE_IRQ_* defines in
@@ -117,6 +118,10 @@ static inline int __must_check
 request_irq(unsigned int irq, irq_handler_t handler, unsigned long flags,
 	    const char *name, void *dev)
 {
+	if (irq >= IRQ_AW9523_P00 && irq <= IRQ_AW9523_P17)
+	{		
+		return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT, name, dev);
+	}
 	return request_threaded_irq(irq, handler, NULL, flags, name, dev);
 }
 
diff --git a/include/linux/kernel_debugger.h b/include/linux/kernel_debugger.h
new file mode 100644
index 00000000000..b4dbfe99d79
--- /dev/null
+++ b/include/linux/kernel_debugger.h
@@ -0,0 +1,41 @@
+/*
+ * include/linux/kernel_debugger.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_KERNEL_DEBUGGER_H_
+#define _LINUX_KERNEL_DEBUGGER_H_
+
+struct kdbg_ctxt {
+	int (*printf)(void *cookie, const char *fmt, ...);
+	void *cookie;
+};
+
+/* kernel_debugger() is called from IRQ context and should
+ * use the kdbg_ctxt.printf to write output (do NOT call
+ * printk, do operations not safe from IRQ context, etc).
+ *
+ * kdbg_ctxt.printf will return -1 if there is not enough
+ * buffer space or if you are being aborted.  In this case
+ * you must return as soon as possible.
+ *
+ * Return non-zero if more data is available -- if buffer
+ * space ran and you had to stop, but could print more,
+ * for example.
+ *
+ * Additional calls where cmd is "more" will be made if
+ * the additional data is desired.
+ */
+int kernel_debugger(struct kdbg_ctxt *ctxt, char *cmd);
+
+#endif
diff --git a/include/linux/keychord.h b/include/linux/keychord.h
new file mode 100644
index 00000000000..856a5850217
--- /dev/null
+++ b/include/linux/keychord.h
@@ -0,0 +1,52 @@
+/*
+ *  Key chord input driver
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#ifndef __LINUX_KEYCHORD_H_
+#define __LINUX_KEYCHORD_H_
+
+#include <linux/input.h>
+
+#define KEYCHORD_VERSION		1
+
+/*
+ * One or more input_keychord structs are written to /dev/keychord
+ * at once to specify the list of keychords to monitor.
+ * Reading /dev/keychord returns the id of a keychord when the
+ * keychord combination is pressed.  A keychord is signalled when
+ * all of the keys in the keycode list are in the pressed state.
+ * The order in which the keys are pressed does not matter.
+ * The keychord will not be signalled if keys not in the keycode
+ * list are pressed.
+ * Keychords will not be signalled on key release events.
+ */
+struct input_keychord {
+	/* should be KEYCHORD_VERSION */
+	__u16 version;
+	/*
+	 * client specified ID, returned from read()
+	 * when this keychord is pressed.
+	 */
+	__u16 id;
+
+	/* number of keycodes in this keychord */
+	__u16 count;
+
+	/* variable length array of keycodes */
+	__u16 keycodes[];
+};
+
+#endif	/* __LINUX_KEYCHORD_H_ */
diff --git a/include/linux/keyreset.h b/include/linux/keyreset.h
new file mode 100644
index 00000000000..50c4b952b8f
--- /dev/null
+++ b/include/linux/keyreset.h
@@ -0,0 +1,27 @@
+/*
+ * include/linux/keyreset.h - platform data structure for resetkeys driver
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_KEYRESET_H
+#define _LINUX_KEYRESET_H
+
+#define KEYRESET_NAME "keyreset"
+
+struct keyreset_platform_data {
+	int *keys_up;
+	int keys_down[]; /* 0 terminated */
+};
+
+#endif /* _LINUX_KEYRESET_H */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 24c395694f4..397a3774e6e 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -713,6 +713,7 @@ extern void show_free_areas(void);
 
 int shmem_lock(struct file *file, int lock, struct user_struct *user);
 struct file *shmem_file_setup(const char *name, loff_t size, unsigned long flags);
+void shmem_set_file(struct vm_area_struct *vma, struct file *file);
 int shmem_zero_setup(struct vm_area_struct *);
 
 #ifndef CONFIG_MMU
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index eaf36364b7d..c3b88ff5654 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -193,6 +193,10 @@ struct mmc_host {
 	const struct mmc_bus_ops *bus_ops;	/* current bus driver */
 	unsigned int		bus_refs;	/* reference counter */
 
+	unsigned int		bus_resume_flags;
+#define MMC_BUSRESUME_MANUAL_RESUME	(1 << 0)
+#define MMC_BUSRESUME_NEEDS_RESUME	(1 << 1)
+
 	unsigned int		sdio_irqs;
 	struct task_struct	*sdio_irq_thread;
 	atomic_t		sdio_irq_thread_abort;
@@ -203,6 +207,15 @@ struct mmc_host {
 
 	struct dentry		*debugfs_root;
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	struct {
+		struct sdio_cis			*cis;
+		struct sdio_cccr		*cccr;
+		struct sdio_embedded_func	*funcs;
+		int				num_funcs;
+	} embedded_sdio_data;
+#endif
+
 	unsigned long		private[0] ____cacheline_aligned;
 };
 
@@ -211,6 +224,14 @@ extern int mmc_add_host(struct mmc_host *);
 extern void mmc_remove_host(struct mmc_host *);
 extern void mmc_free_host(struct mmc_host *);
 
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+extern void mmc_set_embedded_sdio_data(struct mmc_host *host,
+				       struct sdio_cis *cis,
+				       struct sdio_cccr *cccr,
+				       struct sdio_embedded_func *funcs,
+				       int num_funcs);
+#endif
+
 static inline void *mmc_priv(struct mmc_host *host)
 {
 	return (void *)host->private;
@@ -221,6 +242,17 @@ static inline void *mmc_priv(struct mmc_host *host)
 #define mmc_dev(x)	((x)->parent)
 #define mmc_classdev(x)	(&(x)->class_dev)
 #define mmc_hostname(x)	(dev_name(&(x)->class_dev))
+#define mmc_bus_needs_resume(host) ((host)->bus_resume_flags & MMC_BUSRESUME_NEEDS_RESUME)
+
+static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual)
+{
+	if (manual)
+		host->bus_resume_flags |= MMC_BUSRESUME_MANUAL_RESUME;
+	else
+		host->bus_resume_flags &= ~MMC_BUSRESUME_MANUAL_RESUME;
+}
+
+extern int mmc_resume_bus(struct mmc_host *host);
 
 extern int mmc_suspend_host(struct mmc_host *, pm_message_t);
 extern int mmc_resume_host(struct mmc_host *);
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index ac3ab683fec..1ebd07e756e 100644..100755
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
@@ -21,6 +21,14 @@ struct sdio_func;
 typedef void (sdio_irq_handler_t)(struct sdio_func *);
 
 /*
+ * Structure used to hold embedded SDIO device data from platform layer
+ */
+struct sdio_embedded_func {
+	uint8_t f_class;
+	uint32_t f_maxblksize;
+};
+
+/*
  * SDIO function CIS tuple (unknown to the core)
  */
 struct sdio_func_tuple {
@@ -128,6 +136,8 @@ extern int sdio_release_irq(struct sdio_func *func);
 extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz);
 
 extern u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret);
+extern u8 sdio_readb_ext(struct sdio_func *func, unsigned int addr, int *err_ret,
+	unsigned in);
 extern u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret);
 extern u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret);
 
diff --git a/include/linux/mmc328x.h b/include/linux/mmc328x.h
new file mode 100755
index 00000000000..3d21498a1e4
--- /dev/null
+++ b/include/linux/mmc328x.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ *	Dale Hou
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+/*
+ * Definitions for mmc328x magnetic sensor chip.
+ */
+#ifndef __MMC328X_H__
+#define __MMC328X_H__
+
+#include <linux/ioctl.h>
+
+#define MMC328X_I2C_NAME		"mmc328x"
+
+/*
+ * This address comes must match the part# on your target.
+ * Address to the sensor part# support as following list:
+ *	MMC3280MS - 0110000b
+ *	MMC3281MS - 0110001b
+ *	MMC3282MS - 0110010b
+ *	MMC3283MS - 0110011b
+ *	MMC3284MS - 0110100b
+ *	MMC3285MS - 0110101b
+ *	MMC3286MS - 0110110b
+ *	MMC3287MS - 0110111b
+ * Please refer to sensor datasheet for detail.
+ */
+#define MMC328X_I2C_ADDR		0x30
+
+/* MMC328X register address */
+#define MMC328X_REG_CTRL		0x07
+#define MMC328X_REG_DATA		0x00
+#define MMC328X_REG_DS			0x06
+
+/* MMC328X control bit */
+#define MMC328X_CTRL_TM			0x01
+#define MMC328X_CTRL_RM			0x20
+
+/* Use 'm' as magic number */
+#define MMC328X_IOM			'm'
+
+/* IOCTLs for MMC328X device */
+#define MMC328X_IOC_TM			_IO (MMC328X_IOM, 0x00)
+#define MMC328X_IOC_RM			_IO (MMC328X_IOM, 0x01)
+#define MMC328X_IOC_READ		_IOR(MMC328X_IOM, 0x02, int[3])
+#define MMC328X_IOC_READXYZ		_IOR(MMC328X_IOM, 0x03, int[3])
+
+#endif /* __MMC328X_H__ */
+
diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
index ce38f1caa5e..844d77ddfb3 100644
--- a/include/linux/msdos_fs.h
+++ b/include/linux/msdos_fs.h
@@ -100,6 +100,7 @@ struct __fat_dirent {
 /* <linux/videotext.h> has used 0x72 ('r') in collision, so skip a few */
 #define FAT_IOCTL_GET_ATTRIBUTES	_IOR('r', 0x10, __u32)
 #define FAT_IOCTL_SET_ATTRIBUTES	_IOW('r', 0x11, __u32)
+#define VFAT_IOCTL_GET_VOLUME_ID	_IOR('r', 0x12, __u32)
 
 struct fat_boot_sector {
 	__u8	ignored[3];	/* Boot strap short or near jump */
@@ -137,6 +138,17 @@ struct fat_boot_fsinfo {
 	__le32   reserved2[4];
 };
 
+struct fat_boot_bsx {
+	__u8     drive;		    /* drive number */
+	__u8     reserved1;
+	__u8     signature;	    /* extended boot signature */
+	__u8     vol_id[4];     /* volume ID */
+	__u8     vol_label[11]; /* volume label */
+	__u8     type[8];       /* file system type */
+};
+#define FAT16_BSX_OFFSET	36 /* offset of fat_boot_bsx in FAT12 and FAT16 */
+#define FAT32_BSX_OFFSET	64 /* offset of fat_boot_bsx in FAT32 */
+
 struct msdos_dir_entry {
 	__u8	name[MSDOS_NAME];/* name and extension */
 	__u8	attr;		/* attribute bits */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 7a232a9bdd6..2957272a73a 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -43,8 +43,8 @@ extern void nand_wait_ready(struct mtd_info *mtd);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	128
-#define NAND_MAX_PAGESIZE	4096
+#define NAND_MAX_OOBSIZE	576
+#define NAND_MAX_PAGESIZE	8192
 
 /*
  * Constants for hardware specific CLE/ALE/NCE function
@@ -122,6 +122,7 @@ typedef enum {
 	NAND_ECC_HW,
 	NAND_ECC_HW_SYNDROME,
 	NAND_ECC_HW_OOB_FIRST,
+	NAND_ECC_HW_ANYKA,
 } nand_ecc_modes_t;
 
 /*
@@ -378,6 +379,8 @@ struct nand_chip {
 	int		(*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 	void		(*cmd_ctrl)(struct mtd_info *mtd, int dat,
 				    unsigned int ctrl);
+    int     (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
+                u8 *id_data);
 	int		(*dev_ready)(struct mtd_info *mtd);
 	void		(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 	int		(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
diff --git a/include/linux/mxc622x.h b/include/linux/mxc622x.h
new file mode 100755
index 00000000000..d58fbfa6196
--- /dev/null
+++ b/include/linux/mxc622x.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2010 MEMSIC, Inc.
+ *
+ * Initial Code:
+ *	Robbie Cao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+/*
+ * Definitions for mxc622x accelorometer sensor chip.
+ */
+#ifndef __MXC622X_H__
+#define __MXC622X_H__
+
+#include <linux/ioctl.h>
+#include <mach/gpio.h>
+
+#define MXC622X_I2C_NAME		"mxc622x"
+
+/*
+ * This address comes must match the part# on your target.
+ * Address to the sensor part# support as following list:
+ *   MXC6220	- 0x10
+ *   MXC6221	- 0x11
+ *   MXC6222	- 0x12
+ *   MXC6223	- 0x13
+ *   MXC6224	- 0x14
+ *   MXC6225	- 0x15
+ *   MXC6226	- 0x16
+ *   MXC6227	- 0x17
+ * Please refer to sensor datasheet for detail.
+ */
+#define MXC622X_I2C_ADDR		0x15
+
+/* MXC622X register address */
+#define MXC622X_REG_CTRL		0x04
+#define MXC622X_REG_DATA		0x00
+
+/* MXC622X control bit */
+#define MXC622X_CTRL_PWRON		0x00	/* power on */
+#define MXC622X_CTRL_PWRDN		0x80	/* power donw */
+
+/* Use 'm' as magic number */
+#define MXC622X_IOM			'm'
+
+/* IOCTLs for MXC622X device */
+#define MXC622X_IOC_PWRON		_IO (MXC622X_IOM, 0x00)
+#define MXC622X_IOC_PWRDN		_IO (MXC622X_IOM, 0x01)
+#define MXC622X_IOC_READXYZ		_IOR(MXC622X_IOM, 0x05, int[3])
+#define MXC622X_IOC_READSTATUS		_IOR(MXC622X_IOM, 0x07, int[3])
+#define MXC622X_IOC_SETDETECTION	_IOW(MXC622X_IOM, 0x08, unsigned char)
+
+struct mxc622x_platform_data {
+	void (* hw_init) (const struct gpio_info *);
+	const int irq;
+	struct gpio_info gpio;
+	int exist;
+};
+
+#endif /* __MXC622X_H__ */
+
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index b5d096d3a9b..01fa7c2428f 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -14,6 +14,7 @@
 #define __LINUX_POWER_SUPPLY_H__
 
 #include <linux/device.h>
+#include <linux/wakelock.h>
 #include <linux/workqueue.h>
 #include <linux/leds.h>
 
@@ -152,6 +153,9 @@ struct power_supply {
 	/* private */
 	struct device *dev;
 	struct work_struct changed_work;
+	spinlock_t changed_lock;
+	bool changed;
+	struct wake_lock work_wake_lock;
 
 #ifdef CONFIG_LEDS_TRIGGERS
 	struct led_trigger *charging_full_trig;
diff --git a/include/linux/sched.h b/include/linux/sched.h
index e48311e8c92..30473ee9628 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1724,6 +1724,9 @@ extern cputime_t task_utime(struct task_struct *p);
 extern cputime_t task_stime(struct task_struct *p);
 extern cputime_t task_gtime(struct task_struct *p);
 
+extern int task_free_register(struct notifier_block *n);
+extern int task_free_unregister(struct notifier_block *n);
+
 /*
  * Per process flags
  */
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index db532ce288b..9a840659d22 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -179,6 +179,13 @@
 /* BCM63xx family SoCs */
 #define PORT_BCM63XX	89
 
+/* AK88 uart */
+#define PORT_AK88	90
+
+/* AK98 uart */
+#define PORT_AK98	91
+
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
@@ -217,6 +224,7 @@ struct uart_ops {
 	void		(*pm)(struct uart_port *, unsigned int state,
 			      unsigned int oldstate);
 	int		(*set_wake)(struct uart_port *, unsigned int state);
+	void		(*wake_peer)(struct uart_port *);
 
 	/*
 	 * Return a string describing the type of the port
diff --git a/include/linux/sockios.h b/include/linux/sockios.h
index 241f179347d..f4fa1a164c7 100644
--- a/include/linux/sockios.h
+++ b/include/linux/sockios.h
@@ -65,6 +65,7 @@
 #define SIOCDIFADDR	0x8936		/* delete PA address		*/
 #define	SIOCSIFHWBROADCAST	0x8937	/* set hardware broadcast addr	*/
 #define SIOCGIFCOUNT	0x8938		/* get number of devices */
+#define SIOCKILLADDR	0x8939		/* kill sockets with this local addr */
 
 #define SIOCGIFBR	0x8940		/* Bridging support		*/
 #define SIOCSIFBR	0x8941		/* Set bridging options 	*/
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 5e781d824e6..6dd7bd3289f 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -32,7 +32,16 @@ typedef int __bitwise suspend_state_t;
 #define PM_SUSPEND_ON		((__force suspend_state_t) 0)
 #define PM_SUSPEND_STANDBY	((__force suspend_state_t) 1)
 #define PM_SUSPEND_MEM		((__force suspend_state_t) 3)
+#ifdef CONFIG_CPU_FREQ
+#define CPU_FREQ_NORMAL_100M ((__force suspend_state_t) 4)
+#define CPU_FREQ_NORMAL_200M ((__force suspend_state_t) 5)
+#define CPU_FREQ_NORMAL_400M ((__force suspend_state_t) 6)
+#define CPU_FREQ_VIDEO		((__force suspend_state_t) 7)
+#define CPU_FREQ_LOW_CLOCK	((__force suspend_state_t) 8)
+#define PM_SUSPEND_MAX		((__force suspend_state_t) 9)
+#else
 #define PM_SUSPEND_MAX		((__force suspend_state_t) 4)
+#endif
 
 /**
  * struct platform_suspend_ops - Callbacks for managing platform dependent
@@ -117,9 +126,11 @@ struct platform_suspend_ops {
 
 #ifdef CONFIG_SUSPEND
 /**
+ * cpufreq_set_ops - set platform dependent suspend operations
  * suspend_set_ops - set platform dependent suspend operations
  * @ops: The new suspend operations to set.
  */
+extern void cpufreq_set_ops(struct platform_suspend_ops *ops);
 extern void suspend_set_ops(struct platform_suspend_ops *ops);
 extern int suspend_valid_only_mem(suspend_state_t state);
 
@@ -145,6 +156,7 @@ extern int pm_suspend(suspend_state_t state);
 #else /* !CONFIG_SUSPEND */
 #define suspend_valid_only_mem	NULL
 
+static inline void cpufreq_set_ops(struct platform_suspend_ops *ops) {}
 static inline void suspend_set_ops(struct platform_suspend_ops *ops) {}
 static inline int pm_suspend(suspend_state_t state) { return -ENOSYS; }
 #endif /* !CONFIG_SUSPEND */
diff --git a/include/linux/switch.h b/include/linux/switch.h
new file mode 100644
index 00000000000..3e4c748e343
--- /dev/null
+++ b/include/linux/switch.h
@@ -0,0 +1,53 @@
+/*
+ *  Switch class driver
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#ifndef __LINUX_SWITCH_H__
+#define __LINUX_SWITCH_H__
+
+struct switch_dev {
+	const char	*name;
+	struct device	*dev;
+	int		index;
+	int		state;
+
+	ssize_t	(*print_name)(struct switch_dev *sdev, char *buf);
+	ssize_t	(*print_state)(struct switch_dev *sdev, char *buf);
+};
+
+struct gpio_switch_platform_data {
+	const char *name;
+	unsigned 	gpio;
+
+	/* if NULL, switch_dev.name will be printed */
+	const char *name_on;
+	const char *name_off;
+	/* if NULL, "0" or "1" will be printed */
+	const char *state_on;
+	const char *state_off;
+};
+
+extern int switch_dev_register(struct switch_dev *sdev);
+extern void switch_dev_unregister(struct switch_dev *sdev);
+
+static inline int switch_get_state(struct switch_dev *sdev)
+{
+	return sdev->state;
+}
+
+extern void switch_set_state(struct switch_dev *sdev, int state);
+
+#endif /* __LINUX_SWITCH_H__ */
diff --git a/include/linux/synaptics_i2c_rmi.h b/include/linux/synaptics_i2c_rmi.h
new file mode 100644
index 00000000000..5539cc52077
--- /dev/null
+++ b/include/linux/synaptics_i2c_rmi.h
@@ -0,0 +1,55 @@
+/*
+ * include/linux/synaptics_i2c_rmi.h - platform data structure for f75375s sensor
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_SYNAPTICS_I2C_RMI_H
+#define _LINUX_SYNAPTICS_I2C_RMI_H
+
+#define SYNAPTICS_I2C_RMI_NAME "synaptics-rmi-ts"
+
+enum {
+	SYNAPTICS_FLIP_X = 1UL << 0,
+	SYNAPTICS_FLIP_Y = 1UL << 1,
+	SYNAPTICS_SWAP_XY = 1UL << 2,
+	SYNAPTICS_SNAP_TO_INACTIVE_EDGE = 1UL << 3,
+};
+
+struct synaptics_i2c_rmi_platform_data {
+	uint32_t version;	/* Use this entry for panels with */
+				/* (major << 8 | minor) version or above. */
+				/* If non-zero another array entry follows */
+	int (*power)(int on);	/* Only valid in first array entry */
+	uint32_t flags;
+	unsigned long irqflags;
+	uint32_t inactive_left; /* 0x10000 = screen width */
+	uint32_t inactive_right; /* 0x10000 = screen width */
+	uint32_t inactive_top; /* 0x10000 = screen height */
+	uint32_t inactive_bottom; /* 0x10000 = screen height */
+	uint32_t snap_left_on; /* 0x10000 = screen width */
+	uint32_t snap_left_off; /* 0x10000 = screen width */
+	uint32_t snap_right_on; /* 0x10000 = screen width */
+	uint32_t snap_right_off; /* 0x10000 = screen width */
+	uint32_t snap_top_on; /* 0x10000 = screen height */
+	uint32_t snap_top_off; /* 0x10000 = screen height */
+	uint32_t snap_bottom_on; /* 0x10000 = screen height */
+	uint32_t snap_bottom_off; /* 0x10000 = screen height */
+	uint32_t fuzz_x; /* 0x10000 = screen width */
+	uint32_t fuzz_y; /* 0x10000 = screen height */
+	int fuzz_p;
+	int fuzz_w;
+	int8_t sensitivity_adjust;
+};
+
+#endif /* _LINUX_SYNAPTICS_I2C_RMI_H */
diff --git a/include/linux/uid_stat.h b/include/linux/uid_stat.h
new file mode 100644
index 00000000000..fcd3ab1f8d3
--- /dev/null
+++ b/include/linux/uid_stat.h
@@ -0,0 +1,24 @@
+/* include/linux/uid_stat.h
+ *
+ * Copyright (C) 2008-2009 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __uid_stat_h
+#define __uid_stat_h
+
+/* Contains definitions for resource tracking per uid. */
+
+extern int update_tcp_snd(uid_t uid, int size);
+extern int update_tcp_rcv(uid_t uid, int size);
+
+#endif /* _LINUX_UID_STAT_H */
diff --git a/include/linux/uio-dma.h b/include/linux/uio-dma.h
new file mode 100644
index 00000000000..5f834569f10
--- /dev/null
+++ b/include/linux/uio-dma.h
@@ -0,0 +1,86 @@
+/*
+   UIO-DMA kernel back-end 
+   Copyright (C) 2009 Qualcomm Inc. All rights reserved.
+   Written by Max Krasnyansky <maxk@qualcommm.com>
+
+   The UIO-DMA is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The UIO-DMA is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.
+*/
+
+#ifndef UIO_DMA_H
+#define UIO_DMA_H
+
+#include <linux/types.h>
+#include <linux/device.h>
+
+/* kernel interfaces */
+int uio_dma_init_module(void);
+void uio_dma_exit_module(void);
+
+int uio_dma_device_open(struct device *dev, uint32_t *devid);
+int uio_dma_device_close(uint32_t devid);
+
+/* ioctl defines */
+
+/* Caching modes */
+enum {
+	UIO_DMA_CACHE_DEFAULT = 0,
+	UIO_DMA_CACHE_DISABLE,
+	UIO_DMA_CACHE_WRITECOMBINE
+};
+
+/* DMA mapping direction */
+enum {
+	UIO_DMA_BIDIRECTIONAL = 0,
+	UIO_DMA_TODEVICE,
+	UIO_DMA_FROMDEVICE
+};
+
+#define UIO_DMA_ALLOC _IOW('U', 200, int)
+struct uio_dma_alloc_req {
+	uint64_t dma_mask;
+	uint16_t memnode;
+	uint16_t cache;
+	uint32_t flags;
+	uint32_t chunk_size;
+	uint32_t chunk_count;
+	uint64_t mmap_offset;
+};
+
+#define UIO_DMA_FREE  _IOW('U', 201, int)
+struct uio_dma_free_req {
+	uint64_t mmap_offset;
+};
+
+#define UIO_DMA_MAP   _IOW('U', 202, int)
+struct uio_dma_map_req {
+	uint64_t mmap_offset;
+	uint32_t flags;
+	uint32_t devid;
+	uint8_t  direction;
+	uint32_t chunk_count;
+	uint32_t chunk_size;
+	uint64_t dmaddr[0];
+};
+
+#define UIO_DMA_UNMAP _IOW('U', 203, int)
+struct uio_dma_unmap_req {
+	uint64_t mmap_offset;
+	uint32_t devid;
+	uint32_t flags;
+	uint8_t  direction;
+};
+
+#endif /* UIO_DMA_H */
diff --git a/include/linux/uio_driver.h b/include/linux/uio_driver.h
index 5dcc9ff72f6..2bcf6acf481 100644
--- a/include/linux/uio_driver.h
+++ b/include/linux/uio_driver.h
@@ -17,6 +17,9 @@
 #include <linux/module.h>
 #include <linux/fs.h>
 #include <linux/interrupt.h>
+#ifdef CONFIG_UIODMA
+#include <linux/uio-dma.h>
+#endif
 
 struct uio_map;
 
@@ -38,7 +41,7 @@ struct uio_mem {
 	struct uio_map		*map;
 };
 
-#define MAX_UIO_MAPS	5
+#define MAX_UIO_MAPS	16
 
 struct uio_portio;
 
@@ -86,12 +89,17 @@ struct uio_info {
 	struct uio_port		port[MAX_UIO_PORT_REGIONS];
 	long			irq;
 	unsigned long		irq_flags;
+#ifdef CONFIG_UIODMA
+	bool			use_dma;
+	uint32_t		dma_dev_id;
+#endif
 	void			*priv;
 	irqreturn_t (*handler)(int irq, struct uio_info *dev_info);
 	int (*mmap)(struct uio_info *info, struct vm_area_struct *vma);
 	int (*open)(struct uio_info *info, struct inode *inode);
 	int (*release)(struct uio_info *info, struct inode *inode);
 	int (*irqcontrol)(struct uio_info *info, s32 irq_on);
+	int (*ioctl)(struct uio_info *info, unsigned int cmd, unsigned long arg);
 };
 
 extern int __must_check
diff --git a/include/linux/usb/ak98fsh.h b/include/linux/usb/ak98fsh.h
new file mode 100644
index 00000000000..f440d408e98
--- /dev/null
+++ b/include/linux/usb/ak98fsh.h
@@ -0,0 +1,29 @@
+/*
+ * board initialization should put one of these into dev->platform_data
+ * and place the ak98hs onto platform_bus named "ak98-hcd".
+ */
+
+#ifndef __LINUX_USB_AK98_H
+#define __LINUX_USB_AK98_H
+
+struct ak98_platform_data {
+	unsigned	can_wakeup:1;
+
+	/* given port_power, msec/2 after power on till power good */
+	u8		potpg;
+
+	/* mA/2 power supplied on this port (max = default = 250) */
+	u8		power;
+
+	/* ak98 relies on an external source of VBUS current */
+	void		(*port_power)(struct device *dev, int is_on);
+
+	/* pulse ak98 nRST (probably with a GPIO) */
+	void		(*reset)(struct device *dev);
+
+	/* some boards need something like these: */
+	/* int		(*check_overcurrent)(struct device *dev); */
+	/* void		(*clock_enable)(struct device *dev, int is_on); */
+};
+
+#endif /* __LINUX_USB_AK98_H */
diff --git a/include/linux/usb/android_composite.h b/include/linux/usb/android_composite.h
new file mode 100644
index 00000000000..50889ba138b
--- /dev/null
+++ b/include/linux/usb/android_composite.h
@@ -0,0 +1,98 @@
+/*
+ * Platform data for Android USB
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef	__LINUX_USB_ANDROID_H
+#define	__LINUX_USB_ANDROID_H
+
+#include <linux/usb/composite.h>
+#include <linux/if_ether.h>
+
+struct android_usb_function {
+	struct list_head	list;
+	char			*name;
+	int 			(*bind_config)(struct usb_configuration *c);
+};
+
+struct android_usb_product {
+	/* Default product ID. */
+	__u16 product_id;
+
+	/* List of function names associated with this product.
+	 * This is used to compute the USB product ID dynamically
+	 * based on which functions are enabled.
+	 */
+	int num_functions;
+	char **functions;
+};
+
+struct android_usb_platform_data {
+	/* USB device descriptor fields */
+	__u16 vendor_id;
+
+	/* Default product ID. */
+	__u16 product_id;
+
+	__u16 version;
+
+	char *product_name;
+	char *manufacturer_name;
+	char *serial_number;
+
+	/* List of available USB products.
+	 * This is used to compute the USB product ID dynamically
+	 * based on which functions are enabled.
+	 * if num_products is zero or no match can be found,
+	 * we use the default product ID
+	 */
+	int num_products;
+	struct android_usb_product *products;
+
+	/* List of all supported USB functions.
+	 * This list is used to define the order in which
+	 * the functions appear in the configuration's list of USB interfaces.
+	 * This is necessary to avoid depending upon the order in which
+	 * the individual function drivers are initialized.
+	 */
+	int num_functions;
+	char **functions;
+};
+
+/* Platform data for "usb_mass_storage" driver. */
+struct usb_mass_storage_platform_data {
+	/* Contains values for the SC_INQUIRY SCSI command. */
+	char *vendor;
+	char *product;
+	int release;
+
+	/* number of LUNS */
+	int nluns;
+};
+
+/* Platform data for USB ethernet driver. */
+struct usb_ether_platform_data {
+	u8	ethaddr[ETH_ALEN];
+	u32	vendorID;
+	const char *vendorDescr;
+};
+
+extern void android_usb_set_connected(int on);
+
+extern void android_register_function(struct android_usb_function *f);
+
+extern void android_enable_function(struct usb_function *f, int enable);
+
+
+#endif	/* __LINUX_USB_ANDROID_H */
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
index 4f6bb3d2160..080365ba3b2 100644
--- a/include/linux/usb/composite.h
+++ b/include/linux/usb/composite.h
@@ -36,8 +36,10 @@
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/switch.h>
 
 
+struct usb_composite_dev;
 struct usb_configuration;
 
 /**
@@ -101,6 +103,9 @@ struct usb_function {
 
 	struct usb_configuration	*config;
 
+	/* disabled is zero if the function is enabled */
+	int				disabled;
+
 	/* REVISIT:  bind() functions can be marked __init, which
 	 * makes trouble for section mismatch analysis.  See if
 	 * we can't restructure things to avoid mismatching.
@@ -127,6 +132,7 @@ struct usb_function {
 	/* private: */
 	/* internals */
 	struct list_head		list;
+	struct device			*dev;
 };
 
 int usb_add_function(struct usb_configuration *, struct usb_function *);
@@ -136,6 +142,9 @@ int usb_function_activate(struct usb_function *);
 
 int usb_interface_id(struct usb_configuration *, struct usb_function *);
 
+void usb_function_set_enabled(struct usb_function *, int);
+void usb_composite_force_reset(struct usb_composite_dev *);
+
 /**
  * ep_choose - select descriptor endpoint at current device speed
  * @g: gadget, connected and running at some speed
@@ -267,6 +276,9 @@ struct usb_composite_driver {
 	const struct usb_device_descriptor	*dev;
 	struct usb_gadget_strings		**strings;
 
+	struct class		*class;
+	atomic_t		function_count;
+
 	/* REVISIT:  bind() functions can be marked __init, which
 	 * makes trouble for section mismatch analysis.  See if
 	 * we can't restructure things to avoid mismatching...
@@ -278,6 +290,8 @@ struct usb_composite_driver {
 	/* global suspend hooks */
 	void			(*suspend)(struct usb_composite_dev *);
 	void			(*resume)(struct usb_composite_dev *);
+
+	void			(*enable_function)(struct usb_function *f, int enable);
 };
 
 extern int usb_composite_register(struct usb_composite_driver *);
@@ -337,6 +351,11 @@ struct usb_composite_dev {
 
 	/* protects at least deactivation count */
 	spinlock_t			lock;
+
+	struct switch_dev sdev;
+	/* used by usb_composite_force_reset to avoid signalling switch changes */
+	bool				mute_switch;
+	struct work_struct switch_work;
 };
 
 extern int usb_string_id(struct usb_composite_dev *c);
diff --git a/include/linux/wakelock.h b/include/linux/wakelock.h
new file mode 100755
index 00000000000..a096d24ada1
--- /dev/null
+++ b/include/linux/wakelock.h
@@ -0,0 +1,91 @@
+/* include/linux/wakelock.h
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_WAKELOCK_H
+#define _LINUX_WAKELOCK_H
+
+#include <linux/list.h>
+#include <linux/ktime.h>
+
+/* A wake_lock prevents the system from entering suspend or other low power
+ * states when active. If the type is set to WAKE_LOCK_SUSPEND, the wake_lock
+ * prevents a full system suspend. If the type is WAKE_LOCK_IDLE, low power
+ * states that cause large interrupt latencies or that disable a set of
+ * interrupts will not entered from idle until the wake_locks are released.
+ */
+
+enum {
+	WAKE_LOCK_SUSPEND, /* Prevent suspend */
+	WAKE_LOCK_IDLE,    /* Prevent low power idle */
+	WAKE_LOCK_TYPE_COUNT
+};
+
+struct wake_lock {
+#ifdef CONFIG_HAS_WAKELOCK
+	struct list_head    link;
+	int                 flags;
+	const char         *name;
+	unsigned long       expires;
+#ifdef CONFIG_WAKELOCK_STAT
+	struct {
+		int             count;
+		int             expire_count;
+		int             wakeup_count;
+		ktime_t         total_time;
+		ktime_t         prevent_suspend_time;
+		ktime_t         max_time;
+		ktime_t         last_time;
+	} stat;
+#endif
+#endif
+};
+
+#ifdef CONFIG_HAS_WAKELOCK
+
+void wake_lock_init(struct wake_lock *lock, int type, const char *name);
+void wake_lock_destroy(struct wake_lock *lock);
+void wake_lock(struct wake_lock *lock);
+void wake_lock_timeout(struct wake_lock *lock, long timeout);
+void wake_unlock(struct wake_lock *lock);
+
+/* wake_lock_active returns a non-zero value if the wake_lock is currently
+ * locked. If the wake_lock has a timeout, it does not check the timeout
+ * but if the timeout had aready been checked it will return 0.
+ */
+int wake_lock_active(struct wake_lock *lock);
+
+/* has_wake_lock returns 0 if no wake locks of the specified type are active,
+ * and non-zero if one or more wake locks are held. Specifically it returns
+ * -1 if one or more wake locks with no timeout are active or the
+ * number of jiffies until all active wake locks time out.
+ */
+long has_wake_lock(int type);
+
+#else
+
+static inline void wake_lock_init(struct wake_lock *lock, int type,
+					const char *name) {}
+static inline void wake_lock_destroy(struct wake_lock *lock) {}
+static inline void wake_lock(struct wake_lock *lock) {}
+static inline void wake_lock_timeout(struct wake_lock *lock, long timeout) {}
+static inline void wake_unlock(struct wake_lock *lock) {}
+
+static inline int wake_lock_active(struct wake_lock *lock) { return 0; }
+static inline long has_wake_lock(int type) { return 0; }
+
+#endif
+
+#endif
+
diff --git a/include/linux/wifi_tiwlan.h b/include/linux/wifi_tiwlan.h
new file mode 100644
index 00000000000..f07e0679fb8
--- /dev/null
+++ b/include/linux/wifi_tiwlan.h
@@ -0,0 +1,27 @@
+/* include/linux/wifi_tiwlan.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _LINUX_WIFI_TIWLAN_H_
+#define _LINUX_WIFI_TIWLAN_H_
+
+#include <linux/wlan_plat.h>
+
+#define WMPA_NUMBER_OF_SECTIONS	3
+#define WMPA_NUMBER_OF_BUFFERS	160
+#define WMPA_SECTION_HEADER	24
+#define WMPA_SECTION_SIZE_0	(WMPA_NUMBER_OF_BUFFERS * 64)
+#define WMPA_SECTION_SIZE_1	(WMPA_NUMBER_OF_BUFFERS * 256)
+#define WMPA_SECTION_SIZE_2	(WMPA_NUMBER_OF_BUFFERS * 2048)
+
+#endif
diff --git a/include/linux/wl127x-rfkill.h b/include/linux/wl127x-rfkill.h
new file mode 100644
index 00000000000..9057ec63d5d
--- /dev/null
+++ b/include/linux/wl127x-rfkill.h
@@ -0,0 +1,35 @@
+/*
+ * Bluetooth TI wl127x rfkill power control via GPIO
+ *
+ * Copyright (C) 2009 Motorola, Inc.
+ * Copyright (C) 2008 Texas Instruments
+ * Initial code: Pavan Savoy <pavan.savoy@gmail.com> (wl127x_power.c)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _LINUX_WL127X_RFKILL_H
+#define _LINUX_WL127X_RFKILL_H
+
+#include <linux/rfkill.h>
+
+struct wl127x_rfkill_platform_data {
+	int nshutdown_gpio;
+
+	struct rfkill *rfkill;  /* for driver only */
+};
+
+#endif
diff --git a/include/linux/wlan_plat.h b/include/linux/wlan_plat.h
new file mode 100644
index 00000000000..70ee63b44ad
--- /dev/null
+++ b/include/linux/wlan_plat.h
@@ -0,0 +1,25 @@
+/* include/linux/wlan_plat.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _LINUX_WLAN_PLAT_H_
+#define _LINUX_WLAN_PLAT_H_
+
+struct wifi_platform_data {
+	int (*set_power)(int val);
+	int (*set_reset)(int val);
+	int (*set_carddetect)(int val);
+	void *(*mem_prealloc)(int section, unsigned long size);
+};
+
+#endif
diff --git a/include/mach-anyka/Kbuild b/include/mach-anyka/Kbuild
new file mode 100644
index 00000000000..486cf616b00
--- /dev/null
+++ b/include/mach-anyka/Kbuild
@@ -0,0 +1,4 @@
+header-y += fha.h
+header-y += anyka_types.h
+header-y += nand_list.h
+
diff --git a/include/mach-anyka/anyka_types.h b/include/mach-anyka/anyka_types.h
new file mode 100644
index 00000000000..fdeda90a6d0
--- /dev/null
+++ b/include/mach-anyka/anyka_types.h
@@ -0,0 +1,69 @@
+/** @file

+ * @brief Define the register operator for system

+ *

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author 

+ * @date 2006-01-16

+ * @version 1.0

+ */

+

+#ifndef _ANYKA_TYPES_H_

+#define _ANYKA_TYPES_H_

+

+/** @defgroup ANYKA_CPU  

+ *    @ingroup M3PLATFORM

+ */

+/*@{*/

+

+/* preliminary type definition for global area */

+typedef    unsigned char          T_U8;       /* unsigned 8 bit integer */

+typedef    unsigned short         T_U16;      /* unsigned 16 bit integer */

+typedef    unsigned long          T_U32;      /* unsigned 32 bit integer */

+typedef    signed char            T_S8;       /* signed 8 bit integer */

+typedef    signed short           T_S16;      /* signed 16 bit integer */

+typedef    signed long            T_S32;      /* signed 32 bit integer */

+typedef    void                   T_VOID;     /* void */

+

+#define    T_U8_MAX             ((T_U8)0xff)                 // maximum T_U8 value

+#define    T_U16_MAX            ((T_U16)0xffff)              // maximum T_U16 value

+#define    T_U32_MAX            ((T_U32)0xffffffff)          // maximum T_U32 value

+#define    T_S8_MIN             ((T_S8)(-127-1))             // minimum T_S8 value

+#define    T_S8_MAX             ((T_S8)127)                  // maximum T_S8 value

+#define    T_S16_MIN            ((T_S16)(-32767L-1L))        // minimum T_S16 value

+#define    T_S16_MAX            ((T_S16)(32767L))            // maximum T_S16 value

+#define    T_S32_MIN            ((T_S32)(-2147483647L-1L))   // minimum T_S32 value

+#define    T_S32_MAX            ((T_S32)(2147483647L))       // maximum T_S32 value

+

+/* basal type definition for global area */

+typedef T_S8                    T_CHR;      /* char */

+typedef T_U8                    T_BOOL;     /* BOOL type */

+

+typedef T_VOID *                T_pVOID;    /* pointer of void data */

+typedef const T_VOID *          T_pCVOID;   /* const pointer of void data */

+

+typedef T_S8 *                  T_pSTR;     /* pointer of string */

+typedef const T_S8 *            T_pCSTR;    /* const pointer of string */

+

+

+typedef T_U16                   T_WCHR;     /**< unicode char */

+typedef T_U16 *                 T_pWSTR;    /* pointer of unicode string */

+typedef const T_U16 *           T_pCWSTR;   /* const pointer of unicode string */

+

+

+typedef T_U8 *                  T_pDATA;    /* pointer of data */

+typedef const T_U8 *            T_pCDATA;   /* const pointer of data */

+

+typedef T_U32                   T_COLOR;    /* color value */

+

+typedef T_U32                   T_HANDLE;   /* a handle */

+

+#define        AK_FALSE            0

+#define        AK_TRUE             1

+#define        AK_NULL             ((T_pVOID)(0))

+

+#define        AK_EMPTY

+/*@}*/

+

+

+#endif    //  _ANYKA_TYPES_H_

+

diff --git a/include/mach-anyka/fha.h b/include/mach-anyka/fha.h
new file mode 100644
index 00000000000..09fa8f0a81b
--- /dev/null
+++ b/include/mach-anyka/fha.h
@@ -0,0 +1,369 @@
+#ifndef        _FHA_H_

+#define        _FHA_H_

+

+#include "anyka_types.h"

+#include "nand_list.h"

+

+#define FHA_SUCCESS 1

+#define FHA_FAIL    0

+

+#define VER_NAME_FHA        "FHA"

+#define VER_NAME_FS         "FS"

+#define VER_NAME_MTD        "MTD"

+#define VER_NAME_DRV        "DRV"

+#define VER_NAME_MOUNT      "MOUNT"

+#define VER_NAME_FSA        "FSA"

+

+typedef enum

+{

+    FHA_CHIP_880X,      //aspen3

+    FHA_CHIP_10XX,      //snowbirds

+    FHA_CHIP_980X,      //aspen3s

+    FHA_CHIP_37XX,      //Sundance3

+    FHA_CHIP_11XX,      //snowbird2

+}E_FHA_CHIP_TYPE;

+

+typedef enum

+{

+    PLAT_SPOT,          //spot system

+    PLAT_SPR,           //spring system    

+    PLAT_SWORD,         //sword system

+    PLAT_LINUX          //linux system

+}E_FHA_PLATFORM_TYPE;

+

+typedef enum

+{

+    MEDIUM_NAND,                //nand

+    MEDIUM_SPIFLASH,            //spiflash

+    MEDIUM_EMMC,                //sd, emmc, inand

+    MEDIUM_SPI_EMMC,            //data is stored in spiflash and sd

+    MEDIUM_EMMC_SPIBOOT,        //data is stored in sd and boot from spiflash

+}E_FHA_MEDIUM_TYPE;

+

+typedef enum

+{

+    MODE_NEWBURN = 1,           //new burn

+    MODE_UPDATE,                //update mode

+}E_BURN_MODE;

+

+typedef enum

+{

+    FHA_DATA_BOOT,

+    FHA_DATA_ASA,

+    FHA_DATA_BIN,

+    FHA_DATA_FS,

+    FHA_GET_NAND_PARAM

+}E_FHA_DATA_TYPE;

+

+typedef struct

+{

+    T_U8 lib_name[10];

+    T_U8 lib_version[40];

+}T_LIB_VER_INFO;

+

+

+/************************************************************************

+ * NAME:     FHA_Erase

+ * FUNCTION  callback function, medium erase

+ * PARAM:    [in] nChip--meidum chip

+ *           [in] nPage--medium page

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+typedef  T_U32 (*FHA_Erase)(T_U32 nChip,  T_U32 nPage); 

+

+/************************************************************************

+ * NAME:     FHA_Write

+ * FUNCTION  callback function, medium write

+ * PARAM:    [in] nChip-----meidum chip

+ *           [in] nPage-----medium page

+ *           [in] pData-----need to write data pointer addr

+ *           [in] nDataLen--need to write data length

+ *                          nand(unit byte)

+ *                          SD(unit sector count(1sec = 512byte))

+ *                          SPI(unit 1 page, page size in platform define)

+ *           [in] pOob------Spare area£ºOut Of Band, only nand use

+ *           [in] nOobLen---Spare area length

+ *           [in] eDataType-burn medium data type

+ *                          nand -- E_FHA_DATA_TYPE

+ *                          SD----- MEDIUM_EMMC

+ *                          SPI---- MEDIUM_SPIFLASH

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+typedef T_U32 (*FHA_Write)(T_U32 nChip, T_U32 nPage, const T_U8 *pData, T_U32 nDataLen,  T_U8 *pOob, T_U32 nOobLen, T_U32 eDataType);

+

+/************************************************************************

+ * NAME:     FHA_Read

+ * FUNCTION  callback function, medium read

+ * PARAM:    [in] nChip-----meidum chip

+ *           [in] nPage-----medium page

+ *           [out]pData-----need to read data pointer addr

+ *           [in] nDataLen--need to ren data length

+ *                          nand(unit byte)

+ *                          SD(unit sector count(1sec = 512byte))

+ *                          SPI(unit 1 page, page size in platform define)

+ *           [out]pOob------Spare area£ºOut Of Band, only nand use

+ *           [in] nOobLen---Spare area length

+ *           [in] eDataType-burn medium data type

+ *                          nand -- E_FHA_DATA_TYPE

+ *                          SD----- MEDIUM_EMMC

+ *                          SPI---- MEDIUM_SPIFLASH

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+typedef T_U32 (*FHA_Read)(T_U32 nChip,  T_U32 nPage, T_U8 *pData, T_U32 nDataLen,  T_U8 *pOob, T_U32 nOobLen , T_U32 eDataType);

+

+/************************************************************************

+ * NAME:     FHA_ReadNandBytes

+ * FUNCTION  callback function, nand read no ECC

+ * PARAM:    [in] nChip-------meidum chip

+ *           [in] rowAddr-----nand physical row addr

+ *           [in] columnAddr--nand physical cloumn addr

+ *           [out] pData------need to read data pointer addr

+ *           [in] nDataLen----need to ren data length

+ *                            nand(unit byte)

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+typedef T_U32 (*FHA_ReadNandBytes)(T_U32 nChip, T_U32 rowAddr, T_U32 columnAddr, T_U8 *pData, T_U32 nDataLen);

+

+typedef T_pVOID (*FHA_RamAlloc)(T_U32 size);

+typedef T_pVOID (*FHA_RamFree)(T_pVOID var);

+typedef T_pVOID (*FHA_MemSet)(T_pVOID pBuf, T_S32 value, T_U32 count);

+typedef T_pVOID (*FHA_MemCpy)(T_pVOID dst, T_pCVOID src, T_U32 count);

+typedef T_S32   (*FHA_MemCmp)(T_pCVOID pbuf1, T_pCVOID pbuf2, T_U32 count);

+typedef T_pVOID (*FHA_MemMov)(T_pVOID dst, const T_pCVOID src, T_U32 count);

+typedef T_S32   (*FHA_Printf)(T_pCSTR s, ...);

+

+typedef struct tag_FHA_LibCallback

+{

+    FHA_Erase Erase;

+    FHA_Write Write;

+    FHA_Read  Read;

+    FHA_ReadNandBytes ReadNandBytes;

+    FHA_RamAlloc RamAlloc;

+    FHA_RamFree  RamFree;

+    FHA_MemSet   MemSet;

+    FHA_MemCpy   MemCpy;

+    FHA_MemCmp   MemCmp;

+    FHA_MemMov   MemMov;

+    FHA_Printf   Printf;

+}T_FHA_LIB_CALLBACK, *T_PFHA_LIB_CALLBACK;

+

+typedef struct tag_FHA_Init_Info

+{

+    T_U32 nChipCnt;                //ƬѡÊý

+    T_U32 nBlockStep;            //nand block stepÖµ

+    E_FHA_CHIP_TYPE     eAKChip;    //AKоƬÀàÐÍ

+    E_FHA_PLATFORM_TYPE ePlatform;  //ϵͳÀàÐÍ

+    E_FHA_MEDIUM_TYPE   eMedium;    //´æ´¢½éÖÊÀàÐÍ

+    E_BURN_MODE     eMode;        //ÉÕ¼ģʽ

+}T_FHA_INIT_INFO, *T_PFHA_INIT_INFO;

+

+typedef struct tag_FHABinParam

+{

+    T_U32   data_length;    //Êý¾Ý³¤¶È

+    T_U32   ld_addr;        //ÔËÐеØÖ·

+    T_U8    file_name[16];  //ÎļþÃû³Æ

+    T_BOOL  bBackup;        //ÊÇ·ñ±¸·Ý

+    T_BOOL  bCheck;         //ÊÇ·ñУÑé

+    T_BOOL  bUpdateSelf;    //spotlight×ÔÉý¼¶Ó㬻á¸øÿ¸öBINÔ¤ÁôͬÑù¶àµÄ¿Õ¼ä    

+}T_FHA_BIN_PARAM, *T_PFHA_BIN_PARAM;

+

+typedef struct

+{

+    T_U32 BinPageStart; /*bin data start addr*/

+    T_U32 PageSize; /*spi page size*/

+    T_U32 PagesPerBlock;/*page per block*/

+}T_SPI_INIT_INFO, *T_PSPI_INIT_INFO;

+

+/************************************************************************

+ * NAME:     FHA_burn_init

+ * FUNCTION  Initial FHA callback function, init fha init info para

+ * PARAM:    [in] pInit----burn platform init struct pointer

+ *           [in] pCB------callback function struct pointer

+ *           [in] pPhyInfo-input medium struct pointer

+ *                         NAND-------T_NAND_PHY_INFO*

+ *                         SPIFLASH---T_PSPI_INIT_INFO

+ *                         EMMC-------AK_NULL

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_burn_init(T_PFHA_INIT_INFO pInit, T_PFHA_LIB_CALLBACK pCB, T_pVOID pPhyInfo);

+

+/************************************************************************

+ * NAME:     FHA_set_resv_zone_info

+ * FUNCTION  set reserve area

+ * PARAM:    [in] nSize--set reserve area size(unit Mbyte)

+ *           [in] bErase-if == 1 ,erase reserve area, or else not erase 

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32 FHA_set_resv_zone_info(T_U32  nSize, T_BOOL bErase);

+

+/************************************************************************

+ * NAME:     FHA_write_bin_begin

+ * FUNCTION  set write bin start init para

+ * PARAM:    [in] bin_param--Bin file info struct

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_write_bin_begin(T_PFHA_BIN_PARAM bin_param);

+

+/************************************************************************

+ * NAME:     FHA_write_bin

+ * FUNCTION  write bin to medium

+ * PARAM:    [in] pData-----need to write bin data pointer addr

+ *           [in] data_len--need to write bin data length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_write_bin(const T_U8 * pData,  T_U32 data_len);

+

+/************************************************************************

+ * NAME:     FHA_write_boot_begin

+ * FUNCTION  set write boot start init para

+ * PARAM:    [in] bin_len--boot length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_write_boot_begin(T_U32 bin_len);

+

+/************************************************************************

+ * NAME:     FHA_write_boot

+ * FUNCTION  write boot to medium

+ * PARAM:    [in] pData-----need to write boot data pointer addr

+ *           [in] data_len--need to write boot data length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_write_boot(const T_U8 *pData,  T_U32 data_len);

+

+/************************************************************************

+ * NAME:     FHA_get_last_pos

+ * FUNCTION  get fs start position

+ * PARAM:    NULL

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_last_pos();

+

+/************************************************************************

+ * NAME:     FHA_set_fs_part

+ * FUNCTION  set fs partition info to medium 

+ * PARAM:    [in] pInfoBuf-----need to write fs info data pointer addr

+ *           [in] data_len--need to write fs info data length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_set_fs_part(const T_U8 *pInfoBuf, T_U32 buf_len);

+

+/************************************************************************

+ * NAME:     FHA_close

+ * FUNCTION  flush all need to save data to medium, and free all fha malloc ram

+ * PARAM:    NULL

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_close(T_VOID);

+

+/************************************************************************

+ * NAME:     FHA_mount

+ * FUNCTION  Initial FHA mount callback function, init fha mount init info para

+ * PARAM:    [in] pInit----burn platform init struct pointer

+ *           [in] pCB------callback function struct pointer

+ *           [in] pPhyInfo-input medium struct pointer

+ *                         NAND-------T_NAND_PHY_INFO*, linux platform == AK_NULL

+ *                         SPIFLASH---T_PSPI_INIT_INFO

+ *                         EMMC-------AK_NULL

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_mount(T_PFHA_INIT_INFO pInit, T_PFHA_LIB_CALLBACK pCB, T_pVOID pPhyInfo);

+

+/************************************************************************

+ * NAME:     FHA_read_bin_begin

+ * FUNCTION  set read bin start init para

+ * PARAM:    [in] bin_param--Bin file info struct

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_read_bin_begin(T_PFHA_BIN_PARAM bin_param);

+

+/************************************************************************

+ * NAME:     FHA_read_bin

+ * FUNCTION  read bin to buf from medium

+ * PARAM:    [out]pData-----need to read bin data buf pointer addr

+ *           [in] data_len--need to read bin data length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_read_bin(T_U8 *pData,  T_U32 data_len);

+

+/************************************************************************

+ * NAME:     FHA_get_maplist

+ * FUNCTION  get block address map of bin. (only nand)

+ * PARAM:    [in] file_name---need to get bin's file name

+ *           [out]map_data----need to get bin's block map buf pointer addr

+ *           [out]file_len----need to get bin's file length 

+ *           [in] bBackup-----if AK_TRUE == bBackup, get backup block map, or else get origin block map

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_maplist(T_U8 file_name[], T_U16 *map_data, T_U32 *file_len, T_BOOL bBackup);

+

+/************************************************************************

+ * NAME:     FHA_get_nand_para

+ * FUNCTION  get nand para

+ * PARAM:    [out] pNandPhyInfo--nand info struct pointer

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_nand_para(T_NAND_PHY_INFO *pNandPhyInfo);

+

+/************************************************************************

+ * NAME:     FHA_get_fs_part

+ * FUNCTION  get fs partition info

+ * PARAM:    [out]pInfoBuf---need to get fs info data pointer addr

+ *           [in] data_len---need to get fs info data length

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_fs_part(T_U8 *pInfoBuf , T_U32 buf_len);

+

+/************************************************************************

+ * NAME:     FHA_get_resv_zone_info

+ * FUNCTION  get reserve area

+ * PARAM:    [out] start_block--get reserve area start block

+ *           [out] block_cnt----get reserve area block count

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32 FHA_get_resv_zone_info(T_U16 *start_block, T_U16 *block_cnt);

+

+/************************************************************************

+ * NAME:     FHA_get_bin_num

+ * FUNCTION  get bin file number

+ *           [out] cnt----bin file count in medium

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_bin_num(T_U32 *cnt);

+

+/************************************************************************

+ * NAME:     FHA_set_lib_version

+ * FUNCTION  set burn all lib version

+ * PARAM:    [in] lib_info--all lib version struct pointer addr

+ *           [in] lib_cnt---lib count

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_set_lib_version(T_LIB_VER_INFO *lib_info,  T_U32 lib_cnt);

+

+/************************************************************************

+ * NAME:     FHA_get_lib_verison

+ * FUNCTION  get burn lib version by input lib_info->lib_name

+ * PARAM:    [in-out] lib_info--input lib_info->lib_name, output lib_info->lib_version

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32  FHA_get_lib_verison(T_LIB_VER_INFO *lib_info);

+

+/************************************************************************

+ * NAME:     FHA_get_version

+ * FUNCTION  get fha version

+ * PARAM:    NULL

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U8 *FHA_get_version();

+

+/************************************************************************

+ * NAME:     FHA_check_lib_version

+ * FUNCTION  check burn lib version

+ * PARAM:    [in] lib_info lib name and verison

+ * RETURN:   success return FHA_SUCCESS, fail retuen FHA_ FAIL

+**************************************************************************/

+T_U32 FHA_check_lib_version(T_LIB_VER_INFO *lib_info);

+

+

+#endif      //_FHA_BINBURN_H_

+

+

diff --git a/include/mach-anyka/fha_asa.h b/include/mach-anyka/fha_asa.h
new file mode 100644
index 00000000000..c1d09d4a7ae
--- /dev/null
+++ b/include/mach-anyka/fha_asa.h
@@ -0,0 +1,34 @@
+#ifndef		_FHA_ASA_H_

+#define		_FHA_ASA_H_

+

+#define ASA_FILE_FAIL   	0

+#define ASA_FILE_SUCCESS    1

+#define ASA_FILE_EXIST   	2

+#define ASA_MODE_OPEN		0

+#define ASA_MODE_CREATE		1

+

+ 

+#define ASA_FORMAT_NORMAL   0

+#define ASA_FORMAT_EWR      1

+#define ASA_FORMAT_RESTORE  2

+

+

+#define ASA_MAIN_VER  1

+#define ASA_SUB_VER   5

+

+T_U32  FHA_asa_scan(T_BOOL  bMount);

+

+T_U32  FHA_asa_format(T_U32 type);

+

+T_U32  FHA_set_bad_block(T_U32 block);

+

+T_BOOL  FHA_check_bad_block(T_U32 block);

+

+T_U32  FHA_get_bad_block(T_U32 start_block, T_U8 *pData, T_U32 blk_cnt);

+

+T_U32  FHA_asa_write_file(T_U8 file_name[], const T_U8 *pData, T_U32 data_len, T_U8 mode);

+

+T_U32  FHA_asa_read_file(T_U8 file_name[], T_U8 *pData, T_U32 data_len);

+

+#endif    //

+

diff --git a/include/mach-anyka/nand_list.h b/include/mach-anyka/nand_list.h
new file mode 100644
index 00000000000..6f2f609d7b0
--- /dev/null
+++ b/include/mach-anyka/nand_list.h
@@ -0,0 +1,85 @@
+/**

+ * @filename nand_list.h

+ * @brief: AK3223M interrupt

+ *

+ * This file describe what is in the table of nand list

+ * Copyright (C) 2006 Anyka (GuangZhou) Software Technology Co., Ltd.

+ * @author  zhaojiahuan

+ * @modify chenyanyan

+ * @date    2007-1-10

+ * @version 1.0

+ * @ref

+ */

+

+#ifndef __CHIP_NFC_3224__

+#define __CHIP_NFC_3224__

+

+#include	"anyka_types.h"

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @defgroup NandFlash Architecture NandFlash Interface

+ *  @ingroup Architecture

+ */

+/*@{*/

+

+/**

+* @BRIEF    Nandflash info define

+* @AUTHOR   zhaojiahuan

+* @DATE     2006-7-17

+*/

+

+typedef struct

+Nand_phy_info{

+    T_U32  chip_id;//chip id

+    T_U16  page_size; //page size

+    T_U16  page_per_blk; //page of one blok

+    T_U16  blk_num;//total block number

+    T_U16  group_blk_num;//the same concept as die, according to nand's struture

+    T_U16  plane_blk_num;   

+    T_U8   spare_size;//spareÇøÓò´óСµÄµÍ룬²»³¬¹ý255 Byte

+    T_U8   col_cycle;//column address cycle

+    T_U8   lst_col_mask;//last column  addrress cycle mask bit

+    T_U8   row_cycle;//row address cycle

+    T_U8   delay_cnt;//Rb delay, unit is 1024 asic clock, default value corresponds to 84MHz

+    T_U8   custom_nd;//nand type flag, used to detect the original invilid block

+        //currently there are 7 types, more types might be added when new nand come out

+        //˵Ã÷£ºÀ¨ºÅÀïÇ°Ò»¸öÊÇpageºÅ,ºóÒ»¸öÊÇpageÖеÄλÖÃ, Èç¹ûÕâЩλÖò»Îª0xFFÔò¸ÃblockÊdzö³§»µ¿ì

+        //NAND_TYPE_SAMSUNG:        0x1 СҳSLC([0,1],[517]),   ´óÒ³SLC([0,1],[2048]),          MLC([127], [2048/4096])

+        //NAND_TYPE_HYNIX:          0x2 СҳSLC([0,1],[517]),   ´óÒ³SLC([0,1],[2048]),          MLC([125,127], [2048/4096])

+        //NAND_TYPE_TOSHIBA:        0x3 СҳSLC([0,1],[0,512]), ´óÒ³SLC([0,1],[0,2048]),        MLC([127], [0,2048/4096])

+        //NAND_TYPE_TOSHIBA_EXT:    0x4 СҳSLC(),              ´óÒ³SLC(),                      MLC([0,127/255], [0,2048/4096/8192])

+        //NAND_TYPE_MICRON:         0x5 СҳSLC([0,1],[512]),   ´óÒ³SLC([0,1],[2048]),          MLC([0,1], [2048/4096])

+        //NAND_TYPE_ST:             0x6 СҳSLC([0,1],[517]),   ´óÒ³SLC([0],[2048,2053]),       MLC([127], [0])

+        //NAND_TYPE_MICRON_4K       0x7 СҳSLC(),              ´óÒ³SLC(),                      MLC([0], [4096 ~ 4096+218])

+    T_U32  flag;//character bits, ×î¸ß4λ±íʾplaneÊôÐÔ£¬×îµÍλ±íʾÊÇ·ñÐèÒªblockÄÚ˳Ðòдpage

+    //bit31±íʾÊÇ·ñÓÐcopyback£¬1±íʾÓÐcopyback

+    //bit30±íʾÊÇ·ñÖ»ÓÐÒ»¸öplane£¬1±íʾֻÓÐÒ»¸öplane

+    //bit29±íʾÊÇ·ñÇ°ºóplane£¬1±íʾÓÐÇ°ºóplane

+    //bit28±íʾÊÇ·ñÆæżplane£¬1±íʾÓÐÆæżplane

+

+    //ÒÔÏÂbitÊÇΪÁ˽â¾öpageºÍblockµØÖ·²»Á¬Ðø¶øÔö¼ÓµÄ¿ØÖÆbit:

+    //bit11±íʾblock number per dieÊÇ·ñÐèÒªÏòÉϹæÕû£¬ÈçToshiba TH58NVG6D2ETA20ÊÇ2048 block/die(ʵ¼ÊÓÐ2084 block/die)

+         //ΪÁ˶ÔÆëÏÂÒ»¸ödieµÄblockÔòÐèÒª¹æÕûΪ4096 block/die¸øµ×²ãÇý¶¯

+    //bit10±íʾpage numberÊÇ·ñÐèÒªÏòÉϹæÕû£¬ÈçTLCÊÇ192page/block£¬ÎªÁ˶ÔÆëÏÂÒ»¸öblockÔòÐèÒª¹æÕûΪ256page/block¸øÇý¶¯

+    

+    //bit8~9±íʾspareÇøÓò´óСµÄ¸ß룬µ¥Î»ÊÇ256 Bytes¡£Òòspare_size½öΪT_U8£¬²»×ãÒÔ±íʾÐÂÐÍnandµÄ400¶à¸ö×Ö½ÚµÄspare´óС

+    //bit4-7±íʾECCÀàÐÍ£¬0Ϊ4 bit/512B£¬1Ϊ8 bit/512B£¬2Ϊ12 bit/512B£¬3Ϊ16 bit/512B£¬4Ϊ24 bit/1024B£¬5Ϊ32 bit/1024B

+    //bit0±íʾÔÚͬһ¸öblockÄÚÊÇ·ñÐèҪ˳Ðòдpage£¬1±íʾÐèÒª°´Ë³Ðòд£¬¼´¸ÃnandΪMLC

+    //×¢Òâ: Èç¹û(bit29ºÍbit28)Ϊ'11'£¬Ôò±íʾ¸Ãchip°üÀ¨4¸öplane£¬¼ÈÓÐÆæżҲÓÐÇ°ºóplane

+

+    T_U32  cmd_len;//nandflash command length

+    T_U32  data_len;//nandflash data length

+    T_U8   des_str[32];//descriptor string

+}T_NAND_PHY_INFO;

+

+#define ERROR_CHIP_ID   0xFFFFFFFF

+

+/*@}*/

+#ifdef __cplusplus

+}

+#endif

+

+#endif

diff --git a/include/media/hi253.h b/include/media/hi253.h
new file mode 100644
index 00000000000..e5c0863ed6b
--- /dev/null
+++ b/include/media/hi253.h
@@ -0,0 +1,105 @@
+/* hi253 Camera

+ *

+ * Copyright (C) 2008 Renesas Solutions Corp.

+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ */

+

+#ifndef __HI253_H__

+#define __HI253_H__

+

+#include <media/soc_camera.h>

+

+/* for flags */

+#define HI253_FLAG_VFLIP     0x00000001 /* Vertical flip image */

+#define HI253_FLAG_HFLIP     0x00000002 /* Horizontal flip image */

+

+/*

+ * for Edge ctrl

+ *

+ * strength also control Auto or Manual Edge Control Mode

+ * see also HI253_MANUAL_EDGE_CTRL

+ */

+struct hi253_edge_ctrl {

+	unsigned char strength;

+	unsigned char threshold;

+	unsigned char upper;

+	unsigned char lower;

+};

+

+/*

+ * hi253 camera info

+ */

+struct hi253_camera_info {

+	unsigned long		   buswidth;

+	unsigned long		   flags;

+	struct soc_camera_link link;

+	struct hi253_edge_ctrl edgectrl;

+};

+

+

+#define HI253_MANUAL_EDGE_CTRL	0x80 /* un-used bit of strength */

+#define EDGE_STRENGTH_MASK	0x1F

+#define EDGE_THRESHOLD_MASK	0x0F

+#define EDGE_UPPER_MASK		0xFF

+#define EDGE_LOWER_MASK		0xFF

+

+#define HI253_AUTO_EDGECTRL(u, l)	\

+{					\

+	.upper = (u & EDGE_UPPER_MASK),	\

+	.lower = (l & EDGE_LOWER_MASK),	\

+}

+

+#define HI253_MANUAL_EDGECTRL(s, t)					\

+{									\

+	.strength  = (s & EDGE_STRENGTH_MASK) | hi253_MANUAL_EDGE_CTRL,\

+	.threshold = (t & EDGE_THRESHOLD_MASK),				\

+}

+

+/*

+** initialize parameter 

+*/

+

+#define DELAY_FLAG        0xFE   // first parameter is 0xfe, then 2nd parameter is delay time count

+#define END_FLAG          0xFF   // first parameter is 0xff, then parameter table is over 

+

+struct regval_list {

+	unsigned char reg_num;

+	unsigned char value;

+};

+

+extern u32 HI253_pv_HI253_exposure_lines;

+

+extern u32 HI253_cp_HI253_exposure_lines;

+

+extern const struct regval_list hi253_sensor_yuvinit[];

+

+/**---------------------------------------------------------------------------*

+ ** 						Local Variables 								 *

+ **---------------------------------------------------------------------------*/

+

+/*lint -save -e533 */

+extern const struct regval_list hi253_sensor_yuv640X480[];

+

+extern const struct regval_list hi253_sensor_yuv352X288[];

+	

+extern const struct regval_list hi253_sensor_yuv800X600[];

+

+extern const struct regval_list hi253_sensor_yuv1600X1200[];

+

+

+/******************************************************************************/

+// Description: set brightness 

+// Global resource dependence: 

+// Author:

+// Note:

+//		level  must smaller than 8

+/******************************************************************************/

+extern const struct regval_list HI253_brightness_tab[][7];

+extern const struct regval_list HI253_YUV_640X480[];

+

+#endif /* END __HI253_H__ */

+

diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
index be51ae2bd0f..b5ff06f3498 100644
--- a/include/mtd/mtd-abi.h
+++ b/include/mtd/mtd-abi.h
@@ -119,7 +119,7 @@ struct nand_oobinfo {
 	__u32 useecc;
 	__u32 eccbytes;
 	__u32 oobfree[8][2];
-	__u32 eccpos[32];
+	__u32 eccpos[96];
 };
 
 struct nand_oobfree {
@@ -128,6 +128,8 @@ struct nand_oobfree {
 };
 
 #define MTD_MAX_OOBFREE_ENTRIES	8
+//#define MTD_MAX_OOBFREE_ENTRIES	16         //Lynn
+
 /*
  * ECC layout control structure. Exported to userspace for
  * diagnosis and to allow creation of raw images
@@ -135,6 +137,7 @@ struct nand_oobfree {
 struct nand_ecclayout {
 	__u32 eccbytes;
 	__u32 eccpos[64];
+	//__u32 eccpos[256];
 	__u32 oobavail;
 	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
 };
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
index ed3aea1605e..bfd23aeedc4 100644
--- a/include/net/bluetooth/hci.h
+++ b/include/net/bluetooth/hci.h
@@ -139,15 +139,20 @@ enum {
 #define ESCO_2EV5	0x0100
 #define ESCO_3EV5	0x0200
 
-#define SCO_ESCO_MASK  (ESCO_HV1 | ESCO_HV2 | ESCO_HV3)
-#define EDR_ESCO_MASK  (ESCO_2EV3 | ESCO_3EV3 | ESCO_2EV5 | ESCO_3EV5)
+#define SCO_ESCO_MASK	(ESCO_HV1 | ESCO_HV2 | ESCO_HV3)
+#define EDR_ESCO_MASK	(ESCO_2EV3 | ESCO_3EV3 | ESCO_2EV5 | ESCO_3EV5)
+#define ALL_ESCO_MASK	(SCO_ESCO_MASK | ESCO_EV3 | ESCO_EV4 | ESCO_EV5 | \
+			EDR_ESCO_MASK)
 
 /* ACL flags */
+#define ACL_START_NO_FLUSH	0x00
 #define ACL_CONT		0x01
 #define ACL_START		0x02
 #define ACL_ACTIVE_BCAST	0x04
 #define ACL_PICO_BCAST		0x08
 
+#define ACL_PB_MASK	(ACL_CONT | ACL_START)
+
 /* Baseband links */
 #define SCO_LINK	0x00
 #define ACL_LINK	0x01
@@ -186,6 +191,7 @@ enum {
 #define LMP_EDR_ESCO_3M	0x40
 #define LMP_EDR_3S_ESCO	0x80
 
+#define LMP_NO_FLUSH	0x01
 #define LMP_SIMPLE_PAIR	0x08
 
 /* Connection modes */
@@ -991,6 +997,9 @@ struct hci_conn_info {
 	__u8     out;
 	__u16    state;
 	__u32    link_mode;
+	__u32    mtu;
+	__u32    cnt;
+	__u32    pkts;
 };
 
 struct hci_dev_req {
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 7b640aeddb6..f5da4e6cfc2 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -326,12 +326,15 @@ void hci_acl_disconn(struct hci_conn *conn, __u8 reason);
 void hci_add_sco(struct hci_conn *conn, __u16 handle);
 void hci_setup_sync(struct hci_conn *conn, __u16 handle);
 
-struct hci_conn *hci_conn_add(struct hci_dev *hdev, int type, bdaddr_t *dst);
+struct hci_conn *hci_conn_add(struct hci_dev *hdev, int type,
+					__u16 pkt_type, bdaddr_t *dst);
 int hci_conn_del(struct hci_conn *conn);
 void hci_conn_hash_flush(struct hci_dev *hdev);
 void hci_conn_check_pending(struct hci_dev *hdev);
 
-struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8 sec_level, __u8 auth_type);
+struct hci_conn *hci_connect(struct hci_dev *hdev, int type,
+					__u16 pkt_type, bdaddr_t *dst,
+					__u8 sec_level, __u8 auth_type);
 int hci_conn_check_link_mode(struct hci_conn *conn);
 int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type);
 int hci_conn_change_link_key(struct hci_conn *conn);
@@ -358,7 +361,7 @@ static inline void hci_conn_put(struct hci_conn *conn)
 			if (conn->state == BT_CONNECTED) {
 				timeo = msecs_to_jiffies(conn->disc_timeout);
 				if (!conn->out)
-					timeo *= 2;
+					timeo *= 20;
 			} else
 				timeo = msecs_to_jiffies(10);
 		} else
@@ -476,6 +479,7 @@ void hci_conn_del_sysfs(struct hci_conn *conn);
 #define lmp_sniffsubr_capable(dev) ((dev)->features[5] & LMP_SNIFF_SUBR)
 #define lmp_esco_capable(dev)      ((dev)->features[3] & LMP_ESCO)
 #define lmp_ssp_capable(dev)       ((dev)->features[6] & LMP_SIMPLE_PAIR)
+#define lmp_no_flush_capable(dev)  ((dev)->features[6] & LMP_NO_FLUSH)
 
 /* ----- HCI protocols ----- */
 struct hci_proto {
diff --git a/include/net/bluetooth/l2cap.h b/include/net/bluetooth/l2cap.h
index 9516f4b4a3c..23f37b48797 100644
--- a/include/net/bluetooth/l2cap.h
+++ b/include/net/bluetooth/l2cap.h
@@ -70,6 +70,7 @@ struct l2cap_conninfo {
 #define L2CAP_LM_TRUSTED	0x0008
 #define L2CAP_LM_RELIABLE	0x0010
 #define L2CAP_LM_SECURE		0x0020
+#define L2CAP_LM_FLUSHABLE	0x0040
 
 /* L2CAP command codes */
 #define L2CAP_COMMAND_REJ	0x01
@@ -316,6 +317,7 @@ struct l2cap_pinfo {
 	__u8		sec_level;
 	__u8		role_switch;
 	__u8		force_reliable;
+	__u8		flushable;
 
 	__u8		conf_req[64];
 	__u8		conf_len;
diff --git a/include/net/bluetooth/rfcomm.h b/include/net/bluetooth/rfcomm.h
index 921d7b3c7f8..c274993234e 100644
--- a/include/net/bluetooth/rfcomm.h
+++ b/include/net/bluetooth/rfcomm.h
@@ -29,7 +29,6 @@
 #define RFCOMM_CONN_TIMEOUT (HZ * 30)
 #define RFCOMM_DISC_TIMEOUT (HZ * 20)
 #define RFCOMM_AUTH_TIMEOUT (HZ * 25)
-#define RFCOMM_IDLE_TIMEOUT (HZ * 2)
 
 #define RFCOMM_DEFAULT_MTU	127
 #define RFCOMM_DEFAULT_CREDITS	7
@@ -155,7 +154,6 @@ struct rfcomm_msc {
 struct rfcomm_session {
 	struct list_head list;
 	struct socket   *sock;
-	struct timer_list timer;
 	unsigned long    state;
 	unsigned long    flags;
 	atomic_t         refcnt;
diff --git a/include/net/bluetooth/sco.h b/include/net/bluetooth/sco.h
index e28a2a77147..924338ac322 100644
--- a/include/net/bluetooth/sco.h
+++ b/include/net/bluetooth/sco.h
@@ -37,6 +37,7 @@
 struct sockaddr_sco {
 	sa_family_t	sco_family;
 	bdaddr_t	sco_bdaddr;
+	__u16		sco_pkt_type;
 };
 
 /* SCO socket options */
@@ -72,7 +73,8 @@ struct sco_conn {
 
 struct sco_pinfo {
 	struct bt_sock	bt;
-	__u32		flags;
+	__u16		pkt_type;
+
 	struct sco_conn	*conn;
 };
 
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 842ac4de21c..b9648890b3e 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1449,6 +1449,8 @@ extern struct sk_buff **tcp4_gro_receive(struct sk_buff **head,
 extern int tcp_gro_complete(struct sk_buff *skb);
 extern int tcp4_gro_complete(struct sk_buff *skb);
 
+extern void tcp_v4_nuke_addr(__u32 saddr);
+
 #ifdef CONFIG_PROC_FS
 extern int  tcp4_proc_init(void);
 extern void tcp4_proc_exit(void);
diff --git a/include/video/anyka_lcdc.h b/include/video/anyka_lcdc.h
new file mode 100644
index 00000000000..20adcb3808e
--- /dev/null
+++ b/include/video/anyka_lcdc.h
@@ -0,0 +1,66 @@
+/*
+ *  Header file for AK88 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2010 Anyka Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ANYKA_LCDC_H__
+#define __ANYKA_LCDC_H__
+
+#include <linux/workqueue.h>
+
+/* Way LCD wires are connected to the chip:
+ * Some Anyka chips use BGR color mode (instead of standard RGB)
+ * A swapped wiring onboard can bring to RGB mode.
+ */
+
+#define ANYKA_LCDC_WIRING_BGR		0
+#define ANYKA_LCDC_WIRING_RGB		1
+#define ANYKA_LCDC_WIRING_RGB555	2
+
+ /* LCD Controller info data structure, stored in device platform_data */
+struct anyka_lcdfb_info {
+	spinlock_t lock;
+	struct fb_info *info;
+	void __iomem *mmio;
+	int irq_base;
+	struct work_struct task;
+
+	unsigned int guard_time;
+	unsigned int smem_len;
+	struct platform_device *pdev;
+	struct clk *bus_clk;
+	struct clk *lcdc_clk;
+
+#ifdef CONFIG_BACKLIGHT_ANYKA_LCDC
+	struct backlight_device *backlight;
+	u8 bl_power;
+#endif
+	bool lcdcon_is_backlight;
+	u8 saved_lcdcon;
+
+	u8 default_bpp;
+	u8 lcd_wiring_mode;
+	unsigned int default_lcdcon2;
+	unsigned int default_dmacon;
+	void (*anyka_lcdfb_power_control) (int on);
+	struct fb_monspecs *default_monspecs;
+	u32 pseudo_palette[16];
+};
+
+#endif				/* __ANYKA_LCDC_H__ */
diff --git a/init/Kconfig b/init/Kconfig
index eb4b33725db..c244706e262 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -737,6 +737,12 @@ config SYSCTL
 config ANON_INODES
 	bool
 
+config PANIC_TIMEOUT
+	int "Default panic timeout"
+	default 0
+	help
+	  Set default panic timeout.
+
 menuconfig EMBEDDED
 	bool "Configure standard kernel features (for small systems)"
 	help
@@ -908,6 +914,15 @@ config SHMEM
 	  option replaces shmem and tmpfs with the much simpler ramfs code,
 	  which may be appropriate on small systems without swap.
 
+config ASHMEM
+	bool "Enable the Anonymous Shared Memory Subsystem"
+	default n
+	depends on SHMEM || TINY_SHMEM
+	help
+	  The ashmem subsystem is a new shared memory allocator, similar to
+	  POSIX SHM but with different behavior and sporting a simpler
+	  file-based API.
+
 config AIO
 	bool "Enable AIO support" if EMBEDDED
 	default y
diff --git a/kernel/cgroup.c b/kernel/cgroup.c
index 1fbcc748044..29500c8fe8e 100644
--- a/kernel/cgroup.c
+++ b/kernel/cgroup.c
@@ -51,6 +51,7 @@
 #include <linux/pid_namespace.h>
 #include <linux/idr.h>
 #include <linux/vmalloc.h> /* TODO: replace with more sophisticated array */
+#include <linux/capability.h>
 
 #include <asm/atomic.h>
 
@@ -1555,6 +1556,15 @@ int cgroup_attach_task(struct cgroup *cgrp, struct task_struct *tsk)
 			retval = ss->can_attach(ss, cgrp, tsk, false);
 			if (retval)
 				return retval;
+		} else if (!capable(CAP_SYS_ADMIN)) {
+			const struct cred *cred = current_cred(), *tcred;
+
+			/* No can_attach() - check perms generically */
+			tcred = __task_cred(tsk);
+			if (cred->euid != tcred->uid &&
+			    cred->euid != tcred->suid) {
+				return -EACCES;
+			}
 		}
 	}
 
@@ -1611,7 +1621,6 @@ int cgroup_attach_task(struct cgroup *cgrp, struct task_struct *tsk)
 static int attach_task_by_pid(struct cgroup *cgrp, u64 pid)
 {
 	struct task_struct *tsk;
-	const struct cred *cred = current_cred(), *tcred;
 	int ret;
 
 	if (pid) {
@@ -1621,14 +1630,6 @@ static int attach_task_by_pid(struct cgroup *cgrp, u64 pid)
 			rcu_read_unlock();
 			return -ESRCH;
 		}
-
-		tcred = __task_cred(tsk);
-		if (cred->euid &&
-		    cred->euid != tcred->uid &&
-		    cred->euid != tcred->suid) {
-			rcu_read_unlock();
-			return -EACCES;
-		}
 		get_task_struct(tsk);
 		rcu_read_unlock();
 	} else {
diff --git a/kernel/cgroup_freezer.c b/kernel/cgroup_freezer.c
index 59e9ef6aab4..67b155f65a6 100644
--- a/kernel/cgroup_freezer.c
+++ b/kernel/cgroup_freezer.c
@@ -163,6 +163,14 @@ static int freezer_can_attach(struct cgroup_subsys *ss,
 {
 	struct freezer *freezer;
 
+	if ((current != task) && (!capable(CAP_SYS_ADMIN))) {
+		const struct cred *cred = current_cred(), *tcred;
+
+		tcred = __task_cred(task);
+		if (cred->euid != tcred->uid && cred->euid != tcred->suid)
+			return -EPERM;
+	}
+
 	/*
 	 * Anything frozen can't move or be moved to/from.
 	 *
diff --git a/kernel/cpuset.c b/kernel/cpuset.c
index 39e5121a78a..993c884ccb4 100644
--- a/kernel/cpuset.c
+++ b/kernel/cpuset.c
@@ -1330,6 +1330,13 @@ static int cpuset_can_attach(struct cgroup_subsys *ss, struct cgroup *cont,
 	int ret;
 	struct cpuset *cs = cgroup_cs(cont);
 
+	if ((current != tsk) && (!capable(CAP_SYS_ADMIN))) {
+		const struct cred *cred = current_cred(), *tcred;
+
+		if (cred->euid != tcred->uid && cred->euid != tcred->suid)
+			return -EPERM;
+	}
+ 
 	if (cpumask_empty(cs->cpus_allowed) || nodes_empty(cs->mems_allowed))
 		return -ENOSPC;
 
diff --git a/kernel/fork.c b/kernel/fork.c
index 166b8c49257..2cfa6dcfd44 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -138,6 +138,9 @@ struct kmem_cache *vm_area_cachep;
 /* SLAB cache for mm_struct structures (tsk->mm) */
 static struct kmem_cache *mm_cachep;
 
+/* Notifier list called when a task struct is freed */
+static ATOMIC_NOTIFIER_HEAD(task_free_notifier);
+
 static void account_kernel_stack(struct thread_info *ti, int account)
 {
 	struct zone *zone = page_zone(virt_to_page(ti));
@@ -156,6 +159,18 @@ void free_task(struct task_struct *tsk)
 }
 EXPORT_SYMBOL(free_task);
 
+int task_free_register(struct notifier_block *n)
+{
+	return atomic_notifier_chain_register(&task_free_notifier, n);
+}
+EXPORT_SYMBOL(task_free_register);
+
+int task_free_unregister(struct notifier_block *n)
+{
+	return atomic_notifier_chain_unregister(&task_free_notifier, n);
+}
+EXPORT_SYMBOL(task_free_unregister);
+
 void __put_task_struct(struct task_struct *tsk)
 {
 	WARN_ON(!tsk->exit_state);
@@ -165,6 +180,7 @@ void __put_task_struct(struct task_struct *tsk)
 	exit_creds(tsk);
 	delayacct_tsk_free(tsk);
 
+	atomic_notifier_call_chain(&task_free_notifier, 0, tsk);
 	if (!profile_handoff_task(tsk))
 		free_task(tsk);
 }
diff --git a/kernel/futex.c b/kernel/futex.c
index 1ad4fa6db72..c6a80616fcf 100644
--- a/kernel/futex.c
+++ b/kernel/futex.c
@@ -220,6 +220,7 @@ get_futex_key(u32 __user *uaddr, int fshared, union futex_key *key)
 	struct mm_struct *mm = current->mm;
 	struct page *page;
 	int err;
+	struct vm_area_struct *vma;
 
 	/*
 	 * The futex address must be "naturally" aligned.
@@ -245,6 +246,37 @@ get_futex_key(u32 __user *uaddr, int fshared, union futex_key *key)
 		return 0;
 	}
 
+	/*
+	 * The futex is hashed differently depending on whether
+	 * it's in a shared or private mapping.  So check vma first.
+	 */
+	vma = find_extend_vma(mm, address);
+	if (unlikely(!vma))
+		return -EFAULT;
+
+	/*
+	 * Permissions.
+	 */
+	if (unlikely((vma->vm_flags & (VM_IO|VM_READ)) != VM_READ))
+		return (vma->vm_flags & VM_IO) ? -EPERM : -EACCES;
+
+	/*
+	 * Private mappings are handled in a simple way.
+	 *
+	 * NOTE: When userspace waits on a MAP_SHARED mapping, even if
+	 * it's a read-only handle, it's expected that futexes attach to
+	 * the object not the particular process.  Therefore we use
+	 * VM_MAYSHARE here, not VM_SHARED which is restricted to shared
+	 * mappings of _writable_ handles.
+	 */
+	if (likely(!(vma->vm_flags & VM_MAYSHARE))) {
+		key->both.offset |= FUT_OFF_MMSHARED; /* reference taken on mm */
+		key->private.mm = mm;
+		key->private.address = address;
+		get_futex_key_refs(key);
+		return 0;
+	}
+
 again:
 	err = get_user_pages_fast(address, 1, 1, &page);
 	if (err < 0)
diff --git a/kernel/panic.c b/kernel/panic.c
index 96b45d0b4ba..5fc6031d195 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -29,7 +29,10 @@ static int pause_on_oops;
 static int pause_on_oops_flag;
 static DEFINE_SPINLOCK(pause_on_oops_lock);
 
-int panic_timeout;
+#ifndef CONFIG_PANIC_TIMEOUT
+#define CONFIG_PANIC_TIMEOUT 0
+#endif
+int panic_timeout = CONFIG_PANIC_TIMEOUT;
 
 ATOMIC_NOTIFIER_HEAD(panic_notifier_list);
 
diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
index 91e09d3b2eb..1621b707647 100644
--- a/kernel/power/Kconfig
+++ b/kernel/power/Kconfig
@@ -119,6 +119,73 @@ config SUSPEND_FREEZER
 config HIBERNATION_NVS
 	bool
 
+config HAS_WAKELOCK
+	bool
+
+config HAS_EARLYSUSPEND
+	bool
+
+config WAKELOCK
+	bool "Wake lock"
+	depends on PM && RTC_CLASS
+	default n
+	select HAS_WAKELOCK
+	---help---
+	  Enable wakelocks. When user space request a sleep state the
+	  sleep request will be delayed until no wake locks are held.
+
+config WAKELOCK_STAT
+	bool "Wake lock stats"
+	depends on WAKELOCK
+	default y
+	---help---
+	  Report wake lock stats in /proc/wakelocks
+
+config USER_WAKELOCK
+	bool "Userspace wake locks"
+	depends on WAKELOCK
+	default y
+	---help---
+	  User-space wake lock api. Write "lockname" or "lockname timeout"
+	  to /sys/power/wake_lock lock and if needed create a wake lock.
+	  Write "lockname" to /sys/power/wake_unlock to unlock a user wake
+	  lock.
+
+config EARLYSUSPEND
+	bool "Early suspend"
+	depends on WAKELOCK
+	default y
+	select HAS_EARLYSUSPEND
+	---help---
+	  Call early suspend handlers when the user requested sleep state
+	  changes.
+
+choice
+	prompt "User-space screen access"
+	default FB_EARLYSUSPEND if !FRAMEBUFFER_CONSOLE
+	default CONSOLE_EARLYSUSPEND
+	depends on HAS_EARLYSUSPEND
+
+	config NO_USER_SPACE_SCREEN_ACCESS_CONTROL
+		bool "None"
+
+	config CONSOLE_EARLYSUSPEND
+		bool "Console switch on early-suspend"
+		depends on HAS_EARLYSUSPEND && VT
+		---help---
+		  Register early suspend handler to perform a console switch to
+		  when user-space should stop drawing to the screen and a switch
+		  back when it should resume.
+
+	config FB_EARLYSUSPEND
+		bool "Sysfs interface"
+		depends on HAS_EARLYSUSPEND
+		---help---
+		  Register early suspend handler that notifies and waits for
+		  user-space through sysfs when user-space should stop drawing
+		  to the screen and notifies user-space when it should resume.
+endchoice
+
 config HIBERNATION
 	bool "Hibernation (aka 'suspend to disk')"
 	depends on PM && SWAP && ARCH_HIBERNATION_POSSIBLE
diff --git a/kernel/power/Makefile b/kernel/power/Makefile
index c3b81c30e5d..3231c48a579 100644
--- a/kernel/power/Makefile
+++ b/kernel/power/Makefile
@@ -10,5 +10,10 @@ obj-$(CONFIG_SUSPEND)		+= suspend.o
 obj-$(CONFIG_PM_TEST_SUSPEND)	+= suspend_test.o
 obj-$(CONFIG_HIBERNATION)	+= swsusp.o hibernate.o snapshot.o swap.o user.o
 obj-$(CONFIG_HIBERNATION_NVS)	+= hibernate_nvs.o
+obj-$(CONFIG_WAKELOCK)		+= wakelock.o
+obj-$(CONFIG_USER_WAKELOCK)	+= userwakelock.o
+obj-$(CONFIG_EARLYSUSPEND)	+= earlysuspend.o
+obj-$(CONFIG_CONSOLE_EARLYSUSPEND)	+= consoleearlysuspend.o
+obj-$(CONFIG_FB_EARLYSUSPEND)	+= fbearlysuspend.o
 
 obj-$(CONFIG_MAGIC_SYSRQ)	+= poweroff.o
diff --git a/kernel/power/consoleearlysuspend.c b/kernel/power/consoleearlysuspend.c
new file mode 100644
index 00000000000..a3edcb26738
--- /dev/null
+++ b/kernel/power/consoleearlysuspend.c
@@ -0,0 +1,78 @@
+/* kernel/power/consoleearlysuspend.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/earlysuspend.h>
+#include <linux/kbd_kern.h>
+#include <linux/module.h>
+#include <linux/vt_kern.h>
+#include <linux/wait.h>
+
+#define EARLY_SUSPEND_CONSOLE	(MAX_NR_CONSOLES-1)
+
+static int orig_fgconsole;
+static void console_early_suspend(struct early_suspend *h)
+{
+	acquire_console_sem();
+	orig_fgconsole = fg_console;
+	if (vc_allocate(EARLY_SUSPEND_CONSOLE))
+		goto err;
+	if (set_console(EARLY_SUSPEND_CONSOLE))
+		goto err;
+	release_console_sem();
+
+	if (vt_waitactive(EARLY_SUSPEND_CONSOLE + 1))
+		pr_warning("console_early_suspend: Can't switch VCs.\n");
+	return;
+err:
+	pr_warning("console_early_suspend: Can't set console\n");
+	release_console_sem();
+}
+
+static void console_late_resume(struct early_suspend *h)
+{
+	int ret;
+	acquire_console_sem();
+	ret = set_console(orig_fgconsole);
+	release_console_sem();
+	if (ret) {
+		pr_warning("console_late_resume: Can't set console.\n");
+		return;
+	}
+
+	if (vt_waitactive(orig_fgconsole + 1))
+		pr_warning("console_late_resume: Can't switch VCs.\n");
+}
+
+static struct early_suspend console_early_suspend_desc = {
+	.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING,
+	.suspend = console_early_suspend,
+	.resume = console_late_resume,
+};
+
+static int __init console_early_suspend_init(void)
+{
+	register_early_suspend(&console_early_suspend_desc);
+	return 0;
+}
+
+static void  __exit console_early_suspend_exit(void)
+{
+	unregister_early_suspend(&console_early_suspend_desc);
+}
+
+module_init(console_early_suspend_init);
+module_exit(console_early_suspend_exit);
+
diff --git a/kernel/power/earlysuspend.c b/kernel/power/earlysuspend.c
new file mode 100644
index 00000000000..84bed51dcdc
--- /dev/null
+++ b/kernel/power/earlysuspend.c
@@ -0,0 +1,178 @@
+/* kernel/power/earlysuspend.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/earlysuspend.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/rtc.h>
+#include <linux/syscalls.h> /* sys_sync */
+#include <linux/wakelock.h>
+#include <linux/workqueue.h>
+
+#include "power.h"
+
+enum {
+	DEBUG_USER_STATE = 1U << 0,
+	DEBUG_SUSPEND = 1U << 2,
+};
+static int debug_mask = DEBUG_USER_STATE;
+module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+static DEFINE_MUTEX(early_suspend_lock);
+static LIST_HEAD(early_suspend_handlers);
+static void early_suspend(struct work_struct *work);
+static void late_resume(struct work_struct *work);
+static DECLARE_WORK(early_suspend_work, early_suspend);
+static DECLARE_WORK(late_resume_work, late_resume);
+static DEFINE_SPINLOCK(state_lock);
+enum {
+	SUSPEND_REQUESTED = 0x1,
+	SUSPENDED = 0x2,
+	SUSPEND_REQUESTED_AND_SUSPENDED = SUSPEND_REQUESTED | SUSPENDED,
+};
+static int state;
+
+void register_early_suspend(struct early_suspend *handler)
+{
+	struct list_head *pos;
+
+	mutex_lock(&early_suspend_lock);
+	list_for_each(pos, &early_suspend_handlers) {
+		struct early_suspend *e;
+		e = list_entry(pos, struct early_suspend, link);
+		if (e->level > handler->level)
+			break;
+	}
+	list_add_tail(&handler->link, pos);
+	if ((state & SUSPENDED) && handler->suspend)
+		handler->suspend(handler);
+	mutex_unlock(&early_suspend_lock);
+}
+EXPORT_SYMBOL(register_early_suspend);
+
+void unregister_early_suspend(struct early_suspend *handler)
+{
+	mutex_lock(&early_suspend_lock);
+	list_del(&handler->link);
+	mutex_unlock(&early_suspend_lock);
+}
+EXPORT_SYMBOL(unregister_early_suspend);
+
+static void early_suspend(struct work_struct *work)
+{
+	struct early_suspend *pos;
+	unsigned long irqflags;
+	int abort = 0;
+
+	mutex_lock(&early_suspend_lock);
+	spin_lock_irqsave(&state_lock, irqflags);
+	if (state == SUSPEND_REQUESTED)
+		state |= SUSPENDED;
+	else
+		abort = 1;
+	spin_unlock_irqrestore(&state_lock, irqflags);
+
+	if (abort) {
+		if (debug_mask & DEBUG_SUSPEND)
+			pr_info("early_suspend: abort, state %d\n", state);
+		mutex_unlock(&early_suspend_lock);
+		goto abort;
+	}
+
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("early_suspend: call handlers\n");
+	list_for_each_entry(pos, &early_suspend_handlers, link) {
+		if (pos->suspend != NULL)
+			pos->suspend(pos);
+	}
+	mutex_unlock(&early_suspend_lock);
+
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("early_suspend: sync\n");
+
+	sys_sync();
+abort:
+	spin_lock_irqsave(&state_lock, irqflags);
+	if (state == SUSPEND_REQUESTED_AND_SUSPENDED)
+		wake_unlock(&main_wake_lock);
+	spin_unlock_irqrestore(&state_lock, irqflags);
+}
+
+static void late_resume(struct work_struct *work)
+{
+	struct early_suspend *pos;
+	unsigned long irqflags;
+	int abort = 0;
+
+	mutex_lock(&early_suspend_lock);
+	spin_lock_irqsave(&state_lock, irqflags);
+	if (state == SUSPENDED)
+		state &= ~SUSPENDED;
+	else
+		abort = 1;
+	spin_unlock_irqrestore(&state_lock, irqflags);
+
+	if (abort) {
+		if (debug_mask & DEBUG_SUSPEND)
+			pr_info("late_resume: abort, state %d\n", state);
+		goto abort;
+	}
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("late_resume: call handlers\n");
+	list_for_each_entry_reverse(pos, &early_suspend_handlers, link)
+		if (pos->resume != NULL)
+			pos->resume(pos);
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("late_resume: done\n");
+abort:
+	mutex_unlock(&early_suspend_lock);
+}
+
+void request_suspend_state(suspend_state_t new_state)
+{
+	unsigned long irqflags;
+	int old_sleep;
+
+	spin_lock_irqsave(&state_lock, irqflags);
+	old_sleep = state & SUSPEND_REQUESTED;
+	if (debug_mask & DEBUG_USER_STATE) {
+		struct timespec ts;
+		struct rtc_time tm;
+		getnstimeofday(&ts);
+		rtc_time_to_tm(ts.tv_sec, &tm);
+		pr_info("request_suspend_state: %s (%d->%d) at %lld "
+			"(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
+			new_state != PM_SUSPEND_ON ? "sleep" : "wakeup",
+			requested_suspend_state, new_state,
+			ktime_to_ns(ktime_get()),
+			tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+			tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
+	}
+	if (!old_sleep && new_state != PM_SUSPEND_ON) {
+		state |= SUSPEND_REQUESTED;
+		queue_work(suspend_work_queue, &early_suspend_work);
+	} else if (old_sleep && new_state == PM_SUSPEND_ON) {
+		state &= ~SUSPEND_REQUESTED;
+		wake_lock(&main_wake_lock);
+		queue_work(suspend_work_queue, &late_resume_work);
+	}
+	requested_suspend_state = new_state;
+	spin_unlock_irqrestore(&state_lock, irqflags);
+}
+
+suspend_state_t get_suspend_state(void)
+{
+	return requested_suspend_state;
+}
diff --git a/kernel/power/fbearlysuspend.c b/kernel/power/fbearlysuspend.c
new file mode 100644
index 00000000000..15137650149
--- /dev/null
+++ b/kernel/power/fbearlysuspend.c
@@ -0,0 +1,153 @@
+/* kernel/power/fbearlysuspend.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/earlysuspend.h>
+#include <linux/module.h>
+#include <linux/wait.h>
+
+#include "power.h"
+
+static wait_queue_head_t fb_state_wq;
+static DEFINE_SPINLOCK(fb_state_lock);
+static enum {
+	FB_STATE_STOPPED_DRAWING,
+	FB_STATE_REQUEST_STOP_DRAWING,
+	FB_STATE_DRAWING_OK,
+} fb_state;
+
+/* tell userspace to stop drawing, wait for it to stop */
+static void stop_drawing_early_suspend(struct early_suspend *h)
+{
+	int ret;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&fb_state_lock, irq_flags);
+	fb_state = FB_STATE_REQUEST_STOP_DRAWING;
+	spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+
+	wake_up_all(&fb_state_wq);
+	ret = wait_event_timeout(fb_state_wq,
+				 fb_state == FB_STATE_STOPPED_DRAWING,
+				 HZ);
+	if (unlikely(fb_state != FB_STATE_STOPPED_DRAWING))
+		pr_warning("stop_drawing_early_suspend: timeout waiting for "
+			   "userspace to stop drawing\n");
+}
+
+/* tell userspace to start drawing */
+static void start_drawing_late_resume(struct early_suspend *h)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&fb_state_lock, irq_flags);
+	fb_state = FB_STATE_DRAWING_OK;
+	spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+	wake_up(&fb_state_wq);
+}
+
+static struct early_suspend stop_drawing_early_suspend_desc = {
+	.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING,
+	.suspend = stop_drawing_early_suspend,
+	.resume = start_drawing_late_resume,
+};
+
+static ssize_t wait_for_fb_sleep_show(struct kobject *kobj,
+				      struct kobj_attribute *attr, char *buf)
+{
+	char *s = buf;
+	int ret;
+
+	ret = wait_event_interruptible(fb_state_wq,
+				       fb_state != FB_STATE_DRAWING_OK);
+	if (ret && fb_state == FB_STATE_DRAWING_OK)
+		return ret;
+	else
+		s += sprintf(buf, "sleeping");
+	return s - buf;
+}
+
+static ssize_t wait_for_fb_wake_show(struct kobject *kobj,
+				     struct kobj_attribute *attr, char *buf)
+{
+	char *s = buf;
+	int ret;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&fb_state_lock, irq_flags);
+	if (fb_state == FB_STATE_REQUEST_STOP_DRAWING) {
+		fb_state = FB_STATE_STOPPED_DRAWING;
+		wake_up(&fb_state_wq);
+	}
+	spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+
+	ret = wait_event_interruptible(fb_state_wq,
+				       fb_state == FB_STATE_DRAWING_OK);
+	if (ret && fb_state != FB_STATE_DRAWING_OK)
+		return ret;
+	else
+		s += sprintf(buf, "awake");
+
+	return s - buf;
+}
+
+#define power_ro_attr(_name) \
+static struct kobj_attribute _name##_attr = {	\
+	.attr	= {				\
+		.name = __stringify(_name),	\
+		.mode = 0444,			\
+	},					\
+	.show	= _name##_show,			\
+	.store	= NULL,		\
+}
+
+power_ro_attr(wait_for_fb_sleep);
+power_ro_attr(wait_for_fb_wake);
+
+static struct attribute *g[] = {
+	&wait_for_fb_sleep_attr.attr,
+	&wait_for_fb_wake_attr.attr,
+	NULL,
+};
+
+static struct attribute_group attr_group = {
+	.attrs = g,
+};
+
+static int __init android_power_init(void)
+{
+	int ret;
+
+	init_waitqueue_head(&fb_state_wq);
+	fb_state = FB_STATE_DRAWING_OK;
+
+	ret = sysfs_create_group(power_kobj, &attr_group);
+	if (ret) {
+		pr_err("android_power_init: sysfs_create_group failed\n");
+		return ret;
+	}
+
+	register_early_suspend(&stop_drawing_early_suspend_desc);
+	return 0;
+}
+
+static void  __exit android_power_exit(void)
+{
+	unregister_early_suspend(&stop_drawing_early_suspend_desc);
+	sysfs_remove_group(power_kobj, &attr_group);
+}
+
+module_init(android_power_init);
+module_exit(android_power_exit);
+
diff --git a/kernel/power/main.c b/kernel/power/main.c
index 347d2cc88cd..cde13acc325 100644
--- a/kernel/power/main.c
+++ b/kernel/power/main.c
@@ -20,6 +20,31 @@ DEFINE_MUTEX(pm_mutex);
 unsigned int pm_flags;
 EXPORT_SYMBOL(pm_flags);
 
+#ifdef CONFIG_CPU_FREQ
+DEFINE_MUTEX(cpufreq_mutex);
+
+static struct platform_suspend_ops *cpufreq_ops;
+
+static int cpu_freq_mode[] = {
+	CPU_FREQ_NORMAL_100M,
+	CPU_FREQ_NORMAL_200M,
+	CPU_FREQ_NORMAL_400M,
+	CPU_FREQ_VIDEO,
+	CPU_FREQ_LOW_CLOCK,
+};
+
+/**
+ *  cpufreq_set_ops - Set the global cpufreq method table.
+ *  @ops:   Pointer to ops structure.
+ */
+void cpufreq_set_ops(struct platform_suspend_ops * ops)
+{
+    mutex_lock(&cpufreq_mutex);
+    cpufreq_ops = ops;
+    mutex_unlock(&cpufreq_mutex);
+}
+#endif
+
 #ifdef CONFIG_PM_SLEEP
 
 /* Routines for PM-transition notifications */
@@ -146,8 +171,13 @@ static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr,
 static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr,
 			   const char *buf, size_t n)
 {
+	int i;
 #ifdef CONFIG_SUSPEND
+#ifdef CONFIG_EARLYSUSPEND
+	suspend_state_t state = PM_SUSPEND_ON;
+#else
 	suspend_state_t state = PM_SUSPEND_STANDBY;
+#endif
 	const char * const *s;
 #endif
 	char *p;
@@ -168,8 +198,28 @@ static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr,
 		if (*s && len == strlen(*s) && !strncmp(buf, *s, len))
 			break;
 	}
-	if (state < PM_SUSPEND_MAX && *s)
-		error = enter_state(state);
+	if (state < PM_SUSPEND_MAX && *s) {
+#ifdef CONFIG_EARLYSUSPEND
+		if (state == PM_SUSPEND_ON || valid_state(state)) {
+			error = 0;
+			request_suspend_state(state);
+		}
+#else
+		if(state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM)
+			error = enter_state(state);
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+		for(i = 0; i < ARRAY_SIZE(cpu_freq_mode); i++) {
+			if(cpu_freq_mode[i] == state) {
+				if(cpufreq_ops) {
+					cpufreq_ops->enter(state);
+					break;
+				}
+			}
+		}
+#endif
+	}
 #endif
 
  Exit:
@@ -203,6 +253,11 @@ pm_trace_store(struct kobject *kobj, struct kobj_attribute *attr,
 power_attr(pm_trace);
 #endif /* CONFIG_PM_TRACE */
 
+#ifdef CONFIG_USER_WAKELOCK
+power_attr(wake_lock);
+power_attr(wake_unlock);
+#endif
+
 static struct attribute * g[] = {
 	&state_attr.attr,
 #ifdef CONFIG_PM_TRACE
@@ -211,6 +266,10 @@ static struct attribute * g[] = {
 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PM_DEBUG)
 	&pm_test_attr.attr,
 #endif
+#ifdef CONFIG_USER_WAKELOCK
+	&wake_lock_attr.attr,
+	&wake_unlock_attr.attr,
+#endif
 	NULL,
 };
 
diff --git a/kernel/power/power.h b/kernel/power/power.h
index 46c5a26630a..957d51fea8b 100644
--- a/kernel/power/power.h
+++ b/kernel/power/power.h
@@ -236,3 +236,27 @@ static inline void suspend_thaw_processes(void)
 {
 }
 #endif
+
+#ifdef CONFIG_WAKELOCK
+/* kernel/power/wakelock.c */
+extern struct workqueue_struct *suspend_work_queue;
+extern struct wake_lock main_wake_lock;
+extern suspend_state_t requested_suspend_state;
+#endif
+
+#ifdef CONFIG_USER_WAKELOCK
+ssize_t wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr,
+			char *buf);
+ssize_t wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr,
+			const char *buf, size_t n);
+ssize_t wake_unlock_show(struct kobject *kobj, struct kobj_attribute *attr,
+			char *buf);
+ssize_t  wake_unlock_store(struct kobject *kobj, struct kobj_attribute *attr,
+			const char *buf, size_t n);
+#endif
+
+#ifdef CONFIG_EARLYSUSPEND
+/* kernel/power/earlysuspend.c */
+void request_suspend_state(suspend_state_t state);
+suspend_state_t get_suspend_state(void);
+#endif
diff --git a/kernel/power/process.c b/kernel/power/process.c
index cc2e55373b6..6a152641b11 100644
--- a/kernel/power/process.c
+++ b/kernel/power/process.c
@@ -14,11 +14,14 @@
 #include <linux/module.h>
 #include <linux/syscalls.h>
 #include <linux/freezer.h>
+#include <linux/wakelock.h>
 
 /* 
  * Timeout for stopping processes
  */
 #define TIMEOUT	(20 * HZ)
+#define CPUFREQ_TIMEOUT	(1 * HZ)
+
 
 static inline int freezeable(struct task_struct * p)
 {
@@ -37,6 +40,7 @@ static int try_to_freeze_tasks(bool sig_only)
 	struct timeval start, end;
 	u64 elapsed_csecs64;
 	unsigned int elapsed_csecs;
+	unsigned int wakeup = 0;
 
 	do_gettimeofday(&start);
 
@@ -63,10 +67,14 @@ static int try_to_freeze_tasks(bool sig_only)
 		} while_each_thread(g, p);
 		read_unlock(&tasklist_lock);
 		yield();			/* Yield is okay here */
+		if (todo && has_wake_lock(WAKE_LOCK_SUSPEND)) {
+			wakeup = 1;
+			break;
+		}
 		if (time_after(jiffies, end_time))
 			break;
 	} while (todo);
-
+	
 	do_gettimeofday(&end);
 	elapsed_csecs64 = timeval_to_ns(&end) - timeval_to_ns(&start);
 	do_div(elapsed_csecs64, NSEC_PER_SEC / 100);
@@ -79,14 +87,17 @@ static int try_to_freeze_tasks(bool sig_only)
 		 * but it cleans up leftover PF_FREEZE requests.
 		 */
 		printk("\n");
-		printk(KERN_ERR "Freezing of tasks failed after %d.%02d seconds "
+		printk(KERN_ERR "Freezing of tasks %s after %d.%02d seconds "
 				"(%d tasks refusing to freeze):\n",
+				wakeup ? "aborted" : "failed",
 				elapsed_csecs / 100, elapsed_csecs % 100, todo);
-		show_state();
+		if(!wakeup)
+			show_state();
 		read_lock(&tasklist_lock);
 		do_each_thread(g, p) {
 			task_lock(p);
-			if (freezing(p) && !freezer_should_skip(p))
+			if (freezing(p) && !freezer_should_skip(p) &&
+							elapsed_csecs > 100)
 				printk(KERN_ERR " %s\n", p->comm);
 			cancel_freezing(p);
 			task_unlock(p);
@@ -127,6 +138,109 @@ int freeze_processes(void)
 	return error;
 }
 
+static int cpufreq_try_to_freeze_tasks(bool sig_only)
+{
+	struct task_struct *g, *p;
+	unsigned long end_time;
+	unsigned int todo;
+	struct timeval start, end;
+	u64 elapsed_csecs64;
+	unsigned int elapsed_csecs;
+	unsigned int wakeup = 0;
+	
+	do_gettimeofday(&start);
+
+	end_time = jiffies + CPUFREQ_TIMEOUT;
+	do {
+		todo = 0;
+		read_lock(&tasklist_lock);
+		do_each_thread(g, p) {
+			if (frozen(p) || !freezeable(p))
+				continue;
+
+			if (!freeze_task(p, sig_only))
+				continue;
+
+			/*
+			 * Now that we've done set_freeze_flag, don't
+			 * perturb a task in TASK_STOPPED or TASK_TRACED.
+			 * It is "frozen enough".  If the task does wake
+			 * up, it will immediately call try_to_freeze.
+			 */
+			if (!task_is_stopped_or_traced(p) &&
+			    !freezer_should_skip(p)) {
+				todo++;
+			}
+		} while_each_thread(g, p);	
+		read_unlock(&tasklist_lock);
+		yield();			/* Yield is okay here */
+
+		if (time_after(jiffies, end_time)){
+			break;
+		}
+	} while (todo);
+	
+	do_gettimeofday(&end);
+	elapsed_csecs64 = timeval_to_ns(&end) - timeval_to_ns(&start);
+	do_div(elapsed_csecs64, NSEC_PER_SEC / 100);
+	elapsed_csecs = elapsed_csecs64;
+
+	if (todo) {
+		/* This does not unfreeze processes that are already frozen
+		 * (we have slightly ugly calling convention in that respect,
+		 * and caller must call thaw_processes() if something fails),
+		 * but it cleans up leftover PF_FREEZE requests.
+		 */
+		printk("\n");
+		printk(KERN_ERR "Freezing of tasks %s after %d.%02d seconds "
+				"(%d tasks refusing to freeze):\n",
+				wakeup ? "aborted" : "failed",
+				elapsed_csecs / 100, elapsed_csecs % 100, todo);
+		read_lock(&tasklist_lock);
+		do_each_thread(g, p) {
+			task_lock(p);
+			if (freezing(p) && !freezer_should_skip(p) &&
+							elapsed_csecs > 100)
+				printk(KERN_ERR " %s\n", p->comm);
+			cancel_freezing(p);
+			task_unlock(p);
+		} while_each_thread(g, p);
+		read_unlock(&tasklist_lock);
+	} else {
+		printk("(elapsed %d.%02d seconds) ", elapsed_csecs / 100,
+			elapsed_csecs % 100);
+	}
+
+	return todo ? -EBUSY : 0;
+}
+
+/**
+ *	freeze_processes - tell processes to enter the refrigerator
+ */
+int cpufreq_freeze_processes(void)
+{
+	int error;
+
+	printk("Cpufreq freezing user space processes ... ");
+	error = cpufreq_try_to_freeze_tasks(true);
+	if (error)
+		goto Exit;
+	printk("done.\n");
+
+	printk("Cpufreq freezing remaining freezable tasks ... ");
+	error = cpufreq_try_to_freeze_tasks(false);
+	if (error)
+		goto Exit;
+	printk("done.");
+
+	oom_killer_disable();
+ Exit:
+	BUG_ON(in_atomic());
+	printk("\n");
+
+	return error;
+}
+
 static void thaw_tasks(bool nosig_only)
 {
 	struct task_struct *g, *p;
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 6f10dfc2d3e..247d99691e7 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -18,9 +18,21 @@
 
 #include "power.h"
 
+atomic_t suspend_flags = ATOMIC_INIT(0);
+
 const char *const pm_states[PM_SUSPEND_MAX] = {
+#ifdef CONFIG_EARLYSUSPEND
+	[PM_SUSPEND_ON]		= "on",
+#endif
 	[PM_SUSPEND_STANDBY]	= "standby",
 	[PM_SUSPEND_MEM]	= "mem",
+#ifdef CONFIG_CPU_FREQ
+	[CPU_FREQ_NORMAL_100M] = "normal_100M",
+	[CPU_FREQ_NORMAL_200M] = "normal_200M",
+	[CPU_FREQ_NORMAL_400M] = "normal_400M",
+	[CPU_FREQ_VIDEO] = "video",
+	[CPU_FREQ_LOW_CLOCK] = "low_clock"
+#endif
 };
 
 static struct platform_suspend_ops *suspend_ops;
@@ -261,14 +273,17 @@ int enter_state(suspend_state_t state)
 	if (!mutex_trylock(&pm_mutex))
 		return -EBUSY;
 
+	atomic_inc(&suspend_flags);
 	printk(KERN_INFO "PM: Syncing filesystems ... ");
 	sys_sync();
 	printk("done.\n");
 
 	pr_debug("PM: Preparing system for %s sleep\n", pm_states[state]);
 	error = suspend_prepare();
-	if (error)
+	if (error) {
+		atomic_dec(&suspend_flags);
 		goto Unlock;
+	}
 
 	if (suspend_test(TEST_FREEZER))
 		goto Finish;
@@ -278,6 +293,7 @@ int enter_state(suspend_state_t state)
 
  Finish:
 	pr_debug("PM: Finishing wakeup.\n");
+	atomic_dec(&suspend_flags);
 	suspend_finish();
  Unlock:
 	mutex_unlock(&pm_mutex);
diff --git a/kernel/power/userwakelock.c b/kernel/power/userwakelock.c
new file mode 100644
index 00000000000..d7242d99437
--- /dev/null
+++ b/kernel/power/userwakelock.c
@@ -0,0 +1,218 @@
+/* kernel/power/userwakelock.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/wakelock.h>
+
+#include "power.h"
+
+enum {
+	DEBUG_FAILURE	= BIT(0),
+	DEBUG_ERROR	= BIT(1),
+	DEBUG_NEW	= BIT(2),
+	DEBUG_ACCESS	= BIT(3),
+	DEBUG_LOOKUP	= BIT(4),
+};
+static int debug_mask = DEBUG_FAILURE;
+module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+static DEFINE_MUTEX(tree_lock);
+
+struct user_wake_lock {
+	struct rb_node		node;
+	struct wake_lock	wake_lock;
+	char			name[0];
+};
+struct rb_root user_wake_locks;
+
+static struct user_wake_lock *lookup_wake_lock_name(
+	const char *buf, int allocate, long *timeoutptr)
+{
+	struct rb_node **p = &user_wake_locks.rb_node;
+	struct rb_node *parent = NULL;
+	struct user_wake_lock *l;
+	int diff;
+	u64 timeout;
+	int name_len;
+	const char *arg;
+
+	/* Find length of lock name and start of optional timeout string */
+	arg = buf;
+	while (*arg && !isspace(*arg))
+		arg++;
+	name_len = arg - buf;
+	if (!name_len)
+		goto bad_arg;
+	while (isspace(*arg))
+		arg++;
+
+	/* Process timeout string */
+	if (timeoutptr && *arg) {
+		timeout = simple_strtoull(arg, (char **)&arg, 0);
+		while (isspace(*arg))
+			arg++;
+		if (*arg)
+			goto bad_arg;
+		/* convert timeout from nanoseconds to jiffies > 0 */
+		timeout += (NSEC_PER_SEC / HZ) - 1;
+		do_div(timeout, (NSEC_PER_SEC / HZ));
+		if (timeout <= 0)
+			timeout = 1;
+		*timeoutptr = timeout;
+	} else if (*arg)
+		goto bad_arg;
+	else if (timeoutptr)
+		*timeoutptr = 0;
+
+	/* Lookup wake lock in rbtree */
+	while (*p) {
+		parent = *p;
+		l = rb_entry(parent, struct user_wake_lock, node);
+		diff = strncmp(buf, l->name, name_len);
+		if (!diff && l->name[name_len])
+			diff = -1;
+		if (debug_mask & DEBUG_ERROR)
+			pr_info("lookup_wake_lock_name: compare %.*s %s %d\n",
+				name_len, buf, l->name, diff);
+
+		if (diff < 0)
+			p = &(*p)->rb_left;
+		else if (diff > 0)
+			p = &(*p)->rb_right;
+		else
+			return l;
+	}
+
+	/* Allocate and add new wakelock to rbtree */
+	if (!allocate) {
+		if (debug_mask & DEBUG_ERROR)
+			pr_info("lookup_wake_lock_name: %.*s not found\n",
+				name_len, buf);
+		return ERR_PTR(-EINVAL);
+	}
+	l = kzalloc(sizeof(*l) + name_len + 1, GFP_KERNEL);
+	if (l == NULL) {
+		if (debug_mask & DEBUG_FAILURE)
+			pr_err("lookup_wake_lock_name: failed to allocate "
+				"memory for %.*s\n", name_len, buf);
+		return ERR_PTR(-ENOMEM);
+	}
+	memcpy(l->name, buf, name_len);
+	if (debug_mask & DEBUG_NEW)
+		pr_info("lookup_wake_lock_name: new wake lock %s\n", l->name);
+	wake_lock_init(&l->wake_lock, WAKE_LOCK_SUSPEND, l->name);
+	rb_link_node(&l->node, parent, p);
+	rb_insert_color(&l->node, &user_wake_locks);
+	return l;
+
+bad_arg:
+	if (debug_mask & DEBUG_ERROR)
+		pr_info("lookup_wake_lock_name: wake lock, %.*s, bad arg, %s\n",
+			name_len, buf, arg);
+	return ERR_PTR(-EINVAL);
+}
+
+ssize_t wake_lock_show(
+	struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+	char *s = buf;
+	char *end = buf + PAGE_SIZE;
+	struct rb_node *n;
+	struct user_wake_lock *l;
+
+	mutex_lock(&tree_lock);
+
+	for (n = rb_first(&user_wake_locks); n != NULL; n = rb_next(n)) {
+		l = rb_entry(n, struct user_wake_lock, node);
+		if (wake_lock_active(&l->wake_lock))
+			s += scnprintf(s, end - s, "%s ", l->name);
+	}
+	s += scnprintf(s, end - s, "\n");
+
+	mutex_unlock(&tree_lock);
+	return (s - buf);
+}
+
+ssize_t wake_lock_store(
+	struct kobject *kobj, struct kobj_attribute *attr,
+	const char *buf, size_t n)
+{
+	long timeout;
+	struct user_wake_lock *l;
+
+	mutex_lock(&tree_lock);
+	l = lookup_wake_lock_name(buf, 1, &timeout);
+	if (IS_ERR(l)) {
+		n = PTR_ERR(l);
+		goto bad_name;
+	}
+
+	if (debug_mask & DEBUG_ACCESS)
+		pr_info("wake_lock_store: %s, timeout %ld\n", l->name, timeout);
+
+	if (timeout)
+		wake_lock_timeout(&l->wake_lock, timeout);
+	else
+		wake_lock(&l->wake_lock);
+bad_name:
+	mutex_unlock(&tree_lock);
+	return n;
+}
+
+
+ssize_t wake_unlock_show(
+	struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+	char *s = buf;
+	char *end = buf + PAGE_SIZE;
+	struct rb_node *n;
+	struct user_wake_lock *l;
+
+	mutex_lock(&tree_lock);
+
+	for (n = rb_first(&user_wake_locks); n != NULL; n = rb_next(n)) {
+		l = rb_entry(n, struct user_wake_lock, node);
+		if (!wake_lock_active(&l->wake_lock))
+			s += scnprintf(s, end - s, "%s ", l->name);
+	}
+	s += scnprintf(s, end - s, "\n");
+
+	mutex_unlock(&tree_lock);
+	return (s - buf);
+}
+
+ssize_t wake_unlock_store(
+	struct kobject *kobj, struct kobj_attribute *attr,
+	const char *buf, size_t n)
+{
+	struct user_wake_lock *l;
+
+	mutex_lock(&tree_lock);
+	l = lookup_wake_lock_name(buf, 0, NULL);
+	if (IS_ERR(l)) {
+		n = PTR_ERR(l);
+		goto not_found;
+	}
+
+	if (debug_mask & DEBUG_ACCESS)
+		pr_info("wake_unlock_store: %s\n", l->name);
+
+	wake_unlock(&l->wake_lock);
+not_found:
+	mutex_unlock(&tree_lock);
+	return n;
+}
+
diff --git a/kernel/power/wakelock.c b/kernel/power/wakelock.c
new file mode 100644
index 00000000000..ca48bb8d316
--- /dev/null
+++ b/kernel/power/wakelock.c
@@ -0,0 +1,607 @@
+/* kernel/power/wakelock.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h> /* sys_sync */
+#include <linux/wakelock.h>
+#ifdef CONFIG_WAKELOCK_STAT
+#include <linux/proc_fs.h>
+#endif
+#include "power.h"
+
+enum {
+	DEBUG_EXIT_SUSPEND = 1U << 0,
+	DEBUG_WAKEUP = 1U << 1,
+	DEBUG_SUSPEND = 1U << 2,
+	DEBUG_EXPIRE = 1U << 3,
+	DEBUG_WAKE_LOCK = 1U << 4,
+};
+static int debug_mask = DEBUG_EXIT_SUSPEND | DEBUG_WAKEUP;
+module_param_named(debug_mask, debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+#define WAKE_LOCK_TYPE_MASK              (0x0f)
+#define WAKE_LOCK_INITIALIZED            (1U << 8)
+#define WAKE_LOCK_ACTIVE                 (1U << 9)
+#define WAKE_LOCK_AUTO_EXPIRE            (1U << 10)
+#define WAKE_LOCK_PREVENTING_SUSPEND     (1U << 11)
+
+static DEFINE_SPINLOCK(list_lock);
+static LIST_HEAD(inactive_locks);
+static struct list_head active_wake_locks[WAKE_LOCK_TYPE_COUNT];
+static int current_event_num;
+struct workqueue_struct *suspend_work_queue;
+struct wake_lock main_wake_lock;
+suspend_state_t requested_suspend_state = PM_SUSPEND_MEM;
+static struct wake_lock unknown_wakeup;
+
+#ifdef CONFIG_WAKELOCK_STAT
+static struct wake_lock deleted_wake_locks;
+static ktime_t last_sleep_time_update;
+static int wait_for_wakeup;
+
+int get_expired_time(struct wake_lock *lock, ktime_t *expire_time)
+{
+	struct timespec ts;
+	struct timespec kt;
+	struct timespec tomono;
+	struct timespec delta;
+	unsigned long seq;
+	long timeout;
+
+	if (!(lock->flags & WAKE_LOCK_AUTO_EXPIRE))
+		return 0;
+	do {
+		seq = read_seqbegin(&xtime_lock);
+		timeout = lock->expires - jiffies;
+		if (timeout > 0)
+			return 0;
+		kt = current_kernel_time();
+		tomono = wall_to_monotonic;
+	} while (read_seqretry(&xtime_lock, seq));
+	jiffies_to_timespec(-timeout, &delta);
+	set_normalized_timespec(&ts, kt.tv_sec + tomono.tv_sec - delta.tv_sec,
+				kt.tv_nsec + tomono.tv_nsec - delta.tv_nsec);
+	*expire_time = timespec_to_ktime(ts);
+	return 1;
+}
+
+
+static int print_lock_stat(struct seq_file *m, struct wake_lock *lock)
+{
+	int lock_count = lock->stat.count;
+	int expire_count = lock->stat.expire_count;
+	ktime_t active_time = ktime_set(0, 0);
+	ktime_t total_time = lock->stat.total_time;
+	ktime_t max_time = lock->stat.max_time;
+
+	ktime_t prevent_suspend_time = lock->stat.prevent_suspend_time;
+	if (lock->flags & WAKE_LOCK_ACTIVE) {
+		ktime_t now, add_time;
+		int expired = get_expired_time(lock, &now);
+		if (!expired)
+			now = ktime_get();
+		add_time = ktime_sub(now, lock->stat.last_time);
+		lock_count++;
+		if (!expired)
+			active_time = add_time;
+		else
+			expire_count++;
+		total_time = ktime_add(total_time, add_time);
+		if (lock->flags & WAKE_LOCK_PREVENTING_SUSPEND)
+			prevent_suspend_time = ktime_add(prevent_suspend_time,
+					ktime_sub(now, last_sleep_time_update));
+		if (add_time.tv64 > max_time.tv64)
+			max_time = add_time;
+	}
+
+	return seq_printf(m,
+		     "\"%s\"\t%d\t%d\t%d\t%lld\t%lld\t%lld\t%lld\t%lld\n",
+		     lock->name, lock_count, expire_count,
+		     lock->stat.wakeup_count, ktime_to_ns(active_time),
+		     ktime_to_ns(total_time),
+		     ktime_to_ns(prevent_suspend_time), ktime_to_ns(max_time),
+		     ktime_to_ns(lock->stat.last_time));
+}
+
+static int wakelock_stats_show(struct seq_file *m, void *unused)
+{
+	unsigned long irqflags;
+	struct wake_lock *lock;
+	int ret;
+	int type;
+
+	spin_lock_irqsave(&list_lock, irqflags);
+
+	ret = seq_puts(m, "name\tcount\texpire_count\twake_count\tactive_since"
+			"\ttotal_time\tsleep_time\tmax_time\tlast_change\n");
+	list_for_each_entry(lock, &inactive_locks, link)
+		ret = print_lock_stat(m, lock);
+	for (type = 0; type < WAKE_LOCK_TYPE_COUNT; type++) {
+		list_for_each_entry(lock, &active_wake_locks[type], link)
+			ret = print_lock_stat(m, lock);
+	}
+	spin_unlock_irqrestore(&list_lock, irqflags);
+	return 0;
+}
+
+static void wake_unlock_stat_locked(struct wake_lock *lock, int expired)
+{
+	ktime_t duration;
+	ktime_t now;
+	if (!(lock->flags & WAKE_LOCK_ACTIVE))
+		return;
+	if (get_expired_time(lock, &now))
+		expired = 1;
+	else
+		now = ktime_get();
+	lock->stat.count++;
+	if (expired)
+		lock->stat.expire_count++;
+	duration = ktime_sub(now, lock->stat.last_time);
+	lock->stat.total_time = ktime_add(lock->stat.total_time, duration);
+	if (ktime_to_ns(duration) > ktime_to_ns(lock->stat.max_time))
+		lock->stat.max_time = duration;
+	lock->stat.last_time = ktime_get();
+	if (lock->flags & WAKE_LOCK_PREVENTING_SUSPEND) {
+		duration = ktime_sub(now, last_sleep_time_update);
+		lock->stat.prevent_suspend_time = ktime_add(
+			lock->stat.prevent_suspend_time, duration);
+		lock->flags &= ~WAKE_LOCK_PREVENTING_SUSPEND;
+	}
+}
+
+static void update_sleep_wait_stats_locked(int done)
+{
+	struct wake_lock *lock;
+	ktime_t now, etime, elapsed, add;
+	int expired;
+
+	now = ktime_get();
+	elapsed = ktime_sub(now, last_sleep_time_update);
+	list_for_each_entry(lock, &active_wake_locks[WAKE_LOCK_SUSPEND], link) {
+		expired = get_expired_time(lock, &etime);
+		if (lock->flags & WAKE_LOCK_PREVENTING_SUSPEND) {
+			if (expired)
+				add = ktime_sub(etime, last_sleep_time_update);
+			else
+				add = elapsed;
+			lock->stat.prevent_suspend_time = ktime_add(
+				lock->stat.prevent_suspend_time, add);
+		}
+		if (done || expired)
+			lock->flags &= ~WAKE_LOCK_PREVENTING_SUSPEND;
+		else
+			lock->flags |= WAKE_LOCK_PREVENTING_SUSPEND;
+	}
+	last_sleep_time_update = now;
+}
+#endif
+
+
+static void expire_wake_lock(struct wake_lock *lock)
+{
+#ifdef CONFIG_WAKELOCK_STAT
+	wake_unlock_stat_locked(lock, 1);
+#endif
+	lock->flags &= ~(WAKE_LOCK_ACTIVE | WAKE_LOCK_AUTO_EXPIRE);
+	list_del(&lock->link);
+	list_add(&lock->link, &inactive_locks);
+	if (debug_mask & (DEBUG_WAKE_LOCK | DEBUG_EXPIRE))
+		pr_info("expired wake lock %s\n", lock->name);
+}
+
+/* Caller must acquire the list_lock spinlock */
+static void print_active_locks(int type)
+{
+	struct wake_lock *lock;
+	bool print_expired = true;
+
+	BUG_ON(type >= WAKE_LOCK_TYPE_COUNT);
+	list_for_each_entry(lock, &active_wake_locks[type], link) {
+		if (lock->flags & WAKE_LOCK_AUTO_EXPIRE) {
+			long timeout = lock->expires - jiffies;
+			if (timeout > 0)
+				pr_info("active wake lock %s, time left %ld\n",
+					lock->name, timeout);
+			else if (print_expired)
+				pr_info("wake lock %s, expired\n", lock->name);
+		} else {
+			pr_info("active wake lock %s\n", lock->name);
+			if (!debug_mask & DEBUG_EXPIRE)
+				print_expired = false;
+		}
+	}
+}
+
+static long has_wake_lock_locked(int type)
+{
+	struct wake_lock *lock, *n;
+	long max_timeout = 0;
+
+	BUG_ON(type >= WAKE_LOCK_TYPE_COUNT);
+	list_for_each_entry_safe(lock, n, &active_wake_locks[type], link) {
+		if (lock->flags & WAKE_LOCK_AUTO_EXPIRE) {
+			long timeout = lock->expires - jiffies;
+			if (timeout <= 0)
+				expire_wake_lock(lock);
+			else if (timeout > max_timeout)
+				max_timeout = timeout;
+		} else
+			return -1;
+	}
+	return max_timeout;
+}
+
+long has_wake_lock(int type)
+{
+	long ret;
+	unsigned long irqflags;
+	spin_lock_irqsave(&list_lock, irqflags);
+	ret = has_wake_lock_locked(type);
+	if (ret && (debug_mask & DEBUG_SUSPEND) && type == WAKE_LOCK_SUSPEND)
+		print_active_locks(type);
+	spin_unlock_irqrestore(&list_lock, irqflags);
+	return ret;
+}
+
+static void suspend(struct work_struct *work)
+{
+	int ret;
+	int entry_event_num;
+
+	if (has_wake_lock(WAKE_LOCK_SUSPEND)) {
+		if (debug_mask & DEBUG_SUSPEND)
+			pr_info("suspend: abort suspend\n");
+		return;
+	}
+
+	entry_event_num = current_event_num;
+	sys_sync();
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("suspend: enter suspend\n");
+	ret = pm_suspend(requested_suspend_state);
+	if (debug_mask & DEBUG_EXIT_SUSPEND) {
+		struct timespec ts;
+		struct rtc_time tm;
+		getnstimeofday(&ts);
+		rtc_time_to_tm(ts.tv_sec, &tm);
+		pr_info("suspend: exit suspend, ret = %d "
+			"(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n", ret,
+			tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+			tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
+	}
+	if (current_event_num == entry_event_num) {
+		if (debug_mask & DEBUG_SUSPEND)
+			pr_info("suspend: pm_suspend returned with no event\n");
+		wake_lock_timeout(&unknown_wakeup, HZ / 2);
+	}
+}
+static DECLARE_WORK(suspend_work, suspend);
+
+static void expire_wake_locks(unsigned long data)
+{
+	long has_lock;
+	unsigned long irqflags;
+	if (debug_mask & DEBUG_EXPIRE)
+		pr_info("expire_wake_locks: start\n");
+	spin_lock_irqsave(&list_lock, irqflags);
+	if (debug_mask & DEBUG_SUSPEND)
+		print_active_locks(WAKE_LOCK_SUSPEND);
+	has_lock = has_wake_lock_locked(WAKE_LOCK_SUSPEND);
+	if (debug_mask & DEBUG_EXPIRE)
+		pr_info("expire_wake_locks: done, has_lock %ld\n", has_lock);
+	if (has_lock == 0)
+		queue_work(suspend_work_queue, &suspend_work);
+	spin_unlock_irqrestore(&list_lock, irqflags);
+}
+static DEFINE_TIMER(expire_timer, expire_wake_locks, 0, 0);
+
+static int power_suspend_late(struct device *dev)
+{
+	int ret = has_wake_lock(WAKE_LOCK_SUSPEND) ? -EAGAIN : 0;
+#ifdef CONFIG_WAKELOCK_STAT
+	wait_for_wakeup = 1;
+#endif
+	if (debug_mask & DEBUG_SUSPEND)
+		pr_info("power_suspend_late return %d\n", ret);
+	return ret;
+}
+
+static struct dev_pm_ops power_driver_pm_ops = {
+	.suspend_noirq = power_suspend_late,
+};
+
+static struct platform_driver power_driver = {
+	.driver.name = "power",
+	.driver.pm = &power_driver_pm_ops,
+};
+static struct platform_device power_device = {
+	.name = "power",
+};
+
+void wake_lock_init(struct wake_lock *lock, int type, const char *name)
+{
+	unsigned long irqflags = 0;
+
+	if (name)
+		lock->name = name;
+	BUG_ON(!lock->name);
+
+	if (debug_mask & DEBUG_WAKE_LOCK)
+		pr_info("wake_lock_init name=%s\n", lock->name);
+#ifdef CONFIG_WAKELOCK_STAT
+	lock->stat.count = 0;
+	lock->stat.expire_count = 0;
+	lock->stat.wakeup_count = 0;
+	lock->stat.total_time = ktime_set(0, 0);
+	lock->stat.prevent_suspend_time = ktime_set(0, 0);
+	lock->stat.max_time = ktime_set(0, 0);
+	lock->stat.last_time = ktime_set(0, 0);
+#endif
+	lock->flags = (type & WAKE_LOCK_TYPE_MASK) | WAKE_LOCK_INITIALIZED;
+
+	INIT_LIST_HEAD(&lock->link);
+	spin_lock_irqsave(&list_lock, irqflags);
+	list_add(&lock->link, &inactive_locks);
+	spin_unlock_irqrestore(&list_lock, irqflags);
+}
+EXPORT_SYMBOL(wake_lock_init);
+
+void wake_lock_destroy(struct wake_lock *lock)
+{
+	unsigned long irqflags;
+	if (debug_mask & DEBUG_WAKE_LOCK)
+		pr_info("wake_lock_destroy name=%s\n", lock->name);
+	spin_lock_irqsave(&list_lock, irqflags);
+	lock->flags &= ~WAKE_LOCK_INITIALIZED;
+#ifdef CONFIG_WAKELOCK_STAT
+	if (lock->stat.count) {
+		deleted_wake_locks.stat.count += lock->stat.count;
+		deleted_wake_locks.stat.expire_count += lock->stat.expire_count;
+		deleted_wake_locks.stat.total_time =
+			ktime_add(deleted_wake_locks.stat.total_time,
+				  lock->stat.total_time);
+		deleted_wake_locks.stat.prevent_suspend_time =
+			ktime_add(deleted_wake_locks.stat.prevent_suspend_time,
+				  lock->stat.prevent_suspend_time);
+		deleted_wake_locks.stat.max_time =
+			ktime_add(deleted_wake_locks.stat.max_time,
+				  lock->stat.max_time);
+	}
+#endif
+	list_del(&lock->link);
+	spin_unlock_irqrestore(&list_lock, irqflags);
+}
+EXPORT_SYMBOL(wake_lock_destroy);
+
+static void wake_lock_internal(
+	struct wake_lock *lock, long timeout, int has_timeout)
+{
+	int type;
+	unsigned long irqflags;
+	long expire_in;
+
+	spin_lock_irqsave(&list_lock, irqflags);
+	type = lock->flags & WAKE_LOCK_TYPE_MASK;
+	BUG_ON(type >= WAKE_LOCK_TYPE_COUNT);
+	BUG_ON(!(lock->flags & WAKE_LOCK_INITIALIZED));
+#ifdef CONFIG_WAKELOCK_STAT
+	if (type == WAKE_LOCK_SUSPEND && wait_for_wakeup) {
+		if (debug_mask & DEBUG_WAKEUP)
+			pr_info("wakeup wake lock: %s\n", lock->name);
+		wait_for_wakeup = 0;
+		lock->stat.wakeup_count++;
+	}
+	if ((lock->flags & WAKE_LOCK_AUTO_EXPIRE) &&
+	    (long)(lock->expires - jiffies) <= 0) {
+		wake_unlock_stat_locked(lock, 0);
+		lock->stat.last_time = ktime_get();
+	}
+#endif
+	if (!(lock->flags & WAKE_LOCK_ACTIVE)) {
+		lock->flags |= WAKE_LOCK_ACTIVE;
+#ifdef CONFIG_WAKELOCK_STAT
+		lock->stat.last_time = ktime_get();
+#endif
+	}
+	list_del(&lock->link);
+	if (has_timeout) {
+		if (debug_mask & DEBUG_WAKE_LOCK)
+			pr_info("wake_lock: %s, type %d, timeout %ld.%03lu\n",
+				lock->name, type, timeout / HZ,
+				(timeout % HZ) * MSEC_PER_SEC / HZ);
+		lock->expires = jiffies + timeout;
+		lock->flags |= WAKE_LOCK_AUTO_EXPIRE;
+		list_add_tail(&lock->link, &active_wake_locks[type]);
+	} else {
+		if (debug_mask & DEBUG_WAKE_LOCK)
+			pr_info("wake_lock: %s, type %d\n", lock->name, type);
+		lock->expires = LONG_MAX;
+		lock->flags &= ~WAKE_LOCK_AUTO_EXPIRE;
+		list_add(&lock->link, &active_wake_locks[type]);
+	}
+	if (type == WAKE_LOCK_SUSPEND) {
+		current_event_num++;
+#ifdef CONFIG_WAKELOCK_STAT
+		if (lock == &main_wake_lock)
+			update_sleep_wait_stats_locked(1);
+		else if (!wake_lock_active(&main_wake_lock))
+			update_sleep_wait_stats_locked(0);
+#endif
+		if (has_timeout)
+			expire_in = has_wake_lock_locked(type);
+		else
+			expire_in = -1;
+		if (expire_in > 0) {
+			if (debug_mask & DEBUG_EXPIRE)
+				pr_info("wake_lock: %s, start expire timer, "
+					"%ld\n", lock->name, expire_in);
+			mod_timer(&expire_timer, jiffies + expire_in);
+		} else {
+			if (del_timer(&expire_timer))
+				if (debug_mask & DEBUG_EXPIRE)
+					pr_info("wake_lock: %s, stop expire timer\n",
+						lock->name);
+			if (expire_in == 0)
+				queue_work(suspend_work_queue, &suspend_work);
+		}
+	}
+	spin_unlock_irqrestore(&list_lock, irqflags);
+}
+
+void wake_lock(struct wake_lock *lock)
+{
+	wake_lock_internal(lock, 0, 0);
+}
+EXPORT_SYMBOL(wake_lock);
+
+void wake_lock_timeout(struct wake_lock *lock, long timeout)
+{
+	wake_lock_internal(lock, timeout, 1);
+}
+EXPORT_SYMBOL(wake_lock_timeout);
+
+void wake_unlock(struct wake_lock *lock)
+{
+	int type;
+	unsigned long irqflags;
+	spin_lock_irqsave(&list_lock, irqflags);
+	type = lock->flags & WAKE_LOCK_TYPE_MASK;
+#ifdef CONFIG_WAKELOCK_STAT
+	wake_unlock_stat_locked(lock, 0);
+#endif
+	if (debug_mask & DEBUG_WAKE_LOCK)
+		pr_info("wake_unlock: %s\n", lock->name);
+	lock->flags &= ~(WAKE_LOCK_ACTIVE | WAKE_LOCK_AUTO_EXPIRE);
+	list_del(&lock->link);
+	list_add(&lock->link, &inactive_locks);
+	if (type == WAKE_LOCK_SUSPEND) {
+		long has_lock = has_wake_lock_locked(type);
+		if (has_lock > 0) {
+			if (debug_mask & DEBUG_EXPIRE)
+				pr_info("wake_unlock: %s, start expire timer, "
+					"%ld\n", lock->name, has_lock);
+			mod_timer(&expire_timer, jiffies + has_lock);
+		} else {
+			if (del_timer(&expire_timer))
+				if (debug_mask & DEBUG_EXPIRE)
+					pr_info("wake_unlock: %s, stop expire "
+						"timer\n", lock->name);
+			if (has_lock == 0)
+				queue_work(suspend_work_queue, &suspend_work);
+		}
+		if (lock == &main_wake_lock) {
+			if (debug_mask & DEBUG_SUSPEND)
+				print_active_locks(WAKE_LOCK_SUSPEND);
+#ifdef CONFIG_WAKELOCK_STAT
+			update_sleep_wait_stats_locked(0);
+#endif
+		}
+	}
+	spin_unlock_irqrestore(&list_lock, irqflags);
+}
+EXPORT_SYMBOL(wake_unlock);
+
+int wake_lock_active(struct wake_lock *lock)
+{
+	return !!(lock->flags & WAKE_LOCK_ACTIVE);
+}
+EXPORT_SYMBOL(wake_lock_active);
+
+static int wakelock_stats_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, wakelock_stats_show, NULL);
+}
+
+static const struct file_operations wakelock_stats_fops = {
+	.owner = THIS_MODULE,
+	.open = wakelock_stats_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static int __init wakelocks_init(void)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(active_wake_locks); i++)
+		INIT_LIST_HEAD(&active_wake_locks[i]);
+
+#ifdef CONFIG_WAKELOCK_STAT
+	wake_lock_init(&deleted_wake_locks, WAKE_LOCK_SUSPEND,
+			"deleted_wake_locks");
+#endif
+	wake_lock_init(&main_wake_lock, WAKE_LOCK_SUSPEND, "main");
+	wake_lock(&main_wake_lock);
+	wake_lock_init(&unknown_wakeup, WAKE_LOCK_SUSPEND, "unknown_wakeups");
+
+	ret = platform_device_register(&power_device);
+	if (ret) {
+		pr_err("wakelocks_init: platform_device_register failed\n");
+		goto err_platform_device_register;
+	}
+	ret = platform_driver_register(&power_driver);
+	if (ret) {
+		pr_err("wakelocks_init: platform_driver_register failed\n");
+		goto err_platform_driver_register;
+	}
+
+	suspend_work_queue = create_singlethread_workqueue("suspend");
+	if (suspend_work_queue == NULL) {
+		ret = -ENOMEM;
+		goto err_suspend_work_queue;
+	}
+
+#ifdef CONFIG_WAKELOCK_STAT
+	proc_create("wakelocks", S_IRUGO, NULL, &wakelock_stats_fops);
+#endif
+
+	return 0;
+
+err_suspend_work_queue:
+	platform_driver_unregister(&power_driver);
+err_platform_driver_register:
+	platform_device_unregister(&power_device);
+err_platform_device_register:
+	wake_lock_destroy(&unknown_wakeup);
+	wake_lock_destroy(&main_wake_lock);
+#ifdef CONFIG_WAKELOCK_STAT
+	wake_lock_destroy(&deleted_wake_locks);
+#endif
+	return ret;
+}
+
+static void  __exit wakelocks_exit(void)
+{
+#ifdef CONFIG_WAKELOCK_STAT
+	remove_proc_entry("wakelocks", NULL);
+#endif
+	destroy_workqueue(suspend_work_queue);
+	platform_driver_unregister(&power_driver);
+	platform_device_unregister(&power_device);
+	wake_lock_destroy(&unknown_wakeup);
+	wake_lock_destroy(&main_wake_lock);
+#ifdef CONFIG_WAKELOCK_STAT
+	wake_lock_destroy(&deleted_wake_locks);
+#endif
+}
+
+core_initcall(wakelocks_init);
+module_exit(wakelocks_exit);
diff --git a/kernel/printk.c b/kernel/printk.c
index f38b07f78a4..82e721e291c 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -51,6 +51,7 @@ void asmlinkage __attribute__((weak)) early_printk(const char *fmt, ...)
 
 #define __LOG_BUF_LEN	(1 << CONFIG_LOG_BUF_SHIFT)
 
+
 /* printk's without a loglevel use this.. */
 #define DEFAULT_MESSAGE_LOGLEVEL 4 /* KERN_WARNING */
 
@@ -257,6 +258,53 @@ static inline void boot_delay_msec(void)
 #endif
 
 /*
+ * Return the number of unread characters in the log buffer.
+ */
+static int log_buf_get_len(void)
+{
+	return logged_chars;
+}
+
+/*
+ * Clears the ring-buffer
+ */
+void log_buf_clear(void)
+{
+	logged_chars = 0;
+}
+
+/*
+ * Copy a range of characters from the log buffer.
+ */
+int log_buf_copy(char *dest, int idx, int len)
+{
+	int ret, max;
+	bool took_lock = false;
+
+	if (!oops_in_progress) {
+		spin_lock_irq(&logbuf_lock);
+		took_lock = true;
+	}
+
+	max = log_buf_get_len();
+	if (idx < 0 || idx >= max) {
+		ret = -1;
+	} else {
+		if (len > max - idx)
+			len = max - idx;
+		ret = len;
+		idx += (log_end - max);
+		while (len-- > 0)
+			dest[len] = LOG_BUF(idx + len);
+	}
+
+	if (took_lock)
+		spin_unlock_irq(&logbuf_lock);
+
+	return ret;
+}
+
+/*
  * Commands to do_syslog:
  *
  * 	0 -- Close the log.  Currently a NOP.
diff --git a/kernel/sched.c b/kernel/sched.c
index 60d74cc721c..f297f4c2be5 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -6899,7 +6899,7 @@ void sched_show_task(struct task_struct *p)
 	unsigned state;
 
 	state = p->state ? __ffs(p->state) + 1 : 0;
-	printk(KERN_INFO "%-13.13s %c", p->comm,
+	printk(KERN_INFO "%-15.15s %c", p->comm,
 		state < sizeof(stat_nam) - 1 ? stat_nam[state] : '?');
 #if BITS_PER_LONG == 32
 	if (state == TASK_RUNNING)
@@ -9613,13 +9613,24 @@ static inline int preempt_count_equals(int preempt_offset)
 	return (nested == PREEMPT_INATOMIC_BASE + preempt_offset);
 }
 
+static int __might_sleep_init_called;
+int __init __might_sleep_init(void)
+{
+	__might_sleep_init_called = 1;
+	return 0;
+}
+early_initcall(__might_sleep_init);
+
 void __might_sleep(char *file, int line, int preempt_offset)
 {
 #ifdef in_atomic
 	static unsigned long prev_jiffy;	/* ratelimiting */
 
 	if ((preempt_count_equals(preempt_offset) && !irqs_disabled()) ||
-	    system_state != SYSTEM_RUNNING || oops_in_progress)
+	    oops_in_progress)
+		return;
+	if (system_state != SYSTEM_RUNNING &&
+	    (!__might_sleep_init_called || system_state != SYSTEM_BOOTING))
 		return;
 	if (time_before(jiffies, prev_jiffy + HZ) && prev_jiffy)
 		return;
@@ -10439,6 +10450,15 @@ cpu_cgroup_destroy(struct cgroup_subsys *ss, struct cgroup *cgrp)
 static int
 cpu_cgroup_can_attach_task(struct cgroup *cgrp, struct task_struct *tsk)
 {
+	if ((current != tsk) && (!capable(CAP_SYS_NICE))) {
+		const struct cred *cred = current_cred(), *tcred;
+
+		tcred = __task_cred(tsk);
+
+		if (cred->euid != tcred->uid && cred->euid != tcred->suid)
+			return -EPERM;
+	}
+
 #ifdef CONFIG_RT_GROUP_SCHED
 	if (!sched_rt_can_attach(cgroup_tg(cgrp), tsk))
 		return -EINVAL;
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index b8bd058c5cd..771ac48f165 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -79,6 +79,7 @@ extern char core_pattern[];
 extern unsigned int core_pipe_limit;
 extern int pid_max;
 extern int min_free_kbytes;
+extern int min_free_order_shift;
 extern int pid_max_min, pid_max_max;
 extern int sysctl_drop_caches;
 extern int percpu_pagelist_fraction;
@@ -1229,6 +1230,14 @@ static struct ctl_table vm_table[] = {
 		.extra1		= &zero,
 	},
 	{
+		.ctl_name	= CTL_UNNUMBERED,
+		.procname	= "min_free_order_shift",
+		.data		= &min_free_order_shift,
+		.maxlen		= sizeof(min_free_order_shift),
+		.mode		= 0644,
+		.proc_handler	= &proc_dointvec
+	},
+	{
 		.ctl_name	= VM_PERCPU_PAGELIST_FRACTION,
 		.procname	= "percpu_pagelist_fraction",
 		.data		= &percpu_pagelist_fraction,
diff --git a/mm/Makefile b/mm/Makefile
index ebf849042ed..66f548652fa 100644
--- a/mm/Makefile
+++ b/mm/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_HUGETLBFS)	+= hugetlb.o
 obj-$(CONFIG_NUMA) 	+= mempolicy.o
 obj-$(CONFIG_SPARSEMEM)	+= sparse.o
 obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
+obj-$(CONFIG_ASHMEM) += ashmem.o
 obj-$(CONFIG_TMPFS_POSIX_ACL) += shmem_acl.o
 obj-$(CONFIG_SLOB) += slob.o
 obj-$(CONFIG_MMU_NOTIFIER) += mmu_notifier.o
diff --git a/mm/ashmem.c b/mm/ashmem.c
new file mode 100644
index 00000000000..7b75f41a2d4
--- /dev/null
+++ b/mm/ashmem.c
@@ -0,0 +1,706 @@
+/* mm/ashmem.c
+**
+** Anonymous Shared Memory Subsystem, ashmem
+**
+** Copyright (C) 2008 Google, Inc.
+**
+** Robert Love <rlove@google.com>
+**
+** This software is licensed under the terms of the GNU General Public
+** License version 2, as published by the Free Software Foundation, and
+** may be copied, distributed, and modified under those terms.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+*/
+
+#include <linux/module.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/security.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/uaccess.h>
+#include <linux/personality.h>
+#include <linux/bitops.h>
+#include <linux/mutex.h>
+#include <linux/shmem_fs.h>
+#include <linux/ashmem.h>
+
+#define ASHMEM_NAME_PREFIX "dev/ashmem/"
+#define ASHMEM_NAME_PREFIX_LEN (sizeof(ASHMEM_NAME_PREFIX) - 1)
+#define ASHMEM_FULL_NAME_LEN (ASHMEM_NAME_LEN + ASHMEM_NAME_PREFIX_LEN)
+
+/*
+ * ashmem_area - anonymous shared memory area
+ * Lifecycle: From our parent file's open() until its release()
+ * Locking: Protected by `ashmem_mutex'
+ * Big Note: Mappings do NOT pin this structure; it dies on close()
+ */
+struct ashmem_area {
+	char name[ASHMEM_FULL_NAME_LEN];/* optional name for /proc/pid/maps */
+	struct list_head unpinned_list;	/* list of all ashmem areas */
+	struct file *file;		/* the shmem-based backing file */
+	size_t size;			/* size of the mapping, in bytes */
+	unsigned long prot_mask;	/* allowed prot bits, as vm_flags */
+};
+
+/*
+ * ashmem_range - represents an interval of unpinned (evictable) pages
+ * Lifecycle: From unpin to pin
+ * Locking: Protected by `ashmem_mutex'
+ */
+struct ashmem_range {
+	struct list_head lru;		/* entry in LRU list */
+	struct list_head unpinned;	/* entry in its area's unpinned list */
+	struct ashmem_area *asma;	/* associated area */
+	size_t pgstart;			/* starting page, inclusive */
+	size_t pgend;			/* ending page, inclusive */
+	unsigned int purged;		/* ASHMEM_NOT or ASHMEM_WAS_PURGED */
+};
+
+/* LRU list of unpinned pages, protected by ashmem_mutex */
+static LIST_HEAD(ashmem_lru_list);
+
+/* Count of pages on our LRU list, protected by ashmem_mutex */
+static unsigned long lru_count;
+
+/*
+ * ashmem_mutex - protects the list of and each individual ashmem_area
+ *
+ * Lock Ordering: ashmex_mutex -> i_mutex -> i_alloc_sem
+ */
+static DEFINE_MUTEX(ashmem_mutex);
+
+static struct kmem_cache *ashmem_area_cachep __read_mostly;
+static struct kmem_cache *ashmem_range_cachep __read_mostly;
+
+#define range_size(range) \
+  ((range)->pgend - (range)->pgstart + 1)
+
+#define range_on_lru(range) \
+  ((range)->purged == ASHMEM_NOT_PURGED)
+
+#define page_range_subsumes_range(range, start, end) \
+  (((range)->pgstart >= (start)) && ((range)->pgend <= (end)))
+
+#define page_range_subsumed_by_range(range, start, end) \
+  (((range)->pgstart <= (start)) && ((range)->pgend >= (end)))
+
+#define page_in_range(range, page) \
+ (((range)->pgstart <= (page)) && ((range)->pgend >= (page)))
+
+#define page_range_in_range(range, start, end) \
+  (page_in_range(range, start) || page_in_range(range, end) || \
+   page_range_subsumes_range(range, start, end))
+
+#define range_before_page(range, page) \
+  ((range)->pgend < (page))
+
+#define PROT_MASK		(PROT_EXEC | PROT_READ | PROT_WRITE)
+
+static inline void lru_add(struct ashmem_range *range)
+{
+	list_add_tail(&range->lru, &ashmem_lru_list);
+	lru_count += range_size(range);
+}
+
+static inline void lru_del(struct ashmem_range *range)
+{
+	list_del(&range->lru);
+	lru_count -= range_size(range);
+}
+
+/*
+ * range_alloc - allocate and initialize a new ashmem_range structure
+ *
+ * 'asma' - associated ashmem_area
+ * 'prev_range' - the previous ashmem_range in the sorted asma->unpinned list
+ * 'purged' - initial purge value (ASMEM_NOT_PURGED or ASHMEM_WAS_PURGED)
+ * 'start' - starting page, inclusive
+ * 'end' - ending page, inclusive
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int range_alloc(struct ashmem_area *asma,
+		       struct ashmem_range *prev_range, unsigned int purged,
+		       size_t start, size_t end)
+{
+	struct ashmem_range *range;
+
+	range = kmem_cache_zalloc(ashmem_range_cachep, GFP_KERNEL);
+	if (unlikely(!range))
+		return -ENOMEM;
+
+	range->asma = asma;
+	range->pgstart = start;
+	range->pgend = end;
+	range->purged = purged;
+
+	list_add_tail(&range->unpinned, &prev_range->unpinned);
+
+	if (range_on_lru(range))
+		lru_add(range);
+
+	return 0;
+}
+
+static void range_del(struct ashmem_range *range)
+{
+	list_del(&range->unpinned);
+	if (range_on_lru(range))
+		lru_del(range);
+	kmem_cache_free(ashmem_range_cachep, range);
+}
+
+/*
+ * range_shrink - shrinks a range
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static inline void range_shrink(struct ashmem_range *range,
+				size_t start, size_t end)
+{
+	size_t pre = range_size(range);
+
+	range->pgstart = start;
+	range->pgend = end;
+
+	if (range_on_lru(range))
+		lru_count -= pre - range_size(range);
+}
+
+static int ashmem_open(struct inode *inode, struct file *file)
+{
+	struct ashmem_area *asma;
+	int ret;
+
+	ret = nonseekable_open(inode, file);
+	if (unlikely(ret))
+		return ret;
+
+	asma = kmem_cache_zalloc(ashmem_area_cachep, GFP_KERNEL);
+	if (unlikely(!asma))
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&asma->unpinned_list);
+	memcpy(asma->name, ASHMEM_NAME_PREFIX, ASHMEM_NAME_PREFIX_LEN);
+	asma->prot_mask = PROT_MASK;
+	file->private_data = asma;
+
+	return 0;
+}
+
+static int ashmem_release(struct inode *ignored, struct file *file)
+{
+	struct ashmem_area *asma = file->private_data;
+	struct ashmem_range *range, *next;
+
+	mutex_lock(&ashmem_mutex);
+	list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned)
+		range_del(range);
+	mutex_unlock(&ashmem_mutex);
+
+	if (asma->file)
+		fput(asma->file);
+	kmem_cache_free(ashmem_area_cachep, asma);
+
+	return 0;
+}
+
+static ssize_t ashmem_read(struct file *file, char __user *buf,
+			   size_t len, loff_t *pos)
+{
+	struct ashmem_area *asma = file->private_data;
+	int ret = 0;
+
+	mutex_lock(&ashmem_mutex);
+
+	/* If size is not set, or set to 0, always return EOF. */
+	if (asma->size == 0) {
+		goto out;
+        }
+
+	if (!asma->file) {
+		ret = -EBADF;
+		goto out;
+	}
+
+	ret = asma->file->f_op->read(asma->file, buf, len, pos);
+
+out:
+	mutex_unlock(&ashmem_mutex);
+	return ret;
+}
+
+static inline unsigned long
+calc_vm_may_flags(unsigned long prot)
+{
+	return _calc_vm_trans(prot, PROT_READ,  VM_MAYREAD ) |
+	       _calc_vm_trans(prot, PROT_WRITE, VM_MAYWRITE) |
+	       _calc_vm_trans(prot, PROT_EXEC,  VM_MAYEXEC);
+}
+
+static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct ashmem_area *asma = file->private_data;
+	int ret = 0;
+
+	mutex_lock(&ashmem_mutex);
+
+	/* user needs to SET_SIZE before mapping */
+	if (unlikely(!asma->size)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* requested protection bits must match our allowed protection mask */
+	if (unlikely((vma->vm_flags & ~calc_vm_prot_bits(asma->prot_mask)) &
+						calc_vm_prot_bits(PROT_MASK))) {
+		ret = -EPERM;
+		goto out;
+	}
+	vma->vm_flags &= ~calc_vm_may_flags(~asma->prot_mask);
+
+	if (!asma->file) {
+		char *name = ASHMEM_NAME_DEF;
+		struct file *vmfile;
+
+		if (asma->name[ASHMEM_NAME_PREFIX_LEN] != '\0')
+			name = asma->name;
+
+		/* ... and allocate the backing shmem file */
+		vmfile = shmem_file_setup(name, asma->size, vma->vm_flags);
+		if (unlikely(IS_ERR(vmfile))) {
+			ret = PTR_ERR(vmfile);
+			goto out;
+		}
+		asma->file = vmfile;
+	}
+	get_file(asma->file);
+
+	if (vma->vm_flags & VM_SHARED)
+		shmem_set_file(vma, asma->file);
+	else {
+		if (vma->vm_file)
+			fput(vma->vm_file);
+		vma->vm_file = asma->file;
+	}
+	vma->vm_flags |= VM_CAN_NONLINEAR;
+
+out:
+	mutex_unlock(&ashmem_mutex);
+	return ret;
+}
+
+/*
+ * ashmem_shrink - our cache shrinker, called from mm/vmscan.c :: shrink_slab
+ *
+ * 'nr_to_scan' is the number of objects (pages) to prune, or 0 to query how
+ * many objects (pages) we have in total.
+ *
+ * 'gfp_mask' is the mask of the allocation that got us into this mess.
+ *
+ * Return value is the number of objects (pages) remaining, or -1 if we cannot
+ * proceed without risk of deadlock (due to gfp_mask).
+ *
+ * We approximate LRU via least-recently-unpinned, jettisoning unpinned partial
+ * chunks of ashmem regions LRU-wise one-at-a-time until we hit 'nr_to_scan'
+ * pages freed.
+ */
+static int ashmem_shrink(int nr_to_scan, gfp_t gfp_mask)
+{
+	struct ashmem_range *range, *next;
+
+	/* We might recurse into filesystem code, so bail out if necessary */
+	if (nr_to_scan && !(gfp_mask & __GFP_FS))
+		return -1;
+	if (!nr_to_scan)
+		return lru_count;
+
+	mutex_lock(&ashmem_mutex);
+	list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) {
+		struct inode *inode = range->asma->file->f_dentry->d_inode;
+		loff_t start = range->pgstart * PAGE_SIZE;
+		loff_t end = (range->pgend + 1) * PAGE_SIZE - 1;
+
+		vmtruncate_range(inode, start, end);
+		range->purged = ASHMEM_WAS_PURGED;
+		lru_del(range);
+
+		nr_to_scan -= range_size(range);
+		if (nr_to_scan <= 0)
+			break;
+	}
+	mutex_unlock(&ashmem_mutex);
+
+	return lru_count;
+}
+
+static struct shrinker ashmem_shrinker = {
+	.shrink = ashmem_shrink,
+	.seeks = DEFAULT_SEEKS * 4,
+};
+
+static int set_prot_mask(struct ashmem_area *asma, unsigned long prot)
+{
+	int ret = 0;
+
+	mutex_lock(&ashmem_mutex);
+
+	/* the user can only remove, not add, protection bits */
+	if (unlikely((asma->prot_mask & prot) != prot)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* does the application expect PROT_READ to imply PROT_EXEC? */
+	if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC))
+		prot |= PROT_EXEC;
+
+	asma->prot_mask = prot;
+
+out:
+	mutex_unlock(&ashmem_mutex);
+	return ret;
+}
+
+static int set_name(struct ashmem_area *asma, void __user *name)
+{
+	int ret = 0;
+
+	mutex_lock(&ashmem_mutex);
+
+	/* cannot change an existing mapping's name */
+	if (unlikely(asma->file)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (unlikely(copy_from_user(asma->name + ASHMEM_NAME_PREFIX_LEN,
+				    name, ASHMEM_NAME_LEN)))
+		ret = -EFAULT;
+	asma->name[ASHMEM_FULL_NAME_LEN-1] = '\0';
+
+out:
+	mutex_unlock(&ashmem_mutex);
+
+	return ret;
+}
+
+static int get_name(struct ashmem_area *asma, void __user *name)
+{
+	int ret = 0;
+
+	mutex_lock(&ashmem_mutex);
+	if (asma->name[ASHMEM_NAME_PREFIX_LEN] != '\0') {
+		size_t len;
+
+		/*
+		 * Copying only `len', instead of ASHMEM_NAME_LEN, bytes
+		 * prevents us from revealing one user's stack to another.
+		 */
+		len = strlen(asma->name + ASHMEM_NAME_PREFIX_LEN) + 1;
+		if (unlikely(copy_to_user(name,
+				asma->name + ASHMEM_NAME_PREFIX_LEN, len)))
+			ret = -EFAULT;
+	} else {
+		if (unlikely(copy_to_user(name, ASHMEM_NAME_DEF,
+					  sizeof(ASHMEM_NAME_DEF))))
+			ret = -EFAULT;
+	}
+	mutex_unlock(&ashmem_mutex);
+
+	return ret;
+}
+
+/*
+ * ashmem_pin - pin the given ashmem region, returning whether it was
+ * previously purged (ASHMEM_WAS_PURGED) or not (ASHMEM_NOT_PURGED).
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_pin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
+{
+	struct ashmem_range *range, *next;
+	int ret = ASHMEM_NOT_PURGED;
+
+	list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
+		/* moved past last applicable page; we can short circuit */
+		if (range_before_page(range, pgstart))
+			break;
+
+		/*
+		 * The user can ask us to pin pages that span multiple ranges,
+		 * or to pin pages that aren't even unpinned, so this is messy.
+		 *
+		 * Four cases:
+		 * 1. The requested range subsumes an existing range, so we
+		 *    just remove the entire matching range.
+		 * 2. The requested range overlaps the start of an existing
+		 *    range, so we just update that range.
+		 * 3. The requested range overlaps the end of an existing
+		 *    range, so we just update that range.
+		 * 4. The requested range punches a hole in an existing range,
+		 *    so we have to update one side of the range and then
+		 *    create a new range for the other side.
+		 */
+		if (page_range_in_range(range, pgstart, pgend)) {
+			ret |= range->purged;
+
+			/* Case #1: Easy. Just nuke the whole thing. */
+			if (page_range_subsumes_range(range, pgstart, pgend)) {
+				range_del(range);
+				continue;
+			}
+
+			/* Case #2: We overlap from the start, so adjust it */
+			if (range->pgstart >= pgstart) {
+				range_shrink(range, pgend + 1, range->pgend);
+				continue;
+			}
+
+			/* Case #3: We overlap from the rear, so adjust it */
+			if (range->pgend <= pgend) {
+				range_shrink(range, range->pgstart, pgstart-1);
+				continue;
+			}
+
+			/*
+			 * Case #4: We eat a chunk out of the middle. A bit
+			 * more complicated, we allocate a new range for the
+			 * second half and adjust the first chunk's endpoint.
+			 */
+			range_alloc(asma, range, range->purged,
+				    pgend + 1, range->pgend);
+			range_shrink(range, range->pgstart, pgstart - 1);
+			break;
+		}
+	}
+
+	return ret;
+}
+
+/*
+ * ashmem_unpin - unpin the given range of pages. Returns zero on success.
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_unpin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
+{
+	struct ashmem_range *range, *next;
+	unsigned int purged = ASHMEM_NOT_PURGED;
+
+restart:
+	list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
+		/* short circuit: this is our insertion point */
+		if (range_before_page(range, pgstart))
+			break;
+
+		/*
+		 * The user can ask us to unpin pages that are already entirely
+		 * or partially pinned. We handle those two cases here.
+		 */
+		if (page_range_subsumed_by_range(range, pgstart, pgend))
+			return 0;
+		if (page_range_in_range(range, pgstart, pgend)) {
+			pgstart = min_t(size_t, range->pgstart, pgstart),
+			pgend = max_t(size_t, range->pgend, pgend);
+			purged |= range->purged;
+			range_del(range);
+			goto restart;
+		}
+	}
+
+	return range_alloc(asma, range, purged, pgstart, pgend);
+}
+
+/*
+ * ashmem_get_pin_status - Returns ASHMEM_IS_UNPINNED if _any_ pages in the
+ * given interval are unpinned and ASHMEM_IS_PINNED otherwise.
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_get_pin_status(struct ashmem_area *asma, size_t pgstart,
+				 size_t pgend)
+{
+	struct ashmem_range *range;
+	int ret = ASHMEM_IS_PINNED;
+
+	list_for_each_entry(range, &asma->unpinned_list, unpinned) {
+		if (range_before_page(range, pgstart))
+			break;
+		if (page_range_in_range(range, pgstart, pgend)) {
+			ret = ASHMEM_IS_UNPINNED;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
+			    void __user *p)
+{
+	struct ashmem_pin pin;
+	size_t pgstart, pgend;
+	int ret = -EINVAL;
+
+	if (unlikely(!asma->file))
+		return -EINVAL;
+
+	if (unlikely(copy_from_user(&pin, p, sizeof(pin))))
+		return -EFAULT;
+
+	/* per custom, you can pass zero for len to mean "everything onward" */
+	if (!pin.len)
+		pin.len = PAGE_ALIGN(asma->size) - pin.offset;
+
+	if (unlikely((pin.offset | pin.len) & ~PAGE_MASK))
+		return -EINVAL;
+
+	if (unlikely(((__u32) -1) - pin.offset < pin.len))
+		return -EINVAL;
+
+	if (unlikely(PAGE_ALIGN(asma->size) < pin.offset + pin.len))
+		return -EINVAL;
+
+	pgstart = pin.offset / PAGE_SIZE;
+	pgend = pgstart + (pin.len / PAGE_SIZE) - 1;
+
+	mutex_lock(&ashmem_mutex);
+
+	switch (cmd) {
+	case ASHMEM_PIN:
+		ret = ashmem_pin(asma, pgstart, pgend);
+		break;
+	case ASHMEM_UNPIN:
+		ret = ashmem_unpin(asma, pgstart, pgend);
+		break;
+	case ASHMEM_GET_PIN_STATUS:
+		ret = ashmem_get_pin_status(asma, pgstart, pgend);
+		break;
+	}
+
+	mutex_unlock(&ashmem_mutex);
+
+	return ret;
+}
+
+static long ashmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct ashmem_area *asma = file->private_data;
+	long ret = -ENOTTY;
+
+	switch (cmd) {
+	case ASHMEM_SET_NAME:
+		ret = set_name(asma, (void __user *) arg);
+		break;
+	case ASHMEM_GET_NAME:
+		ret = get_name(asma, (void __user *) arg);
+		break;
+	case ASHMEM_SET_SIZE:
+		ret = -EINVAL;
+		if (!asma->file) {
+			ret = 0;
+			asma->size = (size_t) arg;
+		}
+		break;
+	case ASHMEM_GET_SIZE:
+		ret = asma->size;
+		break;
+	case ASHMEM_SET_PROT_MASK:
+		ret = set_prot_mask(asma, arg);
+		break;
+	case ASHMEM_GET_PROT_MASK:
+		ret = asma->prot_mask;
+		break;
+	case ASHMEM_PIN:
+	case ASHMEM_UNPIN:
+	case ASHMEM_GET_PIN_STATUS:
+		ret = ashmem_pin_unpin(asma, cmd, (void __user *) arg);
+		break;
+	case ASHMEM_PURGE_ALL_CACHES:
+		ret = -EPERM;
+		if (capable(CAP_SYS_ADMIN)) {
+			ret = ashmem_shrink(0, GFP_KERNEL);
+			ashmem_shrink(ret, GFP_KERNEL);
+		}
+		break;
+	}
+
+	return ret;
+}
+
+static struct file_operations ashmem_fops = {
+	.owner = THIS_MODULE,
+	.open = ashmem_open,
+	.release = ashmem_release,
+        .read = ashmem_read,
+	.mmap = ashmem_mmap,
+	.unlocked_ioctl = ashmem_ioctl,
+	.compat_ioctl = ashmem_ioctl,
+};
+
+static struct miscdevice ashmem_misc = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "ashmem",
+	.fops = &ashmem_fops,
+};
+
+static int __init ashmem_init(void)
+{
+	int ret;
+
+	ashmem_area_cachep = kmem_cache_create("ashmem_area_cache",
+					  sizeof(struct ashmem_area),
+					  0, 0, NULL);
+	if (unlikely(!ashmem_area_cachep)) {
+		printk(KERN_ERR "ashmem: failed to create slab cache\n");
+		return -ENOMEM;
+	}
+
+	ashmem_range_cachep = kmem_cache_create("ashmem_range_cache",
+					  sizeof(struct ashmem_range),
+					  0, 0, NULL);
+	if (unlikely(!ashmem_range_cachep)) {
+		printk(KERN_ERR "ashmem: failed to create slab cache\n");
+		return -ENOMEM;
+	}
+
+	ret = misc_register(&ashmem_misc);
+	if (unlikely(ret)) {
+		printk(KERN_ERR "ashmem: failed to register misc device!\n");
+		return ret;
+	}
+
+	register_shrinker(&ashmem_shrinker);
+
+	printk(KERN_INFO "ashmem: initialized\n");
+
+	return 0;
+}
+
+static void __exit ashmem_exit(void)
+{
+	int ret;
+
+	unregister_shrinker(&ashmem_shrinker);
+
+	ret = misc_deregister(&ashmem_misc);
+	if (unlikely(ret))
+		printk(KERN_ERR "ashmem: failed to unregister misc device!\n");
+
+	kmem_cache_destroy(ashmem_range_cachep);
+	kmem_cache_destroy(ashmem_area_cachep);
+
+	printk(KERN_INFO "ashmem: unloaded\n");
+}
+
+module_init(ashmem_init);
+module_exit(ashmem_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 36992b68500..7d4406f07d9 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -122,6 +122,7 @@ static char * const zone_names[MAX_NR_ZONES] = {
 };
 
 int min_free_kbytes = 1024;
+int min_free_order_shift = 1;
 
 static unsigned long __meminitdata nr_kernel_pages;
 static unsigned long __meminitdata nr_all_pages;
@@ -1380,7 +1381,7 @@ int zone_watermark_ok(struct zone *z, int order, unsigned long mark,
 		free_pages -= z->free_area[o].nr_free << o;
 
 		/* Require fewer higher order pages to be free */
-		min >>= 1;
+		min >>= min_free_order_shift;
 
 		if (free_pages <= min)
 			return 0;
@@ -2859,6 +2860,20 @@ static inline unsigned long wait_table_bits(unsigned long size)
 #define LONG_ALIGN(x) (((x)+(sizeof(long))-1)&~((sizeof(long))-1))
 
 /*
+ * Check if a pageblock contains reserved pages
+ */
+static int pageblock_is_reserved(unsigned long start_pfn)
+{
+	unsigned long end_pfn = start_pfn + pageblock_nr_pages;
+	unsigned long pfn;
+
+	for (pfn = start_pfn; pfn < end_pfn; pfn++)
+		if (PageReserved(pfn_to_page(pfn)))
+			return 1;
+	return 0;
+}
+
+/*
  * Mark a number of pageblocks as MIGRATE_RESERVE. The number
  * of blocks reserved is based on min_wmark_pages(zone). The memory within
  * the reserve will tend to store contiguous free pages. Setting min_free_kbytes
@@ -2897,7 +2912,7 @@ static void setup_zone_migrate_reserve(struct zone *zone)
 			continue;
 
 		/* Blocks with reserved pages will never free, skip them. */
-		if (PageReserved(page))
+		if (pageblock_is_reserved(pfn))
 			continue;
 
 		block_migratetype = get_pageblock_migratetype(page);
diff --git a/mm/shmem.c b/mm/shmem.c
index 356dd99566e..66af0c87d91 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -2674,6 +2674,14 @@ put_memory:
 }
 EXPORT_SYMBOL_GPL(shmem_file_setup);
 
+void shmem_set_file(struct vm_area_struct *vma, struct file *file)
+{
+	if (vma->vm_file)
+		fput(vma->vm_file);
+	vma->vm_file = file;
+	vma->vm_ops = &shmem_vm_ops;
+}
+
 /**
  * shmem_zero_setup - setup a shared anonymous mapping
  * @vma: the vma to be mmapped is prepared by do_mmap_pgoff
@@ -2686,10 +2694,6 @@ int shmem_zero_setup(struct vm_area_struct *vma)
 	file = shmem_file_setup("dev/zero", size, vma->vm_flags);
 	if (IS_ERR(file))
 		return PTR_ERR(file);
-
-	if (vma->vm_file)
-		fput(vma->vm_file);
-	vma->vm_file = file;
-	vma->vm_ops = &shmem_vm_ops;
+	shmem_set_file(vma, file);
 	return 0;
 }
diff --git a/net/Kconfig b/net/Kconfig
index 041c35edb76..94312cb3a57 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -79,6 +79,12 @@ source "net/netlabel/Kconfig"
 
 endif # if INET
 
+config ANDROID_PARANOID_NETWORK
+	bool "Only allow certain groups to create sockets"
+	default y
+	help
+		none
+
 config NETWORK_SECMARK
 	bool "Security Marking"
 	help
diff --git a/net/bluetooth/af_bluetooth.c b/net/bluetooth/af_bluetooth.c
index 8cfb5a84984..1707efb7cb0 100644
--- a/net/bluetooth/af_bluetooth.c
+++ b/net/bluetooth/af_bluetooth.c
@@ -41,6 +41,15 @@
 
 #include <net/bluetooth/bluetooth.h>
 
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+#include <linux/android_aid.h>
+#endif
+
+#ifndef CONFIG_BT_SOCK_DEBUG
+#undef  BT_DBG
+#define BT_DBG(D...)
+#endif
+
 #define VERSION "2.15"
 
 /* Bluetooth sockets */
@@ -126,10 +135,39 @@ int bt_sock_unregister(int proto)
 }
 EXPORT_SYMBOL(bt_sock_unregister);
 
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+static inline int current_has_bt_admin(void)
+{
+	return (!current_euid() || in_egroup_p(AID_NET_BT_ADMIN));
+}
+
+static inline int current_has_bt(void)
+{
+	return (current_has_bt_admin() || in_egroup_p(AID_NET_BT));
+}
+# else
+static inline int current_has_bt_admin(void)
+{
+	return 1;
+}
+
+static inline int current_has_bt(void)
+{
+	return 1;
+}
+#endif
+
 static int bt_sock_create(struct net *net, struct socket *sock, int proto)
 {
 	int err;
 
+	if (proto == BTPROTO_RFCOMM || proto == BTPROTO_SCO ||
+			proto == BTPROTO_L2CAP) {
+		if (!current_has_bt())
+			return -EPERM;
+	} else if (!current_has_bt_admin())
+		return -EPERM;
+
 	if (net != &init_net)
 		return -EAFNOSUPPORT;
 
diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index b7c4224f4e7..2f4d30fd122 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -196,7 +196,8 @@ static void hci_conn_idle(unsigned long arg)
 	hci_conn_enter_sniff_mode(conn);
 }
 
-struct hci_conn *hci_conn_add(struct hci_dev *hdev, int type, bdaddr_t *dst)
+struct hci_conn *hci_conn_add(struct hci_dev *hdev, int type,
+					__u16 pkt_type, bdaddr_t *dst)
 {
 	struct hci_conn *conn;
 
@@ -221,14 +222,22 @@ struct hci_conn *hci_conn_add(struct hci_dev *hdev, int type, bdaddr_t *dst)
 		conn->pkt_type = hdev->pkt_type & ACL_PTYPE_MASK;
 		break;
 	case SCO_LINK:
-		if (lmp_esco_capable(hdev))
-			conn->pkt_type = (hdev->esco_type & SCO_ESCO_MASK) |
-					(hdev->esco_type & EDR_ESCO_MASK);
-		else
-			conn->pkt_type = hdev->pkt_type & SCO_PTYPE_MASK;
-		break;
+		if (!pkt_type)
+			pkt_type = SCO_ESCO_MASK;
 	case ESCO_LINK:
-		conn->pkt_type = hdev->esco_type & ~EDR_ESCO_MASK;
+		if (!pkt_type)
+			pkt_type = ALL_ESCO_MASK;
+		if (lmp_esco_capable(hdev)) {
+			/* HCI Setup Synchronous Connection Command uses
+			   reverse logic on the EDR_ESCO_MASK bits */
+			conn->pkt_type = (pkt_type ^ EDR_ESCO_MASK) &
+					hdev->esco_type;
+		} else {
+			/* Legacy HCI Add Sco Connection Command uses a
+			   shifted bitmask */
+			conn->pkt_type = (pkt_type << 5) & hdev->pkt_type &
+					SCO_PTYPE_MASK;
+		}
 		break;
 	}
 
@@ -340,7 +349,9 @@ EXPORT_SYMBOL(hci_get_route);
 
 /* Create SCO or ACL connection.
  * Device _must_ be locked */
-struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8 sec_level, __u8 auth_type)
+struct hci_conn *hci_connect(struct hci_dev *hdev, int type,
+					__u16 pkt_type, bdaddr_t *dst,
+					__u8 sec_level, __u8 auth_type)
 {
 	struct hci_conn *acl;
 	struct hci_conn *sco;
@@ -348,7 +359,7 @@ struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8
 	BT_DBG("%s dst %s", hdev->name, batostr(dst));
 
 	if (!(acl = hci_conn_hash_lookup_ba(hdev, ACL_LINK, dst))) {
-		if (!(acl = hci_conn_add(hdev, ACL_LINK, dst)))
+		if (!(acl = hci_conn_add(hdev, ACL_LINK, 0, dst)))
 			return NULL;
 	}
 
@@ -364,7 +375,7 @@ struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8
 		return acl;
 
 	if (!(sco = hci_conn_hash_lookup_ba(hdev, type, dst))) {
-		if (!(sco = hci_conn_add(hdev, type, dst))) {
+		if (!(sco = hci_conn_add(hdev, type, pkt_type, dst))) {
 			hci_conn_put(acl);
 			return NULL;
 		}
@@ -377,6 +388,9 @@ struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8
 
 	if (acl->state == BT_CONNECTED &&
 			(sco->state == BT_OPEN || sco->state == BT_CLOSED)) {
+		acl->power_save = 1;
+		hci_conn_enter_active_mode(acl);
+
 		if (lmp_esco_capable(hdev))
 			hci_setup_sync(sco, acl->handle);
 		else
@@ -497,7 +511,7 @@ void hci_conn_enter_active_mode(struct hci_conn *conn)
 	if (test_bit(HCI_RAW, &hdev->flags))
 		return;
 
-	if (conn->mode != HCI_CM_SNIFF || !conn->power_save)
+	if (conn->mode != HCI_CM_SNIFF /* || !conn->power_save */)
 		goto timer;
 
 	if (!test_and_set_bit(HCI_CONN_MODE_CHANGE_PEND, &conn->pend)) {
@@ -636,6 +650,15 @@ int hci_get_conn_list(void __user *arg)
 		(ci + n)->out   = c->out;
 		(ci + n)->state = c->state;
 		(ci + n)->link_mode = c->link_mode;
+		if (c->type == SCO_LINK) {
+			(ci + n)->mtu = hdev->sco_mtu;
+			(ci + n)->cnt = hdev->sco_cnt;
+			(ci + n)->pkts = hdev->sco_pkts;
+		} else {
+			(ci + n)->mtu = hdev->acl_mtu;
+			(ci + n)->cnt = hdev->acl_cnt;
+			(ci + n)->pkts = hdev->acl_pkts;
+		}
 		if (++n >= req.conn_num)
 			break;
 	}
@@ -672,6 +695,15 @@ int hci_get_conn_info(struct hci_dev *hdev, void __user *arg)
 		ci.out   = conn->out;
 		ci.state = conn->state;
 		ci.link_mode = conn->link_mode;
+		if (req.type == SCO_LINK) {
+			ci.mtu = hdev->sco_mtu;
+			ci.cnt = hdev->sco_cnt;
+			ci.pkts = hdev->sco_pkts;
+		} else {
+			ci.mtu = hdev->acl_mtu;
+			ci.cnt = hdev->acl_cnt;
+			ci.pkts = hdev->acl_pkts;
+		}
 	}
 	hci_dev_unlock_bh(hdev);
 
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index e1da8f68759..84a9d75b0c6 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -1239,7 +1239,7 @@ int hci_send_acl(struct hci_conn *conn, struct sk_buff *skb, __u16 flags)
 
 	skb->dev = (void *) hdev;
 	bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT;
-	hci_add_acl_hdr(skb, conn->handle, flags | ACL_START);
+	hci_add_acl_hdr(skb, conn->handle, flags);
 
 	if (!(list = skb_shinfo(skb)->frag_list)) {
 		/* Non fragmented */
@@ -1256,12 +1256,14 @@ int hci_send_acl(struct hci_conn *conn, struct sk_buff *skb, __u16 flags)
 		spin_lock_bh(&conn->data_q.lock);
 
 		__skb_queue_tail(&conn->data_q, skb);
+		flags &= ~ACL_PB_MASK;
+		flags |= ACL_CONT;
 		do {
 			skb = list; list = list->next;
 
 			skb->dev = (void *) hdev;
 			bt_cb(skb)->pkt_type = HCI_ACLDATA_PKT;
-			hci_add_acl_hdr(skb, conn->handle, flags | ACL_CONT);
+			hci_add_acl_hdr(skb, conn->handle, flags);
 
 			BT_DBG("%s frag %p len %d", hdev->name, skb, skb->len);
 
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index e99fe385fba..5343e0f664d 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -579,7 +579,7 @@ static inline void hci_cs_create_conn(struct hci_dev *hdev, __u8 status)
 		}
 	} else {
 		if (!conn) {
-			conn = hci_conn_add(hdev, ACL_LINK, &cp->bdaddr);
+			conn = hci_conn_add(hdev, ACL_LINK, 0, &cp->bdaddr);
 			if (conn) {
 				conn->out = 1;
 				conn->link_mode |= HCI_LM_MASTER;
@@ -964,7 +964,9 @@ static inline void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *sk
 
 		conn = hci_conn_hash_lookup_ba(hdev, ev->link_type, &ev->bdaddr);
 		if (!conn) {
-			if (!(conn = hci_conn_add(hdev, ev->link_type, &ev->bdaddr))) {
+			/* pkt_type not yet used for incoming connections */
+			if (!(conn = hci_conn_add(hdev, ev->link_type, 0,
+							&ev->bdaddr))) {
 				BT_ERR("No memmory for new connection");
 				hci_dev_unlock(hdev);
 				return;
@@ -1698,7 +1700,9 @@ static inline void hci_sync_conn_complete_evt(struct hci_dev *hdev, struct sk_bu
 		hci_conn_add_sysfs(conn);
 		break;
 
+	case 0x10:	/* Connection Accept Timeout */
 	case 0x1c:	/* SCO interval rejected */
+	case 0x1a:	/* unsupported feature */
 	case 0x1f:	/* Unspecified error */
 		if (conn->out && conn->attempt < 2) {
 			conn->pkt_type = (hdev->esco_type & SCO_ESCO_MASK) |
diff --git a/net/bluetooth/l2cap.c b/net/bluetooth/l2cap.c
index 947f8bbb4bb..424712ca28b 100644
--- a/net/bluetooth/l2cap.c
+++ b/net/bluetooth/l2cap.c
@@ -325,13 +325,19 @@ static inline u8 l2cap_get_ident(struct l2cap_conn *conn)
 static inline int l2cap_send_cmd(struct l2cap_conn *conn, u8 ident, u8 code, u16 len, void *data)
 {
 	struct sk_buff *skb = l2cap_build_cmd(conn, code, ident, len, data);
+	u8 flags;
 
 	BT_DBG("code 0x%2.2x", code);
 
 	if (!skb)
 		return -ENOMEM;
 
-	return hci_send_acl(conn->hcon, skb, 0);
+	if (lmp_no_flush_capable(conn->hcon->hdev))
+		flags = ACL_START_NO_FLUSH;
+	else
+		flags = ACL_START;
+
+	return hci_send_acl(conn->hcon, skb, flags);
 }
 
 static inline int l2cap_send_sframe(struct l2cap_pinfo *pi, u16 control)
@@ -458,7 +464,8 @@ static void l2cap_conn_start(struct l2cap_conn *conn)
 					struct sock *parent = bt_sk(sk)->parent;
 					rsp.result = cpu_to_le16(L2CAP_CR_PEND);
 					rsp.status = cpu_to_le16(L2CAP_CS_AUTHOR_PEND);
-					parent->sk_data_ready(parent, 0);
+					if (parent)
+						parent->sk_data_ready(parent, 0);
 
 				} else {
 					sk->sk_state = BT_CONFIG;
@@ -770,6 +777,7 @@ static void l2cap_sock_init(struct sock *sk, struct sock *parent)
 		pi->sec_level = l2cap_pi(parent)->sec_level;
 		pi->role_switch = l2cap_pi(parent)->role_switch;
 		pi->force_reliable = l2cap_pi(parent)->force_reliable;
+		pi->flushable = l2cap_pi(parent)->flushable;
 	} else {
 		pi->imtu = L2CAP_DEFAULT_MTU;
 		pi->omtu = 0;
@@ -778,6 +786,7 @@ static void l2cap_sock_init(struct sock *sk, struct sock *parent)
 		pi->sec_level = BT_SECURITY_LOW;
 		pi->role_switch = 0;
 		pi->force_reliable = 0;
+		pi->flushable = 0;
 	}
 
 	/* Default config options */
@@ -953,7 +962,7 @@ static int l2cap_do_connect(struct sock *sk)
 		}
 	}
 
-	hcon = hci_connect(hdev, ACL_LINK, dst,
+	hcon = hci_connect(hdev, ACL_LINK, 0, dst,
 					l2cap_pi(sk)->sec_level, auth_type);
 	if (!hcon)
 		goto done;
@@ -1258,11 +1267,18 @@ static void l2cap_drop_acked_frames(struct sock *sk)
 static inline int l2cap_do_send(struct sock *sk, struct sk_buff *skb)
 {
 	struct l2cap_pinfo *pi = l2cap_pi(sk);
+	struct hci_conn *hcon = pi->conn->hcon;
 	int err;
+	u16 flags;
 
 	BT_DBG("sk %p, skb %p len %d", sk, skb, skb->len);
 
-	err = hci_send_acl(pi->conn->hcon, skb, 0);
+	if (lmp_no_flush_capable(hcon->hdev) && !l2cap_pi(sk)->flushable)
+		flags = ACL_START_NO_FLUSH;
+	else
+		flags = ACL_START;
+
+	err = hci_send_acl(hcon, skb, flags);
 	if (err < 0)
 		kfree_skb(skb);
 
@@ -1747,6 +1763,7 @@ static int l2cap_sock_setsockopt_old(struct socket *sock, int optname, char __us
 
 		l2cap_pi(sk)->role_switch    = (opt & L2CAP_LM_MASTER);
 		l2cap_pi(sk)->force_reliable = (opt & L2CAP_LM_RELIABLE);
+		l2cap_pi(sk)->flushable = (opt & L2CAP_LM_FLUSHABLE);
 		break;
 
 	default:
@@ -1874,6 +1891,9 @@ static int l2cap_sock_getsockopt_old(struct socket *sock, int optname, char __us
 		if (l2cap_pi(sk)->force_reliable)
 			opt |= L2CAP_LM_RELIABLE;
 
+		if (l2cap_pi(sk)->flushable)
+			opt |= L2CAP_LM_FLUSHABLE;
+
 		if (put_user(opt, (u32 __user *) optval))
 			err = -EFAULT;
 		break;
@@ -3801,7 +3821,7 @@ static int l2cap_recv_acldata(struct hci_conn *hcon, struct sk_buff *skb, u16 fl
 
 	BT_DBG("conn %p len %d flags 0x%x", conn, skb->len, flags);
 
-	if (flags & ACL_START) {
+	if (!(flags & ACL_CONT)) {
 		struct l2cap_hdr *hdr;
 		int len;
 
diff --git a/net/bluetooth/rfcomm/core.c b/net/bluetooth/rfcomm/core.c
index 25692bc0a34..483b8ab62f0 100644
--- a/net/bluetooth/rfcomm/core.c
+++ b/net/bluetooth/rfcomm/core.c
@@ -244,33 +244,6 @@ static inline int rfcomm_check_security(struct rfcomm_dlc *d)
 								auth_type);
 }
 
-static void rfcomm_session_timeout(unsigned long arg)
-{
-	struct rfcomm_session *s = (void *) arg;
-
-	BT_DBG("session %p state %ld", s, s->state);
-
-	set_bit(RFCOMM_TIMED_OUT, &s->flags);
-	rfcomm_session_put(s);
-	rfcomm_schedule(RFCOMM_SCHED_TIMEO);
-}
-
-static void rfcomm_session_set_timer(struct rfcomm_session *s, long timeout)
-{
-	BT_DBG("session %p state %ld timeout %ld", s, s->state, timeout);
-
-	if (!mod_timer(&s->timer, jiffies + timeout))
-		rfcomm_session_hold(s);
-}
-
-static void rfcomm_session_clear_timer(struct rfcomm_session *s)
-{
-	BT_DBG("session %p state %ld", s, s->state);
-
-	if (timer_pending(&s->timer) && del_timer(&s->timer))
-		rfcomm_session_put(s);
-}
-
 /* ---- RFCOMM DLCs ---- */
 static void rfcomm_dlc_timeout(unsigned long arg)
 {
@@ -347,7 +320,6 @@ static void rfcomm_dlc_link(struct rfcomm_session *s, struct rfcomm_dlc *d)
 
 	rfcomm_session_hold(s);
 
-	rfcomm_session_clear_timer(s);
 	rfcomm_dlc_hold(d);
 	list_add(&d->list, &s->dlcs);
 	d->session = s;
@@ -363,9 +335,6 @@ static void rfcomm_dlc_unlink(struct rfcomm_dlc *d)
 	d->session = NULL;
 	rfcomm_dlc_put(d);
 
-	if (list_empty(&s->dlcs))
-		rfcomm_session_set_timer(s, RFCOMM_IDLE_TIMEOUT);
-
 	rfcomm_session_put(s);
 }
 
@@ -459,7 +428,6 @@ static int __rfcomm_dlc_close(struct rfcomm_dlc *d, int err)
 
 	switch (d->state) {
 	case BT_CONNECT:
-	case BT_CONFIG:
 		if (test_and_clear_bit(RFCOMM_DEFER_SETUP, &d->flags)) {
 			set_bit(RFCOMM_AUTH_REJECT, &d->flags);
 			rfcomm_schedule(RFCOMM_SCHED_AUTH);
@@ -479,7 +447,6 @@ static int __rfcomm_dlc_close(struct rfcomm_dlc *d, int err)
 		break;
 
 	case BT_OPEN:
-	case BT_CONNECT2:
 		if (test_and_clear_bit(RFCOMM_DEFER_SETUP, &d->flags)) {
 			set_bit(RFCOMM_AUTH_REJECT, &d->flags);
 			rfcomm_schedule(RFCOMM_SCHED_AUTH);
@@ -598,8 +565,6 @@ static struct rfcomm_session *rfcomm_session_add(struct socket *sock, int state)
 
 	BT_DBG("session %p sock %p", s, sock);
 
-	setup_timer(&s->timer, rfcomm_session_timeout, (unsigned long) s);
-
 	INIT_LIST_HEAD(&s->dlcs);
 	s->state = state;
 	s->sock  = sock;
@@ -631,7 +596,6 @@ static void rfcomm_session_del(struct rfcomm_session *s)
 	if (state == BT_CONNECTED)
 		rfcomm_send_disc(s, 0);
 
-	rfcomm_session_clear_timer(s);
 	sock_release(s->sock);
 	kfree(s);
 
@@ -673,7 +637,6 @@ static void rfcomm_session_close(struct rfcomm_session *s, int err)
 		__rfcomm_dlc_close(d, err);
 	}
 
-	rfcomm_session_clear_timer(s);
 	rfcomm_session_put(s);
 }
 
@@ -1148,7 +1111,8 @@ static int rfcomm_recv_ua(struct rfcomm_session *s, u8 dlci)
 			break;
 
 		case BT_DISCONN:
-			rfcomm_session_put(s);
+			if (s->sock->sk->sk_state != BT_CLOSED)
+				rfcomm_session_put(s);
 			break;
 		}
 	}
@@ -1229,8 +1193,6 @@ void rfcomm_dlc_accept(struct rfcomm_dlc *d)
 
 	rfcomm_send_ua(d->session, d->dlci);
 
-	rfcomm_dlc_clear_timer(d);
-
 	rfcomm_dlc_lock(d);
 	d->state = BT_CONNECTED;
 	d->state_change(d, 0);
@@ -1248,11 +1210,6 @@ static void rfcomm_check_accept(struct rfcomm_dlc *d)
 		if (d->defer_setup) {
 			set_bit(RFCOMM_DEFER_SETUP, &d->flags);
 			rfcomm_dlc_set_timer(d, RFCOMM_AUTH_TIMEOUT);
-
-			rfcomm_dlc_lock(d);
-			d->state = BT_CONNECT2;
-			d->state_change(d, 0);
-			rfcomm_dlc_unlock(d);
 		} else
 			rfcomm_dlc_accept(d);
 	} else {
@@ -1794,11 +1751,6 @@ static inline void rfcomm_process_dlcs(struct rfcomm_session *s)
 				if (d->defer_setup) {
 					set_bit(RFCOMM_DEFER_SETUP, &d->flags);
 					rfcomm_dlc_set_timer(d, RFCOMM_AUTH_TIMEOUT);
-
-					rfcomm_dlc_lock(d);
-					d->state = BT_CONNECT2;
-					d->state_change(d, 0);
-					rfcomm_dlc_unlock(d);
 				} else
 					rfcomm_dlc_accept(d);
 			}
@@ -1914,12 +1866,6 @@ static inline void rfcomm_process_sessions(void)
 		struct rfcomm_session *s;
 		s = list_entry(p, struct rfcomm_session, list);
 
-		if (test_and_clear_bit(RFCOMM_TIMED_OUT, &s->flags)) {
-			s->state = BT_DISCONN;
-			rfcomm_send_disc(s, 0);
-			continue;
-		}
-
 		if (s->state == BT_LISTEN) {
 			rfcomm_accept_connection(s);
 			continue;
diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c
index 77f4153bdb5..e4343cabedf 100644
--- a/net/bluetooth/sco.c
+++ b/net/bluetooth/sco.c
@@ -176,6 +176,7 @@ static int sco_connect(struct sock *sk)
 {
 	bdaddr_t *src = &bt_sk(sk)->src;
 	bdaddr_t *dst = &bt_sk(sk)->dst;
+	__u16 pkt_type = sco_pi(sk)->pkt_type;
 	struct sco_conn *conn;
 	struct hci_conn *hcon;
 	struct hci_dev  *hdev;
@@ -192,10 +193,13 @@ static int sco_connect(struct sock *sk)
 
 	if (lmp_esco_capable(hdev) && !disable_esco)
 		type = ESCO_LINK;
-	else
+	else {
 		type = SCO_LINK;
+		pkt_type &= SCO_ESCO_MASK;
+	}
 
-	hcon = hci_connect(hdev, type, dst, BT_SECURITY_LOW, HCI_AT_NO_BONDING);
+	hcon = hci_connect(hdev, type, pkt_type, dst,
+					BT_SECURITY_LOW, HCI_AT_NO_BONDING);
 	if (!hcon)
 		goto done;
 
@@ -451,18 +455,22 @@ static int sco_sock_create(struct net *net, struct socket *sock, int protocol)
 	return 0;
 }
 
-static int sco_sock_bind(struct socket *sock, struct sockaddr *addr, int addr_len)
+static int sco_sock_bind(struct socket *sock, struct sockaddr *addr, int alen)
 {
-	struct sockaddr_sco *sa = (struct sockaddr_sco *) addr;
+	struct sockaddr_sco sa;
 	struct sock *sk = sock->sk;
-	bdaddr_t *src = &sa->sco_bdaddr;
-	int err = 0;
+	bdaddr_t *src = &sa.sco_bdaddr;
+	int len, err = 0;
 
-	BT_DBG("sk %p %s", sk, batostr(&sa->sco_bdaddr));
+	BT_DBG("sk %p %s", sk, batostr(&sa.sco_bdaddr));
 
 	if (!addr || addr->sa_family != AF_BLUETOOTH)
 		return -EINVAL;
 
+	memset(&sa, 0, sizeof(sa));
+	len = min_t(unsigned int, sizeof(sa), alen);
+	memcpy(&sa, addr, len);
+
 	lock_sock(sk);
 
 	if (sk->sk_state != BT_OPEN) {
@@ -476,7 +484,8 @@ static int sco_sock_bind(struct socket *sock, struct sockaddr *addr, int addr_le
 		err = -EADDRINUSE;
 	} else {
 		/* Save source address */
-		bacpy(&bt_sk(sk)->src, &sa->sco_bdaddr);
+		bacpy(&bt_sk(sk)->src, &sa.sco_bdaddr);
+		sco_pi(sk)->pkt_type = sa.sco_pkt_type;
 		sk->sk_state = BT_BOUND;
 	}
 
@@ -489,26 +498,34 @@ done:
 
 static int sco_sock_connect(struct socket *sock, struct sockaddr *addr, int alen, int flags)
 {
-	struct sockaddr_sco *sa = (struct sockaddr_sco *) addr;
 	struct sock *sk = sock->sk;
-	int err = 0;
-
+	struct sockaddr_sco sa;
+	int len, err = 0;
 
 	BT_DBG("sk %p", sk);
 
-	if (addr->sa_family != AF_BLUETOOTH || alen < sizeof(struct sockaddr_sco))
+	if (!addr || addr->sa_family != AF_BLUETOOTH)
 		return -EINVAL;
 
-	if (sk->sk_state != BT_OPEN && sk->sk_state != BT_BOUND)
-		return -EBADFD;
-
-	if (sk->sk_type != SOCK_SEQPACKET)
-		return -EINVAL;
+	memset(&sa, 0, sizeof(sa));
+	len = min_t(unsigned int, sizeof(sa), alen);
+	memcpy(&sa, addr, len);
 
 	lock_sock(sk);
 
+	if (sk->sk_type != SOCK_SEQPACKET) {
+		err = -EINVAL;
+		goto done;
+	}
+
+	if (sk->sk_state != BT_OPEN && sk->sk_state != BT_BOUND) {
+		err = -EBADFD;
+		goto done;
+	}
+
 	/* Set destination address and psm */
-	bacpy(&bt_sk(sk)->dst, &sa->sco_bdaddr);
+	bacpy(&bt_sk(sk)->dst, &sa.sco_bdaddr);
+	sco_pi(sk)->pkt_type = sa.sco_pkt_type;
 
 	if ((err = sco_connect(sk)))
 		goto done;
@@ -614,6 +631,7 @@ static int sco_sock_getname(struct socket *sock, struct sockaddr *addr, int *len
 		bacpy(&sa->sco_bdaddr, &bt_sk(sk)->dst);
 	else
 		bacpy(&sa->sco_bdaddr, &bt_sk(sk)->src);
+	sa->sco_pkt_type = sco_pi(sk)->pkt_type;
 
 	return 0;
 }
diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile
index 80ff87ce43a..6a13dce23c4 100644
--- a/net/ipv4/Makefile
+++ b/net/ipv4/Makefile
@@ -14,6 +14,7 @@ obj-y     := route.o inetpeer.o protocol.o \
 	     inet_fragment.o
 
 obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o
+obj-$(CONFIG_SYSFS) += sysfs_net_ipv4.o
 obj-$(CONFIG_IP_FIB_HASH) += fib_hash.o
 obj-$(CONFIG_IP_FIB_TRIE) += fib_trie.o
 obj-$(CONFIG_PROC_FS) += proc.o
diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c
index 57737b8d171..58525bd7250 100644
--- a/net/ipv4/af_inet.c
+++ b/net/ipv4/af_inet.c
@@ -116,6 +116,19 @@
 #include <linux/mroute.h>
 #endif
 
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+#include <linux/android_aid.h>
+
+static inline int current_has_network(void)
+{
+	return in_egroup_p(AID_INET) || capable(CAP_NET_RAW);
+}
+#else
+static inline int current_has_network(void)
+{
+	return 1;
+}
+#endif
 
 /* The inetsw table contains everything that inet_create needs to
  * build a new socket.
@@ -258,6 +271,7 @@ static inline int inet_netns_ok(struct net *net, int protocol)
 	return ipprot->netns_ok;
 }
 
+
 /*
  *	Create an inet socket.
  */
@@ -273,6 +287,9 @@ static int inet_create(struct net *net, struct socket *sock, int protocol)
 	int try_loading_module = 0;
 	int err;
 
+	if (!current_has_network())
+		return -EACCES;
+
 	if (unlikely(!inet_ehash_secret))
 		if (sock->type != SOCK_RAW && sock->type != SOCK_DGRAM)
 			build_ehash_secret();
@@ -836,6 +853,7 @@ int inet_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg)
 	case SIOCSIFPFLAGS:
 	case SIOCGIFPFLAGS:
 	case SIOCSIFFLAGS:
+	case SIOCKILLADDR:
 		err = devinet_ioctl(net, cmd, (void __user *)arg);
 		break;
 	default:
diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c
index 0030e73728e..19a5f3ce53a 100644
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -57,6 +57,7 @@
 
 #include <net/arp.h>
 #include <net/ip.h>
+#include <net/tcp.h>
 #include <net/route.h>
 #include <net/ip_fib.h>
 #include <net/rtnetlink.h>
@@ -631,6 +632,7 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg)
 	case SIOCSIFBRDADDR:	/* Set the broadcast address */
 	case SIOCSIFDSTADDR:	/* Set the destination address */
 	case SIOCSIFNETMASK: 	/* Set the netmask for the interface */
+	case SIOCKILLADDR:	/* Nuke all sockets on this address */
 		ret = -EACCES;
 		if (!capable(CAP_NET_ADMIN))
 			goto out;
@@ -680,7 +682,8 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg)
 	}
 
 	ret = -EADDRNOTAVAIL;
-	if (!ifa && cmd != SIOCSIFADDR && cmd != SIOCSIFFLAGS)
+	if (!ifa && cmd != SIOCSIFADDR && cmd != SIOCSIFFLAGS
+	    && cmd != SIOCKILLADDR)
 		goto done;
 
 	switch (cmd) {
@@ -804,6 +807,10 @@ int devinet_ioctl(struct net *net, unsigned int cmd, void __user *arg)
 			inet_insert_ifa(ifa);
 		}
 		break;
+	case SIOCKILLADDR:	/* Nuke all connections on this address */
+		ret = 0;
+		tcp_v4_nuke_addr(sin->sin_addr.s_addr);
+		break;
 	}
 done:
 	rtnl_unlock();
diff --git a/net/ipv4/sysfs_net_ipv4.c b/net/ipv4/sysfs_net_ipv4.c
new file mode 100644
index 00000000000..0cbbf10026a
--- /dev/null
+++ b/net/ipv4/sysfs_net_ipv4.c
@@ -0,0 +1,88 @@
+/*
+ * net/ipv4/sysfs_net_ipv4.c
+ *
+ * sysfs-based networking knobs (so we can, unlike with sysctl, control perms)
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * Robert Love <rlove@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/init.h>
+#include <net/tcp.h>
+
+#define CREATE_IPV4_FILE(_name, _var) \
+static ssize_t _name##_show(struct kobject *kobj, \
+			    struct kobj_attribute *attr, char *buf) \
+{ \
+	return sprintf(buf, "%d\n", _var); \
+} \
+static ssize_t _name##_store(struct kobject *kobj, \
+			     struct kobj_attribute *attr, \
+			     const char *buf, size_t count) \
+{ \
+	int val, ret; \
+	ret = sscanf(buf, "%d", &val); \
+	if (ret != 1) \
+		return -EINVAL; \
+	if (val < 0) \
+		return -EINVAL; \
+	_var = val; \
+	return count; \
+} \
+static struct kobj_attribute _name##_attr = \
+	__ATTR(_name, 0644, _name##_show, _name##_store)
+
+CREATE_IPV4_FILE(tcp_wmem_min, sysctl_tcp_wmem[0]);
+CREATE_IPV4_FILE(tcp_wmem_def, sysctl_tcp_wmem[1]);
+CREATE_IPV4_FILE(tcp_wmem_max, sysctl_tcp_wmem[2]);
+
+CREATE_IPV4_FILE(tcp_rmem_min, sysctl_tcp_rmem[0]);
+CREATE_IPV4_FILE(tcp_rmem_def, sysctl_tcp_rmem[1]);
+CREATE_IPV4_FILE(tcp_rmem_max, sysctl_tcp_rmem[2]);
+
+static struct attribute *ipv4_attrs[] = {
+	&tcp_wmem_min_attr.attr,
+	&tcp_wmem_def_attr.attr,
+	&tcp_wmem_max_attr.attr,
+	&tcp_rmem_min_attr.attr,
+	&tcp_rmem_def_attr.attr,
+	&tcp_rmem_max_attr.attr,
+	NULL
+};
+
+static struct attribute_group ipv4_attr_group = {
+	.attrs = ipv4_attrs,
+};
+
+static __init int sysfs_ipv4_init(void)
+{
+	struct kobject *ipv4_kobject;
+	int ret;
+
+	ipv4_kobject = kobject_create_and_add("ipv4", kernel_kobj);
+	if (!ipv4_kobject)
+		return -ENOMEM;
+
+	ret = sysfs_create_group(ipv4_kobject, &ipv4_attr_group);
+	if (ret) {
+		kobject_put(ipv4_kobject);
+		return ret;
+	}
+
+	return 0;
+}
+
+subsys_initcall(sysfs_ipv4_init);
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index 7cda24b53f6..315805d1ced 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -1884,6 +1884,49 @@ void tcp_v4_destroy_sock(struct sock *sk)
 
 EXPORT_SYMBOL(tcp_v4_destroy_sock);
 
+/*
+ * tcp_v4_nuke_addr - destroy all sockets on the given local address
+ */
+void tcp_v4_nuke_addr(__u32 saddr)
+{
+	unsigned int bucket;
+
+	for (bucket = 0; bucket < tcp_hashinfo.ehash_size; bucket++) {
+		struct hlist_nulls_node *node;
+		struct sock *sk;
+		spinlock_t *lock = inet_ehash_lockp(&tcp_hashinfo, bucket);
+
+restart:
+		spin_lock_bh(lock);
+		sk_nulls_for_each(sk, node, &tcp_hashinfo.ehash[bucket].chain) {
+			struct inet_sock *inet = inet_sk(sk);
+
+			if (inet->rcv_saddr != saddr)
+				continue;
+			if (sysctl_ip_dynaddr && sk->sk_state == TCP_SYN_SENT)
+				continue;
+			if (sock_flag(sk, SOCK_DEAD))
+				continue;
+
+			sock_hold(sk);
+			spin_unlock_bh(lock);
+
+			local_bh_disable();
+			bh_lock_sock(sk);
+			sk->sk_err = ETIMEDOUT;
+			sk->sk_error_report(sk);
+
+			tcp_done(sk);
+			bh_unlock_sock(sk);
+			local_bh_enable();
+			sock_put(sk);
+
+			goto restart;
+		}
+		spin_unlock_bh(lock);
+	}
+}
+
 #ifdef CONFIG_PROC_FS
 /* Proc filesystem TCP sock list dumping. */
 
@@ -2493,4 +2536,3 @@ EXPORT_SYMBOL(tcp_proc_register);
 EXPORT_SYMBOL(tcp_proc_unregister);
 #endif
 EXPORT_SYMBOL(sysctl_tcp_low_latency);
-
diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c
index e127a32f954..2f7c3bf90e8 100644
--- a/net/ipv6/af_inet6.c
+++ b/net/ipv6/af_inet6.c
@@ -62,6 +62,20 @@
 #include <asm/system.h>
 #include <linux/mroute6.h>
 
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+#include <linux/android_aid.h>
+
+static inline int current_has_network(void)
+{
+	return in_egroup_p(AID_INET) || capable(CAP_NET_RAW);
+}
+#else
+static inline int current_has_network(void)
+{
+	return 1;
+}
+#endif
+
 MODULE_AUTHOR("Cast of dozens");
 MODULE_DESCRIPTION("IPv6 protocol stack for Linux");
 MODULE_LICENSE("GPL");
@@ -107,6 +121,9 @@ static int inet6_create(struct net *net, struct socket *sock, int protocol)
 	int try_loading_module = 0;
 	int err;
 
+	if (!current_has_network())
+		return -EACCES;
+
 	if (sock->type != SOCK_RAW &&
 	    sock->type != SOCK_DGRAM &&
 	    !inet_ehash_secret)
diff --git a/net/rfkill/Kconfig b/net/rfkill/Kconfig
index eaf76587645..51f4baeede8 100644
--- a/net/rfkill/Kconfig
+++ b/net/rfkill/Kconfig
@@ -10,6 +10,11 @@ menuconfig RFKILL
 	  To compile this driver as a module, choose M here: the
 	  module will be called rfkill.
 
+config RFKILL_PM
+	bool "Power off on suspend"
+	depends on RFKILL && PM
+	default y
+
 # LED trigger support
 config RFKILL_LEDS
 	bool
diff --git a/net/rfkill/core.c b/net/rfkill/core.c
index a001f7c1f71..c95475de2ce 100644
--- a/net/rfkill/core.c
+++ b/net/rfkill/core.c
@@ -741,6 +741,7 @@ void rfkill_pause_polling(struct rfkill *rfkill)
 }
 EXPORT_SYMBOL(rfkill_pause_polling);
 
+#ifdef CONFIG_RFKILL_PM
 void rfkill_resume_polling(struct rfkill *rfkill)
 {
 	BUG_ON(!rfkill);
@@ -775,14 +776,17 @@ static int rfkill_resume(struct device *dev)
 
 	return 0;
 }
+#endif
 
 static struct class rfkill_class = {
 	.name		= "rfkill",
 	.dev_release	= rfkill_release,
 	.dev_attrs	= rfkill_dev_attrs,
 	.dev_uevent	= rfkill_dev_uevent,
+#ifdef CONFIG_RFKILL_PM
 	.suspend	= rfkill_suspend,
 	.resume		= rfkill_resume,
+#endif
 };
 
 bool rfkill_blocked(struct rfkill *rfkill)
diff --git a/net/socket.c b/net/socket.c
index 75655365b5f..ed84099da26 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -97,6 +97,10 @@
 #include <net/sock.h>
 #include <linux/netfilter.h>
 
+#ifdef CONFIG_UID_STAT
+#include <linux/uid_stat.h>
+#endif
+
 static int sock_no_open(struct inode *irrelevant, struct file *dontcare);
 static ssize_t sock_aio_read(struct kiocb *iocb, const struct iovec *iov,
 			 unsigned long nr_segs, loff_t pos);
@@ -570,7 +574,12 @@ static inline int __sock_sendmsg(struct kiocb *iocb, struct socket *sock,
 	if (err)
 		return err;
 
-	return sock->ops->sendmsg(iocb, sock, msg, size);
+	err = sock->ops->sendmsg(iocb, sock, msg, size);
+#ifdef CONFIG_UID_STAT
+	if (err > 0)
+		update_tcp_snd(current_uid(), err);
+#endif
+	return err;
 }
 
 int sock_sendmsg(struct socket *sock, struct msghdr *msg, size_t size)
@@ -684,7 +693,12 @@ static inline int __sock_recvmsg(struct kiocb *iocb, struct socket *sock,
 	if (err)
 		return err;
 
-	return sock->ops->recvmsg(iocb, sock, msg, size, flags);
+	err = sock->ops->recvmsg(iocb, sock, msg, size, flags);
+#ifdef CONFIG_UID_STAT
+	if (err > 0)
+		update_tcp_rcv(current_uid(), err);
+#endif
+	return err;
 }
 
 int sock_recvmsg(struct socket *sock, struct msghdr *msg,
diff --git a/security/commoncap.c b/security/commoncap.c
index fe30751a6cd..ea768866f70 100644
--- a/security/commoncap.c
+++ b/security/commoncap.c
@@ -28,6 +28,10 @@
 #include <linux/prctl.h>
 #include <linux/securebits.h>
 
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+#include <linux/android_aid.h>
+#endif
+
 /*
  * If a non-root user executes a setuid-root binary in
  * !secure(SECURE_NOROOT) mode, then we raise capabilities.
@@ -82,6 +86,12 @@ EXPORT_SYMBOL(cap_netlink_recv);
 int cap_capable(struct task_struct *tsk, const struct cred *cred, int cap,
 		int audit)
 {
+#ifdef CONFIG_ANDROID_PARANOID_NETWORK
+	if (cap == CAP_NET_RAW && in_egroup_p(AID_NET_RAW))
+		return 0;
+	if (cap == CAP_NET_ADMIN && in_egroup_p(AID_NET_ADMIN))
+		return 0;
+#endif
 	return cap_raised(cred->cap_effective, cap) ? 0 : -EPERM;
 }
 
diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig
index 885683a3b0b..9c47ee292e2 100644
--- a/sound/arm/Kconfig
+++ b/sound/arm/Kconfig
@@ -11,6 +11,28 @@ menuconfig SND_ARM
 
 if SND_ARM
 
+config SND_AK98_PCM
+   tristate "Anyka AK98 ADC/DAC sound driver"
+   depends on ARCH_AK98
+   select SND_PCM
+   help
+      ALSA sound driver for the AK98 ADC/DAC.
+
+choice
+	prompt "HP/Speaker switch mode"
+	depends on SND_AK98_PCM
+
+config SPKHP_SWITCH_AUTO
+	bool "auto switch in audio driver(default, for both linux and android)"
+
+config SPKHP_SWITCH_MIXER
+	bool "notify,but not switch in audio driver(with ALSA lib amixer)"
+
+config SPKHP_SWITCH_UEVENT
+	bool "detect HP by UEVENT(only for android)"
+	
+endchoice
+
 config SND_ARMAACI
 	tristate "ARM PrimeCell PL041 AC Link support"
 	depends on ARM_AMBA
diff --git a/sound/arm/Makefile b/sound/arm/Makefile
index 5a549ed6c8a..8c6b9bb29d9 100644
--- a/sound/arm/Makefile
+++ b/sound/arm/Makefile
@@ -14,3 +14,6 @@ snd-pxa2xx-lib-$(CONFIG_SND_PXA2XX_LIB_AC97)	+= pxa2xx-ac97-lib.o
 
 obj-$(CONFIG_SND_PXA2XX_AC97)	+= snd-pxa2xx-ac97.o
 snd-pxa2xx-ac97-objs		:= pxa2xx-ac97.o
+
+obj-$(CONFIG_SND_AK98_PCM)    += snd-ak98pcm.o
+snd-ak98pcm-objs               := ak98pcm.o ak98_hal.o
diff --git a/sound/arm/ak98_hal.c b/sound/arm/ak98_hal.c
new file mode 100755
index 00000000000..85c155f41c7
--- /dev/null
+++ b/sound/arm/ak98_hal.c
@@ -0,0 +1,991 @@
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/i2c/aw9523.h>
+#include "mach/clock.h"
+
+#include <mach/ak98_hal.h>
+
+#define MAX_DACCLK 14000000
+#define HP_GAIN_MAX     0x8
+
+REG_ADDR RegAddr;
+static int ADC23_State = 0;
+static int DAC_State = 0;
+
+/**
+ * @brief  open a dac device 
+ * @author 
+ * @date   
+ * @return void
+ */
+void AK98_DAC_Open(void)
+{
+	int RegValue;
+	if(!DAC_State)
+	{
+	DAC_State = 1;
+	//enable DAC controller clk, l2 controller clk
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) &= ~(DAC_CLK_CTRL_EN | L2_CLK_CTRL_EN);
+
+	// to enable DAC CLK
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= DAC_CLK_EN;
+
+	//soft reset DAC
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) |= DAC_SOFT_RST;
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) &= ~(DAC_SOFT_RST);
+
+	//reset DAC
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~(DAC_RST);
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= DAC_RST;
+
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) &= ~MUTE;
+	//I2S config reg
+	REG32(RegAddr.pAddress2002E + I2S_CONFIG_REG) &= (~I2S_CONFIG_WORDLENGTH_MASK);
+	REG32(RegAddr.pAddress2002E + I2S_CONFIG_REG) |= 0XF;  //16 bit   for  memory saving mode.
+	REG32(RegAddr.pAddress2002E + I2S_CONFIG_REG) |= POLARITY_SEL; //Send data when left channel data shen data lrclk is high 
+
+	//enable internal DAC/ADC
+	REG32(RegAddr.pAddress0800 + MULTIPLE_FUN_CTRL_REG1) |= IN_DAAD_EN;
+
+	//to provide DAC CLK for DAC
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~(DAC_GATE);
+
+	// to enable DACs
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) |= DAC_EN;
+
+	//config I2S interface DAC
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) |= L2_EN;
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) |= DAC_CTRL_EN;
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) &= ~ARM_INT;
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) |= FORMAT;
+
+	//disable vcm2 discharging
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(PTM_D_CHG_EN);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+	//set vcm2 to normal
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(PL_VCM2);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+	//charge vcm2 slow
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(VREF_CHG_FAST);  //not charge VREF fast
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) |= (1 << 13);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) &= ~(1 << 12);
+
+	//power on integrator in DAC, power on DAC clk
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(PD_OP | PD_CK);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	
+	//power on DAC amplifier
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) &= ~(PD_DAOUTL);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) &= ~(PD_DAOUTR);
+	}
+}
+
+/**
+ * @brief   Close a dac device
+ * @author  
+ * @date   
+ * @return  void
+ */
+void AK98_DAC_Close(void)
+{
+	int RegValue;
+	if(DAC_State)
+	{
+	DAC_State = 0;
+	REG32(RegAddr.pAddress2002E + DAC_CONFIG_REG) &= (~L2_EN);
+
+	// to power off DACs/DAC clock
+    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);   
+    RegValue |= (PD_OP);
+    RegValue |= (PD_CK);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+	mdelay(10);
+
+    REG32(RegAddr.pAddress0800 + MULTIPLE_FUN_CTRL_REG1) &= (~(IN_DAAD_EN));// tdisable internal DAC/ADC
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= (~DAC_CLK_EN);// disable DAC CLK
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= DAC_GATE;//inhibit DAC CLK for DAC
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) &= (~DAC_EN);// to disable DACs
+	}
+}
+
+/**
+ * @brief   Get OSR and DACDIV refer to appointed PLL and sample rate
+ * @author  
+ * @date   
+ * @input   des_sr: destination sample rate
+ * @output  osrindex: OSR index
+ * @output  mclkdiv: mclk div
+ * @return  void
+ */
+static void DAC_GetOsrDiv(unsigned char *osrindex, unsigned char *mclkdiv, unsigned long des_sr)
+{
+    const unsigned short OSR_table[8] = 
+        {256, 272, 264, 248, 240, 136, 128, 120};
+
+    unsigned long j;
+    unsigned long max_div;
+    long k;
+    unsigned long SR_save, out_sr=0;
+    long a;
+    long b;
+    unsigned long clk168m;
+
+	clk168m = ak98_get_clk168m_clk(); 
+
+    max_div = 0x100;
+    SR_save = 0;
+    *osrindex = 0;
+    *mclkdiv = 0xff;
+    for(j=0; j<8; j++) //OSR index
+    {
+        for(k=max_div-1; k>=0; k--) //DAC_DIV value
+        {
+            out_sr = clk168m/(k+1);
+            if (out_sr > MAX_DACCLK)
+                break;
+            out_sr = out_sr/OSR_table[j];
+            a = out_sr-des_sr;
+            a = (a>0)? a : (-a);
+            b = SR_save-des_sr;
+            b = (b>0)? b : (-b);
+            if (a<b)
+            {
+                SR_save = out_sr;
+                *mclkdiv = k;
+                *osrindex = j;
+            }
+        }
+    }	
+}
+
+/**
+ * @brief   Set sample rate
+ * @author 
+ * @date   
+ * @param[in]  samplerate: desired sample rate
+ * @return  void
+ */
+void AK98_DAC_Set_SampleRate(unsigned long samplerate)
+{
+	unsigned char osr, mclkdiv;
+	DAC_GetOsrDiv(&osr, &mclkdiv, samplerate);
+
+	 // NOTE: should reset DAC!!!
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= (~DAC_RST);
+	mdelay(5);
+    //set OSR
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) &= (~ANALOG_CTRL4_OSR_MASK);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) |= (ANALOG_CTRL4_OSR(osr));
+	mdelay(2);
+
+    //set DIV
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= (~(MASK_CLKDIV2_DAC_DIV));
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= (CLKDIV2_DAC_DIV(mclkdiv));    
+	mdelay(2);
+
+    //to reset dac
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= DAC_RST;
+}
+
+/**
+ * @brief   Set DAC channels: mono,stereo
+ * @author 
+ * @date   
+ * @param[in]  bool mono: true-mono, false-stereo
+ * @return  void
+ */
+void AK98_DAC_Set_Channels(unsigned long chnl)
+{
+
+}
+
+static void SetHpDisChgCur(unsigned long value)
+{
+	int RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(0x7 << 27);
+	RegValue |= (value << 27);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+}
+
+static void SetPmosCur(unsigned long value)
+{
+	int RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(0xf << 23);
+	RegValue |= (value << 23);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+}
+
+static void SetVcm2DischgCur(unsigned long value)
+{
+	int RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~(0xf << 6);
+	RegValue |= (value << 6);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+}
+
+static void SetVcm2Cur(unsigned long value)
+{
+	int RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+	RegValue &= ~(0xf << 16);
+	RegValue |= (value << 16);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+}
+
+
+/**
+ * @brief   power on HP
+ * @author 
+ * @date   
+ * @param[in] bool poweron or poweroff
+ * @return  void
+ */
+void AK98_Poweron_HP(bool bOn)
+{
+	int RegValue;
+	printk("-------------------------- AK98_Poweron_HP %d\n",bOn);
+	if(bOn)
+	{
+		/*
+		* power on codec,power off vcm2/vcm3, pull down vcm2
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PD_REF);
+		RegValue |= PD_VCM2;
+		RegValue |= PD_VCM3;
+		RegValue |= PL_VCM2;
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		//mdelay(10);
+
+		/*
+		* Headphone discharging selection
+		*/
+		SetHpDisChgCur(0x0);
+		//mdelay(2);
+		SetHpDisChgCur(0x1);
+		//mdelay(2);
+		SetHpDisChgCur(0x3);
+		//mdelay(2);
+		SetHpDisChgCur(0x7);
+		//mdelay(2);
+
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PTM_D_CHG_EN);  //disable VCM2 discharing
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		
+		//disable to discharge the off-chip AC coupling capacitor
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(1<<27);  //disable VCM2 discharing
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(1<<28);  //disable VCM2 discharing
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(1<<29);  //disable VCM2 discharing
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		* to enable de-pipa noise control
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= PRE_EN1;
+		RegValue |= PRE_EN2;
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		* set hp gain
+		*/
+		//SetHpGain(0x1);
+
+		SetPmosCur(0x0);   //set headphone PMOS
+
+		/*
+		* power on HP
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PD1_HP);
+		RegValue &= ~(1<<23);
+		RegValue &= ~(1<<24);
+		RegValue &= ~(1<<25);
+		RegValue &= ~(1<<26);
+		RegValue &= ~(PD2_HP);
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		//mdelay(5);
+
+		/*
+		* charge PMOS
+		*/
+		SetPmosCur(0x0);
+		//mdelay(5);
+		SetPmosCur(0x8);
+		//mdelay(5);
+		SetPmosCur(0xb);
+		//mdelay(5);
+		SetPmosCur(0xe);
+		//mdelay(5);
+		SetPmosCur(0xf);
+		//mdelay(5);
+		//SetPmosCur(0x0);
+
+		/*
+		* to set VCM2 normal,  power on vcm2 vcm3
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PL_VCM2); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PD_VCM2); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PD_VCM3); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		*  charge VCM2
+		*/
+		SetVcm2Cur(0xf);
+		//mdelay(20);
+		SetVcm2Cur(0xe);
+		//mdelay(10);
+		SetVcm2Cur(0xd);
+		//mdelay(10);
+		SetVcm2Cur(0xc);
+		//mdelay(10);
+		SetVcm2Cur(0x7);
+		//mdelay(10);
+		SetVcm2Cur(0x8);
+		//mdelay(10);
+		SetVcm2Cur(0x6);
+		//mdelay(10);
+		SetVcm2Cur(0x3);
+		//mdelay(10);
+		SetVcm2Cur(0x4);
+		//mdelay(10);
+		SetVcm2Cur(0x2);
+		//mdelay(10);
+		SetVcm2Cur(0x1);
+		//mdelay(600);
+		SetVcm2Cur(0x0);
+
+		/*
+		*  select HP in
+		*/
+		// selectHPIn();
+		//setHPGain();
+	}
+	else
+	{
+		/*
+		* to set VCM2 normal
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PL_VCM2); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		//setHPGain();
+		//setHPMute();
+
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= PTM_D_CHG_EN;  //to enable VCM2 discharing
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		SetVcm2DischgCur(0x0);
+
+		/*
+		* power off vcm2,vcm3
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PD_VCM2); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PD_VCM3); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		* discharge vcm2
+		*/
+		SetVcm2DischgCur(0x1);
+		//mdelay(10);
+		SetVcm2DischgCur(0x3);
+		//mdelay(10);
+		SetVcm2DischgCur(0x7);
+		//mdelay(10);
+		SetVcm2DischgCur(0x8);
+		//mdelay(50);
+		SetVcm2DischgCur(0xf);
+		//mdelay(500);
+
+		/*
+		* pull down vcm2
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PL_VCM2); 
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		* power off HP
+		*/
+		SetPmosCur(0x0);
+		SetPmosCur(0xf);
+		//mdelay(5);
+		SetPmosCur(0xe);
+		//mdelay(5);
+		SetPmosCur(0xb);
+		//mdelay(5);
+		SetPmosCur(0x8);
+		//mdelay(5);
+		
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PD2_HP); //power off pmos
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		//mdelay(20);
+		SetHpDisChgCur(0x1);
+		//mdelay(2);
+		SetHpDisChgCur(0x3);
+		//mdelay(2);
+		SetHpDisChgCur(0x7);
+		//mdelay(50);
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PD1_HP); //power off nmos
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+		//mdelay(2);
+
+		/*
+		*  enable de-pipa
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= PRE_EN1;
+		RegValue |= PRE_EN2;
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		/*
+		* power off codec
+		*/
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue |= (PD_REF);
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief  set HP gain
+ * @author 
+ * @date   
+ * @param[in]  x: (0.x)times
+ * @return  void
+ */
+void AK98_Set_HPGain(unsigned long gain)
+{
+    unsigned long reg_value;
+    unsigned long gain_table[9] = {0x1ff,0xff,0x7f,0x3f,0x1f,0xf,0x7,0x3,0x1};
+    if(gain > HP_GAIN_MAX)
+    {
+    	gain = HP_GAIN_MAX;
+    }
+
+    reg_value = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+    reg_value &= ~(0x1FF << 23);
+    reg_value |= (gain_table[gain] << 23);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = reg_value;
+}
+
+/**
+ * @brief  select HP in signal
+ * @author 
+ * @date   
+ * @param[in]  (HP_In_Signal)signal: signal desired
+ * @return  void
+ */
+void AK98_Set_HP_In(unsigned long signal)
+{
+	unsigned long RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+    RegValue &= ~(0x7 << 12);
+    RegValue |= ((signal&0x7) << 12);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+}
+
+/**
+ * @brief  open ADC23
+ * @author 
+ * @date   
+ * @param[in]  void
+ * @return  void
+ */
+void AK98_ADC23_Open(void)
+{
+	unsigned long RegValue;
+	if(!ADC23_State)
+	{
+	ADC23_State = 1;
+	//reset ADC2 and ADC3
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~(ADC2_RST);
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= (ADC2_RST);
+
+	// soft reset ADC2 controller
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) |= (ADC2Ctrl_SOFT_RST);
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) &= ~(ADC2Ctrl_SOFT_RST);
+
+	SetPmosCur(0x0);  //must be set to 0 when ADC23 is working
+	
+	REG32(RegAddr.pAddress0800 + CLOCK_CTRL_REG1) &= ~(ADC2_CLK_CTRL_EN);//enable ADC23 Clock 
+	REG32(RegAddr.pAddress0800 + MULTIPLE_FUN_CTRL_REG1) |= (1 << 23); //enable internal
+	
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	RegValue &= ~PD_VCM3;                  //power on vcm3   
+    RegValue &= ~PD_VCM2;                  //power on vcm2  
+    RegValue &= ~PL_VCM2;                  //power on vcm2 
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) |= ADC2_CTRL_EN;
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) |= ADC2MODE_L2_EN;
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) &= ~HOST_RD_INT_EN;
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) |= CH_POLARITY_SEL;//Receive the left channel data when the lrclk is high
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) &= ~I2S_EN;        //Internal ADC MODE
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) &= ~WORD_LENGTH_MASK;
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) |= (0XF << 8);     //WORD LENGTH IS 16 BIT
+
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) |= (1 << 13);   //enable verf 
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) |= (1 << 12);   //choose rerf
+
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= (ADC2_CLK_EN);    //enable adc23 clock
+	REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~(ADC2_GATE);     //provide adc23 clock
+
+    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+    RegValue &= ~(1 << 5);                 //DisableVcm2Dischange
+    RegValue &= ~(1 << 4);                 //don't change ver fast
+    RegValue |= (0xf << 6);
+    RegValue &= ~(1 << 15);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+    mdelay(1);
+
+    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+    RegValue &= ~PD_REF;     //power on codec
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      close ADC23
+ * @author 
+ * @date   
+ * @param[in]    void 
+ * @return  void
+ */
+void AK98_ADC23_Close(void)
+{
+	unsigned long RegValue;
+	if(ADC23_State)
+	{
+	ADC23_State = 0;
+
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~ADC2_CLK_EN;     //disable ADC2 clk
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= (ADC2_GATE);     //inhabit adc23 clock
+    REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) &= ~ADC2_CTRL_EN; //disable ADC2 interface
+	REG32(RegAddr.pAddress2002D + ADC2MODE_CFG_REG) &= ~ADC2MODE_L2_EN;
+	
+    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+    RegValue |= (PD_ADC2 | PD_ADC3); 
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      set ADC23 mode and clk_div
+ * @author 
+ * @date   
+ * @param[in]    des_sr: desired rate to be set
+ * @param[out]  mode_sel: reg(0x08000064) bit[12]
+ * @param[out]  mclkdiv: reg(0x08000008) bit[11:4]
+ * @return  void
+ */
+static void ADC2_GetOsrDiv(unsigned char *mode_sel, unsigned char *mclkdiv, unsigned long des_sr)
+{
+	
+    unsigned short k, max_div;
+    unsigned short OSR_value=256;
+    unsigned long SR_save, out_sr=0;
+    signed long a, b;
+	unsigned long clk168m;
+	clk168m = ak98_get_clk168m_clk();
+
+    max_div = 0x100;
+    SR_save = 0;
+    *mode_sel = 0;
+    *mclkdiv = 0;
+
+    if (des_sr > 24000)
+    {
+        OSR_value = 256;
+        *mode_sel = 1; //48k mode
+    }
+    else
+    {
+        OSR_value = 512;
+        *mode_sel = 0; //16k mode
+    }
+    
+    for(k=0; k<max_div; k++) //DIV
+    {
+        out_sr = clk168m/(k+1)/OSR_value;
+        a = out_sr - des_sr;
+        a = (a>0)? a : (-a);
+        b = SR_save - des_sr;
+        b = (b>0)? b : (-b);
+        if (a<b)
+        {
+            SR_save = out_sr;
+            *mclkdiv = k;
+        }
+    }
+}
+
+/**
+ * @brief      set ADC23 sample rate
+ * @author 
+ * @date   
+ * @param[in]    samplerate:  desired rate to be set
+ * @return  void
+ */
+void AK98_ADC23_Set_SampleRate(unsigned long  samplerate)
+{
+	unsigned char mode_sel = 0;
+    unsigned char save_div = 0;
+
+	ADC2_GetOsrDiv(&mode_sel, &save_div, samplerate);
+
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) &= ~(MASK_CLKDIV2_ADC2_DIV);
+    REG32(RegAddr.pAddress0800 + CLK_DIV_REG2) |= CLKDIV2_ADC2_DIV(save_div);
+
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) &= ~(1 << ADC_OSR);
+    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG4) |= (mode_sel << ADC_OSR);
+}
+
+/**
+ * @brief      set ADC23 source
+ * @author 
+ * @date   
+ * @param[in]    signal:  DAC|LINEIN|MIC
+ * @return  void
+ */
+void AK98_Set_ADC23_In(unsigned long signal)
+{
+	unsigned long RegValue;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+	RegValue &= ~(0x7 << 2);
+	RegValue |= ((signal&0x7) << 2);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+}
+
+/**
+ * @brief      set ADC23 channel
+ * @author 
+ * @date   
+ * @param[in]    chnl: 1-mono; 2-stereo
+ * @return  void
+ */
+void AK98_ADC23_Set_Channels(unsigned long chnl)
+{
+	unsigned long RegValue = 0;	
+	switch(chnl)
+    {
+        case 1:
+			RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+			RegValue &= ~(1 << 20); 			   //power on adc2 conversion
+			RegValue |= (1 << 21); 			   //power off adc3 conversion
+			RegValue &= ~PD_ADC2;            //power on left channel
+			RegValue |= PD_ADC3;             //power off right channel
+			RegValue |= (1 << 5);				   //ADC2 limit function
+			RegValue &= ~(1 << 6);				   //disable ADC3 limit function
+			REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+        break;
+        case 2:
+        default:
+	        RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+			RegValue &= ~(1 << 20); 			   //power on adc2 conversion
+			RegValue &= ~(1 << 21); 			   //power on adc3 conversion
+			RegValue &= ~PD_ADC2;				   //power on adc2
+			RegValue &= ~PD_ADC3;				   //power on adc3
+			RegValue |= (1 << 5);				   //ADC2 limit function
+			RegValue |= (1 << 6);				   //ADC3 limit function
+			REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+        break;
+    }
+}
+
+/**
+ * @brief      set mic gain
+ * @author 
+ * @date   
+ * @param[in]    gain: 0~7
+ * @return  void
+ */
+void AK98_Set_MicGain(unsigned long gain)
+{
+	unsigned long RegValue = 0;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+	RegValue &= ~(0x7<<11);
+	RegValue |= ((gain&0x7)<<11);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+}
+
+/**
+ * @brief      set linein gain
+ * @author 
+ * @date   
+ * @param[in]    gain: 0~15
+ * @return  void
+ */
+void AK98_Set_LineinGain(unsigned long gain)
+{
+	unsigned long RegValue = 0;
+	RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+	RegValue &= ~(0xF<<7);
+	RegValue |= ((gain&0xF)<<7);
+	REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+}
+
+/**
+ * @brief      set linein interface power
+ * @author 
+ * @date   
+ * @param[in]    bTrue: 1-power on; 0-power off 
+ * @return  void
+ */
+void AK98_Linein_PowerOn(bool bOn)
+{
+	unsigned long RegValue = 0;
+	if(bOn)
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+	    RegValue &= ~(1 << 14); //power on left channel
+	    RegValue &= ~(1 << 15); //power on reght channel
+	    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+	}
+	else
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_READ);
+		RegValue |= (1 << 14); //power off left channel
+		RegValue |= (1 << 15); //power off reght channel
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG2_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      set DAC to lineout
+ * @author 
+ * @date   
+ * @param[in]    bTrue: 1-connet DACto lineout; 0-disconnect 
+ * @return  void
+ */
+void AK98_Mic_PowerOn(bool bOn)
+{
+ 	unsigned long RegValue = 0;
+	if(bOn)
+	{
+		//power on mic interface
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+        RegValue &= ~(0x3 << 21);  //power on differential mic
+        REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+	else
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+        RegValue |= (0x3 << 21);  //power off differential mic
+        REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      set DAC to lineout
+ * @author 
+ * @date   
+ * @param[in]    bTrue: 1-connet DACto lineout; 0-disconnect 
+ * @return  void
+ */
+void AK98_DAC_Bypass(bool bTrue)
+{
+	unsigned long RegValue = 0;
+	if(bTrue)
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+        RegValue &= ~(MUXDA_L | MUXDA_R);  //enable left/right channel of DAC out
+        REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+	else
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+        RegValue |= (MUXDA_L | MUXDA_R);  //disable left/right channel of DAC out
+        REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      set mic to lineout
+ * @author 
+ * @date   
+ * @param[in]    bTrue: 1-connet mic to lineout; 0-disconnect 
+ * @return  void
+ */
+void AK98_MicIn_Bypass(bool bTrue)
+{
+	unsigned long RegValue = 0;
+	if(bTrue)
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3);
+		RegValue |= (MICIN_BYPASS); //bypass mic in to lineout
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) = RegValue;
+	}
+	else
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3);
+		RegValue &= ~(MICIN_BYPASS);  //not bypass
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) = RegValue;
+	}
+}
+
+/**
+ * @brief      set linein to lineout
+ * @author 
+ * @date   
+ * @param[in]    bTrue: 1-connet linein to lineout; 0-disconnect 
+ * @return  void
+ */
+void AK98_LineIn_Bypass(bool bTrue)
+{
+	unsigned long RegValue = 0;
+	if(bTrue)
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3);
+		RegValue |= (LINEIN_BYPASS);   //bypass linein to lineout
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) = RegValue;
+	}
+	else
+	{
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3);
+		RegValue &= ~(LINEIN_BYPASS);  //not bypass
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG3) = RegValue;
+	}
+}
+
+/**
+ * @brief      set src to lineout
+ * @author 
+ * @date   
+ * @param[in]      src: DAC|LINEIN|MIC  
+ * @return  void
+ */
+void AK98_Set_Bypass(unsigned long src)
+{
+	bool s_DAC = src&(0x1);
+	bool s_Linein = src&(0x2);
+	bool s_Mic = src&(0x4);
+	AK98_DAC_Bypass(s_DAC);
+	AK98_LineIn_Bypass(s_Linein);
+	AK98_MicIn_Bypass(s_Mic);	
+}
+
+void AK98_Poweron_VCM_REF(bool bOn)
+{
+	unsigned long RegValue;
+	if(bOn)
+	{
+		//add power control here for MIC-to-Lineout channel
+		//power on REF
+		RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+		RegValue &= ~(PD_REF | PL_VCM2 );
+		//RegValue |= (PRE_EN1 | PRE_EN2 | TRIMP_HP | TRIMN_HP);
+		REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+		//power on vcm2/vcm3
+	    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	    RegValue &= ~(PD_VCM2 | PD_VCM3);
+	    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+	else
+	{
+		//power off vcm2/vcm3
+	    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	    RegValue |= (PD_VCM2);
+	    RegValue |= (PD_VCM3);           
+	    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+
+	    //power off codec
+	    RegValue = REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_READ);
+	    RegValue |= (PD_REF | PL_VCM2);
+	    REG32(RegAddr.pAddress0800 + ANALOG_CTRL_REG1_WRITE) = RegValue;
+	}
+}
+
+/**
+ * @brief      set input device power
+ * @author 
+ * @date   
+ * @param[in]      src: DAC|LINEIN|MIC  
+ *                       addr:route No.  
+ *                       CurSrc:all three route's current src
+ * @return  void
+ */
+void AK98_Set_SrcPower(int src,int addr,int *CurSrc)
+{
+	bool s_DAC = 0;
+	bool s_Linein = 0;
+	bool s_Mic = 0;
+	bool s_src = 0;
+
+	if(0==addr)
+	{
+		s_DAC = (src|CurSrc[1]|CurSrc[2])&(0x1);
+		s_Linein = (src|CurSrc[1]|CurSrc[2])&(0x2);
+		s_Mic = (src|CurSrc[1]|CurSrc[2])&(0x4);
+		
+	}
+	else if(1==addr)
+	{
+		s_DAC = (src|CurSrc[0]|CurSrc[2])&(0x1);
+		s_Linein = (src|CurSrc[0]|CurSrc[2])&(0x2);
+		s_Mic = (src|CurSrc[0]|CurSrc[2])&(0x4);
+	}
+	else if(2==addr)
+	{
+		s_DAC = (src|CurSrc[0]|CurSrc[1])&(0x1);
+		s_Linein = (src|CurSrc[0]|CurSrc[1])&(0x2);
+		s_Mic = (src|CurSrc[0]|CurSrc[1])&(0x4);
+	}
+	s_src = s_DAC|s_Linein|s_Mic;
+	AK98_Poweron_VCM_REF(s_src);
+	
+	//set DAC power in PCM interface function: ak98pcm_playback_prepare()
+	AK98_Linein_PowerOn(s_Linein);
+	AK98_Mic_PowerOn(s_Mic);
+}
+
+/**
+ * @brief   cfg shutdown speaker GPIO
+ * @author 
+ * @date   
+ * @param[in]  bOn: 1-power on; 0-power off
+ * @return  void
+ */
+void AK98_Poweron_Speaker(unsigned int pin, bool bOn)
+{
+	printk("-----------------------AK98_Poweron_Speaker %d\n",bOn);
+	ak98_setpin_as_gpio(pin);
+	ak98_gpio_cfgpin(pin, AK98_GPIO_DIR_OUTPUT);
+	ak98_gpio_setpin(pin, bOn);	
+}
diff --git a/sound/arm/ak98pcm.c b/sound/arm/ak98pcm.c
new file mode 100755
index 00000000000..5cf22a109b0
--- /dev/null
+++ b/sound/arm/ak98pcm.c
@@ -0,0 +1,1906 @@
+/*
+ *  ak98pcm soundcard
+ *  Copyright (c) by Anyka, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/time.h>
+#include <linux/wait.h>
+#include <linux/hrtimer.h>
+#include <linux/math64.h>
+#include <linux/moduleparam.h>
+#include <linux/completion.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/i2c/aw9523.h>
+#include <asm/bitops.h>
+#include <sound/core.h>
+#include <sound/control.h>
+#include <sound/tlv.h>
+#include <sound/pcm.h>
+#include <sound/rawmidi.h>
+#include <sound/info.h>
+#include <sound/initval.h>
+
+#include <mach/l2.h>
+
+#include <mach/ak98_hal.h>
+
+
+MODULE_AUTHOR("Anyka, Inc.");
+MODULE_DESCRIPTION("ak98pcm soundcard");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("{{ALSA,ak98pcm soundcard}}");
+
+#define MIXER_ADDR_HPVOL	            0
+#define MIXER_ADDR_LINEINVOL		    1
+#define MIXER_ADDR_MICVOL		        2
+#define MIXER_ADDR_LASTVOL              2
+
+#define MIXER_ADDR_HPSRC                0
+#define MIXER_ADDR_LINEOUTSRC           1
+#define MIXER_ADDR_ADC23SRC             2
+#define MIXER_ADDR_LASTSRC		        2
+
+#define MIXER_ADDR_HPDET                0
+#define MIXER_ADDR_SWITCH_LASTDET       0
+
+#define DEFAULT_HPVOL                   5
+#define DEFAULT_LINEINVOL               10
+#define DEFAULT_MICVOL                  6
+
+#define MIXER_ADDR_OUTMODE           0
+#define MIXER_ADDR_OUTMODE_LAST      0
+
+#define OUTMODE_AUTO                 0
+#define OUTMODE_HP                   1
+#define OUTMODE_LINEOUT              2
+#define OUTMODE_MIN                  OUTMODE_AUTO
+#define OUTMODE_MAX                  OUTMODE_LINEOUT
+
+#define MIXER_ADDR_CHNLDURATION      0
+#define MIXER_ADDR_CHNLDURATION_LAST 0
+
+#define CHNLDURATION_CONSTANT        0
+#define CHNLDURATION_EVEROPEN        1
+#define CHNLDURATION_MIN             CHNLDURATION_CONSTANT
+#define CHNLDURATION_MAX             CHNLDURATION_EVEROPEN
+
+struct snd_ak98pcm {
+	struct snd_card *card;
+	struct snd_pcm *pcm;
+	spinlock_t mixer_lock;
+	struct snd_pcm_substream *playbacksubstrm;
+	struct snd_pcm_substream *capturesubstrm;
+	struct completion playbackHWDMA_completion;
+	struct completion captureHWDMA_completion;
+	void __iomem  *AnalogCtrlRegs;
+	void __iomem  *I2SCtrlRegs;
+	void __iomem  *ADC2ModeCfgRegs;
+	u8   L2BufID_For_DAC;
+	u8   L2BufID_For_ADC23;
+	snd_pcm_uframes_t PlaybackCurrPos;
+	snd_pcm_uframes_t CaptureCurrPos;
+	unsigned long   playbackStrmDMARunning;//bit[0]:strm state(running or not). bit[1]:DMA state(running or finished)
+	unsigned long   captureStrmDMARunning;//bit[0]:strm state(running or not). bit[1]:DMA state(running or finished)
+	int mixer_volume[MIXER_ADDR_LASTVOL+1];
+	int mixer_source[MIXER_ADDR_LASTSRC+1];
+	int mixer_switch[MIXER_ADDR_SWITCH_LASTDET+1];
+	int mixer_OutMode[MIXER_ADDR_OUTMODE_LAST+1];
+	int mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION_LAST+1];
+	struct snd_kcontrol *ctl_switch;
+	int hp_det_irq;
+	int hp_on_value;
+	int irqType_for_hpOn;
+	int irqType_for_hpOff;
+	struct gpio_info hpdet_gpio;
+	struct gpio_info spkrshdn_gpio;
+	int hpmute_enable_value;
+	int hpmute_disable_value;
+	struct gpio_info hpmute_gpio;
+	int bIsHPmuteUsed; // whether to use hardware de-pipa or not
+	int bIsMetalFixed; // whether the chip DAC module has been fixed
+	struct delayed_work d_work;
+	struct work_struct stopoutput_work;
+	struct timer_list timer;
+};
+
+extern REG_ADDR RegAddr;
+struct captureSync{
+	unsigned long long adcCapture_bytes;
+	struct timeval tv;
+};
+
+struct captureSync capSync;
+
+/*************
+ * PCM interface
+ *************/
+
+#define USE_FORMATS 		(SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE)
+#define USE_RATE			(SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000)
+#define USE_RATE_MIN		5500
+#define USE_RATE_MAX		48000
+#define USE_CHANNELS_MIN 	2
+#define USE_CHANNELS_MAX 	2
+
+
+#define ak98pcm_playback_buf_bytes_max     (8*4096)
+#define ak98pcm_playback_period_bytes_min  4096
+#define ak98pcm_playback_periods_min       6
+#define ak98pcm_playback_periods_max       8
+
+#define ak98pcm_capture_buf_bytes_max      (10*4096)
+#define ak98pcm_capture_period_bytes_min   2048
+#define ak98pcm_capture_periods_min        1
+#define ak98pcm_capture_periods_max        10
+
+ /**
+ * @brief   tell camera driver the audio capture samples for AV sync 
+ * @author  
+ * @date   
+ * @input   void
+ * @output  void *
+ * @return  void
+ */
+void *getRecordSyncSamples(void)
+{
+	return &capSync;
+}
+
+/**
+ * @brief  config input signal and output channel
+ * @author  Cheng Mingjuan
+ * @date   
+ * @input  int addr: output channel
+               int src: input signal
+ * @return int
+ */
+//set source signal for both output channel(HP,speaker) and input channel(ADC23)
+static int set_channel_source(struct snd_ak98pcm *ak98pcm,int addr,int src)
+{
+	int change = 0;
+	change = (ak98pcm->mixer_source[addr]!= src);
+	if(change)
+	{
+		if(MIXER_ADDR_HPSRC == addr) //set hp channel src
+		{
+			ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_enable_value);
+			AK98_Poweron_HP((bool)src);
+			ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_disable_value);
+			AK98_Set_HP_In(src);
+			AK98_Set_SrcPower(src,addr,ak98pcm->mixer_source);
+		}
+		else if(MIXER_ADDR_LINEOUTSRC == addr)  //set lineout channel src
+		{
+			if(src)
+			{
+				AK98_Set_SrcPower(src,addr,ak98pcm->mixer_source);
+				AK98_Set_Bypass(src);
+				mdelay(500);
+			}
+			AK98_Poweron_Speaker(ak98pcm->spkrshdn_gpio.pin,(bool)src);
+			if(!src)
+			{
+				AK98_Set_Bypass(src);
+				AK98_Set_SrcPower(src,addr,ak98pcm->mixer_source);
+			}
+		}
+		else if(MIXER_ADDR_ADC23SRC ==addr)  //set ADC23 channel src
+		{
+			AK98_Set_SrcPower(src,addr,ak98pcm->mixer_source);
+			AK98_Set_ADC23_In(src);
+			/*set ADC23 poweron in PCM interface function: ak98pcm_capture_prepare()*/
+		}
+		else
+		{
+			printk("unsupport mixer addr!\n");
+			return -EINVAL;
+		}
+		ak98pcm->mixer_source[addr] = src;
+	}
+	return change;	
+}
+
+/*
+ * timer interrupt handler
+ *power off HP
+ */
+static void ak98pcm_timer_func(unsigned long data)
+{
+	struct snd_ak98pcm *ak98pcm = (struct snd_ak98pcm *)data;
+	int dstsrc = 0;
+	printk("---------------------------ak98pcm_timer_func\n");
+	dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] & (~SOURCE_DAC);
+	set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+}
+
+/**
+ * @brief  when playback stop, schedule stopOutput_work to close output channel
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static void stopOutput_work(struct work_struct *work)
+{
+	struct snd_ak98pcm *ak98pcm =
+		container_of(work, struct snd_ak98pcm, stopoutput_work);
+	int dstsrc = 0;
+
+	AK98_DAC_Close();
+	//if we want to open some channel for ever, return
+	if(ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION]==CHNLDURATION_EVEROPEN)
+		return 0;
+
+	//if we config output to hp, close hp channel
+	if(OUTMODE_HP == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		//printk("------------------delay 30s to close hp channel\n");
+		//ak98pcm->timer.expires = jiffies + 30*HZ;
+		//add_timer(&ak98pcm->timer);
+		printk("------------------close hp channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] & (~SOURCE_DAC);
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+	}
+	//if we config output to lineout, close lineout channel
+	else if(OUTMODE_LINEOUT == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		printk("------------------close lineout channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] & (~SOURCE_DAC);
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+	}
+	//we want auto change, close hp/speaker channel
+	else
+	{
+		if(ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION]==CHNLDURATION_CONSTANT)
+		{
+			if(ak98pcm->mixer_switch[MIXER_ADDR_HPDET])  //headset plug in, select headset for output
+			{
+				//printk("------------------delay 30s to close hp channel\n");
+				//ak98pcm->timer.expires = jiffies + 30*HZ;
+				//add_timer(&ak98pcm->timer);
+				printk("------------------close hp channel\n");
+				dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] & (~SOURCE_DAC);
+				set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);	
+			}
+			else if(!ak98pcm->mixer_switch[MIXER_ADDR_HPDET])  //headset pull out, select speaker for output
+			{
+				printk("------------------close lineout channel\n");
+				dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] & (~SOURCE_DAC);
+				set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+			}
+		}
+	}
+	// close all channels
+	dstsrc = ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC] & (~SOURCE_DAC);
+	set_channel_source(ak98pcm,MIXER_ADDR_ADC23SRC,dstsrc);
+}
+
+
+/**
+ * @brief  DMA transfer for playback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+void ak98pcm_playback_interrupt(unsigned long data)
+{
+	struct snd_ak98pcm *ak98pcm = (struct snd_ak98pcm *)data;
+	struct snd_pcm_substream *substream = ak98pcm->playbacksubstrm;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	dma_addr_t paddr = runtime->dma_addr;
+	u8 id = ak98pcm->L2BufID_For_DAC;
+	unsigned long period_bytes = 0;
+	unsigned long buffer_bytes = 0;
+
+	period_bytes = frames_to_bytes(runtime,runtime->period_size);
+	buffer_bytes = frames_to_bytes(runtime,runtime->buffer_size);
+	ak98pcm->PlaybackCurrPos += period_bytes;
+	if(ak98pcm->PlaybackCurrPos >= buffer_bytes)
+	{
+		ak98pcm->PlaybackCurrPos = 0;
+	}
+	snd_pcm_period_elapsed(substream);
+	if(test_bit(0,&ak98pcm->playbackStrmDMARunning))//output stream is running
+	{
+		//printk(KERN_ERR "begin next dma");
+		ak98_l2_combuf_dma(paddr+ak98pcm->PlaybackCurrPos, id, ak98pcm_playback_period_bytes_min, 
+			(ak98_l2_dma_transfer_direction_t)MEM2BUF,1);
+	}
+	else //output strm has been stopped
+	{
+		printk("output stream stopped\n");
+		clear_bit(1,&ak98pcm->playbackStrmDMARunning); //DMA has finished
+		complete(&(ak98pcm->playbackHWDMA_completion));
+		schedule_work(&ak98pcm->stopoutput_work);
+	}
+}
+
+/**
+ * @brief  DMA transfer for capture
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+void ak98pcm_capture_interrupt(unsigned long data)
+{
+	struct snd_ak98pcm *ak98pcm = (struct snd_ak98pcm *)data;
+	struct snd_pcm_substream *substream = ak98pcm->capturesubstrm;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	dma_addr_t paddr = runtime->dma_addr;
+	u8 id = ak98pcm->L2BufID_For_ADC23;
+	int hpsrc=0,lineoutsrc=0,ADC23src=0;
+	
+	unsigned long period_bytes = 0;
+	unsigned long buffer_bytes = 0;
+	period_bytes = frames_to_bytes(runtime,runtime->period_size);
+	buffer_bytes = frames_to_bytes(runtime,runtime->buffer_size);
+	do_gettimeofday(&capSync.tv);
+	capSync.adcCapture_bytes += period_bytes;
+	ak98pcm->CaptureCurrPos += period_bytes;
+	if(ak98pcm->CaptureCurrPos >= buffer_bytes)
+	{
+		ak98pcm->CaptureCurrPos = 0;
+	}
+	snd_pcm_period_elapsed(substream);
+	if(test_bit(0,&ak98pcm->captureStrmDMARunning)) //input stream is running
+	{
+		//printk(KERN_ERR "begin next dma");
+		ak98_l2_combuf_dma(paddr+ak98pcm->CaptureCurrPos, id, ak98pcm_capture_period_bytes_min, 
+			(ak98_l2_dma_transfer_direction_t)BUF2MEM,1);
+	}
+	else  //input stream has been stopped
+	{
+		printk("input stream stopped\n");
+		clear_bit(1,&ak98pcm->captureStrmDMARunning);
+		complete(&(ak98pcm->captureHWDMA_completion));
+		AK98_ADC23_Close();
+		hpsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC];
+		lineoutsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC];
+		ADC23src = ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC];
+		if(SOURCE_MIC==ADC23src)
+		{
+			if((0==(hpsrc&SOURCE_MIC))&&(0==(lineoutsrc&SOURCE_MIC)))
+			{
+				AK98_Mic_PowerOn(0);//power off mic
+			}
+			AK98_Set_ADC23_In(0);  //clear adc23 src
+			ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC] = 0;
+			if((0==hpsrc)&&((0==lineoutsrc)||(SOURCE_LINEIN==lineoutsrc)))
+			{
+				AK98_Poweron_VCM_REF(0);
+			}
+		}
+	}
+}
+
+/**
+ * @brief  trigger callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	{
+		dma_addr_t paddr = runtime->dma_addr;
+		u8 id = ak98pcm->L2BufID_For_DAC;
+		del_timer(&ak98pcm->timer);
+		set_bit(0,&ak98pcm->playbackStrmDMARunning);  //set bit to inform that playback stream is running
+		set_bit(1,&ak98pcm->playbackStrmDMARunning);   //set bit to inform that DMA is working
+		init_completion(&(ak98pcm->playbackHWDMA_completion));
+		ak98_l2_clr_status(id);
+		ak98_l2_combuf_dma(paddr, id, ak98pcm_playback_period_bytes_min, 
+			(ak98_l2_dma_transfer_direction_t)MEM2BUF,1);//start dma
+		return 0;
+	}
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+		clear_bit(0,&ak98pcm->playbackStrmDMARunning); //stop playback stream
+		return 0;
+	}
+	return -EINVAL;
+}
+
+/**
+ * @brief  trigger callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	{
+		dma_addr_t paddr = runtime->dma_addr;
+		u8 id = ak98pcm->L2BufID_For_ADC23;
+		set_bit(0,&ak98pcm->captureStrmDMARunning);  //set bit to inform that capture stream is running
+		set_bit(1,&ak98pcm->captureStrmDMARunning);  //set bit to inform that DMA is working
+		init_completion(&(ak98pcm->captureHWDMA_completion));
+		ak98_l2_clr_status(id);		
+		ak98_l2_combuf_dma(paddr, id, ak98pcm_capture_period_bytes_min, 
+			(ak98_l2_dma_transfer_direction_t)BUF2MEM,1); //start dma
+		return 0;	
+	}
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+		clear_bit(0,&ak98pcm->captureStrmDMARunning); //stop capture stream
+		return 0;		
+	}
+	return -EINVAL;
+}
+
+/**
+ * @brief  prepare callback,open DAC, power on hp/speaker
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_prepare(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int dstsrc = 0;
+	if(test_bit(1,&ak98pcm->playbackStrmDMARunning))
+	{
+		wait_for_completion(&(ak98pcm->playbackHWDMA_completion));
+	}
+	cancel_work_sync(&ak98pcm->stopoutput_work);
+	ak98_l2_set_dma_callback(ak98pcm->L2BufID_For_DAC,ak98pcm_playback_interrupt,(unsigned long)ak98pcm);
+
+	ak98pcm->PlaybackCurrPos = 0;
+	AK98_DAC_Set_SampleRate(runtime->rate);
+	AK98_DAC_Open();
+	//if we want to open some channel for ever, return
+	if(ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION]==CHNLDURATION_EVEROPEN)
+	{
+		return 0;
+	}
+
+	//if we config output to hp, open hp channel
+	if(OUTMODE_HP == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		printk("--------------prepare hp channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] | SOURCE_DAC;
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+	}
+	//if we config output to lineout, open lineout channel
+	else if(OUTMODE_LINEOUT == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		printk("--------------prepare lineout channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] | SOURCE_DAC;
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+	}
+	else   // open hp/speaker channel according to hp state
+	{
+		if(ak98pcm->mixer_switch[MIXER_ADDR_HPDET])  //hp persent, select hp for output
+		{
+			printk("--------------prepare hp channel\n");
+			dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] | SOURCE_DAC;
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+		}
+		else if(!ak98pcm->mixer_switch[MIXER_ADDR_HPDET])//hp not persent, select speaker for output
+		{
+			printk("--------------prepare lineout channel\n");
+			dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] | SOURCE_DAC;
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * @brief  prepare callback,open ADC23, power on mic
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_prepare(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	int hpsrc=0,lineoutsrc=0,ADC23src=0;
+
+	ak98_l2_set_dma_callback(ak98pcm->L2BufID_For_ADC23,ak98pcm_capture_interrupt,(unsigned long)ak98pcm);
+	do_gettimeofday(&capSync.tv);
+	capSync.adcCapture_bytes = 0;
+	ak98pcm->CaptureCurrPos = 0;
+	AK98_ADC23_Set_SampleRate(runtime->rate);
+	AK98_ADC23_Set_Channels(runtime->channels);
+	AK98_ADC23_Open();   //open ADC23
+	hpsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC];
+	lineoutsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC];
+	ADC23src = ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC];
+	if(0==ADC23src)
+	{
+		AK98_Mic_PowerOn(1);  //power on mic
+		AK98_Set_ADC23_In(SOURCE_MIC);
+		ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC] = SOURCE_MIC;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief  pointer callback,updata ringbuffer pointer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static snd_pcm_uframes_t ak98pcm_playback_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	return(bytes_to_frames(runtime,ak98pcm->PlaybackCurrPos)); //updata ringbuffer pointer	
+}
+
+/**
+ * @brief  pointer callback, updata ringbuffer pointer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static snd_pcm_uframes_t ak98pcm_capture_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	return(bytes_to_frames(runtime,ak98pcm->CaptureCurrPos)); //updata ringbuffer pointer
+}
+
+static struct snd_pcm_hardware ak98pcm_playback_hardware = {
+	.info =			(SNDRV_PCM_INFO_MMAP |
+				 SNDRV_PCM_INFO_INTERLEAVED |
+				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
+				 SNDRV_PCM_INFO_RESUME |
+				 SNDRV_PCM_INFO_MMAP_VALID),
+	.formats =		USE_FORMATS,
+	.rates =		USE_RATE,
+	.rate_min =		USE_RATE_MIN,
+	.rate_max =		USE_RATE_MAX,
+	.channels_min =		USE_CHANNELS_MIN,
+	.channels_max =		USE_CHANNELS_MAX,
+	.buffer_bytes_max =	ak98pcm_playback_buf_bytes_max,
+	.period_bytes_min =	ak98pcm_playback_period_bytes_min,
+	.period_bytes_max =	ak98pcm_playback_period_bytes_min,
+	.periods_min =		ak98pcm_playback_periods_min,
+	.periods_max =		ak98pcm_playback_periods_max,
+	.fifo_size =		0,
+};
+
+static struct snd_pcm_hardware ak98pcm_capture_hardware = {
+	.info =			(SNDRV_PCM_INFO_MMAP |
+				 SNDRV_PCM_INFO_INTERLEAVED |
+				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
+				 SNDRV_PCM_INFO_RESUME |
+				 SNDRV_PCM_INFO_MMAP_VALID),
+	.formats =		USE_FORMATS,
+	.rates =		USE_RATE,
+	.rate_min =		USE_RATE_MIN,
+	.rate_max =		USE_RATE_MAX,
+	.channels_min =		USE_CHANNELS_MIN,
+	.channels_max =		USE_CHANNELS_MAX,
+	.buffer_bytes_max =	ak98pcm_capture_buf_bytes_max,
+	.period_bytes_min =	ak98pcm_capture_period_bytes_min,
+	.period_bytes_max =	ak98pcm_capture_period_bytes_min,
+	.periods_min =		ak98pcm_capture_periods_min,
+	.periods_max =		ak98pcm_capture_periods_max,
+	.fifo_size =		0,
+};
+
+/**
+ * @brief  hw_params callback, malloc ringbuffer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_hw_params(struct snd_pcm_substream *substream,
+			       struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	if(BUF_NULL==ak98pcm->L2BufID_For_DAC)
+	{
+		ak98pcm->L2BufID_For_DAC = ak98_l2_alloc((ak98_l2_device_t)ADDR_DAC); //alloc l2 buffer for DAC	
+		if(BUF_NULL==ak98pcm->L2BufID_For_DAC)
+		{
+			printk(KERN_ERR "alloc L2 buffer for DAC error!");
+			return -ENOMEM;
+		}
+	}
+	return(snd_pcm_lib_malloc_pages(substream,
+					params_buffer_bytes(hw_params)));
+}
+
+/**
+ * @brief  hw_params callback, malloc ringbuffer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_hw_params(struct snd_pcm_substream *substream,
+			       struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	if(BUF_NULL==ak98pcm->L2BufID_For_ADC23)
+	{
+		ak98pcm->L2BufID_For_ADC23 = ak98_l2_alloc((ak98_l2_device_t)ADDR_ADC); //alloc l2 buffer for ADC23	
+		if(BUF_NULL==ak98pcm->L2BufID_For_ADC23)
+		{
+			printk(KERN_ERR "alloc L2 buffer for DAC error!");
+			return -ENOMEM;
+		}
+	}
+	return(snd_pcm_lib_malloc_pages(substream,
+					params_buffer_bytes(hw_params)));
+}
+
+/**
+ * @brief  hw_free callback, free ringbuffer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_hw_free(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	
+	if(test_bit(1,&ak98pcm->playbackStrmDMARunning))
+	{
+		wait_for_completion(&(ak98pcm->playbackHWDMA_completion));
+	}
+	if(BUF_NULL!=ak98pcm->L2BufID_For_DAC)
+	{
+		AK98_DAC_Close();
+		ak98_l2_free((ak98_l2_device_t)ADDR_DAC);
+		ak98pcm->L2BufID_For_DAC = BUF_NULL;
+	}
+	return snd_pcm_lib_free_pages(substream);
+}
+
+/**
+ * @brief  hw_free callback, free ringbuffer
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_hw_free(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	
+	if(test_bit(1,&ak98pcm->captureStrmDMARunning))
+	{
+		wait_for_completion(&(ak98pcm->captureHWDMA_completion));
+	}
+	if(BUF_NULL!=ak98pcm->L2BufID_For_ADC23)
+	{
+		AK98_ADC23_Close();
+		ak98_l2_free((ak98_l2_device_t)ADDR_ADC);
+		ak98pcm->L2BufID_For_ADC23 = BUF_NULL;
+	}
+	return(snd_pcm_lib_free_pages(substream));	
+}
+
+/**
+ * @brief  open callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_open(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	ak98pcm->playbacksubstrm = substream;
+	runtime->hw = ak98pcm_playback_hardware;
+	ak98pcm->PlaybackCurrPos = 0;
+
+	return 0;
+}
+
+/**
+ * @brief  open callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_open(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	
+	ak98pcm->capturesubstrm = substream;
+	runtime->hw = ak98pcm_capture_hardware;	
+	ak98pcm->CaptureCurrPos = 0;
+	
+	return 0;
+}
+
+/**
+ * @brief  close callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_playback_close(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+
+	ak98pcm->playbacksubstrm=NULL;
+	return 0;
+}
+
+/**
+ * @brief  close callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_capture_close(struct snd_pcm_substream *substream)
+{
+	struct snd_ak98pcm *ak98pcm = snd_pcm_substream_chip(substream);
+	capSync.adcCapture_bytes = 0;
+	ak98pcm->capturesubstrm=NULL;
+	return 0;
+}
+
+/**
+ * @brief  mmap callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int ak98pcm_pcm_mmap(struct snd_pcm_substream *substream,
+	struct vm_area_struct *vma)
+{
+	return remap_pfn_range(vma, vma->vm_start,
+		       substream->dma_buffer.addr >> PAGE_SHIFT,
+		       vma->vm_end - vma->vm_start, vma->vm_page_prot);
+}
+
+
+static struct snd_pcm_ops ak98pcm_playback_ops = {
+	.open =		ak98pcm_playback_open,
+	.close =	ak98pcm_playback_close,
+	.ioctl =	snd_pcm_lib_ioctl,
+	.hw_params =	ak98pcm_playback_hw_params,
+	.hw_free =	ak98pcm_playback_hw_free,
+	.prepare =	ak98pcm_playback_prepare,
+	.trigger =	ak98pcm_playback_trigger,
+	.pointer =	ak98pcm_playback_pointer,
+	.mmap =	    ak98pcm_pcm_mmap,
+};
+
+static struct snd_pcm_ops ak98pcm_capture_ops = {
+	.open =		ak98pcm_capture_open,
+	.close =	ak98pcm_capture_close,
+	.ioctl =	snd_pcm_lib_ioctl,
+	.hw_params =	ak98pcm_capture_hw_params,
+	.hw_free =	ak98pcm_capture_hw_free,
+	.prepare =	ak98pcm_capture_prepare,
+	.trigger =	ak98pcm_capture_trigger,
+	.pointer =	ak98pcm_capture_pointer,
+	.mmap =	    ak98pcm_pcm_mmap,
+};
+
+/**
+ * @brief  create new card
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int __devinit snd_card_ak98pcm_pcm(struct snd_ak98pcm *ak98pcm, int device,
+					int substreams)
+{
+	struct snd_pcm *pcm;
+	int err;
+	err = snd_pcm_new(ak98pcm->card, "ak98pcm PCM", device,
+			       substreams, substreams, &pcm);
+	if (err < 0)
+		return err;
+	ak98pcm->pcm = pcm;
+	
+	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &ak98pcm_playback_ops); //register callbacks
+	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &ak98pcm_capture_ops);//register callbacks
+	pcm->private_data = ak98pcm;
+	pcm->info_flags = 0;
+	strcpy(pcm->name, "ak98pcm PCM");
+
+	snd_pcm_lib_preallocate_pages_for_all(pcm,
+			SNDRV_DMA_TYPE_DEV,
+			ak98pcm->card->dev,
+			ak98pcm_playback_periods_max*ak98pcm_playback_period_bytes_min,
+			ak98pcm_playback_buf_bytes_max); //malloc ringbuffer
+	return 0;
+}
+
+
+/**************
+ * mixer interface
+ **************/
+
+
+/**********************HPDet switch**************************/
+
+/**
+ * @brief  when hp state is changed,schedule hpDet_wq_work to config output \
+               channel to speaker or not
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static void hpDet_wq_work(struct work_struct *work)
+{
+	struct snd_ak98pcm *ak98pcm = container_of(work, struct snd_ak98pcm,d_work.work);
+	int hpsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC];
+	int spksrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC];
+	int dstsrc = hpsrc | spksrc;
+	if(!test_bit(0,&ak98pcm->playbackStrmDMARunning))
+	{
+		dstsrc &= ~SOURCE_DAC;
+	}
+	if(ak98pcm->mixer_switch[MIXER_ADDR_HPDET])  //headset plug in, select headset for output
+	{
+		if(CHNLDURATION_EVEROPEN == ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION])
+		{
+			dstsrc |= SOURCE_DAC;
+		}
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+	}
+	else  //headset pull out, select speaker for output
+	{
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+		if((dstsrc&SOURCE_DAC)&&(!test_bit(0,&ak98pcm->playbackStrmDMARunning)))
+		{
+			dstsrc &= (~SOURCE_DAC);
+		}
+		if(CHNLDURATION_EVEROPEN == ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION])
+		{
+			dstsrc |= SOURCE_DAC;
+		}
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+	}
+}
+
+/**
+ * @brief  hp det
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static irqreturn_t ak98pcm_HPDet_interrupt(int irq, void *dev_id)
+{
+	struct snd_card *card = dev_id;
+	struct snd_ak98pcm *ak98pcm = card->private_data;
+
+	if(ak98_gpio_getpin(ak98pcm->hpdet_gpio.pin) == ak98pcm->hp_on_value)
+	{
+		//hp is plugged in
+		ak98pcm->mixer_switch[MIXER_ADDR_HPDET] = 1;
+		set_irq_type(ak98pcm->hp_det_irq, ak98pcm->irqType_for_hpOff);
+		printk("-------------- hp on\n");
+	}
+	else
+	{
+		//hp is pulled out
+		ak98pcm->mixer_switch[MIXER_ADDR_HPDET] = 0;
+		set_irq_type(ak98pcm->hp_det_irq, ak98pcm->irqType_for_hpOn);
+		printk("-------------- hp off\n");
+	}
+	snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE,&ak98pcm->ctl_switch->id);
+	if(ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE] != OUTMODE_AUTO)
+		return IRQ_HANDLED;
+#ifdef CONFIG_SPKHP_SWITCH_AUTO
+	schedule_delayed_work(&ak98pcm->d_work, msecs_to_jiffies(100));
+#endif
+	return IRQ_HANDLED;
+}
+
+/***********************config channel duration*******************************/
+#define AK98PCM_OUTPUTCHNL_DURATION(xname, xindex, addr) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+  .name = xname, .index = xindex, \
+  .info = snd_ak98pcm_ChnlDuration_info, \
+  .get = snd_ak98pcm_ChnlDuration_get, \
+  .put = snd_ak98pcm_ChnlDuration_put, \
+  .private_value = addr \
+}
+
+/**
+ * @brief  info callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_ChnlDuration_info(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_info *uinfo)
+{
+	int addr = kcontrol->private_value;
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	if(MIXER_ADDR_CHNLDURATION == addr)
+	{
+		uinfo->value.integer.min = CHNLDURATION_MIN;
+		uinfo->value.integer.max = CHNLDURATION_MAX;
+	}
+	else
+	{
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief  get callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_ChnlDuration_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	if(addr != MIXER_ADDR_CHNLDURATION)
+	{
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] = ak98pcm->mixer_ChnlDuration[addr];
+	return 0;
+}
+
+/**
+ * @brief  put callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_ChnlDuration_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	int duration = ucontrol->value.integer.value[0];
+	int dstsrc = 0;
+	printk("-------------snd_ak98pcm_ChnlDuration_put duration=%d\n",duration);
+	if(duration == ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION])
+	{
+		return 0;
+	}
+	if(addr != MIXER_ADDR_CHNLDURATION)
+	{
+		return -EINVAL;
+	}
+	if((duration > CHNLDURATION_MAX)||(duration < CHNLDURATION_MIN))
+	{
+		return -EINVAL;
+	}
+	ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION] = duration;
+	if(CHNLDURATION_CONSTANT == duration)
+	{
+		if(!test_bit(0,&ak98pcm->playbackStrmDMARunning))
+		{
+			dstsrc =ak98pcm->mixer_source[MIXER_ADDR_HPSRC] & (~SOURCE_DAC);
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+			dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] & (~SOURCE_DAC);
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+		}
+		return 0;
+	}
+	
+	if(OUTMODE_HP == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		printk("--------------prepare hp channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] | SOURCE_DAC;
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+	}
+	else if(OUTMODE_LINEOUT == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		printk("--------------prepare lineout channel\n");
+		dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] | SOURCE_DAC;
+		set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+		set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+	}
+	else
+	{
+		if(ak98pcm->mixer_switch[MIXER_ADDR_HPDET])  //hp persent, select hp for output
+		{
+			printk("--------------prepare hp channel\n");
+			dstsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC] | SOURCE_DAC;
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+		}
+		else if(!ak98pcm->mixer_switch[MIXER_ADDR_HPDET])//hp not persent, select speaker for output
+		{
+			printk("--------------prepare lineout channel\n");
+			dstsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] | SOURCE_DAC;
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+		}
+	}
+	return 0;
+}
+
+/*********************select fixed output channel**********************************/
+#define AK98PCM_DAC_OUT_MODE(xname, xindex, addr) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+  .name = xname, .index = xindex, \
+  .info = snd_ak98pcm_DACOutMode_info, \
+  .get = snd_ak98pcm_DACOutMode_get, \
+  .put = snd_ak98pcm_DACOutMode_put, \
+  .private_value = addr \
+}
+
+/**
+ * @brief  info callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_DACOutMode_info(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_info *uinfo)
+{
+	int addr = kcontrol->private_value;
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	if(MIXER_ADDR_OUTMODE == addr)
+	{
+		uinfo->value.integer.min = OUTMODE_MIN;
+		uinfo->value.integer.max = OUTMODE_MAX;
+	}
+	else
+	{
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief  get callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_DACOutMode_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	if(addr != MIXER_ADDR_OUTMODE)
+	{
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] = ak98pcm->mixer_OutMode[addr];
+	return 0;
+}
+
+/**
+ * @brief  put callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_DACOutMode_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	int mode = ucontrol->value.integer.value[0];
+	int dstsrc = 0;
+	int tempsrc = 0;
+	printk("-------------snd_ak98pcm_DACOutMode_put mode=%d\n",mode);
+	if(mode == ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE])
+	{
+		return 0;
+	}
+	if(addr != MIXER_ADDR_OUTMODE)
+	{
+		return -EINVAL;
+	}
+	if((mode > OUTMODE_MAX)||(mode < OUTMODE_MIN))
+	{
+		mode = OUTMODE_AUTO;
+	}
+	switch(mode)
+	{
+		case OUTMODE_HP:
+			tempsrc = ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC];
+			set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,0);
+			if(tempsrc)
+			{
+				set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,tempsrc);
+			}
+
+			if(ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION]==CHNLDURATION_EVEROPEN)
+			{
+				dstsrc =ak98pcm->mixer_source[MIXER_ADDR_HPSRC]| SOURCE_DAC;
+				set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,dstsrc);
+			}
+			break;
+		case OUTMODE_LINEOUT:
+			tempsrc = ak98pcm->mixer_source[MIXER_ADDR_HPSRC];
+			set_channel_source(ak98pcm,MIXER_ADDR_HPSRC,0);
+			if(tempsrc)
+			{
+				set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,tempsrc);
+			}
+
+			if(ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION]==CHNLDURATION_EVEROPEN)
+			{
+				dstsrc =ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC]| SOURCE_DAC;
+				set_channel_source(ak98pcm,MIXER_ADDR_LINEOUTSRC,dstsrc);
+			}
+			break;
+		case OUTMODE_AUTO:
+		default:
+			schedule_delayed_work(&ak98pcm->d_work, msecs_to_jiffies(100));
+			break;
+	}
+	ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE] = mode;
+	return 0;
+}
+
+/**********************hp detect (read-only)****************************/
+#define AK98PCM_SWITCH(xname, xindex, addr) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
+  .name = xname, .index = xindex, \
+  .info = snd_ak98pcm_switch_info, \
+  .get = snd_ak98pcm_switch_get, \
+  .private_value = addr \
+}
+
+/**
+ * @brief  info callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_switch_info(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_info *uinfo)
+{
+	int addr = kcontrol->private_value;
+	if(MIXER_ADDR_HPDET != addr)
+	{
+		return -EINVAL;
+	}
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;		
+	return 0;
+}
+
+/**
+ * @brief  get callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_switch_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	if(MIXER_ADDR_HPDET != addr)
+	{
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] = ak98pcm->mixer_switch[addr];
+	return 0;
+}
+
+/***************************VOLUME*********************/
+#define AK98PCM_VOLUME(xname, xindex, addr) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+  .name = xname, .index = xindex, \
+  .info = snd_ak98pcm_volume_info, \
+  .get = snd_ak98pcm_volume_get, \
+  .put = snd_ak98pcm_volume_put, \
+  .private_value = addr \
+}
+
+/**
+ * @brief  info callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_volume_info(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_info *uinfo)
+{
+	int addr = kcontrol->private_value;
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	if(MIXER_ADDR_HPVOL == addr)
+	{
+		uinfo->value.integer.min = HEADPHONE_GAIN_MIN;
+		uinfo->value.integer.max = HEADPHONE_GAIN_MAX;
+	}
+	else if(MIXER_ADDR_LINEINVOL == addr)
+	{
+		uinfo->value.integer.min = LINEIN_GAIN_MIN;
+		uinfo->value.integer.max = LINEIN_GAIN_MAX;
+	}
+	else if(MIXER_ADDR_MICVOL == addr)
+	{
+		uinfo->value.integer.min = MIC_GAIN_MIN;
+		uinfo->value.integer.max = MIC_GAIN_MAX;
+	}
+	else
+	{
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief  get callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_volume_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	if(addr > MIXER_ADDR_LASTVOL)
+	{
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] = ak98pcm->mixer_volume[addr];
+	return 0;
+}
+
+/**
+ * @brief  put callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_volume_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	int vol = 0;
+	int change = 0;
+
+	vol = ucontrol->value.integer.value[0];
+	if(MIXER_ADDR_HPVOL == addr)
+	{
+		if(vol < HEADPHONE_GAIN_MIN)
+		{
+			vol = HEADPHONE_GAIN_MIN;
+		}
+		if(vol > HEADPHONE_GAIN_MAX)
+		{
+			vol = HEADPHONE_GAIN_MAX;
+		}
+
+		change = (ak98pcm->mixer_volume[addr] != vol);
+		if(change)
+		{
+			AK98_Set_HPGain(vol);
+		}
+		ak98pcm->mixer_volume[addr] = vol;
+	}
+	else if(MIXER_ADDR_LINEINVOL == addr)
+	{
+		if(vol < LINEIN_GAIN_MIN)
+		{
+			vol = LINEIN_GAIN_MIN;
+		}
+		if(vol > LINEIN_GAIN_MAX)
+		{
+			vol = LINEIN_GAIN_MAX;
+		}
+
+		change = (ak98pcm->mixer_volume[addr] != vol);
+		if(change)
+		{
+			AK98_Set_LineinGain(vol);
+		}
+		ak98pcm->mixer_volume[addr] = vol;
+	}
+	else if(MIXER_ADDR_MICVOL == addr)
+	{
+		if(vol < MIC_GAIN_MIN)
+		{
+			vol = MIC_GAIN_MIN;
+		}
+		if(vol > MIC_GAIN_MAX)
+		{
+			vol = MIC_GAIN_MAX;
+		}
+
+		change = (ak98pcm->mixer_volume[addr] != vol);
+		if(change)
+		{
+			AK98_Set_MicGain(vol);
+		}
+		ak98pcm->mixer_volume[addr] = vol;
+	}
+	else
+	{
+		return -EINVAL;
+	}
+
+	return change;
+}
+
+/***************************ROUTE**************************/
+#define AK98PCM_ROUTE(xname, xindex, addr) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \
+  .name = xname, \
+  .index = xindex, \
+  .info = snd_ak98pcm_route_info, \
+  .get = snd_ak98pcm_route_get, \
+  .put = snd_ak98pcm_route_put, \
+  .private_value = addr \
+}
+
+/**
+ * @brief  info callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_route_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	int addr = kcontrol->private_value;
+	if(addr > MIXER_ADDR_LASTSRC)
+	{
+		return -EINVAL;
+	}
+	
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = SIGNAL_SRC_MAX;
+	return 0;
+}
+
+/**
+ * @brief  get callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98pcm_route_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int addr = kcontrol->private_value;
+	if(addr > MIXER_ADDR_LASTSRC)
+	{
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] = ak98pcm->mixer_source[addr];
+	return 0;
+}
+
+/**
+ * @brief  put callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+/*application has to call this callback with params value=0 to power down input&output devices*/
+static int snd_ak98pcm_route_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_ak98pcm *ak98pcm = snd_kcontrol_chip(kcontrol);
+	int change, addr = kcontrol->private_value;
+	int src = 0;
+
+	src = ucontrol->value.integer.value[0];
+	if(src < SIGNAL_SRC_MUTE)
+	{
+		src = SIGNAL_SRC_MUTE;
+	}
+	if(src > SIGNAL_SRC_MAX)
+	{
+		src = SIGNAL_SRC_MAX;
+	}
+	change = set_channel_source(ak98pcm,addr,src);
+	return change;
+}
+
+static struct snd_kcontrol_new snd_ak98pcm_controls[] = {
+AK98PCM_VOLUME("Headphone Playback Volume", 0, MIXER_ADDR_HPVOL),
+AK98PCM_VOLUME("LineIn Capture Volume", 0, MIXER_ADDR_LINEINVOL),
+AK98PCM_VOLUME("Mic Capture Volume", 0, MIXER_ADDR_MICVOL),
+AK98PCM_ROUTE("Headphone Playback Route", 0, MIXER_ADDR_HPSRC),
+AK98PCM_ROUTE("LineOut Playback Route", 0, MIXER_ADDR_LINEOUTSRC),
+AK98PCM_ROUTE("ADC23 Capture Route", 0, MIXER_ADDR_ADC23SRC),
+AK98PCM_SWITCH("HPDet switch", 0, MIXER_ADDR_HPDET),
+AK98PCM_DAC_OUT_MODE("DAC out mode", 0, MIXER_ADDR_OUTMODE),
+AK98PCM_OUTPUTCHNL_DURATION("duration of output channel", 0, MIXER_ADDR_CHNLDURATION),
+};
+
+
+/**
+ * @brief  create new mixer interface
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int __devinit snd_card_ak98pcm_new_mixer(struct snd_ak98pcm *ak98pcm)
+{
+	struct snd_card *card = ak98pcm->card;
+	unsigned int idx;
+	struct snd_ctl_elem_id elem_id;
+	int err;
+
+	strcpy(card->mixername, "ak98pcm Mixer");
+
+	for (idx = 0; idx < ARRAY_SIZE(snd_ak98pcm_controls); idx++) {
+		err = snd_ctl_add(card, snd_ctl_new1(&snd_ak98pcm_controls[idx], ak98pcm));
+		if (err < 0)
+			return err;
+	}
+
+	/* attach master switch for HPDet switch control */	
+	memset(&elem_id, 0, sizeof(elem_id));
+	elem_id.iface = SNDRV_CTL_ELEM_IFACE_HWDEP;
+	strcpy(elem_id.name, "HPDet switch");
+	ak98pcm->ctl_switch = snd_ctl_find_id(card, &elem_id);
+
+	return 0;
+}
+
+/**************
+ * proc interface
+ **************/
+static void dac_mfix_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
+{
+	struct snd_ak98pcm *ak98pcm = entry->private_data;
+
+	snd_iprintf(buffer,"%d\n",ak98pcm->bIsMetalFixed);
+}
+
+static int __devinit snd_ak98pcm_probe(struct platform_device *devptr)
+{
+	struct snd_card *card;
+	struct snd_ak98pcm *ak98pcm;
+	struct resource *AnalogCtrlRegs;
+	struct resource *I2SCtrlRegs;
+	struct resource *ADC2ModeCfgRegs;
+	struct ak98pcm_platform_data *ak98pcm_plat_data;
+	int dev_id, err;
+
+	//get analog control registers
+	AnalogCtrlRegs = platform_get_resource_byname(devptr, IORESOURCE_MEM, "ak98pcm_AnalogCtrlRegs"); 
+	if(!AnalogCtrlRegs)
+	{
+		printk(KERN_ERR "no memory resource for AnalogCtrlRegs\n");
+		return -ENXIO;
+	}
+
+	//get I2S control registers
+	I2SCtrlRegs = platform_get_resource_byname(devptr, IORESOURCE_MEM, "ak98pcm_I2SCtrlRegs"); 
+	if(!I2SCtrlRegs)
+	{
+		printk(KERN_ERR "no memory resource for I2SCtrlRegs\n");
+		return -ENXIO;
+	}
+
+	//get ADC23 mode registers
+	ADC2ModeCfgRegs = platform_get_resource_byname(devptr, IORESOURCE_MEM, "ak98pcm_ADC2ModeCfgRegs");
+	if(!ADC2ModeCfgRegs)
+	{
+		printk(KERN_ERR "no memory resource for ADC2ModeCfgRegs\n");
+		return -ENXIO;
+	}
+
+	dev_id = devptr->id;
+	if (dev_id < 0)
+		dev_id = 0;
+	err = snd_card_create(dev_id, NULL, THIS_MODULE, sizeof(struct snd_ak98pcm), &card);
+	if (err < 0)
+		return err;
+
+	snd_card_set_dev(card, &devptr->dev);
+
+	ak98pcm = card->private_data;
+	ak98pcm->card = card;
+
+	ak98pcm->AnalogCtrlRegs = ioremap(AnalogCtrlRegs->start, AnalogCtrlRegs->end - AnalogCtrlRegs->start + 1);
+	if (!ak98pcm->AnalogCtrlRegs) {
+		printk(KERN_ERR "could not remap AnalogCtrlRegs memory");
+		goto __out_free_card;
+	}
+
+	ak98pcm->I2SCtrlRegs = ioremap(I2SCtrlRegs->start, I2SCtrlRegs->end - I2SCtrlRegs->start + 1);
+	if (!ak98pcm->I2SCtrlRegs) {
+		printk(KERN_ERR "could not remap I2SCtrlRegs memory");
+		goto __out_unmap_AnalogCtrlRegs;
+	}
+
+	ak98pcm->ADC2ModeCfgRegs = ioremap(ADC2ModeCfgRegs->start, ADC2ModeCfgRegs->end - ADC2ModeCfgRegs->start + 1);
+	if (!ak98pcm->ADC2ModeCfgRegs) {
+		printk(KERN_ERR "could not remap ADC2ModeCfgRegs memory");
+		goto __out_unmap_I2SCtrlRegs;
+	}
+
+	RegAddr.pAddress0800 = ak98pcm->AnalogCtrlRegs;
+	RegAddr.pAddress2002E = ak98pcm->I2SCtrlRegs;
+	RegAddr.pAddress2002D = ak98pcm->ADC2ModeCfgRegs;
+
+	//init l2 buf for audio
+	ak98pcm->L2BufID_For_DAC = BUF_NULL;
+	ak98pcm->L2BufID_For_ADC23 = BUF_NULL;
+
+	err = snd_card_ak98pcm_pcm(ak98pcm, 0, 1);
+	if (err < 0)
+		goto __out_unmap_ADC2ModeCfgRegs;
+	err = snd_card_ak98pcm_new_mixer(ak98pcm);
+	if(err < 0)
+		goto __out_unmap_ADC2ModeCfgRegs;
+
+	//init default volume
+	ak98pcm->mixer_volume[MIXER_ADDR_HPVOL] = DEFAULT_HPVOL;
+	AK98_Set_HPGain(DEFAULT_HPVOL);
+	ak98pcm->mixer_volume[MIXER_ADDR_LINEINVOL] = DEFAULT_LINEINVOL;
+	AK98_Set_LineinGain(DEFAULT_LINEINVOL);
+	ak98pcm->mixer_volume[MIXER_ADDR_MICVOL] = DEFAULT_MICVOL;
+	AK98_Set_MicGain(DEFAULT_MICVOL);
+	ak98pcm->mixer_source[MIXER_ADDR_HPSRC] = 0;
+	ak98pcm->mixer_source[MIXER_ADDR_LINEOUTSRC] = 0;
+	ak98pcm->mixer_source[MIXER_ADDR_ADC23SRC] = 0;
+	ak98pcm->mixer_OutMode[MIXER_ADDR_OUTMODE] = OUTMODE_AUTO;
+	ak98pcm->mixer_ChnlDuration[MIXER_ADDR_CHNLDURATION] = CHNLDURATION_CONSTANT;
+	
+#if defined CONFIG_SPKHP_SWITCH_AUTO || defined CONFIG_SPKHP_SWITCH_MIXER
+#ifdef CONFIG_SPKHP_SWITCH_AUTO
+	INIT_DELAYED_WORK(&ak98pcm->d_work, hpDet_wq_work);
+#endif
+	//config hp det gpio
+	ak98pcm_plat_data = (struct ak98pcm_platform_data *)devptr->dev.platform_data;
+	ak98pcm->hpdet_gpio = ak98pcm_plat_data->hpdet_gpio;
+	ak98_gpio_set(&(ak98pcm->hpdet_gpio));
+
+	//set hp det pin irq
+	ak98pcm->hp_det_irq = ak98pcm_plat_data->hpdet_irq;
+	ak98pcm->hp_on_value = ak98pcm_plat_data->hp_on_value;
+	if(AK98_GPIO_LOW == ak98pcm->hp_on_value)
+	{
+		ak98pcm->irqType_for_hpOn = IRQ_TYPE_LEVEL_LOW;
+		ak98pcm->irqType_for_hpOff = IRQ_TYPE_LEVEL_HIGH;
+	}
+	else if(AK98_GPIO_HIGH == ak98pcm->hp_on_value)
+	{
+		ak98pcm->irqType_for_hpOn = IRQ_TYPE_LEVEL_HIGH;
+		ak98pcm->irqType_for_hpOff = IRQ_TYPE_LEVEL_LOW;
+	}
+	if(ak98_gpio_getpin(ak98pcm->hpdet_gpio.pin) == ak98pcm->hp_on_value)
+	{
+		//hp is plugged in
+		ak98pcm->mixer_switch[MIXER_ADDR_HPDET] = 1;
+		set_irq_type(ak98pcm->hp_det_irq, ak98pcm->irqType_for_hpOff);
+		printk("--------------probe: hp on\n");
+	}
+	else
+	{
+		//hp is pulled out
+		ak98pcm->mixer_switch[MIXER_ADDR_HPDET] = 0;
+		set_irq_type(ak98pcm->hp_det_irq, ak98pcm->irqType_for_hpOn);
+		printk("--------------probe: hp off\n");
+	}
+	err = request_irq(ak98pcm->hp_det_irq, ak98pcm_HPDet_interrupt, IRQF_DISABLED, devptr->name, card);
+	if(err)
+	{
+		printk(KERN_ERR "request irq error!");
+		goto __out_unmap_ADC2ModeCfgRegs;
+	}
+#else
+    // will not detect headset pin in audio driver
+	memset(&(ak98pcm->hpdet_gpio),0,sizeof(struct gpio_info));
+#endif
+
+	//config speaker shutdown gpio
+	ak98pcm->spkrshdn_gpio = ak98pcm_plat_data->spk_down_gpio;
+	ak98_gpio_set(&(ak98pcm->spkrshdn_gpio));
+
+	//config hp mute gpio
+	ak98pcm->hpmute_gpio = ak98pcm_plat_data->hpmute_gpio;
+	ak98_gpio_set(&(ak98pcm->hpmute_gpio));
+	ak98pcm->hpmute_enable_value = ak98pcm_plat_data->hp_mute_enable_value;
+	if(AK98_GPIO_HIGH == ak98pcm->hpmute_enable_value)
+	{
+		ak98pcm->hpmute_disable_value = AK98_GPIO_LOW;
+	}
+	else if(AK98_GPIO_LOW == ak98pcm->hpmute_enable_value)
+	{
+		ak98pcm->hpmute_disable_value = AK98_GPIO_HIGH;
+	}
+
+	ak98pcm->bIsHPmuteUsed = ak98pcm_plat_data->bIsHPmuteUsed;
+	ak98pcm->bIsMetalFixed = ak98pcm_plat_data->bIsMetalfixed;
+
+	//init workqueue to stop output channel
+	INIT_WORK(&ak98pcm->stopoutput_work, stopOutput_work);
+
+	clear_bit(0,&ak98pcm->playbackStrmDMARunning);
+	clear_bit(1,&ak98pcm->playbackStrmDMARunning);
+	clear_bit(0,&ak98pcm->captureStrmDMARunning);
+	clear_bit(1,&ak98pcm->captureStrmDMARunning);
+
+	//timer for delay to stop output channel when playback is stopped
+	init_timer(&ak98pcm->timer);
+	ak98pcm->timer.function = ak98pcm_timer_func;
+	ak98pcm->timer.data = (unsigned long)ak98pcm;
+
+	// register a proc file to tell user whether the chip DAC module has been fixed
+	struct snd_info_entry *entry;
+	snd_card_proc_new (ak98pcm->card, "dac-metalfix", &entry);
+	snd_info_set_text_ops(entry, ak98pcm, dac_mfix_proc_read);
+	
+	strcpy(card->driver, "ak98pcm");
+	strcpy(card->shortname, "Ak98 AD/DA");
+	sprintf(card->longname, "Ak98 ADC DAC pcm input & output module %i", dev_id + 1);
+
+	err = snd_card_register(card);
+	if (err == 0) {
+		platform_set_drvdata(devptr, card);
+		return 0;
+	}
+
+	free_irq(ak98pcm->hp_det_irq, ak98pcm);
+	__out_unmap_ADC2ModeCfgRegs:
+	iounmap(ak98pcm->ADC2ModeCfgRegs);
+	__out_unmap_I2SCtrlRegs:
+	iounmap(ak98pcm->I2SCtrlRegs);	
+	__out_unmap_AnalogCtrlRegs:
+	iounmap(ak98pcm->AnalogCtrlRegs);	
+	__out_free_card:
+	snd_card_free(card);
+
+	return err;
+}
+
+static int __devexit snd_ak98pcm_remove(struct platform_device *devptr)
+{
+	struct snd_card *card = platform_get_drvdata(devptr);
+	struct snd_ak98pcm *ak98pcm = card->private_data;
+
+#ifdef CONFIG_SPKHP_SWITCH_AUTO
+	cancel_delayed_work_sync(&ak98pcm->d_work);
+#endif
+	del_timer(&ak98pcm->timer);
+	cancel_work_sync(&ak98pcm->stopoutput_work);
+	free_irq(ak98pcm->hp_det_irq, ak98pcm);
+	iounmap(ak98pcm->AnalogCtrlRegs);
+	iounmap(ak98pcm->I2SCtrlRegs);
+	iounmap(ak98pcm->ADC2ModeCfgRegs);
+	snd_card_set_dev(card, NULL);
+	snd_card_free(card);
+	platform_set_drvdata(devptr, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/**
+ * @brief  suspend callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98_suspend(struct platform_device *pdev, pm_message_t msg)
+{
+	struct snd_card *card = platform_get_drvdata(pdev);
+	struct snd_ak98pcm *ak98pcm = card->private_data;
+
+	if(test_bit(1,&ak98pcm->playbackStrmDMARunning))
+	{
+		wait_for_completion(&(ak98pcm->playbackHWDMA_completion));
+	}
+
+	if(test_bit(1,&ak98pcm->captureStrmDMARunning))
+	{
+		wait_for_completion(&(ak98pcm->captureHWDMA_completion));
+	}
+
+	//close analog module
+	AK98_DAC_Close();
+	ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_enable_value);
+	AK98_Poweron_HP(0);
+	ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_disable_value);
+	AK98_Set_HP_In(0);
+	AK98_Set_Bypass(0);
+	AK98_Poweron_Speaker(ak98pcm->spkrshdn_gpio.pin,0);
+
+	AK98_ADC23_Close();
+	AK98_Set_ADC23_In(0);
+
+	AK98_Poweron_VCM_REF(0);
+
+	return 0;
+}
+
+/**
+ * @brief  resume callback
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int snd_ak98_resume(struct platform_device *pdev)
+{
+	struct snd_card *card = platform_get_drvdata(pdev);
+	struct snd_ak98pcm *ak98pcm = card->private_data;
+	struct snd_pcm_substream *substream_playback = ak98pcm->playbacksubstrm;
+	struct snd_pcm_substream *substream_capture = ak98pcm->capturesubstrm;
+	struct snd_pcm_runtime *runtime_playback = NULL;
+	struct snd_pcm_runtime *runtime_capture = NULL;
+	dma_addr_t paddr_playback = 0;
+	dma_addr_t paddr_capture = 0;
+	u8 id_DAC = 0;
+	u8 id_ADC23 = 0;
+	int i=0;
+	
+	if(substream_playback!=NULL)
+	{
+		runtime_playback = substream_playback->runtime;
+		paddr_playback = runtime_playback->dma_addr;
+		id_DAC = ak98pcm->L2BufID_For_DAC;
+	}
+	if(substream_capture!=NULL)
+	{
+		runtime_capture = substream_capture->runtime;
+		paddr_capture = runtime_capture->dma_addr;
+		id_ADC23 = ak98pcm->L2BufID_For_ADC23;
+	}
+
+	for(i=MIXER_ADDR_HPSRC;i<=MIXER_ADDR_LASTSRC;i++)
+	{
+		if(ak98pcm->mixer_source[i])
+		{
+			if(ak98pcm->mixer_source[i]&SOURCE_DAC)//if playback stream is running when suspend
+			{
+				AK98_DAC_Open();
+				if((substream_playback!=NULL) &&
+					test_bit(0,&ak98pcm->playbackStrmDMARunning))
+				{
+					init_completion(&(ak98pcm->playbackHWDMA_completion));
+					ak98_l2_clr_status(id_DAC);
+					ak98_l2_combuf_dma(paddr_playback+ak98pcm->PlaybackCurrPos, id_DAC, ak98pcm_playback_period_bytes_min, 
+							   (ak98_l2_dma_transfer_direction_t)MEM2BUF,1);
+				}
+			}
+			if(ak98pcm->mixer_source[i]&SOURCE_LINEIN)  //linein input when suspend
+			{
+				AK98_Linein_PowerOn(1);
+			}
+			if(ak98pcm->mixer_source[i]&SOURCE_MIC)    //mic input(recording) when suspend
+			{
+				AK98_Mic_PowerOn(1);
+			}
+			AK98_Poweron_VCM_REF(1);
+			if(MIXER_ADDR_HPSRC == i)  //hp channel is opend when suspend
+			{
+				AK98_Set_HP_In(ak98pcm->mixer_source[i]);
+				ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_enable_value);
+				AK98_Poweron_HP(1);
+				ak98_gpio_setpin(ak98pcm->hpmute_gpio.pin, ak98pcm->hpmute_disable_value);
+			}
+			else if(MIXER_ADDR_LINEOUTSRC == i)  //lineout channel is opend when suspend
+			{
+				AK98_Set_Bypass(ak98pcm->mixer_source[i]);
+				AK98_Poweron_Speaker(ak98pcm->spkrshdn_gpio.pin,1);
+			}
+			else if(MIXER_ADDR_ADC23SRC == i)   //ADC23 is powed on when suspend
+			{
+				AK98_Set_ADC23_In(ak98pcm->mixer_source[i]);
+				AK98_ADC23_Open();
+				if((substream_capture!=NULL) &&
+					test_bit(0,&ak98pcm->captureStrmDMARunning))
+				{
+					init_completion(&(ak98pcm->captureHWDMA_completion));
+					ak98_l2_clr_status(id_ADC23);
+					ak98_l2_combuf_dma(paddr_capture+ak98pcm->CaptureCurrPos, id_ADC23, ak98pcm_capture_period_bytes_min, 
+							   (ak98_l2_dma_transfer_direction_t)BUF2MEM,1);
+				}
+			}
+		}
+	}
+	return 0;
+}
+#else
+#define snd_ak98_suspend NULL
+#define snd_ak98_resume NULL
+#endif
+
+
+#define SND_AK98PCM_DRIVER	"snd_ak98pcm"
+
+static struct platform_driver snd_ak98pcm_driver = {
+	.probe		= snd_ak98pcm_probe,
+	.remove		= __devexit_p(snd_ak98pcm_remove),
+	.suspend	= snd_ak98_suspend,
+	.resume		= snd_ak98_resume,
+	.driver		= {
+		.name	= SND_AK98PCM_DRIVER
+	},
+};
+
+/**
+ * @brief  register driver
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static int __init alsa_card_ak98pcm_init(void)
+{
+	int err;
+
+	err = platform_driver_register(&snd_ak98pcm_driver);
+	if (err < 0)
+		return err;
+	
+	return 0;
+}
+
+/**
+ * @brief  unregister driver
+ * @author  Cheng Mingjuan
+ * @date   
+ * @return void
+ */
+static void __exit alsa_card_ak98pcm_exit(void)
+{
+	platform_driver_unregister(&snd_ak98pcm_driver);
+}
+
+module_init(alsa_card_ak98pcm_init)
+module_exit(alsa_card_ak98pcm_exit)
diff --git a/sound/arm/dma.c b/sound/arm/dma.c
new file mode 100644
index 00000000000..17e209657ff
--- /dev/null
+++ b/sound/arm/dma.c
@@ -0,0 +1,474 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+//#include <asm/system.h>
+//#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/ak8801_addr.h>
+//#include <asm/io.h>
+
+#define dmawarn(fmt...) DBG(KERN_DEBUG fmt)
+
+#define BUF_MAGIC (0xcafebabe)
+
+#define AK7801_DMAF_AUTOSTART    (1<<1)
+
+int ak7801_dma_enqueue(unsigned int dma_id, void *runtime, dma_addr_t data, int size);
+
+static int irq_count = 0;
+static unsigned long tmp_pos = 0;
+
+static void __iomem *dma_base;
+static struct kmem_cache *dma_kmem;
+
+enum ak7801_dma_op {
+	AK7801_DMAOP_START,
+	AK7801_DMAOP_STOP,
+	AK7801_DMAOP_PAUSE,
+	AK7801_DMAOP_RESUME,
+	AK7801_DMAOP_FLUSH,
+	AK7801_DMAOP_TIMEOUT,
+	AK7801_DMAOP_STARTED,
+};
+
+enum ak7801_dma_dataresult { AK7801_RES_OK, AK7801_RES_ERR,
+	AK7801_RES_ABORT
+};
+
+
+struct ak7801_dma_client {
+	char	*name;
+};
+
+
+struct ak7801_dma_db {
+	struct ak7801_dma_db	*next;
+	int			magic;
+	int			size;
+	dma_addr_t		data;
+	dma_addr_t		start;
+	dma_addr_t		end;
+	dma_addr_t		ptr;
+	unsigned int		area;
+	int			run_state;
+	int			full_state;
+	void			*runtime;
+};
+
+static struct ak7801_dma_db db0;
+static struct ak7801_dma_db db1;
+static struct ak7801_dma_db * l2_db[] = {
+&db0, &db1
+};
+
+typedef void (*ak7801_dma_cbfn_t)(void *buf, int size, enum ak7801_dma_dataresult result);
+
+typedef int  (*ak7801_dma_opfn_t)(enum ak7801_dma_op );
+
+
+struct ak7801_dma_stats {
+	unsigned long		loads;
+	unsigned long		timeout_longest;
+	unsigned long		timeout_shortest;
+	unsigned long		timeout_avg;
+	unsigned long		timeout_failed;
+};
+
+enum ak7801_dma_state {
+	AK7801_DMA_IDLE, 
+	AK7801_DMA_RUNNING,
+	AK7801_DMA_PAUSED
+};
+
+
+enum ak7801_dma_loadst {
+	AK7801_DMALOAD_NONE,
+	AK7801_DMALOAD_1LOADED,
+	AK7801_DMALOAD_1RUNNING,
+	AK7801_DMALOAD_1LOADED_1RUNNING,
+};
+
+
+struct ak7801_dma_chan {
+	unsigned char		 dma_id; 
+	unsigned char		 in_use;
+	unsigned char		 irq_claimed;
+	unsigned char		 irq_enabled;
+	unsigned char		 xfer_unit;
+	enum ak7801_dma_state	 state;
+	enum ak7801_dma_loadst	 load_state;
+	struct ak7801_dma_client *client;
+	unsigned long		 dev_addr;
+	unsigned long		 load_timeout;
+	unsigned int		 flags;	
+	unsigned int		 hw_cfg;
+	void __iomem		*regs;	
+	void __iomem		*addr_reg;
+	unsigned int		 irq;
+	ak7801_dma_cbfn_t	 callback_fn;
+	ak7801_dma_opfn_t	 op_fn;	
+	struct ak7801_dma_stats *stats;
+	struct ak7801_dma_stats  stats_store;
+	struct ak7801_dma_db	*curr;
+	struct ak7801_dma_db	*next;
+	struct ak7801_dma_db	*end;
+	struct sys_device	dev;
+};
+
+
+
+static struct ak7801_dma_chan l2_dma_dac;
+static struct ak7801_dma_chan l2_dma_adc;
+static struct ak7801_dma_chan * l2_dma_chan[] = {
+	&l2_dma_dac, &l2_dma_adc,
+};
+
+
+int ak7801_dma_ctrl(struct ak7801_snd_runtime *or, enum ak7801_dma_op op);
+
+static void ak7801_dma_stats_timeout(struct ak7801_dma_stats *stats, int val)
+{
+	if (stats == NULL) return;
+	if (val > stats->timeout_longest)
+		stats->timeout_longest = val;
+	if (val < stats->timeout_shortest)
+		stats->timeout_shortest = val;
+	stats->timeout_avg += val;
+}
+
+
+static inline int ak7801_dma_loadbuffer(struct ak7801_dma_chan *dma_chan, struct ak7801_dma_db *db)
+{
+	if (db == NULL) {
+		DBG("buffer is NULL\n");
+		return -EINVAL;
+	}
+
+	if ((db->data & 0xf0000000) != 0x30000000)
+	{
+		DBG("dma load buf error\n");
+	}
+
+	l2_dma_config(db->data, db->size, dma_chan->dma_id);
+
+	return 0;
+}
+
+
+static inline void ak7801_dma_freebuf(struct ak7801_dma_db *db)
+{
+	int magicok = (db->magic == BUF_MAGIC);
+
+	db->magic = -1;
+
+	if (magicok) 
+	{
+		kmem_cache_free(dma_kmem, db);
+	}
+	else
+	{
+		DBG("ak7801_dma_freebuf: buff %p with bad magic\n", db);
+	}
+}
+
+
+static inline void ak7801_dma_bufdone(struct ak7801_dma_chan *dma_chan, struct ak7801_dma_db *db)
+{
+	if (dma_chan->callback_fn != NULL) 
+	{
+		(dma_chan->callback_fn)(dma_chan, db->runtime, db->size);
+	}
+	else
+	{
+		return IRQ_HANDLED;
+	}
+}
+
+
+
+static irq_handler_t  l2_dac_irq(void)
+{
+	is_mask_l2_int();
+	ak7801_dma_bufdone(&l2_dma_dac, &db0);
+	set_l2buf_ram_addr(l2_buf0, db0.data);
+	set_l2buf_dma_times(l2_buf0, db0.size >> 6);
+
+	if(stop_state == 1)
+	{
+		return IRQ_HANDLED;
+	} 
+	else
+	{
+		l2_dma_req(0);
+		is_unmask_l2_int();
+		return IRQ_HANDLED;
+	}
+}
+
+
+static irq_handler_t  l2_adc_irq(void)
+{
+	is_mask_l2_int();
+	ak7801_dma_bufdone(&l2_dma_adc, &db1);
+	set_l2buf_ram_addr(l2_buf1, db1.data);
+	set_l2buf_dma_times(l2_buf1, db1.size >> 6);
+
+	if(stop_state == 1)
+	{
+		return IRQ_HANDLED;
+	}
+	else
+	{
+		l2_dma_req(1);
+		is_unmask_l2_int();
+		return IRQ_HANDLED;
+	}
+}
+
+
+int ak7801_dma_request(unsigned int dma_id, struct ak7801_dma_client *client, void *dev)
+{
+	unsigned long flags;
+	int err;
+	struct ak7801_dma_chan *dma_chan = l2_dma_chan[dma_id];
+
+	dma_chan->client = client;
+	dma_chan->in_use = 1;
+
+	if (!dma_chan->irq_claimed) 
+	{
+		dma_chan->irq_claimed = 1;
+		if(dma_id == 0)
+		{
+			err = request_irq(dma_chan->irq, l2_dac_irq, IRQF_DISABLED, client->name, (void *)l2_dac_irq);
+			if (err) 
+			{
+				dma_chan->in_use = 0;
+				dma_chan->irq_claimed = 0;
+
+				DBG( "%s: cannot get IRQ %d for DMA %d\n",
+						client->name, dma_chan->irq, dma_chan->dma_id);
+				return err;
+			}
+			dma_chan->irq_enabled = 1;
+		}
+		else if(dma_id == 1)
+		{
+			err = request_irq(dma_chan->irq, l2_adc_irq, IRQF_DISABLED, client->name, (void *)l2_adc_irq);
+			if (err) 
+			{
+				dma_chan->in_use = 0;
+				dma_chan->irq_claimed = 0;
+
+				DBG( "%s: cannot get IRQ %d for DMA %d\n",
+						client->name, dma_chan->irq, dma_chan->dma_id);
+				return err;
+			}
+			dma_chan->irq_enabled = 1;
+		}
+		else
+		{
+			printk("l2 buf id is wrong !\n");
+		}
+	}
+
+	return 0;
+}
+
+EXPORT_SYMBOL(ak7801_dma_request);
+
+
+
+static void ak7801_dma_call_op(struct ak7801_dma_chan *dma_chan, enum ak7801_dma_op op)
+{
+	if (dma_chan->op_fn != NULL) 
+	{
+		(dma_chan->op_fn)(op);
+	}
+	else
+		DBG("%s: dma_chan->op_fn = NULL \n",__FUNCTION__);
+}
+
+
+int ak7801_dma_set_buffdone_fn(unsigned int dma_id, ak7801_dma_cbfn_t rtn)
+{
+	struct ak7801_dma_chan *dma_chan = l2_dma_chan[dma_id];
+	if(rtn == NULL)
+		DBG("%s:dma_chan->call_fn == NULL \n");
+	dma_chan->callback_fn = rtn;
+	return 0;
+}
+EXPORT_SYMBOL(ak7801_dma_set_buffdone_fn);
+
+
+static int ak7801_dma_dostop(struct ak7801_snd_runtime *or, struct ak7801_dma_chan *dma_chan)
+{
+	unsigned long flags;
+
+	is_mask_l2_int();
+
+	if(or->dma_id == 0)
+		disable_dac_config();
+	else
+		disable_adc_config();
+
+	return 0;
+}
+
+
+static int ak7801_dma_flush(struct ak7801_snd_runtime *or,  struct ak7801_dma_chan *dma_dac)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	ak7801_dma_freebuf(&db0);
+	ak7801_dma_freebuf(&db1);
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+
+static int ak7801_dma_preload (struct ak7801_snd_runtime *or) 
+{
+	int i;
+	int j;
+	dma_addr_t pos;
+
+	struct ak7801_dma_db *db = l2_db[or->dma_id];
+
+	db->next  = NULL;
+	db->data = or->dma_npos;
+	db->start = or->dma_start;
+	db->end = or->dma_end;
+	db->ptr = or->dma_npos;
+	db->area = or->dma_area;
+	db->size  = or->dma_period;
+	db->runtime  = or;
+	db->magic = BUF_MAGIC;
+	db->full_state = 1;
+
+	or->dma_cpos = or->dma_npos;
+	pos = or->dma_cpos + or->dma_period;
+	if (pos >= or->dma_end)
+		pos = or->dma_start;
+	or->dma_npos = pos;
+
+	return 0;
+}
+
+
+static int ak7801_dma_start(struct ak7801_snd_runtime *or,  struct ak7801_dma_chan *dma_chan)
+{
+	unsigned long tmp;
+	unsigned long flags;
+	int id = or->dma_id;
+	ak7801_dma_preload(or);
+	local_irq_save(flags);
+	l2_dma_config(l2_db[id]->data, l2_db[id]->size, id);
+	is_enable_dma(1);
+	l2_dma_req(id);
+	is_unmask_l2_int();
+	local_irq_restore(flags);
+
+	return 0;
+}
+
+
+int ak7801_dma_ctrl(struct ak7801_snd_runtime *or,  enum ak7801_dma_op op)
+{
+	struct ak7801_dma_chan *dma_chan = l2_dma_chan[or->dma_id];
+
+	switch (op)
+	{
+		case AK7801_DMAOP_START:
+			return ak7801_dma_start(or, dma_chan);
+
+		case AK7801_DMAOP_STOP:
+			return ak7801_dma_dostop(or, dma_chan);
+
+		case AK7801_DMAOP_FLUSH:
+			return ak7801_dma_flush(or, dma_chan);
+#if 0
+		case AK7801_DMAOP_PAUSE:
+		case AK7801_DMAOP_RESUME:
+			return -ENOENT;
+
+		case AK7801_DMAOP_FLUSH:
+			return ak7801_dma_flush(or, dma_dac);
+
+		case AK7801_DMAOP_STARTED:
+			return ak7801_dma_started(or, dma_dac);
+
+		case AK7801_DMAOP_TIMEOUT:
+			return 0;
+#endif
+	}
+
+	return -ENOENT; 
+}
+
+
+
+static int ak7801_dma_canload(struct ak7801_dma_chan *dma_chan)
+{
+	return 0;
+}
+
+
+
+static void ak7801_dma_cache_ctor(struct kmem_cache *c, void *p )
+{
+	memset(p, 0, sizeof(struct ak7801_dma_db));
+}
+
+
+static int __init ak7801_init_dma(void)
+{
+	struct ak7801_dma_chan *dma_dac = &l2_dma_dac;
+	struct ak7801_dma_chan *dma_adc = &l2_dma_adc;
+	int ret;
+
+	dma_kmem = kmem_cache_create("dma_desc", sizeof(struct ak7801_dma_db), 0,
+		SLAB_HWCACHE_ALIGN, ak7801_dma_cache_ctor);
+	if (dma_kmem == NULL) 
+	{
+		DBG( "dma failed to make kmem cache\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	memset(dma_dac, 0, sizeof(struct ak7801_dma_chan));
+	memset(dma_adc, 0, sizeof(struct ak7801_dma_chan));
+
+	dma_dac->irq = PLAY_IRQ;
+	dma_dac->dma_id = l2_buf0;
+	dma_dac->stats = &dma_dac->stats_store;
+	dma_dac->stats_store.timeout_shortest = LONG_MAX;
+	dma_dac->load_timeout = 1<<18;
+
+
+	dma_adc->irq = CAPTURE_IRQ;
+	dma_adc->dma_id = l2_buf1;
+	dma_adc->stats = &dma_dac->stats_store;
+	dma_adc->stats_store.timeout_shortest = LONG_MAX;
+	dma_adc->load_timeout = 1<<18;
+
+	audio_set_bit(rL2_FRACDMAADDR, 1<<29|1<<28, 0);
+	audio_set_bit(rL2_CONBUF0_7, 0xffff00ff, 0);
+
+	return 0;
+
+ err:
+	kmem_cache_destroy(dma_kmem);
+	return ret;
+}
+__initcall(ak7801_init_dma);