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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-08-22 21:28:01 +0300 |
|---|---|---|
| committer | Ryo Kataoka <ryo.kataoka.wt@renesas.com> | 2018-09-25 13:52:46 +0900 |
| commit | a259daf4b67ac3cee55ef4df7686128a108612f3 (patch) | |
| tree | 664b91d64eee76e8e743e7db57fd152193047402 | |
| parent | 65f0921ab7bc98b0b733902b2a2a5b8f31daa2b4 (diff) | |
| download | renesas-bsp-v4.14/rcar-3.7.2.rc3.tar.gz | |
mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITSrcar-3.7.2.rc3v4.14/rcar-3.7.2.rc3
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 9faf870e559a710c44e747ba20383ea82d8ac5d2)
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
| -rw-r--r-- | drivers/mmc/host/renesas_sdhi_internal_dmac.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 2f24a4890418b9..012f701ff50edd 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -45,7 +45,7 @@ /* DM_CM_RST */ #define RST_DTRANRST1 BIT(9) #define RST_DTRANRST0 BIT(8) -#define RST_RESERVED_BITS GENMASK_ULL(32, 0) +#define RST_RESERVED_BITS GENMASK_ULL(31, 0) /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ #define INFO1_CLEAR 0 |